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FAN5066

Ultra Low Voltage Synchronous DC-DC Controller

Description

Features

The FAN5066 is a synchronous mode DC-DC controller IC

which provides an adjustable output voltage for ultra-low

voltage applications, down to 400mV. The FAN5066 uses a

high level of integration to deliver load currents in excess of

19A from a 5V source with minimal external circuitry.

Synchronous-mode operation offers optimum efﬁciency over

the entire output voltage range, and the internal oscillator

can be programmed from 80KHz to 1MHz for additional

ﬂexibility in choosing external components. The FAN5066

also offers integrated functions including a four-bit

• Output adjustable from 400mV to 3.5V

• Synchronous Rectiﬁcation

• Adjustable operation from 80KHz to 1MHz

• Integrated Power Good and Enable functions

• Overvoltage protection

• Overcurrent protection

• Drives N-channel MOSFETs

• 20 pin SOIC or TSSOP package

Applications

• Power supply DDR SDRAM VTT

• Power Supply HSTL

DAC-controlled reference, Power Good, Output Enable,

over-voltage protection and current limiting.

• Power Supply for ASICs

• Adjustable ultra-low voltage step-down power supply

Block Diagram

+12V

+5V

FAN5066

5

4

–

+

1

OSC

13

12

–

+

+5V

7

–

DIGITAL

CONTROL

+

VO

–

+

9

16

CNTRL

20

1.24V

REFERENCE

4-BIT

DAC

VREF

3

POWER

GOOD

PWRGD

19 18 17

VID2

8

2

ENABLE

VID4

VID1

VID3

PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals

REV. 2.1.4 11/13/01

and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.

FAN5066

PRODUCT SPECIFICATION

Pin Assignments

CEXT

ENABLE

PWRGD

IFB

1

2

20

19

18

17

16

15

14

13

12

11

VREF

VID1

3

VID2

4

VID3

VFB

5

CNTRL

GNDA

GNDD

VCCQP

HIDRV

GNDP

FAN5066

VCCA

VCCP

VID4

6

7

8

LODRV

GNDP

9

10

Pin Deﬁnitions

Pin Number Pin Name Pin Function Description

1

CEXT

Oscillator Capacitor Connection. Connecting an external capacitor to this pin sets

the internal oscillator frequency. Layout of this pin is critical to system performance.

See Application Information for details.

2

3

4

ENABLE Output Enable. A logic LOW on this pin will disable the output. An internal pull-up

resistor allows for either open collector or TTL compatibility.

PWRGD Power Good Flag. An open collector output that will be at logic LOW if the output

voltage is not within ±12% of the nominal output voltage setpoint.

IFB

High Side Current Feedback. Pins 4 and 5 are used as the inputs for the current

feedback control loop. Layout of these traces is critical to system performance. See

Application Information for details.

5

VFB

Voltage Feedback. Pin 5 is used as the input for the voltage feedback control loop and

as the low side current feedback input. See Application Information for details regarding

correct layout.

6

7

8

VCCA

VCCP

VID4

Analog VCC. Connect to system 5V supply and decouple with a 0.1µF ceramic

capacitor.

Power VCC for low side FET driver. Connect to system 5V supply and place a 1µF

ceramic capacitor for decoupling and local charge storage.

VID4 Input. A logic 1 on this open collector/TTL input will enable the VID3–VID0 inputs

to set the output from 2.1V to 3.5V, and a logic 0 will set the output from 1.3V to 2.05V,

as shown in Table 1. Pullup resistors are internal to the controller.

9

10, 11

12

LODRV

GNDP

Low Side FET Driver. Connect this pin to the gate of an N-channel MOSFET for

synchronous operation. The trace from this pin to the MOSFET gate should be < 0.5".

Power Ground. Return pin for high currents flowing in pins 7 and 13 (VCCP and

VCCQP). Connect to a low impedance ground.

HIDRV

VCCQP

High Side FET Driver. Connect this pin to the gate of an N-channel MOSFET. The

trace from this pin to the MOSFET gate should be < 0.5".

13

Power VCC. For high side FET driver. VCCQP must be connected to a voltage of at

least VCCA + V

(MOSFET), and place a 1µF ceramic capacitor for decoupling

GS,ON

and local charge storage. See Application Information for details

14

15

GNDD

GNDA

CNTRL

Digital Ground. Return path for digital logic. Connect to a low impedance system

ground plane to minimize ground loops.

Analog Ground. Return path for low power analog circuitry. This pin should be

connected to a low impedance system ground plane to minimize ground loops.

16

Voltage Control. The voltage forced on this pin determines the output voltage of the

converter.

17-19

VID1-VID3 Voltage Identification Code Inputs. These open collector/TTL compatible inputs will

program the output voltage of the reference over the ranges specified in Table 1.

Pull-up resistors are internal to the controller.

20

VREF

Reference Voltage Test Point. This pin provides access to the DAC output and should

be decoupled to ground using 0.1µF capacitor.

2

REV. 2.1.4 11/13/01

PRODUCT SPECIFICATION

FAN5066

Absolute Maximum Ratings

Supply Voltages, VCCA, VCCP, VCCQP to GND

13V

18V

Supply Voltage VCCQP, Charge Pump (V +VCCA)

IN

Voltage Identification Code Inputs, VID3-VID0

VREF Output Current

13V

3mA

150°C

Junction Temperature, T

Storage Temperature

J

-65 to 150°C

300°C

Lead Soldering Temperature, 10 seconds

Operating Conditions

Parameter

Conditions

Min.

Typ.

Max.

Units

Supply Voltage, VCCA, VCCP

4.75

5

5.25

V

Input Logic HIGH

2.0

Input Logic LOW

0.8

70

12

V

Ambient Operating Temp

Output Driver Supply, VCCQP

0

°C

V

8.5

Electrical Speciﬁcations

(V

CCA

= 5V, V

= 900mV, f

= 300 KHz, and T = +25°C using circuit in Figure 1, unless otherwise noted)

osc A

CNTRL

The • denotes speciﬁcations which apply over the full operating temperature range.

Parameter

Conditions

Min.

Typ.

Max. Units

Initial Voltage Setpoint

I

= 0.8A, V

V

= 1.25V

= 900mV

1.237 1.250 1.263

V

mV

LOAD

CTRL

891

900

909

Output Temperature Drift

T = 0 to 70°C V

= 1.25V

= 900mV

•

+6

+4

mV

A

OUT

V

Load Regulation

I

= 0.8A to 3A

•

-20

±2

mV

mVpk

V

LOAD

Line Regulation

V

= 4.75V to 5.25V

IN

Output Ripple

20MHz BW, I

= 3A

±13

LOAD

DAC Output Voltage

DAC Accuracy

See Table 1

1.3

-3

3.4

+3

%

Short Circuit Detect Threshold

Output Driver Rise and Fall Time

Output Driver Deadtime 1

Output Driver Deadtime 2

Turn-on Response Time

Oscillator Range

•

90

120

80

5

150

mV

nsec

See Figure 3

%/f

OSC

80

nsec

I

= 0A to 3A

10

msec

KHz

LOAD

80

1000

330

Oscillator Frequency

PWRGD threshold

C

EXT

= 100 pF

270

300

Logic High

Logic Low

93

88

107 %V

112 %V

OUT

PWRGD Minimum Operating

Voltage

1.0

95

V

Max Duty Cycle

90

%

Control Pin Input Current

V

CTRL

= 400mV to 3.5V

•

235

µA

REV. 2.1.4 11/13/01

3

FAN5066

PRODUCT SPECIFICATION

Table 1. DAC Output Voltage Programming Codes

VID4

0

VID3

1

VID2

1

VID1

1

V

REF

1.30V

1.40V

1.50V

1.60V

1.70V

1.80V

1.90V

2.00V

No Output

2.2V

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2.4V

1

0

2.6V

1

0

1

2.8V

1

0

1

0

3.0V

1

0

1

3.2V

1

0

3.4V

Note:

1. 0 = processor pin is tied to GND.

1 = processor pin is open.

4

REV. 2.1.4 11/13/01

PRODUCT SPECIFICATION

FAN5066

Typical Operating Characteristics

(VCCA, VCCD = 5V, f

= 280 KHz, and T = +25°C using circuit in Figure 1, unless otherwise noted)

A

OSC

Load Regulation V

= 0.9V

Efficiency vs. Output Current

OUT

80

70

60

50

40

30

20

0.895

0.890

0.885

0.880

0.875

0.870

0

0.5

1

1.5

2

2.5

3

0.1 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7

3

Output Current (A)

Output Voltage vs. Output Current,

R_SENSE= 6mΩ

Oscillator Frequency vs. C_EXT

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

1250

1050

850

650

450

250

50

0

1

2

3

4

5

18

39

75

150

300

560

Output Current (A)

C_EXT(pf)

REV. 2.1.4 11/13/01

5

FAN5066

PRODUCT SPECIFICATION

Typical Operating Characteristics (continued)

Transient Response, 3A to 0.1A

Output Ripple, 900m @ 3A

Time (10µs/division)

Time (1µs/division)

Transient Response, 0.1A to 3A

Time (1µs/division)

Switching Waveforms, 3A Load

Output Startup, System Power-up

HIDRV

LODRV

Time (1µs/division)

Time (5ms/division)

65-5051-12

6

REV. 2.1.4 11/13/01

PRODUCT SPECIFICATION

FAN5066

Application Circuit

+12V

L1

+5V

2.2µH

C

D1

1N4735A

IN

C2

0.1µF

C1

0.1µF

R1

47Ω

330µF

C6

0.1µF

C5

1µF

+5V

FDS6984S

R2

Q1

Q2

R

L2

4.7µH

SENSE

R5

2KΩ

4.7Ω

C4

1µF

VO

11

10

9

8

7

6

5

4

3

2

1

25mΩ

R3

12

13

14

15

16

17

18

19

20

C

OUT

470µF

4.7Ω

R6

324Ω

U2

FAN4041

U1

FAN5066

R7

909Ω

C9

0.1µF

C

EXT

100pF

C3

0.1µF

VID4

VCC

ENABLE

C7

VID3

VID2

VID1

10KΩ

R4

C8

0.1µF

PWRGD

0.1µF

Figure 1. Application Circuit for 900mV @ 3A

REV. 2.1.4 11/13/01

7

FAN5066

PRODUCT SPECIFICATION

Table 2. FAN5066 Application Bill of Materials for 900mV @ 3A

Reference

Manufacturer Part #

Quantity Description

100nF, 50V Capacitor

Requirements/Comments

C1–3, C6–C9

Panasonic

7

2

1

ECU-V1H104ZFX

C4–5

Panasonic

ECU-V1C105ZFX

1µF, 16V Capacitor

100pF Capacitor

C

Panasonic

ECU-V1H101JCG

5%, C0G

ext

AVX

330µF, 10V Tantalum

470µF, 6.3V Tantalum

6.2V Zener Diode

I

= 1.3A

rms

IN

TPSE337*010R0100

AVX

ESR = 100mΩ

OUT

TPSE477*006R0100

D1

L1

L2

Q1

Motorola

1N4735A

Coiltronics

MP2-2R2

2.2µH, 1.4A Inductor

4.7µH, 5A inductor

DCR ~ 130mΩ

See Note 1.

Coiltronics

UP2B-4R7

DCR ~ 17mΩ

Fairchild

FDS6984S

N-Channel MOSFET with

Integrated Schottky

R1

Any

1

2

1

47Ω

R2-3

R4

4.7Ω

10KΩ

R5

2.0KΩ

324Ω

R6

R7

909Ω

R

25mΩ

SENSE

U1

Fairchild

DC/DC Controller

FAN5066M

U2

Fairchild

1

Shunt Regulator

FAN4041

Notes:

1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching. L1 may be

omitted if desired.

8

REV. 2.1.4 11/13/01

PRODUCT SPECIFICATION

FAN5066

Application Circuit

+12V

L1

+5V

1.5µH

D1

1N4735A

C2

0.1µF

C11

680µF

C1

0.1µF

R1

47Ω

C6

0.1µF

C5

1µF

R2

Q1

Q2

L2

4.7Ω

C4

1µF

VO

11

10

9

8

7

6

5

4

3

2

1

1.5µH

R3

VDDQ

12

13

14

15

16

17

18

19

20

C

*

OUT

4.7Ω

R5

499

U1

FAN5066

R6

499

C10

100pF

C9

0.1µF

VCC

ENABLE

C7

*Refer to Table 3 for value

of C

10KΩ

0.1µF

R4

C8

.

OUT

0.1µF

PWRGD

Figure 2. 12A Application Circuit for DDR VTT

REV. 2.1.4 11/13/01

9

FAN5066

PRODUCT SPECIFICATION

Table 3. FAN5066 Application Bill of Materials for DDR VTT

Reference

Manufacturer Part #

Quantity Description

Requirements/Comments

C1–2, C6–C9

Panasonic

ECU-V1H104ZFX

6

2

1

4

1

100nF, 50V Capacitor

C4–5

C10

Panasonic

ECU-V1C105ZFX

1µF, 16V Capacitor

100pF Capacitor

Panasonic

ECU-V1H101JCG

5%, C0G

C11

Sanyo

6SP680M

680µF, 6.3V OSCON

820µF, 4V OSCON

6.2V Zener Diode

I

= 4.8A

RMS

C

Sanyo

4SP820M

ESR < 12mΩ

OUT

D1

Motorola

1N4735A

L1

Coiltronics

UP1B-1R5

Optional 1.5µH, 4A Inductor

DCR ~ 20mΩ

See Note 1.

L2

Coiltronics

UP4B-1R5

1

2

1.5µH, 13A Inductor

DCR ~ 4mΩ

Q1–2

Fairchild

FDS6680S

N-Channel MOSFET

w/ Integrated Schottky

R

= 17mΩ @

DS(ON)

V = 4.5V

GS

R1

Any

1

2

1

2

1

47Ω

R2-3

R4

4.7Ω

10KΩ

R5-6

U1

499Ω

Fairchild

DC/DC Controller

FAN5066M

Notes:

1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching. L1 may be

omitted if desired.

Test Circuit

+12V

47Ω

1µF

t

F

R

VCCQP

HIDRV

90%

50%

90%

50%

4.7Ω

HIDRV

+5V

VCCA

VCCP

0.1µF

1µF

3000pF

10%

t

DT2

DT1

LODRV

50%

LODRV

GNDA GNDD GNDP

Figure 3. Output Drive Test Circuit and Timing Diagram

10

REV. 2.1.4 11/13/01

PRODUCT SPECIFICATION

FAN5066

VCCQP, which is supplied from an external 12V source

Application Information

through a series resistor or from a charge-pump circuit

powered from 5V if 12V is not available. The LODRV driver

has a power supply pin, VCCP, which can be supplied from

either the 12V or 5V source. The resulting voltages are sufﬁ-

cient to provide the gate to source drive to the external

The FAN5066 Controller

The FAN5066 is a programmable synchronous DC-DC con-

troller IC. When designed around the appropriate external

components, the FAN5066 can be conﬁgured to deliver more

than 19A of output current. The FAN5066 functions as a

ﬁxed frequency PWM step down regulator.

MOSFETs required in order to achieve a low R

.

DS,ON

Power Good (PWRGD)

The FAN5066 Power Good function is designed in accor-

dance with the Pentium II DC-DC converter speciﬁcations

and provides a continuous voltage monitor on the VFB pin.

The circuit compares the VFB signal to the VREF voltage

and outputs an active-low interrupt signal to the CPU should

the power supply voltage deviate more than ±12% of its

nominal setpoint. The Power Good ﬂag provides no other

control function to the FAN5066.

Main Control Loop

Refer to the FAN5066 Block Diagram on page 1. The

FAN5066 implements “summing mode control”, which is

different from both classical voltage-mode and current-mode

control. It provides superior performance to either by allow-

ing a large converter bandwidth over a wide range of output

loads.

The control loop of the regulator contains two main sections:

the analog control block and the digital control block. The

analog section consists of signal conditioning ampliﬁers

feeding into a set of comparators which provide the inputs to

the digital control block. The signal conditioning section

accepts inputs from the IFB (current feedback) and VFB

(voltage feedback) pins and sets up two controlling signal

paths. The ﬁrst, the voltage control path, ampliﬁes the differ-

ence between the VFB signal the reference voltage from the

DAC and presents the output to one of the summing ampli-

ﬁer inputs. The second, current control path, takes the differ-

ence between the IFB and VFB pins and presents the

resulting signal to another input of the summing ampliﬁer.

These two signals are then summed together with the slope

compensation input from the oscillator. This output is then

presented to a comparator, which provides the main PWM

control signal to the digital control block.

Output Enable (ENABLE)

The FAN5066 will accept an open collector/TTL signal for

controlling the output voltage. The low state disables the out-

put voltage. When disabled, the PWRGD output is in the low

state. If an enable is not required in the circuit, this pin may

be left open.

Over-Voltage Protection

The FAN5066 constantly monitors the output voltage for

protection against over voltage conditions. If the voltage at

the VFB pin exceeds 20% of the selected program voltage,

an over-voltage condition is assumed and the FAN5066 dis-

ables the output drive signal to the external MOSFETs. The

DC-DC converter returns to normal operation after the fault

has been removed.

Over-Current Protection

The digital control block takes the analog comparator inputs

and the main clock signal from the oscillator to provide the

appropriate pulses to the HIDRV and LODRV output pins.

These two outputs control the external power MOSFETs.

The digital block utilizes high speed Schottky transistor

logic, allowing the FAN5066 to operate at clock speeds as

high as 1MHz.

Current sense is implemented in the FAN5066 to reduce the

duty cycle of the output drive signal to the MOSFETs when

an over-current condition is detected. The voltage drop

created by the output current ﬂowing across a sense resistor

is presented to an internal comparator. When the voltage

developed across the sense resistor exceeds the 120mV com-

parator threshold voltage, the FAN5066 reduces the output

duty cycle to help protect the power devices. The DC-DC

converter returns to normal operation after the fault has been

removed.

There are additional comparators in the analog control sec-

tion whose function is to set the point at which the FAN5066

enters its pulse skipping mode during light loads, as well as

the point at which the current limit comparator disables the

output drive signals to the external power MOSFETs.

Oscillator

The FAN5066 oscillator section uses a ﬁxed current capaci-

tor charging conﬁguration. An external capacitor (CEXT) is

used to set the oscillator frequency between 80KHz and

1MHz. This scheme allows maximum ﬂexibility in choosing

external components.

High Current Output Drivers

The FAN5066 contains two identical high current output

drivers that utilize high speed bipolar transistors in a push-

pull conﬁguration. The drivers’ power and ground are sepa-

rated from the chip’s power and ground for switching noise

immunity. The HIDRV driver has a power supply pin,

REV. 2.1.4 11/13/01

11

FAN5066

PRODUCT SPECIFICATION

In general, a higher operating frequency decreases the peak

ripple current ﬂowing in the output inductor, thus allowing

the use of a smaller inductor value. In addition, operation at

higher frequencies decreases the amount of energy storage

that must be provided by the bulk output capacitors during

load transients due to faster loop response of the controller.

mately 4.5V. When the MOSFET Q1 turns on, the voltage at

the source of the MOSFET is equal to 5V. The capacitor

voltage follows, and hence provides a voltage at VCCQP

equal to almost 10V. The Schottky diode D1 is required to

provide the charge path when the MOSFET is off, and

reverses biases when VCCQP goes to 10V. The charge pump

capacitor (CP) needs to be a high Q, high frequency capaci-

tor. A 1µF ceramic capacitor is recommended here.

Unfortunately, the efﬁciency losses due to switching of the

MOSFETs increase as the operating frequency is increased.

Thus, efﬁciency is optimized at lower frequencies. An oper-

ating frequency of 300KHz is a typical choice which opti-

mizes efﬁciency and minimizes component size while

maintaining excellent regulation and transient performance

under all operating conditions.

+5V

D1

VCCQP

HIDRV

Q1

CP

Design Considerations and Component

Selection

L2 RS

VO

PWM/PFM

Control

Additional information on design and component selection

may be found in Fairchild Semiconductor’s Application

Note 53.

C_OUT

LODRV

GNDP

Q2

D2

MOSFET Selection

This application requires N-channel Logic Level Enhance-

ment Mode Field Effect Transistors. Desired characteristics

are as follows:

Figure 4. Charge Pump Configuration

Method 2. 12V Gate Bias

Figure 5 illustrates how a 12V source can be used to bias

VCCQP. A 47Ω resistor is used to limit the transient current

into the VCCQP pin and a 1µF capacitor is used to ﬁlter the

VCCQP supply. This method provides a higher gate bias

• Low Static Drain-Source On-Resistance,

R

< 20mΩ (lower is better)

DS,ON

• Low gate drive voltage, V = 4.5V rated

GS

• Power package with low Thermal Resistance

• Drain-Source voltage rating > 15V.

voltage (V ) to the high side MOSFET than the charge

GS

pump method, and therefore reduces the R

and the

DS,ON

The on-resistance (R ) is the primary parameter for

DS,ON

resulting power loss within the MOSFET. In designs where

efﬁciency is a primary concern, the 12V gate bias method is

recommended. A 6.2V Zener diode, D1, is used to clamp the

voltage at VCCQP to a maximum of 12V and ensure that the

absolute maximum voltage of the IC will not be exceeded.

MOSFET selection. The on-resistance determines the power

dissipation within the MOSFET and therefore signiﬁcantly

affects the efﬁciency of the DC-DC Converter. For details

and a spreadsheet on MOSFET selection, refer to Applica-

tions Bulletin AB-8

+5V

MOSFET Gate Bias

+12V

47Ω

D1

The high side MOSFET gate driver can be biased by one of

two methods–Charge Pump or 12V Gate Bias. The charge

pump method has the advantage of requiring only +5V as an

input voltage to the converter, but the 12V method will real-

ize increased efﬁciency by providing an increased V to the

GS

high side MOSFETs.

VCCQP

Q1

HIDRV

1µF

L2 RS

VO

PWM/PFM

Control

Method 1. Charge Pump (Bootstrap)

C_OUT

Figure 4 shows the use of a charge pump to provide gate bias

to the high side MOSFET when +12V is unavailable. Capac-

itor CP is the charge pump used to boost the voltage of the

FAN5066 output driver. When the MOSFET Q1 switches

off, the source of the MOSFET is at approximately 0V

because of the MOSFET Q2. (The Schottky D2 conducts for

only a very short time, and is not relevent to this discussion.)

CP is charged through the Schottky diode D1 to approxi-

LODRV

Q2

D2

GNDP

Figure 5. Gate Bias Configuration

12

REV. 2.1.4 11/13/01

PRODUCT SPECIFICATION

FAN5066

Inductor Selection

Output Voltage vs. Output Current

Choosing the value of the inductor is a tradeoff between

allowable ripple voltage and required transient response. The

system designer can choose any value within the allowed

minimum to maximum range in order to either minimize rip-

ple or maximize transient performance. The ﬁrst order equa-

tion (close approximation) for minimum inductance is:

RSENSE = 6mΩ

3.5

3.0

2.5

2.0

1.5

1.0

(V_in– V_out

)

V_out

ESR

------------------------------ ---------- -----------------

L_min

=

×

f

V_inV_ripple

0.5

0

where:

V

= Input Power Supply

in

0

5

10

15

20

25

V

out

= Output Voltage

Output Current (A)

f = DC/DC converter switching frequency

ESR = Equivalent series resistance of all output capacitors in

parallel

Figure 6. FAN5066 Short Circuit Characteristic

The output voltage does not return to its nominal value until

the output current is reduced to a value within the safe oper-

ating range for the DC-DC converter

V

= Maximum peak to peak output ripple voltage

ripple

budget.

The ﬁrst order equation for maximum allowed inductance is:

Schottky Selection

(V_in– V_out)D V_tb

------------------------------------^m------------

×

A schottky diode is not required in Figures 1 and 2, because

the low-side MOSFETs have built in schottkies using Fair-

child SyncFET technology. If some other type of MOSFET

is used, a schottky must be used in anti-parallel with the low-

side MOSFET. Selection of a schottky is determined by the

maximum output. In the converter of Figure 1, maximum

output current is 3A, and suppose the MOSFET has a body

L_max= 2C_O

I²_PP

where:

C

= The total output capacitance

o

I

= Maximum to minimum load transient current

= The output voltage tolerance budget allocated to load

pp

V

tb

transient

= Maximum duty cycle for the DC/DC converter

diode V = 0.75V at this current. The schottky must have at

f

D

m

least 100mV less V at the same current to ensure that the

f

(usually 95%).

body diode does not turn on. The MBRS130L diode has V =

f

0.45V typical at 3A at 25°C, and so is a suitable choice.

Some margin should be maintained away from both L

min

and L

. Adding margin by increasing L almost always

max

Output Filter Capacitors

adds expense since all the variables are predetermined by

The output bulk capacitors of a converter help determine its

output ripple voltage and its transient response. It has

already been seen in the section on selecting an inductor that

the ESR helps set the minimum inductance, and the capaci-

tance value helps set the maximum inductance. For most

converters, however, the number of capacitors required is

determined by the transient response and the output ripple

voltage, and these are determined by the ESR and not the

capacitance value. That is, in order to achieve the necessary

ESR to meet the transient and ripple requirements, the

capacitance value required is already very large.

system performance except for C , which must be increased

o

to increase L. Adding margin by decreasing L can either be

done by purchasing capacitors with lower ESR or by increas-

ing the DC/DC converter switching frequency. The

FAN5066 is capable of running at high switching frequen-

cies and provides signiﬁcant cost savings for the newer CPU

systems that typically run at high supply current.

FAN5066 Short Circuit Current Characteristics

The FAN5066 short circuit current characteristic includes a

hysteresis function that prevents the DC-DC converter from

oscillating in the event of a short circuit. Figure 6 shows the

typical characteristic of the DC-DC converter circuit with a

6.8 mΩ sense resistor. The converter exhibits a normal load

regulation characteristic until the voltage across the resistor

exceeds the internal short circuit threshold of 120mV

(= 17.5A * 6.8mΩ). At this point, the internal comparator

trips and signals the controller to reduce the converter’s

duty cycle to approximately 20%. This causes a drastic

reduction in the output voltage as the load regulation

collapses into the short circuit control mode. With a 40mΩ

output short,the voltage is reduced to 15A * 40mΩ = 600mV.

The most commonly used choice for output bulk capacitors

is aluminum electrolytics, because of their low cost and low

ESR. The only type of aluminum capacitor used should be

those that have an ESR rated at 100kHz. Consult Application

Bulletin AB-14 for detailed information on output capacitor

selection.

The output capacitance should also include a number of

small value ceramic capacitors placed as close as possible to

the processor; 0.1µF and 0.01µF are recommended values.

REV. 2.1.4 11/13/01

13

FAN5066

PRODUCT SPECIFICATION

Input Filter

PCB Layout Guidelines

The DC-DC converter design may include an input inductor

between the system +5V supply and the converter input as

shown in Figure 6. This inductor serves to isolate the +5V

supply from the noise in the switching portion of the DC-DC

converter, and to limit the inrush current into the input capac-

itors during power up. A value of 2.5µH is recommended.

• Placement of the MOSFETs relative to the FAN5066 is

critical. Place the MOSFETs such that the trace length of

the HIDRV and LODRV pins of the FAN5066 to the FET

gates is minimized. A long lead length on these pins will

cause high amounts of ringing due to the inductance of the

trace and the gate capacitance of the FET. This noise

radiates throughout the board, and, because it is switching

at such a high voltage and frequency, it is very difﬁcult to

suppress.

• In general, all of the noisy switching lines should be kept

away from the quiet analog section of the FAN5066. That

is, traces that connect to pins 9, 12, and 13 (LODRV,

HIDRV and VCCQP) should be kept far away from the

traces that connect to pins 1 through 5, and pin 16.

• Place the 0.1µF decoupling capacitors as close to the

FAN5066 pins as possible. Extra lead length on these

reduces their ability to suppress noise.

It is necessary to have some low ESR aluminum electrolytic

capacitors at the input to the converter. These capacitors

deliver current when the high side MOSFET switches on.

Figure 7 shows 3 x 1000µF, but the exact number required

will vary with the speed and type of the processor. For the

top speed Klamath and Deschutes, the capacitors should be

rated to take 7A of ripple current. Capacitor ripple current

rating is a function of temperature, and so the manufacturer

should be contacted to ﬁnd out the ripple current rating at the

expected operational temperature. For details on the design

of an input ﬁlter, refer to Applications Bulletin AB-15.

• Each VCC and GND pin should have its own via to the

appropriate plane. This helps provide isolation between

pins.

2.5µH

5V

Vin

• Surround the CEXT timing capacitor with a ground trace.

Be sure to place a ground or power plane underneath the

capacitor for further noise isolation, in order to provide

additional shielding to the oscillator (pin 1) from the noise

on the PCB. In addition, place this capacitor as close to

pin 1 as possible.

1000µF, 10V

Electrolytic

0.1µF

• Place the MOSFETs, inductor, and Schottky as close

together as possible for the same reasons as in the ﬁrst

bullet above. Place the input bulk capacitors as close to

the drains of the high side MOSFETs as possible. In

addition, placement of a 0.1µF decoupling cap right on

the drain of each high side MOSFET helps to suppress

some of the high frequency switching noise on the input

of the DC-DC converter.

Figure 7. Input Filter

Droop Resistor

Figure 8 shows a converter using a “droop resistor”, R . The

D

function of the droop resistor is to improve the transient

response of the converter, potentially reducing the number of

output capacitors required. In operation, the droop resistor

causes the output voltage to be slightly lower at heavy load

current than it otherwise would be. When the load transitions

from heavy to light current, the output can swing up farther

without exceeding limits, because it started from a lower

voltage, thus reducing the capacitor requirements.

• Place the output bulk capacitors as close to the CPU as

possible to optimize their ability to supply instantaneous

current to the load in the event of a current transient.

Additional space between the output capacitors and the

CPU will allow the parasitic resistance of the board traces

to degrade the DC-DC converter’s performance under

severe load transient conditions, causing higher voltage

deviation. For more detailed information regarding

capacitor placement, refer to Application Bulletin AB-5.

• The traces that run from the FAN5066 IFB (pin 4) and

VFB (pin 5) pins should be run together next to each other

and Kelvin connected to the sense resistor. Running these

lines together rejects some of the common mode noise

that is presented to the FAN5066 feedback input. Try, as

much as possible, to run the noisy switching signals

(HIDRV, LODRV & VCCQP) on one layer, but use the

inner layers for power and ground only. If the top layer is

being used to route all of the noisy switching signals, use

the bottom layer to route the analog sensing sign VFB and

IFB.

Q1

R_SENSE

R_DROOP

L2

VO

C_OUT

Q2

IFB

VFB

Figure 8. Use of a Droop Resistor

• A PC Board Layout Checklist is available from Fairchild

Applications. Ask for Application Bulletin AB-11.

14

REV. 2.1.4 11/13/01

PRODUCT SPECIFICATION

FAN5066

Additional Information

For additional information contact your local Fairchild

Semiconductor representative, or visit us on our website at

www.fairchildsemi.com.

REV. 2.1.4 11/13/01

15

FAN5066

PRODUCT SPECIFICATION

Mechanical Dimensions – 20 Lead SOIC

Notes:

Inches

Millimeters

Symbol

Notes

1. Dimensioning and tolerancing per ANSI Y14.5M-1982.

Min.

Max.

Min.

Max.

2. "D" and "E" do not include mold flash. Mold flash or

protrusions shall not exceed .010 inch (0.25mm).

A

.093

.004

.013

.009

.496

.291

.104

.012

.020

.013

.512

.299

2.35

0.10

0.33

0.23

12.60

7.40

2.65

0.30

0.51

0.32

13.00

7.60

A1

B

3. "L" is the length of terminal for soldering to a substrate.

4. Terminal numbers are shown for reference only.

5. "C" dimension does not include solder finish thickness.

6. Symbol "N" is the maximum number of terminals.

C

D

E

5

2

e

.050 BSC

1.27 BSC

H

h

.394

.010

.016

.419

.029

.050

10.00

0.25

0.40

10.65

0.75

1.27

L

3

6

N

α

20

0°

8°

0°

8°

ccc

—

.004

—

0.10

20

11

E

H

1

10

h x 45°

D

C

A1

A

α

SEATING

PLANE

– C –

e

B

L

LEAD COPLANARITY

ccc C

16

REV. 2.1.4 11/13/01

PRODUCT SPECIFICATION

FAN5066

Mechanical Dimensions – 20 Lead TSSOP

Notes:

Inches

Millimeters

Min. Max.

Symbol

Notes

1. Dimensioning and tolerancing per ANSI Y14.5M-1982.

Min.

Max.

2. "D" and "E" do not include mold flash. Mold flash or

protrusions shall not exceed .006 inch (0.15mm).

A

—

.047

.006

.012

.008

.260

.177

—

1.20

0.15

0.30

0.20

6.60

4.50

A1

B

.002

.007

.004

.252

.169

0.05

0.19

0.09

6.40

4.30

3. "L" is the length of terminal for soldering to a substrate.

4. Terminal numbers are shown for reference only.

5. Symbol "N" is the maximum number of terminals.

C

D

E

2

e

.026 BSC

.252 BSC

.018 .030

0.65 BSC

6.40 BSC

0.45 0.75

H

L

3

5

N

α

20

0°

8°

0°

8°

ccc

—

.004

—

0.10

D

E

H

C

A1

A

α

SEATING

PLANE

– C –

L

B

LEAD COPLANARITY

ccc C

e

REV. 2.1.4 11/13/01

17

FAN5066

PRODUCT SPECIFICATION

Ordering Information

Product Number

FAN5066M

Package

20 pin SOIC

20 pin TSSOP

FAN5066MTC

FAN5066MTCX

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY

PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY

LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER

DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES

OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR

CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, or (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

11/13/01 0.0m 001

Stock#DS30005066

2001 Fairchild Semiconductor Corporation


型号：	FAN5066M
厂家：	Rochester Electronics
描述：	Switching Controller, Current/voltage-mode, 1000kHz Switching Freq-Max, PDSO20, SOIC-20 开关光电二极管
文件：	总19页 (文件大小：921K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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