DS1330WP-150 [ROCHESTER]
32KX8 NON-VOLATILE SRAM MODULE, 150ns, DMA34, POWERCAP MODULE-34;
| 型号： | DS1330WP-150 |
| 厂家： | 
Rochester Electronics |
| 描述： | 32KX8 NON-VOLATILE SRAM MODULE, 150ns, DMA34, POWERCAP MODULE-34 静态存储器 内存集成电路 |
| 文件： | 总13页 (文件大小：912K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1330W
3.3V 256k Nonvolatile SRAM
www.maxim-ic.com
FEATURES
PIN ASSIGNMENT
Cꢀ10 years minimum data retention in the
absence of external power
CꢀData is automatically protected during power
loss
BW
NC
NC
NC
A14
A13
A12
A11
A10
A9
1
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2
NC
3
RST
VCC
4
CꢀPower supply monitor resets processor when
5
V
CC power loss occurs and holds processor in
WE
6
OE
7
reset during VCC ramp-up
CE
8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
A8
9
CꢀBattery monitor checks remaining capacity
daily
A7
10
11
12
13
14
15
16
17
A6
A5
CꢀRead and write access times as fast as 100 ns
CꢀUnlimited write cycle endurance
CꢀTypical standby current 50 µA
CꢀUpgrade for 32k x 8 SRAM, EEPROM or
Flash
A4
A3
A2
VBAT
GND
A1
A0
34-Pin PowerCap Module (PCM)
(Uses DS9034PC PowerCap)
CꢀLithium battery is electrically disconnected to
retain freshness until power is applied for the
first time
PIN DESCRIPTION
A0-A14
DQ0-DQ7
CE
WE
OE
RST
BW
- Address Inputs
CꢀOptional industrial temperature range of
-40°C to +85°C, designated IND
CꢀPowerCap Module (PCM) package
ꢀꢁDirectly surface-mountable module
ꢀꢁReplaceable snap-on PowerCap provides
lithium backup battery
- Data In/Data Out
- Chip Enable
- Write Enable
- Output Enable
- Reset Output
ꢀꢁStandardized pinout for all nonvolatile
SRAM products
ꢀꢁDetachment feature on PowerCap allows
easy removal using a regular screwdriver
- Battery Warning Output
- Power (+3.3V)
- Ground
VCC
GND
NC
- No Connect
DESCRIPTION
The DS1330W 3.3V 256k Nonvolatile SRAM is a 262,144-bit, fully static, nonvolatile SRAM organized
as 32,768 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control
circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs,
the lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. Additionally, the DS1330W has dedicated circuitry for monitoring the status of
VCC and the status of the internal lithium battery. DS1330W devices in the PowerCap Module package
are directly surface mountable and are normally paired with a DS9034PC PowerCap to form a complete
Nonvolatile SRAM module. The devices can be used in place of 32k x 8 SRAM, EEPROM or Flash
components.
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083106
DS1330W
READ MODE
The DS1330W executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 15 address inputs
(A0 - A14) defines which of the 32,768 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later-occurring signal (CE or OE ) and the limiting
parameter is either tCO for CE or tOE for OE rather than address access.
WRITE MODE
The DS1330W executes a write cycle whenever the WE and CE signals are in the active (low) state after
address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must
be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE active) then
WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The DS1330W provides full-functional capability for VCC greater than 3.0 volts and write protects by 2.8
volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile
static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically
write protect themselves, all inputs become “don’t care,” and all outputs become high impedance. As VCC
falls below approximately 2.5 volts, the power switching circuit connects the lithium energy source to
RAM to retain data. During power-up, when VCC rises above approximately 2.5 volts, the power
switching circuit connects external VCC to the RAM and disconnects the lithium energy source. Normal
RAM operation can resume after VCC exceeds 3.0 volts.
SYSTEM POWER MONITORING
The DS1330W has the ability to monitor the external VCC power supply. When an out-of-tolerance power
supply condition is detected, the NV SRAM warns a processor-based system of impending power failure
by asserting RST . On power-up, RST is held active for 200ms nominally to prevent system operation
during power-on transients and to allow tREC to elapse. RST has an open-drain output driver.
BATTERY MONITORING
The DS1330W automatically performs periodic battery voltage monitoring on a 24-hour time interval.
Such monitoring begins within tREC after VCC rises above VTP and is suspended when power failure
occurs.
After each 24-hour period has elapsed, the battery is connected to an internal 1MΩ test resistor for 1
second. During this 1 second, if battery voltage falls below the battery voltage trip point (2.6V), the
battery warning output BW is asserted. Once asserted, BW remains active until the module is replaced.
The battery is still re-tested after each VCC power-up, however, even if BW is active. If the battery
voltage is found to be higher than 2.6V during such testing, BW is de-asserted and regular 24-hour testing
resumes. BW has an open-drain output driver.
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DS1330W
FRESHNESS SEAL
Each DS1330W is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When VCC is first applied at a level greater than VTP, the lithium
energy source is enabled for battery backup operation.
PACKAGES
The 34-pin PowerCap Module integrates SRAM memory and nonvolatile control into a module base
along with contacts for connection to the lithium battery in the DS9034PC PowerCap. The PowerCap
Module package design allows a DS1330W device to be surface mounted without subjecting its lithium
backup battery to destructive high-temperature reflow soldering. After a DS1330W module base is reflow
soldered, a DS9034PC is snapped on top of the base to form a complete Nonvolatile SRAM module. The
DS9034PC is keyed to prevent improper attachment. DS1330W module bases and DS9034PC
PowerCaps are ordered separately and shipped in separate containers. See the DS9034PC data sheet for
further information.
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DS1330W
ABSOLUTE MAXIMUM RATINGS*
Voltage On Any Pin Relative To Ground
Operating Temperature
-0.3V to +4.6V
0°C to 70°C, -40°C to +85°C for IND parts
Storage Temperature
-40°C to +70°C, -40°C to +85°C for IND parts
See IPC/JEDEC J-STD-020
Soldering Temperature
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA: See Note 10)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Power Supply Voltage
Logic 1
Logic 0
VCC
VIH
VIL
3.0
2.2
0.0
3.3
3.6
VCC
0.4
V
V
V
DC ELECTRICAL CHARACTERISTICS
(TA: See Note 10) (VCC=3.3V ±0.3V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Input Leakage Current
IIL
-1.0
+1.0
µA
I/O Leakage Current CE O
VIH ? VCC
IIO
-1.0
+1.0
µA
Output Current @ 2.2V
Output Current @ 0.4V
Standby Current CE = 2.2V
IOH
IOL
ICCS1
-1.0
2.0
mA
mA
µA
14
14
50
30
250
150
Standby Current CE = VCC
-
ICCS2
µA
0.2V
Operating Current
ICCO1
VTP
50
3.0
mA
V
Write Protection Voltage
2.8
2.9
CAPACITANCE
PARAMETER
(TA= 25°C)
UNITS NOTES
SYMBOL
MIN
TYP
MAX
Input Capacitance
Input/Output Capacitance
CIN
CI/O
5
5
10
10
pF
pF
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DS1330W
AC ELECTRICAL CHARACTERISTICS
(TA: See Note 10) (VCC =3.3V ±0.3V)
DS1330W-100 DS1330W-150
PARAMETER
SYMBOL
UNITS NOTES
MIN
MAX MIN MAX
Read Cycle Time
tRC
tACC
tOE
tCO
tCOE
100
150
ns
ns
ns
ns
Access Time
100
50
100
150
70
150
OE to Output Valid
CE to Output Valid
OE or CE to Output Active
5
5
5
5
ns
5
5
Output High Z from
tOD
35
35
35
35
ns
Deselection
Output Hold from Address
Change
tOH
ns
Write Cycle Time
Write Pulse Width
Address Setup Time
tWC
tWP
tAW
tWR1
tWR2
tODW
tOEW
tDS
100
75
0
5
20
150
100
0
ns
ns
ns
3
12
13
5
5
4
5
Write Recovery Time
ns
20
ns
ns
ns
Output High Z from WE
Output Active from WE
Data Setup Time
5
40
0
5
60
tDH1
tDH2
12
13
0
Data Hold Time
ns
20
20
READ CYCLE
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DS1330W
WRITE CYCLE 1
WRITE CYCLE 2
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DS1330W
POWER-DOWN/POWER-UP CONDITION
BATTERY WARNING DETECTION
7 of 12
DS1330W
POWER-DOWN/POWER-UP TIMING
(TA: See Note 10)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
VCC Fail Detect to CE and
WE Inactive
VCC slew from VTP to 0V
VCC Fail Detect to
tPD
tF
1.5
µs
µs
µs
µs
ms
11
14
150
150
tRPD
tR
15
RST Active
VCC slew from 0V to VTP
VCC Valid to CE and
WE Inactive
tPU
2
VCC Valid to End of
Write Protection
tREC
125
ms
tRPU
tBPU
150
200
350
1
ms
s
14
14
VCC Valid to RST Inactive
VCC Valid to BW Valid
BATTERY WARNING TIMING
(TA: See Note 10)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Battery Test Cycle
Battery Test Pulse Width
Battery Test to BW Active
tBTC
tBTPW
tBW
24
hr
s
s
1
1
(TA= 25°C)
UNITS NOTES
PARAMETER
SYMBOL
MIN
TYP
MAX
Expected Data
Retention Time
tDR
10
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1. WE is high for a Read Cycle.
2. OE = VIH or VIL . If OE = VIH during write cycle, the output buffers remain in a high impedance state.
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. tDS is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output
buffers remain in a high impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in high-impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high-impedance state during this period.
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DS1330W
9. Each DS1330W has a built-in switch that disconnects the lithium source until VCC is first applied by
the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the
time power is first applied by the user.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.
11. In a power-down condition the voltage on any pin may not exceed the voltage on VCC.
12. tWR1 and tDH1 are measured from WE going high.
13. tWR2 and tDH2 are measured from CE going high.
14. RST and BW are open drains and cannot source current. External pullup resistors should be
connected to these pins for proper operation. Both pins will sink 10mA.
15. DS1330 modules are recognized by Underwriters Laboratory (U.L.®) under file E99151.
DC TEST CONDITIONS
Outputs Open
Cycle = 200 ns for operating current
All voltages are referenced to ground
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0 to 2.7V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
Supply
Part Number
Temperature Range
Pin/Package
Speed Grade
Tolerance
3.3V M 0.3V
3.3V M 0.3V
3.3V M 0.3V
3.3V M 0.3V
3.3V M 0.3V
3.3V M 0.3V
DS1330WP-100
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
34 / PowerCap*
34 / PowerCap*
34 / PowerCap*
34 / PowerCap*
34 / PowerCap*
34 / PowerCap*
100ns
100ns
100ns
100ns
150ns
150ns
DS1330WP-100+
DS1330WP-100IND
DS1330WP-100IND+
DS1330WP-150
DS1330WP-150+
+ Denotes lead-free/RoHS-compliant product.
* DS9034PC or DS9034PCI (PowerCap) required. Must be ordered separately.
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DS1330W
DS1330W NONVOLATILE SRAM, 34-PIN POWERCAP MODULE
PKG
DIM
INCHES
NOM
0.925
0.985
-
0.055
0.050
0.020
0.025
MIN
0.920
0.980
-
0.052
0.048
0.015
0.020
MAX
0.930
0.990
0.080
0.058
0.052
0.025
0.030
A
B
C
D
E
F
G
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DS1330W
DS1330W NONVOLATILE SRAM, 34-PIN POWERCAP MODULE WITH
POWERCAP
PKG
INCHES
NOM
0.925
0.960
0.245
0.055
0.050
0.020
0.025
DIM
MIN
0.920
0.955
0.240
0.052
0.048
0.015
0.020
MAX
0.930
0.965
0.250
0.058
0.052
0.025
0.030
A
B
C
D
E
F
G
ASSEMBLY AND USE
Reflow soldering
Dallas Semiconductor recommends that
PowerCap Module bases experience one pass
through solder reflow oriented label-side up
(live bug).
Hand soldering and touch-up
Do not touch soldering iron to leads for more
than 3 seconds. To solder, apply flux to the
pad, heat the lead frame pad and apply
solder. To remove part, apply flux, heat pad
until solder reflows, and use a solder wick.
LPM replacement in a socket
To replace a Low Profile Module in a 68-pin
PLCC socket, attach a DS9034PC PowerCap
to a module base then insert the complete
module into the socket one row of leads at a
time, pushing only on the corners of the cap.
Never apply force to the center of the device.
To remove from a socket, use a PLCC
extraction tool and ensure that it does not hit
or damage any of the module IC
components. Do not use any other tool for
extraction.
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DS1330W
RECOMMENDED POWERCAP MODULE LAND PATTERN
PKG
INCHES
NOM
1.050
DIM
A
MIN
MAX
-
-
-
-
-
-
-
-
-
-
B
0.826
C
0.050
D
0.030
E
0.112
RECOMMENDED POWERCAP MODULE SOLDER STENCIL
PKG
INCHES
NOM
1.050
DIM
A
MIN
MAX
-
-
-
-
-
-
-
-
-
-
B
0.890
C
0.050
D
0.030
E
0.080
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