DS1005M-250+ [ROCHESTER]
SILICON DELAY LINE, TRUE OUTPUT, PDIP8, 0.300 INCH, LOW PROFILE, DIP-8;
| 型号： | DS1005M-250+ |
| 厂家： | 
Rochester Electronics |
| 描述： | SILICON DELAY LINE, TRUE OUTPUT, PDIP8, 0.300 INCH, LOW PROFILE, DIP-8 光电二极管 输出元件 逻辑集成电路 延迟线 |
| 文件： | 总7页 (文件大小：744K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1005
5-Tap Silicon Delay Line
www.dalsemi.com
FEATURES
PIN ASSIGNMENT
ꢀ All-silicon time delay
IN
1
2
14
13
VCC
NC
IN
1
2
16
15
VCC
NC
ꢀ 5 taps equally spaced
ꢀ Delay tolerance ±2 ns or ±3%, whichever is
greater
ꢀ Stable and precise over temperature and
voltage range
ꢀ Leading and trailing edge accuracy
ꢀ Economical
ꢀ Auto-insertable, low profile
ꢀ Standard 14-pin DIP, 8-pin DIP, or 16-pin
SOIC
NC
NC
NC
TAP 2
NC
3
4
5
6
7
12
11
10
9
TAP 1
NC
NC
TAP 2
NC
3
4
5
6
7
8
14
13
12
11
10
9
NC
TAP 1
NC
TAP 3
NC
TAP 3
NC
TAP 4
GND
TAP 4
NC
8
TAP 5
GND
TAP 5
DS1005 14-Pin DIP (300-mil)
See Mech. Drawings Section
DS1005S 16-Pin SOIC
(300-mil)
See Mech. Drawings Section
ꢀ Tape and reel available for surface-mount
ꢀ Low-power CMOS
ꢀ TTL/CMOS compatible
ꢀ Vapor phase, IR and wave solderability
ꢀ Custom delays available
ꢀ Quick turn prototypes
1
VCC
8
IN
2
7
TAP 1
TAP 3
TAP 5
TAP 2
TAP 4
GND
3
4
6
5
ꢀ Extended temperature range available
DS1005M 8-Pin DIP (300-mil)
See Mech. Drawings Section
PIN DESCRIPTION
TAP 1-TAP 5 - TAP Output Number
VCC
GND
NC
- +5 Volts
- Ground
- No Connection
- Input
IN
DESCRIPTION
The DS1005 5-Tap Silicon Delay Line provides five equally spaced taps with delays ranging from 12 ns
to 250 ns, with an accuracy of ±2 ns or ±3%, whichever is greater. This device is offered in a standard 14-
pin DIP, making it compatible with existing delay line products. Space-saving 8-pin DIPs and 16-pin
SOICs are also available. Both enhanced performance and superior reliability over hybrid technology is
achieved by the combination of a 100% silicon delay line and industry standard DIP and SOIC
packaging. In order to maintain complete pin compatibility, DIP packages are available with hybrid lead
configurations. The DS1005 reproduces the input logic level at each tap after the fixed delay specified by
the dash number in Table 1. The device is designed with both leading and trailing edge accuracy. Each
tap is capable of driving up to ten 74LS loads. Dallas Semiconductor can customize standard products to
meet special needs. For special requests and rapid delivery, call (972) 371–4348.
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111799
DS1005
LOGIC DIAGRAM Figure 1
PART NUMBER DELAY TABLE (tPHL, tPLH) Table 1
PART NO.
DS1005-60
DS1005-75
DS1005-100
DS1005-125
DS1005-150
DS1005-175
DS1005-200
DS1005-250
TAP 1
12 ns
15 ns
20 ns
25 ns
30 ns
35 ns
40 ns
50 ns
TAP 2
24 ns
30 ns
40 ns
50 ns
60 ns
70 ns
80 ns
100 ns
TAP 3
36 ns
45 ns
60 ns
75 ns
TAP 4
48 ns
60 ns
TAP 5
60 ns
75 ns
100 ns
125 ns
150 ns
175 ns
200 ns
250 ns
80 ns
100 ns
120 ns
140 ns
160 ns
200 ns
90 ns
105 ns
120 ns
150 ns
Custom delays available
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DS1005
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
-1.0V to +7.0V
0°C to 70°C
Storage Temperature
Soldering Temperature
Short Circuit Output Current
-55°C to +125°C
260°C for 10 seconds
50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 5.0V ± 5%)
PARAMETER
SYM
TEST
MIN TYP
MAX
UNITS NOTES
CONDITION
Supply Voltage
High Level Input
Voltage
VCC
VIH
4.75
2.2
5.00
5.25
VCC + 0.5
V
V
1
1
Low Level Input
Voltage
Input Leakage
Current
VIL
II
-0.5
-1.0
0.8
1.0
70
V
1
u A
mA
mA
mA
0.0V ≤ VI ≤ VCC
Active Current
ICC
IOH
IOL
VCC=Max;
Period=Min.
VCC=Min.
VOH=4
VCC=Min.
VOL=0.5
40
2
High Level Output
Current
Low Level Output
Current
-1.0
12
AC ELECTRICAL CHARACTERISTICS
(TA = 25°C; VCC = 5V ± 5%)
PARAMETER
Input Pulse Width
Input to Tap Delay
(leading edge)
SYMBOL
tWI
MIN
TYP
MAX UNITS
NOTES
7
3, 4, 5, 6
40% of Tap 5 tPLH
ns
ns
tPLH
Table 1
Table 1
Input to Tap Delay
(trailing edge)
tPHL
ns
3, 4, 5, 6
Power-up Time
tPU
Period
100
ms
ns
4 (tWI)
7
CAPACITANCE
PARAMETER
Input Capacitance
(TA = 25°C)
MAX UNITS
10 pF
SYMBOL
MIN
TYP
5
NOTES
CIN
3 of 6
DS1005
NOTES:
1. All voltages are referenced to ground.
2. Measured with outputs open.
3. VCC = 5V @ 25°C. Delays accurate on both rising and falling edges within ±2 ns or ±3%, whichever
is greater.
4. See Test Conditions.
5. The combination of temperature variations from 25°C to 0°C or 25°C to 70°C and voltage variations
from 5.0V to 4.75V or 5.0V to 5.25V may produce an additional input-to-tap delay shift of ±1.5 ns or
±4%, whichever is greater.
6. All tap delays tend to vary unidirectionally with temperature or voltage. For example, if TAP 1 slows
down, all other taps will also slow down; TAP 3 can never be faster than TAP 2.
7. Pulse width and duty cycle specifications may be exceeded; however, accuracy will be application-
sensitive (decoupling, layout, etc.).
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
4 of 6
DS1005
TEST SETUP DESCRIPTION
Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1005.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected between the input and each tap. Each
tap is selected and connected to the counter by a VHF switch control unit. All measurements are fully
automated, with each instrument controlled by a central computer over an IEEE 488 bus.
TEST CONDITIONS
INPUT:
Ambient Temperature
Supply Voltage (VCC)
Input Pulse
25°C ±=3°C
5.0V ±=0.1V
High = 3.0V ±=0.1V
Low = 0.0V ±=0.1V
Source Impedance
Rise and Fall Time
Pulse Width
50 ohm maximum
3.0 ns maximum
500 ns
Period
1 µs
OUTPUT:
Each output is loaded with the equivalent of a 74F04 input gate. Delay is measured at the 1.5V level on
the rising and falling edge.
NOTE:
Above conditions are for test only and do not restrict the operation of the device under other data sheet
conditions.
5 of 6
DS1005
TIMING DIAGRAM: SILICON DELAY LINE Figure 2
DALLAS SEMICONDUCTOR TEST CIRCUIT Figure 3
6 of 6
相关型号：
DS1005S-100+
Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDSO16, 0.300 INCH, SOIC-16
MAXIM
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