CY7C1370DV25-167BZCT [ROCHESTER]
512KX36 ZBT SRAM, 3.4ns, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165;
| 型号： | CY7C1370DV25-167BZCT |
| 厂家： | 
Rochester Electronics |
| 描述： | 512KX36 ZBT SRAM, 3.4ns, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 静态存储器 内存集成电路 |
| 文件： | 总28页 (文件大小：1218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1370DV25
CY7C1372DV25
18-Mbit (512K x 36/1M x 18)
Pipelined SRAM with NoBL™ Architecture
Functional Description
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 MHz
The CY7C1370DV25 and CY7C1372DV25 are 2.5V, 512K x
36 and 1 Mbit x 18 Synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL™) logic, respectively. They are
designed to support unlimited true back-to-back Read/Write
operations with no wait states. The CY7C1370DV25 and
CY7C1372DV25 are equipped with the advanced (NoBL) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of data in systems that
require frequent Write/Read transitions. The CY7C1370DV25
and CY7C1372DV25 are pin-compatible and functionally
equivalent to ZBT devices.
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 2.5V core power supply (VDD
)
• 2.5V I/O power supply (VDDQ
• Fast clock-to-output times
)
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
— 2.6 ns (for 250-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in JEDEC-standard lead-free 100-Pin TQFP,
lead-free and non-lead-free 119-Ball BGA and 165-Ball
FBGA packages
Write operations are controlled by the Byte Write Selects
(BWa–BWd for CY7C1370DV25 and BWa–BWb for
CY7C1372DV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram-CY7C1370DV25 (512K x 36)
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
O
S
U
D
A
T
U
T
P
T
P
E
N
S
U
T
U
T
ADV/LD
A
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
R
E
G
I
MEMORY
ARRAY
B
U
F
S
T
E
E
R
I
DQs
DQP
DQP
DQP
DQP
WRITE
DRIVERS
BW
BW
a
a
b
c
d
A
M
P
b
BW
BW
c
S
T
E
R
S
F
d
E
R
S
S
WE
E
E
N
G
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
CONTROL
ZZ
Cypress Semiconductor Corporation
Document #: 38-05558 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 29, 2006
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CY7C1370DV25
CY7C1372DV25
Logic Block Diagram-CY7C1372DV25 (1M x 18)
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
U
T
P
O
U
T
S
E
N
S
P
U
T
D
A
T
U
T
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
A
R
E
G
I
MEMORY
ARRAY
E
B
U
F
DQs
DQP
DQP
WRITE
DRIVERS
BW
BW
a
S
T
E
E
R
I
A
M
P
a
F
b
S
T
E
R
S
b
E
R
S
S
N
G
WE
E
E
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
Sleep
Control
ZZ
Selection Guide
250 MHz
200 MHz
3.0
167 MHz
3.4
Unit
ns
Maximum Access Time
2.6
350
70
Maximum Operating Current
300
275
mA
mA
Maximum CMOS Standby Current
70
70
Document #: 38-05558 Rev. *D
Page 2 of 27
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CY7C1370DV25
CY7C1372DV25
Pin Configurations
100-Pin TQFP Pinout
DQPc
DQc
DQc
1
2
3
4
5
6
7
8
NC
NC
NC
DDQ
1
2
3
4
5
6
7
8
A
NC
NC
78
DQPb
DQb
DQb
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
80
79
V
V
DDQ
V
V
V
NC
DQPa
DQa
DQa
DDQ
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
SS
V
V
V
SS
SS
SS
DQc
DQc
NC
NC
DQb
DQb
DQb
DQb
DQb
DQc
DQc
9
DQb
9
V
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
V
V
DDQ
DDQ
V
V
DQa
DQa
V
NC
V
ZZ
DDQ
DDQ
DQc
DQc
NC
DQb
DQb
DQb
DQb
NC
V
SS
CY7C1370DV25
(512K × 36)
SS
V
V
DD
NC
DD
CY7C1372DV25
(1M × 18)
NC
NC
V
DD
DD
V
V
SS
SS
ZZ
DQa
DQa
DQd
DQb
DQa
DQa
DQd
DQb
DDQ
V
V
DDQ
V
V
V
DQa
DQa
NC
NC
V
V
DDQ
DDQ
V
V
SS
V
SS
SS
SS
DQd
DQd
DQd
DQd
DQa
DQa
DQb
DQb
DQa DQPb
DQa
NC
V
SS
V
V
SS
SS
SS
V
V
DDQ
DDQ
V
DDQ
DDQ
DQd
DQd
DQPd
NC
NC
NC
DQa
DQa
DQPa
NC
NC
NC
Document #: 38-05558 Rev. *D
Page 3 of 27
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CY7C1370DV25
CY7C1372DV25
Pin Configurations (continued)
119-Ball BGA
Pinout
CY7C1370DV25 (512K × 36)
1
2
3
4
5
6
7
VDDQ
A
A
A
A
A
VDDQ
A
NC/576M
NC/1G
DQc
CE2
A
A
A
ADV/LD
VDD
A
A
CE3
A
NC
NC
B
C
D
DQPc
VSS
NC
VSS
DQPb
DQb
DQc
VDDQ
DQc
DQc
DQc
DQc
DQc
VDD
VSS
VSS
CE1
VSS
VSS
DQb
DQb
DQb
DQb
VDD
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
E
F
OE
A
G
H
J
BWc
VSS
NC
BWb
VSS
NC
DQc
WE
VDD
VDDQ
DQd
DQd
VDDQ
DQd
DQd
DQd
DQd
DQd
DQd
DQPd
VSS
BWd
VSS
CLK
NC
VSS
BWa
VSS
VSS
VSS
DQa
DQa
DQa
DQa
DQPa
K
L
M
N
P
CEN
A1
VSS
VSS
MODE
A
A0
NC/144M
NC
A
VDD
A
A
NC/288M
ZZ
R
T
NC
A
NC/72M
TMS
NC/36M
NC
VDDQ
TDI
TCK
TDO
VDDQ
U
CY7C1372DV25 (1M x 18)
1
2
3
4
5
6
7
VDDQ
A
A
A
A
A
VDDQ
A
B
C
D
E
F
NC/576M
NC/1G
DQb
CE2
A
A
A
NC
NC
CE3
A
ADV/LD
VDD
A
A
NC
DQb
NC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQPa
NC
NC
NC
DQa
VDDQ
CE1
VDDQ
DQa
OE
A
NC
DQb
VDDQ
DQb
NC
VDD
NC
VSS
NC
NC
DQa
VDD
DQa
NC
VDDQ
G
H
J
BWb
VSS
NC
WE
VDD
NC
DQb
DQb
NC
VSS
NC
CLK
NC
VSS
NC
DQa
NC
DQa
NC
A
DQa
NC
K
L
BWa
VSS
VDDQ
DQb
DQb
NC
VSS
VSS
VSS
MODE
A
VDDQ
NC
M
N
P
R
T
CEN
A1
VSS
VSS
NC
A
NC
DQPb
A
A0
DQa
NC/144M
NC/72M
VDDQ
VDD
NC/36M
TCK
NC/288M
ZZ
A
A
TMS
TDI
TDO
NC
VDDQ
U
Document #: 38-05558 Rev. *D
Page 4 of 27
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CY7C1370DV25
CY7C1372DV25
Pin Configurations (continued)
165-Ball FBGA Pinout
CY7C1370DV25 (512K × 36)
1
2
A
3
4
5
6
7
8
9
A
10
A
11
NC
NC/576M
NC/1G
DQPc
ADV/LD
A
B
C
D
CE1
BWc
BWd
VSS
VDD
BWb
BWa
VSS
VSS
CE3
CLK
VSS
VSS
CEN
WE
A
CE2
VDDQ
VDDQ
OE
VSS
VDD
A
A
NC
NC
DQc
VSS
VSS
VDDQ
VDDQ
NC
DQb
DQPb
DQb
DQc
DQc
DQc
DQc
NC
DQc
DQc
DQc
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQb
DQb
DQb
NC
DQb
DQb
DQb
ZZ
E
F
G
H
J
DQd
DQd
DQd
DQd
DQd
DQd
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQa
DQa
DQa
DQa
DQa
DQa
K
L
DQd
DQd
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQa
NC
A
DQa
DQPa
M
N
P
DQPd
NC/144M NC/72M
MODE NC/36M
TDI
TDO
NC/288M
A
A
TMS
A0
TCK
A
A
A
A
R
CY7C1372DV25 (1M × 18)
1
NC/576M
NC/1G
NC
2
A
3
4
5
NC
6
CE3
7
8
9
A
10
A
11
A
A
B
C
D
CE1
BWb
NC
CEN
ADV/LD
A
CE2
VDDQ
VDDQ
BWa
VSS
VSS
CLK
VSS
VSS
A
A
NC
WE
VSS
VSS
OE
VSS
VDD
NC
DQb
VSS
VDD
VDDQ
VDDQ
NC
NC
DQPa
DQa
NC
NC
NC
DQb
DQb
DQb
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQa
DQa
DQa
ZZ
E
F
NC
NC
G
H
J
NC
NC
DQb
DQb
DQb
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQa
DQa
DQa
NC
NC
NC
K
L
NC
NC
DQb
NC
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQa
NC
A
NC
NC
M
N
P
DQPb
NC/144M NC/72M
MODE NC/36M
TDI
TDO
NC/288M
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05558 Rev. *D
Page 5 of 27
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CY7C1370DV25
CY7C1372DV25
Pin Definitions
Pin Name
I/O Type
Pin Description
Address Inputs used to select one of the address locations. Sampled at the rising edge of
A0
Input-
A1
A
Synchronous the CLK.
BWa
BWb
BWc
BWd
Input-
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Synchronous Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb,
BWc controls DQc and DQPc, BWd controls DQd and DQPd.
WE
Input-
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
Synchronous signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input- Advance/Load Input used to advance the on-chip address counter or load a new address.
Synchronous When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
CLK
CE1
CE2
CE3
OE
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE2 and CE3 to select/deselect the device.
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
Synchronous with CE1 and CE3 to select/deselect the device.
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE2 to select/deselect the device.
Input-
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
Asynchronous control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked
during the data portion of a write sequence, during the first clock when emerging from a
deselected state and when the device has been deselected.
CEN
DQS
Input-
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
Synchronous SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQa–DQd are placed in a three-state condition. The outputs are
automatically three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless of the state of
OE.
DQPX
MODE
TDO
TDI
I/O-
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQs. During write
Synchronous sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc,
and DQPd is controlled by BWd.
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
output
Synchronous
JTAG serial Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
input
Synchronous
TMS
TCK
Test Mode This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Select
Synchronous
JTAG-Clock Clock input to the JTAG circuitry.
Document #: 38-05558 Rev. *D
Page 6 of 27
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CY7C1370DV25
CY7C1372DV25
Pin Definitions (continued)
Pin Name
VDD
I/O Type
Pin Description
Power Supply Power supply inputs to the core of the device.
VDDQ
I/O Power Power supply for the I/O circuitry.
Supply
VSS
NC
Ground
Ground for the device. Should be connected to ground of the system.
–
–
No connects. This pin is not connected to the die.
NC/(36M,72M,
144M, 288M,
576M, 1G)
These pins are not connected. They will be used for expansion to the 36M, 72M, 144M, 288M,
576M, and 1G densities.
ZZ
Input-
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
Asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
of the chip enable signals, its output will three-state following
the next clock rise.
Introduction
Functional Overview
The CY7C1370DV25
and
CY7C1372DV25
are
synchronous-pipelined Burst NoBL SRAMs designed specifi-
cally to eliminate wait states during Write/Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(tCO) is 2.6 ns (250-MHz device).
Burst Read Accesses
The CY7C1370DV25 and CY7C1372DV25 have an on-chip
burst counter that allows the user the ability to supply a single
address and conduct up to four Reads without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
a new address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap around when incremented suffi-
ciently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BWX can be used to
conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented is loaded into the
Address Register. The write signals are latched into the
Control Logic block.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 and DQa,b/DQPa,b
for CY7C1372DV25). In addition, the address for the subse-
quent access (Read/Write/Deselect) is latched into the
Address Register (provided the appropriate control signals are
asserted).
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 2.6 ns
(250-MHz device) provided OE is active LOW. After the first
clock of the read access the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 & DQa,b/DQPa,b for
CY7C1372DV25) (or a subset for byte write operations, see
Write Cycle Description table for details) inputs is latched into
the device and the write is complete.
The data written during the write operation is controlled by BW
(BWa,b,c,d for CY7C1370DV25 and BWa,b for CY7C1372DV25)
Document #: 38-05558 Rev. *D
Page 7 of 27
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CY7C1370DV25
CY7C1372DV25
signals. The CY7C1370DV25/CY7C1372DV25 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the Write Enable input (WE) with the selected
Byte Write Select (BW) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
will remain unaltered.
A synchronous self-timed write
mechanism has been provided to simplify the write operations.
Byte write capability has been included in order to greatly
simplify Read/Modify/Write sequences, which can be reduced
to simple byte write operations.
Because the CY7C1370DV25 and CY7C1372DV25 are
common I/O devices, data should not be driven into the device
while the outputs are active. The Output Enable (OE) can be
deasserted HIGH before presenting data to the DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 and DQa,b/DQPa,b
for CY7C1372DV25) inputs. Doing so will three-state the
output drivers. As a safety precaution, DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 and DQa,b/DQPa,b
for CY7C1372DV25) are automatically three-stated during the
data portion of a write cycle, regardless of the state of OE.
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
00
A1,A0
01
A1,A0
10
A1,A0
11
01
00
11
10
10
11
00
01
Burst Write Accesses
11
10
01
00
The CY7C1370DV25/CY7C1372DV25 has an on-chip burst
counter that allows the user the ability to supply a single
address and conduct up to four WRITE operations without
reasserting the address inputs. ADV/LD must be driven LOW
in order to load the initial address, as described in the Single
Write Access section above. When ADV/LD is driven HIGH on
the subsequent clock rise, the chip enables (CE1, CE2, and
CE3) and WE inputs are ignored and the burst counter is incre-
mented. The correct BW (BWa,b,c,d for CY7C1370DV25 and
BWa,b for CY7C1372DV25) inputs must be driven in each
cycle of the burst write in order to write the correct bytes of
data.
Linear Burst Address Table (MODE = GND)
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
00
A1,A0
01
A1,A0
10
A1,A0
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
ZZ > VDD − 0.2V
Min.
Max.
Unit
mA
ns
80
tZZS
ZZ > VDD − 0.2V
2tCYC
tZZREC
tZZI
ZZ < 0.2V
2tCYC
0
ns
ZZ active to sleep current
ZZ Inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2tCYC
ns
tRZZI
ns
Document #: 38-05558 Rev. *D
Page 8 of 27
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CY7C1370DV25
CY7C1372DV25
Truth Table[1, 2, 3, 4, 5, 6, 7]
Address
Used
Operation
Deselect Cycle
CE
H
X
L
ZZ
L
ADV/LD WE BWx
OE
CEN CLK
L-H
DQ
Tri-state
Tri-state
Data Out (Q)
Data Out (Q)
Tri-state
Tri-state
Data In (D)
Data In (D)
Tri-state
Tri-state
–
None
L
H
L
X
X
H
X
H
X
L
X
X
X
X
X
X
L
X
L
L
L
L
L
L
L
L
L
L
Continue Deselect Cycle
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
NOP/Write Abort (Begin Burst)
Write Abort (Continue Burst)
Ignore Clock Edge (Stall)
Sleep Mode
None
L
X
L
L-H
External
Next
L
L-H
X
L
L
H
L
L
L-H
External
Next
L
H
H
X
X
X
X
X
X
L-H
X
L
L
H
L
L-H
External
Next
L
L-H
X
L
L
H
L
X
L
L
L-H
None
L
H
H
X
X
L-H
Next
X
X
X
L
H
X
X
X
X
X
L-H
Current
None
L
H
X
L-H
X
H
Tri-state
Partial Write Cycle Description[1, 2, 3, 8]
Function (CY7C1370DV25)
Read
WE
BWd
X
H
H
H
H
H
H
H
H
L
BWc
X
H
H
H
H
L
BWb
X
H
H
L
BWa
X
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Write – No bytes written
Write Byte a – (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Bytes b, a
H
L
L
Write Byte c – (DQc and DQPc)
Write Bytes c, a
H
H
L
H
L
L
Write Bytes c, b
L
H
L
Write Bytes c, b, a
L
L
Write Byte d – (DQd and DQPd)
Write Bytes d, a
H
H
H
H
L
H
H
L
H
L
L
Write Bytes d, b
L
H
L
Write Bytes d, b, a
L
L
Write Bytes d, c
L
H
H
L
H
L
Write Bytes d, c, a
L
L
Write Bytes d, c, b
L
L
H
L
Write All Bytes
L
L
L
Notes:
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BW = Valid
x
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BW . See Write Cycle Description table for details.
X
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQ and DQP = Three-state when
s
X
OE is inactive or when the device is deselected, and DQ = data when OE is active.
s
8. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid. Appropriate write will be done based on which byte write is active.
X
Document #: 38-05558 Rev. *D
Page 9 of 27
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CY7C1370DV25
CY7C1372DV25
Function (CY7C1372DV25)
WE
H
L
BWb
BWa
x
Read
x
H
H
L
Write – No Bytes Written
Write Byte a – (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Both Bytes
H
L
L
L
H
L
L
L
Test Mode Select (TMS)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
The CY7C1370DV25/CY7C1372DV25 incorporates a serial
boundary scan test access port (TAP).This part is fully
compliant with 1149.1. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic levels.
Test Data-In (TDI)
The CY7C1370DV25/CY7C1372DV25 contains
a
TAP
controller, instruction register, boundary scan register, bypass
register, and ID register.
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
(See Tap Controller Block Diagram.)
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
TAP Controller Block Diagram
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
Bypass Register
0
0
2
1
0
0
0
SHIFT-DR
0
SHIFT-IR
0
Selection
Circuitry
Instruction Register
31 30 29
Identification Register
Selection
TDI
TDO
1
1
Circuitr
y
1
1
.
.
. 2 1
EXIT1-DR
EXIT1-IR
0
0
x
.
.
.
.
. 2 1
PAUSE-DR
0
PAUSE-IR
0
1
1
Boundary Scan Register
0
0
EXIT2-DR
1
EXIT2-IR
1
TCK
TMS
UPDATE-DR
UPDATE-IR
TAP CONTROLLER
1
0
1
0
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
Document #: 38-05558 Rev. *D
Page 10 of 27
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CY7C1370DV25
CY7C1372DV25
TAP Registers
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
Bypass Register
SAMPLE Z
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
Boundary Scan Register
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the in-
struction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is cap-
tured in the boundary scan register.
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possi-
ble that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.
Identification (ID) Register
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the bound-
ary scan register between the TDI and TDO pins.
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells pri-
or to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
Document #: 38-05558 Rev. *D
Page 11 of 27
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CY7C1370DV25
CY7C1372DV25
BYPASS
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR,” the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
preset HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #85
(for 119-BGA package) or bit #89 (for 165-fBGA package).
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
TH
CYC
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
Document #: 38-05558 Rev. *D
Page 12 of 27
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CY7C1370DV25
CY7C1372DV25
TAP AC Switching Characteristics Over the Operating Range[9, 10]
Parameter
Clock
tTCYC
tTF
Description
Min.
Max.
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
20
tTH
20
20
tTL
ns
Output Times
tTDOV TCK Clock LOW to TDO Valid
tTDOX TCK Clock LOW to TDO Invalid
Set-up Times
tTMSS TMS Set-up to TCK Clock Rise
tTDIS
10
ns
ns
0
5
5
5
ns
ns
ns
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
tCH
Capture Hold after Clock Rise
Notes:
9. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
10. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.
R
F
Document #: 38-05558 Rev. *D
Page 13 of 27
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CY7C1370DV25
CY7C1372DV25
2.5V TAP AC Test Conditions
2.5V TAP AC Output Load Equivalent
1.25V
Input pulse levels ................................................ VSS to 2.5V
Input rise and fall time..................................................... 1 ns
Input timing reference levels.........................................1.25V
Output reference levels.................................................1.25V
Test load termination supply voltage.............................1.25V
50Ω
TDO
ZO= 50Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted)[11]
Parameter
VOH1
Description
Test Conditions
Min.
Max.
Unit
V
Output HIGH Voltage IOH = –1.0 mA, VDDQ = 2.5V
Output HIGH Voltage IOH = –100 µA, VDDQ = 2.5V
Output LOW Voltage IOL = 8.0 mA, VDDQ = 2.5V
2.0
2.1
VOH2
VOL1
VOL2
VIH
V
0.4
0.2
V
Output LOW Voltage IOL = 100 µA
Input HIGH Voltage
VDDQ = 2.5V
V
VDDQ = 2.5V
VDDQ = 2.5V
1.7
–0.3
–5
VDD + 0.3
0.7
V
VIL
Input LOW Voltage
V
IX
Input Load Current
GND < VIN < VDDQ
5
µA
Scan Register Sizes
Bit Size (x18)
Register Name
Bit Size (x36)
Instruction
3
3
Bypass
1
1
ID
32
85
89
32
85
89
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball fBGA package)
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1)
CY7C1372DV25
CY7C1370DV25
Description
Reserved for version number.
000
000
01011001000100101
00000110100
01011001000010101 Reserved for future use.
00000110100
Allows unique identification of
SRAM vendor.
ID Register Presence (0)
1
1
Indicate the presence of an ID
register.
Note:
11.All voltages referenced to V (GND).
SS
Document #: 38-05558 Rev. *D
Page 14 of 27
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CY7C1370DV25
CY7C1372DV25
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
119-Ball BGA Boundary Scan Order [12, 13]
Bit #
1
Ball ID
Bit #
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Ball ID
F6
Bit #
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Ball ID
G4
A4
G3
C3
B2
B3
A3
C2
A2
B1
C1
D2
E1
F2
Bit #
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
Ball ID
L1
H4
T4
T5
T6
R5
L5
2
E7
D7
H7
G6
E6
D6
C7
B7
C6
A6
C5
B5
G5
B6
D4
B4
F4
M2
N1
3
4
P1
5
K1
6
L2
7
R6
U6
R7
T7
P6
N7
M6
L7
N2
P2
8
9
R3
10
11
12
13
14
15
16
17
18
19
20
21
22
T1
R1
T2
L3
R2
K6
P7
N6
L6
G1
H2
D1
E2
G2
H1
J3
T3
L4
N4
P4
K7
J5
M4
A5
K4
E4
Internal
H6
G7
2K
Notes:
12. Balls which are NC (No Connect) are pre-set LOW.
13. Bit# 85 is pre-set HIGH.
Document #: 38-05558 Rev. *D
Page 15 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
165-Ball FBGA Boundary Scan Order [12, 14]
Bit #
1
Ball ID
N6
Bit #
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Ball ID
D10
C11
A11
B11
A10
B10
A9
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
G1
D2
E2
2
N7
3
N10
P11
P8
4
F2
5
G2
H1
H3
J1
6
R8
7
R9
8
P9
B9
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
C10
A8
K1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
L1
B8
M1
J2
A7
B7
K2
B6
L2
A6
M2
N1
N2
P1
B5
A5
A4
B4
R1
R2
P3
B3
A3
A2
R3
P2
H10
G11
F11
E11
D11
G10
F10
E10
B2
C2
R4
P4
B1
A1
N5
P6
C1
D1
R6
Internal
E1
F1
Note:
14. Bit# 89 is pre-set HIGH.
Document #: 38-05558 Rev. *D
Page 16 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V
Supply Voltage on VDDQ Relative to GND ......–0.5V to +VDD
DC to Outputs in Tri-State................... –0.5V to VDDQ + 0.5V
Ambient
VDD/VDDQ
Range
Commercial
Industrial
Temperature
0°C to +70°C
2.5V ±5%
–40°C to +85°C
Electrical Characteristics Over the Operating Range[15, 16]
Parameter
VDD
Description
Test Conditions
Min.
2.375
2.375
2.0
Max.
2.625
VDD
Unit
V
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[17] for 2.5V I/O
Input LOW Voltage[17] for 2.5V I/O
VDDQ
VOH
VOL
VIH
VIL
for 2.5V I/O
V
for 2.5V I/O, IOH = −1.0 mA
V
for 2.5V I/O, IOL= 1.0 mA
0.4
V
1.7
–0.3
–5
VDD + 0.3V
V
0.7
5
V
IX
Input Leakage Current GND ≤ VI ≤ VDDQ
except ZZ and MODE
µA
Input Current of MODE Input = VSS
Input = VDD
–30
–5
µA
µA
5
Input Current of ZZ
Input = VSS
Input = VDD
µA
30
5
µA
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled
–5
µA
VDD Operating Supply VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
350
300
275
160
150
140
70
mA
mA
mA
mA
mA
mA
mA
ISB1
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz
VIN ≥ VIH or VIN ≤ VIL, f = fMAX =
1/tCYC
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
ISB2
Automatic CE
Power-down
Current—CMOS Inputs f = 0
Max. VDD, Device Deselected, All speed grades
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
ISB3
Automatic CE
Power-down
Current—CMOS Inputs f = fMAX = 1/tCYC
Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz
135
130
125
80
mA
mA
mA
mA
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
ISB4
Automatic CE
Max. VDD, Device Deselected, All speed grades
Power-down
Current—TTL Inputs
VIN ≥ VIH or VIN ≤ VIL, f = 0
Notes:
15. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC)> –2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
.
16. T
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
Power-up
DD
IH
DD
DDQ DD
17. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05558 Rev. *D
Page 17 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
Capacitance[17]
100 TQFP
Package
119 BGA
Package
165 FBGA
Parameter
Description
Test Conditions
Package
Unit
pF
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
DD = 2.5V.
VDDQ = 2.5V
5
5
5
8
8
8
9
9
9
V
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
pF
pF
Thermal Resistance[17]
100 TQFP
Package
119 BGA
Package
165 FBGA
Package
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard
test methods and procedures
for measuring thermal
28.66
23.8
20.7
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
4.08
6.2
4.0
°C/W
impedance, per EIA/JESD51.
AC Test Loads and Waveforms
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
R = 1538Ω
≤ 1 ns
≤ 1 ns
V = 1.25V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Document #: 38-05558 Rev. *D
Page 18 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
[22, 23]
Switching Characteristics Over the Operating Range
–250
–200
–167
Parameter
Description
Min. Max. Min.
Max. Min. Max.
Unit
[18]
tPower
VCC (typical) to the first access read or write
1
1
5
1
ms
Clock
tCYC
Clock Cycle Time
Maximum Operating Frequency
Clock HIGH
4.0
6
ns
MHz
ns
FMAX
tCH
250
200
167
1.7
1.7
2.0
2.0
2.2
2.2
tCL
Clock LOW
ns
Output Times
tCO
Data Output Valid After CLK Rise
OE LOW to Output Valid
2.6
2.6
3.0
3.0
3.4
3.4
ns
ns
ns
ns
ns
ns
ns
tEOV
tDOH
Data Output Hold After CLK Rise
Clock to High-Z[19, 20, 21]
Clock to Low-Z[19, 20, 21]
OE HIGH to Output High-Z[19, 20, 21]
OE LOW to Output Low-Z[19, 20, 21]
1.0
1.0
0
1.3
1.3
0
1.3
1.3
0
tCHZ
2.6
2.6
3.0
3.0
3.4
3.4
tCLZ
tEOHZ
tEOLZ
Set-up Times
tAS
Address Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
CEN Set-up Before CLK Rise
WE, BWx Set-up Before CLK Rise
ADV/LD Set-up Before CLK Rise
Chip Select Set-up
1.2
1.2
1.2
1.2
1.2
1.2
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
tDS
tCENS
tWES
tALS
tCES
Hold Times
tAH
Address Hold After CLK Rise
Data Input Hold After CLK Rise
CEN Hold After CLK Rise
0.3
0.3
0.3
0.3
0.3
0.3
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tDH
tCENH
tWEH
WE, BWx Hold After CLK Rise
ADV/LD Hold after CLK Rise
Chip Select Hold After CLK Rise
tALH
tCEH
Notes:
18. This part has a voltage regulator internally; t
is the time power needs to be supplied above V minimum initially, before a Read or Write operation can
DD
Power
be initiated.
19. t
, t
, t
, and t
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
EOHZ
CHZ CLZ EOLZ
20. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
EOHZ
EOLZ
CHZ
CLZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
22. Timing reference 1.25V when V
= 2.5V.
DDQ
23. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05558 Rev. *D
Page 19 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
Switching Waveforms
Read/Write/Timing[24, 25, 26]
1
2
3
4
5
6
7
8
9
10
t
CYC
t
CLK
t
t
t
CENS CENH
CL
CH
CEN
t
t
CES
CEH
CE
ADV/LD
WE
BW
x
A1
A2
A4
CO
A3
A5
A6
A7
ADDRESS
t
t
t
t
DS
DH
t
t
t
DOH
OEV
CLZ
CHZ
t
t
AS
AH
Data
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
In-Out (DQ)
t
OEHZ
t
DOH
t
OELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Notes:
24. For this waveform ZZ is tied LOW.
25. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
26. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 38-05558 Rev. *D
Page 20 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
Switching Waveforms (continued)
NOP,STALL and DESELECT Cycles[24, 25, 27]
1
2
3
4
5
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
A1
A2
A3
A4
A5
ADDRESS
t
CHZ
D(A4)
D(A1)
Q(A2)
Q(A3)
Q(A5)
Data
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
ZZ Mode Timing[28, 29]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
27. The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle
28. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
29. I/Os are in High-Z when exiting ZZ sleep mode.
Document #: 38-05558 Rev. *D
Page 21 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Part and Package Type
167
CY7C1370DV25-167AXC
CY7C1372DV25-167AXC
CY7C1370DV25-167BGC
CY7C1372DV25-167BGC
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1370DV25-167BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1372DV25-167BGXC
CY7C1370DV25-167BZC
CY7C1372DV25-167BZC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1370DV25-167BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Lead-Free
CY7C1372DV25-167BZXC
CY7C1370DV25-167AXI
CY7C1372DV25-167AXI
CY7C1370DV25-167BGI
CY7C1372DV25-167BGI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Industrial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1370DV25-167BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1372DV25-167BGXI
CY7C1370DV25-167BZI
CY7C1372DV25-167BZI
CY7C1370DV25-167BZXI
CY7C1372DV25-167BZXI
CY7C1370DV25-200AXC
CY7C1372DV25-200AXC
CY7C1370DV25-200BGC
CY7C1372DV25-200BGC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Lead-Free
200
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1370DV25-200BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1372DV25-200BGXC
CY7C1370DV25-200BZC
CY7C1372DV25-200BZC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1370DV25-200BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Lead-Free
CY7C1372DV25-200BZXC
CY7C1370DV25-200AXI
CY7C1372DV25-200AXI
CY7C1370DV25-200BGI
CY7C1372DV25-200BGI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Industrial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1370DV25-200BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1372DV25-200BGXI
CY7C1370DV25-200BZI
CY7C1372DV25-200BZI
CY7C1370DV25-200BZXI
CY7C1372DV25-200BZXI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Lead-Free
Document #: 38-05558 Rev. *D
Page 22 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
250
CY7C1370DV25-250AXC
CY7C1372DV25-250AXC
CY7C1370DV25-250BGC
CY7C1372DV25-250BGC
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1370DV25-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1372DV25-250BGXC
CY7C1370DV25-250BZC
CY7C1372DV25-250BZC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1370DV25-250BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Lead-Free
CY7C1372DV25-250BZXC
CY7C1370DV25-250AXI
CY7C1372DV25-250AXI
CY7C1370DV25-250BGI
CY7C1372DV25-250BGI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Industrial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1370DV25-250BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1372DV25-250BGXI
CY7C1370DV25-250BZI
CY7C1372DV25-250BZI
CY7C1370DV25-250BZXI
CY7C1372DV25-250BZXI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Lead-Free
Document #: 38-05558 Rev. *D
Page 23 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)
16.00 0.20
14.00 0.10
1.40 0.05
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
1. JEDEC STD REF MS-026
0.25
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
A
Document #: 38-05558 Rev. *D
Page 24 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
Package Diagrams (continued)
119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)
51-85115-*B
Document #: 38-05558 Rev. *D
Page 25 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)
BOTTOM VIEW
PIN 1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
PIN 1 CORNER
-0.06
Ø0.50 (165X)
+0.14
1
2
3
4
5
6
7
8
9
10
11
11 10
9
8
7
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
A
1.00
5.00
10.00
B
13.00 0.10
B
13.00 0.10
0.15(4X)
NOTES :
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
SEATING PLANE
C
51-85180-*A
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05558 Rev. *D
Page 26 of 27
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback
CY7C1370DV25
CY7C1372DV25
Document History Page
Document Title: CY7C1370DV25/CY7C1372DV25 18-Mbit (512K x 36/1M x 18)
Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05558
Orig. of
REV.
**
ECN No. Issue Date Change
Description of Change
254509
288531
See ECN
See ECN
RKF
SYT
New data sheet
*A
Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for
non-compliance with 1149.1
Removed 225 Mhz Speed Bin
Added lead-free information for 100-Pin TQFP, 119 BGA and 165 FBGA
package
Added comment of ‘Lead-free BG packages availability’ below the Ordering
Information
*B
326078
See ECN
PCI
Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard
Added description on EXTEST Output Bus Tri-State
Changed description on the Tap Instruction Set Overview and Extest
Changed ΘJA and ΘJC for TQFP Package from 31 and 6 °C/W to 28.66 and
4.08 °C/W respectively
Changed ΘJA and ΘJC for BGA Package from 45 and 7 °C/W to 23.8 and 6.2
°C/W respectively
Changed ΘJA and ΘJC for FBGA Package from 46 and 3 °C/W to 20.7 and
4.0 °C/W respectively
Modified VOL, VOH test conditions
Removed comment of ‘Lead-free BG packages availability’ below the
Ordering Information
Updated Ordering Information Table
*C
418125
See ECN
NXR
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed the description of IX from Input Load Current to Input Leakage
Current on page# 18
Changed the IX current values of MODE on page # 18 from –5 µA and 30 µA
to –30 µA and 5 µA
Changed the IX current values of ZZ on page # 18 from –30 µA and 5 µA
to –5 µA and 30 µA
Changed VIH < VDD to VIH < VDDon page # 18
Updated Ordering Information Table
*D
475677
See ECN
VKN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP
AC Switching Characteristics table.
Updated the Ordering Information table.
Document #: 38-05558 Rev. *D
Page 27 of 27
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