CY7C1338B-100AC [ROCHESTER]
128KX32 CACHE SRAM, 8ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100;
| 型号： | CY7C1338B-100AC |
| 厂家： | 
Rochester Electronics |
| 描述： | 128KX32 CACHE SRAM, 8ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总19页 (文件大小：1051K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
338B
CY7C1338B
128K x 32 Synchronous-Flow-Through 3.3V Cache RAM
Features
Functional Description
• Supports117-MHzmicroprocessorcachesystemswith
The CY7C1338B is a 3.3V, 128K by 32 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap-
tures the first address in a burst and increments the address
automatically for the rest of the burst access.
zero wait states
• 128K by 32 common I/O
• Fast clock-to-output times
— 7.5 ns (117-MHz version)
• Two-bit wraparound counter supporting either inter-
leaved or linear burst sequence
• Separate processor and controller address strobes
providedirectinterfacewiththeprocessorandexternal
cache controller
• Synchronous self-timed write
• Asynchronous output enable
• 3.3V/ 2.5V I/Os
• JEDEC-standard pinout
• 100-pin TQFP packaging
• ZZ “sleep” mode
The CY7C1338B allows both interleaved and linear burst se-
quences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address
Strobe (ADSC) inputs. Address advancement is controlled by
the Address Advancement (ADV) input.
A synchronous self-timed write mechanism is provided to sim-
plify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.
• Available in Commercial and Industrial Temperatures
Logic Block Diagram
MODE
2
(A ,A )
0
1
Q
Q
CLK
ADV
ADSC
0
BURST
COUNTER
CE
CLR
1
ADSP
Q
15
17
ADDRESS
REGISTER
CE
D
128K X 32
MEMORY
ARRAY
A
[16:0]
17
15
GW
Q
Q
Q
Q
DQ[31:24]
D
BYTEWRITE
REGISTERS
BWE
BW
3
D
D
D
DQ[23:16]
BYTEWRITE
REGISTERS
BW
2
DQ[15:8]
BYTEWRITE
REGISTERS
BW
1
DQ[7:0]
BW
BYTEWRITE
REGISTERS
0
32
32
CE
1
CE
2
D
CE
ENABLE
REGISTER
CLK
Q
CE
3
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ
[31:0]
Selection Guide
-117
7.5
-100
Maximum Access Time (ns)
8.0
325
2.0
Maximum Operating Current (mA)
Maximum Standby Current (mA)
350
2.0
Cypress Semiconductor Corporation
Document #: 38-05143 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised January 18, 2003
CY7C1338B
Pin Configurations
100-Pin TQFP
NC
NC
DQ
DQ
V
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ
DQ
16
17
15
14
V
V
DDQ
DDQ
SSQ
SSQ
V
DQ
DQ
DQ
DQ
18
19
DQ
DQ
DQ
DQ
V
13
12
11
10
BYTE2
BYTE1
20
21
9
V
V
SSQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SSQ
DDQ
DDQ
V
DQ
DQ
22
23
DQ
DQ
V
9
8
NC
SS
V
DD
NC
CY7C1338B
NC
V
DD
V
SS
ZZ
DQ
DQ
V
DQ
DQ
24
25
7
6
V
V
DDQ
DDQ
SSQ
SSQ
V
DQ
DQ
DQ
DQ
26
27
DQ
DQ
DQ
DQ
V
5
4
3
2
BYTE3
BYTE0
28
29
V
V
SSQ
SSQ
DDQ
DDQ
V
DQ
DQ
30
31
DQ
DQ
NC
1
0
NC
Document #: 38-05143 Rev. *B
Page 2 of 18
CY7C1338B
Pin Configurations (continued)
119-Ball BGA
CY7C1338B (128K x 32)
1
2
A
3
A
A
A
4
5
A
A
A
6
A
7
A
VDDQ
NC
ADSP
ADSC
VDD
VDDQ
NC
B
C
CE2
A
NC
A
NC
NC
D
E
F
DQc
DQc
NC
VSS
VSS
VSS
BWc
VSS
NC
NC
CE1
OE
VSS
VSS
VSS
BWb
VSS
NC
NC
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQc
DQc
DQc
DQc
VDD
DQd
DQb
DQb
DQb
DQb
VDD
DQa
VDDQ
DQc
ADV
GW
VDD
CLK
G
H
J
DQc
VDDQ
DQd
VSS
VSS
K
L
M
N
DQd
VDDQ
DQd
DQd
DQd
DQd
BWd
VSS
VSS
NC
BWE
A1
BWa
VSS
VSS
DQa
DQa
DQa
DQa
VDDQ
DQa
DQd
NC
NC
A
VSS
MODE
A
A0
VDD
A
VSS
VDD
A
NC
A
DQa
NC
P
R
T
NC
NC
TMS
NC
NC
ZZ
U
VDDQ
TDI
TCK
TDO
VDDQ
Pin Descriptions
Name
I/O
Input-
Description
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[16:0] is
ADSC
Synchronous captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ADSP
Input-
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A[16:0] is
Synchronous captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
A[1:0]
Input-
A1, A0 Address Inputs. These inputs feed the on-chip burst counter as the LSBs as well as being
Synchronous used to access a particular memory location in the memory array.
A[16:2]
Input- Address Inputs used in conjunction with A[1:0] to select one of the 64K address locations. Sampled
Synchronous at the rising edge of the CLK, if CE1, CE2, and CE3 are sampled active, and ADSP or ADSC is active
LOW.
BW[3:0] Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes. Sampled on the
Synchronous rising edge. BW0 controls DQ[7:0] and DP0, BW1 controls DQ[15:8] and DP1, BW2 controls DQ[23:16]
and DP2, and BW3 controls DQ[31:24] and DP3. See Write Cycle Descriptions table for further details.
ADV
BWE
GW
Input-
Advance Input used to advance the on-chip address counter. When LOW the internal burst counter
Synchronous is advanced in a burst sequence. The burst sequence is selected using the MODE input.
Input- Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
Synchronous asserted LOW to conduct a byte write.
Input-
Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is used to conduct
Synchronous a global write, independent of the state of BWE and BW[3:0]. Global writes override byte writes.
CLK
CE1
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select/deselect the device. CE1 gates ADSP.
Document #: 38-05143 Rev. *B
Page 3 of 18
CY7C1338B
Pin Descriptions (continued)
Name
I/O
Input-
Synchronous and CE3 to select/deselect the device.
Description
CE2
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
CE3
OE
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select/deselect the device.
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins.
ZZ
Input-
Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a low-power standby
Asynchronous mode in which all other inputs are ignored, but the data in the memory array is maintained. Leaving
ZZ floating or NC will default the device into an active state. ZZ pin has an internal pull-down.
MODE
-
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. When left floating or NC, defaults to interleaved burst
order. Mode Pin has an internal pull-up.
DQ[31:0] I/O-
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by
Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by A[16:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by
OE in conjunction with the internal control logic. When OE is asserted LOW, the pins behave as
outputs. When HIGH, DQ[31:0] and DP[3:0] are placed in a three-state condition. The outputs are
automatically three-stated when a WRITE cycle is detected.
VDD
Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power supply.
VSS
Ground
Ground
Ground for the I/O circuitry of the device. Should be connected to ground of the system.
Ground for the device. Should be connected to ground of the system.
VSSQ
VDDQ
I/O Power
Supply
Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
NC
-
-
No connects.
DNU
Do not use pins. Should be left unconnected or tied LOW.
Single Read Accesses
Functional Overview
A single read access is initiated when the following conditions
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (tCDV) is 7.5 ns (117-MHz device).
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all as-
serted active, and (2) ADSP or ADSC is asserted LOW (if the
access is initiated by ADSC, the write inputs must be deassert-
ed during this first cycle). The address presented to the ad-
dress inputs is latched into the address register and the burst
counter/control logic and presented to the memory core. If the
OE input is asserted LOW, the requested data will be available
at the data outputs a maximum to tCDV after clock rise. ADSP
is ignored if CE1 is HIGH.
The CY7C1338B supports secondary cache in systems utiliz-
ing either a linear or interleaved burst sequence. The inter-
leaved burst order supports Pentium and i486 processors. The
linear burst sequence is suited for processors that utilize a
linear burst sequence. The burst order is user selectable, and
is determined by sampling the MODE input. Accesses can be
initiated with either the Processor Address Strobe (ADSP) or
the Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first ad-
dress in a burst sequence and automatically increments the
address for the rest of the burst access.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP is asserted LOW. The addresses pre-
sented are loaded into the address register and the burst
counter/control logic and delivered to the RAM core. The write
inputs (GW, BWE, and BW[3:0]) are ignored during this first
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BW0 controls DQ[7:0], BW1 controls
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[3:0]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip synchro-
nous self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. ADSP is ignored if CE1
is HIGH.
DQ[15:8], BW2 controls DQ[23:16], and BW3 controls DQ[31:24]
.
All I/Os are three-stated during a byte write. Since this is a
common I/O device, the asynchronous OE input signal must
be deasserted and the I/Os must be three-stated prior to the
presentation of data to DQ[31:0]. As a safety precaution, the
Document #: 38-05143 Rev. *B
Page 4 of 18
CY7C1338B
data lines are three-stated once a write cycle is detected, re-
gardless of the state of OE.
Table 1. Counter Implementation for the Intel
Pentium®/80486 Processor’s Sequence
First
Second
Third
Fourth
Single Write Accesses Initiated by ADSC
Address
Address
Address
Address
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BW[3:0]
indicate a write access. ADSC is ignored if ADSP is active LOW.
AX + 1,Ax
AX + 1,Ax
AX + 1,Ax
AX + 1,Ax
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
)
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the RAM
core. The information presented to DQ[31:0] will be written into
the specified address location. Byte writes are allowed. During
byte writes, BW0 controls DQ[7:0], BW1 controls DQ[15:8], BW2
controls DQ[23:16], and BWS3 controls DQ[31:24]. All I/Os are
three-stated when a write is detected, even a byte write. Since
this is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be three-stated prior to
the presentation of data to DQ[31:0]. As a safety precaution, the
data lines are three-stated once a write cycle is detected, re-
gardless of the state of OE.
Table 2. Counter Implementation for a Linear Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
AX + 1, Ax
AX + 1, Ax
AX + 1, Ax
AX + 1, Ax
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Burst Sequences
The CY7C1338B provides an on-chip 2-bit wraparound burst
Sleep Mode
counter inside the SRAM. The burst counter is fed by A[1:0]
,
The ZZ input pin is an asynchronous input. Asserting ZZ HIGH
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed. Ac-
cesses pending when entering the “sleep” mode are not con-
sidered valid nor is the completion of the operation guaran-
teed. The device must be deselected prior to entering the
“sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW. Leaving ZZ unconnected defaults the device into an ac-
tive state.
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LOW on MODE will select a linear burst sequence. A HIGH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default to an interleaved
burst sequence.
ZZ Mode Electrical Characteristics
Parameter
ICCZZ
Description
Test Conditions
Min.
Max.
Unit
Snooze mode
standby current
ZZ > VDD − 0.2V
10
mA
tZZS
Deviceoperationto
ZZ
ZZ > VDD − 0.2V
2tCYC
ns
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
2tCYC
Document #: 38-05143 Rev. *B
Page 5 of 18
CY7C1338B
Cycle Description Table[1, 2, 3]
ADD
Used
Cycle Description
CE1 CE3 CE2 ZZ ADSP ADSC ADV WE
OE CLK
DQ
Deselected Cycle, Pow-
er-down
None
H
L
L
L
X
X
X
H
X
X
X
L
L
L
L
L
X
L
X
X
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L-H High-Z
Deselected Cycle, Pow-
er-down
None
None
None
None
L
L
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
Deselected Cycle, Pow-
er-down
X
L
L
Deselected Cycle, Pow-
er-down
H
H
Deselected Cycle, Pow-
er-down
X
Snooze Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
None
External
External
External
External
External
Next
X
L
X
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
X
X
X
L
X
X
X
X
X
X
L
X
X
X
L
X
L
X
High-Z
Q
L-H
L
L
L
H
X
L
L-H High-Z
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H
L-H
D
Q
L
L
L
H
H
H
H
H
H
L
L
L
L
H
L
L-H High-Z
L-H
L-H High-Z
L-H
L-H High-Z
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L-H
L-H
L-H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H High-Z
L-H
L-H High-Z
Q
H
X
X
L-H
L-H
D
D
Write Cycle, Suspend Burst
L
Notes:
1. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW.
2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWS[3:0]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE
is a “Don't Care” for the remainder of the write cycle.
3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ = High-Z when OE is inactive, and DQ = data when OE is active.
Document #: 38-05143 Rev. *B
Page 6 of 18
CY7C1338B
Write Cycle Descriptions[1, 2, 3, 4]
Function
Read
GW
1
BWE
1
BW3
X
1
BW2
X
1
BW1
BW0
X
1
X
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
X
Read
1
0
Write Byte 0 - DQ[7:0]
Write Byte 1 - DQ[15:8]
Write Bytes 1, 0
Write Byte 2 - DQ[23:16]
Write Bytes 2, 0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3 - DQ[31:24]
Write Bytes 3, 0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
1
0
1
1
0
1
0
1
1
1
1
0
1
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
0
1
1
0
1
0
0
1
0
0
1
1
1
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
0
0
0
1
1
0
0
0
0
1
0
0
0
1
1
0
0
0
0
Write All Bytes
0
X
X
X
X
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature ...................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Ambient
Range Temperature[6]
VDD
VDDQ
Supply Voltage on VDD Relative to GND................ –0.5V to +4.6V
Com’l
Ind’l
0°C to +70°C
3.135V to 3.6V 2.375V to VDD
DC Voltage Applied to Outputs
in High Z State[5] ...............................................–0.5V to VDD + 0.5V
–40°C to +85°C
DC Input Voltage[5]...........................................–0.5V to VDD + 0.5V
Notes:
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
6.
TA is the case temperature.
Document #: 38-05143 Rev. *B
Page 7 of 18
CY7C1338B
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 2.5V, VDD = Min., IOH = –2.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
VDDQ = 2.5V, VDD = Min., IOL = 2.0 mA
VDDQ = 3.3V
Min. Max. Unit
VOH
Output HIGH Voltage
2.4
2.0
V
V
V
V
V
VOL
Output LOW Voltage
0.4
0.7
VIH
VIH
Input HIGH Voltage
Input HIGH Voltage
2.0
1.7
VDD +
0.3V
VDDQ = 2.5V
VDD
+
V
0.3V
VIL
VIL
IX
Input LOW Voltage[5]
Input LOW Voltage[5]
VDDQ = 3.3V
–0.3
–0.3
−1
0.8
0.7
1
V
V
VDDQ = 2.5V
Input Load Current
(except ZZ and MODE)
GND ≤ VI ≤ VDDQ
µA
Input Current of MODE
Input = VSS
–30
–5
µA
µA
µA
µA
µA
Input = VDDQ
5
Input Current of ZZ
Input = VSS
Input = VDDQ
30
5
IOZ
IOS
IDD
Output Leakage Current
Output Short Circuit Current[7]
GND ≤ VI ≤ VDD, Output Disabled
VDD = Max., VOUT = GND
–5
–300 mA
VDD Operating Supply Current
VDD = Max., IOUT = 0 mA,
f = fMAX =1/tCYC
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
350
325
125
110
mA
mA
mA
mA
ISB1
Automatic CE Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected, 8.5-ns cycle, 117 MHz
IN ≥ VIH or VIN ≤ VIL,
V
10-ns cycle, 100 MHz
f = fMAX = 1/tCYC
,
inputs switching
ISB2
Automatic CE Power-Down
Current —CMOS Inputs
Max. VDD, Device Deselected, All speeds
IN ≤ 0.3V or VIN > VDDQ – 0.3V,
10
mA
V
f = 0, inputs static
ISB3
Automatic CE Power-Down
Current—CMOS Inputs
Max. VDD, Device Deselected,
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
95
85
mA
mA
VIN ≥ VDDQ– 0.3V or VIN ≤ 0.3V,
f = fMAX, inputs switching
ISB4
Automatic CE Power-Down Cur- Max. VDD, Device Deselected,
rent —CMOS Inputs IN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
All speeds
30
mA
V
Note:
7. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Document #: 38-05143 Rev. *B
Page 8 of 18
CY7C1338B
Capacitance[8]
Parameter
Description
Input Capacitance
I/O Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 5.0V
Max.
5.0
Unit
pF
CIN
CI/O
8.0
pF
AC Test Loads and Waveforms [9]
R1=317Ω
3.3V
OUTPUT
OUTPUT
ALL INPUT PULSES
90%
Z =50Ω
0
3.0V
GND
90%
10%
R =50Ω
L
10%
R2=351Ω
5 pF
V =1.5V
L
INCLUDING
JIG AND
SCOPE
≤ 3.0 ns
≤ 3.0 ns
(a)
(b)
Switching Characteristics Over the Operating Range[10]
-117
-100
Parameter
tCYC
Description
Min.
8.5
3.0
3.0
1.5
0.5
Max.
Min.
10
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycle Time
Clock HIGH
tCH
4.0
4.0
1.5
0.5
tCL
Clock LOW
tAS
Address Set-Up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-Up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
BWS[1:0], GW,BWE Set-Up Before CLK Rise
BWS[1:0], GW,BWE Hold After CLK Rise
ADV Set-Up Before CLK Rise
ADV Hold After CLK Rise
tAH
tCDV
tDOH
tADS
tADH
tWES
tWEH
tADVS
tADVH
tDS
7.5
8.0
2.0
2.0
0.5
2.0
0.5
2.0
0.5
1.5
0.5
2.0
0.5
2.0
2.0
0.5
2.0
0.5
2.0
0.5
1.5
0.5
2.0
0.5
Data Input Set-Up Before CLK Rise
Data Input Hold After CLK Rise
Chip Enable Set-Up
tDH
tCES
tCEH
tCHZ
tCLZ
tEOHZ
tEOLZ
Chip Enable Hold After CLK Rise
Clock to High-Z[11, 12]
3.5
3.5
3.5
3.5
3.5
3.5
Clock to Low-Z[11, 12]
0
0
0
0
OE HIGH to Output High-Z[11, 13]
OE LOW to Output Low-Z[11, 13]
OE LOW to Output Valid
tEOV
Notes:
8. Tested initially and after any design or process changes that may affect these parameters.
9. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot: VIL(AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for
t < 200 ms
10. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC test loads.
11. tCHZ, tCLZ, tEOHZ, and tEOLZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
12. At any given voltage and temperature, tCHZ (max) is less than tCLZ (min).
13. This parameter is sampled and not 100% tested.
Document #: 38-05143 Rev. *B
Page 9 of 18
CY7C1338B
Timing Diagrams
Write Cycle Timing[14, 15]
Single Write
Burst Write
Pipelined Write
t
Unselected
CH
t
CYC
CLK
t
ADH
t
ADS
t
ADSP ignored with CE inactive
CL
1
ADSP
ADSC
ADV
t
ADH
t
ADSC initiated write
ADS
t
t
ADVH
ADVS
t
ADV Must Be Inactive for ADSP Write
WD2
AS
WD3
ADD
GW
WE
WD1
t
AH
t
WH
t
WH
t
WS
t
WS
t
t
CES
CE masks ADSP
CEH
1
CE
1
t
t
CEH
CES
Unselected with CE
2
CE
2
CE
3
t
CES
t
CEH
OE
t
DH
t
DS
High-Z
High-Z
Data
In
3a
2a
= UNDEFINED
1a
2b
2c
2d
= DON’T CARE
Notes:
14. WE is the combination of BWE, BW[3:0], and GW to define a write cycle (see Write Cycle Descriptions table).
15. WDx stands for Write Data to Address X.
Document #: 38-05143 Rev. *B
Page 10 of 18
CY7C1338B
Timing Diagrams (continued)
Read Cycle Timing[14, 16]
Burst Read
Single Read
tCYC
Unselected
tCH
Pipelined Read
CLK
tADH
tADS
ADSP
tCL
ADSP ignored with CE1 inactive
tADS
ADSC initiated read
ADSC
ADV
tADVS
tADH
Suspend Burst
tADVH
tAS
ADD
GW
RD1
RD3
RD2
tAH
tWS
tWS
tWH
WE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
Unselected with CE2
CE2
tCES
tCEH
CE3
OE
tCEH
tEOV
tCES
tOEHZ
tDOH
tCDV
3a
Data Out
2d
2a
2b
2c
1a
tCLZ
tCHZ
= DON’T CARE
= UNDEFINED
Note:
16. RDx stands for Read Data from Address X.
Document #: 38-05143 Rev. *B
Page 11 of 18
CY7C1338B
Timing Diagrams (continued)
Read/Write Cycle Timing
tCYC
tCL
tCH
CLK
tAH
tAS
A
D
B
C
ADD
tADH
tADS
ADSP
tADH
tADS
ADSC
ADV
tADVH
tADVS
tCEH
tCES
CE1
tCEH
tCES
CE
tWES
tWEH
WE
OE
ADSP ignored
with CE1 HIGH
tEOHZ
tCLZ
Data
In/Out
Q
(B+3)
D
(C+1)
D
(C+2)
D
(C+3)
Q
(B+2)
Q
(B+1)
Q(B)
Q(B)
D(C)
Q(D)
Q(A)
tCDV
tDOH
tCHZ
Device originally
deselected
WE is the combination of BWE, BWS[1:0], and GW to define a write cycle (see Write Cycle Descriptions table).
CE is the combination of CE2 and CE3. All chip selects need to be active in order to select
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
Qx stands for Data-out X.
Document #: 38-05143 Rev. *B
Page 12 of 18
CY7C1338B
Timing Diagrams (continued)
Pipeline Timing
tCYC
tCL
tCH
CLK
tAS
C
E
F
G
H
B
D
A
ADD
tADH
tADS
ADSP
ADSC
ADV
tCEH
tCES
CE1
CE
tWES
tWEH
WE
OE
ADSP ignored
with CE1 HIGH
tCLZ
Data
D (E)
D (F)
D (H)
Q(A)
D (G)
Q(B)
Q(C)
Q(D)
In/Out
tCDV
tDOH
tCHZ
Device originally
deselected
WE is the combination of BWE, BW[1:0], and GW to define a write cycle (see Write Cycle Descriptions table).
CE is the combination of CE2 and CE3. All chip selects need to be active in order to select
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
Qx stands for Data-out X.
= UNDEFINED
= DON’T CARE
Document #: 38-05143 Rev. *B
Page 13 of 18
CY7C1338B
Timing Diagrams (continued)
OE Switching Waveforms
OE
tEOV
tEOHZ
three-state
I/Os
tEOLZ
Document #: 38-05143 Rev. *B
Page 14 of 18
CY7C1338B
Timing Diagrams (continued)
ZZ Mode Timing [17, 18]
CLK
ADSP
HIGH
ADSC
CE1
LOW
CE2
HIGH
CE3
ZZ
tZZS
ICC
ICC(active)
tZZREC
ICCZZ
I/Os
Three-state
Notes:
17. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device.
18. I/Os are in three-state when exiting ZZ “sleep” mode.
Document #: 38-05143 Rev. *B
Page 15 of 18
CY7C1338B
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
Package Type
100-Lead Thin Quad Flat Pack
119-Ball BGA
117
CY7C1338B-117AC
CY7C1338B-117BGC
CY7C1338B-100AC
CY7C1338B-100BGC
CY7C1338B-100AI
CY7C1338B-100BGI
A101
BG119
A101
Commercial
Industrial
100
100-Lead Thin Quad Flat Pack
119-Ball BGA
BG119
A101
100-Lead Thin Quad Flat Pack
119-Ball BGA
BG119
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
Document #: 38-05143 Rev. *B
Page 16 of 18
CY7C1338B
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Pentium is a registered trademark of Intel Corporation. All product and company names mentioned in this document may be the
trademarks of their respective holders.
Document #: 38-05143 Rev. *B
Page 17 of 18
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1338B
Document History Page
Document Title: CY7C1338B 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM
Document Number: 38-05143
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
109887
121471
123113
Description of Change
Change from Spec number 38-00939 to 38-05143
Update package diagram 51-85115 (BG119) to rev. *B
09/15/01
11/14/02
01/18/03
SZV
DSG
RBI
*A
*B
Added power up requirements to AC Test loads and waveforms information
Document #: 38-05143 Rev. *B
Page 18 of 18
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