CY62148BLL-70ZRIT [ROCHESTER]
Standard SRAM, 512KX8, 70ns, CMOS, PDSO32, REVERSE, TSOP2-32;
| 型号： | CY62148BLL-70ZRIT |
| 厂家： | 
Rochester Electronics |
| 描述： | Standard SRAM, 512KX8, 70ns, CMOS, PDSO32, REVERSE, TSOP2-32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：338K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62148B MoBL™
4-Mbit (512K x 8) Static RAM
is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and three-state drivers. This device
has an automatic power-down feature that reduces power
consumption by more than 99% when deselected.
Features
• High Speed: 70 ns
• 4.5V–5.5V operation
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A18).
• Low active power
— Typical active current: 2.5 mA @ f = 1 MHz
— Typical active current: 12.5 mA @ f = fmax(70 ns)
• Low standby current
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH for read. Under these conditions, the
contents of the memory location specified by the address pins
will appear on the I/O pins.
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• CMOS for optimum speed/power
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
• Available in standard 32-lead (450-mil) SOIC, 32-lead
TSOP II and 32-lead Reverse TSOP II packages
The CY62148B is available in a standard 32-pin 450-mil-wide
body width SOIC, 32-pin TSOP II, and 32-pin Reverse TSOP
II packages.
Functional Description
The CY62148B is a high-performance CMOS static RAM
organized as 512K words by 8 bits. Easy memory expansion
Logic Block Diagram
Pin Configuration
Top View
SOIC
TSOP II
V
A
32
31
30
1
2
3
4
5
6
7
17
CC
A
A
A
A
A
16
15
14
12
18
29
28
27
26
WE
A
A
A
7
13
6
A
A
8
A
5
9
I/O
25
24
23
22
21
A
A
A
0
8
9
10
11
12
13
A
4
11
INPUT BUFFER
3
2
OE
A
10
I/O
I/O
1
2
A
0
A
CE
I/O
I/O
1
A
1
A
7
0
A
I/O
I/O
I/O
4
0
1
2
20
19
6
A
5
6
I/O
5
14
15
16
A
I/O
I/O
I/O
I/O
I/O
18
17
4
3
3
4
5
512K x 8
ARRAY
A
7
GND
A
12
A
14
Top View
Reverse
TSOP II
A
16
A
17
I/O
I/O
I/O
GND
I/O
I/O
1
17
18
19
20
21
22
16
15
14
13
12
11
10
9
8
7
6
5
3
I/O
6
7
POWER
DOWN
2
4
5
COLUMN
DECODER
CE
I/O
I/O
I/O
0
6
I/O
WE
A
0
7
A
CE
1
OE
23 A10
A
2
24
A
OE
A11
3
25
26
27
28
29
30
A
4
A
A
5
9
A
6
A
8
A
A
13
7
A
A
A
12
14
16
4
3
2
1
WE
A
18
A
31
32
15
A
V
17
cc
Cypress Semiconductor Corporation
Document #: 38-05039 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 2, 2006
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CY62148B MoBL™
Product Portfolio
Power Dissipation
Operating, Icc
f = fmax
Standby (ISB2)
VCC Range
Typ.
Product
Min.
Max.
Speed
Temp.
Com’l
Ind’l
Typ.[3]
Max.
Typ.[3]
Max.
CY62148BLL
4.5 V
5.0V
5.5V
70 ns
12.5 mA
20 mA
4 µA
20 µA
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage...............................................2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.....................................................>200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on VCC to Relative GND........ –0.5V to +7.0V
Ambient
Range
Commercial
Industrial
Temperature[2]
0°C to +70°C
VCC
DC Voltage Applied to Outputs
in High Z State[1] .....................................–0.5V to VCC +0.5V
4.5V–5.5V
DC Input Voltage[1]..................................–0.5V to VCC +0.5V
–40°C to +85°C
Electrical Characteristics Over the Operating Range
CY62148B-70
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Test Conditions
Min.
Typ.[3]
Max.
Unit
V
VCC = Min., IOH = – 1 mA
VCC = Min., IOL = 2.1 mA
2.4
0.4
VCC+0.3
0.8
V
VIH
2.2
–0.3
–1
V
VIL
V
IIX
GND ≤ VI ≤ VCC
+1
µA
µA
IOZ
Output Leakage
Current
GND ≤ VI ≤ VCC, Output Disabled
–1
+1
ICC
VCC Operating
Supply Current
f = fMAX = 1/tRC
f = 1 MHz
Com/Ind’l
OUT =0 mA
CC = Max.,
12.5
2.5
20
mA
mA
I
V
ISB1
Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC
,
Com/Ind’l
1.5
mA
CE ≥ VIH
VIN ≥ VIH or
VIN ≤ VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC
,
Com/Ind’l
4
20
µA
CE ≥ VCC – 0.3V,
VIN ≥ VCC – 0.3V,
or VIN ≤ 0.3V, f =0
Notes:
1. V (min.) = –2.0V for pulse durations of less than 20 ns.
IL
2. T is the “Instant On” case temperature.
A
3. Typical values are measured at V = 5V, T = 25°C, and are included for reference only and are not tested or guaranteed.
CC
A
Document #: 38-05039 Rev. *C
Page 2 of 11
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CY62148B MoBL™
Capacitance[4]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
CC = 5.0V
6
8
V
COUT
pF
AC Test Loads and Waveforms
R1 1800Ω
R1 1800 Ω
5V
ALL INPUT PULSES
5V
3.0V
R2
OUTPUT
OUTPUT
R2
990Ω
90%
10%
90%
100 pF
5 pF
10%
990Ω
GND
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
≤ 3 ns
≤ 3 ns
(b)
(a)
Equivalent to:
OUTPUT
THEVENIN EQUIVALENT
639Ω
1.77V
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05039 Rev. *C
Page 3 of 11
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CY62148B MoBL™
Switching Characteristics[5] Over the Operating Range
62148BLL-70
Parameter
Description
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
70
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[6]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
70
tOHA
tACE
70
35
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
5
10
0
25
25
70
tPD
WRITE CYCLE[8]
tWC
Write Cycle Time
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tAW
tHA
tSA
0
tPWE
tSD
55
30
0
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[6]
tHD
tLZWE
tHZWE
5
WE LOW to High Z[6, 7]
25
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I and 100-pF load capacitance.
OL OH
6. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
7. t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
HZOE HZCE
HZWE
8. The internal write time of the memory is defined by the overlap of CELOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Document #: 38-05039 Rev. *C
Page 4 of 11
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CY62148B MoBL™
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Description
VCC for Data Retention
Data Retention Current
Conditions
Min.
Typ.[3]
Max.
Unit
V
2.0
Com’l LL
Ind’l LL
No input may exceed
CC + 0.3V
CC = VDR = 3.0V
CE > VCC – 0.3V
VIN > VCC – 0.3V or
IN < 0.3V
20
20
µA
µA
ns
V
V
[4]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
[9]
tR
tRC
ns
V
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
V
CC
DR
t
t
R
CDR
CE
Switching Waveforms
Read Cycle No.1[10, 11]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
V
CC
50%
50%
SUPPLY
ISB
CURRENT
Notes:
9. Full Device operatin requires linear V ramp from V to V
> 100 µs or stable at V > 100 µs.
cc(min)
CC
DR
CC(min)
10. Device is continuously selected. OE, CE = V .
IL
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05039 Rev. *C
Page 5 of 11
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CY62148B MoBL™
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[13]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]
t
WC
ADDRESS
CE
t
SCE
tHZCE
t
t
HA
AW
t
t
PWE
SA
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE
15
t
HZOE
Notes:
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
14. Data I/O is high-impedance if OE = V
.
IH
15. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05039 Rev. *C
Page 6 of 11
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CY62148B MoBL™
Switching Waveforms (continued)
Write Cycle No.3 (WE Controlled, OE LOW)[13, 14]
t
WC
ADDRESS
t
SCE
CE
tHZCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 15
DATAI/O
DATA VALID
t
t
LZWE
HZWE
Truth Table
CE
H
L
OE
WE
I/O0 – I/O7
High Z
Mode
Power
X
L
X
H
L
Power-Down
Read
Standby (ISB
)
Data Out
Data In
High Z
Active (ICC
Active (ICC
Active (ICC)
)
L
X
H
Write
)
L
H
Selected, Outputs Disabled
Ordering Information
Speed
Package
Operating
Range
Ordering Code
Package Type
(ns)
Diagram
51-85081
51-85095
51-85138
51-85081
51-85095
51-85138
70
CY62148BLL-70SC
CY62148BLL-70ZC
CY62148BLL-70ZRC
CY62148BLL-70SI
CY62148BLL-70ZI
CY62148BLL-70ZRI
32-lead (450-Mil) Molded SOIC
32-lead TSOP II
Commercial
32-lead RTSOP II
32-lead (450-Mil) Molded SOIC
32-lead TSOP II
Industrial
32-lead RTSOP II
Please contact your local Cypress sales representative for availability of these parts
Document #: 38-05039 Rev. *C
Page 7 of 11
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CY62148B MoBL™
Package Diagrams
32-lead (450 MIL) Molded SOIC (51-85081)
51-85081-A
Document #: 38-05039 Rev. *C
Page 8 of 11
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CY62148B MoBL™
Package Diagrams (continued)
32-lead Thin Small Outline Package Type II
(51-85095)
51-85095-**
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05039 Rev. *C
Page 9 of 11
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CY62148B MoBL™
Package Diagrams (continued)
32-lead Reverse Thin Small Outline Package Type II (51-85138)
51-85138-**
Document #: 38-05039 Rev. *C
Page 10 of 11
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62148B MoBL™
Document History Page
Document Title: CY62148B 4-Mbit (512K x 8) Static RAM
Document Number: 38-05039
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
106833
106970
109766
485639
Description of Change
05/01/01
07/16/01
10/09/01
See ECN
SZV
GAV
MGN
VKN
Change from Spec number 38-01104 to 38-05039
Modified annotations on Pin Configurations; tSD = 30 ns
Remove 55-ns devices
*A
*B
*C
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Corrected the typo in the Array size in the Logic Block Diagram on page# 1
Renamed Package Name column with Package Diagram in the Ordering
Information Table
Document #: 38-05039 Rev. *C
Page 11 of 11
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