CS8182YDPS5 [ROCHESTER]
2.8 V-45 V ADJUSTABLE POSITIVE LDO REGULATOR, 0.6 V DROPOUT, PSSO5, D2PAK-5;
| 型号： | CS8182YDPS5 |
| 厂家： | 
Rochester Electronics |
| 描述： | 2.8 V-45 V ADJUSTABLE POSITIVE LDO REGULATOR, 0.6 V DROPOUT, PSSO5, D2PAK-5 输出元件 调节器 |
| 文件： | 总13页 (文件大小：793K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS8182
Micropower 200 mA
Low Dropout Tracking
Regulator/Line Driver
The CS8182 is a monolithic integrated low dropout tracking
regulator designed to provides an adjustable buffered output voltage
that closely tracks ( 10 mV) the reference input. The output delivers
up to 200 mA while being able to be configured higher, lower or equal
to the reference voltages.
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The device has been designed to operate over a wide range (2.8 V to
45 V) while still maintaining excellent DC characteristics. The
CS8182 is protected from reverse battery, short circuit and thermal
runaway conditions. The device also can withstand 45 V load dump
transients and −50 V reverse polarity input voltage transients. This
makes it suitable for use in automotive environments.
8
1
1
1
5
5
2
SO−8
D PAK−5
DPS SUFFIX
CASE 936AC
DPAK−5
DF SUFFIX
CASE 751
DT SUFFIX
CASE 175AA
The V /ENABLE lead serves two purposes. It is used to provide
REF
the input voltage as a reference for the output and it also can be pulled
low to place the device in sleep mode where it nominally draws less
than 30 mA from the supply.
PIN CONNECTIONS AND
MARKING DIAGRAMS
1
8
V
GND
GND
V
V
Features
IN
OUT
GND
GND
Adj
• 200 mA Source Capability
• Output Tracks within 10 mV Worst Case
• Low Dropout (0.35 V Typ. @ 200 mA)
• Low Quiescent Current
/ENABLE
8182G
REF
Tab
Pin 1. V
2. V
GND
IN
CS
8182
AWLYWWG
• Thermal Shutdown
OUT
ALYWW
3. GND
4. Adj
• Short Circuit Protection
• Wide Operating Range
5. V
REF
1
5
• Internally Fused Leads in SO−8 Package
• For Automotive and Other Applications Requiring Site and Change
Control
1
A
= Assembly Location
= Wafer Lot
WL, L
YY, Y
= Year
• Pb−Free Packages are Available
WW, W = Work Week
G or G
= Pb−Free Device
V
V
OUT
IN
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Current Limit &
SAT Sense
Adj
−
ENABLE
+
V
/ENABLE
REF
+
−
GND
Thermal
Shutdown
2.0 V
Figure 1. Block Diagram
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
February, 2006 − Rev. 23
CS8182/D
CS8182
PACKAGE PIN DESCRIPTION
Package Lead Number
2
SO−8
D PAK 5−PIN
DPAK 5−PIN
Lead Symbol
Function
8
1
2
3
4
5
1
2
3
4
5
V
Input Voltage
IN
1
V
Regulated Output
Ground
OUT
2, 3, 6, 7
GND
Adj
4
5
Adjust Lead
V
/ENABLE
Reference Voltage and ENABLE Input
REF
MAXIMUM RATINGS
Rating
Value
−65 to +150
+150
Unit
°C
°C
V
Storage Temperature Range
Junction Temperature
Supply Voltage Range (Continuous)
−16 to 45
45
Peak Transient Voltage (V = 14 V, Load Dump Transient = 31 V)
V
IN
Voltage Range (Adj, V
, V /ENABLE)
OUT REF
−10 to +V
V
IN
Package Thermal Resistance, SO−8:
Junction−to−Case, R
25
80
°C/W
°C/W
q
JC
Junction−to−Air, R
q
JA
2
Package Thermal Resistance, D PAK
Junction−to−Case, R
4.0
48
°C/W
°C/W
q
JC
Junction−to−Air, R
q
JA
Package Thermal Resistance, DPAK
Junction−to−Case, R
8.0
64
°C/W
°C/W
q
JC
Junction−to−Air, R
q
JA
ESD Capability (Human Body Model)
(Machine Model)
2.0
200
kV
V
Lead Temperature Soldering: (Note 1)
(SO−8)
(D PAK)
(DPAK)
240
225
260
2
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. 60 second maximum above 183°C.
RECOMMENDED OPERATING RANGES
Rating
Value
Unit
°C
Junction Temperature, T
−40 to+125
3.4 to 45
J
Input Voltage, Continuous V
V
IN
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2
CS8182
ELECTRICAL CHARACTERISTICS (V = 14 V; V
/ENABLE > 2.75 V; −40°C < T < +125°C; C
≥ 10 mF;
IN
REF
J
OUT
0.1 W < C
< 1.0 W @ 10 kHz, unless otherwise specified.)
OUT−ESR
Parameter
Regular Output
− V
Test Conditions
Min
Typ
Max
Unit
V
4.5 V ≤ V ≤ 26 V, 100 mA ≤ I ≤ 200 mA, Note 2
OUT
−10
−5.0
−
−
10
5
mV
mV
REF
OUT
IN
V
Tracking Error
V
= 12 V, I
= 30 mA, V = 5.0 V, Note 2
OUT
IN
OUT
REF
Dropout Voltage (V − V
)
I
I
I
= 100 mA
= 30 mA
= 200 mA
−
−
−
100
−
350
150
500
600
mV
mV
mV
IN
OUT
OUT
OUT
OUT
Line Regulation
Load Regulation
Adj Lead Current
Current Limit
4.5 V ≤ V ≤ 26 V, Note 2
−
−
−
−
10
10
mV
mV
mA
IN
100 mA ≤ I
≤ 200 mA, Note 2
OUT
Loop in Regulation
−
0.2
−
1.0
700
V
= 14 V, V
= 5.0 V, V
= 90% of V
, Note 2
REF
225
mA
IN
REF
OUT
Quiescent Current (I − I
)
V
V
V
= 12 V, I
= 12 V, I
= 12 V, V
= 200 mA
= 100 mA
−
−
−
15
75
30
25
150
55
mA
mA
mA
IN
OUT
IN
IN
IN
OUT
OUT
/ENABLE = 0 V
REF
Reverse Current
Ripple Rejection
Thermal Shutdown
V
= 5.0 V, V = 0 V
−
0.2
−
1.5
−
mA
dB
°C
OUT
IN
f = 120 Hz, I
GBD
= 200 mA, 4.5 V ≤ V ≤ 26 V
60
OUT
IN
150
180
210
V
/ENABLE
REF
Enable Voltage
−
0.80
−
2.00
0.2
2.75
1.0
V
Input Bias Current
V
/ENABLE
REF
mA
2. V
connected to Adj lead.
OUT
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3
CS8182
TYPICAL CHARACTERISTICS
18
16
14
12
10
8
6
4
2
0
0
20 40 60 80 100 120 140 160 180 200
OUTPUT CURRENT (mA)
Figure 2. Quiescent Current vs. Output Current
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
100
90
80
70
60
50
40
30
20
I (V
) = 20 mA
OUT
V
/ ENABLE = 0 V
0.1
0
10
0
REF
I (V
) = 1 mA
OUT
0
5
10
15
20
25
30
35
40
45
0
5
10
15
V , INPUT VOLTAGE (V)
IN
20
25
30
35
40
45
V
, INPUT VOLTAGE (V)
IN
Figure 3. Quiescent Current vs. Input Voltage
(Operating Mode)
Figure 4. Quiescent Current vs. Input Voltage
(Sleep Mode)
20
18
16
14
12
10
8
140
120
100
80
* Graph is duplicate for V > 1.6 V.
* Graph is duplicate for V > 1.6 V.
IN
IN
**Dip (@5 V) shifts with V
voltage.
**Dip (@5 V) shifts with V
voltage.
REF
REF
V
= 0 V
IN
60
V
V
= 6 V*
IN
REF
V
V
= 6 V*
= 5 V**
IN
REF
6
= 5 V**
40
4
20
0
2
0
V
= 0 V
IN
0
5
10
FORCED V
15
20
25
0
5
10
15
20
25
30
35
40
VOLTAGE (V)
FORCED V
VOLTAGE (V)
OUT
OUT
Figure 5. VOUT Reverse Current
Figure 6. VOUT Reverse Current
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4
CS8182
CIRCUIT DESCRIPTION
ENABLE Function
Output Voltage
By pulling the V /ENABLE lead below 2.0 V typically,
(see Figure 10 or Figure 11), the IC is disabled and enters a
sleep state where the device draws less than 55 mA from
The output is capable of supplying 200 mA to the load
while configured as a similar (Figure 7), lower (Figure 9), or
higher (Figure 8) voltage as the reference lead. The Adj lead
REF
supply. When the V /ENABLE lead is greater than 2.75 V,
acts as the inverting terminal of the op amp and the V
lead as the non−inverting.
REF
REF
V
OUT
tracks the V /ENABLE lead normally.
REF
The device can also be configured as a high−side driver as
displayed in Figure 12.
V
, 200 mA
OUT
V
, 200 mA
OUT
Loads
C2**
10 mF
V
V
IN
B+
Loads
C2**
10 mF
V
V
B+
OUT
OUT
IN
C1*
1.0 mF
C1*
1.0 mF
GND
GND
Adj
GND
GND
GND
GND
Adj
GND
GND
R
F
V
V
/
REF
5.0 V
REF
V
/
REF
ENABLE
C3***
10 nF
C3***
10 nF
ENABLE
R
A
R
R
E
A
V
OUT
+ V
REF
V
OUT
+ V (1 )
REF
)
Figure 8. Tracking Regulator at Higher Voltages
Figure 7. Tracking Regulator at the Same Voltage
V
, 200 mA
OUT
V
, 200 mA
OUT
V
V
B+
OUT
IN
Loads
C2**
10 mF
V
V
B+
OUT
IN
C1*
C2**
10 mF
C1*
GND
GND
Adj
GND
GND
1.0 mF
GND
GND
Adj
GND
GND
1.0 mF
R
R1
R2
V
V
/
REF
REF
ENABLE
V
V
/
REF
REF
ENABLE
C3***
10 nF
C3***
10 nF
from MCU
R2
R1 ) R2
V
OUT
+ V
(
)
REF
Figure 9. Tracking Regulator at Lower Voltages
Figure 10. Tracking Regulator with ENABLE Circuit
V
V
(5.0 V)
IN
REF
6.0 V−40 V
NCV8501
200 mA
V
V
B+
100 nF
OUT
IN
GND
GND
Adj
GND
GND
5.0 V
V
V
IN
OUT
mC
C1*
10 mF
To Load
(e.g. sensor)
GND
GND
Adj
GND
GND
1.0 mF
MCU
V
/
REF
C3***
10 nF
ENABLE
I/O
V
/
REF
C3***
10 nF
ENABLE
V
+ B ) * V
OUT
SAT
Figure 11. Alternative ENABLE Circuit
Figure 12. High−Side Driver
* C1 is required if the regulator is far from the power source filter.
** C2 is required for stability.
*** C3 is recommended for EMC susceptibility.
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5
CS8182
APPLICATION NOTES
VOUT Short to Battery
Figure14. In this case the CS8182 supply input voltage is set
at 7 V when a short to battery (14 V typical) occurs on V
which normally runs at 5 V. The current into the device
(ammeter in Figure 14) will draw additional current as
displayed in Figure 15.
OUT
The CS8182 will survive a short to battery when hooked
up the conventional way as shown in Figure 13. No damage
to the part will occur. The part also endures a short to battery
when powered by an isolated supply at a lower voltage as in
Short to battery
B+
V
70 mA
OUT
Loads
V
V
IN
OUT
+
−
Automotive Battery
typically 14 V
C1*
1.0 mF
C2**
10 mF
GND
GND
Adj
GND
GND
V
/
REF
5.0 V
+
ENABLE
C3***
10 nF
5.0 V
−
V
= V
OUT
REF
Figure 13.
Short to battery
Loads
A
B+
Automotive Battery
typically 14 V
V
70 mA
OUT
V
V
IN
OUT
+
C1*
7 V
C2**
10 mF
−
1.0 mF
GND
GND
Adj
GND
GND
V
/
REF
5.0 V
+
ENABLE
C3***
10 nF
* C1 is required if the regulator is far from the power source filter.
** C2 is required for stability.
*** C3 is recommended for EMC susceptibility.
5.0 V
−
V
= V
OUT
REF
Figure 14.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
Switched Application
The CS8182 has been designed for use in systems where
the reference voltage on the V /ENABLE pin is
continuously on. Typically, the current into the
REF
V /ENABLE pin will be less than 1.0 mA when the
REF
voltage on the V pin (usually the ignition line) has been
IN
switched out (V can be at high impedance or at ground.)
IN
Reference Figure 16.
Ignition
Switch
V
OUT
V
V
IN
OUT
V
BAT
0.2
0
C1
1.0 mF
C2
10 mF
GND
GND
Adj
GND
GND
5 6 7 8 9 10 1112131415 1617181920 212223242526
V
VOLTAGE (V)
OUT
Figure 15. VOUT Short to Battery
V
/
REF
ENABLE
V
< 1.0 mA
REF
5.0 V
Figure 16.
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6
CS8182
External Capacitors
The value of R
can then be compared with those in the
qJA
package section of the data sheet. Those packages with
’s less than the calculated value in equation 2 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external heat
sink will be required.
The output capacitor for the CS8182 is required for
stability. Without it, the regulator output will oscillate.
Actual size and type may vary depending upon the
application load and temperature range. Capacitor effective
series resistance (ESR) is also a factor in the IC stability.
Worst−case is determined at the minimum ambient
temperature and maximum load expected.
R
qJA
The output capacitor can be increased in size to any
desired value above the minimum. One possible purpose of
this would be to maintain the output voltage during brief
conditions of negative input transients that might be
characteristic of a particular system.
The capacitor must also be rated at all ambient
temperatures expected in the system. To maintain regulator
stability down to −40°C, a capacitor rated at that temperature
must be used.
SMART
I
IN
REGULATORꢀ
I
OUT
V
IN
V
OUT
Control
Features
I
Q
More information on capacitor selection for SMART
REGULATOR®s is available in the SMART REGULATOR
application note, “Compensation for Linear Regulators,”
document number SR003AN/D, available through our
website at http://www.onsemi.com.
Figure 17. Single Output Regulator with Key
Performance Parameters Labeled
Heatsinks
Calculating Power Dissipation in a Single Output
Linear Regulator
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
The maximum power dissipation for a single output
regulator (Figure 17) is:
{
}
(min) I
OUT
PD(max) + V (max) * V
(max)
IN OUT
) V (max)I
IN
Q
determine the value of R
(1)
qJA:
where:
(3)
R
+ R
qJC
) R ) R
qCS qSA
qJA
V
V
is the maximum input voltage,
is the minimum output voltage,
is the maximum output current, for the
IN(max)
OUT(min)
OUT(max)
where:
I
R
qJC
R
qCS
R
qSA
= the junction−to−case thermal resistance,
= the case−to−heatsink thermal resistance, and
= the heatsink−to−ambient thermal resistance.
application,and
I
I
is the quiescent current the regulator consumes at
Q
.
OUT(max)
Once the value of PD(max) is known, the maximum
R
qJC
appears in the package section of the data sheet. Like
permissible value of R
can be calculated:
R
qJA
, it is a function of package type. R
and R
are
qJA
qCS
qSA
functions of the package type, heatsink and the interface
between them. These values appear in heat sink data sheets
of heatsink manufacturers.
150°C * T
A
R
qJA
+
(2)
P
D
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7
CS8182
180
160
180
160
140
120
100
80
140
120
100
80
1 oz
2 oz
1 oz
2 oz
60
60
40
40
20
0
20
0
0
100
200
300
400
500
600
700 800
0
100
200
300
400
500
600
700 800
2
2
COPPER AREA (mm )
COPPER AREA (mm )
Figure 18. 8 Lead SOIC (Fused) Thermal
Resistance
Figure 19. 5 Lead DPAK Thermal Resistance
180
160
140
180
160
140
120
8 Lead SOIC w/ 4 Thermal Leads 1 oz
8 Lead SOIC w/ 4 Thermal Leads 2 oz
5 Lead DPAK 1 oz
120
100
80
5 Lead DPAK 2 oz
100
80
1 oz
2 oz
60
60
2
5 Lead D PAK 1 oz
40
40
2
5 Lead D PAK 2 oz
20
0
20
0
0
100
200
300
400
500
600
700 800
0
100
200
300
400
500
600
700 800
2
2
COPPER AREA (mm )
COPPER AREA (mm )
Figure 20. 5 Lead D2PAK Thermal Resistance
Figure 21. Thermal Resistance Summary
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8
CS8182
ORDERING INFORMATION
Device
†
Package
Shipping
CS8182YDF8
SO−8
95 Units / Rail
95 Units / Rail
CS8182YDF8G
SO−8
(Pb−Free)
CS8182YDFR8
SO−8
2500 / Tape & Reel
2500 / Tape & Reel
CS8182YDFR8G
SO−8
(Pb−Free)
2
CS8182YDPS5
D PAK 5−PIN
50 Units / Rail
50 Units / Rail
2
CS8182YDPS5G
D PAK 5−PIN
(Pb−Free)
2
CS8182YDPSR5
D PAK 5−PIN
750 / Tape & Reel
750 / Tape & Reel
2
CS8182YDPSR5G
D PAK 5−PIN
(Pb−Free)
CS8182DTG
DPAK 5L
(Pb−Free)
50 Units / Rail
CS8182DTRKG
DPAK 5L
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
CS8182
PACKAGE DIMENSIONS
SOIC−8
DF SUFFIX
CASE 751−07
ISSUE AG
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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10
CS8182
PACKAGE DIMENSIONS
D2PAK−5
DP SUFFIX
CASE 936AC−01
ISSUE O
A
TERMINAL 6
NOTES:
U
E
1. DIMENSIONS AND TOLERANCING PER
ANSI Y14.5M, 1982.
K
B
2. CONTROLLING DIMENSION: INCH.
3. PACKAGE OUTLINE EXCLUSIVE OF
MOLD FLASH AND METAL BURR.
4. PACKAGE OUTLINE INCLUSIVE OF
PLATING THICKNESS.
5. FOOT LENGTH MEASURED AT
INTERCEPT POINT BETWEEN DATUM A
AND LEAD SURFACE.
S
V
M
H
L
P
W
INCHES
MILLIMETERS
DIM
A
B
C
D
E
MIN
MAX
0.406
0.340
0.180
0.036
0.055
MIN
10.05
8.38
4.31
0.66
1.14
MAX
10.31
8.64
4.57
0.91
1.40
0.396
0.330
0.170
0.026
0.045
G
N
R
D
G
H
K
L
M
N
P
R
S
U
V
0.067 REF
1.70 REF
0.580
0.620
0.066
0.010
0.108
0.023
0.110
8
14.73
15.75
1.68
0.25
2.74
0.58
2.79
8
−A−
0.055
0.000
0.098
0.017
0.090
0
1.40
0.00
2.49
0.43
2.29
0
C
_
_
_
_
0.095
0.105
2.41
2.67
0.30 REF
7.62 REF
7.75 REF
0.25
0.305 REF
0.010
W
http://onsemi.com
11
CS8182
PACKAGE DIMENSIONS
DPAK−5
DT SUFFIX
CASE 175AA−01
ISSUE A
NOTES:
SEATING
PLANE
−T−
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
C
B
R
2. CONTROLLING DIMENSION: INCH.
E
V
INCHES
DIM MIN MAX
MILLIMETERS
R1
MIN
5.97
6.35
2.19
0.51
0.46
0.61
MAX
6.22
6.73
2.38
0.71
0.58
0.81
A
B
C
D
E
F
G
H
J
0.235 0.245
0.250 0.265
0.086 0.094
0.020 0.028
0.018 0.023
0.024 0.032
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.045 BSC
Z
A
K
S
1 2 3 4
5
U
4.56 BSC
0.87
0.46
2.60
1.01
0.58
2.89
K
L
F
1.14 BSC
J
R
0.170 0.190
4.32
4.70
0.63
0.51
0.89
3.93
4.83
5.33
1.01
−−−
1.27
4.32
L
H
R1 0.185 0.210
S
U
V
Z
0.025 0.040
0.020 −−−
0.035 0.050
0.155 0.170
D 5 PL
M
G
0.13 (0.005)
T
SOLDERING FOOTPRINT*
6.4
0.252
2.2
0.086
0.34
0.013
5.8
0.228
5.36
0.217
10.6
0.417
0.8
0.031
mm
inches
ǒ
Ǔ
SCALE 4:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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CS8182/D
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