AD876JR-8 [ROCHESTER]
1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28, SOIC-28;
| 型号： | AD876JR-8 |
| 厂家： | 
Rochester Electronics |
| 描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28, SOIC-28 光电二极管 转换器 |
| 文件： | 总17页 (文件大小：1018K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10-Bit 20 MSPS 160 mW
CMOS A/D Converter
a
AD876
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
CMOS 10-Bit 20 MSPS Sam pling A/ D Converter
Pin-Com patible 8-Bit Option
AV
DV
DD
DRV
CLK
DD
DD
Pow er Dissipation: 160 m W
+5 V Single Supply Operation
Differential Nonlinearity: 0.5 LSB
Guaranteed No Missing Codes
Pow er Dow n (Standby) Mode
Three-State Outputs
Digital I/ Os Com patible w ith +5 V or +3.3 V Logic
Adjustable Reference Input
Sm all Size: 28-Lead SOIC, 28-Lead SSOP, or 48-Lead
Thin Quad Flatpack (TQFP)
SHA
SHA
GAIN
SHA
GAIN
SHA
GAIN
STBY
A/D
AIN
D/A
A/D
D/A
A/D
D/A
A/D
THREE-
STATE
REFTF
REFTS
CORRECTION LOGIC
OUTPUT BUFFERS
REFBS
REFBF
(MSB)
D9
AD876
D0
(LSB)
AV
DV
DRV
SS
CML
SS
SS
P RO D UCT D ESCRIP TIO N
T he AD876 comes in a space saving 28-lead SOIC and 48-lead
thin quad flatpack (T QFP) and is specified over the commercial
(0°C to +70°C) temperature range.
T he AD876 is a CMOS, 160 mW, 10-bit, 20 MSPS analog-to-
digital converter (ADC). T he AD876 has an on-chip input
sample-and-hold amplifier. By implementing a multistage pipe-
lined architecture with output error correction logic, the AD876
offers accurate performance and guarantees no missing codes
over the full operating temperature range. Force and sense con-
nections to the reference inputs minimize external voltage drops.
P RO D UCT H IGH LIGH TS
Low P ower
T he AD876 at 160 mW consumes a fraction of the power of
presently available 8- or 10-bit, video speed converters. Power-
down mode and single-supply operation further enhance its
desirability in low power, battery operated applications such
as electronic still cameras, camcorders and communication
systems.
T he AD876 can be placed into a standby mode of operation
reducing the power below 50 mW. T he AD876’s digital I/O
interfaces to either +5 V or +3.3 V logic. Digital output pins
can be placed in a high impedance state; the format of the out-
put is straight binary coding.
Ver y Sm all P ackage
T he AD876 comes in a 28-lead SOIC, 28-lead SSOP, and 48-
lead surface mount, thin quad flat package. T he T QFP package
is ideal for very tight, low headroom designs.
T he AD876’s speed, resolution and single-supply operation
ideally suit a variety of applications in video, multimedia, imag-
ing, high speed data acquisition and communications. T he
AD876’s low power and single-supply operation satisfy require-
ments for high speed portable applications. Its speed and reso-
lution ideally suit charge coupled device (CCD) input systems
such as color scanners, digital copiers, electronic still cameras
and camcorders.
D igital I/O Functionality
T he AD876 offers three-state output control.
P in Com patible Upgr ade P ath
T he AD876 offers the option of laying out designs for eight
bits and migrating to 10-bit resolution if prototype results
warrant.
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1998
(TMIN to TMAX with AV = +5.0 V, DV = +5.0 V, DRV = +3.3 V, VREFB = +4.0 V, V =
REFB
DD
DD
DD
+2.0 V, fCLOCK = 20 MSPS, unless otherwise noted)
AD876–SPECIFICATIONS
AD 876JR-8
AD 876
Typ
P aram eter
Min
Typ
Max
Min
Max
Units
RESOLUT ION
8
10
Bits
DC ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
No Missing Codes
Offset Error
±0.3
±0.1
GUARANT EED
±1.0
±0.75
±1.0
±0.5
GUARANT EED
LSB
LSB
±1
0.1
0.1
0.4
0.2
% FSR
% FSR
Gain Error
ANALOG INPUT
Input Range
2
2
V p-p
pF
Input Capacitance
5.0
5.0
REFERENCE INPUT
Reference T op Voltage
Reference Bottom Voltage
Reference Input Resistance
Reference Input Current
Reference T op Offset
3.5
1.6
4.0
2.0
250
8.0
35
4.5
2.5
3.5
1.6
4.0
2.0
250
8.0
35
4.5
2.5
V
V
Ω
mA
mV
mV
Reference Bottom Offset
35
35
DYNAMIC PERFORMANCE
Effective Number of Bits
fIN = 1 MHz
fIN = 3.58 MHz
fIN = 10 MHz
Signal-to-Noise and Distortion (S/N+D) Ratio
fIN = 1 MHz
fIN = 3.58 MHz
7.8
7.8
7.5
9.0
9.0
8.2
Bits
Bits
Bits
7.4
46
8.2
51
49
49
47
56
56
51
dB
dB
dB
fIN = 10 MHz
T otal Harmonic Distortion (T HD)
fIN =1 MHz
fIN = 3.58 MHz
–62
–62
–60
–65
150
0.5
1
–62
–62
–60
–65
150
0.5
1
dB
dB
dB
dB
MHz
Degree
%
–56
–56
fIN =10 MHz
Spurious Free Dynamic Range2
Full Power Bandwidth
Differential Phase
Differential Gain
POWER SUPPLIES
Operating Voltage
1
AVDD
+4.5
+4.5
+3.0
+5.25
+5.25
+5.25
+4.5
+4.5
+3.0
+5.25
+5.25
+5.25
Volts
Volts
Volts
1
DVDD
DRVDD
Operating Current
IAVDD
IDVDD
IDRVDD
20
12
0.1
25
16
1
20
12
0.1
25
16
1
mA
mA
mA
POWER CONSUMPT ION
160
190
160
190
mW
T EMPERAT URE RANGE
Specified
0
+70
0
+70
°C
NOT ES
1AVDD and DVDD must be within 0.5 V of each other to maintain specified performance levels.
23.58 MHz Input Frequency.
Specifications subject to change without notice. See Definition of Specifications for additional information.
–2–
REV. B
AD876
MIN to TMAX with AV = +5.0 V, DV = +5.0 V, DRV = +3.3 V, VREFT = +4.0 V, VREFB = +2.0 V,
DIGITAL SPECIFICATIONS f(TCLOCK = 20 MSPS, C = 20 pF unless otherwise noted)
DD
DD
DD
L
AD 876
Typ
P aram eter
Sym bol
D RVD D
Min
Max
Units
LOGIC INPUT
High Level Input Voltage
VIH
3.0
5.0
5.25
3.0
5.0
5.25
5.0
5.0
5.0
2.4
4.0
4.2
V
V
V
V
V
V
µA
µA
µA
pF
Low Level Input Voltage
VIL
0.6
1.0
1.05
+10
+50
+10
High Level Input Current
Low Level Input Current
Low Level Input Current (CLK Only)
Input Capacitance
IIH
IIL
IIL
–10
–50
–10
CIN
5
LOGIC OUT PUT S
High Level Output Voltage
(IOH = 50 µA)
VOH
3.0
5.0
5.0
2.4
3.8
2.4
V
V
V
(IOH = 0.5 mA)
Low Level Output Voltage
(IOL = 50 µA)
VOL
3.6
0.7
V
5.25
5.25
1.05
0.4
V
V
(IOL = 0.6 mA)
Output Capacitance
Output Leakage Current
COUT
IOZ
5
pF
µA
–10
10
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Sym bol
Min
Typ
Max
Units
Maximum Conversion Rate1
Clock Period
Clock High
Clock Low
Output Delay
20
MHz
ns
ns
ns
tC
50
25
25
20
tCH
tCL
tOD
23
23
10
ns
Pipeline Delay (Latency)
Aperture Delay T ime
Aperture Jitter
3.5
Clock Cycles
ns
ps
4
22
NOT E
1Conversion rate is operational down to 10 kHz without degradation in specified performance.
SAMPLE N
SAMPLE N+1 SAMPLE N+2
AIN
tCH tCL
CLK
tOD
tC
OUT
DATA N-4
DATA N-3
DATA N-2
DATA N-1
DATA N
Figure 1. Tim ing Diagram
REV. B
–3–
AD876
P IN FUNCTIO N D ESCRIP TIO NS
SO IC
TQFP
Sym bol
P in No.
P in No.
Type
Nam e and Function
D0 (LSB)
D1–D4
3
1
DO
DO
Least Significant Bit.
Data Bits 1 through 4.
Data Bits 5 through 8.
Most Significant Bit.
T HREE-ST AT E = LOW
or N/C
4–7
8–11
12
2–5
8–11
12
D5–D8
D9 (MSB)
T HREE-
ST AT E
DO
DI
16
23
T HREE-ST AT E = HIGH
Normal Operating Mode
ST BY = LOW or N/C
Normal Operating Mode
Clock Input.
H igh Impedance Outputs
ST BY = HIGH
Standby Mode
ST BY
17
24
DI
CLK
15
22
DI
AO
AI
AI
AI
AI
AI
P
CML
26
38
Bypass Pin for an Internal Bias Point.
Reference T op Force.
REFT F
REFBF
REFT S
REFBS
AIN
22
30
24
34
Reference Bottom Force.
Reference T op Sense.
21
29
25
35
Reference Bottom Sense.
Analog Input.
27
39
AVDD
28
42
+5 V Analog Supply.
AVSS
1
44
P
Analog Ground.
DVDD
DVSS
18
26
P
+5 V Digital Supply.
14, 19, 20
2
17, 27, 28
45
P
Digital Ground.
DRVDD
P
+3.3 V/+5 V Digital Supply. Supply for digital
input and output buffers.
+3.3 V/+5 V Digital Ground. Ground for digital
input and output buffers.
DRVSS
13
16
P
T ype: AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Output; P = Power.
P IN CO NFIGURATIO NS
SO IC/SSO P
TQFP
AV
1
2
3
4
5
28
AV
DD
SS
48 47 46 45 44 43 42
39 38 37
41 40
DRV
27 AIN
DD
26
25
CML
36
35
34
33
32
31
30
29
28
27
26
25
1
2
D0
D1
D2
D3
D4
*D0
*D1
D2
REFBS
REFBS
REFBF
24 REFBF
3
23
D3
D4
D5
D6
6
7
8
4
NC
AD876
TOP VIEW
REFTF
REFTS
22
21
5
AD876
(Not to Scale)
6
TOP VIEW
20 DV
19 DV
18 DV
9
7
SS
SS
DD
(Not to Scale)
REFTF
REFTS
D7 10
8
D5
D6
D7
D8
D9
D8
D9
11
12
13
14
9
DV
SS
17 STBY
10
11
12
DV
SS
DRV
THREE-STATE
16
15
SS
SS
DV
DD
DV
CLK
13 14 15 16 17 18 19 20 21 22 23 24
*
PINS D0 AND D1 ARE LEFT OPEN
FOR THE AD876JR-8
NC = NO CONNECT
–4–
REV. B
AD876
ABSO LUTE MAXIMUM RATINGS*
O RD ERING GUID E
P aram eter
With Respect to Min
Max Units
Tem perature
P ackage
P ackage
Model
Range
D escription
O ptions
AVDD
DVDD, DRVDD
AVSS
AVSS
–0.5
–0.5
–0.5
–0.5
+6.5 Volts
+6.5 Volts
+0.5 Volts
+6.5 Volts
DVSS, DRVSS
DVSS, DRVSS
AVSS
AD876JR
AD876JST -Reel 0°C to +70°C
0°C to +70°C
28-Lead SOIC
48-Lead T QFP
(Tape and Reel 13")
28-Lead SOIC
R-28
ST -48
AIN
REFT S, REFT F
REFBS, REFBF
Digital Inputs, CLK
Junction T emperature
Storage T emperature
Lead T emperature
(10 sec)
AD876JR-8
AD876AR
AD876ARS
AD876JRS
AD876JRS-8
0°C to +70°C
–40°C to +85°C 28-Lead SOIC
–40°C to +85°C 28-Lead SSOP
0°C to +70°C
0°C to +70°C
R-28
R-28
RS-28
RS-28
RS-28
AVSS
DVSS, DRVSS
–0.5
–0.5
+6.5 Volts
+6.5 Volts
+150 °C
28-Lead SSOP
28-Lead SSOP
–65
+150 °C
+300 °C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
DV
DD
DV
DD
DRV
DD
DRV
DD
DV
DRV
DD
DD
DV
SS
DRV
SS
DV
SS
DV
SS
DRV
SS
DRV
SS
DV
SS
a) D0–D9
b) Three-State, Standby
c) CLK
AV
DD
REFTF
REFTS
AV
AV
SS
AV
DD
AV
DD
INTERNAL
REFERENCE
VOLTAGE
SS
AV
SS
AV
AV
DD
DD
d) AIN
INTERNAL
REFERENCE
VOLTAGE
REFBS
REFBF
AV
SS
AV
SS
Figure 2. Equivalent Circuits
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD876 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–5–
–Typical Performance Characteristics
AD876
1
0
–10
–20
–30
–40
–50
0.5
0
THD
2ND
–60
–70
–80
–90
–0.5
–1
3RD
0
64 128 192 256 320 384 448 512 576 640 704 768 832 896 960
CODE OFFSET
10
1
FREQUENCY – MHz
Figure 3. AD876 Typical DNL
Figure 6. THD vs. Input Frequency 2nd, 3rd Harm onics
2
60
0
–2
–4
55
50
45
40
35
30
–6
–8
–10
1
10
100
FREQUENCY – MHz
1000
5
10
15
20
25
30
CLOCK FREQUENCY – MHz
Figure 4. Full Power Bandwidth
Figure 7. SINAD vs. CLK Frequency (AIN = –0.5 dB)
180
170
160
60
55
50
150
140
130
120
45
40
35
30
110
100
0
5
10
15
20
25
0
1
2
10
10
10
CLOCK FREQUENCY – MHz
INPUT FREQUENCY – MHz
Figure 8. Power Consum ption vs. Sam ple Rate
Figure 5. SINAD vs. Input Frequency
(fCLK = 20 MSPS, AIN = –0.5 dB)
–6–
REV. B
AD876
1
P IP ELINE D ELAY (LATENCY)
T he number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided every clock cycle.
HARMONICS (dBc)
2ND –68.02
6TH –77.74
7TH –75.62
8TH –75.98
9TH –81.20
3RD –72.85
4TH –70.68
5TH –78.09
REFERENCE TO P /BO TTO M O FFSET
THD = –64.12
Resistance between the reference input and comparator input
tap points causes offset errors. T hese errors can be nulled out
by using the force-sense connection as shown in the Reference
Input section.
SNR = 48.73
SINAD = 48.61
SFDR = –68.02
2
4
3
6
7
8
5
9
TH EO RY O F O P ERATIO N
T he AD876 implements a pipelined multistage architecture to
achieve high sample rate with low power. T he AD876 distrib-
utes the conversion over several smaller A/D subblocks, refining
the conversion with progressively higher accuracy as it passes
the results from stage to stage. As a consequence of the distrib-
uted conversion, the AD876 requires a small fraction of the 1023
comparators used in a traditional flash type A/D. A sample-and-
hold function within each of the stages permits the first stage to
operate on a new input sample while the second and third stages
operate on the two preceding samples.
Figure 9. AD876J R-8 Typical FFT (fIN = 3.58 MHz,
AIN = –0.5 dB, fCLOCK = 20 MSPS)
1
HARMONICS (dBc)
2ND –68.91
3RD –73.92
4TH –68.67
5TH –73.26
6TH –80.55
7TH –82.02
8TH –81.02
9TH –88.94
THD = –64.24
SNR = 55.71
AP P LYING TH E AD 876
SINAD = 55.14
SFDR = –68.67
D RIVING TH E ANALO G INP UT
Figure 11 shows the equivalent analog input of the AD876, a
sample-and-hold amplifier (SHA). Bringing CLK to a logic low
level closes Switches 1 and 2 and opens Switch 3. T he input
source connected to AIN must charge capacitor CH during this
time. When CLK transitions from logic “low” to logic “high,”
Switch 1 opens first, placing the SHA in hold mode. Switch 2
opens subsequently. Switch 3 then closes, connects the feed-
back loop around the op amp, and forces the output of the op
amp to equal the voltage stored on CH. When CLK transitions
from logic “high” to logic “low”, Switch 3 opens first. Switch 2
closes and reconnects the input to CH. Finally, Switch 1 closes
and places the SHA in track mode.
2
4
5
3
6
7
8
9
Figure 10. AD876 Typical FFT (fIN = 3.58 MHz, AIN = –0.5 dB,
CLOCK = 20 MSPS)
f
D EFINITIO NS O F SP ECIFICATIO NS
INTEGRAL NO NLINEARITY (INL)
Integral nonlinearity refers to the deviation of each individual
code from a line drawn from “zero” through “full scale”. T he
point used as “zero” occurs 1/2 LSB before the first code transi-
tion. “Full scale” is defined as a level 1 1/2 LSB beyond the last
code transition. T he deviation is measured from the center of
each particular code to the true straight line.
T he structure of the input SHA places certain requirements on
the input drive source. T he combination of the pin capacitance,
CP, and the hold capacitance, CH, is typically less than 5 pF.
T he input source must be able to charge or discharge this ca-
pacitance to 10-bit accuracy in one half of a clock cycle. When
the SHA goes into track mode, the input source must charge or
discharge capacitor CH from the voltage already stored on CH
(the previously captured sample) to the new voltage. In the
worst case, a full-scale voltage step on the input, the input
source must provide the charging current through the RON (50 Ω)
of Switch 2 and quickly settle (within 1/2 CLK period). T his
situation corresponds to driving a low input impedance. On the
other hand, when the source voltage equals the value previously
stored on CH , the hold capacitor requires no input current and
the equivalent input impedance is extremely high.
D IFFERENTIAL NO NLINEARITY (D NL, NO MISSING
CO D ES)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. It is often
specified in terms of the resolution for which no missing codes
(NMC) are guaranteed.
O FFSET ERRO R
T he first transition should occur at a level 1/2 LSB above
“zero.” Offset is defined as the deviation of the actual first code
transition from that point.
Adding series resistance between the output of the source and
the AIN pin reduces the drive requirements placed on the
source. Figure 12 shows this configuration. T he bandwidth of
the particular application limits the size of this resistor. T o
maintain the performance outlined in the data sheet specifica-
tions, the resistor should be limited to 200 Ω or less. For appli-
cations with signal bandwidths less than 10 MHz, the user may
increase the size of the series resistor proportionally. Alterna-
tively, adding a shunt capacitance between the AIN pin and
GAIN ERRO R
T he first code transition should occur for an analog value 1/2 LSB
above nominal negative full scale. T he last transition should
occur for an analog value 1 1/2 LSB below the nominal positive
full scale. Gain error is the deviation of the actual difference
between first and last code transitions and the ideal difference
between the first and last code transitions.
REV. B
–7–
AD876
analog ground can lower the ac source impedance. T he value
of this capacitance will depend on the source resistance and the
required signal bandwidth.
20 kHz. At a sample clock frequency of 20 MHz, the dc bias
current at 3 V dc is approximately 30 µA. If we choose R2 equal
to 1 kΩ and R1 equal to 50 Ω, the parallel capacitance should
be a minimum of 0.008 µF to avoid attenuating signals close to
20 kHz. Note that the bias current will cause a 31.5 mV offset
from the 3 V bias.
T he input span of the AD876 is a function of the reference
voltages. For more information regarding the input range, see
the DRIVING T HE REFERENCE T ERMINALS section of
the data sheet.
In systems that must use dc-coupling, use an op amp to level-
shift a ground-referenced signal to comply with the input
requirements of the AD876. Figure 14 shows an AD817
configured in inverting mode with ac signal gain of –1. T he dc
voltage at the noninverting input of the op amp controls the
amount of dc level shifting. A resistive voltage divider attenu-
ates the REFBF signal. T he op amp then multiplies the attenu-
ated signal by 2. In the case where REFBF = 1.6 V, the dc
output level will be 2.6 V. T he AD817 is a low cost, fast settling,
single supply op amp with a G = –1 bandwidth of 29 MHz. T he
AD818 is similar to the AD817 but has a 50 MHz bandwidth.
Other appropriate op amps include the AD8011, AD812 (a dual),
and the AD8001.
3
AD876
1
AIN
2
C
H
C
P
Figure 11. AD876 Equivalent Input Structure
< Ϸ 200⍀
AIN
V
S
R = 4.99k⍀
f
+V
CC
0.1F
Figure 12. Sim ple AD876 Drive Requirem ents
AD876
AIN
NC
In many cases, particularly in single-supply operation, ac-
coupling offers a convenient way of biasing the analog input
signal at the proper signal range. Figure 13 shows a typical
configuration for ac-coupling the analog input signal to the
AD876. Maintaining the specifications outlined in the data
sheet requires careful selection of the component values. T he
most important concern is the f-3 dB high-pass corner that is a
function of R2, and the parallel combination of C1 and C2.
T he f-3 dB point can be approximated by the equation
2V p-p
REFBF
0Vdc
R
= 4.99k⍀
IN
AD817 OR
AD818
3k⍀
14.7k⍀
NC
Figure 14. Bipolar Level Shift
An integrated difference amplifier such as the AD830 is an
alternate means of providing dc level shifting. T he AD830
provides a great deal of flexibility with control over offset and
gain. Figure 15 shows the AD830 precisely level-shifting a
unipolar, ground-referenced signal. T he reference voltage,
REFBS, determines the amount of level-shifting. T he ac gain
is 1. T he AD830 offers the advantages of high CMRR, precise
gain, offset, and high-impedance inputs when compared with a
discrete implementation. For more information regarding the
AD830, see the AD830 data sheet.
1
f −3 dB
=
[2 × π ×( R2) Ceq]
where Ceq is the parallel combination of C1 and C2. Note that
C1 is typically a large electrolytic or tantalum capacitor that
becomes inductive at high frequencies. Adding a small ceramic
or polystyrene capacitor on the order of 0.01 µF that does not
become inductive until negligibly higher frequencies maintains
a low impedance over a wide frequency range.
+12V
AD876
0.1
R1
C1
C2
2V
V
+2V
B
V
AIN
IN
0
AD876
R2
V
V
I
B
B
AIN
AD830
–12V
3V
BIAS
V
B
0.1
Figure 13. AC-Coupled Inputs
T here are additional considerations when choosing the resistor
values. T he ac-coupling capacitors integrate the switching
transients present at the input of the AD876 and cause a net dc
bias current, IB, to flow into the input. T he magnitude of this
bias current increases with increasing dc signal level and also
increases with sample frequency. T his bias current will result in
an offset error of (R1 + R2) × IB. If it is necessary to compen-
sate this error, consider making R2 negligibly small or modify-
ing VBIAS to account for the resultant offset.
REFBS
Figure 15. Level Shifting with the AD830
REFERENCE INP UT D RIVING TH E REFERENCE
TERMINALS
T he AD876 requires an external reference on pins REFT F and
REFBF. T he AD876 provides reference sense pins, REFT S
and REFBS, to minimize voltage drops caused by external and
internal wiring resistance. A resistor ladder, nominally 250 Ω,
connects pins REFT F and REFBF.
As an example, assume that the input to the AD876 must have
a dc bias of 3 V and the minimum expected signal frequency is
–8–
REV. B
AD876
ance changes associated with the reference inputs. T he simpli-
fied diagram of Figure 16 shows that the reference pins connect
to a capacitor for one-half of the clock period. T he size of the
capacitor is a function of the analog input voltage.
Figure 16 shows the equivalent input structure for the AD876
reference pins. T here is approximately 5 Ω of resistance between
both the REFT F and REFBT pins and the reference ladder. If
the force-sense connections are not used, the voltage drop
across the 5 Ω resistors will result in a reduced voltage appear-
ing across the ladder resistance. T his reduces the input span of
the converter. Applying a slightly larger span between the REFT F
and REFBF pins compensates this error. Note that the tem-
perature coefficients of the 5 Ω resistors are 1350 ppm. T he
user should consider the effects of temperature when not using
a force-sense reference configuration.
T he external reference must be able to maintain a low imped-
ance over all frequencies of interest in order to provide the charge
required by the capacitance. By supplying the requisite charge,
the reference voltages will be relatively constant and perfor-
mance will not degrade. For some reference configurations,
voltage transients will be present on the reference lines; this
is particularly true during the falling edge of CLK. It is impor-
tant that the reference recovers from the transients and settles to
the desired level of accuracy prior to the rising edges of CLK.
AD876
5⍀
REFTF
T here are several reference configurations suitable for the
AD876 depending on the application, desired level of accuracy,
and cost trade-offs. T he simplest configuration, shown in Fig-
ure 18, utilizes a resistor string to generate the reference volt-
ages from the converter’s analog power supply. T he 0.1 µF
bypass capacitors effectively reduce high-frequency transients.
T he 10 µF capacitors act to reduce the impedances at the
REFT F and REFBF pins at lower frequencies. As input fre-
quencies approach dc, the capacitors become ineffective, and
small voltage deviations will appear across the biasing resistors.
T his application can maintain 10-bit accuracy for input frequen-
cies above approximately 200 Hz. 8-bit applications can use this
circuit for input frequencies above approximately 50 Hz.
CLK
REFTS
V1
R
LADDER
C (V
)
DACS
IN
250⍀
REFBS
REFBF
V2
CLK
5⍀
Figure 16. AD876 Equivalent Reference Structure
Do not connect the REFT S and REFBS pins in configurations
that do not use a force-sense reference. Connecting the force
and sense lines together allows current to flow in the sense lines.
Any current allowed to flow through these lines must be negligi-
bly small. Current flow causes voltage drops across the resis-
tance in the sense lines. Because the internal D/As of the
AD876 tap different points along the sense lines, each D/A
would receive a slightly different reference voltage if current
were flowing in these wires. T o avoid this undesirable condition,
leave the sense lines unconnected. Any current allowed to flow
through these lines must be negligibly small (<100 µA).
AD876
REFTS
NC
140⍀ (؎1%)
4V
REFTF
+5V
0.1F
10F
10F
250⍀
(؎15%)
10F
T he voltage drop across the internal resistor ladder determines
the input span of the AD876. T he driving voltages required at
the V1 and V2 points are respectively +4 V and +2 V. Calculate
the full-scale input span from the equation
250⍀ (؎1%)
2V
REFBF
REFBS
0.1F
NC
Input Span (V ) = REFTS – REFBS
NC = NO CONNECT
T his results in a full-scale input span of approximately +2 V
when REFT S = +4 V and REFBS = +2 V In order to maintain
the requisite 2 V drop across the internal ladder, the external
reference must be capable of providing approximately 8.0 mA.
Figure 18. Low Cost Reference Circuit
T his reference configuration provides the lowest cost but has
several disadvantages. T hese disadvantages include poor dc
power supply rejection and poor accuracy due to the variability
of the internal and external resistors.
T he user has flexibility in determining both the full-scale span of
the analog input and where to center this voltage. Figure 17
shows the range over which the AD876 can operate without
degrading the typical performance.
T he AD876 offers force-sense reference connections to elimi-
nate the voltage drops associated with the internal connections
to the reference ladder. Figure 19 shows a suggested circuit
using an AD826 dual, high speed op amp. T his configuration
uses 3.6 V and 1.6 V reference voltages for REFT and REFB,
respectively. T he connections shown in Figure 19 configure the
op amps as voltage followers.
(2.5, 4.5)
(2.5, 3.5)
2.5
(1.6, 4.5)
4.5
4.0
3.5
3.0
2.5
(1.6, 3.5)
1.0
1.5
2.0
3.0
REFBF, REFBS
Figure 17. AD876 Reference Ranges
While the previous issues address the dc aspects of the AD876
reference, the user must also be aware of the dynamic imped-
REV. B
–9–
AD876
common ground, are effectively removed by the AD876’s high
common-mode rejection.
C3
0.1F
AD876
High frequency noise sources, VN1 and VN2, are shunted to
ground by decoupling capacitors. Any voltage drops between
the analog input ground and the reference bypassing points will
be treated as input signals by the converter via the reference
inputs. Consequently, the reference decoupling capacitors
should be connected to the same analog ground point used to
define the analog input voltage. (For further suggestions, see
the “Grounding and Layout Rules” section of the data sheet.)
REFTS
+5V
8
C4
0.1F
6
5
7
REFTF
REFT
1/2
C2
0.1F
AD826
REFBS
REFBF
C5
0.1F
2
3
6
C1
0.1F
REFB
4
1/2
AD826
V
4V
N1
REFTF
REFBF
AD876
Figure 19. Kelvin Connected Reference Using the AD826
By connecting the op amp feedback through the sense connec-
tions of the AD876, the outputs of the op amps automatically
adjust to compensate for the voltage drops that occur within
the converter. T he AD826 has the advantage of being able to
maintain stability while driving unlimited capacitive loads. As a
result, 0.1 µF capacitors C1, C2, and C3 can connect directly
to the outputs of the op amps. T hese decoupling capacitors
reduce high frequency transients. Capacitors C4 and C5 shunt
across the internal resistors of the force sense connections and
prevent instability.
V
2V
N2
AIN
Figure 21. Recom m ended Bypassing for the Reference
Inputs
CLO CK INP UT
T his configuration provides excellent performance and a mini-
mal number of components. T he circuit also offers the advan-
tage of operating from a single +5 V supply. While alternative
op amps may also be suitable, consider the stability of these op
amps while driving capacitive loads.
T he AD876 clock input is buffered internally with an inverter
powered from the DRVDD pin. T his feature allows the AD876
to accommodate either +5 V or +3.3 V CMOS logic input sig-
nal swings with the input threshold for the CLK pin nominally
at DRVDD /2.
T he circuit shown in Figure 20 allows a wider selection of op
amps when compared with the previous configuration. An
T he AD876’s pipelined architecture operates on both rising and
falling edges of the input clock. T o minimize duty cycle varia-
tions the recommended logic family to drive the clock input is
high speed or advanced CMOS (HC/HCT , AC/ACT ) logic.
CMOS logic provides both symmetrical voltage threshold levels
and sufficient rise and fall times to support 20 MSPS operation.
T he AD876 is designed to support a conversion rate of 20 MSPS;
running the part at slightly faster clock rates may be possible,
although at reduced performance levels. Conversely, some
slight performance improvements might be realized by clocking
the AD876 at slower clock rates.
AD876
20k⍀
REFTS
47nF
22F
10⍀
REFTF
REFT
1/2
OP-295
10F
20k⍀
0.1F
REFBS
REFBF
47nF
T he power dissipated by the correction logic and output buffers
is largely proportional to the clock frequency; running at reduced
clock rates provides a reduction in power consumption. Figure
8 illustrates this trade-off.
10⍀
10F
REFB
1/2
OP-295
0.1F
D IGITAL INP UTS AND O UTP UTS
Figure 20. Kelvin Connected Reference Using the OP295
Each of the AD876 digital control inputs, T HREE-ST AT E and
ST BY, has an input buffer powered from the DRVDD supply
pins. With DRVDD set to +5 V, all digital inputs readily inter-
face with +5 V CMOS logic. For interfacing with lower voltage
CMOS logic, DRVDD can be set to 3.3 V, effectively lowering
the nominal input threshold of all digital inputs to 3.3 V/2 =
1.65 V.
OP295 dual, single-supply op amp provides stable 3.6 V and
1.6 V reference voltages. T he AD822 dual op amp is also suit-
able for single-supply applications. Each half of the OP295 is
compensated to drive the 10 µF and 0.1 µF decoupling capaci-
tors at the REFT F and REFBF pins and maintain stability.
Like any high resolution converter, the layout and decoupling of
the reference is critical. T he actual voltage digitized by the
AD876 is relative to the reference voltages. In Figure 21, for
example, the reference return and the bypass capacitors are
connected to the shield of the incoming analog signal. Distur-
bances in the ground of the analog input, that will be common-
mode to the REFT , REFB, and AIN pins because of the
T he format of the digital output is straight binary. T able I shows
the output format for the case where REFT S = 4 V and REFBS
= 2 V.
–10–
REV. B
AD876
Table I. O utput D ata Form at
For DRVDD = 5 V, the AD876 output signal swing is compat-
ible with both high speed CMOS and T T L logic families. For
T T L, the AD876 on-chip, output drivers were designed to
support several of the high speed T T L families (F, AS, S). For
applications where the clock rate is below 20 MSPS, other T T L
families may be appropriate. For interfacing with lower voltage
CMOS logic, the AD876 sustains 20 MSPS operation with
DRVDD = 3.3 V. In all cases, check your logic family data
sheets for compatibility with the AD876 Digital Specification
table.
Approx.
AIN (V)
TH REE- D ATA
STATE D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
>4
4
0
0
0
0
0
1
1
1
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
3
2
<2
X
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
TH REE-STATE O UTP UTS
A low power mode feature is provided such that for ST BY =
HIGH and the clock disabled, the static power of the AD876
will drop below 50 mW.
T he digital outputs of the AD876 can be placed in a high im-
pedance state by setting the T HREE-ST AT E pin to HIGH.
T his feature is provided to facilitate in-circuit testing or
evaluation. Note that this function is not intended for enabling/
disabling the ADC outputs from a bus at 20 MSPS. Also, to
avoid corruption of the sampled analog signal during conversion
(3.5 clock cycles), it is highly recommended that the AD876
outputs be enabled on the bus prior to the first sampling. For
the purpose of budgetary timing, the maximum access and float
delay times (tDD, tHL shown in Figure 15) for the AD876 are
150 ns.
GRO UND ING AND LAYO UT RULES
As is the case for any high performance device, proper ground-
ing and layout techniques are essential in achieving optimal
performance. T he analog and digital grounds on the AD876
have been separated to optimize the management of return
currents in a system. It is recommended that a printed circuit
board (PCB) of at least 4 layers employing a ground plane and
power planes be used with the AD876. T he use of ground and
power planes offers distinct advantages:
THREE-STATE
1. T he minimization of the loop area encompassed by a signal
and its return path.
tDD
tHL
D0–D9
2. T he minimization of the impedance associated with ground
and power paths.
HIGH IMPEDANCE
ACTIVE
3. T he inherent distributed capacitor formed by the power
plane, PCB insulation, and ground plane.
Figure 22. High-Im pedance Output Tim ing Diagram
T hese characteristics result in both a reduction of electro-
magnetic interference (EMI) and an overall improvement in
performance.
It is important to design a layout which prevents noise from
coupling onto the input signal. Digital signals should not be run
in parallel with the input signal traces and should be routed
away from the input circuitry. Separate analog and digital
grounds should be joined together directly under the AD876. A
solid ground plane under the AD876 is also acceptable if the
power and ground return currents are managed carefully. A
general rule of thumb for mixed signal layouts dictates that the
return currents from digital circuitry should not pass through
critical analog circuitry. For further layout suggestions, see the
AD876 Evaluation Board data sheet.
D IGITAL O UTP UTS
Each of the on-chip buffers for the AD876 output bits (D0–D9)
is powered from the DRVDD supply pins, separate from AVDD or
DVDD. T he output drivers are sized to handle a variety of logic
families while minimizing the amount of glitch energy gener-
ated. In all cases, a fan-out of one is recommended to keep the
capacitive load on the output data bits below the specified 20 pF
level.
REV. B
–11–
AD876
TP3
TP4
1
2
U4
74F04
CLK_IN
TP1
U4
74F04
J1
4
3
3ST
VP5
STBY
VP6
+5VD
+5VD
R1
51⍀
C50
10F
+
JP4
JP1
JP2
U1
AD876
P1
P1
P1
P1
P1
1
3
5
7
9
P1
P1
P1
P1
2
4
6
8
U2
74ALS541
1
19
9
8
7
6
5
4
3
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
G1
D9
R2
*
CLK
DV
SS
11
G2
A7
A6
A5
A4
A3
A2
A1
A0
VP8
13
12
11
10
9
Y7
Y6
Y5
Y4
Y3
Y2
D8
D7
D6
D5
D4
D3
D2
D1
D0
3_STATE
STBY
R3*
R4*
R5*
R6*
12
13
14
15
16
DRV
C62
0.1F
SS
9
8
7
6
5
4
3
2
1
0
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
P1 10
P1 12
P1 14
P1 16
P1 18
P1 20
P1 22
P1 24
P1 26
P1 28
P1 30
P1 32
P1 34
P1 36
P1 38
P1 40
D5
D6
D7
D8
D9
DV
DD
5
6
7
8
9
P1 11
P1 13
P1 15
P1 17
P1 19
P1 21
P1 23
P1 25
P1 27
P1 29
P1 31
P1 33
P1 35
P1 37
P1 39
SUBST
NC
REFTS
VP3
Y1 17
Y0
R7*
18
REFTS
REFTF
NC
8
2
REFTS
REFTF
R8*
7
R9*
U3
6
REFBF
REFBS
CML
1
19
9
8
7
6
5
4
3
R10*
R11*
G1
G2
A7
A6
A5
A4
A3
A2
A1
A0
5
11
12
13
14
15
16
17
18
REFBF
REFBS
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
4
3
AIN
DRV
DD
D0
D1
D2
D3
D4
2
AV
DD
VP4
REFBS
AV
0
1
2
3
4
SS
1
C64
0.1F
REFTF
VP1
REFBF
VP2
R12*
2
74ALS541
C56
0.1F
C4
10F
+
+
+
C49
10F
C2
10F
+5VD
R16
1k⍀
R17
1.13k⍀
+5VA
*R2–R12 = 20⍀
C54
0.1F
DC_IN
R18
R14
1k⍀
100⍀
2
3 INT_CM
EXT_CM
TP18
JP5
1
AIN
J2
C1
0.1F
R15
51⍀
TP2
+
C3
47F
Figure 23. AD876 Evaluation Board Schem atic
–12–
REV. B
AD876
Figure 24. Silkscreen Layer, Com ponent Side PCXB Layout
Figure 25. Silkscreen Layer, Circuit Side PCB Layout
–13–
REV. B
AD876
Figure 26. Com ponent Side PCB Layout
Figure 27. Circuit Side PCB Layout
–14–
REV. B
AD876
Figure 28. Ground Layer PCB Layout
Figure 29. Power Layer PCB Layout
–15–
REV. B
AD876
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
R-28
28-Lead Wide Body (SO IC)
0.7125 (18.10)
0.6969 (17.70)
28
15
1
14
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
PIN 1
x 45°
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
ST-48
28-Lead P lastic Thin Quad Flatpack (TQFP )
0.059 +0.008 –0.004
(1.50 +0.2 –0.1)
0.354 ± 0.008 (9.00 ± 0.2) SQ
0.055 ± 0.002
(1.40 ± 0.05)
0.039 (1.00)
REF
0.02 ± 0.008
(0.5 ± 0.2)
36
25
37
24
SEATING
PLANE
0.276 ± 0.004
(7.0 ± 0.1)
SQ
TOP VIEW
(PINS DOWN)
48
13
0.004 ± 0.002
(0.1 ± 0.05)
1
12
0° MIN
(3.5° ± 3.5°)
0.02 ± 0.003 0.007 +0.003 –0.001
(0.50 ± 0.08) (0.18 +0.08 –0.03)
0.005 +0.002 –0.0008
(0.127 +0.05 –0.02)
RS-28
28-Lead Shrink Sm all O utline P ackage (SSO P )
0.407 (10.34)
0.397 (10.08)
28
15
14
1
0.07 (1.79)
0.078 (1.98)
PIN 1
0.066 (1.67)
0.068 (1.73)
0.03 (0.762)
8°
0°
0.0256
(0.65)
BSC
0.015 (0.38)
0.010 (0.25)
0.022 (0.558)
0.008 (0.203)
0.002 (0.050)
SEATING
PLANE
0.009 (0.229)
0.005 (0.127)
–16–
REV. B
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