AD7834AR_技术文档

LC²MOS

Quad 14-Bit DACs

AD7834/AD7835

FSYNC

into one via DIN, SCLK, and

. The AD7834 has five

FEATURES

dedicated package address pins, PA0 to PA4, that can be ꢂired

to AGND or ꢁ_CCto permit up to 39 AD7834s to be individually

addressed in a multipackage application.

Four 14-bit DACs in one package

AD7834—serial loading

AD7835—parallel 8-bit/14-bit loading

Voltage outputs

The AD7835 can accept either 14-bit parallel loading or double-

byte loading, ꢂhere right-justified data is loaded in one 8-bit

byte and one 6-bit byte. Data is loaded from the external bus

Power-on reset function

Maximum/minimum output voltage range of 8.192 V

Maximum output voltage span of 14 V

Common voltage reference inputs

User-assigned device addressing

Clear function to user-defined voltage

Surface-mount packages

WR CS

into one of the input latches under the control of the

,

BYSHF

, and DAC channel address pins, A0 to A9.

LDAC

With each device, the

signal is used to update all four

DAC outputs simultaneously, or individually, on reception of

CLR

neꢂ data. In addition, for each device, the asynchronous

AD7834—28-lead SOIC and PDIP

AD7835—44-lead MQFP and PLCC

input can be used to set all signal outputs, ꢁ_OUT1 to ꢁ_OUT4, to

the user-defined voltage level on the device sense ground pin,

DSG. On poꢂer-on, before the poꢂer supplies have stabilized,

internal circuitry holds the DAC output voltage levels to ꢂithin

9 ꢁ of the DSG potential. As the supplies stabilize, the DAC

APPLICATIONS

Process control

Automatic test equipment

General-purpose instrumentation

CLR

output levels move to the exact DSG potential (assuming

exercised).

is

GENERAL DESCRIPTION

The AD7834 is available in a 98-lead 0.3" SOIC package and a

98-lead 0.6" PDIP package, and the AD7835 is available in a

44-lead MQFP package and a 44-lead PLCC package.

The AD7834 and AD7835 contain four 14-bit DACs on one

monolithic chip. The AD7834 and AD7835 have output

voltages in the range 8.1ꢀ9 ꢁ ꢂith a maximum span of 14 ꢁ.

The AD7834 is a serial input device. Data is loaded in 16-bit

format from the external serial bus, MSB first after tꢂo leading 0s,

FUNCTIONAL BLOCK DIAGRAMS

V

(–)A

V

REF

V

(+)A

DSGA

REF

V

V (–)

V

REF

V

(+)

REF

CC

DD

SS

CC

DD

SS

AD7835

INPUT

REGISTER

1

INPUT

AD7834

DAC 1

DAC 2

DAC 1

DAC 2

REGISTER

1

LATCH

BYSHF

PAEN

×1

V

1

2

×1

V

1

2

OUT

14

DB13

DB0

INPUT

BUFFER

PA0

PA1

INPUT

REGISTER

2

INPUT

REGISTER

2

DAC 2

LATCH

DAC 2

LATCH

CONTROL

LOGIC

AND

ADDRESS

DECODE

V

WR

CS

OUT

PA2

PA3

PA4

INPUT

REGISTER

3

DAC 3

LATCH

INPUT

REGISTER

3

DAC 3

DAC 4

DAC 3

LATCH

DAC 3

DAC 4

×1

V

3

4

OUT

×1

V

3

4

OUT

A0

A1

A2

FSYNC

INPUT

REGISTER

4

ADDRESS

DECODE

DAC 4

LATCH

INPUT

REGISTER

4

DAC 4

LATCH

SERIAL-TO-

PARALLEL

CONVERTER

DIN

V

OUT

CLR

SCLK

CLR

DSGB

(+)B

AGND

DGND

V

(–)B

V

LDAC

AGND

DGND

LDAC

DSG

REF

Figure 1. AD7834

Figure 2. AD7835

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

AD7834/AD7835

TABLE OF CONTENTS

CLR

LDAC

Poꢂer-On ꢂith

Loꢂ,

High................................... 17

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagrams............................................................. 1

Revision History ............................................................................... 9

Specifications..................................................................................... 3

AC Performance Characteristics................................................ 5

Timing Specifications .................................................................. 6

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Typical Performance Characteristics ........................................... 11

Terminology .................................................................................... 13

Theory of Operation ...................................................................... 14

DAC Architecture....................................................................... 14

Data Loading—AD7834 Serial Input Device ......................... 14

Data Loading—AD7835 Parallel Loading Device ................. 14

Unipolar Configuration............................................................. 15

Bipolar Configuration................................................................ 16

Controlled Poꢂer-On of the Output Stage.................................. 17

LDAC

CLR

Loꢂ,

CLR

Loading the DAC and Using the

Input .......................... 17

DSG ꢁoltage Range.................................................................... 18

Poꢂer-On of the AD7834/AD7835.............................................. 1ꢀ

Microprocessor Interfacing........................................................... 90

AD7834 to 80C51 Interface ...................................................... 90

AD7834 to 68HC11 Interface................................................... 90

AD7834 to ADSP-9101 Interface ............................................. 90

AD7834 to DSP56000/DSP56001 Interface............................ 91

AD7834 to TMS39090/TMS390C95 Interface....................... 91

Interfacing the AD7835—16-Bit Interface.............................. 91

Interfacing the AD7835—8-Bit Interface................................ 99

Applications Information.............................................................. 93

Serial Interface to Multiple AD7834s ...................................... 93

Opto-Isolated Interface ............................................................. 93

Automated Test Equipment ...................................................... 93

Poꢂer Supply Bypassing and Grounding................................ 94

Outline Dimensions....................................................................... 95

Ordering Guide .......................................................................... 97

REVISION HISTORY

8/07—Rev. C to Rev. D

Changes to Table 5 ........................................................................... 7

Added Table 6.................................................................................... 7

Changes to Table 8............................................................................ ꢀ

Updated Outline Dimensions....................................................... 95

Changes to Ordering Guide .......................................................... 97

7/05—Rev. B to Rev. C

Updated Format..................................................................Universal

Changes to Figure 40...................................................................... 95

Changes to Ordering Guide .......................................................... 97

7/03—Rev. A to Rev. B

Revision 0: Initial Version

Rev. D | Page 2 of 28

AD7834/AD7835

SPECIFICATIONS

1

ꢁ_CC= 5 ꢁ 5ꢃ; ꢁ_DD= 15 ꢁ 5ꢃ; ꢁ_SS= −15 ꢁ 5ꢃ; AGND = DGND = 0 ꢁ; T_A= T_MINto T_MAX, unless otherꢂise noted.

Table 1.

Parameter

A

B

S

Unit

Test Conditions/Comments

ACCURACY

Resolution

14

Bits

Relative Accuracy

Differential Nonlinearity

Full-Scale Error

T_MINto T_MAX

Zero-Scale Error

Gain Error

±2

±±.ꢀ

±1

±±.ꢀ

±2

±±.ꢀ

LSB max

Guaranteed monotonic over temperature.

V_REF(+) = +7 V, V_REF(−) = −7 V.

±ꢁ

±4

±±.ꢁ

4

±ꢁ

±4

±±.ꢁ

4

±8

±ꢁ

±±.ꢁ

4

mV max

mV typ

ppm FSR/°C typ

V_REF(+) = +7 V, V_REF(−) = −7 V.

Gain Temperature

Coefficient²

2±

ꢁ±

2±

ꢁ±

2±

ꢁ±

ppm FSR/°C max

μV max

DC Crosstalk²

REFERENCE INPUTS

DC Input Resistance

Input Current

See the Terminology section. R_L= 1± kΩ.

Per input.

3±

±1

3±

±1

3±

±1

MΩ typ

μA max

V_REF(+) Range

V_REF(−) Range

V_REF(+) − V_REF(−)

±/8.1ꢀ2

−8.1ꢀ2/±

ꢁ/14

±/8.1ꢀ2

−8.1ꢀ2/±

7/14

±/8.1ꢀ2

−8.1ꢀ2/±

ꢁ/14

V min/max

For specified performance. Can go as low as

± V, but performance is not guaranteed.

DEVICE SENSE GROUND INPUTS

Input Current

±2

μA max

Per input. V_DSG= −2 V to +2 V.

DIGITAL INPUTS

V_INH, Input High Voltage

2.4

±.8

±1±

1±

2.4

±.8

±1±

1±

2.4

±.8

±1±

1±

V min

V_INL, Input Low Voltage

I_INH, Input Current

V max

μA max

pF max

C_IN, Input Capacitance

POWER REQUIREMENTS

V_CC

V_DD

V_SS

ꢁ.±

1ꢁ.±

−1ꢁ.±

ꢁ.±

1ꢁ.±

−1ꢁ.±

ꢁ.±

1ꢁ.±

−1ꢁ.±

V nom

±ꢁ5 for specified performance.

Power Supply Sensitivity

ΔFull Scale/ΔV_DD

ΔFull Scale/ΔV_SS

I_CC

11±

1±±

±.2

3

11±

1±±

±.2

3

11±

1±±

±.ꢁ

3

dB typ

mA max

V_INH= V_CC, V_INL= DGND.

AD7834: V_INH= 2.4 V min, V_INL= ±.8 V max.

AD783ꢁ: V_INH= 2.4 V min, V_INL= ±.8 V max.

AD7834: outputs unloaded.

AD783ꢁ: outputs unloaded.

Outputs unloaded.

6

I_DD

I_SS

13

1ꢁ

13

1ꢁ

13

1ꢁ

¹Temperature range for A, B, and C versions is −4±°C to +8ꢁ°C.

²Guaranteed by design.

Rev. D | Page 3 of 28

AD7834/AD7835

1

ꢁ_CC= 5 ꢁ 5ꢃ; ꢁ_DD= 19 ꢁ 5ꢃ; ꢁ_SS= −19 ꢁ 5ꢃ; AGND = DGND = 0 ꢁ; T_A= T_MINto T_MAX, unless otherꢂise noted.

Table 2.

Parameter

A

B

S

Unit

Test Conditions/Comments

ACCURACY

Resolution

14

Bits

Relative Accuracy

Differential Nonlinearity

Full-Scale Error

T_MINto T_MAX

Zero-Scale Error

Gain Error

Gain Temperature Coefficient²

±2

±±.ꢀ

±1

±±.ꢀ

±2

±±.ꢀ

LSB max

Guaranteed monotonic over temperature.

V_REF(+) = +ꢁ V, V_REF(−) = –ꢁ V.

±ꢁ

±4

±±.ꢁ

4

2±

ꢁ±

±ꢁ

±4

±±.ꢁ

4

2±

ꢁ±

±8

±ꢁ

±±.ꢁ

4

2±

ꢁ±

mV max

mV typ

ppm FSR/°C typ

ppm FSR/°C max

μV max

V_REF(+) = +ꢁ V, V_REF(−) = −ꢁ V.

DC Crosstalk²

REFERENCE INPUTS

DC Input Resistance

Input Current

See the Terminology section. R_L= 1± kΩ.

Per input.

3±

±1

3±

±1

3±

±1

MΩ typ

μA max

V_REF(+) Range

V_REF(−) Range

V_REF(+) − V_REF(−)

±/8.1ꢀ2

−ꢁ/±

ꢁ/13.1ꢀ2

±/8.1ꢀ2

−ꢁ/±

7/13.1ꢀ2

±/8.1ꢀ2

−ꢁ/±

ꢁ/13.1ꢀ2

V min/max

For specified performance. Can go as low as

± V, but performance is not guaranteed.

DEVICE SENSE GROUND INPUTS

Input Current

±2

μA max

Per input. V_DSG= −2 V to +2 V.

DIGITAL INPUTS

V_INH, Input High Voltage

2.4

±.8

±1±

1±

2.4

±.8

±1±

1±

2.4

±.8

±1±

1±

V min

V_INL, Input Low Voltage

I_INH, Input Current

V max

μA max

pF max

C_IN, Input Capacitance

POWER REQUIREMENTS

V_CC

V_DD

V_SS

ꢁ.±

1ꢁ.±

−1ꢁ.±

ꢁ.±

1ꢁ.±

−1ꢁ.±

ꢁ.±

1ꢁ.±

−1ꢁ.±

V nom

±ꢁ5 for specified performance.

Power Supply Sensitivity

ΔFull Scale/ΔV_DD

ΔFull Scale/ΔV_SS

I_CC

11±

1±±

±.2

3

11±

1±±

±.2

3

11±

1±±

±.ꢁ

3

dB typ

mA max

V_INH= V_CC, V_INL= DGND.

AD7834: V_INH= 2.4 V min, V_INL= ±.8 V max.

AD783ꢁ: V_INH= 2.4 V min, V_INL= ±.8 V max.

AD7834: outputs unloaded.

AD783ꢁ: outputs unloaded.

Outputs unloaded.

6

I_DD

I_SS

13

1ꢁ

13

1ꢁ

13

1ꢁ

¹Temperature range for A, B, and C versions is −4±°C to +8ꢁ°C.

²Guaranteed by design.

Rev. D | Page 4 of 28

AD7834/AD7835

AC PERFORMANCE CHARACTERISTICS

These characteristics are included for design guidance and are not subject to production testing.

Table 3.

Parameter

A

B

S

Unit (typ)

Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time

1±

μs

Full-scale change to ±1/2 LSB. DAC latch contents

alternately loaded with all ±s and all 1s.

Digital-to-Analog Glitch Impulse

12±

nV-s

Measured with V_REF(+) = V_REF(−) = ± V. DAC latch

alternately loaded with all ±s and all 1s.

DC Output Impedance

Channel-to-Channel Isolation

DAC-to-DAC Crosstalk

Digital Crosstalk

±.ꢁ

1±±

2ꢁ

3

±.ꢁ

1±±

2ꢁ

3

±.ꢁ

1±±

2ꢁ

3

Ω

dB

nV-s

See the Terminology section.

See the Terminology section; applies to the AD783ꢁ only.

See the Terminology section.

Feedthrough to DAC output under test due to change in

digital input code to another converter.

Digital Feedthrough—AD7834

Digital Feedthrough—AD783ꢁ

Output Noise Spectral Density at 1 kHz

±.2

1.±

4±

±.2

1.±

4±

±.2

1.±

4±

nV-s

nV/√Hz

Effect of input bus activity on DAC output under test.

All 1s loaded to DAC. V_REF(+) = V_REF(−) = ± V.

Rev. D | Page ꢁ of 28

AD7834/AD7835

TIMING SPECIFICATIONS

ꢁ_CC= 5 ꢁ 5ꢃ; ꢁ_DD= 11.4 ꢁ to 15.75 ꢁ; ꢁ_SS= −11.4 ꢁ to −15.75 ꢁ; AGND = DGND = 0 ꢁ¹.

Table 4.

Parameter

Limit at T_MIN, T_MAX

Unit

Description

AD7834-SPECIFIC

2

t₁

t₂

t₃

t₄

1±±

ꢁ±

3±

4±

3±

1±

±

ns min

SCLK cycle time

SCLK low

SCLK high time

FSYNC, PAEN setup time

FSYNC, PAEN hold time

Data setup time

2

t_ꢁ

t₆

t₇

t₈

Data hold time

LDAC to FSYNC setup time

LDAC to FSYNC hold time

Delay between write operations

t_ꢀ

4±

2±

t₂₁

AD783ꢁ-SPECIFIC

t₁₁

t₁₂

t₁₃

t₁₄

t_1ꢁ

t₁₆

t₁₇

t₁₈

t_1ꢀ

t_2±

1ꢁ

±

ns min

A±, A1, A2, BYSHF to CS setup time

A±, A1, A2, BYSHF to CS hold time

CS to WR setup time

CS to WR hold time

±

4±

1±

±

WR pulse width

Data setup time

Data hold time

LDAC to CS setup time

CS to LDAC setup time

LDAC to CS hold time

±

GENERAL

t_1±

4±

ns min

LDAC, CLR pulse width

¹All input signals are specified with t_r= t_f= ꢁ ns (1±5 to ꢀ±5 of ꢁ V) and time from a voltage level of 1.6 V.

²Rise and fall times should be no longer than ꢁ± ns.

1ST 2ND

CLK CLK

24TH

CLK

t₁

A0 A1 A2

BYSHF

SCLK

t₁₁

t₁₂

t₅

t₄

t₃

t₂

CS

WR

FSYNC

t₂₁

LSB

t₁₄

t₁₃

t₆

t₁₅

t₇

MSB

D23 D22

D0

DIN

D1

t₁₀

t₁₇

t₁₆

LDAC

(SIMULTANEOUS

UPDATE)

DB0 TO DB13

t₈

t₉

LDAC

(PER-CHANNEL

UPDATE)

t₁₀

LDAC

(SIMULTANEOUS

UPDATE)

t₁₉

t₂₀

t₁₈

LDAC

(PER-CHANNEL

UPDATE)

Figure 3. AD7834 Timing Diagram

Figure 4. AD7835 Timing Diagram

Rev. D | Page 6 of 28

AD7834/AD7835

ABSOLUTE MAXIMUM RATINGS

T_A= 95°C unless otherꢂise noted. Transient currents of up to 100 mA do not cause SCR latch-up. ꢁ_CCmust not exceed ꢁ_DDby more than

0.3 ꢁ. If it is possible for this to happen during poꢂer supply sequencing, the diode protection scheme shoꢂn in Figure 5 can be used to

provide protection.

V_DD

V_CC

Table 5.

Parameter

IN4148

SD103C

Rating

V_CCto DGND

−±.3 V to +7 V, or V_DD+ ±.3 V

(whichever is lower)

−±.3 V to +17 V

V_DD

V_CC

AD7834/

AD7835

V_DDto AGND

V_SSto AGND

AGND to DGND

+±.3 V to –17 V

−±.3 V to +±.3 V

Figure 5. Diode Protection

Digital Inputs to DGND

V_REF(+) to V_REF(–)

V_REF(+) to AGND

V_REF(–) to AGND

DSG to AGND

V_OUT(1–4) to AGND

Operating Temperature Range, T_A

Industrial (A Version)

Storage Temperature Range

Junction Temperature, T_J(max)

Power Dissipation, P_D(max)

Lead Temperature

Soldering

−±.3 V to V_CC+ ±.3 V

−±.3 V to +18 V

V_SS– ±.3 V to V_DD+ ±.3 V

THERMAL RESISTANCE

θ_JAis specified for the ꢂorst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 6. Thermal Resistance

Package Type

θ_JA

7ꢁ

ꢀꢁ

ꢁꢁ

Unit

°C/W

PDIP

SOIC

MQFP

PLCC

−4±°C to +8ꢁ°C

−6ꢁ°C to +1ꢁ±°C

1ꢁ±°C

(T_J− T_A)/θ_JA

JEDEC Industry Standard

J-STD-±2±

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. D | Page 7 of 28

AD7834/AD7835

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AGND

V

1

2

3

4

5

6

7

8

9

28

SS

DSG

(–)

27 NC

26 NC

25 NC

24 NC

V

REF

(+)

REF

NC

2

AD7834

TOP VIEW

(Not to Scale)

V

23

V

OUT

DD

V

4

V

1

3

22

21

20

OUT

DGND

V

CLR

CC

SCLK 10

DIN 11

19 LDAC

FSYNC

18

PA0 12

17 PAEN

PA1

13

16

15

PA4

PA3

PA2 14

NC = NO CONNECT

Figure 6. AD7834 PDIP and SOIC Pin Configuration

Table 7. AD7834 Pin Function Descriptions

Pin No.

Pin Mnemonic

Description

1

2

V_SS

DSG

Negative Analog Power Supply: −1ꢁ V ± ꢁ5 or −12 V ± ꢁ5.

Device Sense Ground Input. Used in conjunction with the CLR input for power-on protection of

the DACs. When CLR is low, the DAC outputs are forced to the potential on the DSG pin.

3

4

V_REF(−)

V_REF(+)

NC

Negative Reference Input. The negative reference voltage is referred to AGND.

Positive Reference Input. The positive reference voltage is referred to AGND.

No Connect.

ꢁ, 24, 2ꢁ, 26, 27

22, 6, 21, 7

8

ꢀ

V_OUT1 to V_OUT

DGND

V_CC

4

DAC Outputs.

Digital Ground.

Logic Power Supply: ꢁ V ± ꢁ5.

1±

SCLK

Clock Input. Used for writing data to the device; data is clocked into the input register on the

falling edge of SCLK.

11

DIN

Serial Data Input.

12,13,14,1ꢁ,16

PA± to PA4

Package Address Inputs. These inputs are hardwired high (V_CC) or low (DGND) to assign dedicated

package addresses in a multipackage environment.

17

PAEN

Package Address Enable Input. When low, this input allows normal operation of the device. When

high, the device ignores the package address, but not the channel address, in the serial data

stream and loads the serial data into the input registers. This feature is useful in a multipackage

application where it can be used to load the same data into the same channel in each package.

18

1ꢀ

FSYNC

LDAC

Frame Sync Input. Active low logic input used, in conjunction with DIN and SCLK, to write data to

the device with serial data expected after the falling edge of this signal. The contents of the 24-bit

serial-to-parallel input register are transferred on the rising edge of this signal.

Load DAC Input (Level Sensitive). This input signal, in conjunction with the FSYNC input signal,

determines how the analog outputs are updated. If LDAC is maintained high while new data is

being loaded into the device’s input registers, no change occurs on the analog outputs.

Subsequently, when LDAC is brought low, the contents of all four input registers are transferred

into their respective DAC latches, updating all of the analog outputs simultaneously.

2±

CLR

Asynchronous Clear Input (Level Sensitive, Active Low). When this input is brought low, all analog

outputs are switched to the externally set potential on the DSG pin. When CLR is brought high, the

signal outputs remain at the DSG potential until LDAC is brought low. When LDAC is brought low,

the analog outputs are switched back to reflect their individual DAC output levels. As long as CLR

remains low, the LDAC signals are ignored, and the signal outputs remain switched to the

potential on the DSG pin.

23

28

V_DD

AGND

Positive Analog Power Supply: 1ꢁ V ± ꢁ5 or 12 V ± ꢁ5.

Analog Ground.

Rev. D | Page 8 of 28

AD7834/AD7835

6

5

4

3

2

1

44 43 42 41 40

PIN 1

44 43 42 41 40 39 38 37 36 35 34

NC

7

8

9

39

NC

1

2

3

NC

33

32

31

30

29

IDENTIFIER

PIN 1

IDENTIFIER

DSGA

38 DSGB

DSGA

DSGB

V

1

V

3

4

37

V

1

2

V

3

4

OUT

2 10

36 V

V

4

5

OUT

NC

DB13

DB12

DB11

11

12

13

14

35

34

33

NC

A2

DB13

AD7835

TOP VIEW

(Not to Scale)

AD7835

TOP VIEW

(Not to Scale)

A2

6

28 DB12

27

A1

A0

A1

7

8

DB11

26 DB10

32 DB10

A0

31

CLR 15

LDAC

DB9

25

24

23

CLR

DB9

DB8

9

30 DB8

16

LDAC 10

11

29

BYSHF 17

DB7

BYSHF

DB7

19

26

27 28

18

20 21 22 23 24 25

12 13 14 15 16 17 18 19

21 22

20

NC = NO CONNECT

Figure 7. AD7835 MQFP Pin Configuration

Figure 8. AD7835 PLCC Pin Configuration

Table 8. AD7835 Pin Function Descriptions

Pin No.

MQFP

Pin No. PLCC Pin Mnemonic

Description

1, ꢁ, 33, 34, 3, 6, 7, 11, 3ꢀ, NC

No Connect.

37, 41, 44

2

4±, 43

8

DSGA

Device Sense Ground A Input. Used in conjunction with the CLR input for power-on

protection of the DACs. When CLR is low, DAC outputs V_OUT1 and V_OUT2 are forced to the

potential on the DSGA pin.

3, 4, 31, 3±

8, 7, 6

ꢀ, 1±, 37, 36

14, 13, 12

V_OUT1 to V_OUT

A±, A1, A2

4

DAC Outputs.

Address Inputs. A± and A1 are decoded to select one of the four input latches for a data

transfer. A2 is used to select all four DACs simultaneously.

ꢀ

1ꢁ

16

CLR

Asynchronous Clear Input (Level Sensitive, Active Low). When this input is brought low,

all analog outputs are switched to the externally set potentials on the DSG pins (V_OUT

1

and V_OUT2 follow DSGA, and V_OUT3 and V_OUT4 follow DSGB). When CLR is brought high, the

signal outputs remain at the DSG potentials until LDAC is brought low. When LDAC is

brought low, the analog outputs are switched back to reflect their individual DAC output

levels. As long as CLR remains low, the LDAC signals are ignored, and the signal outputs

remain switched to the potential on the DSG pins.

Load DAC Input (Level Sensitive). This input signal, in conjunction with the WR and CS

input signals, determines how the analog outputs are updated. If LDAC is maintained

high while new data is being loaded into the device’s input registers, no change occurs

on the analog outputs. Subsequently, when LDAC is brought low, the contents of all four

input registers are transferred into their respective DAC latches, updating the analog

outputs simultaneously. Alternatively, if LDAC is brought low while new data is being

entered, the addressed DAC latch and corresponding analog output are updated

immediately on the rising edge of WR.

1±

LDAC

11

12

13

17

18

1ꢀ

BYSHF

CS

Byte Shift Input. When low, it shifts the data on DB± to DB7 into the DB8 to DB13 half of

the input register.

Level-Triggered Chip Select Input (Active Low). The device is selected when this input is

low.

Level-Triggered Write Input (Active Low). When active, it is used in conjunction with CS

to write data over the input databus.

WR

14

1ꢁ

2±

21

V_CC

DGND

Logic Power Supply: ꢁ V ± ꢁ5.

Digital Ground.

Rev. D | Page ꢀ of 28

AD7834/AD7835

Pin No.

MQFP

Pin No. PLCC Pin Mnemonic

Description

16 to 2ꢀ

22 to 3ꢁ

DB± to DB13

Parallel Data Inputs. The AD783ꢁ can accept a straight 14-bit parallel word on DB± to

DB13, where DB13 is the MSB and the BYSHF input is hardwired to a logic high.

Alternatively for byte loading, the bottom eight data inputs, DB± to DB7, are used for

data loading, and the top six data inputs, DB8 to DB13, should be hardwired to a logic

low. The BYSHF control input selects whether 8 LSBs or 6 MSBs of data are being loaded

into the device.

32

38

DSGB

Device Sense Ground B Input. Used in conjunction with the CLR input for power-on

protection of the DACs. When CLR is low, DAC outputs V_OUT3 and V_OUT4 are forced to the

potential on the DSGB pin.

36, 3ꢁ

42, 41

V_REF(+)B, V_REF(−)B

Reference Inputs for DACs 3 and 4. These reference voltages are referred to AGND.

38

3ꢀ

4±

42, 43

44

1

2

AGND

V_DD

V_SS

Analog Ground.

Positive Analog Power Supply: 1ꢁ V ± ꢁ5 or 12 V ± ꢁ5.

Negative Analog Power Supply: −1ꢁ V ± ꢁ5 or −12 V ± ꢁ5.

Reference Inputs for DAC 1 and DAC 2. These reference voltages are referred to AGND.

4, ꢁ

V_REF(+)A, V_REF(−)A

Rev. D | Page 1± of 28

AD7834/AD7835

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

0.8

DAC 1

0.6

0.4

DAC 3

DAC 4

0.2

0

DAC 2

–0.2

–0.4

–0.6

–0.8

–1.0

TEMP = 25°C

ALL DACs FROM 1 DEVICE

0

2

4

6

8

10

12

14

16

0

2.5

5.0

8.0

CODE/1000

V

(+) (V)

REF

Figure 9. Typical INL Plot

Figure 12. Typical INL vs. V_REF(+), V_REF(+) – V_REF(−) = 5 V

0.5

0.4

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

ALL DACs FROM ONE DEVICE

0.3

DAC 1

0.2

DAC 3

0.1

DAC 4

0

–0.1

–0.2

–0.3

–0.4

–0.5

DAC 2

0

2

4

6

8

10

12

14

16

–40

25

TEMPERATURE (°C)

85

CODE/1000

Figure 13. Typical INL vs. Temperature

Figure 10. Typical DNL Plot

1.0

0.8

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

0

2

4

6

8

10

12

14

16

0

1

2

3

4

5

6

7

8

CODE/1000

V

(+) (V)

REF

Figure 11. Typical INL vs. V_REF(+), V_REF(−) = −6 V

Figure 14. Typical DAC-to-DAC Matching

Rev. D | Page 11 of 28

AD7834/AD7835

–2.985

–3.005

–3.025

–3.045

–3.065

–3.085

–3.105

8

6

0.7

VERT = 100mV/DIV

HORIZ = 1μs/DIV

VERT = 10mV/DIV

HORIZ = 1µs/DIV

0.6

0.5

0.4

0.3

0.2

0.1

0

4

V

(+) = +7V

(–) = –3V

REF

2

0

–2

–4

VERT = 2V/DIV

HORIZ = 1µs/DIV

–0.1

–0.2

Figure 15. Typical Digital/Analog Glitch Impulse

Figure 17. Settling Time(−)

7.250

7.225

7.200

7.175

7.150

7.125

7.100

8

6

VERT = 2V/DIV

HORIZ = 1.2μs/DIV

4

V

(+) = +7V

(–) = –3V

REF

2

0

–2

–4

VERT = 25mV/DIV

HORIZ = 2.5μs/DIV

Figure 16. Settling Time(+)

Rev. D | Page 12 of 28

AD7834/AD7835

TERMINOLOGY

DAC-to-DAC Crosstalk

Relative Accuracy

DAC-to-DAC crosstalk is defined as the glitch impulse that

appears at the output of one converter due to both the digital

change and the subsequent analog output (O/P) change at

another converter. It is specified in nꢁ-secs.

Relative accuracy or endpoint linearity is a measure of the

maximum deviation from a straight line passing through the

endpoints of the DAC transfer function. It is measured after

adjusting for zero error and full-scale error. It is normally

expressed in LSBs or as a percentage of full-scale reading.

Digital Crosstalk

The glitch impulse transferred to the output of one converter

due to a change in digital input code to the other converter is

defined as the digital crosstalk and is specified in nꢁ-secs.

Differential Nonlinearity

Differential nonlinearity is the difference betꢂeen the measured

change and the ideal 1 LSB change betꢂeen any tꢂo adjacent

codes. A specified differential nonlinearity of 1 LSB maximum

ensures monotonicity.

Digital Feedthrough

When the device is not selected, high frequency logic activity

on its digital inputs can be capacitively coupled both across and

through the device to shoꢂ up as noise on the ꢁ_OUTpins. This

noise is digital feedthrough.

DC Crosstalk

Although the common input reference (IR) voltage signals are

internally buffered, small IR drops in individual DAC reference

inputs across the die mean that an update to one channel

produces a dc output change in one or more channel outputs.

DC Output Impedance

DC output impedance is the effective output source resistance.

It is dominated by package lead resistance.

The four DAC outputs are buffered by op amps sharing

common ꢁ_DDand ꢁ_SSpoꢂer supplies. If the dc load current

changes in one channel due to an update, a further dc change

occurs in one or more of the channel outputs. This effect is

most obvious at high load currents and is reduced as the load

currents are reduced. With high impedance loads, the effect is

virtually unmeasurable.

Full-Scale Error

Full-scale error is the error in DAC output voltage ꢂhen all 1s

are loaded into the DAC latch. Ideally, the output voltage, ꢂith

all 1s loaded into the DAC latch, should be ꢁ_REF(+) – 1 LSB.

Full-scale error does not include zero-scale error.

Zero-Scale Error

Output Voltage Settling Time

This is the amount of time it takes for the output to settle to a

specified level for a full-scale input change.

Zero-scale error is the error in the DAC output voltage ꢂhen

all 0s are loaded into the DAC latch. Ideally, the output voltage,

ꢂith all 0s in the DAC latch, is equal to ꢁ_REF(−). Zero-scale

error is due mainly to offsets in the output amplifier.

Digital-to-Analog Glitch Impulse

This is the amount of charge injected into the analog output

ꢂhen the inputs change state. It is specified as the area of the

glitch in nꢁ-secs. It is measured ꢂith the reference inputs

connected to 0 ꢁ and the digital inputs toggled betꢂeen all

1s and all 0s.

Gain Error

Gain error is defined as (full-scale error) − (zero-scale error).

Channel-to-Channel Isolation

Channel-to-channel isolation refers to the proportion of input

signal from the reference input of one DAC that appears at the

output of the other DAC. It is expressed in decibels (dB). The

AD7834 has no specification for channel-to-channel isolation

because it has one reference for all DACs. Channel-to-channel

isolation is specified for the AD7835.

Rev. D | Page 13 of 28

AD7834/AD7835

THEORY OF OPERATION

DAC ARCHITECTURE

Table 9. D23 Control

Each channel consists of a segmented 14-bit R-9R voltage-mode

DAC. The full-scale output voltage range is equal to the entire

reference span of ꢁ_REF(+) – ꢁ_REF(−). The DAC coding is straight

binary; all 0s produce an output of ꢁ_REF(−); all 1s produce an

output of ꢁ_REF(+) − 1 LSB.

D23

Control Function

±

Ignore the following 23 bits of information.

1

Use the following 23 bits of address and data as normal.

D22 and D21

D99 and D91 are decoded to select one of the four DAC chan-

nels ꢂithin a device, as shoꢂn in Table 10.

The analog output voltage of each DAC channel reflects the

contents of its oꢂn DAC latch. Data is transferred from the

external bus to the input register of each DAC latch on a per

channel basis. The AD7835 has a feature ꢂhereby the A9 pin

data can be transferred from the input databus to all four input

registers simultaneously.

Table 10. D22, D21 Control

D22

D21

Control Function

Select Channel 1

Select Channel 2

Select Channel 3

Select Channel 4

±

1

±

1

±

1

CLR

Bringing the

line loꢂ sꢂitches all the signal outputs, ꢁ_OUT

1

to ꢁ_OUT4, to the voltage level on the DSG pin. The signal

CLR

LDAC

outputs are held at this level after the removal of the

and do not sꢂitch back to the DAC outputs until the

signal is exercised.

signal

D20 to D16

D90 and D16 determine the package address. The five address

bits alloꢂ up to 39 separate packages to be individually decoded.

Successful decoding is accomplished ꢂhen these five bits match

up ꢂith the five hardꢂired pins on the physical package.

DATA LOADING—AD7834 SERIAL INPUT DEVICE

A ꢂrite operation transfers 94 bits of data to the AD7834. The

first 8 bits are control data and the remaining 16 bits are DAC

data (see Figure 18). The control data identifies the DAC chan-

nel to be updated ꢂith neꢂ data and ꢂhich of 39 possible

packages the DAC resides in. In any communication ꢂith the

device, the first 8 bits must alꢂays be control data.

D15 to D0

D15 and D0 provide DAC data to be loaded into the identified

DAC input register. This data must have tꢂo leading 0s folloꢂed

by 14 bits of data, MSB first. The MSB is in location D13 of the

94-bit data stream.

The DAC output voltages, ꢁ_OUT1 to ꢁ_OUT4, can be updated to

reflect neꢂ data in the DAC input registers in one of tꢂo ꢂays.

DATA LOADING—AD7835 PARALLEL LOADING

DEVICE

LDAC

The first method normally keeps

high and only pulses

loꢂ momentarily to update all DAC latches simultan-

eously ꢂith the contents of their respective input registers. The

LDAC

Data is loaded into the AD7835 in either straight 14-bit ꢂide

ꢂords or in tꢂo 8-bit bytes.

LDAC

second method ties

a per channel basis after neꢂ data has been clocked into the

LDAC FSYNC

transfers

loꢂ and channel updating occurs on

BYSHF

In systems that transfer 14-bit ꢂide data, the

should be hardꢂired to ꢁ_CC. This sets up the AD7835 as a

straight 14-bit parallel-loading DAC.

input

AD7834. With

loꢂ, the rising edge of

the neꢂ data directly into the DAC latch, updating the analog

output voltage.

In 8-bit bus systems ꢂhere it is required to transfer data in tꢂo

BYSHF

bytes, it is necessary to have the

input under logic control.

Data being shifted into the AD7834 enters a 94-bit long shift

In such a system, the top six pins of the device databus, DB8 to

DB13, must be hardꢂired to DGND. Neꢂ loꢂ byte data is

loaded into the loꢂer eight places of the selected input register

FSYNC

register. If more than 94 bits are clocked in before

goes

high, the last 94 bits transmitted are used as the control data

and DAC data.

BYSHF

by carrying out a ꢂrite operation ꢂhile holding

high.

BYSHF

A second ꢂrite operation is subsequently executed ꢂith

Individual bit functions are shoꢂn in Figure 18.

loꢂ and the 6 MSBs on the DB0 to DB5 inputs (DB5 = MSB).

D23

D93 determines ꢂhether the folloꢂing 93 bits of address and

data should be used or ignored. This is effectively a softꢂare

chip select bit. D93 is the first bit to be transmitted in the 94-bit

long ꢂord.

Rev. D | Page 14 of 28

AD7834/AD7835

NOTE: D23 IS THE FIRST BIT TRANSMITTED IN THE SERIAL WORD.

D23 D22 D21 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D20 D19

LSB, DB0

CONTROL BIT TO USE/IGNORE

FOLLOWING 23 BITS OF INFORMATION

SECOND LSB, DB1

THIRD LSB, DB2

DB3

CHANNEL ADDRESS MSB, D1

CHANNEL ADDRESS LSB, D2

PACKAGE ADDRESS MSB, PA4

PACKAGE ADDRESS, PA3

PACKAGE ADDRESS, PA2

PACKAGE ADDRESS, PA1

PACKAGE ADDRESS LSB, PA0

DB4

DB5

DB6

DB7

DB8

DB9

DB10

THIRD MSB, DB11

SECOND MSB, DB12

MSB, DB13

SECOND LEADING ZERO

FIRST LEADING ZERO

Figure 18. Bit Assignments for 24-Bit Data Stream of AD7834

When 14-bit transfers are being used, the DAC output voltages,

ꢁ_OUT1 to ꢁ_OUT4, can be updated to reflect neꢂ data in the DAC

input registers in one of tꢂo ꢂays. The first method normally

gives the code table for unipolar operation of the AD7834/

AD7835.

+15V

+5V

LDAC

keeps

high and only pulses

loꢂ momentarily to

update all DAC latches simultaneously ꢂith the contents of

2

V

CC

DD

LDAC

6

5

their respective input registers. The second method ties

loꢂ, and channel updating occurs on a per channel basis after

neꢂ data is loaded to an input register.

V

OUT

(0V TO 5V)

V

(+)

V

REF

OUT

8

AD586

4

R1

10kΩ

AD7834/

AD7835¹

C1

1nF

AGND

(–)

REF

DGND

To avoid the DAC output going to an intermediate value during

V

SS

SIGNAL

GND

LDAC

a 9-byte transfer,

should not be tied loꢂ permanently but

SIGNAL

GND

should be held high until the tꢂo bytes are ꢂritten to the input

register. When the selected input register has been loaded ꢂith

–15V

ADDITIONAL PINS OMITTED FOR CLARITY

1

Figure 19. Unipolar 5 V Operation

LDAC

the tꢂo bytes,

should then be pulsed loꢂ to update the

DAC latch and, consequently, perform the digital-to-analog

conversion.

Offset and gain can be adjusted in Figure 1ꢀ as folloꢂs:

•

To adjust offset, disconnect the ꢁ_REF(−) input from 0 ꢁ,

load the DAC ꢂith all 0s, and adjust the ꢁ_REF(−) voltage

until ꢁ_OUT= 0 ꢁ.

In many applications, it may be acceptable to alloꢂ the DAC

output to go to an intermediate value during a 9-byte transfer.

LDAC

In such applications,

control line.

can be tied loꢂ, thus using one less

•

To adjust gain, load the AD7834/AD7835 ꢂith all 1s and

adjust R1 until ꢁ_OUT= 5 ꢁ(16383/16384) = 4.ꢀꢀꢀ6ꢀ5 ꢁ.

The actual DAC input register that is being ꢂritten to is deter-

mined by the logic levels present on the device address lines, as

shoꢂn in Table 11.

Many circuits do not require these offset and gain adjustments.

In these circuits, R1 can be omitted. Pin 5 of the AD586 can be

left open circuit, and Pin 9 (ꢁ_REF(−)) of the AD7834/AD7835 is

tied to 0 ꢁ.

Table 11. AD7835—Address Line Truth Table

A2

A1

A0

DAC Selected

Table 12. Code Table for Unipolar Operation^{1, 2}

±

DAC 1

Binary Number in DAC Latch

±

1

±

1

X

1

±

1

X

DAC 2

DAC 3

DAC 4

All DACs selected

MSB

LSB

Analog Output (V_OUT)

11

1111

V_REF(16383/16384) V

1±

±1

±±

±±±±

1111

±±±±

1111

±±±±

1111

±±±1

±±±±

V_REF(81ꢀ2/16384) V

V_REF(81ꢀ1/16384) V

V_REF(1/16384) V

± V

UNIPOLAR CONFIGURATION

Figure 1ꢀ shoꢂs the AD7834/AD7835 in the unipolar binary

circuit configuration. The ꢁ_REF(+) input of the DAC is driven by

the AD586, a 5 ꢁ reference. ꢁ_REF(−) is tied to ground. Table 19

¹V_REF= V_REF(+); VREF(−) = ± V for unipolar operation.

²For V_REF(+) = ꢁ V, 1 LSB = ꢁ V/2¹⁴= ꢁ V/16384 = 3±ꢁ μV.

Rev. D | Page 1ꢁ of 28

AD7834/AD7835

In Figure 90, full-scale and bipolar zero adjustments are

provided by varying the gain and balance on the AD588. R9

varies the gain on the AD588 ꢂhile R3 adjusts the offset of both

the +5 ꢁ and –5 ꢁ outputs together ꢂith respect to ground.

BIPOLAR CONFIGURATION

+15V

+5V

R1

39kΩ

6

4

For bipolar-zero adjustment, the DAC is loaded ꢂith

1000 . . . 0000 and R3 is adjusted until ꢁ_OUT= 0 ꢁ. Full scale

is adjusted by loading the DAC ꢂith all 1s and adjusting R9

until ꢁ_OUT= 5(81ꢀ1/81ꢀ9) ꢁ = 4.ꢀꢀꢀ3ꢀ ꢁ.

7

9

V

2

3

CC

DD

C1

V

1μF

OUT

(–5V TO +5V)

V

(+)

V

REF

OUT

1

AD588

AD7834/

AD7835¹

14

5

10

11

R2

100kΩ

AGND

15

16

V

(–)

REF

DGND

When bipolar zero and full-scale adjustment are not needed, R9

and R3 are omitted. Pin 19 on the AD588 should be connected to

Pin 11, and Pin 5 should be left floating.

V

SS

12

8

13

R3

100kΩ

SIGNAL

GND

–15V

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 20. Bipolar 5 V Operation

Figure 90 shoꢂs the AD7834/AD7835 setup for 5 ꢁ operation.

The AD588 provides precision 5 ꢁ tracking outputs that are

fed to the ꢁ_REF(+) and ꢁ_REF(−) inputs of the AD7834/AD7835.

The code table for bipolar operation of the AD7834/AD7835 is

shoꢂn in Table 13.

Table 13. Code Table for Bipolar Operation^{1, 2}

Binary Number in DAC Latch

MSB

11

LSB

1111 1111 1111

±±±± ±±±± ±±±1

±±±± ±±±± ±±±±

1111 1111 1111

±±±± ±±±± ±±±1

±±±± ±±±± ±±±±

Analog Output (V_OUT)

V_REF(−) + V_REF(16383/16384) V

V_REF(−) + V_REF(81ꢀ3/16384) V

V_REF(−) + V_REF(81ꢀ2/16384) V

V_REF(−) + V_REF(81ꢀ1/16384) V

V_REF(−) + V_REF(1/16384) V

V_REF(−) V

1±

±1

±±

¹V_REF= V_REF(+) – V_REF(−).

²For V_REF(+) = +ꢁ V and V_REF(−) = –ꢁ V, 1 LSB = 1± V/2¹⁴= 1± V/16384 = 61± μV.

Rev. D | Page 16 of 28

AD7834/AD7835

CONTROLLED POWER-ON OF THE OUTPUT STAGE

A block diagram of the output stage of the AD7834/AD7835 is

shoꢂn in Figure 91. It is capable of driving a load of 10 kΩ in

parallel ꢂith 900 pF. G₁to G₆are transmission gates used to

control the poꢂer-on voltage present at ꢁ_OUT. G₁and G₉are also

G

1

G

6

DAC

V

OUT

G

3

G

4

G

CLR

2

used in conjunction ꢂith the

input to set ꢁ_OUTto the user-

G

5

R

defined voltage present at the DSG pin.

G

1

G

6

DAC

DSG

V

OUT

CLR

Figure 23. Output Stage with V_DD> 10 V and

Low

G

3

G

4

ꢁ_OUTis disconnected from the DSG pin by the opening of G₅

but tracks the voltage present at DSG via the unity gain buffer.

G

2

G

5

R

POWER-ON WITH LDAC LOW, CLR HIGH

DSG

LDAC

In many applications of the AD7834/AD7835,

continuously loꢂ, updating the DAC after each valid data

LDAC

is kept

Figure 21. Block Diagram of AD7834/AD7835 Output Stage

POWER-ON WITH CLR LOW, LDAC HIGH

transfer. If

is loꢂ ꢂhen poꢂer is applied, G₁is closed and

G₉is open, connecting the output of the DAC to the input of the

output amplifier. G₃and G₅are closed and G₄and G₆are open,

connecting the amplifier as a unity gain buffer, as before. ꢁ_OUTis

connected to DSG via G₅and R (a thin-film resistance betꢂeen

DSG and ꢁ_OUT) until ꢁ_DDand ꢁ_SSreach approximately 10 ꢁ.

Then, the internal poꢂer-on circuitry opens G₃and G₅and

closes G₄and G₆. This is the situation shoꢂn in Figure 94. At

this point, ꢁ_OUTis at the same voltage as the DAC output.

The output stage of the AD7834/AD7835 is designed to alloꢂ

output stability during poꢂer-on. If

poꢂer-on, and poꢂer is applied to the part, G₁, G₄, and G₆are

open ꢂhile G₉, G₃, and G₅are closed (see Figure 99).

CLR

is kept loꢂ during

G

1

G

6

DAC

V

OUT

G

3

G

1

G

4

G

6

DAC

G

2

V

OUT

G

5

R

G

3

G

4

G

2

DSG

G

5

R

Figure 22. Output Stage with V_DD< 10 V

ꢁ_OUTis kept ꢂithin a feꢂ hundred millivolts of DSG via G₅

and R. R is a thin-film resistor betꢂeen DSG and ꢁ_OUT. The

output amplifier is connected as a unity gain buffer via G₃, and

the DSG voltage is applied to the buffer input via G₉. The

amplifier output is thus at the same voltage as the DSG pin. The

output stage remains configured as in Figure 99 until the

voltage at ꢁ_DDand ꢁ_SSreaches approximately 10 ꢁ. At this

point, the output amplifier has enough headroom to handle

signals at its input and has also had time to settle. The internal

poꢂer-on circuitry opens G₃and G₅and closes G₄and G₆(see

Figure 93). As a result, the output amplifier is connected in

unity gain mode via G₄and G₆. The DSG voltage is still applied

DSG

LDAC

Figure 24. Output Stage with

Low

LOADING THE DAC AND USING THE CLR INPUT

LDAC

When

goes loꢂ, it closes G₁and opens G₉as in Figure 94.

The voltage at ꢁ_OUTnoꢂ folloꢂs the voltage present at the out-

put of the DAC. The output stage remains connected in this

CLR

manner until a

(see Figure 93). Once again, ꢁ_OUTremains at the same voltage as

LDAC

signal is applied. Then, the situation reverts

DSG until

goes loꢂ. This reconnects the DAC output to

the unity gain buffer.

to the noninverting input via G₉. This voltage appears at ꢁ_OUT

.

Rev. D | Page 17 of 28

AD7834/AD7835

Once the AD7834/AD7835 have poꢂered on and the on-chip

amplifiers have settled, the situation is as shoꢂn in Figure 93.

Any voltage subsequently applied to the DSG pin is buffered by

the same amplifier that buffers the DAC output voltage in

normal operation. Thus, for specified operations, the maximum

voltage applied to the DSG pin increases to the maximum

alloꢂable ꢁ_REF(+) voltage, and the minimum voltage applied to

DSG is the minimum ꢁ_REF(−) voltage. After the AD7834 or

AD7835 has fully poꢂered on, the outputs can track any DSG

voltage ꢂithin this minimum/maximum range.

DSG VOLTAGE RANGE

During poꢂer-on, the ꢁ_OUTpins of the AD7834/AD7835 are

connected to the relevant DSG pins via G₆and the thin-film

resistor, R. The DSG potential must obey the maximum ratings

at all times. Thus, the voltage at DSG must alꢂays be ꢂithin the

range ꢁ_SS– 0.3 ꢁ to ꢁ_DD+ 0.3 ꢁ. Hoꢂever, to keep the voltages

at the ꢁ_OUTpins of the AD7834/AD7835 ꢂithin 9 ꢁ of the

relevant DSG potential during poꢂer-on, the voltage applied to

DSG should also be kept ꢂithin the range AGND – 9 ꢁ to

AGND + 9 ꢁ.

Rev. D | Page 18 of 28

AD7834/AD7835

POWER-ON OF THE AD7834/AD7835

Poꢂer is normally applied to the AD7834/AD7835 in the

folloꢂing sequence: first ꢁ_DDand ꢁ_SS, then ꢁ_CC, and then

V

(+)

REF

SD103C

1N5711

1N5712

AD7834¹

ꢁ_REF(+) and ꢁ_REF(−). The ꢁ_REFpins are not alloꢂed to float ꢂhen

poꢂer is applied to the part. ꢁ_REF(+) is not alloꢂed to go beloꢂ

V

(–)

REF

ꢁ_REF(−) − 0.3 ꢁ. ꢁ_REF(−) is not alloꢂed to go beloꢂ ꢁ_SS− 0.3 ꢁ.

1

ADDITIONAL PINS OMITTED FOR CLARITY

ꢁ_DDis not alloꢂed to go beloꢂ ꢁ_CC− 0.3 ꢁ.

Figure 25. Power-On Protection

In some systems, it is necessary to introduce one or more

Schottky diodes betꢂeen pins to prevent the above situations

arising at poꢂer-on. These diodes are shoꢂn in Figure 95.

Hoꢂever, in most systems, ꢂith careful consideration given to

poꢂer supply sequencing, the above rules are adhered to, and

protection diodes are not necessary.

Rev. D | Page 1ꢀ of 28

AD7834/AD7835

MICROPROCESSOR INTERFACING

To load data to the AD7834, PC7 is left loꢂ after the first eight

bits are transferred. A second byte of data is then transmitted

serially to the AD7834. Then, a third byte is transmitted and,

ꢂhen this transfer is complete, the PC7 line is taken high.

AD7834 TO 80C51 INTERFACE

A serial interface betꢂeen the AD7834 and the 80C51 micro-

controller is shoꢂn in Figure 96. TXD of the 80C51 drives SCLK

of the AD7834, ꢂhile RXD drives the serial data line of the part.

68HC11¹

PC5

AD7834¹

The 80C51 provides the LSB of its SBUF register as the first bit

in the serial data stream. The AD7834 expects the MSB of the

94-bit ꢂrite first. Therefore, the user has to ensure that data in

the SBUF register is arranged correctly so the data is received

MSB first by the AD7834/AD7835. When data is to be trans-

mitted to the part, P3.3 is taken loꢂ. Data on RXD is valid on

the falling edge of TXD. The 80C51 transmits its data in 8-bit

bytes ꢂith only eight falling clock edges occurring in the trans-

mit cycle. To load data to the AD7834, P3.3 is left loꢂ after the

first 8 bits are transferred. A second byte is then transferred,

ꢂith P3.3 still kept loꢂ. After the third byte has been trans-

ferred, the P3.3 line is taken high.

CLR

PC6

PC7

SCK

LDAC

FSYNC

SCLK

MOSI

DIN

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 27. AD7834 to 68HC11 Interface

LDAC

CLR

are controlled by the PC6 and PC5

In Figure 97,

and

port outputs, respectively. As ꢂith the 80C51, each DAC of the

AD7834 can be updated after each 3-byte transfer, or all DACs

can be simultaneously updated after 19 bytes are transferred.

80C51¹

AD7834¹

P3.5

CLR

AD7834 TO ADSP-2101 INTERFACE

LDAC

FSYNC

SCLK

P3.4

P3.3

TXD

An interface betꢂeen the AD7834 and the ADSP-9101 is shoꢂn

in Figure 98. In the interface shoꢂn, SPORT0 is used to transfer

data to the part. SPORT1 is configured for alternate functions.

RXD

DIN

LDAC

FO, the flag output on SPORT0, is connected to

and is

used to load the DAC latches. In this ꢂay, data is transferred

from the ADSP-9101 to all the input registers in the DAC, and

the DAC latches are updated simultaneously. In the application

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 26. AD7834 to 80C51 Interface

CLR

shoꢂn, the

pin on the AD7834 is controlled by circuitry

LDAC

CLR

and

on the AD7834 are also controlled by 80C51

LDAC

that monitors the poꢂer in the system.

port outputs. The user can bring

loꢂ after every three

bytes have been transmitted to update the DAC, ꢂhich has been

programmed. Alternatively, it is possible to ꢂait until all the

input registers have been loaded (19-byte transmits) and then

update the DAC outputs.

POWER

MONITOR

ADSP-2101¹

AD7834¹

CLR

LDAC

FSYNC

SCLK

FO

TFS

SCK

AD7834 TO 68HC11 INTERFACE

Figure 97 shoꢂs a serial interface betꢂeen the AD7834 and the

68HC11 microcontroller. SCK of the 68HC11 drives SCLK of

the AD7834, ꢂhile the MOSI output drives the serial data line,

FSYNC

DT

DIN

1

ADDITIONAL PINS OMITTED FOR CLARITY

DIN, of the AD7834. The

Line PC7.

signal is derived from Port

Figure 28. AD7834 to ADSP-2101 Interface

For correct operation of this interface, the 68HC11 should be

configured so that its CPOL bit is 0 and its CPHA bit is 1. When

data is to be transferred to the part, PC7 is taken loꢂ. When the

68HC11 is configured like this, data on MOSI is valid on the

falling edge of SCK. The 68HC11 transmits its serial data in 8-bit

bytes, MSB first. The AD7834 also expects the MSB of the 94-bit

ꢂrite first. Eight falling clock edges occur in the transmit cycle.

The AD7834 requires 94 bits of serial data framed by a single

FSYNC

pulse. It is necessary that this

pulse stay loꢂ until

all the data is transferred. This can be provided by the ADSP-9101

in one of tꢂo ꢂays. Both require setting the serial ꢂord length of

the SPORT to 19 bits, ꢂith the folloꢂing conditions: internal

SCLK, alternate framing mode, and active loꢂ framing signal.

Rev. D | Page 2± of 28

AD7834/AD7835

First, data can be transferred using the autobuffering feature of

the ADSP-9101, sending tꢂo 19-bit ꢂords directly after each

other. This ensures a continuous transmit frame synchron-

ization (TFS ) pulse. Second, the first data ꢂord is loaded to the

serial port, the subsequent generated interrupt is trapped, and

then the second data ꢂord is sent immediately after the first.

Again, this produces a continuous TFS pulse that frames the

94 data bits.

CLOCK/

TIMER

TMS32020/

TMS320C25

AD7834¹

1

LDAC

CLR

XF

FSX

FSYNC

SCLK

CLKX

DX

DIN

1

AD7834 TO DSP56000/DSP56001 INTERFACE

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 9ꢀ shoꢂs a serial interface betꢂeen the AD7834 and the

DSP56000/DSP56001. The serial port is configured for a ꢂord

length of 94 bits, gated clock, and FSL0 and FSL1 control bits

each set to 0. Normal mode synchronous operation is selected,

ꢂhich alloꢂs the use of SC0 and SC1 as outputs controlling

Figure 30. AD7834 to TMS32020/TMS320C25 Interface

INTERFACING THE AD7835—16-BIT INTERFACE

The AD7835 can be interfaced to a variety of microcontrollers

or DSP processors, both 8-bit and 16-bit. Figure 31 shoꢂs the

AD7835 interfaced to a generic 16-bit microcontroller/DSP

CLR

LDAC

and

, respectively. The framing signal on SC9 has to

FSYNC

BYSHF

processor.

is tied to ꢁ_CCin this interface. The loꢂer

be inverted before being applied to

. SCK is internally

address lines from the processor are connected to A0, A1, and

A9 on the AD7835 as shoꢂn. The upper address lines are

decoded to provide a chip select signal for the AD7835. They

are also decoded, in conjunction ꢂith the loꢂer address lines if

generated on the DSP56000/DSP56001 and is applied to SCLK

on the AD7834. Data from the DSP56000/DSP56001 is valid on

the falling edge of SCK.

DSP56000/

AD7834¹

1

LDAC

need be, to provide an

signal. Alternatively, can be

DSP56001

SC0

CLR

driven by an external timing circuit or just tied loꢂ. The data

lines of the processor are connected to the data lines of the

AD7835. Selection options available for the DACs are provided

in Table 11.

LDAC

FSYNC

SCLK

SC1

SC2

SCK

AD7835¹

MICROCONTROLLER/

V

STD

DIN

CC

DSP

1

PROCESSOR

BYSHF

1

ADDITIONAL PINS OMITTED FOR CLARITY

D13

D0

D13

D0

Figure 29. AD7834 to DSP56000/DSP56001 Interface

DATABUS

AD7834 TO TMS32020/TMS320C25 INTERFACE

UPPER BITS OF

ADDRESS BUS

A serial interface betꢂeen the AD7834 and the TMS39090/

TMS390C95 DSP processor is shoꢂn in Figure 30. The

CS

ADDRESS

DECODE

LDAC

CLKX and FSX signals for the TMS39090/TMS39095 are

generated using an external clock/timer circuit. The CLKX and

FSX pins are configured as inputs. The TMS39090/ TMS390C95

are set up for an 8-bit serial data length. Data can then be ꢂritten

to the AD7834 by ꢂriting three bytes to the serial port of the

TMS39090/TMS390C95. In the configuration shoꢂn in Figure

30, the CLR input on the AD7834 is controlled by the XF output

on the TMS39090/TMS390C95. The clock/timer circuit controls

A2

A1

A2

A1

A0

R/W

WR

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 31. AD7835 16-Bit Interface

LDAC

the

input on the AD7834. Alternatively,

can also be

tied to ground to alloꢂ automatic update of the DAC latches after

each transfer.

Rev. D | Page 21 of 28

AD7834/AD7835

When ꢂriting to the DACs, the loꢂer eight bits must be ꢂritten

first, folloꢂed by the upper six bits. The upper six bits should be

output on data lines D0 to D5. Once again, the upper address

INTERFACING THE AD7835—8-BIT INTERFACE

Figure 39 shoꢂs an 8-bit interface betꢂeen the AD7835 and

a generic 8-bit microcontroller/DSP processor. Pin D13 to

Pin D8 of the AD7835 are tied to DGND. Pin D7 to Pin D0 of the

processor are connected to Pin D7 to Pin D0 of the AD7835.

CS

lines of the processor are decoded to provide a

are also decoded in conjunction ꢂith lines A3 to A0 to provide

LDAC LDAC

can be driven by an exter-

signal. They

an

signal. Alternatively,

BYSHF

is driven by the A0 line of the processor. This maps the

nal timing circuit or, if it is acceptable to alloꢂ the DAC output

DAC upper bits and loꢂer bits into adjacent bytes in the proces-

sor address space. Table 14 shoꢂs the truth table for addressing

the DACs in the AD7835. For example, if the base address for the

DACs in the processor address space is decoded by the upper

address bits to location HC000, then the upper and loꢂer bits of

the first DAC are at locations HC000 and HC001, respectively.

LDAC

to go to an intermediate value betꢂeen 8-bit ꢂrites,

be tied loꢂ.

can

Table 14. DAC Channel Decoding, 8-Bit Interface

Processor Address Lines

A3

x

1

±

A2

X

±

1

A1

X

±

1

±

1

A0

±

1

±

1

±

1

±

1

DAC Selected

D13

Upper 6 bits of all DACs

Lower 8 bits of all DACs

Upper 6 bits, DAC 1

Lower 8 bits, DAC 1

Upper 6 bits, DAC 2

Lower 8 bits, DAC 2

Upper 6 bits, DAC 3

Lower 8 bits, DAC 3

Upper 6 bits, DAC 4

Lower 8-bits, DAC 4

MICROCONTROLLER/

DSP

PROCESSOR

1

D8

AD7835¹

DGND

D7

D0

D7

DATABUS

D0

UPPER BITS OF

ADDRESS BUS

CS

ADDRESS

DECODE

LDAC

±

1

A3

A2

A1

1

A1

A0

BYSHF

WR

R/W

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 32. AD7835 8-Bit Interface

Rev. D | Page 22 of 28

AD7834/AD7835

APPLICATIONS INFORMATION

Figure 34 shoꢂs a 5-channel isolated interface to the AD7834.

Multiple devices are connected to the outputs of the opto-coupler

and controlled as for serial interfacing. To reduce the number of

SERIAL INTERFACE TO MULTIPLE AD7834S

Figure 33 shoꢂs hoꢂ the package address pins of the AD7834

are used to address multiple AD7834s. This figure shoꢂs only

10 devices, but up to 39 AD7834s can each be assigned a unique

address by hardꢂiring each of the package address pins to ꢁ_CC

PAEN

opto-isolators, the

PAEN

line doesn’t need to be controlled if it

is not used. If the

line is not controlled by the microcon-

troller, it should be tied loꢂ at each device. If simultaneous updat-

LDAC

PAEN

or DGND. Normal operation of the device occurs ꢂhen

ing of the DACs is not required, the

pin on each part can

is loꢂ. When serial data is being ꢂritten to the AD7834s, only

the device ꢂith the same package address as the package address

contained in the serial data accepts data into the input registers.

be tied permanently loꢂ and another opto-isolator is not needed.

V

CC

MICROCONTROLLER

PAEN

Conversely, if

is high, the package address is ignored, and

the data is loaded into the same channel on each package.

TO PAENs

TO LDACs

TO FSYNCs

TO SCLKs

TO DINs

CONTROL OUT

SYNC OUT

The primary limitation ꢂith multiple packages is the output

update rate. For example, if an output update rate of 10 kHz is

required, 100 μs are available to load all DACs. Assuming a

serial clock frequency of 10 MHz, it takes 9.5 μs to load data to

one DAC. Thus, 40 DACs or 10 packages can be updated in this

time. As the update rate requirement decreases, the number of

possible packages increases.

SERIAL CLOCK OUT

SERIAL DATA OUT

OPTO-COUPLER

AD7834¹

DEVICE 0

Figure 34. Opto-Isolated Interface

MICROCONTROLLER

AUTOMATED TEST EQUIPMENT

CONTROL OUT

PAEN

LDAC

FSYNC

SCLK

PA0

CONTROL OUT

SYNC OUT

PA1

PA2

The AD7834/AD7835 are particularly suited for use in an

automated test environment. Figure 35 shoꢂs the AD7835

providing the necessary voltages for the pin driver and the

ꢂindoꢂ comparator in a typical ATE pin electronics configur-

ation. Tꢂo AD588s are used to provide reference voltages for

the AD7835. In the configuration shoꢂn, the AD588s are

configured so that the voltage at Pin 1 is 5 ꢁ greater than the

voltage at Pin ꢀ and the voltage at Pin 15 is 5 ꢁ less than the

voltage at Pin ꢀ.

PA3

PA4

SERIAL CLOCK OUT

SERIAL DATA OUT

DIN

AD7834¹

DEVICE 1

V

CC

PAEN

PA0

LDAC

FSYNC

SCLK

PA1

PA2

PA3

PA4

DIN

One AD588 is used as a reference for DAC 1 and DAC 9. These

DACs are used to provide high and loꢂ levels for the pin driver.

The pin driver can have an associated offset. This can be nulled

by applying an offset voltage to Pin ꢀ of the AD588. First, the

code 1000 . . . 0000 is loaded into the DAC 1 latch, and the pin

driver output is set to the DAC 1 output. The ꢁ_OFFSETvoltage is

adjusted until 0 ꢁ appears betꢂeen the pin driver output and

DUT GND. This causes both ꢁ_REF(+)A and ꢁ_REF(−)A to be off-

AD7834¹

V

CC

DEVICE 9

PAEN

PA0

LDAC

FSYNC

SCLK

PA1

PA2

PA3

PA4

DIN

set ꢂith respect to AGND by an amount equal to ꢁ_OFFSET

.

1

ADDITIONAL PINS OMITTED FOR CLARITY

Hoꢂever, the output of the pin driver varies from −5 ꢁ to +5 ꢁ

ꢂith respect to DUT GND as the DAC input code varies from

000 . . . 000 to 111 . . . 111. The ꢁ_OFFSETvoltage is also applied to

the DSGA pin. When a clear is performed on the AD7835, the

output of the pin driver is 0 ꢁ ꢂith respect to DUT GND.

Figure 33. Serial Interface to Multiple AD7834s

OPTO-ISOLATED INTERFACE

In many process control applications, it is necessary to provide

an isolation barrier betꢂeen the controller and the unit being

controlled. Opto-isolators can provide voltage isolation in

excess of 3 kꢁ. The serial loading structure of the AD7834

makes it ideal for opto-isolated interfaces because the number

of interface lines is kept to a minimum.

Rev. D | Page 23 of 28

AD7834/AD7835

V

–15V

+15V

OFFSET

If the AD7834/AD7835 are the only devices requiring an AGND

to DGND connection, then the ground planes should be connected

at the AGND and DGND pins of the AD7834/ AD7835. If the

AD7834/AD7835 are in a system ꢂhere multiple devices require

an AGND to DGND connection, the connection can still be made

at one point only, a star ground point, ꢂhich can be established as

close as possible to the AD7834/AD7835.

2

16

3

1

4

6

8

+15V

V

(+)A

(–)A

REF

V

1

OUT

15

14

AD588

13

7

DRIVER

V

REF

V

OUT

2

9

1µF

DSG A

0.1µF

–15V

AD7835¹

10 11 12

+15V –15V

Digital lines running under the device must be avoided because

they couple noise onto the die. The analog ground plane can run

under the AD7834/AD7835 to avoid noise coupling. The poꢂer

supply lines of the AD7834/AD7835 can use as large a trace as

possible to provide loꢂ impedance paths and reduce the effects of

glitches on the poꢂer supply line. Fast sꢂitching signals, such as

clocks, should be shielded ꢂith digital ground to avoid radiating

noise to other parts of the board. These signals should never be

run near the analog inputs. Avoid crossover of digital and analog

signals. Traces on opposite sides of the board should run at right

angles to each other. This reduces the effects of feedthrough

through the board. A microstrip method is best but not alꢂays

possible ꢂith a double-sided board. With this method, the

component side of the board is dedicated to ground plane ꢂhile

signal traces are placed on the solder side.

DSG B

V

DUT

GND

DUT

2

16

V

OUT

3

4

6

3

1

DUT

GND

V

(+)B

(–)B

REF

8

V

OUT

4

15

14

13

V

AD588

REF

10

11

12

AGND

WINDOW

COMPARATOR

7

9

1µF

DUT

GND

TO TESTER

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 35. ATE Application

The other AD588 provides a reference voltage for DAC 3 and

DAC 4. These provide the reference voltages for the ꢂindoꢂ

comparator shoꢂn in Figure 35. Pin ꢀ of this AD588 is con-

nected to DUT GND. This causes ꢁ_REF(+)B and ꢁ_REF(−)B to be

referenced to DUT GND. As DAC 3 and DAC 4 input codes vary

from 000 . . . 000 to 111 . . . 111, ꢁ_OUT3 and ꢁ_OUT4 vary from −5 ꢁ

to +5 ꢁ ꢂith respect to DUT GND. DUT GND is also connected

to DSGB. When the AD7835 is cleared, ꢁ_OUT3 and ꢁ_OUT4 are

cleared to 0 ꢁ ꢂith respect to DUT GND.

The AD7834/AD7835 must have ample supply bypassing located

as close as possible to the package, ideally right up against the

device. Figure 36 shoꢂs the recommended capacitor values of

10 μF in parallel ꢂith 0.1 μF on each of the supplies. The 10 μF

capacitors are the tantalum bead type. The 0.1 μF capacitor can

have loꢂ effective series resistance (ESR) and effective series

inductance (ESI), such as the common ceramic types, ꢂhich

provide a loꢂ impedance path to ground at high frequencies to

handle transient currents due to internal logic sꢂitching.

Care must be taken to ensure that the maximum and minimum

voltage specifications for the AD7835 reference voltages are

folloꢂed as shoꢂn in Figure 35.

POWER SUPPLY BYPASSING AND GROUNDING

V

CC

DD

In any circuit ꢂhere accuracy is important, careful considera-

tion of the poꢂer supply and ground return layout helps to

ensure the rated performance. The printed circuit boards on

ꢂhich the AD7834/AD7835 are mounted should be designed so

the analog and digital sections are separated and confined to

certain areas of the boards. This facilitates the use of ground

planes that can be easily separated. A minimum etch technique

is generally best for ground planes because it gives the best

shielding. Digital and analog ground planes should be joined at

only one place.

0.1μF

10μF

0.1μF

10μF

AD7834/

AD7835¹

DGND

AGND

V

SS

10μF

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 36. Power Supply Decoupling

Rev. D | Page 24 of 28

AD7834/AD7835

OUTLINE DIMENSIONS

18.10 (0.7126)

17.70 (0.6969)

28

1

15

14

7.60 (0.2992)

7.40 (0.2913)

10.65 (0.4193)

10.00 (0.3937)

0.75 (0.0295)

0

.25 (0.0098)

45°

2.65 (0.1043)

2.35 (0.0925)

0.30 (0.0118)

0.10 (0.0039)

8°

0°

COPLANARITY

0.10

SEATING

PLANE

0.51 (0.0201)

0.31 (0.0122)

1.27 (0.0500)

BSC

1.27 (0.0500)

0.40 (0.0157)

0.33 (0.0130)

0.20 (0.0079)

COMPLIANT TO JEDEC STANDARDS MS-013-AE

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 37. 28-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(RW-28)

Dimensions shown in millimeters and (inches)

1.565 (39.75)

1.380 (35.05)

28

1

15

0.580 (14.73)

0.485 (12.31)

14

0.625 (15.88)

0.600 (15.24)

0.100 (2.54)

BSC

0.195 (4.95)

0.125 (3.17)

0.250 (6.35)

MAX

0.015 (0.38)

GAUGE

PLANE

0.015

(0.38)

MIN

0.200 (5.08)

0.115 (2.92)

0.015 (0.38)

0.008 (0.20)

SEATING

PLANE

0.700 (17.78)

MAX

0.022 (0.56)

0.014 (0.36)

0.005 (0.13)

MIN

0.070 (1.78)

0.050 (1.27)

COMPLIANT TO JEDEC STANDARDS MS-011

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

CORNER LEADS MAY BE CONFIGURED AS WHOLE LEADS.

Figure 38. 28-Lead Plastic Dual In-Line Package [PDIP]

Wide Body

(N-28-2)

Dimensions shown in inches and (millimeters)

Rev. D | Page 2ꢁ of 28

AD7834/AD7835

0.180 (4.57)

0.165 (4.19)

0.048 (1.22)

0.042 (1.07)

0.056 (1.42)

0.042 (1.07)

0.020 (0.51)

MIN

6

7

40

39

0.048 (1.22)

0.042 (1.07)

0.021 (0.53)

0.013 (0.33)

PIN 1

IDENTIFIER

0.630 (16.00)

0.590 (14.99)

BOTTOM VIEW

(PINS UP)

0.050

(1.27)

BSC

TOP VIEW

(PINS DOWN)

0.032 (0.81)

0.026 (0.66)

17

18

29

28

0.045 (1.14)

0.025 (0.64)

R

0.656 (16.66)

0.650 (16.51)

0.120 (3.05)

0.090 (2.29)

SQ

0.695 (17.65)

0.685 (17.40)

SQ

COMPLIANT TO JEDEC STANDARDS MO-047-AC

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 39. 44-Lead Plastic Leaded Chip Carrier [PLCC}

(P-44A)

Dimensions shown in inches and (millimeters)

14.15

1.03

0.88

0.73

13.90 SQ

13.65

2.45

MAX

34

44

1.95 REF

1

33

PIN 1

SEATING

PLANE

10.20

10.00 SQ

9.80

TOP VIEW

(PINS DOWN)

2.20

2.00

1.80

0.23

0.11

23

11

7°

0°

22

12

0.25 MIN

0.10

0.45

0.30

LEAD WIDTH

COPLANARITY

VIEW A

0.80 BSC

LEAD PITCH

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MO-112-AA-1

Figure 40. 44-Lead Metric Quad Flat Package [MQFP]

(S-44-2)

Dimensions show in millimeters

Rev. D | Page 26 of 28

AD7834/AD7835

ORDERING GUIDE

Model

Temperature Range

−4±°C to +8ꢁ°C

Linearity Error (LSBs)

DNL (LSBs)

±±.ꢀ

Package Description Package Option

AD7834AR

±2

±1

±2

±1

±2

28-Lead SOIC_W

28-Lead PDIP

RW-28

N-28-2

P-44A

S-44-2

AD7834AR-REEL

AD7834ARZ¹

AD7834ARZ-REEL¹

AD7834BR

AD7834BR-REEL

AD7834BRZ¹

AD7834BRZ-REEL¹

AD7834AN

AD7834ANZ¹

AD7834BN

28-Lead PDIP

AD7834BNZ¹

28-Lead PDIP

AD783ꢁAP

44-Lead PLCC

AD783ꢁAP-REEL

AD783ꢁAPZ¹

AD783ꢁAPZ-REEL¹

44-Lead PLCC

AD783ꢁAS

44-Lead-MQFP

AD783ꢁAS-REEL

AD783ꢁASZ¹

AD783ꢁASZ-REEL¹

¹Z = RoHS Compliant Part.

Rev. D | Page 27 of 28

AD7834/AD7835

NOTES

registered trademarks are the property of their respective owners.

C01006-0-8/07(D)

Rev. D | Page 28 of 28


型号：	AD7834AR
厂家：	Rochester Electronics
描述：	QUAD, SERIAL INPUT LOADING, 10 us SETTLING TIME, 14-BIT DAC, PDSO28, MS-013AE, SOIC-28 输入元件光电二极管
文件：	总29页 (文件大小：2196K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7834AR [ROCHESTER]

相关型号：

AD7834AR-REEL

AD7834ARZ

AD7834ARZ-REEL

AD7834BN

AD7834BN

AD7834BNZ

AD7834BR

AD7834BR

AD7834BR-REEL

AD7834BRZ

AD7834BRZ

AD7834SQ