AD6650ABCZ_技术文档

AD6650 Diversity IF-to-Baseband

GSM/EDGE Narrow-Band Receiver

AD6650

Smart antenna systems

FEATURES

116 dB dynamic range

Software radios

In-building wireless telephony

Digital VGA

I/Q demodulators

Active low-pass filters

PRODUCT DESCRIPTION

The AD6650 is a diversity intermediate frequency-to-baseband

(IF-to-baseband) receiver for GSM/EDGE. This narrow-band

receiver consists of an integrated DVGA, IF-to-baseband I/Q

demodulators, low-pass filtering, and a dual wideband ADC.

The chip can accommodate IF input from 70 MHz to 260 MHz.

The receiver architecture is designed such that only one external

surface acoustic wave (SAW) filter for main and one for diversity

are required in the entire receive signal path to meet GSM/EDGE

blocking requirements.

Dual wideband ADC

Programmable decimation and channel filters

VCO and phase-locked loop circuitry

Serial data output ports

Intermediate frequencies of 70 MHz to 260 MHz

10 dB noise figure

+43 dBm input IP2 at 70 MHz IF

−9.5 dBm input IP3 at 70 MHz IF

3.3 V I/O and CMOS core

Microprocessor interface

JTAG boundary scan

Digital decimation and filtering circuitry provided on-chip

remove unwanted signals and noise outside the channel of

interest. Programmable RAM coefficient filters allow antialiasing,

matched filtering, and static equalization functions to be combined

in a single cost-effective filter. The output of the channel filters

is provided to the user via serial output I/Q data streams.

APPLICATIONS

PHS or GSM/EDGE single carrier, diversity receivers

Microcell and picocell systems

Wireless local loop

FUNCTIONAL BLOCK DIAGRAM

TWEAK GAIN

AD6650 GSM/

EDGE IF RECEIVER

DAC

I

AGC

RELIN

CTRL

LP

FILTER

LPF

TH

4

7

PROG.

FIR

(RCF)

AIN

FINE

DCC

12-BIT

ADC

COARSE

DCC

ORDER

CIC

ORDER

IIR

MUX

Q

BIST

VGA

SCLK

SDFS

SDO0

CPOUT

LF

0

PLL/

VCO

SERIAL

PORT

/4

REF

90

VLDO

SDO1

DR

Q

LPF

TH

4

ORDER

CIC

TH

7

ORDER

IIR

PROG.

FIR

(RCF)

BIN

FINE

DCC

12-BIT

ADC

COARSE

DCC

VGA

MUX

BIST

I

AGC

RELIN

CTRL

LP

FILTER

DAC

TWEAK GAIN

CLK

DIVIDER

JTAG

MICRO

Figure 1.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

AD6650

TABLE OF CONTENTS

Features .............................................................................................. 1

LO Synthesis................................................................................ 22

LDO.............................................................................................. 23

AGC Loop/Relinearization ....................................................... 23

Serial Output Data Port............................................................. 24

Application Information................................................................ 26

Applications....................................................................................... 1

Product Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Explanation of Test Levels........................................................... 3

AC Specifications.......................................................................... 3

Digital Specifications ................................................................... 4

Electrical Characteristics............................................................. 5

General Timing Characteristics ................................................. 5

Microprocessor Port Timing Characteristics ........................... 6

Timing Diagrams.......................................................................... 7

Absolute Maximum Ratings.......................................................... 10

Thermal Characteristics ............................................................ 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

Typical Performance Characteristics ........................................... 13

Terminology .................................................................................... 14

Equivalent Circuits......................................................................... 15

Theory of Operation ...................................................................... 16

Analog Front End....................................................................... 16

Digital Back End......................................................................... 16

DC Correction ............................................................................ 16

Fourth-Order Cascaded Integrator Comb Filter (CIC4)...... 17

Infinite Impulse Response (IIR) Filter..................................... 18

RAM Coefficient Filter.............................................................. 18

Composite Filter ......................................................................... 19

Fine DC Correction ................................................................... 20

Peak Detector DC Correction Ranging................................... 20

User-Configurable Built-In Self-Test (BIST).......................... 21

Required Settings and Start-up Sequence for DC Correction

....................................................................................................... 26

Clocking the AD6650 ................................................................ 26

Driving the Analog Inputs ........................................................ 27

External Reference ..................................................................... 27

Power Supplies............................................................................ 27

Digital Outputs ........................................................................... 28

Grounding................................................................................... 28

Layout Information.................................................................... 28

Chip Synchronization................................................................ 29

Microport Control.......................................................................... 30

External Memory Map .............................................................. 30

Access Control Register (ACR) ................................................ 30

Channel Address Register (CAR) ............................................ 30

Special Function Registers ........................................................ 30

Data Address Registers.............................................................. 31

Write Sequencing ....................................................................... 31

Read Sequencing ........................................................................ 31

Read/Write Chaining................................................................. 31

Programming Modes................................................................. 31

JTAG Boundary Scan................................................................. 32

Register Map ................................................................................... 33

Register Details........................................................................... 39

Outline Dimensions....................................................................... 44

Ordering Guide .......................................................................... 44

REVISION HISTORY

1/07—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Changes to Specifications................................................................ 3

Changes to Figure 18...................................................................... 13

Changes to Power Supplies Section.............................................. 27

Changes to Ordering Guide .......................................................... 44

3/06—Revision 0: Initial Version

Rev. A | Page 2 of 44

AD6650

SPECIFICATIONS

EXPLANATION OF TEST LEVELS

I. 100% production tested.

II. 100% production tested at 25°C; sample tested at specified temperatures.

III. Sample tested only.

IV. Parameter guaranteed by design and analysis.

V. Parameter is typical value only.

VI. 100% production tested at 25°C; sample tested at temperature extreme.

VII. 100% production tested at +85°C.

C_LOAD= 40 pF on all outputs, unless otherwise specified. All timing specifications valid over VDD range of 3.0 V to 3.45 V and VDDIO

range of 3.0 V to 3.45 V.

AC SPECIFICATIONS

AVDD and DVDD = 3.3 V, CLK = 52 MSPS (driven differentially), 50% duty cycle, unless otherwise noted. All minimum ac

specifications are guaranteed from −25°C to +85°C. AC minimum specifications degrade slightly from −25°C to −40°C.

Table 1.

Parameter

Temp

Test Level

Min

Typ

Max

Unit

OVERALL FUNCTION

Frequency Range

GAIN CONTROL

Gain Step Size

Gain Step Accuracy

AGC Range

Full

V

70

260

MHz

25°C

V

0.094

0.047

36

dB

BASEBAND FILTERS

Bandwidth

Full

25°C

IV

V

3.36

3.5

77

3.64

MHz

dB

Alias Rejection at 25.9 MHz

LO PHASE NOISE

At 10 kHz Offset

At 20 kHz Offset

At 50 kHz Offset

At 100 kHz Offset

At 200 kHz Offset

At 400 kHz Offset

At 600 kHz Offset

At 800 kHz Offset

At 1600 kHz Offset

At 3000 kHz Offset

GAIN ERROR

25°C

V

−79

−87

dBc/Hz

dB

−103

−112

−119

−125

−130

−133

−138

−143

−0.7

PSRR (AVDD with 20 mV RMS Ripple)¹

At 5 kHz

At 10 kHz

At 50 kHz

At 100 kHz

25°C

V

−13.4

−17

−34

−39.8

−45.7

dBc

At 150 kHz

f = 70 MHz

Coarse DC Correction

Noise Figure²

V

IV

V

−70

10

43

−9.5

−49

4

189.6 − j33.6

dB

Input IP2²

Full

24

−15

dBm

dBc

dBm

Ω

Input IP3²

Image Rejection

Full-Scale Input Power

Input Impedance

−33

V

Rev. A | Page 3 of 44

AD6650

Parameter

Temp

Test Level

Min

Typ

Max

Unit

f = 150 MHz

Coarse DC Correction

Noise Figure²

V

IV

V

−70

10

37

−11.5

−46.5

4

169.3 − j59.2

dB

Input IP2²

Full

24

−15

dBm

dBc

dBm

Ω

Input IP3²

Image Rejection

Full-Scale Input Power

Input Impedance

f = 200 MHz

−33

V

Coarse DC Correction

Noise Figure²

V

IV

V

−70

10

35

−12

−46.5

4

159.3 − j66.9

dB

Input IP2²

Full

24

−16

dBm

dBc

dBm

Ω

Input IP3²

Image Rejection

Full-Scale Input Power

Input Impedance

f = 250 MHz

−33

V

Coarse DC Correction

Noise Figure²

V

VII

V

−70

10

33

−13

−45

4

137.1 − j72.7

dB

Input IP2²

Full

24

−16

dBm

dBc

dBm

Ω

Input IP3²

Image Rejection

Full-Scale Input Power

Input Impedance

−33

V

¹See Figure 40 and Figure 41 for additional PSRR specifications.

²This measurement applies for maximum gain (36 dB).

DIGITAL SPECIFICATIONS

AVDD and DVDD = 3.3 V, CLK = 52 MSPS, unless otherwise noted.

Table 2.

Parameter

Temp

Full

Test Level

Min

3.0

Typ

Max

3.45

+85

Unit

DVDD

IV

3.3

+25

V

°C

AVDD

T_AMBIENT

1

−25

¹The AD6650 is guaranteed fully functional from −40°C to +85°C. All ac minimum specifications are guaranteed from −25°C to +85°C, but degrade slightly from −25°C

to −40°C.

Rev. A | Page 4 of 44

AD6650

ELECTRICAL CHARACTERISTICS

Table 3.

Parameter (Conditions)

Temp

Test Level

Min

Typ

Max

Unit

LOGIC INPUTS

Logic Compatibility

Digital Logic

Full

IV

3.3 V CMOS

Logic 1 Voltage

Logic 0 Voltage

Logic 1 Current

Logic 0 Current

Full

25°C

IV

V

2.0

0

VDD

0.8

V

μA

pF

60

7

5

Input Capacitance

CLOCK INPUTS

Differential Input Voltage¹

Common-Mode Input Voltage

Differential Input Resistance

Differential Input Capacitance

LOGIC OUTPUTS

Logic Compatibility

Logic 1 Voltage (I_OH= 0.25 mA)

Logic 0 Voltage (I_OL= 0.25 mA)

IDD SUPPLY CURRENT

CLK = 52 MHz (GSM Example)

I_DVDD

25°C

V

0.4

2.4

3.6

V p-p

V

kΩ

pF

DVDD/2

7.5

5

Full

3.3 V CMOS/TTL

VDD − 0.2

0.2

IV

V

0.8

2.1

Full

VII

155

360

mA

I_AVDD

POWER DISSIPATION

CLK = 52 MHz (GSM/EDGE Example)

Full

VII

1.7

W

1

CLK

All ac specifications are tested by driving CLK and

differentially.

GENERAL TIMING CHARACTERISTICS

Table 4.

Parameter (Conditions)

CLK TIMING REQUIREMENTS

CLK Period¹

CLK Width Low

CLK Width High

Symbol Temp Test Level Min Typ

Max Unit

t_CLK

t_CLKL

t_CLKH

Full

I

IV

9.6

19.2 ns

0.5 × t_CLK

ns

RESET TIMING REQUIREMENTS

RESET Width Low

t_SSF

Full

IV

30

ns

PIN_SYNC TIMING REQUIREMENTS

SYNC to ↑ CLK Setup Time

SYNC to ↑ CLK Hold Time

t_SS

Full

IV

−3

6

ns

t_HS

SERIAL PORT TIMING REQUIREMENTS: SWITCHING CHARACTERISTICS²

↑ CLK to ↑ SCLK Delay (Divide-by-1)

↑ CLK to ↑ SCLK Delay (For Any Other Divisor)

↑ CLK to ↓ SCLK Delay (Divide-by-2 or Even Number)

↓ CLK to ↓ SCLK Delay (Divide-by-3 or Odd Number)

↑ SCLK to SDFS Delay

t_DSCLK1

t_DSCLKH

t_DSCLKL

t_DSCLKLL

t_DSDFS

t_DSDO0

t_DSDO1

t_DSDR

Full

IV

3.2

4.4

4.7

4

12.5 ns

16

ns

16

14

1

2.6

3.5

0.5

1

↑ SCLK to SDO0 Delay

↑ SCLK to SDO1 Delay

↑ SCLK to DR Delay

¹Minimum specification is based on a 104 MSPS clock rate (an internal divide-by-2 must be used with a 104 MSPS clock rate); maximum specification is based on a

52 MSPS clock rate. This device is optimized to operate at a clock rate of 52 MSPS or 104 MSPS.

²The timing parameters for SCLK, SDFS, SDO0, SDO1, and DR apply to both Channel 0 and Channel 1.

Rev. A | Page 5 of 44

AD6650

MICROPROCESSOR PORT TIMING CHARACTERISTICS

All timing specifications valid over VDD range of 3.0 V to 3.45 V and VDDIO range of 3.0 V to 3.45 V.

Table 5. Microprocessor Port, Mode INM (MODE = 0); Asynchronous Operation

Parameter

Symbol Temp

Test Level

Min

Typ

Max

Unit

WRITE TIMING

WR (R/W) to RDY (DTACK) Hold Time¹

Address/Data to WR (R/W) Setup Time¹

Address/Data to RDY (DTACK) Hold Time¹

WR (R/W) to RDY (DTACK) Delay

WR (R/W) to RDY (DTACK) High Delay¹

t_HWR

t_SAM

t_HAM

t_DRDY

t_ACC

Full

IV

0.0

ns

0.0

2

9.0

15.0

4 × t_CLK

13 × t_CLK

READ TIMING

Address to RD (DS) Setup Time¹

Address to Data Hold Time¹

Data Three-state Delay¹

RDY (DTACK) to Data Delay¹

RD (DS) to RDY (DTACK) Delay

RD (DS) to RDY (DTACK) High Delay¹

t_SAM

t_HAM

t_ZD

Full

IV

V

IV

0.0

ns

12

t_DD

0.0

2

t_DRDY

t_ACC

9.0

15.0

4 × t_CLK

13 × t_CLK

¹Timing is guaranteed by design.

2

W WR DS RD

CS

Specification pertains to control signals R/ , and such that the minimum specification is valid after the last control signal has reached a valid logic level.

,

Table 6. Microprocessor Port, Mode MNM (MODE = 1)

Parameter

Symbol

Temp

Test Level

Min

Typ

Max

Unit

WRITE TIMING

DS (RD) to DTACK (RDY) Hold Time

R/W (WR) to DTACK (RDY) Hold Time

Address/Data to R/W (WR) Setup Time¹

Address/Data to R/W (WR) Hold Time¹

DS (RD) to DTACK (RDY) Delay²

R/W (WR) to DTACK (RDY) Low Delay¹

t_HDS

Full

IV

V

15.0

0.0

ns

t_HRW

t_SAM

t_HAM

t_DDTACK

t_ACC

0.0

16

IV

4 × t_CLK

13 × t_CLK

READ TIMING

DS (RD) to DTACK (RDY) Hold Time

Address to DS (RD) Setup Time¹

Address to Data Hold Time¹

Data Three-State Delay

DTACK (RDY) to Data Delay¹

DS (RD) to DTACK (RDY) Delay²

DS (RD) to DTACK (RDY) Low Delay¹

t_HDS

t_SAM

t_HAM

t_ZD

Full

IV

V

IV

V

15.0

0.0

ns

0.0

13

16

t_DD

0.0

t_DDTACK

t_ACC

IV

4 × t_CLK

13 × t_CLK

¹Timing is guaranteed by design.

²DTACK

is an open-drain device and must be pulled up with a 1 kΩ resistor.

Rev. A | Page 6 of 44

AD6650

TIMING DIAGRAMS

RESET

t_SSF

RESET

Figure 2.

Timing Requirements

CLK

t_DSCLKH

SCLK

Figure 3. SCLK Switching Characteristics (Divide-by-1)

CLK

t_DSCLKH

t_DSCLKL

SCLK

Figure 4. SCLK Switching Characteristics (Divide-by-2 or Even Integer)

CLK

t_DSCLKH

t_DSCLKLL

SCLK

Figure 5. SCLK Switching Characteristics (Divide-by-3 or Odd Integer)

SCLK

t_DSDR

DR

Figure 6. SCLK, DR Switching Characteristics

SCLK

t_DSDFS

SDFS

Figure 7. SCLK, SDFS Switching Characteristics

SCLK

t_DSD0/t_DSD1

SDO0/SDO1

Figure 8. SCLK, SDO0/SDO1 Switching Characteristics

Rev. A | Page 7 of 44

AD6650

CLK

t_SS

t_HS

SYNC

Figure 9. SYNC Timing Inputs

RD (DS)

t_HWR

WR (R/W)

CS

t_SAM

VALID ADDRESS

t_HAM

A[2:0]

t_SAM

t_HAM

VALID DATA

D[7:0]

t_DRDY

RDY

(DTACK)

t_ACC

NOTES

1. t_ACCACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED

FROM FALLING EDGE OF WR TO RISING EDGE OF RDY.

2. t_ACCREQUIRES A MAXIMUM OF NINE CLK PERIODS.

Figure 10. INM Microport Write Timing Requirements

RD (DS)

WR (R/W)

CS

t_SAM

A[2:0]

VALID ADDRESS

t_HAM

t_ZD

t_DD

D[7:0]

VALID DATA

t_DRDY

RDY

(DTACK)

t_ACC

NOTES

1. t_ACCACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED

FROM FALLING EDGE OF RD TO RISING EDGE OF RDY.

2. t_ACCREQUIRES A MAXIMUM OF 13 CLK PERIODS.

Figure 11. INM Microport Read Timing Requirements

Rev. A | Page 8 of 44

AD6650

t_HDS

DS (RD)

t_HRW

R/W (WR)

CS

t_SAM

VALID ADDRESS

t_SAM

t_HAM

A[2:0]

D[7:0]

VALID DATA

t_DDTACK

DTACK

(RDY)

t_ACC

NOTES

1. t_ACCACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED

FROM FALLING EDGE OF DS TO FALLING EDGE OF DTACK.

2. t_ACCREQUIRES A MAXIMUM OF NINE CLK PERIODS.

Figure 12. MNM Microport Write Timing Requirements

t_HDS

DS (RD)

R/W (WR)

CS

t_SAM

A[2:0]

D[7:0]

VALID ADDRESS

t_HAM

t_ZD

t_DD

t_ZD

VALID DATA

t_DDTACK

DTACK

(RDY)

t_ACC

NOTES

1. t_ACCACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED

FROM FALLING EDGE OF DS TO THE FALLING EDGE OF DTACK.

2. t_ACCREQUIRES A MAXIMUM OF 13 CLK PERIODS.

Figure 13. MNM Microport Read Timing Requirements

Rev. A | Page 9 of 44

AD6650

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

Table 7.

121-lead chip scale package ball grid array:

Parameter

Rating

Supply Voltage

Input Voltage

−0.3 V to +3.6 V

−0.3 V to VDDIO + 0.3 V

200 pF

125°C

−65°C to +150°C

280°C

θ_JA= 22.8°C/W, no airflow, measurements made in the

horizontal position on a 4-layer board.

θ_JA= 20.2°C/W, 200 LFPM airflow, measurements made in the

horizontal position on a 4-layer board.

θ_JA= 20.7°C/W, no airflow, soldered on an 8-layer board with

two layers dedicated as ground planes.

Output Voltage Swing

Load Capacitance

Junction Temperature Under Bias

Storage Temperature Range

Lead Temperature (5 sec)

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

Rev. A | Page 10 of 44

AD6650

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

A1 CORNER

INDEX AREA

1

2 5

3 4 6

8 10 11

7 9

A

B

C

D

E

F

G

H

J

K

L

AD6650

TOP VIEW

(Not to Scale)

Figure 14. Pin Configuration

Table 8. Pin Configuration

1

2

3

4

5

6

7

8

9

10

11

DGND

SDFS

SDO1

D7

D5

D3

TDI

TMS

TRST

RESET

SYNC

DVDD

DGND

DVDD

CHIP_ID1

CHIP_ID0

5

DNC

DVDD

DGND

DVDD

DNC

6

AVDD

7

CLK

AGND

DNC

AGND

10

AGND

BIN

A

B

C

D

E

A

B

C

D

E

SCLK

TDO

TCLK

AVDD

REFGND

VREF

8

AGND

REFT

REFB

9

SDO0

DR

D6

D4

D2

D0

DVDD

CS

DVDD

DGND

DVDD

MODE1

MODE0

4

BIN

AGND

LF

VLDO

CPOUT

AGND

AIN

F

D1

G

H

J

G

H

J

DS (RD)

R/W (WR)

A2

DTACK (RDY)

A1

A0

2

AIN

K

L

K

L

DGND

1

MODE2

3

AGND

11

Table 9. Pin Function Descriptions

Mnemonic

POWER SUPPLY

DVDD

AVDD

DGND

Type

Description

No. of Pins

Power

Ground

3.3 V Digital Supply.

3.3 V Analog Supply.

Digital Ground.

13

19

17

22

AGND

Analog Ground.

DIGITAL INPUTS

RESET

Input

Active Low Reset Pin.

Synchronizes Digital Filters.

Chip ID.

1

2

SYNC

CHIP_ID[1:0]

SERIAL DATA PORT

SCLK

SDFS

SDO[1:0]

DR

Bidirectional Serial Clock.

Bidirectional Serial Data Frame Sync.

Output

1

2

1

Serial Data Outputs. Three-stated when inactive.

Output Data Ready Indicator.

MICROPORTCONTROL

D[7:0]

A[2:0]

Bidirectional Microport Data.

8

3

1

Input

Microport Address Bits.

Chip Select.

CS

DS (RD)

Active Low Data Strobe (Active Low Read).

Rev. A | Page 11 of 44

AD6650

Mnemonic

Type

Description

No. of Pins

DTACK (RDY)

Output

Active Low Data Acknowledge (Microport Status Bit). Open-drain output, requires

external pull-up resistor of 1 kΩ.

1

R/W (WR)

Input

Read Write (Active Low Write).

Selects Control Port Mode.

1

3

MODE [2:0]

JTAG

TRST

Input

Output

Input

Test Reset Pin.

1

TCLK

TMS

TDO

TDI

Test Clock Input.

Test Mode Select Input.

Test Data Output. Three-stated when JTAG is in reset.

Test Data input.

ANALOG INPUTS

AIN

BIN

Input

Main Analog Input.

Complement of AIN. Differential analog input.

Diversity Analog Input.

1

Complement of BIN. Differential analog input.

PLL INPUTS

CPOUT

LF

Output

Input

Output

Charge-Pump Output.

Loop Filter.

Compensation for Internal Low Dropout Regulator. Bypass to ground with a 220

nF chip capacitor.

1

VLDO

REFT

REFB

VREF

Output

Ground

Internal ADC Voltage Reference. Bypass to ground with capacitors. See Figure 39

for recommended connection.

Internal ADC Voltage Reference. Bypass to ground with capacitors. See Figure 39

for recommended connection.

Internal ADC Voltage Reference. Bypass to ground with capacitors. See Figure 39

for recommended connection.

ADC Ground Reference. See Figure 39 for recommended connection.

1

REFGND

CLOCK INPUTS

CLK

Input

Encode Input. Conversion initiated on rising edge.

Complement of Encode.

1

5

CLK

DNC

Do Not Connect.

Rev. A | Page 12 of 44

AD6650

TYPICAL PERFORMANCE CHARACTERISTICS

–44

–45

44

–25°C

42

+25°C

–46

–47

–48

–49

40

+85°C

–25°C

38

36

34

+85°C

–50

–51

32

30

70

90

110

130

150

170

190

210

230

250

70

90

110

130

150

170

190

210

230

250

IF FREQUENCY (MHz)

Figure 17. Image vs. Frequency

Figure 15. Input IP2 vs. Frequency

–6

0.2

0

–7

–8

–25°C

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–9

–10

+25°C

+85°C

+25°C

+85°C

–11

–12

–13

–14

–15

–25°C

70

90

110

130

150

170

190

210

230

250

70

90

110

130

150

170

190

210

230

250

IF FREQUENCY (MHz)

Figure 16. Input IP3 vs. Frequency

Figure 18. Gain Error vs. Frequency

Rev. A | Page 13 of 44

AD6650

TERMINOLOGY

Analog Bandwidth

Image

The analog input frequency at which the spectral power of the

fundamental frequency (as determined by the FFT analysis) is

reduced by 3 dB.

The AD6650 incorporates a quadrature demodulator that mixes

the IF frequency to a baseband frequency. The phase and amplitude

imbalance of this quadrature demodulator is observed in a complex

FFT as an image of the fundamental frequency. The term image

arises from the mirror-like symmetry of signal and image

frequencies about the beating-oscillator frequency (in this

case, this is dc).

Noise Figure (NF)

The degradation in SNR performance (in dB) of an IF input

signal after it passes through a component or system.

The AD6650 noise figure is determined by the equation

Differential Analog Input Resistance, Differential Analog

Input Capacitance, and Differential Analog Input Impedance

The real and complex impedances measured at each analog

input port. The resistance is measured statically, and the

capacitance and differential input impedances are measured

with a network analyzer.

2

⎛

⎞

⎛

⎜

⎝

⎞

⎟

⎠

V

Z_in

kTB

0.001

rms

⎛

⎜

⎝

⎞

⎟

⎠

⎜

⎟

NF = 10 log

− SNR_FS−10 log

(1)

⎜

⎝

⎟

⎠

0.001

where:

k is the Boltzmann constant = 1.38 × 10⁻²³

T is the temperature in kelvin.

.

Differential Analog Input Voltage Range

B is the channel bandwidth in hertz (200 kHz typical).

The peak-to-peak differential voltage that must be applied to

the converter to generate a full-scale response. Peak differential

voltage is computed by observing the voltage on a single pin

and subtracting the voltage from the other pin, which is 180°

out of phase. The peak-to-peak differential voltage is computed

by rotating the phases of the inputs 180° and taking the peak

measurement again. Then the difference is computed between

both peak measurements.

V²_rmsis the full-scale input voltage.

Z_inis the input impedance.

SNR_FSis the computed signal-to-noise ratio referred to full scale

with a small input signal and the AD6650 in maximum gain.

Input Second-Order Intercept (IIP2)

A figure of merit used to determine a component’s or system’s

susceptibility to intermodulation distortion (IMD) from its

second-order nonlinearities. Two unmodulated carriers at a

specified frequency relationship (f1 and f2) are injected into a

nonlinear system exhibiting second-order nonlinearities

producing IMD components at f1 − f2 and f2 − f1. IIP2

graphically represents the extrapolated intersection of the

carrier’s input power with the second-order IMD component

when plotted in decibels.

Full-Scale Input Power

Expressed in dBm. It is computed using the following equation:

2

⎛

⎜

⎞

⎟

V

Full scale

rms

Z_Input

⎜

⎟

Power_{Full scale}=10 log

(2)

0.001

⎜

⎝

⎟

⎠

Input Third-Order Intercept (IIP3)

where Z_Inputis the input impedance.

A figure of merit used to determine a component’s or system’s

susceptibility to intermodulation distortion (IMD) from its

third-order nonlinearities. Two unmodulated carriers at a

specified frequency relationship (f1 and f2) are injected into a

nonlinear system exhibiting third-order nonlinearities

producing IMD components at (2 × f1) – f2 and (2 × f2) – f1.

IIP3 graphically represents the extrapolated intersection of the

carrier’s input power with the third-order IMD component

when plotted in decibels.

Noise

The noise, including both thermal and quantization noise, for

any range within the ADC is computed as

FS

− SNR

− Signal

⎛

⎞

dBm

dBc dBFS

10

⎟

V_noise

where:

Z is the input impedance.

=

Z × 0.001×10^⎜^⎝^⎜

(3)

⎠

FS_dBmis the full scale of the device for the frequency in question.

SNR_dBcis the value for the particular input level.

Signal_dBFSis the signal level within the ADC reported in decibels

below full scale.

Rev. A | Page 14 of 44

AD6650

EQUIVALENT CIRCUITS

1nH

AIN/BIN

25Ω

75Ω

1.3V

CLAMP 1pF

2pF

75Ω

25Ω

1nH

AIN/BIN

Figure 19. Analog Input

AVDD

20kΩ

5kΩ

2.5kΩ

CLK

5pF

5kΩ

2.5kΩ

20kΩ

CLK

20kΩ

Figure 20. Clock Input

Rev. A | Page 15 of 44

AD6650

THEORY OF OPERATION

that the total AD6650 response is unchanged. The 19-bit output of

the AGC block is then decimated and filtered using the CIC4 filter,

the IIR filter, and the programmable RAM coefficient filter (RCF).

Either 16-bit or 24-bit data is output through the serial port.

With the 36 dB VGA gain, 12-bit ADC performance, and

approximately 21 dB of processing gain, the AD6650 is capable

of delivering approximately 116 dB of dynamic range or 19 bits

of performance. For this reason, it is recommended that the

24-bit serial output be used so that dynamic range is not lost.

ANALOG FRONT END

The AD6650 is a mixed-signal front-end (MxFE®) component

intended for direct IF sampling radios requiring high dynamic

range. It is optimized for the demanding performance require-

ments of GSM and EDGE.

The AD6650 has five signal processing stages: a digital VGA,

I/Q demodulators, seventh-order low-pass filters, dual ADCs,

and digital filtering. Programming and control are accom-

plished via a microprocessor interface.

A block diagram of the digital signal path is shown in Figure 21.

DVGA

AGC

RELIN

CTRL

LP

FILTER

A gain-ranging digital VGA is used to extend the dynamic

range of the ADC and minimize signal clipping at the ADC

input. The VGA has a maximum gain of 36 dB with a nominal

step size of 0.094 dB. The amplifier serves as the input stage to

the AD6650 and has a nominal input impedance of 200 Ω and a

4 dBm maximum input.

DITHER

GEN.

TH

4

7

PROG.

FIR

(RCF)

FINE

DCC

COARSE

DCC

ORDER

CIC

ORDER

IIR

BIST

SPORT

Figure 21. Channel Digital Signal Path

I/Q Demodulators

DC CORRECTION

Frequency translation is accomplished with I/Q demodulators.

Real data entering this stage is separated into in-phase (I) and

quadrature (Q) components. This stage translates the input

signal from an intermediate frequency (IF) of 70 MHz to

260 MHz to a baseband frequency.

The dc offset in the analog path of the AD6650 comes from

three sources: the analog baseband filters, the ADCs, and the

LO leakage of the mixers. The dc offsets of the analog filters and

the ADCs dominate that of the LO leakage. The dc offsets on

the I and Q data for both Channel A and Channel B are

different because they use different analog paths. Each path is

corrected independently.

Low-Pass Filters

In each I/Q signal path is a seventh-order low-pass active filter

with 3.5 MHz bandwidth and automatic resistance-capacitance

calibration to 4%. This filter typically offers greater than 70 dB

of alias rejection at 25.9 MHz.

The typical uncorrected dc offset is between −32 dB and −35 dB

relative to full scale (dBFS) of the ADC. When the AGC range is

considered along with this offset, the dc is effectively slid down by

the gain setting so that it is approximately −68 dBFS to −71 dBFS

or smaller when the AD6650 is in maximum gain.

Dual ADCs

The AD6650 has two ADCs. Each is implemented with an

AD9238 core preceded by dual track-and-holds that multiplex

in the I and Q signals at 26 MSPS each. The full-scale input

power into the ADC is 4 dBm.

0

–10

–20

–30

–40

–50

–60

–70

–80

DC OFFSET

DIGITAL BACK END

The 12-bit ADC data goes through the coarse dc correction

block, which performs a one-time calibration of the dc offsets in

the I and Q paths. The output of this block drives the automatic

gain control (AGC) loop block, which adjusts the digitally

controlled VGA in the analog path. The AGC adjusts the amplitude

of the incoming signal of interest to a programmable level and

prevents the ADC from clipping. The gain of the VGA is subtracted

in the relinearization block so that externally the AD6650 appears

to have constant gain. For example, if the VGA must increase the

gain from 20 dB to 30 dB due to a decrease in the signal power,

the relinearization word changes from a −20 dB to a −30 dB gain so

–90

–100

–110

–120

–130

–140

–150

–160

–170

–180

FREQUENCY (MHz)

Figure 22. Uncorrected DC Offset

Rev. A | Page 16 of 44

AD6650

Coarse DC Correction

given by Equation 6 and Equation 7. The gain and pass-band

droop of the CIC4 can be calculated using these equations. If the

gain and/or droop of the CIC4 filter are not acceptable, they can

be compensated for in the programmable RCF filter stage.

The coarse dc correction block is a simple integrate-and-dump

that integrates the data for 16,384 cycles at the ADC clock rate

(typically 26 MSPS) and then updates an estimate of the dc. This

estimate is then subtracted from the signal path. The signal is

clipped after the subtraction to avoid numerical wrap around

with large signals.

4

1 − Z ^−M

1 − Z ⁻¹

CIC4

⎛

⎜

⎝

⎞

⎟

⎠

1

CIC4

(

Z

)

=

×

× CIC _ Gain

(6)

M_CIC4

4

The −32 dBFS to −35 dBFS uncorrected offset is sufficient to

demodulate large signals, but it does not leave any margin if

30 dB of signal-to-dc is desired. It is essential to consider the dc

offset of the signal at the point where the AGC of the AD6650

begins to range. This is important because once the signal or a

blocker is in the range of the AGC loop, the dc signal that appears

at the output of the AD6650 is modulated by the change in gain

of the loop. If the gain decreases, the signal at the output remains

at the same power level due to the digital relinearization, but the

dc signal at the output is gained up by the relinearization process.

For this reason, the coarse dc correction is used to provide addi-

tional correction before relinearizing the data to provide additional

margin. This block gains another 5 dB to 8 dB (sometimes up to

25 dB) of dc rejection that provides additional margin.

⎛

⎜

⎞

⎟

f × M_CIC4

⎛

⎜

⎝

⎞

⎟

⎠

⎜

sin π ×

⎜

⎝

⎟

⎠

f _ADC

1

CIC4

(

f

)

=

×

× CIC _ Gain (7)

M

⎛

⎞

⎟

⎠

f

CIC4

⎜

sin π ×

⎜

⎝

f _ADC

The output rate of this stage is given by Equation 8.

f_ADC

f_SAMP4

≤

(8)

M_CIC4

CIC4 Rejection

Table 10 shows the amount of bandwidth as a percentage of the

input sample rate (ADC sample rate) that can be protected with

various decimation rates and alias rejection specifications. The

maximum input rate into the CIC4 is 26 MHz. Table 10 shows

the half-bandwidth characteristics of the CIC4.

The coarse dc correction is provided for two reasons:

•

To provide additional margin on the carrier-to-dc term for

large input signals.

Table 10. SSB CIC4 Alias Rejection Table

dB

•

To provide more range for the fine dc correction upper

threshold by decreasing the total input power to the block

for small input signals. (This is described in more detail in

the Fine DC Correction section.)

Rate

8

−50

−60

−70

−80

−90

−100

0.651

0.581

0.525

0.478

0.439

0.406

0.378

0.353

0.331

0.312

0.295

0.279

0.265

0.253

0.241

0.231

0.221

0.212

0.204

0.197

0.190

0.183

0.177

0.171

0.166

2.494

2.224

2.006

1.827

1.676

1.549

1.439

1.344

1.261

1.187

1.122

1.063

1.010

0.962

0.919

0.879

0.842

0.809

0.778

0.749

0.722

0.697

0.674

0.653

0.632

1.921

1.713

1.546

1.408

1.292

1.194

1.110

1.037

0.972

0.916

0.865

0.820

0.779

0.742

0.709

0.678

0.650

0.624

0.600

0.578

0.557

0.538

0.520

0.503

0.488

1.473

1.315

1.187

1.081

0.992

0.917

0.852

0.796

0.747

0.703

0.665

0.630

0.599

0.570

0.544

0.521

0.499

0.479

0.461

0.444

0.428

0.413

0.400

0.387

0.375

1.128

1.007

0.909

0.828

0.760

0.703

0.653

0.610

0.572

0.539

0.509

0.483

0.459

0.437

0.417

0.399

0.383

0.367

0.353

0.340

0.328

0.317

0.306

0.297

0.287

0.860

0.768

0.693

0.632

0.580

0.536

0.499

0.466

0.437

0.411

0.389

0.369

0.350

0.334

0.319

0.305

0.292

0.281

0.270

0.260

0.251

0.242

0.234

0.226

0.219

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

FOURTH-ORDER CASCADED INTEGRATOR COMB

FILTER (CIC4)

The CIC4 processing stage implements a fixed-coefficient

decimating filter. It reduces the sample rate of the signal and

allows subsequent filtering stages to be implemented more

efficiently. The input of the CIC4 is driven by the 19-bit relinearized

data at a maximum input rate of 26 MHz (52 MHz clock rate).

The CIC4 decimation ratio, M_CIC4, can be programmed from

8 to 32 (all integer values). The CIC4 scale factor, S_CIC4, is a

programmable unsigned integer between 0 and 8. It serves to

control the attenuation of the data into the CIC4 stage in 6 dB

increments such that the CIC4 does not overflow. Because this

scale factor is in 6 dB steps, the CIC4 filter has a gain between

0 dB and −6.02 dB when properly scaled. For the best dynamic

range, S_CIC4should be set to the smallest value possible (lowest

attenuation) without creating an overflow condition.

S_CIC4= Ceil

(

4 × log₂

(

4

M_CIC4

)

− 12

(4)

M_CIC4

CIC _ Gain =

(5)

+ 12

2^S

CIC4

Table 10 enables the calculation of an upper bound on the

decimation ratio (M_CIC4), given the desired filter characteristics

and input sample rate.

The value of 12 that is subtracted in Equation 4 comes from the

amount of scaling needed to compensate for the minimum

decimation of 8. The frequency response of the CIC4 filter is

Rev. A | Page 17 of 44

AD6650

the band of interest is essentially perfect. From −100 kHz to

+100 kHz, the phase distortion is ~0.056° rms. This phase

response is several orders of magnitude below the analog LO

and analog filter phase distortions.

INFINITE IMPULSE RESPONSE (IIR) FILTER

The IIR filter of the AD6650 is a seventh-order low-pass filter

with an infinite impulse response. This filter cannot be bypassed

and always performs a decimation of 2. As can be seen from the

Z-transform, the IIR filter has a gain of −6.02 dB to accommodate

signal peaking within the structure. It is designed to be free of

limit cycles and is unconditionally stable. The IIR filter is

described by the Z-transform and coefficients shown in the

following equation:

0.001

–4

6 × 10

–4

IIR PHASE RESPONSE

2 × 10

–2 × 10

–6 × 10

(

n₀× z⁷+ n₂× z⁵+ n₃× z³+ n₁× z + n₁× z⁶+ n₃× z⁴+ n₂× z²+ n₀

)

IIR z =

( )

(

d₇× z⁷+ d₅× z⁵+ d₃× z³+ d₁× z

)

× 2

–4

(9)

where:

n₀= 0.046227

n₁= 0.278961

n₂= 0.76021

n₃= 1.208472

d₀= 0

d₁= 0.12895

d₂= 0

d₃= 0.254698

d₄= 0

–0.001

–100

–50

0

50

100

CHANNEL BW (kHz)

Figure 24. IIR Phase Response

RAM COEFFICIENT FILTER

The final signal processing stage is a sum-of-products decimating

filter with programmable coefficients (see Figure 25). The I-RAM

and Q-RAM data memories store the most recent complex

samples from the IIR filter with 23-bit resolution. The number

of samples stored in these memories is equal to the coefficient

length (N_taps), up to 48 taps. The coefficient memory, CMEM,

stores up to 48 coefficients with 20-bit resolution. On every

CLK (up to 52 MHz) cycle, one tap for I and one tap for Q are

calculated using the same coefficients. The RCF output consists

of 16-bit or 24-bit data.

d₅= 1.026276

d₆= 0

d₇= 1

Figure 23 shows the magnitude response of the IIR filter in a

typical GSM/EDGE case where the ADCs are sampling at

26 MHz and the CIC filter is decimating by 12 to generate a

2.16 MHz (8× symbol rate) input rate to the IIR.

28

0

–10

–20

–30

I IN

48 × 23

I-RAM

COARSE

SCALE

25

24

48 × 20

C-RAM

IIR RESPONSE

–40

–50

28

Q IN

48 × 23

Q-RAM

RND

WORD

–60

–70

Figure 25. Block Diagram of the RCF

–80

RCF Decimation Register

–90

Each RCF channel can decimate the data rate by a factor of 1 to

8. The decimation register is a 3-bit register. The RCF decimation is

stored in Address 0x18 in the form of M_RCF− 1. The input rate

–100

–110

–120

to the RCF is f_SAMPIIR

.

FREQUENCY (MHz)

RCF Decimation Phase Register

Figure 23. IIR Frequency Response

The AD6650 uses the value stored in this register to preload the

RCF counter. Therefore, instead of starting from 0, the counter

is loaded with this value, thus creating a time offset in the

output data. This data is stored in Address 0x19 as a 3-bit

number. Time delays can be achieved in even units of the RCF

input rate, which is typically ¼ of the symbol time for GSM.

Figure 24 shows the phase response of the IIR filter over the

range of 100 kHz after a time delay during which ~13.449 input

samples of the filter have been removed. The input rate is the

same 2.16 MHz from the above GSM/EDGE configuration.

Examining the plot shows that the IIR filter is not exactly phase

linear. (Linear phase would be flat after the time delay has been

removed). It can be seen, however, that the phase response over

Rev. A | Page 18 of 44

AD6650

RCF Filter Length

The output rate of this filter (f_SAMPR) is determined by the output

rate of the IIR stage and M_RCF

.

The maximum number of taps this filter can calculate, N_taps, is

given by Equation 10. The value N_taps− 1 is written to the

channel register within the AD6650 at Address 0x1B.

f_SAMPIIR

f_SAMPR

=

(11)

M_RCF

f

× M_RCF

⎛

⎜

⎝

⎞

⎟

⎠

CLK

where:

_SAMPIIRis the input rate to the RCF.

_RCFis the RCF filter decimation rate.

RCF Output Scale Factor and Control Register

N_taps≤ min

, 48

(10)

f_SAMPIIR

f

M

where:

_CLKis the external frequency oscillator.

_RCFis the RCF filter decimation rate.

_SAMPIIRis the input rate to the RCF.

f

M

f

Address 0x1C is used to configure the scale factor for the RCF

filter. This 2-bit register is used to scale the output data in 6 dB

increments. The possible output scales range from 0 dB to −18 dB.

The RCF coefficients are located in Address 0x40 to Address 0x6F,

and are interpreted as 20-bit twos complement numbers. When

writing the coefficient RAM, the lower addresses are multiplied

by relatively older data from the IIR, and the higher coefficient

addresses are multiplied by relatively newer data from the IIR.

The coefficients need not be symmetric, and the coefficient

length, N_taps, can be even or odd. If the coefficients are

symmetric, both sides of the impulse response must be written

into the coefficient RAM.

The AD6650 RCF uses a recirculating multiply accumulator

(MAC) to compute the filter. This accumulator has three bits of

growth, allowing the output of the accumulator to be up to eight

times as large as the input signal. To achieve the best filter

performance, the coefficients should be as large as possible

without overflowing the accumulator. The gain of a filter is

merely the sum of the coefficients; therefore, for normal steady

state signals, the sum of the coefficients must be less than 8. If

the sum of the coefficients is 8 or slightly less, very rare

transient events can overflow the accumulator. To prevent this,

the sum of the absolute values of the coefficients should be less

than 8. It is then impossible for the RCF filter to overflow.

The RCF stores the data from the IIR into a 46 × 48 RAM. A

RAM of 23 × 48 is assigned to I data, and a RAM of 23 × 48 is

assigned to Q data.

When the RCF is triggered to calculate a filter output, it starts

by multiplying the oldest value in the data RAM by the first

coefficient, which is pointed to by the RCF coefficient offset

register (Address 0x1A). This value is accumulated with the

products of newer data-words multiplied by the subsequent

locations in the coefficient RAM until the coefficient address

RCF_OFF+ N_taps− 1 is reached.

The RCF filter has a 4-position mux at the output of the

accumulator. This mux chooses which 24 bits are propagated to

the output and adjusts the rounding appropriately. This can be

viewed as a gain block that can be varied in 6 dB steps and is

controlled by the 2-bit RCF scale register.

The resulting gain of the RCF (RCFgain) is then represented by

the following equation:

Table 11. Three-Tap Filter

Coefficient Address

1

Impulse Response

Data

RCFgain = ∑ Coef ×

(12)

2^{3 − RCFScale}

0

1

h(0)

h(1)

h(2)

N(0) oldest

N(1)

N(2) newest

where RCFScale is the value in the RCF scale register.

2 = (N_taps− 1)

COMPOSITE FILTER

The total gain of the digital filters can be calculated with

Equation 13 and must be less than or equal to 1 (0 dB).

Typically, the RCF coefficient gain is scaled to compensate for

The RCF coefficient offset register can be used for two purposes.

The main purpose is to allow multiple filters to be loaded into

memory and selected simply by changing the offset. The other

is to contribute to the symbol timing adjustment. If the desired

filter length is padded with 0s on the ends, the starting point

can be adjusted to form slight delays in the time the filter is

computed with reference to the high speed clock. This allows

for vernier adjustment of the symbol timing. Coarse adjustments

can be made with the RCF decimation phase.

the gain of the CIC and IIR, and the RCF scale factor is set to 3.

4

M_CIC4

1

2

1

⎛

⎜

⎝

⎞

⎟

⎠

Gain =

×

∑ Coef ×

(13)

+ 12

2^S

2^{3 − RCFScale}

CIC 4

where:

Gain is the gain of the digital filters.

_CIC4is the CIC4 decimation ratio.

_CIC4is the CIC4 scale factor.

RCFScale is the value in the RCF scale register.

M

S

The individual responses of the CIC4 and IIR filters, along with

the composite response of all the filters, are shown in Figure 26.

Rev. A | Page 19 of 44

AD6650

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

⎛

⎜

⎝

⎞

⎟

⎠

f_BW

f_HPF

PG = 10 × log

(14)

where:

CIC4 RESPONSE

AD6650 DIGITAL

COMPOSITE

RESPONSE

f

_BWis the channel filter bandwidth.

_HPFis the HPF bandwidth.

IIR FILTER

RESPONSE

In the case of GSM, a simple HPF is not well suited to this

problem because the signal power can vary 50 dB or more from

time slot to time slot and has a total dynamic range of 91 dB or

more. A large time slot would excite the impulse response of the

HPF, possibly resulting in a peak occurring later when a small

time slot is present. To provide a more optimal dc correction,

the AD6650 adaptively adjusts the bandwidth of the HPF based

on the signal power. As the signal level decreases, the HPF

bandwidth increases. Conversely, as the signal level increases,

the HPF bandwidth decreases.

–120

–1.98

–1.46 –0.94 –0.43 0 17

0.61 1.13

1.65

2.17

FREQUENCY (MHz)

Figure 26. Composite Digital Response with 8× Rate

FINE DC CORRECTION

The fine dc correction block in the AD6650 lies between the

RCF and serial output port. While the coarse dc correction

block at the front of the channel is included to provide a one-

time correction at startup or at rare intervals when commanded

by the user, the fine dc correction block is intended to run

continuously and track any changes in the dc offsets of the

analog front end. To achieve this efficiently under varying

signal conditions, this dc estimation process is adaptive.

The AD6650 implements this high-pass filter in the form of an

accumulator that integrates a number of samples of the output

of the RCF and produces an estimate after the samples are

accumulated. The estimated dc is then removed from the signal

path by a simple subtraction. The subtraction is clamped to

avoid overflow problems. The HPF bandwidth is varied by

changing the integration time (equivalent to a SYNC 1 filter

decimation of the integrator). The integration time is varied based

on the output of a peak detector circuit according to the process

described in the Peak Detector DC Correction Ranging section.

Adaptive DC Correction Filter

In typical applications where dc offsets are to be corrected, a

high-pass filter (HPF) is used to remove the dc and some small

percentage of the input signal power. This approach is

PEAK DETECTOR DC CORRECTION RANGING

The peak detector of the AD6650 always looks at the maximum

signal power present in the I or Q data path. The I and Q paths

are treated totally independently in the dc correction circuitry

because the analog paths are not guaranteed to match. The first

sample that arrives is rectified and preloaded into the peak

detector. A control counter is set to the minimum period

control register setting. On every input sample, the peak

detector determines if the new sample is larger than the

currently held sample, and if so, the peak detector is updated.

The contents of the peak detector are then examined. If they are

below the lower threshold, the control counter counts down and

when it reaches 0, it updates the dc estimate, resets the dc

accumulator, and reloads the peak detector with the newest

input sample magnitude. If the peak detector value is above the

upper threshold of the dc correction, the estimate currently

being calculated is discarded. When the signal drops below the

upper threshold, the calculation of a new dc estimate begins.

The current estimate is held, so the last known dc content

continues to be removed.

straightforward and works well when the input signal has a

relatively constant power or when the bandwidth of the HPF is

extremely small (in the μHz or nHz range) and the dc content

does not vary. In general, the more the input signal power can

vary, the narrower the bandwidth of the high-pass filter must be

to avoid low frequency transients in the filter that are larger

than the smallest expected signals. A fundamental trade-off

exists because if the high-pass filter has a very low bandwidth, it

can only track very slow changes (over hours, days, or weeks) in

the dc offsets of the device. On the other hand, if it has a higher

bandwidth, it may not be able to estimate the dc properly in the

presence of a large baseband signal.

Given the assumption that the signal of interest is uniformly

distributed across frequency, the processing gain equation can

be used to provide a starting point for system optimization.

Enough processing gain must be guaranteed for the dc estimate

to be valid for a minimum signal case. This is typically 20 dB to

30 dB but depends on the baseband signal processing of a

particular system. For GSM/EDGE, which is distributed over

~100 kHz single sideband (SSB), this implies that the HPF

bandwidth must be between 100 Hz to 1 kHz SSB. For every

6 dB that the signal power increases, 6 dB more processing gain

is required; therefore, the HPF bandwidth needs to decrease by

a factor of 4 or more.

The AI, AQ, BI, and BQ paths of the AD6650 are each treated

independently in the dc correction circuitry because the analog

paths are not guaranteed to match, and separate dc estimates

need to be kept for each. Separate peak detectors, dc estimate

accumulators, dc estimate subtractors, and control counters are

implemented for each of these paths.

(14)

Rev. A | Page 20 of 44

AD6650

Peak Detector

⎛

⎜

⎞

⎟

Desired _ Signal _ Power − Lower _Threshold

I _ P = 2^{Min _ Period + Ceil}

× 2

⎜

⎝

⎟

⎠

6.02

The peak detector always stores the input sample with the

largest magnitude. The absolute value of every input sample is

compared to what is currently in the peak detector’s holding

register. The only exception is when the control counter reaches

0; at this point, the dc offset estimate is updated and the peak

detector is set to the current input magnitude. The output of

each of the peak detectors is then encoded into a digital word

that represents the signal power in 6 dB steps relative to full

scale (FS).

(16)

where Min_Period, Upper_Threshold, and Lower_Threshold are

register-programmable values.

To calculate the time required for the fine dc correction to

converge, use the following equation:

I _ P ×T_SYM

Fine _ DC _ Converge =

(17)

60

DC Accumulator

where:

The dc accumulator accumulates the 24-bit samples input from

the RCF filter until the control counter reaches 0. At this time,

the dc estimate in the holding register is updated, and the

accumulator is directly loaded with the new input sample to

begin work on the next estimate.

T

_SYMis the output symbol rate of the AD6650.

Fine_DC_Converge is expressed in minutes, and for a GSM

application with 1× oversampling, it is 3.69 × 10⁻⁶.

USER-CONFIGURABLE BUILT-IN SELF-TEST (BIST)

The AD6650 includes a BIST to assess digital functionality. This

feature verifies the integrity of the main digital signal paths of

the AD6650. Each BIST register is independent, meaning that

each channel can be tested independently at the same time.

Control Counter

This counter controls the update of the dc correction block

based on the peak detector value and the input control registers.

The following three conditions are possible:

The BIST is a thorough test of the selected AD6650 digital

signal path. With this test mode, it is possible to use the internal

pseudorandom generator to produce known test data. A

signature register follows the fine dc correction block. This

register can be read back and compared to a known good

signature. If the known good signature matches the register

value, the channel is fully operational.

•

If the digital word from the peak detector indicates that the

desired signal is below the lower threshold, the counter

merely cycles through at the minimum period.

If the digital word from the peak detector indicates that the

desired signal is above the upper threshold, the control

counter is held at the minimum period value and does

not count down; therefore, no update is made. When the

signal returns below the upper threshold, this counter

resumes counting.

If the digital word from the peak detector indicates that the

desired signal is between the lower threshold and the upper

threshold, the fine dc correction circuit is in its normal mode

of operation. In this mode, the control counter starts with the

minimum period but is reloaded with 4× minimum period

every time the peak detector output words increment by

6 dB. This errs on the side of caution and ensures that the

dc correction integrates long enough to obtain a valid

estimate. If smaller integrations are preferred, the minimum

period can be decreased or the lower threshold can be raised.

•

If an error is detected, each internal block can be bypassed and

another test can be run to debug the fault. The I and Q paths are

tested independently. Use the following steps to perform this test:

•

1. Reset the AD6650.

2. Program the desired AD6650 channel parameters for the

desired application (these parameters include decimation

rates, scalars, and RCF coefficients). Also, ensure that the

start holdoff counter is set to a nonzero value.

3. Set Register 0xA, Bit 1, to 1 (PN_EN).

4. Set Register 0x21, Bit 8, to 0 (fine DCC to BIST).

5. Start the A and/or B channels with a microprocessor write

(Soft_SYNC) or a pulse on the SYNC pin (Pin_SYNC).

6. Wait at least 300 μs.

7. Read the four BIST registers and compare the values to a

known good device. This ensures that the AD6650 is

programmed correctly and that each channel is

functioning correctly.

The integration period is given by Equation 15 and Equation 16.

The factor of 2 in the exponent shows that as peak signal power

increases, the integration time is increased by a factor of 4. This

decreases the bandwidth of the estimation filter, thus providing

the additional processing gain in the dc estimation term.

When the desired signal power equals the upper threshold,

⎛

⎞

Upper _Threshold − Lower _Threshold

I _ P = 2^{Min _ Period + Ceil}

× 2

⎜

⎟

⎜

⎝

⎟

⎠

6.02

(15)

When the desired signal power is less than the upper threshold,

Rev. A | Page 21 of 44

AD6650

therefore, the PFD reference frequency should be set for

optimal placement of spurs.

LO SYNTHESIS

The AD6650 has a fully integrated quadrature LO synthesizer

consisting of a voltage-controlled oscillator (VCO) and a phase-

locked loop (PLL). Together these blocks generate quadrature

IF LO signals for the demodulators.

Prescaler and Feedback Dividers

The dual modulus prescaler, P/(P + 1), and the A and B

feedback dividers (5 bits and 13 bits, respectively) combine to

provide a wide ranging N-divider in the PLL feedback loop. The

feedback division is N = 8B + A. Including the final quadrature

divider (divide-by-4), the LO frequency is given by

Figure 27 shows a block diagram of the LO synthesis block.

Besides the usual PLL and VCO, there is also a programmable

half-rate divider (Div-X and a fixed divide-by-4 quadrature

divider that produces the final I and Q LO signals).

f_CLK

×

(

B × 8 + A

)

f_LO

where:

=

(18)

VCO

4R

The VCO generates an on-chip RF signal in the range of

2.2 GHz to 2.8 GHz. The only external component required is a

bypass capacitor for the low dropout (LDO) voltage regulator

used to power the VCO tank core. The VCO uses overlapping

bands to achieve the wide tuning range while maintaining

excellent phase noise and spurious performance. During band

selection, which takes 5 PFD cycles, the VCO V_TUNEis disconnected

from the output of the loop filter and connected to an internal

reference voltage. After band select, normal PLL action

resumes. The nominal value of K_Vis 65 MHz/V, where K_Vis the

VCO sensitivity.

f_LOis the local oscillator frequency.

f_CLKis the external frequency oscillator.

B is the 13-bit divider (3 to 8191).

A is the 5-bit swallow divider (0 to 31).

R is the input reference divider (1 to 16,384).

The f_CLK/4R term combines the effects of the reference divider

and the final quadrature divider, and determines the frequency

spacing for the LO synthesizer. For a typical GSM application,

f_CLK= 52 MHz and R = 65 result in a 200 kHz PFD update rate,

which sets the frequency spacing at a desired 200 kHz. However,

this also places LO spurs at offsets of 200 kHz multiples, which

might degrade the interferer/blocker performance.

Immediately following the VCO is a programmable half-rate

divider that has settings of divide-by-2, -2.5, -3, -3.5, and so on,

up to divide-by-8. This function divides the VCO frequency

down to four times the LO frequency and effectively extends

the tuning range of the VCO. The VCO and the half-rate

divider can be thought of as a single lower frequency VCO with

a frequency range of 280 MHz to 1040 MHz.

CAL

EXTERNAL

LOOP FILTER

f_REF

R-DIV

14-BIT

UP

DN

f_CLK

I

OUT

CHARGE

PUMP

PFD

DIV-X

DIV-4

Q

OUT

VCO

Autocalibration selects both the VCO operating band and the

oscillator amplitude to ensure peak operating performance

across the entire frequency range. The half-rate divide setting is

also selected as part of the VCO calibration. Autocalibration is

performed whenever PLL Register 3 (the test mode latch) is

written; therefore, all other PLL registers should be set first, and

Register 3 should be written to last. This is true whenever

programming any portion of the LO synthesizer because the

VCO may need to recalibrate itself, depending on the changes

made to the registers.

N-COUNTER

B-DIV

13-BIT

PRESCALER

P/(P + 1)

A-DIV

5-BIT

Figure 27. PLL Circuit

PFD and Charge Pump

The phase-frequency detector (PFD) takes inputs from the

R-divider and N-divider and produces an output proportional

PLL

The integer-N type PLL consists of a programmable reference

divider (R-divider), a prescaler and feedback divider (N-divider),

a phase-frequency detector (PFD), and a charge pump. The

output of the charge pump drives an external loop filter, which

in turn drives the input of the VCO.

to the phase and frequency difference between them. The PFD

includes a programmable delay element that controls the width

of the antibacklash pulse. This pulse ensures that there is no

dead zone in the PFD transfer function and minimizes

reference spurs.

R-Divider

Loop Filter

The 14-bit R-divider divides down the input clock frequency to

produce the reference frequency for the phase-frequency

detector. Although division ratios from 1 to 16,383 are allowed,

the maximum update rate for the PFD is 1 MHz. The selected

update rate of the PFD and the subsequent charge pump

determines the spurious performance of the LO synthesizer;

The final element in the LO synthesizer is the external loop

filter, which is generally a first-order or second-order RC low-

pass filter. A filter like the one shown in Figure 28 is recommended

to provide a good balance of stability, spurs, and phase noise.

This partiular filter is optimized for an update rate of 1 MHz.

Rev. A | Page 22 of 44

AD6650

Slow Loop

867Ω

LF

The slow loop is the main loop and is associated with a loop

gain parameter. This parameter controls the rate of change of

the gain and should always be less than 1. To determine the

loop gain, Equation 19 should be used.

CP

200ꢀ

56000pF

3900pF

AD6650

1.0µF

K

⎛

⎜

⎝

⎞

⎟

⎠

× 2^−K

(19)

Mantissa

Exponent

AGCLoopGain =

VLDO

256

Figure 28. Loop Filter Circuit

where:

V

P

CHARGE

PUMP

K

_Mantissais the loop gain mantissa. Values can range from 0 to 63.

_Exponentis the loop gain exponent. Values can range from 0 to 7.

UP

Q1

HI

D1

U1

As the loop gain value increases, the speed of the response of

the AGC loop increases; as the loop gain value decreases, so

does the speed of the response of the AGC loop. The slow loop

attempts to maintain the signal entering the ADC at a given

level, referred to as the requested level. This level is specified in

dBFS and can be between 0 dBFS and −24 dBFS (in 0.094 dB

steps) of the converter resolution. The default value is −6.02 dBFS.

The slow loop has a peak detection function, the period of

which can be set by the user. This period should be set to ¼ of

the symbol period, or greater, to prevent the AGC loop from

gaining off the envelope of the EDGE signal. This detection

period works because the peak detector’s operation is based on

dB (max(|I|, |Q|)); therefore, all of the I/Q samples are reflected

back into one quadrant of the I/Q plane. At a 26 MHz sampling

frequency, one symbol period is 96 clock cycles. Therefore, to

obtain a peak detector period that is ¼ of the symbol period,

the peak detector period should be set to a minimum of 24

samples. The following equation can also be used:

R-DIVIDER

CLR1

CP

U3

ADP2

ADP1

CLR2

D2 Q2

DOWN

HI

U2

N-DIVIDER

CPGND

R-DIVIDER

N-DIVIDER

CP OUTPUT

Figure 29. PFD Simplified Schematic and Timing (Locked)

SPB Peak Samples ≥ ¹

×

(

f

_SAMP/ f_SYM

)

(20)

LDO

4

The AD6650 includes an on-chip 2.6 V low dropout (LDO)

voltage regulator that supplies the VCO and other sections of

the PLL. A 0.22 μF bypass capacitor is required on the VLDO

output to ensure stability. This LDO employs the same technology

used in the anyCAP® line of regulators from Analog Devices, Inc.,

making it insensitive to the type of capacitor used. Driving an

external load from the VLDO output is not supported.

where:

f

_SYM= 270.833 kHz (GSM symbol rate).

_SAMP= 26 MHz.

Fast Attack (FA) Loop

The FA loop utilizes an analog threshold detector that prevents

overdrive of the analog signal path. In a situation that could

potentially overdrive the ADC, the FA loop takes over from the

slow loop and decreases the gain to the VGA in the front end.

The step size used for the FA loop is programmable between

0 dB and 1.504 dB in 0.094 dB steps. The FA loop also has a

counter that is programmable between 1 and 16. When

initialized to count + 1, the FA loop decreases the gain for

count + 1 clock cycles when the threshold is crossed.

AGC LOOP/RELINEARIZATION

The AGC consists of three gain control loops: a slow loop, a fast

attack (FA) loop, and a fast decay (FD) loop.

ADC

UPPER

THRESHOLD

Fast Decay (FD) Loop

The FD loop is a fast loop that increases the gain when the

signal falls below a threshold during a deep channel fade or on

the ramp down. The fast loop accomplishes this task by

comparing the peak signal-plus-blocker level at the ADC output

(which includes the signal and any blockers that pass through

the SAW filter) with a programmable level (SPB_level) that

determines when this loop is activated. The SBP_level default

ADC

AGC

STATE

MACHINE

FAST LOOP DETECTORS

SLOW LOOP, SIGNAL LEVEL

SIGNAL PLUS BLOCKER LEVEL

Figure 30. AGC Loop Block Diagram

Rev. A | Page 23 of 44

AD6650

value is −40 dBFS. When the wideband signal is below the SPB

level, the FD loop is activated. This loop overrides the slow loop

and has a programmable step size (default 0.094 dB) and a

programmable peak detect period (defaults four samples at

1.08 MHz).

The SDIV for Serial Port 0 and Serial Port 1 can be programmed

via Internal Control Register 0x21. Valid SDIV values are between

0 and 7, corresponding to divide ratios between 1 and 8.

Serial Output Frame Timing

The SDFS signal transitions high to signal the start of a data

frame. On the next rising edge of SCLK, the port drives the first

bit of the serial data on the SDO pin. The falling edge of SCLK

or the subsequent rising edge can then be used by the DSP to

sample the data until the required number of bits is received

(determined by the serial output port word length). If the DSP

has the ability to count bits, it can identify when the complete

frame is received.

1

UPPER THRESHOLD

(OVER LOAD PROTECTION)

~–1dBFS

OPERATIONAL

RANGE

–6dBFS

2

REQUESTED LEVEL

–46dBFS

3

LOWER THRESHOLD

(DEEP FADE PROTECTION)

Serial Port Timing Specifications

NOTES

Figure 32 to Figure 35 indicate the timing required for the

AD6650 serial port.

1

ADJUSTABLE LEVEL, WITH PROGRAMMABLE STEP SIZE AND ADJUSTABLE PERIOD.

ADJUSTABLE LEVEL, LOOP GAIN (<1), HYSTERESIS, INTEGRATION PERIOD.

2

3

ADJUSTABLE LEVEL, ADJUSTABLE STEP SIZE.

t_SCLK

Figure 31. AGC Thresholds

t_SCLKH

SERIAL OUTPUT DATA PORT

SCLK

The AD6650 has two configurable serial output ports (SDO0

and SDO1). Both ports must be identically configured and are

programmed using the same control register. The ports share a

common SFDS, SCLK, and DR pin for connection to an

external ASIC or DSP; therefore, the outputs cannot be

programmed independently.

t_SCLKL

Figure 32. SCLK Timing Requirements

CLK

t_DSCLKH

Serial Output Data Format

t_SCLKH

The AD6650 utilizes a twos complement data format with a

selectable serial data-word length of 16 bits or 24 bits. The data

is shifted out of the device in MSB-first format.

SCLK

t_SCLKL

Serial Data Frame Sync

Figure 33. SCLK Switching Characteristics (Divide-by-1)

The serial data frame sync (SDFS) pin signals the start of the

serial data frame. As channel data becomes available at the

output of the AD6650’s filters, this data is transferred into the

serial data buffer. The internal serial controller initiates the

SDFS on the next rising edge of the serial clock. In the AD6650,

there are three modes in which the frame sync can be

t_DSDO

SCLK

I

13

SDO

15

14

Figure 34. Serial Output Data Switching Characteristics

generated, which are described in the SDFS Modes section.

t_DSO

Configuring the Serial Ports

SCLK

Both serial output ports must function as master serial ports. A

serial bus master provides SCLK and SDFS outputs. Serial Port 0

and Serial Port 1 must be programmed as the bus masters by

setting Bit 3 of the serial control register high.

SDFS MINIMUM

WIDTH IS ONE SCLK

SDFS

SDO

I

MSB

MSB1

Serial Port Data Rate

FIRST DATA IS AVAILABLE THE FIRST

RISING SCLK AFTER SDFS GOES HIGH

The SCLK frequency is defined by Equation 21.

Figure 35. Timing for Serial Output Port

f_CLK

SDIV +1

(21)

f_SCLK

=

SCLK

SCLK is an output on the AD6650. All outputs are switched on

the rising edge of SCLK. The SDFS pin is sampled on the falling

edge of SCLK. This allows the AD6650 to recognize the SDFS in

time to initiate a frame on the next SCLK rising edge. The

maximum speed of this port is 52 MHz.

where:

_CLKis the frequency of the master clock of the AD6650 channel.

SDIV is the serial division word for the channel.

f

Rev. A | Page 24 of 44

AD6650

SDO

SDO1. In this condition, there are three modes of operation.

(There are technically four modes, but Mode 0 and Mode 1 are

the same).

SDO is the serial data output. Serial output data is shifted on

the rising edge of SCLK. On the next SCLK rising edge after an

SDFS, the MSB of the I data from the channel is shifted.

•

Mode 0 and Mode 1 (Address 0x21, Bits[6 :5] = 00;

Bit[7] = 1): The SDFS is valid for one complete clock cycle

prior to the data shift. This single pulse is valid for Output

Channel SDO0 and Output Channel SDO1. On the next

clock cycle, the AD6650 begins shifting out the digitally

processed data stream. Depending on the bit precision of

the serial configuration, either 16 bits or 24 bits of I data

are shifted out, followed by 16 bits or 24 bits of Q data.

Mode 2 (Address 0x21, Bits[6:5] = 10; Bit[7] = 1): Because

both SDO0 and SDO1 are used, SDFS pulses high one

clock cycle prior to I data and also pulses high one clock

cycle prior to Q data for each corresponding input channel. In

this mode, there are two SFDS pulses per each output channel.

Mode 3 (Address 0x21, Bits[6:5] = 11; Bit[7] = 1): The SDFS

is high while valid bits are being shifted. On SDO0, SDFS

remains high for 16 bits or 24 bits of I data, followed by

16 bits or 24 bits of Q data corresponding to Input Channel A.

For SDO1, SDFS remains high for 16 bits or 24 bits of I data,

followed by 16 bits or 24 bits of Q data corresponding to

Input Channel B. The SDFS bit goes high one complete

clock cycle before the first bit is shifted out of the AD6650.

On every subsequent SCLK edge, a new piece of data is shifted

out on the SDO pin until the last bit of data is shifted out. The

last bit of data shifted is the LSB of the Q data from the channel.

SDO is three-stated when the serial port is outside its time slot.

This allows the AD6650 to share the SDIN of a DSP with other

AD6650s or other devices.

SDFS

•

SDFS is the serial data frame sync signal. SDFS is configured as

an output. SDFS is sampled on the falling edge of SCLK. When

SBM is sampled high, the chip functions as a serial bus master.

In this mode, the AD6650 is responsible for generating serial

control data. Four modes of that operation are set via Channel

Address 0x21, Bit 6 to Bit 5.

Serial Word Length

Bit 4 of Address 0x21 determines the length of the serial word

(I or Q). If this bit is set to 0, each word is 16 bits wide (16 bits

for I and 16 bits for Q). If this bit is set to 1, the serial words are

24 bits wide.

SDFS Modes

As mentioned in the Serial Data Frame Sync section, there are

three modes of operation.

Setting Bit 7 of Address 0x21 high indicates that Input Channel A

data is output on SDO0 and Input Channel B data is output on

Rev. A | Page 25 of 44

AD6650

APPLICATION INFORMATION

REQUIRED SETTINGS AND START-UP SEQUENCE

FOR DC CORRECTION

Overall DC Correction Performance

With the recommended settings, the dc correction performance

is approximately −120 dBFS or better for small signals. Once the

signal is large enough to trip the AGC loop, the dc component

also rises; however, this component has been shown to always

be 40 dBc below the signal of interest. Therefore, the carrier-to-

dc ratio degrades for small signals. For additional details on the

dc correction registers, see the associated bit descriptions in the

Register Map section.

On startup, the fine dc correction block may take up to several

minutes to converge to a good dc estimate, especially if a large

signal is present on the input. To improve this convergence

without run-time trade-offs, use a two-step start-up process.

The first step is to configure the fine dc correction block with

the parameters shown in Table 12. The freeze is set so that the

fine dc correction responds after the coarse dc correction has

updated. At the same time, the minimum period can be set to a

small value, such as 10. This guarantees a quicker convergence

because the minimum period is smaller, resulting in a smaller

integration period.

CLOCKING THE AD6650

The AD6650 encode signal must be a high quality, low phase

noise source to prevent degradation of performance. The

AD6650 can be clocked with a single-ended signal, but

must be ac-coupled to ground. For optimum performance, the

AD6650 must be clocked differentially. The encode signal

CLK

Also, setting the registers as described in Table 12, and

subsequently programming the AD6650, ensures that the VGA

and mixer are powered down during the power-on calibration

to keep signals with large dc content from interfering with the

estimation of the dc component from the analog path.

CLK

should be ac-coupled into the CLK and

pins via a

transformer or capacitors. These pins are biased internally and

require no additional bias.

After ~500 ms, the freeze bit (Address 0x0B, Bit 0) can be

written low. The dc correction then converges and begins

removing the offset. If desired, the minimum period can

then be set to a larger value.

Figure 36 shows the preferred method for clocking the AD6650.

The clock source (low jitter) is converted from single-ended to

differential using an RF transformer. The back-to-back Schottky

diodes across the secondary transformer limit clock excursions

into the AD6650 to approximately 0.8 V p-p differential. This

helps prevent large voltage swings of the clock from feeding

through to other portions of the AD6650 and limits the noise

presented to the encode inputs.

If the VGA and mixer are not disabled during a power-up using the

AutoCalibration control register as recommended, approximately

30 dB of suppression can be achieved, but the user must

guarantee that significant content is not present at the IF

frequency that will be translated to dc. If enhanced performance

is desired from the coarse dc correction, an RF switch or other

device can be used to shut off the input of the AD6650 until the

correction has been completed.

T1-4T

CLOCK

SOURCE

CLK

0.1µF

AD6650

CLK

HSMS2812

0.01µF

DIODES

Figure 36. Crystal Clock Oscillator—Differential Encode

Table 12. DC Correction Register Recommendations

Description

Channel Address

Bit

Value

AutoCalibration Control Register

Upper Threshold

Lower Threshold

Minimum Period

Freeze

0x22

0x0B

Bit 0

Bit 1

Bit 2

Bit 3

Bit 19 to Bit 13

Bit 12 to Bit 8

Bit 7 to Bit 3

Bit 0

Enabled (1)

Power down DACs at startup (0)

Enabled (1)

Sync ADCs (0)

−48 dBFS

−90 dBFS

+10 sample periods

Enabled (1)

Rev. A | Page 26 of 44

AD6650

Another option is to ac-couple a differential ECL/PECL signal

to the encode input pins as shown in Figure 37. A device that

offers excellent jitter performance is the MC100EL16 (or a

device from the same family) from Motorola.

VT

EXTERNAL REFERENCE

The reference should be connected as shown in Figure 39 to

achieve the results specified in this data sheet.

AIN/BIN

REFT

0.1µF

CLK

CHANNEL A/

0.1µF

ECL/

PECL

REF

AMP

CHANNEL B

ADC

AD6650

CORE

10µF

CLK

0.1µF

REFB

VT

0.1µF

Figure 37. Differential ECL for Encode

VREF

10µF

0.5V

VREF

R

0.1µF

INT

DRIVING THE ANALOG INPUTS

SELECT

LOGIC

As with most new high speed, high dynamic range devices, the

analog input to the AD6650 is differential. Differential inputs

allow much improvement in performance on-chip because signals

are processed through attenuation and gain stages. Most of the

improvement is a result of differential analog stages that have

high rejection of even-order harmonics. Differential inputs are

also beneficial at the PCB level. First, differential inputs have

high common-mode rejection of stray signals, such as ground

and power noise, and good rejection of common-mode signals,

such as local oscillator feedthrough.

REFGND

R

INT

Figure 39. Reference Connection

POWER SUPPLIES

Care should be taken when selecting a power source. Linear

supplies are strongly recommended. Switching supplies tend to

have radiated components that may be received by the AD6650.

Each of the power supply pins should be decoupled as closely to

the package as possible using 0.1 μF chip capacitors.

The AD6650 analog input voltage range is offset from ground

by 1.3 V. The resistor network on the input properly biases the

followers for maximum linearity and range. Therefore, the

analog source driving the AD6650 should be ac-coupled to the

input pins. The input resistance for the AD6650 is 200 Ω, and

the input voltage range is 2 V p-p differential. This equates to

4 dBm full-scale input power. The recommended method for

driving the analog input of the AD6650 is to use an RF balun.

The AD6650 is susceptible to low frequency power supply

interference as shown in Figure 40. This low frequency energy is

translated into spurious tones in the output signal. Analog

power supply ripple couples into the LO through the VCO. This

can be observed from the ripple frequency vs. sideband spur

level plot (see Figure 40). Note that this plot has the spur level

referenced to 1 mV rms supply ripple and is referred to the LO.

Thus, this plot shows a transfer function rather than an absolute

value. The spurious level can be extrapolated to any supply

ripple level from this data using Equation 22.

C101

C102

J101

47000pF

AIN/BIN

5

1

T101

T102

R101

68.9ꢀ

C103

47000pF

4

5

3

1

AIN/BIN

Spur _ Lev = Spur _ Lev_1mV×20log(SupRipple(mV)) (22)

4

3

where:

Figure 38. Balun-Coupled Analog Input Circuit

Spur_Lev is the output spurious level relative to the LO.

Spur_Lev_{1 mV}is the 1 mV referred level from Figure 40 and

Figure 41.

SupRipple (mV) is the RMS ripple on the AVDD power supply.

Rev. A | Page 27 of 44

AD6650

–35

–40

–45

–50

–55

–60

–65

–70

DIGITAL OUTPUTS

It is recommended that the digital outputs drive a series resistor

(for example, 100 Ω). To minimize capacitive loading, the

number of gates on each output pin should be limited. The

series resistors should be placed as close to the AD6650 as

possible to limit the amount of current that can flow into the

output stage. These switching currents are confined between

ground and the DVDD pin. Also, note that excessive capacitive

loading increases output timing and can invalidate timing

specifications.

GROUNDING

–75

1

10

100

1000

For optimum performance, it is highly recommended to use a

split ground between the analog and digital grounds. AGND

should be connected to the analog ground of the RF board, and

DGND should be connected to the digital ground of the RF board.

OFFSET FREQUENCY (kHz)

Figure 40. Output Spurious vs. Power Supply Ripple (AIN = 199 MHz)

An additional parameter that strongly impacts the PSRR is the

sensitivity to the AVDD voltage level. A plot of spur level versus

AVDD is shown below in Figure 41. Note that this plot also has

the spur level referenced to 1mV rms supply ripple and is

referred to the LO. Thus, this plot shows a transfer function

rather than an absolute value. The spurious level can be

extrapolated to any supply ripple level from this plot using

Equation 21.

To minimize the potential for noise coupling, it is highly

recommended to place multiple ground return traces and vias

so that the digital output currents do not flow back toward the

analog front end, but instead are routed quickly away from the

AD6650. This can be accomplished by simply placing

substantial ground connections directly back to the supply at a

point between the analog front end and the digital outputs.

Judicious use of ceramic chip capacitors between the power

supply and ground planes also helps suppress digital noise. The

layout should incorporate enough bulk capacitance to supply

the peak current requirements during switching periods.

–20

–23

–26

–29

–32

–35

–38

–41

–44

–47

LAYOUT INFORMATION

A multilayer board should be utilized to achieve optimal results.

It is highly recommended to use high quality ceramic chip

capacitors to decouple each supply pin to ground directly at the

device. The pin arrangement of the AD6650 facilitates ease of

use in the implementation of high frequency, high resolution

design practices. All of the digital outputs are on the opposite

side of the package from the analog inputs for isolation purposes.

–50

2.95 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 3.55 3.60

Care should be taken when routing the digital output traces. To

prevent coupling through the digital outputs into the analog

portion of the AD6650, minimal capacitive loading should be

placed on these outputs.

AVDD (V)

Figure 41. Output Spurious vs. Power Supply Ripple (AIN = 199 MHz)

The AD6650 has separate digital and analog power supply pins.

The analog supplies are denoted AVDD, and the digital supply

pins are denoted DVDD. Although analog and digital supplies

can be tied together, best performance is achieved when the

supplies are separate because the fast digital output swings can

couple switching current back into the analog supplies. Note

that AVDD and DVDD must be held between 3.0 V and 3.45 V.

The layout of the encode circuit is equally critical. Any noise

received on this circuitry results in corruption in the digitization

process and lower overall performance. The encode clock must

be isolated from the digital outputs and the analog inputs.

Rev. A | Page 28 of 44

AD6650

3. Write the start holdoff counter(s) (Address 0x14) to the

CHIP SYNCHRONIZATION

appropriate value (greater than 1 but less than 65,535).

4. Program all other registers of the AD6650 that are not

already set.

5. Write the Soft_SYNC bit high (External Memory

Address 5, Bit 0).

6. When the Soft_SYNC bit goes high, the start holdoff

counter begins to count down using the AD6650 CLK

signal after the CLK divider. When the start holdoff

counter reaches a count of 1, the selected channel(s) are

activated.

The AD6650 is designed to allow synchronization of multiple

AD6650s within a system. The AD6650 is synchronized with

either a microprocessor write (Soft_SYNC) or a pulse on the

SYNC pin (Pin_SYNC). The first sync event starts the device,

and subsequent sync events resynchronize the filters of the

AD6650. By using a start holdoff counter, it is possible to align the

phase of the AD6650 to other devices. To synchronize the AD6650

with external hardware, see the Start with SYNC Pin section.

Start with Soft_SYNC

The AD6650 includes the ability to synchronize channels or

chips under microprocessor control. The start holdoff counter

(Address 0x14), in conjunction with the SYNC bit (External

Memory Address 5, Bit 0), allows this synchronization. The

start holdoff counter delays the start and synchronization of a

channel(s) by its value (number of AD6650 CLKs).

Start with SYNC Pin

The AD6650 has a SYNC pin that can be used to provide

synchronization between AD6650 devices and external

hardware to a resolution of 1 ADC sample cycle. This can be

accomplished by providing a 1-CLK-cycle-wide pulse on the

SYNC pin when the edge-sensitive bit of the SF1 register is low

(External Memory Address 4, Bit 4), which is useful when an

FPGA or other external hardware is operating at the CLK rate of

the AD6650. Synchronization can also be accomplished by

setting the edge-sensitive bit high so that the SYNC input is

rising-edge sensitive, which is useful when the external

hardware is operating off a clock that is much slower than the

AD6650 or is asynchronous to it.

Use the following method to synchronize the start of a channel

via microprocessor control:

1. Set the appropriate channels to sleep mode. A hard reset to

RESET

the AD6650 (

sleep mode.

taken low) puts both channels into

2. Enable Channel A and/or Channel B (External Memory

Address 3, Bit 0).

Rev. A | Page 29 of 44

AD6650

MICROPORT CONTROL

The AD6650 has an 8-bit microprocessor port. The microport

interface is a multimode interface that allows flexibility when

dealing with the host processor.

ACCESS CONTROL REGISTER (ACR)

Bit 7 of the ACR register is the auto-increment bit. If this bit is set to

1, the CAR register, described in the Channel Address Register

(CAR) section, increments in value after every access to the

channel. This allows blocks of address space, such as coefficient

memory, to be initialized more efficiently.

There are two modes of bus operation: Intel® nonmultiplexed

mode (INM) and Motorola nonmultiplexed mode (MNM). The

mode is selected based on the host processor and which mode

is best suited for that processor. The microport has an 8-bit data

bus (D[7:0]), 3-bit address bus (A[2:0]), three control pin lines

Bit 6 of the ACR register is unused and must be written low.

Bit 5 to Bit 2 of the ACR register are instruction bits that allow

multiple AD6650s to receive the same write access. The instruction

bits allow a single or multiple (up to four) AD6650 chip(s) to be

configured simultaneously. There are seven possible instructions

that are defined in Table 14, where x represents disregarded

values in the digital decoding.

CS DS RD

W

WR

DTACK

(

,

or

, and R/ or

), and one status pin (

or RDY). The functionality of the control signals and status line

changes slightly depending on the selected mode. Refer to the

timing diagrams in Figure 10 through Figure 13 and the

descriptions in the Programming Modes, Intel Nonmultiplexed

Mode (INM), and Motorola Nonmultiplexed Mode (MNM)

sections for details on the operation of each mode.

CS

If multiple AD6650 chips are using the same

is not valid because of the potential for bus contention. Therefore,

CS

line, readback

EXTERNAL MEMORY MAP

if device readback capability is desired, the

lines should be

The external memory map is used to gain access to the channel

address space. The 8-bit data and address buses are used to set

the eight registers shown in Table 13. These registers are

collectively referred to as the external interface registers because

they control all access to the channel address space and global

chip functions. The use of each register is described in Table 13.

separated for individual control. To facilitate device debug and

CS

verification, the use of separate

recommended.

lines for each AD6650 is

Bit 1 to Bit 0 of the ACR register are address bits that decode which

channel is to be accessed. Because the channels of the AD6650

cannot be programmed independently, these bits should be set

to 0.

Table 13. External Memory Map

Addr.

(Hex) Mnemonic

Bit No. Description

CHANNEL ADDRESS REGISTER (CAR)

7

Access Control Register

7

Auto-increment

The CAR register represents the 8-bit internal address of each

channel. If the auto-increment bit of the ACR is 1, this value is

incremented after every access to the DR0 register, which in

turn accesses the location pointed to by this address.

(ACR)

6

Reserved (write low)

Instruction [3:0]

A[9:8]

5 to 2

1 to 0

7 to 0

6

5

Channel Address Register

(CAR)

A[7:0]

SPECIAL FUNCTION REGISTERS

Special Function Register 2

(SF2)

6

5

AGC sync enable

The AD6650 has three special function registers, SF0, SF1, and

SF2, that control synchronizing and enabling of the channels. SF0

controls channel enabling, SF1 controls Pin_SYNC, and SF2

controls Soft_SYNC. For SF0, Bit 0 and Bit 2 allow Channel A

and Channel B, respectively, to exit sleep mode by the method

selected in SF1. Bit 1 and Bit 3 are read-only bits and indicate

whether Channel A and Channel B, respectively, are active. A 1

indicates that the channel is active, and a 0 indicates that it is

not active. Bits 4 through Bit 7 are unused.

DC correction

sync enable

4

PN sync enable

Reserved

3 to 1

0

5

Issue Soft_SYNC

First sync only

4

3

Special Function Register 1

(SF1)

4

Enable edge- sensitivity

Reserved

3 to 1

0

For SF1, if Bit 0 is set to 1, both channels wait for a pulse to

appear on the SYNC pin before exiting sleep mode; otherwise,

the channels assume a soft start is desired and wait for the start

holdoff counter to issue a sync. When Bit 5 is set, both channels

ignore all subsequent attempts to resync once they have exited

sleep mode.

Enable Pin_SYNC

Reserved

Special Function Register 0

(SF0)

7 to 4

3

Status of Channel B

Enable Channel B

Status of Channel A

Enable Channel A

Reserved

2

1

0

2

Data Register 2 (DR2)

7 to 4

3 to 0

D[19:16]

1

0

Data Register 1 (DR1)

Data Register 0 (DR0)

15 to 8 D[15:8]

7 to 0 D[7:0]

Rev. A | Page 30 of 44

AD6650

READ/WRITE CHAINING

Table 14. Microport Instructions

CS

Instruction

Description

The microport of the AD6650 allows multiple accesses while

0xxx

1000

1001

1100

1101

1110

1111

All chips obtain access.

CS

is held low ( can be tied permanently low if the microport is

All chips with Chip_ID [1:0] = x0 obtain access.¹

All chips with Chip_ID [1:0] = x1 obtain access.¹

All chips with Chip_ID [1:0] = 00 obtain access.¹

All chips with Chip_ID [1:0] = 01 obtain access.¹

All chips with Chip_ID [1:0] = 10 obtain access.¹

All chips with Chip_ID [1:0] = 11 obtain access.¹

not shared with additional devices). The user can access

multiple locations by pulsing the

the contents of the external 3-bit address bus. Access to the

external registers listed in Table 13 is accomplished in one of

two modes using the

WR RD

or

line and changing

CS RD WR

,

, and MODE inputs. The

access modes are INM mode and MNM mode. These modes

are controlled by the MODE input (MODE = 0 for INM,

¹Bits A[9:8] control which channel is decoded for the access.

CS RD

WR

MODE = 1 for MNM).

for each mode.

,

, and

control the access type

For SF2, Bit 0 prompts the startup block to run the start hold-

off counter from the value programmed in the start holdoff

counter control register and to issue a sync when this task is

complete. Bit 4 to Bit 6 are used to enable syncs to individual

blocks in the channels.

PROGRAMMING MODES

The AD6650 can be programmed using several different modes.

These modes include two microport modes, INM mode and

MNM mode. The programming mode is selected by setting the

MODE pins. Table 15 identifies how to set the MODE pins to

select the desired programming mode.

DATA ADDRESS REGISTERS

External Addresses [2:0] form Data Register DR2, Data Register

DR1, and Data Register DR0, respectively. All internal data-

words have widths that are less than or equal to 22 bits. Access

to DR0 triggers an internal access to the AD6650 based on the

address indicated in ACR and CAR. Therefore, during writes to

the internal registers, DR0 must be written last. At this point,

data is transferred to the internal memory location indicated in

A[9:0]. Reads are performed in the reverse sequence. Once the

address is set, DR0 must be the first data register read to initiate

an internal access. DR2 is only six bits wide. Data written to the

upper two bits of this register is ignored. Likewise, reading from

this register produces only 6 LSBs.

Table 15. Programming Modes

MODE [2:0] Description

000

001

010

011

100

101

110

111

Microport Intel nonmultiplexed mode

Microport Motorola nonmultiplexed mode

Reserved

WRITE SEQUENCING

Intel Nonmultiplexed Mode (INM)

Writing to an internal location is achieved by first writing the

upper two bits of the address into Bit 1 and Bit 0 of the ACR

(these bits should be set low). Bits[5:2] can be set to select the

chips for access as indicated above. The CAR is then written

with the lower eight bits of the internal address (it does not

matter if the CAR is written to before the ACR, as long as both

are written to before the internal access). DR2 and DR1 must be

written first because the write to Data Register DR0 triggers the

internal access. DR0 must always be the last register written to

initiate the internal write.

Setting the mode word bits to 000 places the AD6650 in INM

CS RD DS

mode. The access is controlled by the user with the

WR DTACK

,

(

),

W

and

(R/ ) inputs. The RDY (

) signal is produced

by the microport to communicate to the user that an access has

DTACK

been completed. RDY ( ) goes low at the start of the access

and is released when the internal cycle is complete. See Figure 10

and Figure 11 for INM mode read and write timing.

Motorola Nonmultiplexed Mode (MNM)

Setting the mode word bits to 001 places the AD6650 in MNM

READ SEQUENCING

CS DS

mode. The access type is controlled by the user with the

RD WR DTACK

(RDY) signal is

,

Reading from the microport is accomplished in the same

manner. The internal address is set up the same way as it is for a

write. A read from DR0 activates the internal read; therefore,

DR0 must be read first to initiate an internal read followed by

reads from DR1 and DR2.

(

), and R/

(

) inputs. The

generated by the microport to signal the user that an access has

DTACK

W

been completed.

is complete and returns high after

Figure 12 and Figure 13 for MNM mode read and write timing.

(RDY) goes low when an internal access

DS RD

(

) is deasserted. See

Rev. A | Page 31 of 44

AD6650

Bypass (2'b11)

JTAG BOUNDARY SCAN

The bypass instruction allows the IC to remain in normal

functional mode and selects a 1-bit bypass register between TDI

and TDO. During this instruction, serial data is transferred

from TDI to TDO without affecting operation of the IC.

The AD6650 supports a subset of the IEEE Standard 1149.1

specification. For details of the standard, see the IEEE Standard

Test Access Port and Boundary-Scan Architecture, an IEEE-1149

publication.

Sample/Preload (2'b01)

The AD6650 has five pins associated with the JTAG interface.

These pins, listed in Table 16, are used to access the on-chip test

access port. All input JTAG pins are pull-ups except TCLK,

which is a pull-down.

The sample/preload instruction allows the IC to remain in

normal functional mode and selects the boundary scan register

to be connected between TDI and TDO. The boundary scan

register can be accessed by a scan operation to take a sample of

the functional data entering and leaving the IC. Also, test data

can be preloaded into the boundary-scan register before an

extest instruction.

Table 16. Boundary Scan Test Pins

Mnemonic Description

TRST

TCLK

TMS

TDI

Test access port reset

Test clock

Test access port mode select

Test data input

Extest (2'b00)

The extest instruction places the IC into an external boundary-

test mode and selects which boundary scan register is connected

between TDI and TDO. During this operation, the boundary

scan register is accessed to drive test data off-chip via boundary

outputs and receive test data off-chip from boundary inputs.

TDO

Test data output

The AD6650 supports three op codes, listed in Table 17. These

instructions set the mode of the JTAG interface.

Table 17. Boundary Scan Op Codes

Instruction

Op Code

Bypass

Sample/Preload

Extest

11

01

00

A boundary scan description language (BSDL) file for this device is

available. Contact an Analog Devices sales representative for

more information.

Rev. A | Page 32 of 44

AD6650

REGISTER MAP

Table 18. Memory Map

Reg.

(Hex)

Bit

Width

Mnemonic

Description

Additional Information

Code

Result

0

Clock Divider Control

1

Power-up value is 1’b1.

0

Bypass

1

Divide-by-2

1

2

3

4

5

PLL Register 0

PLL Register 1

PLL Register 2

PLL Register 3

Clamp Control

22

6

PLL Control Register 0.

PLL Control Register 1.

PLL Control Register 2.

PLL Control Register 3.

Various VGA control signals.

See Table 19

See Table 20

See Table 21

See Table 22

Power-up value is 6’b100011

Code

Gain (dB)

+1.6 dB

+1.4 dB

+1.2 dB

.

5 to 2: Tweak Gain

4

Provides 1.6 dB of additional gain in VGA in

0.2 dB steps.

0

1

2

.

7

8

+0.2 dB

0 dB

9

.

−0.2 dB

.

14

15

−1.2 dB

−1.4 dB

Result

Enable clamp

Disable clamp

Enable clamp

Disable clamp

Code

1: Clamp Disable B

0: Clamp Disable A

1

Disables clamps at the output of the VGA for

Channel B.

0

1

Disables clamps at the output of the VGA for

Channel A.

0

1

6

7

8

9

A

Reserved

8

2

4

Reserved.

Must be written 8’b00000000

Reserved

Reserved.

Must be written 8’b00000000

Reserved

Reserved.

Must be written 8’b00010001

Reserved

Must be written 0.

Coarse dc correction control registers.

Power-up value is 2’b00

Coarse DC Correction

Power-up value is 4’b0000

Code

Result

3: Cal Now B

2: Cal Now A

1: PN_EN

1

Calibrate coarse dc correction for the

Channel B. Coarse dc correction occurs

automatically at start-up if Bit 0 of the

AutoCalibration control register is set high.

0

1

Disabled

Recalibrate

Calibrate coarse dc correction for the

Channel A. Coarse dc correction occurs

automatically at start-up if Bit 0 of the

AutoCalibration control register is set high.

0

1

Disabled

Recalibrate

Enables the PN sequence generator to test

the digital block.

0

1

Disabled

Enable PN

sequence

generator

Code

Result

0: Coarse DCC Enable

1

Enables coarse DCC. This register must be

held high during start-up sequence for

coarse dc correction to occur.

0

1

Disabled

DCC enabled

Rev. A | Page 33 of 44

AD6650

Reg.

(Hex)

Bit

Width

Mnemonic

Description

Additional Information

B

DC Correction Control

20

Fine DCC control registers.

Power-up value is

20’b00000000000000000000

Code

Level (dBFS)

0 dBFS

19 to 13: Upper

Threshold

7

Fine DCC upper threshold. No new dc

estimation is made if the signal is above the

upper threshold.

0

1

2

.

−0.75 dBFS

−1.5 dBFS

.

126

127

0

−94.5 dBFS

−95.25 dBFS

0 dBFS

12 to 8: Lower Threshold

5

Fine DCC lower threshold. The maximum

range for the lower limit is 0 dBFS to

138.46 dBFS.

1

−6.02 dBFS

2

−12.04 dBFS

.

22

23

−132.44 dBFS

−138.46 dBFS

Integration

Time

Code

7 to 3: Minimum Period

5

Fine DCC integration period.

1

2

3

.

2¹× T_S

2²× T_S

2³× T_S

.

30

31

2³⁰× T_S

2³¹× T_S

T_S= sample

period

Code

Result

2: Bypass

1

Fine DCC bypass.

0

Update DCC

estimate

Keep old

estimate

1

1: Interpolate

Fine DCC interpolator reduces discontinuity

between the current dc estimate and the

new estimate.

0

1

Disabled

Enabled

0: Freeze

1

4

1

Fine DCC freeze is used to hold the current

dc estimate.

0

1

Disabled

Enabled

C

AGC Control 0

3: Force VGA Gain

AGC Control Settings.

Code

Result

Force the VGA gain to a specific value. This

control line overrides the slow loop, fast

decay loop, and fast attack loop when

enabled.

0

1

Disabled

Enable forced

gain mode

2: FD_Enable

1

Fast decay loop enable.

0

1

Disabled

Enable fast

decay loop

Code

Result

1: FA_Enable

0: Reserved

1

Fast attack loop enable.

Reserved.

0

1

Disabled

Enable fast

attack loop

N/A

Rev. A | Page 34 of 44

AD6650

Reg.

(Hex)

Bit

Width

Mnemonic

Description

Additional Information

D

AGC Control 1

9

VGA gain (dB) = (0.094) × VGA gain word.

Code

Gain (dB)

8 to 0: VGA Gain

This drives the VGA directly when force VGA

gain = 1.

0

1

2

.

0 dB

0.094 dB

0.188 dB

.

382

383

35.9 dB

36.002 dB

E

AGC Control 2

16

8

AGC hysteresis and requested level.

Code

Hysteresis (dB)

15 to 8: Hysteresis

Upper hysteresis threshold = requested level

+ hysteresis.

0

1

.094 dB

Lower hysteresis threshold = requested level

− hysteresis.

2

.

.188 dB

.

The gain word does not change if the peak

measurement falls between the upper and

lower hysteresis threshold.

.

254

255

23.876 dB

23.97 dB

Requested

Level (dBm)

Code

7 to 0: Requested Level

8

The requested level for the slow loop. The

full-scale input into the AD6650 is

2 V p-p = 4 dBm.

0

1

2

.

+4 dBm

+3.906 dBm

+3.812 dBm

.

254

255

−19.8 dBm

−19.97 dBm

exponent

F

AGC Control 3

11

3

Loop gain = (mantissa/256) × ½

.

Code

Loop Gain Exp

2⁰

10 to 8: Loop Gain

Exponent

Loop gain exponent (slow loop).

0

1

.

2¹

.

6

7

.

2⁶

2⁷

7 to 6: Reserved

2

6

Reserved.

N/A

Code

0

Mantissa

5 to 0: Loop Gain

Mantissa

Loop gain mantissa (slow loop).

0

1

2

.

62

63

62

63

Rev. A | Page 35 of 44

AD6650

Reg.

(Hex)

Bit

Width

Mnemonic

Description

Additional Information

10

AGC Control 4

13

Fast attack and fast decay loop parameters.

Code

Step size (dB)

12 to 10: FD_Step

3

Fast decay step size.

0

0 dB

1

0.094 dB

2

0.188 dB

.

6

0.564 dB

7

0.658 dB

Code

Threshold

9 to 8: FA_Thresh

7 to 4: FA_Count

2

4

Fast attack threshold measured at the

antialiasing filters.

0

1

2

3

−6.02 dBFS

−3.1 dBFS

−0.915 dBFS

0 dBFS

Code

Count

Fast attack count. The fast attack loop steps

the gain down by FA_Step for FA_Count

number of clock cycles.

0

1

2

1

2

3

.

14

15

Code

Step size (dB)

3 to 0: FA_Step

4

Fast attack step size.

0

0 dB

1

2

.

0.094 dB

0.188 dB

.

14

15

1.316 dB

1.41 dB

11

AGC Control 5

16

8

Slow loop peak detector period.

Samples (f_S

clock cycles)

Code

15 to 8: SPB Peak

Detector Period

Signal plus blocker peak detector period for

the slow loop; f_S= 26 MHz; f_SYM=270.833 kHz;

SPB peak period = ¼ × (f_SAMP/f_SYM).

0

1

2

.

254

255

254

255

7 to 0: Reserved

Reserved

8

7

Reserved.

Must be written 8’b00000000

12

13

Must be written 7’b0000000

AGC Control 7

Code

Threshold

0 dBFS

8 to 0: FD SPB Threshold

Fast decay signal plus blocker threshold.

0

1

2

.

−0.094 dBFS

−0.188 dBFS

.

510

511

−47.94 dBFS

−48.034 dBFS

Rev. A | Page 36 of 44

AD6650

Reg.

(Hex)

Bit

Width

Mnemonic

Description

Additional Information

Code

Count

14

Start Holdoff Counter

16

The power-up sequence is initiated with a

Soft_SYNC or Pin_SYNC and then the start

holdoff counter counts down to 1, and the

chip power-up sequence starts. 0 is an

invalid value.

1

2

.

1

2

.

65,534

65,535

Code

Decimation

15

CIC4 Decimation (M_CIC4− 1)

5

Should be ≥12 because CIC and IIR have

maximum rates of 26 MHz/12.

7

8

9

10

.

30

31

Code

0

31

32

Scale Factor

16

CIC4 Scale (Scale − 12)

4

Controls the attenuation of the data into the

CIC4 stage in 6 dB increments. This register

has a range of 12 to 20, which supports

decimations from 8 to 32 according to

Equation 4.

12

13

1

2

14

.

7

19

8

20

Code

Results

17

18

IIR Control

1

3

Sync mask.

0

1

Disabled

Enabled

Code

Decimation

RCF Decimation Register

(M_RCF− 1)

Decimation of 1 to 8.

0

1

2

3

.

6

7

8

Code

Phase

19

1A

RCF Decimation Phase

3

6

Phase from 0 to M_RCF− 1.

0

1

.

6

7

0

1

.

6

7

(P_RCF

)

Code

Offset

RCF Coefficient Offset

(CO_RCF

Range is 0 to 48 taps.

0

1

0

1

)

2

.

46

47

46

47

Rev. A | Page 37 of 44

AD6650

Reg.

(Hex)

Bit

Width

Mnemonic

RCF Taps (N_Taps− 1)

Description

Additional Information

Code

Taps

1B

6

1 to 48.

0

1

2

.

46

47

48

Code

Scale Factor

−18 dB

−12 dB

−6 dB

0 dB

1C

RCF Scale

2

0, −6 dB, −12 dB, and −18 dB gain adjust to

prevent coefficients from clipping the MAC.

0

1

2

3

1D

1E

1F

20

21

BIST for A-I

BIST for A-Q

BIST for B-I

BIST for B-Q

Serial Control

24

9

16-bit data available, I/DATA_I.

16-bit data available, Q/DATA_Q.

16-bit data available, I/DATA_I.

16-bit data available, Q/DATA_Q.

Power-up value is 9’bxxxxx0xxx for Bit 3 to

make it a serial slave.

1

Data is available through the I/Q BIST

registers when Bit 8 is high.

8: Fine DCC Data to BIST

Code

Results

7: B Data Serial Ouput

Select

1

Port B data serial output select.

0

Use SDO0 for

B data

1

Use SDO1 for

B data

6 to 5: I_SDFS Control

2

Serial port control functions.

0

1

2

AI pulse

AI, BI pulses

AI, AQ, BI,

BQ pulses

3

High for

SDO0 valid

4: SOWL

3: SBM

1

Serial output word length.

Serial bus master.

0

1

0

1

16-bit words

24-bit words

Serial slave

Serial bus

master

2 to 0: SDIV [2:0]

3

Serial divider.

0

.

Divide-by-1

.

7

Divide-by-8

22

AutoCalibration Control

4

New calibration sequence control registers.

Power-up value is 4’b0000.

3: Reserved

2: Reserved

1

Reserved.

Must be written 0

Must be written 1

Code

Results

1: DAC Power-Down

Disable

1

Power down VGA DACs during the power-up

sequence to calibrate the dc offset.

0

Power down

DACs

DACs on

Disabled

Enabled

1

0

1

0: Enable

Autocalibration enable.

23 to

3F

Reserved

40 to

6F

Coefficient Memory

Reserved

Common coefficients for Channel A and

Channel B.

48 × 20 bit RAM

70 to

FF

Rev. A | Page 38 of 44

AD6650

REGISTER DETAILS

Table 19. PLL Register 0: Control Latch

CH Address

Register

Description

Comment

DB21 to DB0

RSVD

Reserved

Must be written 00 0000 0111 1100 0100 0000 (MSB ... LSB).

Table 20. PLL Register 1: R Counter Latch

CH Address

DB21 to DB14

DB13 to DB0

Register

Description

Comment

RSVD

R1 to R14

Reserved

14-bit reference counter, R

Must be written 0001 0100 (DB21 ... DB14).

Table 21. PLL Register 2: N Counter Latch

CH Address

DB21 to DB19

DB18 to DB6

DB5

Register

Description

Comment

RSVD

B13 to B1

RSVD

Reserved

13-bit B counter

Reserved

Must be written 000.

B13 to B1 programs the 13-bit B counter.

Must be written 0.

DB4 to DB0

A5-A1

5-bit A counter

A5 to A1 programs the 5-bit counter. The divide range is 0 (00000) to 31 (11111).

Table 22. PLL Register 3—Reserved

CH Address

Register

Bit Definitions

Comment

DB21 to DB0

RSVD

Reserved

Must be written 11 0001 1000 0000 0000 0000 (MSB ... LSB).

0x00: Clock Divider Control [1]

0x05: Clamp Control [5:0]

The clock divider control bit sets the internal clock rate for the

AD6650. If this bit is set low and the clock rate is ≤52 MSPS, the

internal divide-by-2 is bypassed. If a faster clock rate is desired,

the clock divider control bit should be set high. By setting this

bit high, the internal divide-by-2 is used.

This register either enables or disables the clamps on the output

of the mixers. These clamps should be enabled.

0x06: Reserved [8:0]

This register is reserved and must be written 00000000.

0x07: Reserved [8:0]

0x01: PLL Control Register 0 [21:0]

This register is reserved and must be written 00000000.

0x08: Reserved [8:0]

This register is reserved and must be written 00 0000 0111 1100

0100 0000 (MSB ... LSB).

This register is reserved and must be written 00010001.

0x09: Reserved [1:0]

0x02: PLL Control Register 1 [21:0]

DB13 to DB0: These bits are used to set the R-counter for the PLL.

This register is reserved and should be written low.

DB21 to DB14: These bits are reserved and must be written

0001 0100.

0x03: PLL Control Register 2 [21:0]

DB4 to DB0: This 5-bit register is used to set the value for the A

counter in the PLL.

DB5: This bit is reserved and must be written to 0.

DB18 to DB6: This 13-bit register is used to set the value for the

B-counter in the PLL.

DB21 to DB19: These bits are reserved and must be written 000.

0x04: PLL Control Register 3 [21:0]

This register is reserved and must be written 11 0001 1000 0000

0000 0000 (MSB ... LSB).

Rev. A | Page 39 of 44

AD6650

0x0A: Coarse DC Correction Control Register [3:0]

the peak detectors in the fine dc correction block ranges off the

dc content as well as the signal of interest.

Address 0xA is the coarse dc correction control register. It is

used to enable the coarse correction with Bit 0 and to initiate

calibrations on Channel A and/or Channel B. Bit 3 and Bit 2 of

this register can be used to initiate coarse calibrations when the

device is running and can be used in conjunction with an

external switch if desired. Bit 1 is used to activate the internal

pseudorandom noise generator, which is useful for looking at

the digital filter response and performing the built-in self-test.

Bit 12 to Bit 8

The lower threshold determines where the minimum integration

period is used. When the peak of the input to the fine dc

correction block is lower than this level, the accumulators

average 2^Min_periodsamples at the output rate (1 or 2 samples/symbol).

When the peak of the signal increases above this, the integration

periods increase by a factor of 4 for every 6 dB that the signal

power increases.

Table 23. Coarse DC Correction Control Functions

Bit No.

Description

Calibrate B

Calibrate A

PN_EN

It should be noted that any dc content left after the coarse

correction can be seen by the fine dc correction peak detector

and causes the integration period to change. For example, if the

lower threshold is −96 dBFS and the dc content is −78 dBFS, the

signal is at least 18 dB larger; therefore, the integration period is

at least 64× (that is, 4^18/6) the minimum period.

3

2

1

0

CDCC enable

0xB: Fine DC Correction Filter [19:0]

The lower threshold can be set near the upper threshold to

provide a constant integration period of 2^Min_periodif desired.

The fine dc correction block is used to provide a good dc

correction for small signals that are under the range of the AGC

loop. Address 0xB has four parameters.

Bit 7 to Bit 3

This interval is equal to 2^Min_period. The minimum period

determines the integration period when the peak signal power

into the fine dc correction block is less than the lower threshold.

This can be used in combination with the lower threshold to

make sure there is enough integration to estimate the dc for

small signals.

Table 24. Fine DC Correction Filter Functions

Bits

Description

Upper threshold

Lower threshold

Minimum period

Bypass

19 to 13

12 to 8

7 to 3

2

1

0

If Min_period is 12, the period of integration for a signal with

power less than or equal to −96.32 dBFS is 4096 samples. For

each 6.02 dBFS increase in the signal power, the integration

period quadruples. The Min_period register can be programmed

from 1 to 31; 0 is not a valid value for this register.

Interpolator enable

Freeze

Bit 19 to Bit 13

The upper threshold disables the fine dc correction algorithm for

large input signals that could potentially contain significant dc

content from the modulated data. This should be set below the

range of the AGC loop, which is equal to the requested level of

−36 dB. It should also be set above the uncorrected dc level so that

the fine DCC is guaranteed to range.

Bit 2

This is the bypass bit that effectively shuts down the fine dc

correction block. When this bit is 1, no correction is performed.

Bit 1

The upper threshold should be set low enough so that the dc

content is not estimated while the loop is ranging because the

changing gain distorts the estimate. Setting the upper threshold

lower also decreases effects from dc content in the signal such

as dc offset from modulated data with high correlations or

mobiles with LO feedthrough.

This bit enables an interpolator that can smooth out the

updated estimate transition by a fixed interpolation by 256. This

is a linear interpolator that allows the correction block to gradually

shift between the old estimate and the new estimate to avoid

transients if there has been significant dc shift. If disabled, the

shift in correction values happens instantaneously, causing a

discontinuity in the signal; however, if the interpolator is enabled,

this shift occurs over 256 samples, preventing any large

discontinuities. The interpolator should not be enabled if

Min_period is set to less than 8 (a period of 256 samples). Use

of the interpolator is not recommended at this time, and this bit

should be set to 0.

It is equally important not to set the upper threshold too low.

If the upper threshold is set so low that the desired signal is

consistently higher than this threshold, a new dc estimate, which

is necessary to compensate for power supply or temperature

drifts, will not occur. Therefore, a thorough understanding of

the signal statistics for the application is required.

Bit 0

As a guideline, the upper threshold should be set between

−40 dBFS and −70 dBFS. If it is set below −72 dBFS, the

uncorrected dc offset from the analog front end and coarse

correction can increase the effective minimum period because

When set to 1, this bit freezes the estimate of the dc correction

and resets the peak detector to the smallest possible signal state

(−138 dB peak signal). This way, the dc can be estimated once

Rev. A | Page 40 of 44

AD6650

and constantly corrected. This is useful for debugging and for

use when the dc estimate can be performed at discrete

predefined times.

Bit 7 to Bit 0

These lower eight bits set the requested level for the AGC slow

loop. Setting the code to 0 sets the requested level to +4 dBm,

which corresponds to the full-scale input of the AD6650.

Setting the code to 255 sets the requested level to −19.9ꢀ dBm.

Even though the upper threshold register can vary between 0

and 15 and the Min_period register can vary between 1 and 31,

only certain combinations of the two are valid. This is because

the growth is restricted to 34 bits. Equation 23 can be used to

determine if a combination of values is valid. If C < 0, the

combination is invalid; otherwise, the combination is valid.

0x0F: AGC Control 3 [10:0]

Bit 10 to Bit 8

This 3-bit register sets the loop gain exponent

for the slow loop of the AD6650 AGC. The values can range

from 0 to ꢀ. The equation for the loop gain is noted in the AGC

Loop/Relinearization section.

C = 34 − (2 × (16 − Upper Threshold) + Min_period) (23)

0x0C: AGC Control 0 [3:0]

Bit 3

Bit 7 to Bit 6

The force VGA gain control register allows the user to force the

VGA gain to a specific value. This control line overrides the slow

loop, fast decay loop, and fast attack loop when enabled. By setting

this bit low, the force VGA gain control is disabled. By setting

this bit high, the force VGA gain control is enabled. For normal

operation, this bit should be disabled.

These two bits are reserved and should be written low.

Bit 5 to Bit 0

This 6-bit register represents the loop gain mantissa for the slow

loop of the AD6650 AGC. The values for this register range from 0

to 63. The equation for the loop gain is noted in the AGC

Loop/Relinearization section.

Bit 2

0x10: AGC Control 4 [12:0]

By setting this bit high, the fast decay loop is enabled; by setting

this bit low, the fast decay loop is disabled. It is recommended

that the fast decay loop be enabled for normal operation. For a

description of the fast decay functionality, see the AGC

Loop/Relinearization section.

Bit 12 to Bit 10

This 3-bit register is used to set the fast decay step size. The gain

continues to increase until it has reached the fast decay

threshold or until the maximum gain has been reached.

Bit 1

Bit 9 to Bit 8

By setting this bit high, the fast attack loop is enabled; by setting

this bit low, the fast attack loop is disabled. It is recommended

that the fast decay loop be enabled for normal operation. For a

description of the fast attack functionality, see the AGC

Loop/Relinearization section.

This 2-bit register sets the threshold for the fast attack AGC

loop. When the desired signal reaches this threshold, the gain is

reduced by the FA_Step for FA_Count number of clock cycles.

Bit 7 to Bit 4

The fast attack loop steps the gain down by FA_Step for

FA_Count number of clock cycles.

Bit 0

This bit is reserved and should be written low.

0x0D: AGC Control 1 [8:0]

Bit 3 to Bit 0

The FA_Step register determines how large a step to take once

the fast attack threshold has been reached. This value is

expressed in decibels.

If the force VGA bit is enabled in AGC Control Register 0

(Bit 3 = 1), this register controls the gain setting for the VGA.

The gain is controlled in 0.094 dB steps with a maximum gain

of 36 dB. Code 0 corresponds to 0 dB gain or minimum gain,

whereas Code 383 corresponds to 36 dB gain or maximum gain.

0x11: AGC Control 5 [15:0]

Bit 15 to Bit 8

0x0E: AGC Control 2 [15:0]

This 8-bit register sets the signal plus blocker peak detector

period for the AGC slow loop. It can be set from 0 to 255 samples.

The AGC Control 2 register is a 16-bit register that sets the

amount of hysteresis used in the AGC loop and sets the

requested level for the AGC loop.

Bit 7 to Bit 0

Reserved and must be written 00000000.

0x12: Reserved [6:0]

Bit 15 to Bit 8

These upper bits set the hysteresis level in 0.094 dB steps. Code 0

corresponds to 0 dB of hysteresis, and Code 255 corresponds to

23.9ꢀ dB of hysteresis.

This register is reserved and must be written 0000000.

0x13: AGC Control 7 [8:0]

This 9-bit register is used to set the threshold for the fast decay

signal plus blocker. Values can range from 0 dBFS to −48 dBFS.

Rev. A | Page 41 of 44

AD6650

The peak detector for this threshold monitors the desired signal

and blocker peaks at the ADC output.

0x1B: RCF Taps Minus One (N_TAPS− 1) [5:0]

The number of taps for the RCF filter minus one is written to

this register.

0x14: Start Holdoff Counter [15:0]

The start holdoff counter is loaded with the value written to this

address when a sync is initiated. It can be initiated by either a

Soft_SYNC or Pin_SYNC. The counter begins decrementing,

and when it reaches a value of 1, the channel exits sleep mode

and begins processing data. If this register is written 1, the start

occurs immediately when the SYNC comes into the channel. If

it is written 0, no SYNC occurs.

0x1C: RCF Scale Register [1:0]

This 2-bit register represents the output scale factor of the RCF.

This register is used to scale the output data between 0 dB and

−18 dB in 6 dB steps.

0x1D to 0x20: BIST Register [23:0]

These four registers allow the complete digital functionality of

the I and Q data path in the A and B channels to be tested in the

system. See the User-Configurable Built-In Self-Test (BIST)

section for more details.

0x15: CIC4 Decimation Minus One (M_CIC4− 1) [4:0]

This register is used to set the decimation in the CIC4 filter. The

value written to this register is the decimation minus one. The

value of this register should be 12 or greater because the CIC

and IIR have maximum rates of 26 MHz/12. Although this is a

5-bit register, the decimation is usually limited to between 12

and 32. Decimations higher than 32 require more scaling than

the CIC4’s capability.

0x21: Serial Control Register [8:0]

This register controls the serial port of the AD6650 and

determines the output format.

Bit 8

Fine DCC data to BIST.

0x16: CIC4 Scale [3:0]

Bit 7

The CIC4 scale factor is used to compensate for the growth of

the CIC4 filter. See the Fourth-Order Cascaded Integrator

Comb Filter (CIC4) section for details.

If this bit is enabled (set high), Channel B data is output on

Serial Data Output 1 (SDO1).

Bit 6 to Bit 5

0x17: IIR Control Register [1]

Choose the serial data frame sync (SDFS) mode. See the Serial

Data Frame Sync section for a full description of each mode. The

following bits select the corresponding mode.

Address 0x17 is the IIR control register. When this bit is set to 0,

the sync mask is disabled. In this mode, after a SYNC is issued

to the AD6650, the IIR data path is not cleared. If the sync mask

is enabled, the bit is set to 1, and the data path is cleared of its

contents and starts accumulating new data on the first valid

clock after a Soft_SYNC or Pin_SYNC is issued.

Table 25. Serial Port Control Functions

Bits

Description

11

10

01

High for SDO0 valid

AI, AQ, BI, BQ pulses

AI, BI pulses

0x18: RCF Decimation Register Minus One (M_RCF− 1) [2:0]

This register is used to set the decimation of the RCF stage. The

value written is the decimation minus one. This is a 3-bit

register that allows decimations up to 8.

00

AI pulse

Bit 4

0x19: RCF Decimation Phase (P_RCF) [2:0]

By setting this bit low, the output data stream is 16-bit I and 16-bit

Q data-words for both the A and B channels. By setting this bit

high, the output data stream is 24-bit I and 24-bit Q data words

for both the A and B chan nels. To fully realize the dynamic range

of the AD6650, it is recommended that the 24-bit mode be used.

This register allows any one of the MRCF phases of the filter to

be used and can be adjusted dynamically. Each time a filter is

started, this phase is updated. When a channel is synchronized,

it retains the phase setting selected. This can be used as part of a

timing recovery loop with an external processor or can allow

multiple RCFs to work together while using a single RCF pair.

See the RAM Coefficient Filter section for more details.

Bit 3

By setting this bit high, the AD6650 becomes the serial bus

master. It is recommended that this bit be enabled (set high).

0x1A: RCF Coefficient Offset (CO_RCF) [5:0]

Bit 2 to Bit 0

This register is used to specify which section of the 256-word

coefficient memory is used for a filter. It can be used to select

among multiple filters that are loaded into memory and

referenced by this pointer. This register is shadowed and the

filter pointer is updated every time a new filter is started. This

allows the coefficient offset to be written even while a filter is

being computed without disturbing operation. The next sample

that comes out of the RCF will be with the new filter.

This 3-bit register controls the divider on the serial clock

(SCLK) on the output of the AD6650. It is possible to divide the

SCLK by 8, allowing a flexible interface to a DSP or FPGA.

Rev. A | Page 42 of 44

AD6650

0x22: Autocalibration Register [3:0]

Bit 0

Address 0x22 is the autocalibration register and controls the

automatic coarse dc autocalibration at start-up.

Enables the autocalibration. This should be set to 1 for

the calibration to run automatically. Then the AD6650 waits

approximately 20.63 ms after a Soft_SYNC or Pin_SYNC

enables the part and then runs a coarse dc calibration. This

allows some warm-up time for the analog path to thermally

stabilize.

Bit 3

Reserved. This bit should be set to 0.

Bit 2

Reserved. This bit should be set to 1.

0x23 to 0x3F: Reserved

These registers must not be written.

0x40 to 0x6F: Coefficient Memory

Bit 1

Determines whether to power down the VGA and mixer on a

coarse calibration. This should be set to 0 to allow the state

machine to power down the VGA and mixer. If it is known that

there is no dc input into the part, this can be set to 1 to improve

the correction performance, which allows more flexibility in

setting the lower threshold.

This memory is utilized to store up to forty-eight 20-bit RCF

coefficients shared by Channel A and Channel B.

0x70 to 0xFF: Reserved

These registers must not be written.

Rev. A | Page 43 of 44

AD6650

OUTLINE DIMENSIONS

A1 CORNER

INDEX AREA

12.20

12.00 SQ

11.80

11 10

9

7

8 6 5 3

4 2 1

A

B

C

D

E

F

BALL A1

CORNER

10.00

BSC SQ

G

H

J

1.00

BSC

K

L

BOTTOM VIEW

DETAIL A

TOP VIEW

DETAIL A

*

1.85

1.71

1.40

*

1.31

1.21

1.11

0.50 NOM

0.30 MIN

0.20

COPLANARITY

0.70

0.60

0.50

SEATING

PLANE

BALL DIAMETER

*COMPLIANT WITH JEDEC STANDARDS MO-192-ABD-1 WITH

EXCEPTION TO PACKAGE HEIGHT AND THICKNESS.

Figure 42. 121-Lead Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-121)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range¹

−25°C to +85°C

Package Description

Package Option

BC-121

AD6650ABC

AD6650ABCZ²

AD6650BBC

AD6650BBCZ²

AD6650/PCB

121-Lead Chip Scale Package Ball Grid Array [CSP_BGA]

Evaluation Board with AD6650 and Software

¹The AD6650 is guaranteed fully functional from −40°C to +85°C. All ac minimum specifications are guaranteed from −25°C to +85°C, but degrade slightly from −25°C

to −40°C.

²Z = Pb-free part.

registered trademarks are the property of their respective owners.

D03683-0-1/07(A)

Rev. A | Page 44 of 44


型号：	AD6650ABCZ
厂家：	Rochester Electronics
描述：	TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PBGA121, LEAD FREE, MO-192AED-1, BGA-121 蜂窝电信电信集成电路
文件：	总45页 (文件大小：2520K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD6650ABCZ [ROCHESTER]

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