AD5516ABCZ-2_技术文档

16-Channel, 12-Bit Voltage-Output DAC

with 14-Bit Increment Mode

AD5516^*

FEATURES

GENERAL DESCRIPTION

High Integration:

16-Channel DAC in 12 mm

؋

12 mm CSPBGA

The AD5516 is a 16-channel, 12-bit voltage-output DAC. The

selected DAC register is written to via the 3-wire serial inter-

14-Bit Resolution via Increment/Decrement Mode

Guaranteed Monotonic

face. DAC selection is accomplished via address bits A3–A0.

14-bit resolution can be achieved by fine adjustment in Incre-

ment/Decrement Mode (Mode 2). The serial interface operates

at clock rates up to 20 MHz and is compatible with standard

SPI, MICROWIRE, and DSP interface standards. The output

voltage range is fixed at ±2.5 V (AD5516-1), ±5 V (AD5516-2),

and ±10 V (AD5516-3). Access to the feedback resistor in each

channel is provided via the R_FB0 to R_FB15 pins.

Low Power, SPI^®, QSPI™

DSP Compatible

, MICROWIRE™, and

3-Wire Serial Interface

Output Impedance 0.5 ⍀

Output Voltage Range

؎2.5 V (AD5516-1)

؎5 V (AD5516-2)

؎10 V (AD5516-3)

Asynchronous Reset Facility (via RESET Pin)

Asynchronous Power-Down Facility (via PD Pin)

Daisy-Chain Mode

The device is operated with AV_CC= 5 V ± 5%, DV_CC= 2.7 V

to 5.25 V, V_SS= –4.75 V to –12 V, and V_DD= +4.75 V to +12 V,

and requires a stable 3 V reference on REF_IN.

PRODUCT HIGHLIGHTS

1. Sixteen 12-bit DACs in one package, guaranteed monotonic.

Temperature Range: –40؇C to +85؇C

APPLICATIONS

Level Setting

Instrumentation

2. Available in a 74-lead CSPBGA package with a body size of

12 mm ϫ 12 mm.

Automatic Test Equipment

Optical Networks

Industrial Control Systems

Data Acquisition

Low Cost I/O

FUNCTIONAL BLOCK DIAGRAM

DV

AV

CC

V

SS

REF_IN

CC

DD

V

BIAS

R

FB

OFFS

R

0

FB

AD5516

V

0

OUT

DAC

R

RESET

BUSY

OFFS

R

1

FB

V

1

ANALOG

CALIBRATION

LOOP

OUT

R

OFFS

R

14

FB

DACGND

V

14

OUT

AGND

DGND

R

OFFS

MODE1

R

15

FB

V

15

OUT

INTERFACE

CONTROL

LOGIC

MODE2

7-BIT BUS

DCEN

POWER-DOWN

LOGIC

SCLK

D

PD

SYNC

OUT

IN

*Protected by U.S. Patent No. 5,969,657; other patents pending.

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

(V_DD= +4.75 V to +13.2 V, V_SS= –4.75 V to –13.2 V; AV_CC= 4.75 V to 5.25 V; DV_CC=

2.7 V to 5.25 V; AGND = DGND = DACGND = 0 V; REF_IN = 3 V; All outputs unloaded.

All specifications T_MINto T_MAX, unless otherwise noted.)

AD5516–SPECIFICATIONS

Parameter¹

A Version²

Unit

Conditions/Comments

DAC DC PERFORMANCE

Resolution

12

Bits

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

Increment/Decrement Step-Size

Bipolar Zero Error

Positive Full-Scale Error

Negative Full-Scale Error

±2

LSB max

LSB typ

LSB max

Mode 1

–1/+1.3

±0.25

±7

±0.5 LSB typ, Monotonic; Mode 1

Monotonic; Mode 2 Only

±10

VOLTAGE REFERENCE

REF_IN

Nominal Input Voltage

Input Voltage Range³

Input Current

3

V

2.875/3.125

±1

V min/max

mA max

< 1 nA typ

of FSR

ANALOG OUTPUTS (V_OUT0–15)

Output Temperature Coefficient^{3, 4}

DC Output Impedance³

Output Range⁵

10

0.5

ppm/∞C typ

W typ

AD5516-1

AD5516-2

±2.5

±5

V typ

kW min

pF

mA typ

dB typ

LSB max

100 mA Output Load

AD5516-3

±10

5

Resistive Load^{3, 6, 7}

Capacitive Load^{3, 6}

200

7

–85

0.1

Short Circuit Current³

DC Power Supply Rejection Ratio³

DC Crosstalk³

V_DD= +12 V ± 5%, V_SS= –12 V ± 5%

DIGITAL INPUTS³

Input Current

Input Low Voltage

±10

0.8

0.4

2.4

2

mA max

V max

V min

mV typ

pF max

±5 mA typ

DV_CC= 5 V ± 5%

DV_CC= 3 V ± 10%

DV_CC= 5 V ± 5%

DV_CC= 3 V ± 10%

Input High Voltage

Input Hysteresis (SCLK and SYNC)

Input Capacitance

150

10

5 pF typ

3

DIGITAL OUTPUTS (BUSY, D_OUT

Output Low Voltage, DV_CC= 5 V

Output High Voltage, DV_CC= 5 V

Output Low Voltage, DV_CC= 3 V

Output High Voltage, DV_CC= 3 V

)

0.4

4

0.4

2.4

±1

5

V max

V min

V max

V min

mA max

pF typ

Sinking 200 mA

Sourcing 200 mA

Sinking 200 mA

Sourcing 200 mA

DCEN = 0

High Impedance Leakage Current (D_OUTonly)

High Impedance Output Capacitance (D_OUTonly)

DCEN = 0

POWER REQUIREMENTS

Power Supply Voltages

V_DD

V_SS

AV_CC

4.75/15.75

–4.75/–15.75

4.75/5.25

2.7/5.25

V min/max

DV_CC

Power Supply Currents⁸

I_DD

I_SS

AI_CC

5

17

1.5

mA max

3.5 mA typ. All Channels Full-Scale.

13 mA typ

DI_CC

1 mA typ

Power-Down Currents⁸

I_DD

I_SS

AI_CC

DI_CC

1

2

mA typ

mA max

200 nA typ

V_DD= +5 V, V_SS= –5 V

Power Dissipation⁸

105

mW typ

NOTES

¹See Terminology section.

²A Version: Industrial temperature range –40∞C to +85∞C; typical at +25∞C.

³Guaranteed by design and characterization; not production tested.

⁴AD780 as reference for the AD5516.

⁵Output range is restricted from V_SS+ 2 V to V_DD– 2 V. Output span varies with reference voltage and is functional down to 2 V.

⁶Ensure that you do not exceed T_{J (MAX)}. See Absolute Maximum Ratings section.

⁷With 5 k

W resistive load, footroom required is as follows: AD5516–1, 2 V; AD5516–2, 2.5 V; AD5516–3, 3 V.

⁸Outputs unloaded.

Specifications subject to change without notice.

–2–

REV. B

AD5516

(V_DD= +4.75 V to +13.2 V, V_SS= –4.75 V to –13.2 V; AV_CC= 4.75 V to 5.25 V; DV_CC= 2.7 V to 5.25 V;

AGND = DGND = DACGND = 0 V; REF IN = 3 V. All outputs unloaded.

All specifications T_MINto T_MAX, unless otherwise noted.)

AC CHARACTERISTICS

Parameter^{1, 2}

A Version³

Unit

Conditions/Comments

Output Voltage Settling Time (Mode 1)⁴

AD5516–1

100 pF, 5 kW Load Full-Scale Change

32

36

␮s max

AD5516–2

AD5516–3

Output Voltage Settling Time (Mode 2)⁴

AD5516–1

100 pF, 5 kW Load, 127 Code Increment

2.5

3.35

7

0.85

1

␮s max

V/␮s typ

nV-s typ

AD5516–2

AD5516–3

Slew Rate

Digital-to-Analog Glitch Impulse

Digital Crosstalk

Analog Crosstalk

AD5516–1

AD5516–2

AD5516–3

Digital Feedthrough

Output Noise Spectral Density @ 10 kHz

AD5516–1

1 LSB Change around Major Carry

5

1

5

20

1

nV-s typ

150

350

700

nV/(Hz)^1/2typ

AD5516–2

AD5516–3

NOTES

¹See Terminology section.

²Guaranteed by design and characterization; not production tested.

³A version: Industrial temperature range –40∞C to +85∞C.

⁴Timed from the end of a write sequence and includes BUSY low time.

Specifications subject to change without notice.

(V_DD= +4.75 V to +13.2 V, V_SS= – 4.75 V to –13.2 V; AV_CC= 4.75 V to 5.25 V; DV_CC= 2.7 V to 5.25 V;

TIMING CHARACTERISTICS AGND = DGND = DACGND = 0 V. All specifications T_MINto T_MAX, unless otherwise noted.)

Limit at T_MIN, T_MAX

(A Version)

Parameter^{1, 2, 3}

Unit

Conditions/Comments

f_UPDATE1

f_UPDATE2

f_CLKIN

t₁

t₂

t₃

t₄

t₅

32

750

20

15

5

kHz max

MHz max

ns min

ns max

ns min

DAC Update Rate (Mode 1)

DAC Update Rate (Mode 2)

SCLK Frequency

SCLK High Pulsewidth

SCLK Low Pulsewidth

SYNC Falling Edge to SCLK Falling Edge Setup Time

D_INSetup Time

5

0

D_INHold Time

t₆

t₇

SCLK Falling Edge to SYNC Rising Edge

Minimum SYNC High Time (Standalone Mode)

Minimum SYNC High Time (Daisy-Chain Mode)

BUSY Rising Edge to SYNC Falling Edge

18th SCLK Falling Edge to SYNC Falling Edge (Standalone Mode)

SYNC Rising Edge to SCLK Rising Edge (Daisy-Chain Mode)

SCLK Rising Edge to D_OUTValid (Daisy-Chain Mode)

RESET Pulsewidth

10

400

10

200

10

20

t_7MODE2

t_8MODE1

t_9MODE2

t₁₀

4

t₁₁

t₁₂

NOTES

¹See Timing Diagrams in Figures 1 and 2.

²Guaranteed by design and characterization; not production tested.

³All input signals are specified with tr = tf = 5 ns (10% to 90% of DV_CC) and timed from a voltage level of (V_IL+ V_IH)/2.

⁴This is measured with the load circuit of Figure 3.

Specifications subject to change without notice.

REV. B

–3–

AD5516

TIMING DIAGRAMS

SCLK

1

2

17

t₁

18

t₃

t₂

t₆

t₇

SYNC

t₉MODE2

t₄

t₅

MSB

LSB

BIT 0

DIN

BIT 17

t₈MODE1

BUSY

t₁₂

RESET

Figure 1. Serial Interface Timing Diagram

SCLK

t₃

t₂

t₁

t₁₀

t₇MODE2

t₆

SYNC

t₄

t₅

MSB

BIT 17

LSB

D

BIT 0 BIT 17

BIT 0

IN

INPUTWORD FOR DEVICE N

INPUTWORD FOR DEVICE N+1

INPUTWORD FOR DEVICE N

t₁₁

BIT 17

D

BIT 0

OUT

t₈MODE1

UNDEFINED

BUSY

Figure 2. Daisy-Chaining Timing Diagram

I

200␮A

OL

TO OUTPUT

1.6V

C

L

50pF

I

200␮A

OH

Figure 3. Load Circuit for D_OUTTiming Specifications

–4–

REV. B

AD5516

ABSOLUTE MAXIMUM RATINGS^{1, 2}

(T_A= 25°C, unless otherwise noted.)

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature (T_{J MAX}) . . . . . . . . . . . . . . . . . . . 150°C

74-Lead CSPBGA Package, ␪_JAThermal Impedance . . . 41°C/W

Reflow Soldering

V_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V

V_SSto AGND . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –17 V

AV_CCto AGND, DACGND . . . . . . . . . . . . . . .–0.3 V to +7 V

DV_CCto DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V

Digital Inputs to DGND . . . . . . . . . . . –0.3 V to DV_CC+ 0.3 V

Digital Outputs to DGND . . . . . . . . . . –0.3 V to DV_CC+ 0.3 V

REF_IN to AGND, DACGND . . . . . . –0.3 V to AV_CC+ 0.3 V

V_OUT0–15 to AGND . . . . . . . . . . . . V_SS– 0.3 V to V_DD+ 0.3 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

R_FB0–15 to AGND . . . . . . . . . . . . . V_SS– 0.3 V to V_DD+ 0.3 V

Operating Temperature Range, Industrial . . . . . –40°C to +85°C

Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

Time at Peak Temperature . . . . . . . . . . . . . 10 sec to 40 sec

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause permanent

damage to the device. This is a stress rating only; functional operation of the device

at these or any other conditions above those listed in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

²Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

Output Voltage Span

Model

Function

Package Option

AD5516ABC-1

AD5516ABC-2

AD5516ABC-3

EVAL-AD5516-1EB

EVAL-AD5516-2EB

EVAL-AD5516-3EB

16 DACs

2.5 V

5 V

10 V

74-Lead CSPBGA

Evaluation Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

AD5516 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended

to avoid performance degradation or loss of functionality.

REV. B

–5–

AD5516

PIN CONFIGURATION

1

2 3 4 5 6 7 8 9 10 11

A

B

C

D

E

F

A

B

C

D

E

F

TOP VIEW

G

H

J

G

H

J

K

L

K

L

1

2 3 4 5 6 7 8 9 10 11

74-LEAD CSPBGA BALL CONFIGURATION

CSPBGA Ball CSPBGA Ball CSPBGA Ball

CSPBGA Ball

CSPBGA

Number

Ball

Name

Number

Name

Number

Name

Number

Name

Number

Name

K9

K10

K11

L1

L2

L3

L4

L5

L6

L7

R_FB10

D11

E1

E2

E10

E11

F1

NC

V_OUT

NC

AGND1

PD

V_OUT

R_FB

AGND2

R_FB14

H10

H11

J1

J2

J6

J10

J11

K1

K2

K3

K4

K5

K6

K7

K8

V_OUT13

V_OUT12

R_FB3

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

B1

B2

B3

B4

NC

B5

B6

B7

B8

DGND

NC

SCLK

NC

R_FB9

1

V_OUT11

NC

RESET

BUSY

DGND

DV_CC

D_OUT

D_IN

SYNC

NC

DCEN

V_OUT

4

V_OUT

6

B9

NC

R_FB12

R_FB11

R_FB6

2

B10

B11

C1

C2

C6

C10

C11

D1

D2

D10

V_OUT

NC

7

F2

1

REF_IN

F10

F11

G1

V_OUT

0

R_FB

4

V_DD2

DACGND

NC

V_OUT

5

V_DD1

R_FB2

R_FB

5

L8

L9

L10

L11

R_FB7

AV_CC

NC

1

G2

R_FB15

V_OUT14

R_FB13

NC

V_SS2

V_SS1

V_OUT

8

G10

G11

H1

R_FB8

R_FB

DACGND

AV_CC

0

NC

V_OUT10

V_OUT

V_OUT3

2

9

H2

V_OUT15

NC = Not Internally Connected

PIN FUNCTION DESCRIPTIONS

Mnemonic

Function

AGND (1–2)

AV_CC(1–2)

Analog GND Pins

Analog Supply Pins. Voltage range from 4.75 V to 5.25 V.

V_DDSupply Pins. Voltage range from 4.75 V to 15.75 V.

V_SSSupply Pins. Voltage range from –4.75 V to –15.75 V.

Digital GND Pins

Digital Supply Pin. Voltage range from 2.7 V to 5.25 V.

Reference GND Supply for All 16 DACs

Reference Input Voltage for All 16 DACs. The recommended value of REF_IN is 3 V.

Analog Output Voltages from the 16 DAC Channels

Feedback Resistors. For nominal output voltage range, connect each R_FBto its corresponding V_OUT. Access to

the feedback resistors enables the user to increase the DAC current drive or generate programmable current

sources. They should not be used for gain adjustment.

V

_DD(1–2)

_SS(1–2)

DGND

DV_CC

DACGND

REF_IN

V

R

_OUT(0–15)

_FB(0–15)

SYNC

Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is

transferred in on the falling edge of SCLK.

–6–

REV. B

AD5516

PIN FUNCTION DESCRIPTIONS (continued)

Mnemonic

Function

SCLK

Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock

speeds up to 20 MHz.

D_IN

Serial Data Input. Data must be valid on the falling edge of SCLK.

D_OUT

Serial Data Output. D_OUTcan be used for daisy-chaining a number of devices together or for reading back the

data in the shift register for diagnostic purposes. Data is clocked out on D_OUTon the rising edge of SCLK and is

valid on the falling edge of SCLK.

Active High Control Input. This pin is tied high to enable Daisy-Chain Mode.

Active Low Control Input. This resets all DAC registers to power-on value.

DCEN¹

RESET²

PD¹

Active High Control Input. All DACs go into power-down mode when this pin is high. The DAC outputs go into

a high impedance state.

BUSY

Active Low Output. This signal tells the user that the analog calibration loop is active. It goes low during conversion.

The duration of the pulse on BUSY determines the maximum DAC update rate, f_UPDATE. Further writes to the

AD5516 are ignored while BUSY is active.

NOTES

¹Internal pull-down device on this logic input. Therefore it can be left floating and will default to a logic low condition.

²Internal pull-up device on this logic input. Therefore it can be left floating and will default to a logic high condition.

TERMINOLOGY

DC Crosstalk

Integral Nonlinearity (INL)

This is the dc change in the output level of one DAC at midscale

in response to a full-scale code change (all 0s to all 1s and vice

versa) and output change of another DAC. It is expressed in LSB.

This is a measure of the maximum deviation from a straight line

passing through the endpoints of the DAC transfer function. It is

expressed in LSBs.

Output Settling Time

Differential Nonlinearity (DNL)

This is the time taken from when the last data bit is clocked into

the DAC until the output has settled to within ±0.5 LSB of its

final value (see TPC 7).

Differential nonlinearity (DNL) is the difference between the

measured change and the ideal 1 LSB change between any two

adjacent codes. A specified DNL of –1 LSB maximum ensures

monotonicity.

Digital-to-Analog Glitch Impulse

This is the area of the glitch injected into the analog output when

the code in the DAC register changes state. It is specified as the

area of the glitch in nV-s when the digital code is changed by

1 LSB at the major carry transition (011...11 to 100...00 or

100...00 to 011...11).

Bipolar Zero Error

Bipolar zero error is the deviation of the DAC output from the ideal

midscale of 0 V. It is measured with 10...00 loaded to the DAC.

It is expressed in LSBs.

Positive Full-Scale Error

Digital Crosstalk

This is the error in the DAC output voltage with all 1s loaded to

the DAC. Ideally the DAC output voltage, with all 1s loaded to the

DAC registers, should be 2.5 V – 1 LSB (AD5516-1), 5 V – 1 LSB

(AD5516-2), and 10 V – 1 LSB (AD5516-3). It is expressed in LSBs.

This is the glitch impulse transferred to the output of one DAC at

midscale while a full-scale code change (all 1s to all 0s and vice

versa) is being written to another DAC. It is expressed in nV-s.

Analog Crosstalk

Negative Full-Scale Error

This is the area of the glitch transferred to the output (V_OUT) of

one DAC due to a full-scale change in the output (V_OUT) of

another DAC. The area of the glitch is expressed in nV-s.

This is the error in the DAC output voltage with all 0s loaded to

the DAC. Ideally the DAC output voltage, with all 0s loaded to the

DAC registers, should be –2.5 V (AD5516-1), –5 V (AD5516-2),

and –10 V (AD5516-3). It is expressed in LSBs.

Digital Feedthrough

This is a measure of the impulse injected into the analog outputs

from the digital control inputs when the part is not being written

to, i.e., SYNC is high. It is specified in nV-s and measured with

a worst-case change on the digital input pins, e.g., from all 0s to

all 1s and vice versa.

Output Temperature Coefficient

This is a measure of the change in analog output with changes in

temperature. It is expressed in ppm/∞C of FSR.

DC Power Supply Rejection Ratio

DC power supply rejection ratio (PSRR) is a measure of the change

in analog output for a change in supply voltage (V_DDand V_SS).

It is expressed in dB. V_DDand V_SSare varied ±5%.

Output Noise Spectral Density

This is a measure of internally generated random noise. Random

noise is characterized as a spectral density (voltage per root hertz).

It is measured in nV/(Hz)^1/2

.

REV. B

–7–

AD5516–Typical Performance Characteristics

1.0

2.0

1.5

REF_IN = 3V

= 25؇C

REF_IN = 3V

= 25؇C

REF_IN = 3V

T

A

0.8

A

0.6

1.0

INL

0.4

0.5

0.2

+VE

DNL

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.5

–1.0

–1.5

–2.0

–VE

DNL

0

1000

2000

3000

4000

0

1000

2000

3000

4000

–40

–20

0

20

40

60

80

DAC CODE

TEMPERATURE (؇C)

TPC 2. Typical INL Plot

TPC 1. Typical DNL Plot

TPC 3. Typical INL Error and DNL

Error vs. Temperature

3

0.01

0.003

0.002

AV = +12V

DD

AV = +12V

DD

REF_IN = 3V

0.008

AV = –12V

SS

2

1

REF_IN = 3V

MIDSCALE LOADED

0.006

0.004

0.002

REF_IN = 3V

= 25؇C

T

A

0.001

0

BIPOLAR ZERO ERROR

0

0.0

–0.002

–0.004

–0.006

–0.008

–0.01

MIDSCALE

–1

–2

–3

–0.001

–0.002

–0.003

NEGATIVE FS ERROR

POSITIVE FS ERROR

–40

–20

0

20

40

60

80

–40

–20

0

20

40

60

80

–8 –6

–4

–2

0

2

4

6

8

CURRENT (mA)

TEMPERATURE (؇C)

TPC 5. V_OUTvs. Temperature

TPC 4. Bipolar Zero Error and

Full-Scale Error vs. Temperature

TPC 6. V_OUTSource and Sink

Capability

3.0

2.0

–0.029

–0.030

–0.031

–0.032

–0.033

T

= 25؇C

T

= 25؇C

A

T = 25؇C

A

REF_IN = 3V

A

REF_IN = 3V

NEW

VALUE

5V/DIV

2V/DIV

1.0

PD

CALIBRATIONTIME

0

V

OUT

OLD

VALUE

–1.0

–2.0

–3.0

2.5␮s/DIV

TIME BASE = 2.5␮s/DIV

2␮s/DIV

5V

0V

BUSY

TPC 7. AD5516–1 Full-Scale

Settling Time

TPC 8. Exiting Power-Down to

Full Scale

TPC 9. AD5516–1 Major Code

Transition Glitch Impulse

–8–

REV. B

AD5516

450

400

350

300

250

200

150

100

50

40

REF_IN = 3V

= 25؇C

REF_IN = 3V

= 25؇C

T

A

20

0

–10

0

–10

0

10

0

10

2.4893

2.4896

(V)

2.4899

LSBs

V

OUT

TPC 10. AD5516–1 V_OUTRepeatability;

Programming the Same Code

Multiple Times

TPC 11. Bipolar Error Distribution

TPC 12. Positive Full-Scale

Error Distribution

30

2.5

6

5

4

3

2

1

0

REF_IN = 3V

A

REF_IN = 3V

T

= 25؇C

T

= 25؇C

A

T

= 25؇C

A

2.0

1.5

1.0

0.5

0

20

10

0

–10

0

10

0

20

40

60

80

100 120 130

0

500 1000 1500 2000 2500 3000 3500 4000

CODE

LSBs

STEP SIZE

TPC 15. Accuracy vs. Increment

Step, Using All 12 Mode 2 Bits

TPC 13. Negative Full-Scale Error

Distribution

TPC 14. Accuracy vs. Increment Step

REV. B

–9–

AD5516

FUNCTIONAL DESCRIPTION

Where:

The AD5516 consists of sixteen 12-bit DACs in a single pack-

age. A single reference input pin (REF_IN) is used to provide a

3 V reference for all 16 DACs. To update a DAC’s output

voltage, the required DAC is addressed via the 3-wire serial

interface. Once the serial write is complete, the selected DAC

converts the code into an output voltage. The output amplifiers

translate the DAC output range to give the appropriate voltage

range (±2.5 V, ±5 V, or ±10 V) at output pins V_OUT0 to V_OUT15.

D = decimal equivalent of the binary code that is loaded to

the DAC register, i.e., 0–4095

N = DAC resolution = 12

Table I illustrates ideal analog output versus DAC code.

Table I. DAC Register Contents AD5516-1

MSB

LSB

Analog Output, V_OUT

The AD5516 uses a self-calibrating architecture to achieve 12-bit

performance. The calibration routine servos to select the appro-

priate voltage level on an internal 14-bit resolution DAC. BUSY

output goes low for the duration of the calibration and further

writes to the AD5516 are ignored while BUSY is low. BUSY low

time is typically 25 ms. Noise during the calibration (BUSY

low period) can result in the selection of a voltage within a

±0.25 LSB band around the normal selected voltage. See TPC 10.

1111 1111 1111

1000 0000 0000

0000 0000 0000

V_{REF_IN}¥ 2.5/3 – 1 LSB

0 V

–V_{REF_IN}¥ 2.5/3

MODES OF OPERATION

The AD5516 has two modes of operation.

Mode 1 (MODE bits = 00): The user programs a 12-bit data-

word to one of 16 channels via the serial interface. This word is

loaded into the addressed DAC register and is then converted

into an analog output voltage. During conversion, the BUSY

output is low and all SCLK pulses are ignored. At the end of a

conversion BUSY goes high, indicating that the update of the

addressed DAC is complete. It is recommended that SCLK is not

pulsed while BUSY is low. Mode 1 conversion takes 25 ms typ.

It is essential to minimize noise on REFIN for optimal perfor-

mance. The AD780’s specified decoupling makes it the ideal

reference to drive the AD5516.

Upon power-on, all DACs power up to a reset value (see the

RESET section).

DIGITAL-TO-ANALOG SECTION

The architecture of each DAC channel consists of a resistor

string DAC followed by an output buffer amplifier with offset

and gain. The voltage at the REF_IN pin provides the reference

voltage for all 16 DACs. The input coding to the DACs is offset

binary; this results in ideal output voltages as follows:

Mode 2 (MODE bits = 01 or 10): Mode 2 operation allows the

user to increment or decrement the DAC output in 0.25 LSB steps,

resulting in a 14-bit monotonic DAC. The amount by which the

DAC output is incremented or decremented is determined by

Mode 2 bits DB11–DB0, e.g., for a 0.25 LSB increment/decrement

DB11...DB0 = 0000 0000 0001, while for a 2.5 LSB increment/

decrement, DB11...DB0 = 0000 0000 1010. The MODE bits

determine whether the DAC data is incremented (01) or dec-

remented (10). The maximum amount that the user is allowed

to increment or decrement the DAC output is 4095 steps of

0.25 LSB, i.e., DB11...DB0 = 1111 1111 1111. Mode 2 update

takes approximately 1 ms. The Mode 2 feature allows increased

resolution, but overall increment/decrement accuracy varies with

increment/decrement step as shown in TPC 14 and TPC 15.

2 ¥V_{REF_IN}¥ 2.5 ¥ D V_{REF_IN}¥ 2.5

V_OUT

=

–

AD5516-1:

AD5516-2:

AD5516-3:

3 ¥ 2^N

3

4 ¥V_{REF_IN}¥ 2.5 ¥ D 2V_{REF_IN}¥ 2.5

–

3 ¥ 2^N

3

8 ¥V_{REF_IN}¥ 2.5 ¥ D 4V_{REF_IN}¥ 2.5

–

3 ¥ 2^N

3

Mode 2 is useful in applications where greater resolution is

required, for example, in servo applications requiring fine-tune

to 14-bit resolution.

MSB

LSB

0

A3

A2

A1

A0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

MODE

BITS

ADDRESS

BITS

DATA

BITS

Figure 4. Mode 1 Data Format

MSB

LSB

0

1

A3

A2

A1

A0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

MODE

BITS

ADDRESS

BITS

12 INCREMENT

BITS

MSB

LSB

1

0

A2

A1

A0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

MODE

BITS

ADDRESS

BITS

12 DECREMENT

BITS

Figure 5. Mode 2 Data Format

–10–

REV. B

AD5516

The user must allow 200 ns (min) between two consecutive

Mode 2 writes in Standalone Mode and 400 ns (min) between

two consecutive Mode 2 writes in Daisy-Chain Mode. During a

Mode 2 operation the BUSY signal remains high.

SYNC must be taken high and low again for further serial data

transfer. SYNC may be taken high after the falling edge of the

18th SCLK pulse, observing the minimum SCLK falling edge

to SYNC rising edge time, t₆. If SYNC is taken high before the

18th falling edge of SCLK, the data transfer will be aborted and

the addressed DAC will not be updated. See the timing diagram

in Figure 1.

See Figures 4 and 5 for Mode 1 and Mode 2 data formats.

When MODE bits = 11, the device is in No Operation mode.

This may be useful in daisy-chain applications where the user

does not wish to change the settings of the DACs. Simply write

11 to the MODE bits and the following address and data bits

will be ignored.

Daisy-Chain Mode (DCEN = 1)

I

n Daisy-Chain Mode, the internal gating on SCLK is disabled.

The SCLK is continuously applied to the input shift register

when SYNC is low. If more than 18 clock pulses are applied,

the data ripples out of the shift register and appears on the D_OUT

line. This data is clocked out on the rising edge of SCLK and is

valid on the falling edge. By connecting this line to the D_IN

input on the next device in the chain, a multidevice interface is

constructed. Eighteen clock pulses are required for each device

in the system. Therefore, the total number of clock cycles must

equal 18N, where N is the total number of devices in the chain.

See the timing diagram in Figure 2.

SERIAL INTERFACE

The AD5516 has a 3-wire interface that is compatible with

SPI/QSPI/MICROWIRE, and DSP interface standards. Data is

written to the device in 18-bit words. This 18-bit word consists

of two mode bits, four address bits, and 12 data bits as shown

in Figure 4.

The serial interface works with both a continuous and burst

clock. The first falling edge of SYNC resets a counter that counts

the number of serial clocks to ensure the correct number of bits

is shifted in and out of the serial shift registers. In order for

another serial transfer to take place, the counter must be reset

by the falling edge of SYNC.

When the serial transfer to all devices is complete, SYNC should

be taken high. This prevents any further data being clocked into the

input shift register. A burst clock containing the exact number of

clock cycles may be used and SYNC taken high some time later.

After the rising edge of SYNC, data is automatically transferred

from each device’s input shift register to the addressed DAC.

A3–A0

Four address bits (A3 = MSB Address, A0 = LSB). These are

used to address one of 16 DACs.

RESET Function

The RESET function on the AD5516 can be used to reset all

nodes on this device to their power-on reset condition. This is

implemented by applying a low going pulse of 20 ns minimum

to the RESET Pin on the device.

Table II. Selected DAC

A3

A2

A1

A0

Selected DAC

0

:

0

:

0

:

0

1

:

DAC 0

DAC 1

Table III. Typical Power-On Values

Device

Output Voltage

1

DAC 15

AD5516-1

AD5516-2

AD5516-3

–0.073 V

–0.183 V

–0.391 V

DB11–DB0

These are used to write a 12-bit word into the addressed DAC

register. Figures 1 and 2 show the timing diagram for a write

cycle to the AD5516.

BUSY Output

During conversion, the BUSY output is low and all SCLK pulses

are ignored. At the end of a conversion, BUSY goes high indi-

cating that the update of the addressed DAC is complete. It is

recommended that SCLK is not pulsed while BUSY is low.

SYNC FUNCTION

In both Standalone and Daisy-Chain Modes, SYNC is an edge-

triggered input that acts as a frame synchronization signal and

chip enable. Data can only be transferred into the device while

SYNC is low. To start the serial data transfer, SYNC should be

taken low observing the minimum SYNC falling to SCLK falling

edge setup time, t₃.

MICROPROCESSOR INTERFACING

The AD5516 is controlled via a versatile 3-wire serial interface

that is compatible with a number of microprocessors and DSPs.

Standalone Mode (DCEN = 0)

AD5516 to ADSP-2106x SHARC DSP Interface

The ADSP-2106x SHARC DSPs are easily interfaced to the

AD5516 without the need for extra logic.

After SYNC goes low, serial data will be shifted into the device’s

input shift register on the falling edges of SCLK for 18 clock

pulses. After the falling edge of the 18th SCLK pulse, data will

automatically be transferred from the input shift register to the

addressed DAC.

The AD5516 expects a t₃(SYNC falling edge to SCLK falling

edge setup time) of 15 ns min. Consult the ADSP-2106x User

Manual for information on clock and frame sync frequencies for

the SPORT Register and contents of the TDIV and RDIV Registers.

REV. B

–11–

AD5516

A data transfer is initiated by writing a word to the TX Register

after the SPORT has been enabled. In write sequences, data is

clocked out on each rising edge of the DSP’s serial clock and

clocked into the AD5516 on the falling edge of its SCLK. The

SPORT transmit control register should be set up as follows:

AD5516 to PIC16C6x/7x

The PIC16C6x/7x synchronous serial port (SSP) is configured

as an SPI master with the Clock Polarity Bit (CKP) = 0. This is

done by writing to the Synchronous Serial Port Control Register

(SSPCON). See the PIC16/17 Microcontroller User Manual. In this

example, I/O port RA1 is being used to provide a SYNC signal

and enable the serial port of the AD5516. This microcontroller

transfers only eight bits of data during each serial transfer opera-

tion; therefore, three consecutive write operations are required.

Figure 8 shows the connection diagram.

DTYPE

ICLK

TFSR

INTF

LTFS

LAFS

SENDN

SLEN

=

00, Right Justify Data

1, Internal Serial Clock

1, Frame Every Word

1, Internal Frame Sync

1, Active Low Frame Sync Signal

0, Early Frame Sync

0, Data Transmitted MSB First

10011, 18-Bit Data-Words (SLEN = Serial Word)

PIC16C6x/7x*

SCK/RC3

SDI/RC4

AD5516*

SCLK

Figure 6 shows the connection diagram.

D

IN

RA1

SYNC

ADSP-2106x*

AD5516*

*ADDITIONAL PINS OMITTED FOR CLARITY

TFS

SYNC

Figure 8. AD5516 to PIC16C6x/7x Interface

AD5516 to 8051

D

DT

IN

SCLK

A serial interface between the AD5516 and the 80C51/80L51

microcontroller is shown in Figure 9. The AD5516 requires a

clock synchronized to the serial data. The 8051 serial interface

must therefore be operated in Mode 0. TxD of the microcon-

troller drives the SCLK of the AD5516, while RxD drives the

serial data line. P1.1 is a bit programmable pin on the serial port

that is used to drive SYNC. The 80C51/80L51 provides the

LSB first, while the AD5516 expects MSB of the 18-bit word

first. Care should be taken to ensure the transmit routine takes

this into account.

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 6. AD5516 to ADSP-2106x Interface

AD5516 to MC68HC11

The serial peripheral interface (SPI) on the MC68HC11 is

configured for Master Mode (MSTR = 1), Clock Polarity Bit

(CPOL) = 0, and the Clock Phase Bit (CPHA) = 1. The SPI is

configured by writing to the SPI Control Register (SPCR)—see

the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK

of the AD5516, the MOSI output drives the serial data line

(D_IN) of the AD5516. The SYNC signal is derived from a port

line (PC7). When data is being transmitted to the AD5516, the

SYNC line is taken low (PC7). Data appearing on the MOSI

output is valid on the falling edge of SCK. Serial data from the

68HC11 is transmitted in 8-bit bytes with only eight falling

clock edges occurring in the transmit cycle. Data is transmitted

MSB first. In order to transmit 18 data bits, it is important to

left justify the data in the SPDR Register. PC7 must be pulled

low to start a transfer and taken high and low again before any

further read/write cycles can take place. A connection diagram is

shown in Figure 7.

8051*

AD5516*

SCLK

TxD

RxD

P1.1

D

IN

SYNC

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 9. AD5516 to 8051 Interface

When data is to be transmitted to the DAC, P1.1 is taken low.

Data on RxD is valid on the falling edge of TxD, so the clock

must be inverted as the AD5516 clocks data into the input shift

register on the rising edge of the serial clock. The 80C51/80L51

transmits its data in 8-bit bytes with only eight falling clock edges

occurring in the transmit cycle. As the DAC requires an 18-bit

word, P1.1 must be left low after the first eight bits are transferred

and brought high after the complete 18 bits have been transferred.

DOUT may be tied to RxD for data verification purposes when

the device is in Daisy-Chain Mode.

MC68HC11*

AD5516*

PC7

SYNC

SCLK

SCK

D

MOSI

IN

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 7. AD5516 to MC68HC11 Interface

–12–

REV. B

AD5516

APPLICATION CIRCUITS

so that the DAC output has enough headroom to drive the

BJT ~ 0.7 V above the maximum output voltage.

The AD5516 is suited for use in many applications, such as level

setting, optical, industrial systems, and automatic test applications.

In level setting and servo applications where a fine-tune adjust is

required, the Mode 2 function increases resolution. The following

figures show the AD5516 used in some potential applications.

V

DD

V

DD

AD5516 in a Typical ATE System

AD5516-1

The AD5516 is ideally suited for the level setting function in

automatic test equipment. A number of DACs are required to

control pin drivers, comparators, active loads, parametric mea-

surement units, and signal timing. Figure 10 shows the AD5516

in such a system.

V

DAC

0

V

OUT

R

0

FB

X

V

= –2.5V TO +2.5V

x

R

DAC

PARAMETRIC

MEASUREMENT SYSTEM BUS

UNIT

V

SS

ACTIVE

LOAD

Figure 12. AD5516 in a High Current Circuit

Note it is not intended that the R_FBnodes be used to alter

amplifier gain or for force/sense in remote sense applications.

DRIVER

DAC

STORED

DATA AND

INHIBIT

POWER SUPPLY DECOUPLING

PATTERN

FORMATTER

In any circuit where accuracy is important, careful consideration

of the power supply and ground return layout helps to ensure the

rated performance. The printed circuit board on which the AD5516

is mounted should be designed so that the analog and digital

sections are separated and confined to certain areas of the board. If

the AD5516 is in a system where multiple devices require an

AGND-to-DGND connection, the connection should be made at

one point only. The star ground point should be established as

close as possible to the device. For supplies with multiple pins

(AV_CC1, AV_CC2), it is recommended to tie those pins together. The

AD5516 should have ample supply bypassing of 10 mF in parallel

with 0.1 mF on each supply located as closely to the package as

possible, ideally right up against the device. The 10 mF capacitors

are the tantalum bead type. The 0.1 mF capacitor should have low

effective series resistance (ESR) and effective series inductance

(ESI), like the common ceramic types that provide a low impedance

path to ground at high frequencies, to handle transient currents

due to internal logic switching.

DUT

DAC

PERIOD

GENERATION

AND

DAC

DELAY

COMPARE

REGISTER

TIMING

DACs

SYSTEM BUS

COMPARATOR

Figure 10. AD5516 in an ATE System

AD5516 in an Optical Network Control Loop

The AD5516 can be used in optical network control applica-

tions that require a large number of DACs to perform a control

and measurement function. In the example shown in Figure 11,

the outputs of the AD5516 are fed into amplifiers and used to

control actuators that determine the position of MEMS mirrors

in an optical switch. The exact position of each mirror is measured

and the readings are multiplexed into an 8-channel, 14-bit ADC

(AD7865). The increment and decrement modes of the DACs are

useful in this application as they allow 14-bit resolution.

The power supply lines of the AD5516 should use as large a trace

as possible to provide low impedance paths and reduce the effects

of glitches on the power supply line. Fast switching signals such

as clocks should be shielded with digital ground to avoid radiating

noise to other parts of the board, and should never be run near

the reference inputs. A ground line routed between the D_INand

SCLK lines will help reduce crosstalk between them (not required

on a multilayer board as there will be a separate ground plane, but

separating the lines will help). It is essential to minimize noise

on REFIN.

The control loop is driven by an ADSP-2106x, a 32-bit

SHARC^®DSP.

S

E

N

S

O

R

S

0

7

MEMS

MIRROR

ARRAY

ADG609

؋

2

AD5516

AD7865

15

Avoid crossover of digital and analog signals. Traces on opposite

sides of the board should run at right angles to each other. This

reduces the effects of feedthrough through the board. A micro-

strip technique is by far the best, but not always possible with a

double-sided board. In this technique, the component side of

the board is dedicated to ground plane while signal traces are

placed on the solder side.

AD8644

؋

2

ADSP-2106x

Figure 11. AD5516 in an Optical Control Loop

AD5516 in a High Current Circuit

Access to the feedback loop of the AD5516 amplifier provides

greater flexibility, e.g., it enables the user to configure the device

as a digitally programmable current source or increase the out-

put drive current. See Figure 12. Note that V_DDmust be chosen

As is the case for all thin packages, care must be taken to avoid

flexing the package and to avoid a point load on the surface of

the package during the assembly process.

REV. B

–13–

AD5516

OUTLINE DIMENSIONS

74-Lead Chip Scale Ball Grid Array [CSPBGA]

(BC-74)

Dimensions shown in millimeters

A1 CORNER

INDEX AREA

12.00 BSC

SQ

11 10

9 8 7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

A1

1.00

BSC

10.00 BSC

SQ

BOTTOM

VIEW

TOP VIEW

K

L

1.00 BSC

1.70

DETAIL A

MAX

DETAIL A

0.30 MIN

0.20 MAX

COPLANARITY

0.70

0.60

0.50

SEATING

PLANE

BALL DIAMETER

COMPLIANT TO JEDEC STANDARDS MO-192ABD-1

–14–

REV. B

AD5516

Revision History

Location

Page

8/03—Data Sheet changed from REV. A to REV. B.

Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Changes to TPC 14 caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Addition of TPC 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Changes to Mode 2 section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Changes to Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Changes to Figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

8/02—Data Sheet changed from REV. 0 to REV. A.

Term LFBGA updated to CSPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Addition to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Changes to FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Changes to DIGITAL-TO-ANALOG section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Added AD5516 in a High Current Circuit section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Added Figure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Updated BC-74 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

REV. B

–15–

–16–


型号：	AD5516ABCZ-2
厂家：	Rochester Electronics
描述：	SERIAL INPUT LOADING, 14-BIT DAC, PBGA74, 12 X 12 MM, MO-192ABD-1, CSPBGA-74 输入元件
文件：	总17页 (文件大小：1022K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5516ABCZ-2 [ROCHESTER]

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