AD5272BCPZ-20-RL7_技术文档

1024-/256-Position, 1% Resistor Tolerance Error,

I²C Interface and 50-TP Memory Digital Rheostat

Data Sheet

AD5272/AD5274

FEATURES

FUNCTIONAL BLOCK DIAGRAM

V

DD

Single-channel, 1024-/256-position resolution

20 kΩ, 50 kΩ, 100 kΩ nominal resistance

Maximum 1ꢀ nominal resistor tolerance error

50-times programmable (50-TP) wiper memory

Rheostat mode temperature coefficient: 5 ppm/°C

2.7 V to 5.5 V single-supply operation

2.5 V to 2.75 V dual-supply operation for ac or bipolar

operations

POWER-ON

RESET

AD5272/AD5274

RDAC

REGISTER

SCL

SDA

A

2

10/8

I C

SERIAL

INTERFACE

I²C-compatible interface

W

Wiper setting readback

50-TP

MEMORY

BLOCK

ADDR

RESET

Power on refreshed from 50-TP memory

Thin LFCSP 10-lead, 3 mm × 3 mm × 0.8 mm package

Compact MSOP, 10-lead 3 mm × 4.9 mm × 1.1 mm package

V

EXT_CAP

GND

SS

APPLICATIONS

Figure 1.

Mechanical rheostat replacements

Op-amp: variable gain control

Instrumentation: gain, offset adjustment

Programmable voltage to current conversions

Programmable filters, delays, time constants

Programmable power supply

Sensor calibration

GENERAL DESCRIPTION

The AD5272/AD5274¹are single-channel, 1024-/256-position

digital rheostats that combine industry leading variable resistor

performance with nonvolatile memory (NVM) in a compact

package.

The AD5272/AD5274 device wiper settings are controllable

through the I²C-compatible digital interface. Unlimited

adjustments are allowed before programming the resistance

value into the 50-TP memory. The AD5272/AD5274 do not

require any external voltage supply to facilitate fuse blow and

there are 50 opportunities for permanent programming. During

50-TP activation, a permanent blow fuse command freezes the

wiper position (analogous to placing epoxy on a mechanical

trimmer).

The AD5272/AD5274 ensure less than 1% end-to-end resistor

tolerance error and offer 50-times programmable (50-TP) memory.

The guaranteed industry leading low resistor tolerance error

feature simplifies open-loop applications as well as precision

calibration and tolerance matching applications.

The AD5272/AD5274 are available in a 3 mm × 3 mm 10-lead

LFCSP package and in a 10-lead MSOP package. The parts are

guaranteed to operate over the extended industrial temperature

range of −40°C to +125°C.

¹Protected by U.S. Patent Number 7688240.

Rev. D

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

AD5272/AD5274

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Shift Register............................................................................... 18

Write Operation.......................................................................... 19

Read Operation........................................................................... 20

RDAC Register............................................................................ 21

50-TP Memory Block ................................................................ 21

Write Protection ......................................................................... 21

50-TP Memory Write-Acknowledge Polling.......................... 23

Reset............................................................................................. 23

Resistor Performance Mode...................................................... 23

Shutdown Mode ......................................................................... 23

RDAC Architecture.................................................................... 23

Programming the Variable Resistor......................................... 23

EXT_CAP Capacitor.................................................................. 24

Terminal Voltage Operating Range ......................................... 24

Power-Up Sequence ................................................................... 24

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 25

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics—AD5272 .......................................... 3

Electrical Characteristics—AD5274 .......................................... 5

Interface Timing Specifications.................................................. 7

Absolute Maximum Ratings............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 11

Test Circuits..................................................................................... 17

Theory of Operation ...................................................................... 18

Serial Data Interface................................................................... 18

REVISION HISTORY

3/13—Rev. C to Rev. D

3/10—Rev. 0 to Rev. A

Changed Resistor Noise Density, R_AW= 20 kΩ from 50 nV/√Hz

to 13 nV/√Hz; Table 1...................................................................... 4

Changed Resistor Noise Density, R_AW= 20 kΩ from 50 nV/√Hz

to 13 nV/√Hz; Table 4...................................................................... 6

Updated Outline Dimensions....................................................... 25

Changes to Product Title and General Description Section .......1

Changes to Theory of Operation Section.................................... 15

10/09—Revision 0: Initial Version

11/10—Rev. B to Rev. C

Changes to Figure 24...................................................................... 14

5/10—Rev. A to Rev. B

Added LFCSP Package.................................................. Throughout

Changed OTP to 50-TP................................................ Throughout

Changes to Features Section and Applications Section............... 1

Added Endnote 1.............................................................................. 1

Changes to Table 1............................................................................ 3

Added Table 3.................................................................................... 4

Changes to Table 4............................................................................ 5

Added Table 6.................................................................................... 6

Changes to Table 8 and Table 9....................................................... 9

Added Figure 5................................................................................ 10

Added Exposed Pad Note to Table 10.......................................... 10

Changes to Typical Performance Characteristics....................... 11

Changes to Resistor Performance Mode Section ....................... 23

Updated Outline Dimensions....................................................... 25

Changes to Ordering Guide .......................................................... 26

Rev. D | Page 2 of 28

Data Sheet

AD5272/AD5274

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—AD5272

V_DD= 2.7 V to 5.5 V, V _SS= 0 V; V_DD= 2.5 V to 2.75 V, V _SS= −2.5 V to −2.75 V; −40°C < T_A< +125°C, unless otherwise noted.

Table 1.

Parameter

Symbol

R-INL

Test Conditions/Comments

Min

Typ¹Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resolution

Resistor Integral Nonlinearity^{2, 3}

10

−1

Bits

LSB

R_AW= 20 kΩ, |V_DD− V_SS| = 3.0 V to 5.5 V

R_AW= 20 kΩ, |V_DD− V_SS| = 2.7 V to 3.0 V

R_AW= 50 kΩ, 100 kΩ

+1

+1.5

+1

Resistor Differential Nonlinearity²

Nominal Resistor Tolerance

R-Perf Mode⁴

R-DNL

+1

See Table 2 and Table 3

−1

0.5 +1

%

Normal Mode

15

5

35

%

Resistance Temperature Coefficient^{5, 6}

Wiper Resistance

RESISTOR TERMINALS

Terminal Voltage Range^{5, 7}

Capacitance⁵A

Code = full scale

Code = zero scale

ppm/°C

Ω

70

V_SS

V_DD

V

f = 1 MHz, measured to GND, code = half scale

V_A= V_W

90

40

pF

nA

Capacitance⁵W

Common-Mode Leakage Current⁵

50

DIGITAL INPUTS

Input Logic⁵

High

Low

Input Current

Input Capacitance⁵

DIGITAL OUTPUT

Output Voltage⁵

High

V_INH

V_INL

I_IN

2.0

V

µA

pF

0.8

1

5

C_IN

V_OH

V_OL

R_{PULL_UP}= 2.2 kΩ to V_DD

V_DD− 0.1

V

Low

V_DD= 2.7 V to 5.5 V, V_SS= 0 V

V_DD= 2.5 V to 2.75 V, V_SS= −2.5 V to −2.75 V

0.4

0.6

+1

V

µA

pF

Tristate Leakage Current

Output Capacitance⁵

POWER SUPPLIES

Single-Supply Power Range

Dual-Supply Power Range

Supply Current

Positive

−1

5

V_SS= 0 V

2.7

2.5

5.5

2.75

V

I_DD

I_SS

1

µA

Negative

50-TP Store Current^{5, 8}

−1

Positive

Negative

I_{DD_OTP_STORE}

I_{SS_OTP_STORE}

4

−4

mA

50-TP Read Current^{5, 9}

Positive

Negative

Power Dissipation¹⁰

I_{DD_OTP_READ}

I_{SS_OTP_READ}

500

5.5

µA

µW

−500

V_IH= V_DDor V_IL= GND

Rev. D | Page 3 of 28

AD5272/AD5274

Data Sheet

Parameter

Power Supply Rejection Ratio⁵

Symbol

Test Conditions/Comments

ΔV_DD/ΔV_SS= 5 V 10%

R_AW= 20 kΩ

Min

Typ¹Max

Unit

PSRR

dB

−66

−75

−78

−55

−67

−70

R_AW= 50 kΩ

R_AW= 100 kΩ

DYNAMIC CHARACTERISTICS^{5, 11}

Bandwidth

−3 dB, R_AW= 10 kΩ, Terminal W, see Figure 41

R_AW= 20 kΩ

kHz

300

120

60

R_AW= 50 kΩ

R_AW= 100 kΩ

Total Harmonic Distortion

Resistor Noise Density

V_A= 1 V rms, f = 1 kHz, code = half scale

R_AW= 20 kΩ

R_AW= 50 kΩ

R_AW= 100 kΩ

Code = half scale, T_A= 25°C, f = 10 kHz

R_AW= 20 kΩ

dB

−90

−88

−85

nV/√Hz

13

25

32

R_AW= 50 kΩ

R_AW= 100 kΩ

¹Typical specifications represent average readings at 25°C, V_DD= 5 V, and V_SS= 0 V.

²Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions.

³The maximum current in each code is defined by I_AW= (V_DD− 1)/R_AW

.

⁴The terms, resistor performance mode and R-Perf mode, are used interchangeably. See the Resistor Performance Mode section.

⁵Guaranteed by design and not subject to production test.

⁶See Figure 24 for more details.

⁷Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar

signal adjustment.

⁸Different from operating current, the supply current for the fuse program lasts approximately 55 ms.

⁹Different from operating current, the supply current for the fuse read lasts approximately 500 ns.

10

P

is calculated from (I_DD× V_DD) + (I_SS× V_SS).

DISS

¹¹All dynamic characteristics use V_DD= +2.5 V, V_SS= −2.5 V.

Table 2. AD5272 Resistor Performance Mode Code Range

Resistor Tolerance Per Code

|V_DD− V_SS| = 4.5 V to 5.5 V

|V_DD− V_SS| = 2.7 V to 4.5 V

R-TOLERANCE

1% R-Tolerance

2% R-Tolerance

3% R-Tolerance

From 0x078 to 0x3FF

From 0x037 to 0x3FF

From 0x028 to 0x3FF

From 0x0BE to 0x3FF

From 0x055 to 0x3FF

From 0x037 to 0x3FF

Table 3. AD5272 50 kΩ and 100 kΩ Resistor Performance Mode Code Range

Resistor Tolerance Per Code

R_AW= 50 kΩ

R_AW= 100 kΩ

R-TOLERANCE

1% R-Tolerance

2% R-Tolerance

3% R-Tolerance

From 0x078 to 0x3FF

From 0x055 to 0x3FF

From 0x032 to 0x3FF

From 0x04B to 0x3FF

From 0x032 to 0x3FF

From 0x019 to 0x3FF

Rev. D | Page 4 of 28

Data Sheet

AD5272/AD5274

ELECTRICAL CHARACTERISTICS—AD5274

V_DD= 2.7 V to 5.5 V, V_SS= 0 V; V_DD= 2.5 V to 2.75 V, V_SS= −2.5 V to −2.75 V; −40°C < T_A< +125°C, unless otherwise noted.

Table 4.

Parameter

Symbol

Test Conditions/Comments

Min

Typ ¹

Max

Unit

DC CHARACTERISTICS—

RHEOSTAT MODE

Resolution

8

−1

Bits

LSB

Resistor Integral Nonlinearity^{2, 3}

R-INL

R-DNL

+1

Resistor Differential

Nonlinearity²

Nominal Resistor Tolerance

R-Perf Mode⁴

Normal Mode

See Table 5 and Table 6

−1

0.5

15

+1

%

Resistance Temperature

Coefficient^{5, 6}

Wiper Resistance

RESISTOR TERMINALS

Terminal Voltage Range^{5, 7}

Capacitance⁵A

Capacitance⁵W

Common-Mode Leakage

Current⁵

Code = full scale

Code = zero scale

5

ppm/°C

35

70

Ω

V_SS

V_DD

V

f = 1 MHz, measured to GND, code = half scale

V_A= V_W

90

40

pF

nA

50

DIGITAL INPUTS

Input Logic⁵

High

V_INH

V_INL

I_IN

2.0

V

µA

pF

Low

0.8

Input Current

Input Capacitance⁵

DIGITAL OUTPUT

Output Voltage⁵

High

1

5

C_IN

V_OH

V_OL

R_{PULL_UP}= 2.2 kΩ to V_DD

V_DD− 0.1

V

Low

V_DD= 2.7 V to 5.5 V, V_SS= 0 V

V_DD= 2.5 V to 2.75 V, V_SS= −2.5 V to −2.75 V

0.4

0.6

+1

V

µA

pF

Tristate Leakage Current

Output Capacitance⁵

POWER SUPPLIES

Single-Supply Power Range

Dual-Supply Power Range

Supply Current

Positive

−1

5

V_SS= 0 V

2.7

2.5

5.5

2.75

V

I_DD

I_SS

1

µA

Negative

OTP Store Current^{5, 8}

−1

Positive

Negative

I_{DD_OTP_STORE}

I_{SS_OTP_STORE}

4

−4

mA

OTP Read Current^{5, 9}

Positive

Negative

Power Dissipation¹⁰

I_{DD_OTP_READ}

I_{SS_OTP_READ}

500

5.5

µA

µW

dB

−500

V_IH= V_DDor V_IL= GND

ΔV_DD/ΔV_SS= 5 V 10%

R_AW= 20 kΩ

Power Supply Rejection Ratio⁵PSRR

−66

−75

−78

−55

−67

−70

R_AW= 50 kΩ

R_AW= 100 kΩ

Rev. D | Page 5 of 28

AD5272/AD5274

Data Sheet

Parameter

Symbol

Test Conditions/Comments

Min

Typ ¹

Max

Unit

DYNAMIC CHARACTERISTICS^{5, 11}

Bandwidth

−3 dB, R_AW= 10 kΩ, Terminal W, see Figure 41

kHz

R_AW= 20 kΩ

R_AW= 50 kΩ

R_AW= 100 kΩ

300

120

60

Total Harmonic Distortion

Resistor Noise Density

V_A= 1 V rms, f = 1 kHz, code = half scale

R_AW= 20 kΩ

R_AW= 50 kΩ

R_AW= 100 kΩ

Code = half scale, T_A= 25°C, f = 10 kHz

R_AW= 20 kΩ

dB

−90

−88

−85

nV/√Hz

13

25

32

R_AW= 50 kΩ

R_AW= 100 kΩ

¹Typical specifications represent average readings at 25°C, V_DD= 5 V, and V_SS= 0 V.

²Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions.

³The maximum current in each code is defined by IAW = (V_DD− 1)/R_AW

.

⁴The terms, resistor performance mode and R-Perf mode, are used interchangeably. See the Resistor Performance Mode section.

⁵Guaranteed by design and not subject to production test.

⁶See Figure 24 for more details.

⁷Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar

signal adjustment.

⁸Different from operating current, the supply current for the fuse program lasts approximately 55 ms.

⁹Different from operating current, the supply current for the fuse read lasts approximately 500 ns.

10

P

is calculated from (I_DD× V_DD) + (I_SS× V_SS).

DISS

¹¹All dynamic characteristics use V_DD= +2.5 V, V_SS= −2.5 V.

Table 5. AD5274 Resistor Performance Mode Code Range

Resistor Tolerance per Code

|V_DD− V_SS| = 4.5 V to 5.5 V

|V_DD− V_SS| = 2.7 V to 4.5 V

R-TOLERANCE

1% R-Tolerance

2% R-Tolerance

3% R-Tolerance

From 0x1E to 0xFF

From 0x0F to 0xFF

From 0x06 to 0xFF

From 0x32 to 0xFF

From 0x19 to 0xFF

From 0x0E to 0xFF

Table 6. AD5274 50 kΩ and 100 kΩ Resistor Performance Mode Code Range

Resistor Tolerance per Code

R_AW= 50 kΩ

R_AW= 100 kΩ

R-TOLERANCE

1% R-Tolerance

2% R-Tolerance

3% R-Tolerance

From 0x1E to 0xFF

From 0x14 to 0xFF

From 0x0A to 0xFF

From 0x14 to 0xFF

From 0x0F to 0xFF

From 0x0A to 0xFF

Rev. D | Page 6 of 28

Data Sheet

AD5272/AD5274

INTERFACE TIMING SPECIFICATIONS

V_DD= 2.5 V to 5.5 V; all specifications T_MINto T_MAX, unless otherwise noted.

Table 7.

Limit at T_MIN, T_MAX

Parameter

Conditions¹

Standard mode

Fast mode

Min

Max

100

400

Unit

kHz

µs

ns

µs

ns

µs

ns

Description

2

f_SCL

Serial clock frequency

t_HIGH, SCL high time

t_LOW, SCL low time

t₁

t₂

t₃

t₄

t₅

t₆

Standard mode

Fast mode

Standard mode

Fast mode

Standard mode

Fast mode

Standard mode

Fast mode

Standard mode

Fast mode

Standard mode

Fast mode

High speed mode

Standard mode

Fast mode

Standard mode

Fast mode

Standard mode

Fast mode

Standard mode

Fast mode

Standard mode

Fast mode

Standard mode

4

0.6

4.7

1.3

250

100

0

t_LOW, SCL low time

t_SU;DAT, data setup time

t_HD;DAT, data hold time

3.45

0.9

0

4.7

0.6

4

0.6

160

4.7

1.3

4

t_SU;STA, set-up time for a repeated start condition

t_HD;STA, hold time (repeated) start condition

t_BUF, bus free time between a stop and a start condition

t_SU;STO, setup time for a stop condition

t_RDA, rise time of SDA signal

t_FDA, fall time of SDA signal

t_RCL, rise time of SCL signal

t_RCL1, rise time of SCL signal after a repeated start condition and

after an acknowledge bit

t₇

t₈

0.6

t₉

1000

300

1000

300

t₁₀

t₁₁

t_11A

1000

Fast mode

300

ns

t_RCL1, rise time of SCL signal after a repeated start condition and

after an acknowledge bit

t₁₂

t₁₃

Standard mode

Fast mode

RESET pulse time

Fast mode

300

ns

µs

ns

µs

ms

µs

ms

t_FCL, fall time of SCL signal

Minimum RESET low time

20

0

500

3

t_SP

t_EXEC

50

Pulse width of spike suppressed

Command execute time

RDAC register write command execute time (R-Perf mode)

RDAC register write command execute time (normal mode)

Memory readback execute time

Memory program time

4, 5

t_{RDAC_R-PERF}

t_{RDAC_NORMAL}

t_{MEMORY_READ}

t_{MEMORY_PROGRAM}

t_RESET

2

600

6

350

600

2

Reset 50-TP restore time

Power-on 50-TP restore time

6

t_POWER-UP

¹Maximum bus capacitance is limited to 400 pF.

²The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior

of the part.

³Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode.

⁴Refer to t_{RDAC_R-PERF}and t_{RDAC_NORMAL}for RDAC register write operations.

⁵Refer to t

t

_{MEMORY_READ}and

for memory commands operations.

MEMORY_PROGRAM

⁶Maximum time after V_DD− V_SSis equal to 2.5 V.

Rev. D | Page 7 of 28

AD5272/AD5274

Data Sheet

Shift Register and Timing Diagrams

DB9 (MSB)

DB0 (LSB)

D0

D1

C3

C1

C0

D9

D7

D6

D5

D4

D3

D8

0

C2

D2

DATA BITS

CONTROL BITS

Figure 2. Shift Register Content

t₁₂

t₁₁

t₆

t₈

t₂

SCL

SDA

t₅

t₁

t₆

t₁₀

t₉

t₄

t₃

t₇

P

S

P

t₁₃

RESET

Figure 3. 2-Wire Serial Interface Timing Diagram

Rev. D | Page 8 of 28

Data Sheet

AD5272/AD5274

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or

any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 8.

Parameter

Rating

V_DDto GND

V_SSto GND

V_DDto V_SS

–0.3 V to +7.0 V

+0.3 V to −7.0 V

7 V

V_A, V_Wto GND

V_SS− 0.3 V, V_DD+ 0.3 V

−0.3 V to V_DD+ 0.3 V

7 V

THERMAL RESISTANCE

Digital Input and Output Voltage to GND

EXT_CAP to V_SS

I_A, I_W

θ_JAis defined by JEDEC specification JESD-51 and the value is

dependent on the test board and test environment.

Continuous

Table 9. Thermal Resistance

R_AW= 20 kΩ

R_AW= 50 kΩ, 100 kΩ

Pulsed¹

Frequency > 10 kHz

Frequency ≤ 10 kHz

Operating Temperature Range⁴

Maximum Junction Temperature

(T_JMaximum)

3 mA

2 mA

1

Package Type

10-Lead LFCSP

10-Lead MSOP

θ_JA

50

θ_JC

3

N/A

Unit

°C/W

MCC²/d³

MCC²/√d³

−40°C to +125°C

150°C

135

¹JEDEC 2S2P test board, still air (0 m/s air flow).

ESD CAUTION

Storage Temperature Range

Reflow Soldering

−65°C to +150°C

Peak Temperature

260°C

Time at Peak Temperature

Package Power Dissipation

20 sec to 40 sec

(T_Jmax − T_A)/θ_JA

¹Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum

applied voltage across any two of the A and W terminals at a given

resistance.

²Maximum continuous current

³Pulse duty factor.

⁴Includes programming of 50-TP memory.

Rev. D | Page 9 of 28

AD5272/AD5274

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

10

9

V

1

2

3

4

5

ADDR

DD

A

SCL

AD5272/

AD5274

8

SDA

W

(EXPOSED

PAD)

V

7

RESET

GND

SS

V

1

2

3

4

5

10 ADDR

DD

A

AD5272/

AD5274

TOP VIEW

(Not to Scale)

9

8

7

6

SCL

6

EXT_CAP

W

SDA

V

SS

EXT_CAP

RESET

GND

NOTES

1. THE EXPOSED PAD IS LEFT FLOATING

OR IS TIED TO V

.

SS

Figure 4. MSOP Pin Configuration

Figure 5. LFCSP Pin Configuration

Table 10. Pin Function Descriptions

Pin No. Mnemonic Description

1

2

3

4

V_DD

A

W

Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors.

Terminal A of RDAC. V_SS≤ V_A≤ V_DD.

Wiper terminal of RDAC. V_SS≤ V_W≤ V_DD.

Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 ꢀF ceramic capacitors

and 10 ꢀF capacitors.

V_SS

5

EXT_CAP

External Capacitor. Connect a 1 μF capacitor between EXT_CAP and V_SS. This capacitor must have a voltage

rating of ≥7 V.

6

7

GND

RESET

Ground Pin, Logic Ground Reference.

Hardware Reset Pin. Refreshes the RDAC register with the contents of the 50-TP memory register. Factory

default loads midscale until the first 50-TP wiper memory location is programmed. RESET is active low. Tie RESET

to V_DDif not used.

8

SDA

Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input registers. It is

a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor.

9

10

EPAD

SCL

ADDR

Exposed Pad

(LFCSP Only)

Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input registers.

Tristate Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 11).

Leave floating or tie to V_SS.

Rev. D | Page 10 of 28

Data Sheet

AD5272/AD5274

TYPICAL PERFORMANCE CHARACTERISTICS

0.8

0.6

0.4

0.2

+125°C

R

= 20kΩ

T

= 25°C

AW

A

20kΩ

50kΩ

100kΩ

+25°C

–40°C

0.6

0.4

0.2

0

–0.2

–0.4

0

–0.2

–0.4

0

256

512

768

1023

0

128

256

384

512

640

768

896

1023

CODE (Decimal)

Figure 6. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5272)

Figure 9. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5272)

0.6

0.2

T

= 25°C

A

R

= 20kΩ

AW

0.1

0

0.4

0.2

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.2

–0.4

–0.6

–40°C

256

+25°C

512

+125°C

768

20kΩ

50kΩ

100kΩ

0

128

384

640

896

1023

0

256

512

CODE (Decimal)

768

1023

CODE (Decimal)

Figure 7. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5272)

Figure 10. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5272)

0.5

0.6

+125°C

+25°C

–40°C

20kΩ

50kΩ

100kΩ

T

= 25°C

A

R

= 20kΩ

AW

0.4

0.3

0.2

0.4

0.2

0

–0.2

–0.4

0.1

0

–0.1

0

256

512

768

1023

0

128

256

384

512

640

768

896

1023

CODE (Decimal)

Figure 8. R-INL in Normal Mode vs. Code vs. Temperature (AD5272)

Figure 11. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5272)

Rev. D | Page 11 of 28

AD5272/AD5274

Data Sheet

0.15

0.10

+125°C

+25°C

–40°C

T

= 25°C

20kΩ

50kΩ

100kΩ

R

= 20kΩ

A

AW

0.10

0.05

0

0.05

0

–0.05

–0.10

–0.15

–0.20

–0.15

0

256

512

768

1023

0

128

256

384

512

640

768

896

1023

CODE (Decimal)

Figure 12. R-DNL in Normal Mode vs. Code vs. Temperature (AD5272)

Figure 15. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5272)

0.15

0.20

+125°C

+25°C

–40°C

T

= 25°C

20kΩ

A

R

= 20kΩ

AW

100kΩ

0.15

0.10

0.05

0.10

0.05

0

–0.05

–0.10

–0.05

–0.10

0

64

128

192

255

0

64

128

192

255

CODE (Decimal)

Figure 16. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5274)

Figure 13. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5274)

0.15

0.06

+125°C

+25°C

–40°C

R

= 20kΩ

T

= 25°C

AW

A

0.04

0.02

0.10

0.05

0

–0.02

–0.04

–0.06

–0.08

–0.10

–0.12

0

–0.05

–0.10

–0.15

20kΩ

100kΩ

–0.14

0

64

128

CODE (Decimal)

192

255

0

64

128

192

255

CODE (Decimal)

Figure 17. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5274)

Figure 14. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5274)

Rev. D | Page 12 of 28

Data Sheet

AD5272/AD5274

0.10

0.15

0.10

0.05

0

+125°C

+25°C

–40°C

20kΩ

100kΩ

T

= 25°C

R

= 20kΩ

A

AW

0.08

0.06

0.04

0.02

0

–0.05

–0.10

–0.02

0

64

128

192

255

0

64

128

192

255

CODE (Decimal)

Figure 18. R-INL in Normal Mode vs. Code vs. Temperature (AD5274)

Figure 21. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5274)

0.03

0.010

+125°C

+25°C

–40°C

T

= 25°C

R

= 20kΩ

A

100kΩ

20kΩ

AW

0.02

0.01

0

0.008

0.006

0.004

0.002

0

–0.01

–0.02

–0.002

–0.03

0

64

128

192

255

0

64

128

192

255

CODE (Decimal)

Figure 19. R-DNL in Normal Mode vs. Code vs. Temperature (AD5274)

Figure 22. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5274)

0.7

500

400

0.6

0.5

0.4

0.3

I

= 5V

DD

300

200

I

= 3V

DD

100

I

= 3V

0

SS

–100

–200

–300

–400

–500

0.2

0.1

0

= 5V

SS

–0.1

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

(V)

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90 100 110

TEMPERATURE (°C)

V

LOGIC

Figure 20. Supply Current (I_DD, I_SS) vs. Temperature

Figure 23. Supply Current (I_DD) vs. Digital Input Voltage

Rev. D | Page 13 of 28

AD5272/AD5274

Data Sheet

7

6

5

4

3

2

50

45

40

35

30

25

20

15

10

5

V

/V = 5V/0V

DD SS

V

/V = 5V/0V

DD SS

20kΩ

50kΩ

100kΩ

20kΩ

50kΩ

100kΩ

1

0

256

64

512

128

768

192

1023 AD5272

255 AD5274

0

256

64

512

128

768

192

1023 AD5272

255 AD5274

CODE (Decimal)

Figure 24. Tempco ΔR_WA/ΔT vs. Code

Figure 27. Theoretical Maximum Current vs. Code

0

AD5272 (AD5274)

0x200 (0x80)

0x100 (0x40)

0x080 (0x20)

0x040 (0x10)

0x020 (0x08)

0x010 (0x04)

0x008 (0x02)

0x004 (0x01)

0x200 (0x80)

–10

–20

–10 0x100 (0x40)

0x080 (0x20)

–20

0x040 (0x10)

–30

–40

–50

–60

–70

0x020 (0x08)

–30

0x010 (0x04)

0x008 (0x02)

–40

0x004 (0x01)

0x002

0x001

0x002

–50

0x001

–60

1k

10k

100k

1M

10M

10k

100k

1M

10M

1k

FREQUENCY (Hz)

Figure 25. 20 kΩ Gain vs. Code vs. Frequency

Figure 28. 100 kΩ Gain vs. Code vs. Frequency

0

–10

–20

–30

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

V

/V = 5V/0V

AD5272 (AD5274)

DD SS

0x200 (0x80)

CODE = HALF SCALE

0x100 (0x40)

0x080 (0x20)

0x040 (0x10)

0x020 (0x08)

0x010 (0x04)

50kΩ

100kΩ

20kΩ

0x008 (0x02)

0x004 (0x01)

–40

–50

–60

0x002

0x001

100

1k

10k

FREQUENCY (Hz)

100k

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 26. 50 kΩ Gain vs. Code vs. Frequency

Figure 29. PSRR vs. Frequency

Rev. D | Page 14 of 28

Data Sheet

AD5272/AD5274

0

–10

–20

V

/V = 5V/0V

DD SS

20kΩ

50kΩ

100kΩ

V

/V = 5V/0V

DD SS

CODE = HALF SCALE

NOISE BW = 22kHz

V

CODE = HALF SCALE

f_IN= 1kHz

= 1V rms

IN

NOISE BW = 22kHz

–20

–40

–60

20kΩ

50kΩ

100kΩ

–30

–40

–50

–60

–70

–80

–90

–100

0.001

100

1k

10k

0.01

0.1

)

1

100k

VOLTAGE (V

FREQUENCY (Hz)

RMS

Figure 30. THD + N vs. Frequency

Figure 33. THD + N vs. Amplitude

0.03

0.02

0.01

0

0.0010

0.0005

0

V

/V = 5V/0V

DD SS

= 200µA

20kΩ

50kΩ

100kΩ

I

AW

CODE = HALF SCALE

–0.01

–0.0005

–0.0010

–0.0015

–0.02

–0.03

–0.04

–1

4

9

14

19

–10

0

10

20

30

40

50

60

TIME (µs)

Figure 31. Maximum Glitch Energy

Figure 34. Digital Feedthrough

70

60

50

40

30

20

10

0

45

40

11.25

10.00

8.75

15.5

T

= 25°C

A

V

/V = 5V/0V

DD SS

20kΩ

50kΩ

100kΩ

20kΩ

50kΩ

100kΩ

15.0

12.5

10.0

7.5

5.0

2.5

0

35

30

7.50

6.25

25

20

5.00

3.75

2.50

15

10

1.25

0

5

0

–40

–20

0

20

40

60

80

100

120

2.7

3.2

3.7

4.2

(V)

4.7

5.2

V

TEMPERATURE (°C)

DD

Figure 35. Maximum Code Loss vs. Power Supply Range

Figure 32. Maximum Code Loss vs. Temperature

Rev. D | Page 15 of 28

AD5272/AD5274

Data Sheet

8

0.006

0.005

0.004

0.003

0.002

0.001

0

V

/V = 5V/0V

DD SS

= 10µA

I

AW

CODE = HALF SCALE

7

6

5

4

–0.001

–0.002

0

100 200 300 400 500 600 700 800 900 1000

OPERATION AT 150°C (Hours)

0.07

0.09

0.11

0.13

0.15

0.17

TIME (Seconds)

Figure 36. V_{EXT_CAP}Waveform While Writing Fuse

Figure 37. Long-Term Drift Accelerated Average by Burn-In

Rev. D | Page 16 of 28

Data Sheet

AD5272/AD5274

TEST CIRCUITS

Figure 38 to Figure 42 define the test conditions used in the Specifications section.

DUT

I

W

1GΩ

W

A

V

MS

Figure 41. Gain vs. Frequency

Figure 38. Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

DUT

GND

V

I

MS

R

=

WA

I

CM

W

+2.75V

–2.75V

W

CODE = 0x00

DUT

A

R

WA

2

I

W

R

W

A

W

V

NC

GND

–2.75V

MS

NC = NO CONNECT

+2.75V

Figure 39. Wiper Resistance

Figure 42. Common Leakage Current

V+ = V ±10%

DD

V

MS

PSRR (dB) = 20 log

DD

ΔV

%

MS

DD

I

W

PSS (%/%) =

V

DD

W

V+

A

V

MS

Figure 40. Power Supply Sensitivity (PSS, PSRR)

Rev. D | Page 17 of 28

AD5272/AD5274

Data Sheet

THEORY OF OPERATION

The AD5272 and AD5274 digital rheostats are designed to

operate as true variable resistors for analog signals within the

terminal voltage range of V_SS< V_TERM< V_DD. The RDAC register

contents determine the resistor wiper position. The RDAC

register acts as a scratchpad register, which allows unlimited

changes of resistance settings. The RDAC register can be

programmed with any position setting using the I²C interface.

When a desirable wiper position is found, this value can be

stored in a 50-TP memory register. Thereafter, the wiper

position is always restored to that position for subsequent

power-up. The storing of 50-TP data takes approximately

350 ms; during this time, the AD5272/AD5274 is locked and

does not acknowledge any new command thereby preventing

any changes from taking place. The acknowledge bit can be

polled to verify that the fuse program command is complete.

The 2-wire serial bus protocol operates as follows: The master

initiates a data transfer by establishing a start condition, which

is when a high-to-low transition on the SDA line occurs while

SCL is high. The next byte is the address byte, which consists

W

of the 7-bit slave address and a R/ bit. The slave device cor-

responding to the transmitted address responds by pulling

SDA low during the ninth clock pulse (this is termed the

acknowledge bit). At this stage, all other devices on the bus

remain idle while the selected device waits for data to be

written to, or read from, its shift register.

Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge bit).

The transitions on the SDA line must occur during the low

period of SCL and remain stable during the high period of SCL.

When all data bits have been read or written, a stop condition is

established. In write mode, the master pulls the SDA line high

during the 10th clock pulse to establish a stop condition. In read

mode, the master issues a no acknowledge for the ninth clock

pulse (that is, the SDA line remains high). The master then

brings the SDA line low before the 10th clock pulse, and then

high during the 10th clock pulse to establish a stop condition.

The AD5272/AD5274 also feature a patented 1% end-to-end

resistor tolerance. This simplifies precision, rheostat mode, and

open-loop applications where knowledge of absolute resistance

is critical.

SERIAL DATA INTERFACE

The AD5272/AD5274 have 2-wire I²C-compatible serial inter-

faces. Each of these devices can be connected to an I²C bus as

a slave device under the control of a master device; see Figure 3

for a timing diagram of a typical write sequence.

SHIFT REGISTER

For the AD5272/AD5274, the shift register is 16 bits wide, as

shown in Figure 2. The 16-bit word consists of two unused bits,

which should be set to zero, followed by four control bits and

10 RDAC data bits (note that for the AD5274 only, the lower

two RDAC data bits are don’t care if the RDAC register is read

from or written to), and data is loaded MSB first (Bit 15). The

four control bits determine the function of the software command

(Table 12). Figure 43 shows a timing diagram of a typical

AD5272/AD5274 write sequence.

The AD5272/AD5274 support standard (100 kHz) and fast

(400 kHz) data transfer modes. Support is not provided for

10-bit addressing and general call addressing.

The AD5272/AD5274 each has a 7-bit slave address. The five

MSBs are 01011 and the two LSBs are determined by the state

of the ADDR pin. The facility to make hardwired changes to

ADDR allows the user to incorporate up to three of these

devices on one bus as outlined in Table 11.

The command bits (Cx) control the operation of the digital

potentiometer and the internal 50-TP memory. The data bits

(Dx) are the values that are loaded into the decoded register.

Table 11. Device Address Selection

ADDR

A1

1

A0

1

7-Bit I²C Device Address

0101111

GND

V_DD

0

1

0

0101100

0101110

NC (No Connection)¹

¹Not available in bipolar mode. V_SS< 0 V.

Rev. D | Page 18 of 28

Data Sheet

AD5272/AD5274

Two bytes of data are then written to the RDAC, the most

WRITE OPERATION

significant byte followed by the least significant byte; both of

these data bytes are acknowledged by the AD5272/AD5274. A

stop condition follows. The write operations for the AD5272/

AD5274 are shown in Figure 43.

It is possible to write data for the RDAC register or the control

register. When writing to the AD5272/AD5274, the user must

W

begin with a start command followed by an address byte (R/

= 0), after which the AD5272/AD5274 acknowledges that it is

prepared to receive data by pulling SDA low.

A repeated write function gives the user flexibility to update the

device a number of times after addressing the part only once, as

shown in Figure 44.

1

9

1

9

SCL

1

0

1

A1

A0

R/W

0

C3

C2

D9

D8

SDA

START BY

C1

C0

ACK. BY

AD5272/AD5274

ACK. BY

AD5272/AD5274

MASTER

FRAME 2

FRAME 1

MOST SIGNIFICANT DATA BYTE

SERIAL BUS ADDRESS BYTE

9

1

9

SCL (CONTINUED)

SDA (CONTINUED)

D7

D6

D5

D4

D3

D2

D1

D0

ACK. BY

STOP BY

AD5272/AD5274 MASTER

FRAME 3

LEAST SIGNIFICANT DATA BYTE

Figure 43. Write Command

1

9

1

9

SCL

SDA

1

0

1

A1

A0

R/W

ACK.

0

C3

C2

C1

C0

D9

D8

ACK.

START BY

MASTER

BY

AD5272/AD5274

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

MOST SIGNIFICANT DATA BYTE

9

1

9

SCL (CONTINUED)

SDA (CONTINUED)

D7

D6

D5

D4

D3

D2

D1

D0

ACK.

BY

AD5272/AD5274

FRAME 3

LEAST SIGNIFICANT DATA BYTE

9

1

0

9

SCL (CONTINUED)

SDA (CONTINUED)

0

C3

C2

C1

C0

D9

D8

ACK.

BY

AD5272/AD5274

FRAME 4

MOST SIGNIFICANT DATA BYTE

9

1

9

(CONTINUED)

SCL

SDA

D7

D6

D5

D4

D3

D2

D1

D0

ACK.

STOP BY

MASTER

BY

AD5272/AD5274

FRAME 5

LEAST SIGNIFICANT DATA BYTE

Figure 44. Multiple Write

Rev. D | Page 19 of 28

AD5272/AD5274

Data Sheet

A stop condition follows. These bytes contain the read instruc-

tion, which enables readback of the RDAC register, 50-TP

memory, or the control register. The user can then read back

the data beginning with a start command followed by an

READ OPERATION

When reading data back from the AD5272/AD5274, the user

must first issue a readback command to the device, this begins

with a start command followed by an address byte (R/ = 0),

after which the AD5272/AD5274 acknowledges that it is

prepared to receive data by pulling SDA low.

W

address byte (R/ = 1), after which the device acknowledges

that it is prepared to transmit data by pulling SDA low. Two

bytes of data are then read from the device, as shown in Figure 45.

A stop condition follows. If the master does not acknowledge

the first byte, the second byte is not transmitted by the

AD5272/AD5274.

Two bytes of data are then written to the AD5272/AD5274, the

most significant byte followed by the least significant byte; both

of these data bytes are acknowledged by the AD5272/AD5274.

1

9

1

0

9

SCL

1

SDA

START BY

0

1

A1

A0

R/W

ACK. BY

0

C3

C2

C1

C0

D9

D8

ACK. BY

AD5272/AD5274

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

MOST SIGNIFICANT DATA BYTE

9

1

9

SCL (CONTINUED)

SDA (CONTINUED)

D7

D6

D5

D4

D3

D2

D1

D0

ACK. BY

STOP BY

AD5272/AD5274 MASTER

FRAME 3

LEAST SIGNIFICANT DATA BYTE

1

9

1

9

SCL

SDA

START BY

1

0

1

A1

A0

R/W

0

X

D9

D8

ACK. BY

AD5272/AD5274

ACK. BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

MOST SIGNIFICANT DATA BYTE

9

1

9

SCL (CONTINUED)

SDA (CONTINUED)

D7

D6

D5

D4

D3

D2

D1

D0

NO ACK. BY STOP BY

MASTER MASTER

FRAME 3

LEAST SIGNIFICANT DATA BYTE

Figure 45. Read Command

Rev. D | Page 20 of 28

Data Sheet

AD5272/AD5274

Prior to 50-TP activation, the AD5272/AD5274 is preset to

midscale on power-up. It is possible to read back the contents

of any of the 50-TP memory registers through the I²C interface

by using Command 5 in Table 12. The lower six LSB bits, D0 to

D5 of the data byte, select which memory location is to be read

back. A binary encoded version address of the most recently

programmed wiper memory location can be read back using

Command 6 in Table 12. This can be used to monitor the spare

memory status of the 50-TP memory block.

RDAC REGISTER

The RDAC register directly controls the position of the digital

rheostat wiper. For example, when the RDAC register is loaded

with all zeros, the wiper is connected to Terminal A of the

variable resistor. It is possible to both write to and read from

the RDAC register using the I²C interface. The RDAC register

is a standard logic register; there is no restriction on the number

of changes allowed.

50-TP MEMORY BLOCK

WRITE PROTECTION

The AD5272/AD5274 contain an array of 50-TP programmable

memory registers, which allow the wiper position to be pro-

grammed up to 50 times. Table 16 shows the memory map.

Command 3 in Table 12 programs the contents of the RDAC

register to memory. The first address to be programmed is

Location 0x01, see Table 16, and the AD5272/AD5274 incre-

ments the 50-TP memory address for each subsequent program

until the memory is full. Programming data to 50-TP consumes

approximately 4 mA for 55 ms, and takes approximately 350 ms

to complete, during which time the shift register is locked pre-

venting any changes from taking place. Bit C3 of the control

register in Table 15 can be polled to verify that the fuse program

command was successful. No change in supply voltage is required

to program the 50-TP memory; however, a 1 µF capacitor on

the EXT_CAP pin is required as shown in Figure 47.

On power-up, serial data input register write commands for

both the RDAC register and the 50-TP memory registers are

disabled. The RDAC write protect bit (Bit C1) of the control

register (see Table 14 and Table 15) is set to 0 by default. This

disables any change of the RDAC register content regardless of

the software commands, except that the RDAC register can be

refreshed from the 50-TP memory using the software reset,

RESET

Command 4, or through hardware by the

pin. To enable

programming of the variable resistor wiper position (programming

the RDAC register), the write protect bit (Bit C1) of the control

register must first be programmed. This is accomplished by

loading the serial data input register with Command 7 (see

Table 12). To enable programming of the 50-TP memory block,

Bit C0 of the control register, which is set to 0 by default, must

first be set to 1.

Table 12. Command Operation Truth Table

Command[DB13:DB10]

Data[DB9:B0]¹

D9 D8 D7 D6 D5 D4 D3 D2

Command

Number

C3

0

C2

0

C1

0

C0

0

D1 D0 Operation

NOP: do nothing.

0

1

X

0

1

D9 D8 D7 D6 D5 D4 D3 D2

D1²D0²Write contents of serial register

data to RDAC.

2

3

4

0

1

0

1

0

X

Read contents of RDAC wiper

register.

Store wiper setting: store RDAC

setting to 50-T P.

Software reset: refresh RDAC

with the last 50-TP memory

stored value.

5³

6

0

1

0

1

0

1

X

D5 D4 D3 D2

D1

X

D0 Read contents of 50-TP from the

SDO output in the next frame.

X

Read address of the last 50-TP

programmed memory location.

7⁴

D2

D1

D0 Write contents of the serial

register data to the control

register.

8

9

1

0

1

X

Read contents of the control

register.

D0 Software shutdown.

D0 = 0; normal mode.

D0 = 1; shutdown mode.

¹X = don’t care.

²AD5274 = don’t care.

³See Table 16 for the 50-TP memory map.

⁴See Table 15 for bit details.

Rev. D | Page 21 of 28

AD5272/AD5274

Data Sheet

Table 13. Write and Read to RDAC and 50-TP memory

DIN

SDO¹

Action

0x1C03 0xXXXX Enable update of wiper position and 50-TP memory contents through digital interface.

0x0500 0x1C03 Write 0x100 to the RDAC register, wiper moves to ¼ full-scale position.

0x0800 0x0500 Prepare data read from RDAC register.

0x0C00 0x100

Stores RDAC register content into 50-TP memory. 16-bit word appears out of SDO, where last 10-bits contain the

contents of the RDAC Register 0x100.

0x1800 0x0C00 Prepare data read of last programmed 50-TP memory monitor location.

0x0000 0xXX19 NOP Instruction 0 sends a 16-bit word out of SDO, where the six LSBs last 6-bits contain the binary address of the last

programmed 50-TP memory location, for example, 0x19 (see Table 16).

0x1419 0x0000 Prepares data read from Memory Location 0x19.

0x2000 0x0100 Prepare data read from the control register. Sends a 16-bit word out of SDO, where the last 10-bits contain the contents

of Memory Location 0x19.

0x0000 0xXXXX NOP Instruction 0 sends a 16-bit word out of SDO, where the last four bits contain the contents of the control register.

If Bit C3 = 1, fuse program command successful.

¹X is don’t care.

Table 14. Control Register Bit Map

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

C3

C2

C1

C0

Table 15. Control Register Description

Bit Name

Description

C0

50-TP program enable

0 = 50-TP program disabled (default)

1 = enable device for 50-TP program

RDAC register write protect

0 = wiper position frozen to value in 50-TP memory (default)¹

1 = allow update of wiper position through a digital interface

Resistor performance enable

0 = RDAC resistor tolerance calibration enabled (default)

1 = RDAC resistor tolerance calibration disabled

50-TP memory program success bit

C1

C2

C3

0 = fuse program command unsuccessful (default)

1 = fuse program command successful

¹Wiper position is frozen to the last value programmed in the 50-TP memory. Wiper freezes to midscale if 50-TP memory has not been previously programmed.

Table 16. Memory Map

Data Byte [DB9:DB8]¹

Command Number

D9

X

D8

X

D7

X

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

Register Contents

5

Reserved

X

0

1

1st programmed wiper location (0x01)

2nd programmed wiper location (0x02)

3rd programmed wiper location (0x03)

4th programmed wiper location (0x04)

…

X

0

1

0

X

0

1

X

0

1

0

…

X

…

X

…

X

…

0

…

0

…

0

…

1

…

0

…

1

…

0

10th programmed wiper location (0xA)

20th programmed wiper location (0x14)

30th programmed wiper location (0x1E)

40th programmed wiper location (0x28)

50th programmed wiper location (0x32)

X

0

1

0

1

0

X

0

1

0

X

0

1

0

1

0

X

0

1

0

1

0

¹X is don’t care.

Rev. D | Page 22 of 28

Data Sheet

AD5272/AD5274

A

50-TP MEMORY WRITE-ACKNOWLEDGE POLLING

After each write operation to the 50-TP registers, an internal

write cycle begins. The I²C interface of the device is disabled.

To determine if the internal write cycle is complete and the

I²C interface is enabled, interface polling can be executed. I²C

interface polling can be conducted by sending a start condition,

followed by the slave address and the write bit. If the I²C interface

responds with an acknowledge (ACK), the write cycle is complete

and the interface is ready to proceed with further operations.

Otherwise, I²C interface polling can be repeated until it completes.

R

L

R

M

L

S

W

R

M

10-/8-BIT

ADDRESS

DECODER

R

W

R

W

RESET

The AD5272/AD5274 can be reset through software by executing

Command 4 (see Table 12) or through hardware on the low

Figure 46. Simplified RDAC Circuit

RESET

pulse of the

pin. The reset command loads the RDAC

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation—1% Resistor Tolerance

register with the contents of the most recently programmed 50-TP

memory location. The RDAC register loads with midscale if no

50-TP memory location has been previously programmed. Tie

The nominal resistance between Terminal W and Terminal A, R_WA,

is available in 20 kΩ, 50 kΩ, and 100 kΩ, and 1024-/256-tap points

accessed by the wiper terminal. The 10-/8-bit data in the RDAC

latch is decoded to select one of the 1024 or 256 possible wiper

settings. The AD5272/ AD5274 contain an internal 1% resistor

tolerance calibration feature which can be disabled or enabled,

enabled by default, or by programming Bit C2 of the control

register (see Table 15). The digitally programmed output resis-

tance between the W terminal and the A terminal, R_WA, is

calibrated to give a maximum of 1% absolute resistance error

over both the full supply and temperature ranges. As a result,

the general equations for determining the digitally programmed

output resistance between the W terminal and A terminal are as

follows:

RESET

to V_DDif the

pin is not used.

RESISTOR PERFORMANCE MODE

This mode activates a new, patented 1% end-to-end resistor

tolerance that ensures a 1% resistor tolerance on each code,

that is, code = half scale and R_WA= 10 kΩ 100 Ω. See Table 2,

Table 3, Table 5, and Table 6 to check which codes achieve 1%

resistor tolerance. The resistor performance mode is activated by

programming Bit C2 of the control register (see Table 14 and

Table 15).

SHUTDOWN MODE

The AD5272/AD5274 can be shut down by executing the software

shutdown command, Command 9 (see Table 12), and setting

the LSB to 1. This feature places the RDAC in a zero-power-

consumption state where Terminal Ax is disconnected from

the wiper terminal. It is possible to execute any command from

Table 12 while the AD5272 or AD5274 is in shutdown mode.

The part can be taken out of shutdown mode by executing

Command 9 and setting the LSB to 0, or by issuing a software

or hardware reset.

For the AD5272

D

1024

R_WA(D) =

× R_WA

(1)

(2)

For the AD5274

D

256

R_WA(D) =

×R_WA

where:

D is the decimal equivalent of the binary code loaded in the

10-/8-bit RDAC register.

RDAC ARCHITECTURE

To achieve optimum performance, Analog Devices has patented the

RDAC segmentation architecture for all the digital potentiometers.

In particular, the AD5272/AD5274 employ a three-stage

segmentation approach, as shown in Figure 46. The AD5272/

AD5274 wiper switch is designed with the transmission gate

CMOS topology.

R

_WAis the end-to-end resistance.

In the zero-scale condition, a finite total wiper resistance of

120 Ω is present. Regardless of which setting the part is oper-

ating in, take care to limit the current between the A terminal

to B terminal, W terminal to A terminal, and W terminal to

B terminal, to the maximum continuous current of 3 mA, or

the pulse current specified in Table 8. Otherwise, degradation or

possible destruction of the internal switch contact can occur.

Rev. D | Page 23 of 28

AD5272/AD5274

Data Sheet

The ground pins of the AD5272/AD5274 devices are primarily

used as digital ground references. To minimize the digital

ground bounce, join the AD5272/AD5274 ground terminal

remotely to the common ground. The digital input control

signals to the AD5272/AD5274 must be referenced to the

device ground pin (GND) and satisfy the logic level defined in

the Specifications section. An internal level shift circuit ensures

that the common-mode voltage range of the three terminals

extends from V_SSto V_DD, regardless of the digital input level.

EXT_CAP CAPACITOR

A 1 μF capacitor to V_SSmust be connected to the EXT_CAP pin

(see Figure 47) on power-up and throughout the operation of

the AD5272/AD5274.

AD5272/

AD5274

50_OTP

MEMORY

EXT_CAP

BLOCK

C1

1µF

V

POWER-UP SEQUENCE

SS

Because there are diodes to limit the voltage compliance at

Terminal A and Terminal W (see Figure 48), it is important to

power V_DD/V_SSfirst before applying any voltage to Terminal A

and Terminal W; otherwise, the diode is forward-biased such

that V_DD/V_SSare powered unintentionally. The ideal power-up

sequence is V_SS, GND, V_DD, digital inputs, V_A, and V_W. The

order of powering V_A, V_W, and digital inputs is not important

as long as they are powered after V_DD/V_SS.

V

SS

Figure 47. EXT_CAP Hardware Setup

TERMINAL VOLTAGE OPERATING RANGE

The positive V_DDand negative V_SSpower supplies of the

AD5272/AD5274 define the boundary conditions for proper

2-terminal digital resistor operation. Supply signals present on

Terminal A and Terminal W that exceed V_DDor V_SSare clamped

by the internal forward-biased diodes (see Figure 48).

As soon as V_DDis powered, the power-on preset activates, which

first sets the RDAC to midscale and then restores the last

programmed 50-TP value to the RDAC register.

V

DD

A

W

V

SS

Figure 48. Maximum Terminal Voltages Set by V_DDand V_SS

Rev. D | Page 24 of 28

Data Sheet

AD5272/AD5274

OUTLINE DIMENSIONS

3.10

3.00

2.90

10

1

6

5

5.15

4.90

4.65

3.10

3.00

2.90

PIN 1

IDENTIFIER

0.50 BSC

0.95

0.85

0.75

15° MAX

1.10 MAX

0.70

0.55

0.40

0.15

0.05

0.23

0.13

6°

0°

0.30

0.15

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 49. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

2.48

2.38

2.23

3.10

3.00 SQ

0.50 BSC

2.90

10

6

PIN 1 INDEX

EXPOSED

PAD

1.74

1.64

1.49

AREA

0.50

0.40

0.30

0.20 MIN

1

5

BOTTOM VIEW

TOP VIEW

PIN 1

INDICATOR

(R 0.15)

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.30

0.25

0.20

0.20 REF

Figure 50. 10-Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3mm Body, Very Thin, Dual Lead

(CP-10-9)

Dimensions shown in millimeters

Rev. D | Page 25 of 28

AD5272/AD5274

Data Sheet

ORDERING GUIDE

Model¹

AD5272BRMZ-20

AD5272BRMZ-20-RL7

AD5272BRMZ-50

AD5272BRMZ-50-RL7

AD5272BRMZ-100

AD5272BRMZ-100-RL7

AD5272BCPZ-20-RL7

AD5272BCPZ-100-RL7

AD5274BRMZ-20

AD5274BRMZ-20-RL7

AD5274BRMZ-100

AD5274BRMZ-100-RL7

AD5274BCPZ-20-RL7

AD5274BCPZ-100-RL7

EVAL-AD5272SDZ

R_AW(kΩ) Resolution

Temperature Range

−40°C to +125°C

Evaluation Board

Package Description

10-Lead MSOP

10-Lead LFCSP_WD

10-Lead MSOP

10-Lead LFCSP_WD

Package Option

Branding

DE6

DE7

DE5

DE4

DE3

20

50

100

20

100

20

1,024

256

RM-10

CP-10-9

RM-10

CP-10-9

DEE

DED

DE9

20

256

100

20

256

100

256

DE8

¹Z = RoHS Compliant Part.

Rev. D | Page 26 of 28

Data Sheet

NOTES

AD5272/AD5274

Rev. D | Page 27 of 28

AD5272/AD5274

NOTES

Data Sheet

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D08076-0-3/13(D)

Rev. D | Page 28 of 28


型号：	AD5272BCPZ-20-RL7
厂家：	Rochester Electronics
描述：	20K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 1024 POSITIONS, PDSO10, 3 X 3 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, LFCSP-10 光电二极管转换器电阻器
文件：	总29页 (文件大小：1876K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5272BCPZ-20-RL7 [ROCHESTER]

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