74LVCH162244APAG [ROCHESTER]

LVC/LCX/Z SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48, GREEN, TSSOP-48;


型号：	74LVCH162244APAG
厂家：	Rochester Electronics
描述：	LVC/LCX/Z SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48, GREEN, TSSOP-48 驱动光电二极管输出元件逻辑集成电路
文件：	总7页 (文件大小：1107K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74LVCH162244A

3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

IDT74LVCH162244A

3.3V CMOS 16-BIT

BUFFER/DRIVER WITH 3-STATE

OUTPUTS, 5 VOLT TOLERANT I/O,

AND BUS-HOLD

FEATURES:

DESCRIPTION:

• Typical tSK(o) (Output Skew) < 250ps

The LVCH162244A 16-bit buffer/driver is built using advanced dual

metalCMOStechnology. The LVCH162244Ais designedspecificallyto

improve both the performance and density of 3-state memory address

drivers, clock drivers, and bus-oriented receivers and transmitters. The

devicecanbeusedasfour4-bitbuffers,two8-bitbuffers,orone16-bitbuffer.

Thisdeviceprovidestrueoutputsandsymmetricalactive-lowoutput-enable

(OE)inputs.

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• CMOS power levels (0.4μ W typ. static)

• All inputs, outputs, and I/O are 5V tolerant

• Available in TSSOP and TVSOP packages

All pins of this 16-bit buffer/driver can be driven from either 3.3V or 5V

devices. Thisfeatureallowstheuseofthisdeviceasatranslatorinamixed

3.3V/5Vsupplysystem.

The LVCH162244Ahas series resistors inthe device outputstructure

whichwillsignificantlyreduce line noise whenusedwithlightloads. This

driver has been developed to drive ±12mA at the designated threshold

levels.

The LVCH162244A has “bus-hold” which retains the inputs’ last state

whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputs

andeliminates the needforpull-up/downresistors.

DRIVE FEATURES:

• Balanced Output Drivers: ±12mA

• Full internal series termination

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

FUNCTIONALBLOCKDIAGRAM

¹OE

³OE

1A1

3A1

¹Y1

1Y2

³Y1

3Y2

¹A2

¹A3

³A2

³A3

¹Y3

¹Y4

³Y3

³Y4

¹A4

³A4

²OE

2A1

⁴OE

4A1

²Y1

2Y2

⁴Y1

4Y2

²A2

²A3

⁴A2

⁴A3

²Y3

²Y4

⁴Y3

⁴Y4

²A4

⁴A4

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

February 20, 2009

DSC-4727/5

IDT74LVCH162244A

3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

PINCONFIGURATION

Symbol

VTERM

TSTG

Description

Terminal Voltage with Respect to GND

Storage Temperature

Max

Unit

–0.5 to +6.5

–65 to +150

–50 to +50

–50

° C

1OE

1Y1

2OE

1A1

1A2

IOUT

DC Output Current

IIK

IOK

Continuous Clamp Current,

VI < 0 or VO < 0

1Y2

ICC

ISS

Continuous Current through each

VCC or GND

±100

GND

1A3

1Y3

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

1Y4

1A4

VCC

2A1

2Y1

2Y2

2A2

GND

2A3

2A4

3A1

GND

2Y3

2Y4

3Y1

3Y2

CAPACITANCE (TA = +25°C, F = 1.0MHz)

Symbol

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

4.5

COUT

CI/O

6.5

NOTE:

3A2

1. As applicable to the device type.

GND

3A3

3Y3

3Y4

PINDESCRIPTION

Pin Names

3A4

Description

VCC

4A1

xOE

xAx

xYx

3-State Output Enable Inputs (Active LOW)

Data Inputs⁽¹⁾

4Y1

4Y2

3-State Outputs

4A2

NOTE:

GND

1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.

GND

4Y3

4A3

4A4

4Y4

(1)

FUNCTION TABLE (EACH 4-BIT BUFFER)

4OE

3OE

Inputs

Outputs

xOE

xAx

xYx

TSSOP/ TVSOP

TOP VIEW

NOTE:

1. H = HIGH Voltage Level

X = Don’t Care

L = LOW Voltage Level

Z = High-Impedance

IDT74LVCH162244A

3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

OperatingCondition:TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

1.7

Typ.⁽¹⁾

—

Max.

—

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

VIL

Input LOW Voltage Level

Input Leakage Current

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

0.7

0.8

IIH

IIL

VCC = 3.6V

VI = 0 to 5.5V

—

µA

µ A

IOZH

IOZL

High Impedance Output Current

(3-State Output pins)

VCC = 3.6V

VO = 0 to 5.5V

—

IOFF

VIK

Input/Output Power Off Leakage

Clamp Diode Voltage

VCC = 0V, VIN or VO ≤ 5.5V

—

µ A

VCC = 2.3V, IIN = –18mA

–0.7

–1.2

Input Hysteresis

VCC = 3.3V

VCC = 3.6V

—

100

—

µA

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VIN = GND or VCC

(2)

3.6 ≤ VIN ≤ 5.5V

—

ΔICC

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

500

µ A

NOTES:

1. Typical values are at VCC = 3.3V, +25°C ambient.

2. This applies in the disabled state only.

BUS-HOLDCHARACTERISTICS

Symbol

IBHH

Parameter⁽¹⁾

Test Conditions

VI = 2V

Min.

–75

Typ.⁽²⁾

—

Max.

—

Unit

Bus-HoldInputSustainCurrent

VCC = 3V

µ A

IBHL

VI = 0.8V

—

IBHH

Bus-HoldInputSustainCurrent

Bus-HoldInputOverdrive Current

VCC = 2.3V

VCC = 3.6V

VI = 1.7V

—

µ A

IBHL

VI = 0.7V

—

IBHHO

VI = 0 to 3.6V

—

±500

IBHLO

NOTES:

1. Pins with Bus-Hold are identified in the pin description.

2. Typical values are at VCC = 3.3V, +25°C ambient.

IDT74LVCH162244A

3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

OUTPUTDRIVECHARACTERISTICS

Symbol

Parameter

TestConditions⁽¹⁾

Min.

VCC – 0.2

1.9

1.7

2.2

Max.

—

Unit

VOH

OutputHIGHVoltage

VCC = 2.3V to 3.6V

IOH = – 0.1mA

IOH = – 4mA

IOH = – 6mA

IOH = – 4mA

IOH = – 8mA

IOH = – 6mA

IOH = – 12mA

IOL = 0.1mA

IOL = 4mA

VCC = 2.3V

VCC = 2.7V

VCC = 3V

—

2.4

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.55

0.4

0.6

0.55

0.8

—

IOL = 6mA

—

VCC = 2.7V

VCC = 3V

IOL = 4mA

—

IOL = 8mA

—

IOL = 6mA

—

IOL = 12mA

—

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

OPERATING CHARACTERISTICS, TA = 25°C

Symbol

Parameter

Test Conditions

Typical

Unit

CPD

PowerDissipationCapacitanceperBuffer/DriverOutputsenabled

PowerDissipationCapacitanceperBuffer/DriverOutputsdisabled

CL = 0pF, f = 10Mhz

CPD

SWITCHINGCHARACTERISTICS⁽¹⁾

VCC = 2.7V

Max.

VCC = 3.3V ± 0.3V

Symbol

tPLH

Parameter

Min.

Max.

Unit

PropagationDelay

xAx to xYx

—

5.6

1.1

4.4

tPHL

tPZH

OutputEnableTime

xOE to xYx

—

6.9

6.8

—

5.5

6.3

500

tPZL

tPHZ

OutputDisableTime

1.8

—

tPLZ

xOE to xYx

(2)

tSK(o)

OutputSkew

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

IDT74LVCH162244A

3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

TESTCIRCUITSANDWAVEFORMS

TESTCONDITIONS

VIH

SAME PHASE

INPUT TRANSITION

(1)

(2)

Symbol VCC =3.3V±0.3V VCC =2.7V VCC =2.5V±0.2V Unit

tPHL

tPLH

VLOAD

VIH

2 x Vcc

Vcc

VOH

VOL

OUTPUT

2.7

1.5

300

2.7

1.5

300

Vcc / 2

150

VIH

VLZ

VHZ

OPPOSITE PHASE

INPUT TRANSITION

150

LVC Link

Propagation Delay

DISABLE

ENABLE

VLOAD

Open

GND

VIH

VCC

CONTROL

INPUT

tPZL

tPLZ

500Ω

VIN

VLOAD/2

VOUT

VLOAD/2

V^LZ

VOL

OUTPUT

NORMALLY

LOW

(1, 2)

Pulse

SWITCH

CLOSED

D.U.T.

Generator

tPHZ

tPZH

SWITCH

OPEN

500Ω

VOH

VHZ

OUTPUT

NORMALLY

HIGH

LVC Link

Test Circuit for All Outputs

LVC Link

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Enable and Disable Times

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

NOTES:

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.

VIH

DATA

INPUT

t^SU

SWITCHPOSITION

VIH

TIMING

INPUT

Test

Switch

V^LOAD

GND

Open

Open Drain

Disable Low

Enable Low

tREM

VIH

ASYNCHRONOUS

CONTROL

VIH

Disable High

Enable High

SYNCHRONOUS

CONTROL

tSU

All Other Tests

LVC Link

VIH

Set-up, Hold, and Release Times

LOW-HIGH-LOW

INPUT

tPLH1

t^PHL1

PULSE

V^OH

OUTPUT 1

VOL

tSK (x)

HIGH-LOW-HIGH

PULSE

tSK (x)

VOH

LVC Link

VOL

OUTPUT 2

tPLH2

tPHL2

Pulse Width

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

LVC Link

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74LVCH162244A

3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

ORDERINGINFORMATION

LVC

Device Type Package

XXXX

Bus-Hold

Family

Temp. Range

Thin Shrink Small Outline Package

TSSOP - Green

Thin Very Small Outline Package

PAG

TVSOP - Green

PFG

16-Bit Buffer/Driver with 3-State Outputs

Double-Density with Resistors, 12mA

244A

162

Bus-hold

-40°C to +85°C

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

800-345-7015 or 408-284-8200

fax: 408-284-2775

for Tech Support:

logichelp@idt.com

www.idt.com

74LVCH162244APAG [ROCHESTER]

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