24C04AE/P [ROCHESTER]
512X8 I2C/2-WIRE SERIAL EEPROM, PDIP8, PLASTIC, DIP-8;
| 型号： | 24C04AE/P |
| 厂家： | 
Rochester Electronics |
| 描述： | 512X8 I2C/2-WIRE SERIAL EEPROM, PDIP8, PLASTIC, DIP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总15页 (文件大小：809K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Obsolete Device
Please use 24LC04B.
24C04A
4K 5.0V I2C™ Serial EEPROM
FEATURES
PACKAGE TYPES
• Low power CMOS technology
• Hardware write protect
• Two wire serial interface bus, I2C™ compatible
• 5.0V only operation
DIP
A0
A1
1
2
8
7
VCC
WP
• Self-timed write cycle (including auto-erase)
• Page-write buffer
• 1 ms write cycle time for single byte
• 1,000,000 Erase/Write cycles guaranteed
• Data retention >200 years
A2
3
4
6
5
SCL
SDA
VSS
• 8-pin DIP/SOIC packages
• Available for extended temperature ranges
8-lead
SOIC
1
8
A0
A1
VCC
- Commercial (C):
- Industrial (I):
- Automotive (E):
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
2
3
4
7
6
5
WP
A2
SCL
SDA
DESCRIPTION
The Microchip Technology Inc. 24C04A is a 4K bit Elec-
trically Erasable PROM. The device is organized as
with a standard two wire serial interface. Advanced
CMOS technology allows a significant reduction in
power over NMOS serial devices. A special feature
provides hardware write protection for the upper half of
the block. The 24C04A has a page write capability of
up to eight bytes, and up to four 24C04A devices may
be connected to the same two wire bus.
VSS
14-lead
SOIC
14
1
2
3
4
5
NC
Vcc
WP
NC
NC
A0
13
12
11
10
A1
NC
A2
This device offers fast (1ms) byte write and
extended (-40°C to 125°C) temperature operation.
It is recommended that all other applications use
Microchip’s 24LC04B.
SCL
SDA
NC
6
7
9
8
Vss
NC
BLOCK DIAGRAM
Data
Buffer
(FIFO)
Vcc
VPP
R/W Amp
Vss
Data Reg.
A P
d o
Memory
Array
d
r
i
n
t
SDA
Slave Addr.
A0 to
A7
e
s e
s
r
Control
Logic
Increment
SCL
A8
A0 A1 A2 WP
I2C is a trademark of Philips Corporation.
2004 Microchip Technology Inc.
DS11183F-page 1
24C04A
TABLE 1-1:
PIN FUNCTION TABLE
Function
1.0
ELECTRICAL CHARACTERISTICS
Name
1.1
Maximum Ratings*
A0
No Function - Must be connected to
VCC or VSS
VCC...................................................................................7.0V
All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) .............+300°C
ESD protection on all pins................................................4 kV
A1, A2
VSS
Chip Address Inputs
Ground
SDA
SCL
WP
Serial Address/Data I/O
Serial Clock
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Write Protect Input
+5V Power Supply
VCC
TABLE 1-2:
DC CHARACTERISTICS
VCC = +5V (±10%)
Commercial (C): Tamb = 0°C to +70°C
Industrial (I): Tamb = -40°C to +85°C
Automotive (E): Tamb = -40°C to +125°C
Parameter
Symbol
Min.
Max.
Units
Conditions
VCC detector threshold
VTH
2.8
4.5
V
SCL and SDA pins:
High level input voltage
Low level input voltage
Low level output voltage
VIH
VIL
VOL
VCC x 0.7 VCC + 1
V
V
V
-0.3
VCC x 0.3
0.4
IOL = 3.2 mA (SDA only)
A1 & A2 pins:
High level input voltage
Low level input voltage
VIH
VIL
VCC - 0.5 VCC + 0.5
V
V
-0.3
0.5
Input leakage current
Output leakage current
ILI
—
10
µA
µA
pF
VIN = 0V to VCC
ILO
—
10
VOUT = 0V to VCC
Pin capacitance
CIN,
—
7.0
VIN/VOUT = 0V (Note)
(all inputs/outputs)
COUT
Tamb = +25°C, f = 1 MHz
Operating current
ICC Write
—
—
—
—
3.5
4.25
750
100
mA
mA
µA
FCLK = 100 kHz, program cycle time = 1 ms,
Vcc = 5V, Tamb = 0°C to +70°C
ICC Write
FCLK = 100 kHz, program cycle time = 1 ms,
Vcc = 5V, Tamb = (I) and (E)
ICC
Read
VCC = 5V, Tamb= (C), (I) and (E)
Standby current
ICCS
µA
SDA=SCL=VCC=5V (no PROGRAM active)
WP/TEST = VSS, A0, A1, A2 = VSS
Note: This parameter is periodically sampled and not 100% tested
FIGURE 1-1: BUS TIMING START/STOP
VHYS
SCL
SDA
THD:STA
TSU:STA
TSU:STO
START
STOP
DS11183F-page 2
2004 Microchip Technology Inc.
24C04A
TABLE 1-3:
AC CHARACTERISTICS
Parameter
Symbol
Min.
Typ
Max.
Units
Remarks
Clock frequency
FCLK
THIGH
TLOW
TR
—
4000
4700
—
—
—
—
—
—
—
100
—
kHz
ns
Clock high time
Clock low time
—
ns
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
1000
300
—
ns
TF
—
ns
THD:STA
4000
ns
After this period the first
clock pulse is generated
START condition setup time
TSU:STA
4700
—
—
ns
Only relevant for repeated
START condition
Data input hold time
Data input setup time
Data output delay time
STOP condition setup time
Bus free time
THD:DAT
TSU:DAT
TAA
0
—
—
—
—
—
—
—
ns
ns
250
300
4700
4700
3500
—
(Note 1)
TSU:STO
TBUF
ns
ns
—
Time the bus must be free
before a new transmission
can start
Input filter time constant
(SDA and SCL pins)
TI
—
—
—
100
ns
Program cycle time
TWC
.4
.4N
—
1
N
ms
ms
Byte mode
Page mode, N=# of bytes
Endurance
—
1M
—
cycles
25°C, Vcc = 5.0V, Block
Mode (Note 2)
Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (min-
imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our website.
FIGURE 1-2: BUS TIMING DATA
TR
TF
THIGH
TLOW
SCL
TSU:STA
THD:DAT
TSU:DAT
TSU:STO
THD:STA
SDA
IN
TSP
TBUF
TAA
TAA
THD:STA
SDA
OUT
2004 Microchip Technology Inc.
DS11183F-page 3
24C04A
3.4
Data Valid (D)
2.0
FUNCTIONAL DESCRIPTION
The 24C04A supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be con-
trolled by a master device which generates the serial
clock (SCL), controls the bus access, and generates
the START and STOP conditions, while the 24C04A
works as slave. Both master and slave can operate as
transmitter or receiver but the master device deter-
mines which mode is activated.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.
Up to four 24C04As can be connected to the bus,
selected by A1 and A2 chip address inputs. A0 must
be tied to VCC or VSS.
3.5
Acknowledge
3.0
BUS CHARACTERISTICS
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Note: The 24C04A does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C)
(A)
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
DS11183F-page 4
2004 Microchip Technology Inc.
24C04A
4.0
SLAVE ADDRESS
5.0
BYTE PROGRAM MODE
The chip address inputs A1 and A2 must be externally
connected to either VCC or ground (VSS), thereby
assigning a unique address to each device. A0 is not
used on the 24C04A and must be connected to either
VCC or VSS. Up to four 24C04A devices may be con-
nected to the bus. Chip selection is then accomplished
through software by setting the bits A1 and A2 of the
slave address to the corresponding hard-wired logic lev-
els of the selected 24C04A. After generating a START
condition, the bus master transmits the slave address
consisting of a 4-bit device code (1010), followed by the
chip address bits A0, A1 and A2. The seventh bit of that
byte (A0) is used to select the upper block (addresses
100—1FF) or the lower block (addresses 000—0FF) of
the array.
In this mode, the master sends addresses and one
data byte to the 24C04A.
Following the START signal from the master, the device
code (4-bits), the slave address (3-bits), and the R/W
bit, which is logic LOW, are placed onto the bus by the
master. This indicates to the addressed 24C04A that a
byte with a word address will follow after it has gener-
ated an acknowledge bit. Therefore the next byte trans-
mitted by the master is the word address and will be
written into the address pointer of the 24C04A. After
receiving the acknowledge, the master device trans-
mits the data word to be written into the addressed
memory location. The 24C04A acknowledges again
and the master generates a STOP condition. This ini-
tiates the internal programming cycle (Figure 6-1).
The eighth bit of the slave address determines if the
master device wants to read or write to the 24C04A
(Figure 4-1).
The 24C04A monitors the bus for its corresponding
slave address all the time. It generates an acknowl-
edge bit if the slave address was true and it is not in a
programming mode.
FIGURE 4-1: SLAVE ADDRESS
ALLOCATION
START
READ/WRITE
SLAVE ADDRESS
R/W
A
1
0
1
0
A2
A1
A0
2004 Microchip Technology Inc.
DS11183F-page 5
24C04A
as a result of only allowing the address registers bot-
tom 3 bits to increment while the upper 5 bits remain
unchanged.
6.0
PAGE PROGRAM MODE
To program the master sends addresses and data to
the 24C04A which is the slave (Figure 6-1 and
Figure 6-2). This is done by supplying a START condi-
tion followed by the 4-bit device code, the 3-bit slave
address, and the R/W bit which is defined as a logic
LOW for a write. This indicates to the addressed slave
that a word address will follow so the slave outputs the
acknowledge pulse to the master during the ninth clock
pulse. When the word address is received by the
24C04A, it places it in the lower 8 bits of the address
pointer defining which memory location is to be written.
(The A0 bit transmitted with the slave address is the
ninth bit of the address pointer). The 24C04A will gen-
erate an acknowledge after every 8-bits received and
store them consecutively in a RAM (8 bytes maximum)
buffer until a STOP condition is detected. This STOP
condition initiates the internal programming cycle.. If
more than 8 bytes are transmitted by the master, the
24C04A will roll over and overwrite the data beginning
with the first received byte. This does not affect erase/
write cycles of the EEPROM array and is accomplished
If the master generates a STOP condition after trans-
mitting the first data word (Point ‘P’ on Figure 6-1), byte
programming mode is entered.
The internal, completely self-timed PROGRAM cycle
starts after the STOP condition has been generated by
the master and all received data bytes in the page
buffer will be written in a serial manner.
The PROGRAM cycle takes N milliseconds, whereby N
is the number of received data bytes.
FIGURE 6-1: BYTE WRITE
S
T
A
R
T
S
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS
T
DATA
O
P
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
FIGURE 6-2: PAGE WRITE
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS (n)
DATA n
DATA n + 1
DATA n + 7
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
DS11183F-page 6
2004 Microchip Technology Inc.
24C04A
7.0
ACKNOWLEDGE POLLING
8.0
WRITE PROTECTION
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 7-1 for flow diagram.
Programming of the upper half of the memory will not
take place if the WP pin is connected to VCC (+5.0V).
The device will accept slave and word addresses but if
the memory accessed is write protected by the WP pin,
the 24C04A will not generate an acknowledge after the
first byte of data has been received, and thus the pro-
gram cycle will not be started when the STOP condition
is asserted.
FIGURE 7-1: ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
NO
Acknowledge
(ACK = 0)?
YES
Next
Operation
2004 Microchip Technology Inc.
DS11183F-page 7
24C04A
9.0
READ MODE
Note 1: If the master knows where the address
pointer is, it can begin the read sequence
at the current address (Figure 9-1) and
save time transmitting the slave and word
addresses.
In this mode the 24C04A transmits data to the master
devide.
As can be seen from Figure 9-2 and Figure 9-3, the
master first sets up the slave and word addresses by
doing a write. (Note: Although this is a read mode, the
address pointer must be written to). During this period
the 24C04A generates the necessary acknowledge bits
as defined in the appropriate section.
Note 2: In all modes, the address pointer will not
increment through a block (256 byte)
boundary, but will rotate back to the first
location in that block.
The master now generates another START condition
and transmits the slave address again, except this time
the read/write bit is set into the read mode. After the
slave generates the acknowledge bit, it then outputs
the data from the addressed location on to the SDA pin,
increments the address pointer and, if it receives an
acknowledge from the master, will transmit the next
consecutive byte. This auto-increment sequence is
only aborted when the master sends a STOP condition
instead of an acknowledge.
FIGURE 9-1: CURRENT ADDRESS READ
S
T
A
R
T
S
BUS ACTIVITY
MASTER
CONTROL
BYTE
T
DATA n
O
P
SDA LINE
S
P
A
C
K
N
O
BUS ACTIVITY
A
C
K
FIGURE 9-2: RANDOM READ
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS (n)
CONTROL
BYTE
DATA (n)
S
P
S
SDA LINE
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
FIGURE 9-3: SEQUENTIAL READ
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
DATA n
DATA n + 1
DATA n + 2
DATA n + X
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
DS11183F-page 8
2004 Microchip Technology Inc.
24C04A
10.4
WP Write Protection
10.0 PIN DESCRIPTION
This pin must be connected to either VCC or VSS. If tied
to VCC, write operations to the upper memory block will
not be executed. Read operations are possible.
10.1
A0, A1, A2 Chip Address Inputs
A0 is not used as a chip select bit and must be tied to
either Vss or Vcc. The levels on the remaining two
address inputs(A1, A2) are compared with the corre-
sponding bits in the slave address. The chip is selected
if the compare is true. These inputs must be connected
to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
(read/write the entire memory).
This feature allows the user to assign the upper half of
the memory as ROM which can be protected against
accidental programming. When write is disabled, slave
address and word address will be acknowledged but
data will not be acknowledged.
These two address inputs allow up to four 24C04A's
can be connected to the bus
10.2
SDASerialAddress/DataInput/Output
Note 1: A “page” is defined as the maximum num-
ber of bytes that can be programmed in a
single write cycle. The 24C04A page is 8
bytes long.
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to VCC (typical 10KΩ).
Note 2: A “block” is defined as a continuous area
of memory with distinct boundaries. The
address pointer can not cross the bound-
ary from one block to another. It will how-
ever, wrap around from the end of a block
to the first location in the same block. The
24C04A has two blocks, 256 bytes each.
For normal data transfer, SDA is allowed to change
only during SCL LOW. Changes during SCL HIGH are
reserved for indicating the START and STOP condi-
tions.
10.3
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
2004 Microchip Technology Inc.
DS11183F-page 9
24C04A
24C04A Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
24C04A
-
/P
P = Plastic DIP
SN = Plastic SOIC (150 mil Body), 8-lead
SM = Plastic SOIC (207 mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead
Package:
Blank = 0°C to +70°C
= -40°C to +85°C
Temperature
Range:
E = -40°C to +125°C
24C04A
24C04AT
4K I2C Serial EEPROM
Device:
4K I2C Serial EEPROM (Tape and Reel)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip Worldwide Web Site (www.microchip.com)
DS11183F-page 10
2004 Microchip Technology Inc.
24C04A
2004 Microchip Technology Inc.
DS11183F-page 11
24C04A
DS11183F-page 12
2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2004 Microchip Technology Inc.
DS11183F-page 13
WORLDWIDE SALES AND SERVICE
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AMERICAS
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Technical Support: 480-792-7627
Web Address: www.microchip.com
Unit 706B
200 Middle Road
Wan Tai Bei Hai Bldg.
No. 6 Chaoyangmen Bei Str.
Beijing, 100027, China
Tel: 86-10-85282100
Fax: 86-10-85282104
#07-02 Prime Centre
Singapore, 188980
Tel: 65-6334-8870 Fax: 65-6334-8850
Taiwan
Kaohsiung Branch
30F - 1 No. 8
Min Chuan 2nd Road
Kaohsiung 806, Taiwan
Tel: 886-7-536-4816
Fax: 886-7-536-4817
China - Chengdu
Rm. 2401-2402, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
Chengdu 610016, China
Tel: 86-28-86766200
Atlanta
3780 Mansell Road, Suite 130
Alpharetta, GA 30022
Tel: 770-640-0034
Fax: 770-640-0307
Taiwan
Taiwan Branch
Fax: 86-28-86766599
Boston
11F-3, No. 207
China - Fuzhou
Unit 28F, World Trade Plaza
No. 71 Wusi Road
Fuzhou 350001, China
Tel: 86-591-7503506
Fax: 86-591-7503521
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692-3848
Fax: 978-692-3821
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Taiwan
Taiwan Branch
13F-3, No. 295, Sec. 2, Kung Fu Road
Hsinchu City 300, Taiwan
Tel: 886-3-572-9526
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071
Fax: 630-285-0075
China - Hong Kong SAR
Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
Fax: 886-3-572-6459
Dallas
EUROPE
Austria
Durisolstrasse 2
A-4600 Wels
Austria
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45-4420-9895 Fax: 45-4420-9910
France
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
16200 Addison Road, Suite 255
Addison Plaza
China - Shanghai
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Addison, TX 75001
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Tel: 86-21-6275-5700
Fax: 86-21-6275-5060
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250
China - Shenzhen
Rm. 1812, 18/F, Building A, United Plaza
No. 5022 Binhe Road, Futian District
Shenzhen 518033, China
Tel: 86-755-82901380
Fax: 86-755-8295-1393
China - Shunde
Fax: 248-538-2260
Kokomo
2767 S. Albright Road
Kokomo, IN 46902
Tel: 765-864-8360
Fax: 765-864-8387
Room 401, Hongjian Building, No. 2
Fengxiangnan Road, Ronggui Town, Shunde
District, Foshan City, Guangdong 528303, China
Tel: 86-757-28395507 Fax: 86-757-28395571
Los Angeles
25950 Acero St., Suite 200
Mission Viejo, CA 92691
Tel: 949-462-9523
Germany
China - Qingdao
Rm. B505A, Fullhope Plaza,
No. 12 Hong Kong Central Rd.
Qingdao 266071, China
Tel: 86-532-5027355 Fax: 86-532-5027205
Steinheilstrasse 10
D-85737 Ismaning, Germany
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Fax: 949-462-9608
San Jose
1300 Terra Bella Avenue
Mountain View, CA 94043
Tel: 650-215-1444
Italy
India
Via Salvatore Quasimodo, 12
20025 Legnano (MI)
Milan, Italy
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-22290061 Fax: 91-80-22290062
Japan
Fax: 650-961-0286
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands
Waegenburghtplein 4
NL-5152 JR, Drunen, Netherlands
Tel: 31-416-690399
Toronto
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699
Yusen Shin Yokohama Building 10F
3-17-2, Shin Yokohama, Kohoku-ku,
Yokohama, Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Fax: 905-673-6509
Fax: 31-416-690340
ASIA/PACIFIC
Australia
Microchip Technology Australia Pty Ltd
Unit 32 41 Rawson Street
Epping 2121, NSW
Sydney, Australia
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
United Kingdom
505 Eskdale Road
Winnersh Triangle
Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Wokingham
Berkshire, England RG41 5TU
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Tel: 82-2-554-7200 Fax: 82-2-558-5932 or
82-2-558-5934
07/12/04
2004 Microchip Technology Inc.
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