RV5VE001B [RICOH]
MULTI-POWER SUPPLY; MULTI -POWER SUPPLY
| 型号： | RV5VE001B |
| 厂家： | 
RICOH ELECTRONICS DEVICES DIVISION |
| 描述： | MULTI-POWER SUPPLY |
| 文件： | 总49页 (文件大小：318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MULTI-POWER SUPPLY
RV5VE0××× SERIES
APPLICATION MANUAL
NO.EA-021-0006
MULTI-POWER SUPPLY
RV5VE0××× SERIES
OUTLINE
The RV5VE0×××series are multi-power supply ICs with high accuracy output voltage and detector threshold
and with ultra low supply current by CMOS process. Each of these ICs consists of four voltage regulators,two volt-
age detectors and control switches.These ICs can achieve the construction of an ideal power supply system in
accordance with the user's mask option.
Output Voltage and Detector Threshold can be independently set within each IC by laser trim. The package
are of 16pin SSOP(0.8mm pitch) and 16pin SSOP(0.65mm pitch).
FEATURES
•
•
•
•
Ultra-Low Supply Current
.....................
1.5V to 10.0V
Broad Operating Voltage Range
.....................................................
±
2.5%
High Accuracy Output Voltage and Detector Threshold
........
Output Voltage and Detector Threshold
Stepwise setting with a step of 0.1V is possible
(refer to Selection Guide)
.............
±
TYP. 100ppm/˚C
•
•
•
Low Temperature-Drift Coefficients of Output Voltage and Detector Threshold
.....................................
Small Dropout Voltage
50mV when IOUT is 80mA (Regulators 1, 2)
..................................................
Small Package
16pin SSOP (0.8mm pitch)
16pin SSOP (0.65mm pitch)
•
Direct connection to CPU is possible by an internal Level Shift Circuit.
APPLICATIONS
•
Power source system for hand-held communication equipment such as cellular phones and cordless telephones.
•
Power source system for battery-powered appliances.
PIN CONFIGURATION
•
×
RV5VE001
ROUT4
VSEN2
CD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
ROUT3
VSEN1
CSW3
CSW2
CSW1
ROUT2
IBC2
RESET
DOUT
ROUT1
IBC1
GND
1
RV5VE0×××
BLOCK DIAGRAMS
•
×
•
RV5VE0
×××
RV5VE001
(Optional Mask Version)
VDD
VDD
IBC1
IBC1
Regulator
1
Regulator
1
ROUT1
T Q
Q
R
ROUT1
Level
Shift
CSW1
CSW2
CSW3
IBC2
IBC2
Regulator
2
Regulator
2
ROUT2
ROUT2
Level
Shift
Regulator
3
One Shot
Regulator
3
ROUT3
ROUT4
DOUT
GND
ROUT3
Pulse
Generator
Level
Shift
Regulator
4
Regulator
4
ROUT4
DOUT
VSEN1
Detector
1
Detector
1
VSEN2
GND
RESET
CD
Delay
Detector
2
RESET
CD
Delay
Generator
Detector
2
Generator
SELECTION GUIDE
In the RV5VE0×××series, Standard ICs and Customized ICs by mask option (hereinafter Optional Mask
Version ICs) are available at the user's request. Voltage settings for six circuits, four for Regulators and two for
Detectors, can be designated.
Part Number is designated as follows :
RV5VE0
–
← Part Number
××× ××
↑
↑ ↑ ↑ ↑
a
b c d e
Code
Contents
Designation of Package Type:
V : 16pin SSOP (0.65mm pitch)
a
b
c
Serial Number for Multi-Power Supply IC (RV5VE) series:
Serial Number for Mask Version:
×1 for Standard ICs. Other numbers for Optional Mask Version ICs.
Serial Number for Voltage Setting:
d
e
A to Z are assigned in alphabetical order. (except I,O,Q,X)
Designation of Taping Type:
Ex. E1, E2
(refer to Taping Specifications)
2
RV5VE0×××
PIN DESCRIPTION
• RV5VE001×(Standard ICs)
Pin No.
Symbol
ROUT4
VSEN2
CD
Description
1
2
Output Pin for Voltage Regulator 4.
Sense Pin for Voltage Detector 2.
3
Pin for External Capacitor for Delay Time Setting of Voltage Detector 2.
Output Pin of Voltage Detector 2. Nch Open Drain Output. “L” Outputat Detection.
Output Pin of Voltage Detector 1. Nch Open Drain Output. “L” Output at Detection.
Output Pin of Voltage Regulator 1. Connected to Collector of PNP Transistor.
Connected to Base of External PNP Transistor for Voltage Regulator 1 and controls Base Current.
Ground Pin.
4
RESET
DOUT
ROUT1
IBC1
5
6
7
8
GND
IBC2
9
Connected to Base of External PNP Transistor for Voltage Regulator 2 and controls Base Current.
Output Pin of Voltage Regulator 2. Connected to Collector of PNP Transistor.
10
ROUT2
Control Switch Input Pin for turning Voltage Regulator 1 ON/OFF.
Input level for this Input Pin is Active “H” .
11
CSW1
Control Switch Input Pin for turning Voltage Regulator 2 ON/OFF.
Input level for this Input Pin is Active “H”
12
13
CSW2
CSW3
Control Switch Input Pin for turning Voltage Regulator 3 ON/OFF.
Input level for this Input Pin is Active “H” .
14
15
16
VSEN1
ROUT3
VDD
Sense Pin of Voltage Detector 1.
Output Pin of Voltage Regulator 3.
VDD Pin.
• RV5VE0×××(Optional Mask Version ICs)
Pin No.
2
Symbol
Description
5 Pins Nos. 2, 11, 12, 13 and 14 can be designated as Input Pins by User's
choice. Refer to Optional Mask Version Guide.
11
To be
named
by User
12
Pins other than the above 5 Pins can be selected from the same pins as those
used in R×5VE001×(Standard ICs)
13
14
3
RV5VE0×××
OPTIONAL MASK VERSION GUIDE
User can designate an optional mask version in accordance with the following Optional Mask Version Guide:
Item
Description
sense Pins of Voltage Detectors 1, 2 can be connected to Output ROUT , ROUT ,
•
1
2
Sense Pins of Voltage
Detectors 1, 2
3
4
ROUT , ROUT of Voltage Regulators, or VDD.
ON/OFF Control of
Regulators and
Detectors
• ON/OFF Control of Voltage Regulators 1 to 4 and Voltage Detector 1 can be per-
formed by 3 INPUT AND Gate.
• ON/OFF Control of Voltage Detector 2 can be directly performed.
• ON/OFF Control of 4 Voltage Regulators and 2 Voltage Detectors can be per-
formed by AND Gate of Toggle Input and Level Input.
• Edge Trigger Flip-Flop (Rise Edge Operation) is reset and Initialized at the rise
of power source or at the detection operation of Voltage Detector 1 or 2.
• Flip-Flop can be reset by one shot pulse at the detection of Voltage Detector 1 or
2, or the reset state can be maintained during the detection operation.
ON/OFF Control by
Toggle Input
(only Pin 11)
•
Five Input Pins are available as User's Pins as shown in the TABLE shown below.
• ON/OFF Control Input Pins for Regulators and detectors.
• Sense Pins of Voltage Detectors 1,2.
Pins by User's Choice
• Active “H” Input or Active “L” Input can be selected.
• RESET Output and DOUT Output, which are output from Voltage Detectors 1, 2,
can be set at “L” or “H” at the time of the detection.
• RESET Output and DOUT Output, which are output from Voltage Detectors 1,
2,can be set at “L” or “H” at the time of OFF by ON/OFF Control.
• Output Signals of Voltage Detectors 1, 2 can perform ON/OFF control of Voltage
Regulators 1 to 4.
Output of Voltage
Detectors 1, 2
•
Functions of Input Pins by User' Choice
Pin No.
Symbol
Functions
2
Control Switch of Each Circuit, Sense Pin of Voltage Detector 1 or 2.
11
12
13
14
Control Switch of Each Circuit, Schmitt trigger input possible.
Control Switch of Each Circuit only.
To be
named
by User
Control Switch of Each Circuit only.
Control Switch of Each Circuit, Sense Pin of Voltage Detector 1 or 2.
4
RV5VE0×××
DESCRIPTION OF EACH CIRCUIT
1. Voltage Regulators 1,2
•
Voltage Regulators 1, 2 are linear regulators which can be constructed of external PNP Transistor, and are capa-
ble of obtaining a large output current by a small Dropout Voltage.
Output Voltage of each of Voltage Regulators 1, 2 can be set stepwise with a step of 0.1V in the range of 3V to 6V
by laser trim.
•
•
•
•
Voltage Regulators 1, 2 can be turned ON/OFF by Control Pins.
Use External PNP Transistor of a low saturation type, with an hFE of 100 or more.
Use Voltage Regulators 1, 2 with the attachment of a Capacitor with a capacitance of 10µF or more to the Output
Pins.
2. Voltage Regulators 3,4
• Voltage Regulators 3, 4 are CMOS type linear regulators and have the same structure as those of Voltage
Regulators R×5RL and R×5RE series.
• Output Voltage of each of Voltage Regulators 3, 4 can be set stepwise with a step of 0.1V in the range of 2V to 6V
by laser trim.
• Voltage Regulators 3, 4 can be turned ON/OFF by Control Pins.
3. Voltage Detector 1
• When Voltage Detector 1 detects the lowering of VSEN1, the level of the output of Voltage Detector 1 becomes “L”
level. The output of Voltage Detector 1 is Nch Open Drain Output.
• Voltage Detector 1 can be set as follows by optional mask:
1. ON/OFF Control of Voltage Detector 1.
2. Output of Voltage Detector 1 at the detection can be set at “L” level or “H” level.
3. Output of Voltage Detector 1 at OFF can be set at “L” level or “H” level.
4. Sense Pins of Voltage Detectors 1, 2 can be connected to Output ROUT1, ROUT2, ROUT3, ROUT4 of Voltage
Regulators or VDD within the IC.
4. Voltage Detector 2
•
•
•
When Voltage Detector 2 detects the lowering of VSEN2, the level of the output of Voltage Detector 2 becomes “L”
level. The output of Voltage Detector 2 is Nch Open Drain Output.
Voltage Detector 2 can set Reset Delay Time. Delay Time can be set in accordance with the capacitance CD of
External Capacitor as shown on the following pages.
Voltage detector 2 can be set as follows by optional mask:
1. ON/OFF Control of Voltage Detector 2.
2. Output of Voltage Detector 2 at the detection can be set at “L” level or “H” level.
3. Output of Voltage Detector 2 at OFF can be set at “L” level or “H” level.
4. Sense Pins of Voltage Detectors 2 can be connected to Output ROUT1, ROUT2, ROUT3, ROUT4 of Voltage
Regulators or VDD within the IC.
5
RV5VE0×××
• Formula for calculating Reset Delay Time is
tD = 0.69×RD ×CD
wherein RD is the resistance of a built-in resistor and can be set at 1MΩ in IC, so that the above formula is:
tD = 0.69×106×CD
Voltage Detector with Delay Circuit is constructed as shown below.
• Block Diagram of Voltage Detector with delay Circuit.
VSEN2
VDD
Current Source
RD
+
–
RESET
GND
Vref
CD
Extermal Capacitor
5. Main Power Source Control (in the case of Optional Mask Version)
• This IC includes built-in Edge Trigger Flip-Flop (Rising Edge Operation) and AND Gate, so that Main Power
Source of any instruments can be turned ON/OFF by “AND” of Toggle Input and Level Input.
• Edge Trigger Flip-Flop is reset by One Shot Pulse Generator when Voltage Detector 1 or 2 detects the lowering
of the voltage. This Flip-Flop can be continuously reset during the detection.
6
RV5VE0×××
ABSOLUTE MAXIMUM RATINGS
Symbol
Item
Rating
+12
Unit
V
VIN
Input Voltage
VOUT
IOUT
Output Voltage
–0.3 to VIN+0.3
300
V
Output Current
mA
mW
mW
˚C
PD1
Power Dissipation1 (16pin SSOP (0.8mm pitch))
Power Dissipation2 (16pin SSOP (0.65mm pitch))
Operating Temperature Range
Storage Temperature Range
Lead Temperature(Soldering)
500
PD2
470
Topt
Tstg
–30 to +80
–40 to +125
260˚C 10s
˚C
Tsolder
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum ratings are threshold limit values that must not be exceeded even for an instant under any
conditions. Moreover, such values for any two items must not be reached simultaneously. Operation above
these absolute maximum ratings may cause degradation or permanent damage to the device. These are stress
ratings only and do not necessarily imply functional operation below these limits.
OVERALL CHARACTERISTICS
Symbol
Item
Conditions
MIN.
1.5
3.0
2.0
2.0
TYP.
MAX.
10.0
6.0
Unit
V
VDD
Operationg Voltage Range
Output Voltage Setting Range 1
Output Voltage Setting Range 2
Detector Threshold Setting Range
ROUT1,2
ROUT3,4
–VDET
Step of 0.1V
Step of 0.1V
Step of 0.1V
V
6.0
V
6.0
V
• Electrical Characteristics of R×5VE001×
The following three types of ICs are available as Standard ICs.The details of these ICs are shown in the section
of Electrical Characteristics on the following pages:
•
List of Standard Voltage Settings
Type Number
R×5VE001A R×5VE001B R×5VE001C
Output Voltage of Regulator 1 to 4
Threshold Voltage of Detector 1
Threshold Voltage of Detector 2
Conditions for Input Voltage
5.0V
5.4V
4.5V
6.0V
4.0V
4.4V
3.5V
4.8V
3.0V
3.4V
2.5V
3.6V
7
RV5VE0×××
• RV5VE001A
Voltage Regulators 1, 2 [ RV5VE001A]
Topt=25˚C
Symbol
ROUT1,2
ISS1,2
Item
Output Voltage
Quiescent Current
Supply Current
Dropout Voltage
Conditions
MIN.
TYP.
MAX.
5.125
100
1
Unit
4.875
5.000
V
µA
mA
V
IOUT=0mA
IOUT=80mA
Iopr1,2
VDIF1,2
ROUT1,2=5.0V,IOUT=80mA
0.05
0.3
∆VOUT
∆IOUT
ROUT1,2=5.0V
Load Regulation
Line Regulation
50
mV
1mA≤IOUT≤80mA
∆VOUT
∆VIN
ROUT1,2+0.3V≤VIN≤10.0V
0.05
60
0.3
%/V
RR
Ripple Rejection
Current Limit
f=120HZ,Ripple 0.5Vrms
40
3
dB
Base Current of IB1,2of
PNP Transistor
Ilim1,2
10
mA
∆VOUT
∆Topt
Output Voltage
Temperature Coefficient
±100
ppm/˚C
(Note 1) Unless otherwise provided, VDD = 6.0V, IOUT = 50mA, Co = 10µF, Rbe = 100kΩ.
(Note 2) Use External Transistor with hFE ≥ 100.
(Note 3) Quiescent Current = Operating Current of Regulators 1, 2 + 0.6/Rbe.
(Note 4) Supply Current = Quiescent (No Load) Current + Load Current/hFE.
Voltage Regulator 3 [RV5VE001A]
Topt=25˚C
Symbol
Item
Output Voltage
Supply Current
Dropout Voltage
Conditions
MIN.
TYP.
5.000
5.0
MAX.
5.125
10.0
0.3
Unit
ROUT
ISS3
4.875
V
µA
V
3
VDIF3
ROUT3=5.0V,IOUT=50mA
ROUT =5.0V
3
∆VOUT
∆IOUT
Load Regulation
50
mV
1mA≤IOUT≤50mA
∆VOUT
∆VIN
Line Regulation
Current Limit
ROUT3+0.5V≤VIN≤10.0V
0.05
0.3
%/V
Ilim3
100
300
mA
Output Voltage
∆VOUT
∆Topt
±100
ppm/˚C
Temperature Coefficient
(Note) Unless otherwise provided, VDD = 6.0V, IOUT = 30mA
8
RV5VE0×××
Voltage Regulator 4 [RV5VE001A]
Topt=25˚C
Symbol
ROUT4
ISS4
Item
Output Voltage
Supply Current
Dropout Voltage
Conditions
MIN.
TYP.
5.000
1.3
MAX.
Unit
V
4.875
5.125
3.9
µA
V
VDIF4
ROUT4=5.0V,IOUT=20mA
0.3
ROUT4=5.0V
∆VOUT
∆IOUT
Load Regulation
50
mV
1mA≤IOUT≤20mA
∆VOUT
∆VIN
Line Regulation
Current Limit
ROUT4+0.5V≤VIN≤10.0V
0.05
0.3
%/V
Ilim4
100
300
mA
Output Voltage
∆VOUT
∆Topt
±100
ppm/˚C
Temperature Coefficient
(Note) Unless otherwise provided, VDD = 6.0V, IOUT = 10mA
Voltage Detectors 1,2 [RV5VE001A]
Topt=25˚C
Symbol
–VDET1
–VDET2
Item
Conditions
MIN.
5.265
4.388
TYP.
5.400
4.500
MAX.
5.535
4.612
Unit
Detector Threshold 1
Detector Threshold 2
Voltage Detector 1
Voltage Detector 2
V
V
–
( VDET)
VHYS
Detector Threshold Hysteresis
Supply Current
V
×
0.05
Voltage Detector 1,VDD=6.0V
Voltage Detector 2,VDD=6.0V
VDS=0.5V, VDD=1.5V
1.3
1.5
3.9
4.5
µA
µA
ISS5
ISS6
1.5
IOUT
Output Current
mA
VDS=0.5V, VDD=6.0V
11.6
RD
Output Delay Resistor
Sense Pin Input Current
Voltage Detector 2 only
VSEN=6.0V
0.5
1.0
0.5
2.0
2
MΩ
ISEN
µA
∆VDET
∆Topt
Detector Threshold
Temperature Coefficient
±100
ppm/˚C
(Note) Unless otherwise provided, VDD = 6.0V.
9
RV5VE0×××
Input Pins [RV5VE001A]
Topt=25˚C
Symbol
Item
Conditions
MIN.
TYP.
MAX.
Unit
Ileak
VIL
Input Leakage Current
–1
1
µA
V
Control Switch
Low Level Input Voltage
CSW1 to 4
CSW1 to 4
0
2.4
0.8
Control Switch
High Level Input Voltage
VIH
VSIL
VSIH
VHYS
VDD
V
V
V
V
Schmitt Trigger
Low Level Input Voltage
Optional
Optional
Optional
Schmitt Trigger
High Level Input Voltage
Schmitt Trigger
Hysteresis Voltage
(Note) Unless otherwise provided, VDD = 6.0V.
10
RV5VE0×××
• RV5VE001B
Voltage Regulators 1, 2 [RV5VE001B]
Topt=25˚C
Symbol
ROUT1,2
ISS1,2
Item
Output Voltage
Quiescent Current
Supply Current
Dropout Voltage
Conditions
MIN.
TYP.
MAX.
4.100
100
1
Unit
V
3.900
4.000
IOUT=0mA
IOUT=80mA
µA
mA
V
Iopr1,2
VDIF1,2
ROUT1,2=4.0V,IOUT=80mA
0.05
0.3
ROUT1,2=4.0V
∆VOUT
∆IOUT
Load Regulation
Line Regulation
50
mV
1mA≤IOUT≤80mA
∆VOUT
∆VIN
ROUT1,2+0.3V≤VIN≤10.0V
0.05
60
0.3
%/V
RR
Ripple Rejection
Current Limit
f=120HZ,Ripple 0.5Vrms
40
3
dB
Base Current of IB1,2of
PNP Transistor
Ilim1,2
10
mA
∆VOUT
∆Topt
Output Voltage
Temperature Coefficient
±100
ppm/˚C
(Note 1) Unless otherwise provided, VDD = 4.8V, IOUT = 50mA, Co = 10µF, Rbe = 100kΩ.
(Note 2) Use External Transistor with hFE ≥ 100.
(Note 3) Quiescent Current = Operating Current of Regulators 1, 2 + 0.6/Rbe.
(Note 4) Supply Current = Quiescent (No Load) Current + Load Current/hFE.
Voltage Regulator 3 [RV5VE001B]
Topt=25˚C
Symbol
Item
Output Voltage
Supply Current
Dropout Voltage
Conditions
MIN.
TYP.
4.000
5.0
MAX.
4.100
10.0
0.3
Unit
ROUT
ISS3
3.900
V
µA
V
3
VDIF3
ROUT3=4.0V,IOUT=43mA
ROUT =4.0V
3
∆VOUT
∆IOUT
Load Regulation
50
mV
1mA≤IOUT≤43mA
∆VOUT
∆VIN
Line Regulation
Current Limit
ROUT3+0.5V≤VIN≤10.0V
0.05
0.3
%/V
Ilim3
100
300
mA
Output Voltage
∆VOUT
∆Topt
±100
ppm/˚C
Temperature Coefficient
(Note) Unless otherwiseprovided, VDD = 4.8V, IOUT = 30mA.
11
RV5VE0×××
Voltage Regulator 4 [RV5VE001B]
Topt=25˚C
Symbol
ROUT4
ISS4
Item
Output Voltage
Supply Current
Dropout Voltage
Conditions
MIN.
TYP.
4.000
1.3
MAX.
4.100
3.9
Unit
3.900
V
µA
V
VDIF4
ROUT4=4.0V,IOUT=17.5mA
0.3
ROUT4=4.0V
∆VOUT
∆IOUT
Load Regulation
50
mV
1mA≤IOUT≤17.5mA
∆VOUT
∆VIN
Line Regulation
Current Limit
ROUT4+0.5V≤VIN≤10.0V
0.05
0.3
%/V
Ilim4
100
300
mA
Output Voltage
∆VOUT
∆Topt
±100
ppm/˚C
Temperature Coefficient
(Note) Unless otherwise provided, VDD = 4.8V, IOUT = 10mA
Voltage Detectors 1,2 [RV5VE001B]
Topt=25˚C
Symbol
–VDET1
–VDET2
Item
Conditions
MIN.
4.290
3.413
TYP.
4.400
3.500
MAX.
4.510
3.587
Unit
Detector Threshold 1
Detector Threshold 2
Voltage Detector 1
Voltage Detector 2
V
V
(–VDET)
VHYS
Detector Threshold Hysteresis
Supply Current
V
×
0.05
Voltage Detector 1,VDD=4.8V
Voltage Detector 2,VDD=4.8V
VDS=0.5V, VDD=1.5V
1.2
1.4
1.5
9.0
3.6
4.2
µA
µA
ISS5
ISS6
IOUT
Output Current
mA
VDS=0.5V, VDD=4.8V
RD
Output Delay Resistor
Sense Pin Input Current
Voltage Detector 2 only
VSEN=4.8V
0.5
1.0
0.4
2.0
1.6
MΩ
ISEN
µA
∆VDET
∆Topt
Detector Threshold
Temperature Coefficient
±100
ppm/˚C
(Note) Unless otherwise provided, VDD = 4.8V.
12
RV5VE0×××
Input Pins [RV5VE001B]
Topt=25˚C
Symbol
Item
Conditions
MIN.
TYP.
MAX.
Unit
Ileak
VIL
Input Leakage Current
–1
1
µA
Control Switch
Low Level Input Voltage
CSW1 to 4
CSW1 to 4
0
2.0
0.8
V
V
V
V
V
Control Switch
High Level Input Voltage
VIH
VSIL
VSIH
VHYS
VDD
Schmitt Trigger
Low Level Input Voltage
Optional
Optional
Optional
Schmitt Trigger
High Level Input Voltage
Schmitt Trigger
Hysteresis Voltage
(Note) Unless otherwise provided, VDD = 4.8V.
13
RV5VE0×××
• RV5VE001C
Voltage Regulators 1, 2 [RV5VE001C]
Topt=25˚C
Symbol
ROUT1,2
ISS1,2
Item
Output Voltage
Quiescent Current
Supply Current
Dropout Voltage
Conditions
MIN.
TYP.
MAX.
3.075
100
1
Unit
2.925
3.000
V
µA
mA
V
IOUT=0mA
IOUT=80mA
Iopr1,2
VDIF1,2
ROUT1,2=3.0V,IOUT=80mA
0.05
0.3
ROUT1,2=3.0V
∆VOUT
∆IOUT
Load Regulation
Line Regulation
50
mV
1mA≤IOUT≤80mA
∆VOUT
∆VIN
ROUT1,2+0.3V≤VIN≤10.0V
0.05
60
0.3
%/V
RR
Ripple Rejection
Current Limit
f=120HZ,Ripple 0.5Vrms
40
3
dB
Base Current of IB1,2of
PNP Transistor
Ilim1,2
10
mA
∆VOUT
∆Topt
Output Voltage
Temperature Coefficient
±100
ppm/˚C
(Note 1) Unless otherwise provided, VDD = 3.6V, IOUT = 50mA, Co = 10µF, Rbe = 100kΩ.
(Note 2) Use External Transistor with hFE ≥ 100.
(Note 3) Quiescent Current = Operating Current of Regulators 1, 2 + 0.6/Rbe.
(Note 4) Supply Current = Quiescent (No Load) Current + Load Current/hFE.
Voltage Regulator 3 [RV5VE001C]
Topt=25˚C
Symbol
Item
Output Voltage
Supply Current
Dropout Voltage
Conditions
MIN.
TYP.
3.000
5.0
MAX.
3.075
10.0
0.3
Unit
ROUT
ISS3
2.925
V
µA
V
3
VDIF3
ROUT3=3.0V,IOUT=35mA
ROUT =3.0V
3
∆VOUT
∆IOUT
Load Regulation
50
mV
1mA≤IOUT≤35mA
∆VOUT
∆VIN
Line Regulation
Current Limit
ROUT3+0.5V≤VIN≤10.0V
0.05
0.3
%/V
Ilim3
100
300
mA
Output Voltage
∆VOUT
∆Topt
±100
ppm/˚C
Temperature Coefficient
(Note) Unless otherwise provided, VDD = 3.6V, IOUT = 30mA
14
RV5VE0×××
Voltage Regulator 4 [RV5VE001C]
Topt=25˚C
Symbol
ROUT4
ISS4
Item
Output Voltage
Supply Current
Dropout Voltage
Conditions
MIN.
TYP.
3.000
1.1
MAX.
Unit
V
2.925
3.075
3.3
µA
V
VDIF4
ROUT4=3.0V,IOUT=15mA
0.3
ROUT4=3.0V
∆VOUT
∆IOUT
Load Regulation
50
mV
1mA≤IOUT≤15mA
∆VOUT
∆VIN
Line Regulation
Current Limit
ROUT4+0.5V≤VIN≤10.0V
0.05
0.3
%/V
Ilim4
100
300
mA
Output Voltage
∆VOUT
∆Topt
100
±
ppm/˚C
Temperature Coefficient
(Note) Unless otherwise provided, VDD = 3.6V, IOUT = 10mA
Voltage Detectors 1,2 [RV5VE001C]
Topt=25˚C
Symbol
–VDET1
–VDET2
Item
Conditions
MIN.
3.315
2.438
TYP.
3.400
2.500
MAX.
3.485
2.562
Unit
Detector Threshold 1
Detector Threshold 2
Voltage Detector 1
Voltage Detector 2
V
V
(–VDET)
VHYS
Detector Threshold Hysteresis
Supply Current
V
×
0.05
Voltage Detector 1,VDD=3.6V
Voltage Detector 2,VDD=3.6V
VDS=0.5V, VDD=1.5V
1.1
1.3
1.5
6.5
3.3
3.9
µA
µA
ISS5
ISS6
IOUT
Output Current
mA
VDS=0.5V, VDD=3.6V
RD
Output Delay Resistor
Sense Pin Input Current
Voltage Detector 2 only
VSEN=3.6V
0.5
1.0
0.3
2.0
1.2
MΩ
ISEN
µA
∆VDET
∆Topt
Detector Threshold
Temperature Coefficient
±100
ppm/˚C
(Note) Unless otherwise provided, VDD = 6.0V.
15
RV5VE0×××
Input Pins [RV5VE001C]
Topt=25˚C
Symbol
Item
Conditions
MIN.
TYP.
MAX.
Unit
Ileak
VIL
Input Leakage Current
–1
1
µA
V
Control Switch
Low Level Input Voltage
CSW1 to 4
CSW1 to 4
0
1.6
0.6
Control Switch
High Level Input Voltage
VIH
VSIL
VSIH
VHYS
VDD
V
V
V
V
Schmitt Trigger
Low Level Input Voltage
Optional
Optional
Optional
Schmitt Trigger
High Level Input Voltage
Schmitt Trigger
Hysteresis Voltage
(Note) Unless otherwise provided, VDD = 3.6V.
16
RV5VE0×××
OPERATION
•
Regulators 1,2
ROUT4
VDD
Level
Shift
CSW1,2
IBC1,2
Current
Limit
Circuit
+
–
ROUT1,2
R1
R2
C1,2
GND
Each of Regulators 1 and 2 is operating with an external PNP transistor as shown in the above figure.
Regulators 1 and 2 divide Output Voltage VOUT by Feed-back Registers R1 and R2, and the divided voltage at the
node between Registers R1 and R2 is compared with the reference voltage by Error Amplifier, so that the base cur-
rent of the PNP transistor is adjusted, and a constant voltage is output. The output current from each of
Regulators 1 and 2 is monitored by Current Limitter, and when the output current exceeds a limit current,
Current Limitter limits the base current of the PNP transistor to the specified limit current.
The level of input signals to CSW 1, 2 is set at the same level as the output voltage level of ROUT4 by built-in
level shift circuit.
Phase compensation is made externally with C1,2.
•
Regulators 3,4
ROUT4
Level
VDD
Current
Limit
Circuit
Shift
CSW3
+
–
ROUT3,4
R1
R2
A
GND
Regulators 3 and 4 divide Output Voltage VOUT by feed-back Registers R1 and R2, and the divided voltage at
the node between Registers R1 and R2 is compared with the reference voltage by Error Amplifier, so that a con-
stant voltage is output. The output current from each of Regulators 3 and 4 is monitored by Current Limitter, and
when the output current exceeds a limit current, Current Limitter limits the output current to the limit current.
Regulator 4 is connected at Point to the GND in the above figure, so that Regulator 4 is always in operation.
The level of input signals to CSW1, 2 is set at the same level as the output voltage level of ROUT4 by built-in lev-
el shift circuits.
17
RV5VE0×××
•
Detector 1
VDD
VSEN1
Ra
DOUT
Output Tr.
+
–
Current Source
Nch
Rb
Rc
Tr.1
GND
Operation Diagram
Step
1
2
3
4
5
Step
Step 1 Step 2
Step 3
Step 4 Step 5
Detector Threshold Hysteresis
Comparator(+)Pin
Input Voltage
B
Released Voltage +VDET
Detected Voltage –VDET
I
II
II
II
I
A
Comparator Output
H
L
L
L
H
Minimum Operating Voltage
GND
Tr. 1
OFF ON
OFF ON
ON
ON OFF
ON OFF
Output Tr.
Nch
Indefinite
Output Voltage
GND
Rb + Rc
I.
· VDD
Ra + Rb + Rc
Rb
Ra + Rb
· VDD
.
II
Step of Operation
The following descriptions deal with VDD pin and VSEN1 pin as connected each other, but Detector 1 can be detect-
ed the different voltage from VDD through VSEN1 pin.
Step 1. Output Voltage is equal to Pull-up Voltage.
Step 2. When Input Voltage (VSEN1)reaches the state of Vref ≥ VSEN1 · (Rb+Rc)/(Ra+Rb+Rc)at Point A (Detected Voltage–VDET), the output of Comparator
is reversed, so that Output Voltage becomes GND.
Step 3. Output Voltage becomes indefinite when Power Source Voltage (VDD) is smaller than Minimum Operating Voltage. When the output is pulled-
up,VDD is output.
Step 4. Output Voltage becomes equal to GND.
Step 5. When Input Voltage to (VSEN1) reaches the state of Vref ≤ VSEN1 · Rb/(Ra + Rb) at Point B (Released Voltage+VDET), the output of Comparator is reversed,
so that Output Voltage becomes equal to Pulled-up Voltage.
18
RV5VE0×××
•
Detector 2
VSEN2
VDD
Current Source
Rb
Ra
+
–
RESET
GND
Tr.2
Rb
Rc
Tr.1
CD
Output Capacitor
Operation Diagram
Step
1
2
3
4
5
Step
Step 1 Step 2
Step 3
Step 4 Step 5
Detector Threshold Hysteresis
Comparato (+) Pin
Input Voltage
B
I
II
II
II
I
Released Voltage +VDET
Detected Voltage –VDET
A
Comparator Output
H
L
L
L
H
Minimum Operating Voltage
GND
Tr. 1
OFF ON
OFF ON
ON
ON OFF
ON OFF
Output Tr.
Nch
Indefinite
Output Voltage
GND
Delay Time
Rb + Rc
I
.
· VDD
Ra + Rb + Rc
Rb
· VDD
.
II
Ra + Rb
Step of Operation
The following descriptions deal with VDD pin and VSEN2 pin as connected each other, but Detector 2 can be detect-
ed the different voltage from VDD through VSEN2 pin.
Step 1. Output Voltage is equal to Pull-up Voltage.
Step 2. When Input Voltage (VSEN2) reaches the state of Vref ≥ VSEN2 · (Rb+Rc)/(Ra+Rb+Rc)at Point A (Detected Voltage –VDET), the output of Compara-
tor is reversed, so that Output Voltage becomes GND. Discharging is performed from CD pin connected to External Capacitor. No delay time is
generated.
Step 3. Output Voltage becomes indefinite when Power Source Voltage (VDD) is smaller than Minimum Operating Voltage. When the output is pulled-
up,VDD is output.
Step 4. Output Voltage becomes equal to GND.
Step 5. When Input Voltage (VSEN2) reaches the state of Vref≤VSEN2 · Rb/(Ra +Rb) at Point B (Released Voltage +VDET), the output of Comparator is reversed, and
6
the External Capacitor is charged through CD pin,so that Output Voltage becomes equal to Pulled-up Voltage after a delay timeTD (= 0.69 × 10 × CD).
19
RV5VE0×××
TEST CIRCUITS (RV5VE001A,B,C)
•
Test Circuit 1
100kΩ
100kΩ
1
16
H/L
VDD
H/L
H/L
10
µF
Tr.
0.1
µF
Tr.
10 0.1 CD
µF µF
10µF
8
9
100kΩ
ISS
100kΩ
Tr : 2SB804
(hFE=150)
· Output Voltage
· Quiescent Current
· Dropout Voltage
· Load Regulation
· Line Regulation
· Current Limit (Regulator 3, 4)
CSW1
H
L
CSW2
CSW3
L
· Output Voltage Temperature Coefficient
· Detector Threshold
Regulator 1
Regulator 2
Regulator 3
Regulator 4
Detector 1
Detector 2
L
H
L
L
L
L
L
· Detector Threshold Hysteresis
· Output Voltage Transient Response
L
H
L
L
L
L
L
L
•
Test Circuit 2
1
16
open
open
open
VDD
H/L
H/L
Tr
Tr.
10µF
10µF
8
9
100kΩ
100kΩ
Tr : 2SB804
(hFE=150)
· Ripple Rejection (Regulator 1, 2)
CSW1
H
CSW2
L
Regulator 1
Regulator 2
L
H
20
RV5VE0×××
•
Test Circuit 3
· Current Limit (Regulator 1, 2)
1
16
open
open
CSW1
H
CSW2
L
open
Regulator 1
Regulator 2
VDD
L
H
H/L
H/L
A
A
Ilim1
8
9
Ilim2
•
Test Circuit 4
open
· Output Current (Detector 1, 2)
1
16
open
VDD
open
A
A
0.5V
0.5V
8
9
21
RV5VE0×××
TYPICAL CHARACTERISTICS (RV5VE001A)
•
Regulator Section
1) Output Voltage vs. Input Voltage
(zoomed)
Regulator 1,2 (5V)
Regulator 1,2 (5V)
IOUT=50mA
IOUT=50mA
6
5.1
5.0
4.9
4.8
–30˚C
80˚C
5
4
3
2
1
–30˚C
25˚C
25˚C
80˚C
4.8
5.0
5.2
5.4
5.5
0
0
0
2
4
6
8
10
12
Input Voltage VIN(V)
Input Voltage VIN(V)
(zoomed)
Regulator 3 (5V)
Regulator 3 (5V)
IOUT=30mA
IOUT=30mA
80˚C
5.1
6
5
4
3
2
1
–30˚C
25˚C
5.0
4.9
4.8
–30˚C
80˚C
25˚C
4.8
5.0
5.2
5.4
5.6
2
4
6
8
10
12
Input Voltage VIN(V)
Input Voltage VIN(V)
(zoomed)
Regulator 4 (5V)
Regulator 4 (5V)
IOUT=10mA
IOUT=10mA
80˚C
5.1
5.0
4.9
4.8
6
5
4
3
2
1
–30˚C
–30˚C
25˚C
25˚C
80˚C
4.8
5.0
5.2
5.4
5.6
2
4
6
8
10
12
Input Voltage VIN(V)
Input Voltage VIN(V)
22
RV5VE0×××
2) Output Voltage vs. Output Current
Regulator 1,2 (5V)
Regulator 3 (5V)
VDD=6.0V
–30˚C
VDD=6.0V
5.2
5.0
4.8
4.6
4.4
4.2
4.0
5.1
25˚C
80˚C
5.0
80˚C
–30˚C
25˚C
4.9
4.8
0
100
200
300
0
100
200
300
Output Current IOUT(mA)
Output Current IOUT(mA)
Regulator 4 (5V)
VDD=6.0V
5.2
5.0
4.8
4.6
4.4
4.2
4.0
–30˚C
25˚C
80˚C
0
50
100
150
200
Output Current IOUT(mA)
3) Dropout Voltage vs. Output Curret
Regulator 1,2 (5V)
Regulator 3 (5V)
0.3
2.0
1.5
1.0
0.5
0.0
25˚C
25˚C
0.2
80˚C
80˚C
–30˚C
0.1
–30˚C
0.0
0
100
200
300
0
100
200
300
Output Current IOUT(mA)
Output Current IOUT(mA)
23
RV5VE0×××
Regulator 4 (5V)
2.0
1.5
1.0
0.5
0.0
80˚C
25˚C
–30˚C
0
50
100
100
100
Output Current IOUT(mA)
5) Ripple Rejection vs. Frequency
VDD = 6.0V 0.5Vrms
Regulator 1,2: IOUT=50mA C = 4.7µF
Regulator 3 : IOUT=30mA C = 0.1µF
4) Output Voltage vs.Temperature
(5V)
Regulator 4 : IOUT=10mA C = 0.1µF
5.04
70
Regulator 2
60
5.02
5.00
4.98
4.96
Regulator 1,2
50
Regulator 1
Regulator 4
40
Regulator 3
30
Regulator 4
VDD=6.0V
20
Regulator 1: IOUT=50mA
Regulator 2: IOUT=50mA
Regulator 3: IOUT=30mA
Regulator 4: IOUT=10mA
Regulator 3
10
0
10
100
1000
10000
–40 –20
0
20 40 60 80 100
Frequency f(Hz)
Temperature Topt(˚C)
6) Line Transient Response 1
Regulator 1,2 (5V)
IOUT=1mA
COUT=4.7µF
IOUT=1mA
COUT=0.1µF
Regulator 3 (5V)
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Input Voltage
Input Voltage
Output Voltage
Output Voltage
0
1
2
3
4
5
0
1
2
3
4
5
Time t(ms)
Time t(ms)
24
RV5VE0×××
IOUT=1mA
COUT=0.1µF
Regulator 4 (5V)
8
7
6
5
4
3
2
1
0
Input Voltage
Output Voltage
0
1
2
3
4
5
Time t(ms)
7) Line Transient Response 2
Regulator 1,2 (5V)
IOUT=10mA
COUT=4.7µF
IOUT=10mA
COUT=0.1µF
Regulator 3 (5V)
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Input Voltage
Input Voltage
Output Voltage
Output Voltage
0
1
2
3
4
5
0
1
2
3
4
5
Time t(ms)
Time t(ms)
IOUT=10mA
COUT=0.1µF
Regulator 4 (5V)
8
7
6
5
4
3
2
1
0
Input Voltage
Output Voltage
0
1
2
3
4
5
Time t(ms)
25
RV5VE0×××
8) Supply Current vs. Input Voltage
Regulator 1,2 (5V)
Regulator 3 (5V)
10
8
10
8
6
4
2
0
6
4
2
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
Input Voltage VDD(V)
Input Voltage VDD(V)
Regulator 4 (5V)
5
4
3
2
1
0
0
2
4
6
8
10
12
Input Voltage VDD(V)
9) Supply Current vs. Temperature
Regulator 1,2 (5V)
Regulator 3 (5V)
VDD=6.0V
VDD=6.0V
10
8
10
8
6
6
4
4
2
2
0
0
100
–40
0
20 40 60 80
–20
100
–40
0
20 40 60 80
–20
Temperature Topt(˚C)
Temperature Topt(˚C)
26
RV5VE0×××
Regulator 4 (5V)
VDD=6.0V
5
4
3
2
1
0
100
–40
0
20 40 60 80
–20
Temperature Topt(˚C)
10) Output Voltage Transient Response for “CSW” Input Voltage Step
VDD=6.0V
VDD=6.0V
IOUT=30mA
Regulator 3 (5V)
COUT=0.1µF
IOUT=50mA
COUT=10µF
Regulator 1,2 (5V)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
200
400
600
0
100
200
300
Time t(µs)
Time t(µs)
VDD=6.0V
IOUT=10mA
COUT=0.1µF
Regulator 4 (5V)
7
6
5
4
3
2
1
0
(Note) 0µs point is synchronous with being “H” state of Control Switch.
0
400
800
1200
Time t(µs)
27
RV5VE0×××
•
Detectors
1) Output Voltage vs. Input Voltage
2) Output Current vs. Input Voltage
Detector 1,2
Detector 1,2
–VDET1,2=2.0V
VDS=0.5V
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
24
20
–30˚C
16
12
8
25˚C
80˚C
80˚C
25˚C
–30˚C
4
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Input Voltage VDD(V)
0
1
2
3
4
5
6
7
Input Voltage VDD(V)
3) Supply Current vs. Input Voltage
Detector 2
Detector 1
4
10
8
3
80˚C
6
2
1
0
25˚C
4
–30˚C
80˚C
25˚C
–30˚C
2
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
Input Voltage VDD(V)
Input Voltage VDD(V)
4) Detected/Released Voltage vs. Temperature
Detector 1
Detector 2
5.7
4.8
+VDET1
+VDET2
5.6
4.7
4.6
4.5
4.4
5.5
–VDET1
–VDET2
5.4
5.3
–40 –20
0
20 40 60 80 100
–40 –20
0
20 40 60 80 100
Temperature Topt(˚C)
Temperature Topt(˚C)
28
RV5VE0×××
5) Output Delay Time (falling edge) vs.
Load Capacitance
6) Output Delay Time (rising edge) vs.
Input Voltage
Topt = 25˚C
Detector 2
Topt = 25˚C
without COUT
and CD
without CD
Detector 1,2
Detector 1,2
VDD = 3.0V
10-3
10-3
10-4
Detector 2
10-4
Detector 2
10-5
Detector 1
Detector 1
10-5
10-6
10-9
10-8
Load Capacitance COUT(F)
10-7
10-6
0
2
4
6
8
10
Input Voltage VDD(V)
8) Output Delay Time (rising edge) vs.
CD Pin External Capacitance
7) Output Delay Time (falling edge) vs.
CD Pin External Capacitance
Topt = 25˚C
without COUT
Detector 2
Detector 1
Topt = 25˚C
10-0
10-1
10-2
10-3
10-5
10-6
10-9
10-9
10-8
10-7
10-6
10-8
10-7
10-6
CD Pin External Capacitance CD(F)
CD Pin External Capacitance CD(F)
29
RV5VE0×××
TYPICAL CHARACTERISTICS (RV5VE001B)
•
Regulators
1) Output Voltage vs. Input Voltage
(zoomed)
Regulator 1,2 (4V)
Regulator 1,2 (4V)
IOUT=50mA
IOUT=50mA
5
4.1
4.0
3.9
3.8
–30˚C
25˚C
80˚C
4
3
2
1
–30˚C
25˚C
80˚C
2
4
6
8
10
12
0
0
0
3.8
4.0
4.2
4.4
4.6
Input Voltage VIN(V)
Input Voltage VIN(V)
(zoomed)
Regulator 3 (4V)
Regulator 3 (4V)
IOUT=30mA
IOUT=30mA
80˚C
4.1
5
4
3
2
1
–30˚C
25˚C
–30˚C
25˚C
4.0
3.9
3.8
80˚C
3.8
4.0
4.2
4.4
4.6
2
4
6
8
10
12
Input Voltage VIN(V)
Input Voltage VIN(V)
(zoomed)
Regulator 4 (4V)
Regulator 4 (4V)
IOUT=10mA
IOUT=10mA
80˚C
4.1
4.0
3.9
3.8
5
4
3
2
1
–30˚C
25˚C
25˚C
–30˚C
80˚C
3.8
4
4.0
4.2
4.4
4.6
2
4
6
8
10
12
Input Voltage VIN(V)
Input Voltage VIN(V)
30
RV5VE0×××
2) Output Voltage vs. Output Current
Regulator 1,2 (4V)
Regulator 3 (4V)
VDD=4.8V
–30˚C
VDD=4.8V
4.2
4.0
3.8
3.6
3.4
3.2
3.0
4.1
4.0
3.9
3.8
–30˚C 25˚C
25˚C
80˚C
80˚C
0
100
200
300
0
100
200
300
Output Current IOUT(mA)
Output Current IOUT(mA)
Regulator 4 (4V)
VDD=4.8V
4.2
4.0
3.8
3.6
3.4
3.2
3.0
–30˚C
25˚C
80˚C
0
50
100
150
Output Current IOUT(mA)
3) Dropout Voltage vs. Output Curret
Regulator 1,2 (4V)
Regulator 3 (4V)
0.3
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
80˚C
0.2
80˚C
25˚C
25˚C
–30˚C
0.1
–30˚C
0.0
0
100
200
300
0
100
200
300
Output Current IOUT(mA)
Output Current IOUT(mA)
31
RV5VE0×××
Regulator 4 (4V)
2.0
1.5
1.0
0.5
0.0
80˚C
25˚C
–30˚C
0
20
40
60
80
100
Output Current IOUT(mA)
5) Ripple Rejection vs. Frequency
VDD = 4.8V 0.5Vrms
Regulator 1,2: IOUT=50mA C=4.7µF
Regulator 3 : IOUT=30mA C=0.1µF
4) Output Voltage vs.Temperature
Regulator 4 : IOUT=10mA C=0.1µF
(4V)
4.04
70
Regulator 2
Regulator 1
60
4.02
4.00
Regulator 1,2
50
40
30
20
10
0
Regulator 4
VDD=4.8V
Regulator 3
Regulator 3
Regulator 4
Regulator 1: IOUT=50mA
Regulator 2: IOUT=50mA
Regulator 3: IOUT=30mA
Regulator 4: IOUT=10mA
3.98
3.96
–40 –20
0
20 40 60 80 100
10
100
1000
10000
Temperature Topt(˚C)
Frequency f(Hz)
6) Line Transient Response 1
Regulator 1,2 (4V)
IOUT=1mA
COUT=0.1µF
IOUT=1mA
COUT=4.7µF
Regulator 3 (4V)
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Input Voltage
Input Voltage
Output Voltage
Output Voltage
0
1
2
3
4
5
0
1
2
3
4
5
Time t(ms)
Time t(ms)
32
RV5VE0×××
IOUT=1mA
COUT=0.1µF
Regulator 4 (4V)
8
7
6
5
4
3
2
1
0
Input Voltage
Output Voltage
0
1
2
3
4
5
Time t(ms)
7) Line Transient Response 2
Regulator 1,2 (4V)
IOUT=10mA
COUT=0.1µF
IOUT=10mA
COUT=4.7µF
Regulator 3 (4V)
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Input Voltage
Input Voltage
Output Voltage
Output Voltage
0
1
2
3
4
5
0
1
2
3
4
5
Time t(ms)
Time t(ms)
IOUT=10mA
COUT=0.1µF
Regulator 4 (4V)
8
7
6
5
4
3
2
1
0
Input Voltage
Output Voltage
0
1
2
3
4
5
Time t(ms)
33
RV5VE0×××
8) Supply Current vs. Input Voltage
Regulator 1,2 (4V)
Regulator 3 (4V)
10
8
10
8
6
4
2
0
6
4
2
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
Input Voltage VDD(V)
Input Voltage VDD(V)
Regulator 4 (4V)
5
4
3
2
1
0
0
2
4
6
8
10
12
Input Voltage VDD(V)
9) Supply Current vs. Temperature
Regulator 1,2 (4V)
Regulator 3 (4V)
VDD=4.8V
VDD=4.8V
10
8
10
8
6
6
4
4
2
2
0
0
–40 –20
0
20 40 60 80 100
0
–40 –20
20 40 60 80 100
Temperature Topt(˚C)
Temperature Topt(˚C)
34
RV5VE0×××
Regulator 4 (4V)
VDD=4.8V
5
4
3
2
1
0
–40 –20
0
20 40 60 80 100
Temperature Topt(˚C)
10) Output Voltage Transient Response for “CSW” Input Voltage Step
VDD=4.8V
VDD=4.8V
IOUT=30mA
COUT=0.1µF
IOUT=50mA
COUT=10µF
Regulator 1,2 (4V)
Regulator 3 (4V)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
200
400
600
0
100
200
300
Time t(µs)
Time t(µs)
VDD=4.8V
IOUT=10mA
COUT=0.1µF
Regulator 4 (4V)
7
6
5
4
3
2
1
0
(Note) 0µs point is synchronous with being “H” state of Control Switch.
0
400
800
1200
Time t(µs)
35
RV5VE0×××
•
Detectors
1) Output Voltage vs. Input Voltage
2) Output Current vs. Input Voltage
Detector 1,2
Detector 1,2
–VDET1,2=2.0V
VDS=0.5V
4.0
3.5
3.0
2.5
2.0
1.5
24
–30˚C
25˚C
20
16
12
8
80˚C
80˚C
25˚C
–30˚C
1.0
0.5
0.0
4
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
1
2
3
4
5
6
7
0
Input Voltage VDD(V)
Input Voltage VDD(V)
3) Supply Current vs. Input Voltage
Detector 2
Detector 1
10
8
4
3
6
25˚C
80˚C
2
1
0
4
25˚C
80˚C
–30˚C
2
–30˚C
10
0
0
2
4
6
8
12
0
2
4
6
8
10
12
Input Voltage VDD(V)
Input Voltage VDD(V)
4) Detected/Released Voltage vs. Temperature
Detector 1
Detector 2
3.8
4.7
+VDET1
3.7
3.6
3.5
3.4
4.6
+VDET2
4.5
–VDET1
–VDET2
4.4
4.3
–40 –20
0
20 40 60 80 100
–40 –20
0
20 40 60 80 100
Temperature Topt(˚C)
Temperature Topt(˚C)
36
RV5VE0×××
5) Output Delay Time (falling edge) vs.
Load Capacitance
6) Output Delay Time (rising edge) vs.
Input Voltage
Topt = 25˚C
Detector 2
Topt = 25˚C
without COUT
and CD
without C
D
Detector 1,2
Detector 1,2
VDD = 3.0V
10-3
10-4
10-5
10-6
10-3
Detector 2
10-4
Detector 2
Detector 1
Detector 1
10-5
10-9
10-8
10-7
10-6
0
2
4
6
8
10
Input Voltage VDD(V)
Load Capacitance COUT(F)
8) Output Delay Time (rising edge) vs.
CD Pin External Capacitance
7) Output Delay Time (falling edge) vs.
CD Pin External Capacitance
Topt = 25˚C
Detector 2
Detector 2
Topt = 25˚C
without COUT
10-0
10-1
10-2
10-3
10-5
10-6
10-9
10-9
10-8
10-7
10-6
10-8
10-7
10-6
CD Pin External Capacitance CD(F)
CD Pin External Capacitance CD(F)
37
RV5VE0×××
TYPICAL CHARACTERISTICS (RV5VE001C)
•
Regulator Section
1) Output Voltage vs. Input Voltage
(zoomed)
Regulator 1,2 (3V)
Regulator 1,2 (3V)
IOUT=50mA
IOUT=50mA
3.2
3.1
3.0
2.9
2.8
–30˚C
3.0
80˚C
25˚C
2.8
2.6
2.4
2.2
2.0
1.8
80˚C
25˚C –30˚C
0
0
0
2
4
6
8
10
12
2.6
2.8
3.0
3.2
3.4
3.6
Input Voltage VIN(V)
Input Voltage VIN(V)
(zoomed)
Regulator 3 (3V)
Regulator 3 (3V)
IOUT=30mA
IOUT=30mA
3.1
3.0
2.9
2.8
3.5
3.0
2.5
2.0
1.5
–30˚C
25˚C 80˚C
25˚C
–30˚C
80˚C
3.2
2
4
6
8
10
12
2.8
3.0
3.4
3.6
Input Voltage VIN(V)
Input Voltage VIN(V)
(zoomed)
Regulator 4 (3V)
Regulator 4 (3V)
IOUT=10mA
IOUT=10mA
3.1
3.0
2.9
2.8
–30˚C
3.0
2.5
2.0
1.5
80˚C
25˚C
25˚C
–30˚C
80˚C
2
4
6
8
10
12
2.8
3.0
3.2
3.4
3.6
Input Voltage VIN(V)
Input Voltage VIN(V)
38
RV5VE0×××
2) Output Voltage vs. Output Current
Regulator 1,2 (3V)
Regulator 3 (3V)
VDD=3.6V
VDD=3.6V
3.1
3.0
2.8
2.6
2.4
2.2
2.0
3.0
–30˚C
25˚C
–30˚C
80˚C
25˚C
80˚C
2.9
2.8
0
100
200
300
0
100
200
300
Output Current IOUT(mA)
Output Current IOUT(mA)
Regulator 4 (3V)
VDD=3.6V
3.2
3.0
2.8
2.6
2.4
2.2
2.0
–30˚C
80˚C
25˚C
0
50
100
150
Output Current IOUT(mA)
3) Dropout Voltage vs. Output Current
Regulator 1,2 (3V)
Regulator 3 (3V)
2.0
1.5
1.0
0.5
0.0
0.3
80˚C
25˚C
80˚C
0.2
25˚C
–30˚C
0.1
–30˚C
0.0
0
100
200
300
0
100
200
300
Output Current IOUT(mA)
Output Current IOUT(mA)
39
RV5VE0×××
Regulator 4 (3V)
2.0
1.5
1.0
0.5
0.0
80˚C
25˚C
–30˚C
0
20
40
60
80
100
Output Current IOUT(mA)
5) Ripple Rejection vs. Frequency
VDD = 3.6V 0.5Vrms
Regulator 1,2: IOUT=50mA C=4.7 µF
Regulator 3 : IOUT=30mA C=0.1µF
4) Output Voltage vs.Temperature
Regulator 4 : IOUT=10mA C=0.1µF
70
3.02
Regulator 4
60
3.01
3.00
2.99
2.98
2.97
2.96
Regulator 1,2
50
Regulator 1
40
Regulator 3
Regulator 2
Regulator 3
30
Regulator 4
VDD=3.6V
20
10
0
Regulator 1: IOUT=50mA
Regulator 2: IOUT=50mA
Regulator 3: IOUT=30mA
Regulator 4: IOUT=10mA
10
100
1000
10000
–40
–20
0
20 40 60 80 100
Frequency f(Hz)
Temperature Topt(˚C)
6) Line Transient Response 1
IOUT=1mA
COUT=4.7µF
IOUT=1mA
COUT=0.1µF
Regulator 3 (3V)
Regulator 1,2 (3V)
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Input Voltage
Input Voltage
Output Voltage
Output Voltage
0
4
1
5
2
3
0
1
4
5
2
3
Time t(ms)
Time t(ms)
40
RV5VE0×××
IOUT=1mA
COUT=0.1µF
Regulator 4 (3V)
8
7
6
5
4
3
2
1
0
Input Voltage
Output Voltage
0
1
2
3
4
5
Time t(ms)
7) Line Transient Response 2
Regulator 1,2 (3V)
IOUT=10mA
COUT=0.1µF
IOUT=10mA
COUT=4.7µF
Regulator 3 (3V)
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Input Voltage
Input Voltage
Output Voltage
Output Voltage
0
1
2
3
4
5
0
1
2
3
4
5
Time t(ms)
Time t(ms)
Regulator 4 (3V)
IOUT=10mA
COUT=0.1µF
8
7
6
5
4
3
2
1
0
Input Voltage
Output Voltage
0
1
2
3
4
5
Time t(ms)
41
RV5VE0×××
8) Supply Current vs. Input Voltage
Regulator 1,2 (3V)
Regulator 3 (3V)
10
10
8
8
6
4
2
0
6
4
2
0
0
2
4
6
8
10
0
2
4
6
8
10
12
12
Input Voltage VDD(V)
Input Voltage VDD(V)
Regulator 4 (3V)
5
4
3
2
1
0
0
2
4
6
8
10
12
Input Voltage VDD(V)
9) Supply Current vs. Temperature
Regulator 1,2 (3V)
Regulator 3 (3V)
VDD=3.6V
VDD=3.6V
10
8
10
8
6
6
4
4
2
2
0
0
100
100
–40
0
20 40 60 80
–40
0
20 40 60 80
–20
–20
Temperature Topt(˚C)
Temperature Topt(˚C)
42
RV5VE0×××
Regulator 4 (3V)
VDD=3.6V
5
4
3
2
1
0
–40 –20
0
20 40 60 80 100
Temperature Topt(˚C)
10) Output Voltage Transient Response for “CSW” Input Voltage Step
VDD=3.6V
VDD=3.6V
IOUT=30mA
COUT=0.1µF
IOUT=50mA
COUT=10µF
Regulator 1,2 (3V)
Regulator 3 (3V)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
200
400
600
0
0
100
200
Time t(µs)
300
Time t(µs)
VDD=3.6V
IOUT=10mA
COUT=0.1µF
Regulator 4 (3V)
7
6
5
4
3
2
1
0
(Note) Control Switch becomes ON ( “H” ) at 0µs.
0
400
800
Time t(µs)
1200
43
RV5VE0×××
•
Detectors
1) Output Voltage vs. Input Voltage
2) Output Current vs. Input Voltage
Detector 1,2
Detector 1,2
–VDET1,2=2.0V
VSD=0.5V
24
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
–30˚C
25˚C
20
16
12
8
80˚C
80˚C
25˚C
4
–30˚C
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0
1
2
3
4
5
6
7
Input Voltage VDD(V)
Input Voltage VDD(V)
3) Supply Current vs. Input Voltage
Detector 1
Detector 2
10
8
4
3
6
25˚C
80˚C
2
1
0
4
25˚C
6
80˚C
–30˚C
2
–30˚C
10
0
0
2
4
8
12
0
2
4
6
8
10
12
Input Voltage VDD(V)
Input Voltage VDD(V)
4) Detected/Released Voltage vs. Temperature
Detector 1
Detector 2
3.7
2.8
+VDET1
3.6
2.7
2.6
2.5
2.4
+VDET2
3.5
–VDET2
–VDET1
3.4
3.3
–40 –20
0
20 40 60 80 100
–40 –20
0
20 40 60 80 100
Temperature Topt(˚C)
Temperature Topt(˚C)
44
RV5VE0×××
5) Output Delay Time (falling edge) vs.
Load Capacitance
6) Output Delay Time (rising edge) vs.
Input Voltage
Topt = 25˚C
Detector 2
Topt = 25˚C
without COUT
and CD
without C
D
Detector 1,2
Detector 1,2
VDD = 3.0V
10-3
10-3
10-4
Detector 2
10-4
Detector 2
10-5
10-6
Detector 1
Detector 1
10-5
10-6
10-9
10-8
10-7
0
2
4
6
8
10
Load Capacitance COUT(F)
Input Voltage VDD(V)
8) Output Delay Time (rising edge) vs.
CD Pin External Capacitance
7) Output Delay Time (falling edge) vs.
CD Pin External Capacitance
Topt = 25˚C
without CD
Detector 2
Detector 2
Topt = 25˚C
10-0
10-1
10-2
10-3
10-5
10-6
10-9
10-8
10-7
10-6
10-9
10-8
10-7
10-6
CD Pin External Capacitance CD(F)
CD Pin External Capacitance CD(F)
45
RV5VE0×××
TYPICAL APPLICATION
• RV5VE001×
In this example of the circuit, the output of Regulator 4 is used as the power source for CPU. The voltage input
to CSW 1, 2, 3 pins is subject to level shift within the IC so as to have the same level as that of the voltage of CPU.
Therefore CSW 1, 2, 3 pins can be directly connected to CPU. Detector 1 monitors the voltage of the battery and
Detector 2 monitors the voltage of the power source for CPU.
Application for Cellular Phones (RV5VE001×)
SBD
R×5VE001×
R3
R4
ROUT4
VSEN2
CD
VDD
ROUT3
VSEN1
VCC
RESET
C5
RESET CSW3
DOUT CSW2
ROUT1 CSW1
I/O
I/O
I/O
CPU
INT
IBC1
ROUT2
IBC2
Tr
GND
Tr
R1
R2
C2
CD C1
C4 C3
Memory
Unit
Logic
Unit
C1,2,5=10µF / C3,4=0.1µF / CD=0.1µF
R1,2,3,4=100kΩ
Transmitter
Unit
Receiver/Audio
Unit
Tr: 2SB799(NEC PNP type,hFE=100 to 200)
SBD: MA717(Panasonic)
APPLICATION HINTS
When using these ICs, be sure to take care of the following points :
•
Minimize the impedance of VDD and GND wiring. In particular, with respect to the VDD wiring, the output cur-
rent of Regulators flows thereinto, so that when the wiring impedance is high, the operation of the IC tends to be
unstable and is vulnerable to noise.
•
•
Provide a capacitor with a capacitance of about 10µF between VDD pin and GND pin with a minimum wiring
length.
Rush current flows into the capacitor connected to the output of Regulators at the start of the operation of the
Regulators. In particular, Regulators 1, 2 are equipped with External PNP Transistor and accordingly have
excellent drive performance. Therefore, when Regulators 1, 2 start to operate, for example, under the conditions
that hFE of External PNP Transistor is 100 and the base current of the limiter is 5mA, a rush current of 500mA
flows into the regulators. When the wiring impedance is high, the Power Source Voltage applied to IC tends to
be varied by the rush current, so that the operation of IC may be adversely affected by the variation of the Power
Source Voltage.
•
•
In these ICs phase compensation is made for securing stable operation even when the load current is varied.
1
4
Select the capacitors C1 to C4 conecting the Pin ROUT to ROUT with good frequency characteristics and small
ESR.
Be sure to connect a resistor with a resistance of about 100kΩ between the base and the emitter for preventing
the oscillation.
•
•
Set external parts as close as possible to the IC and minimize the connection between the parts and the IC.
When using a capacitor connected to CD pin, use a Schottky Barrier Diode (SBD) to discharge CD capacitor at
the time of abrupt fluctuation of power source voltage.
46
RV5VE0×××
APPLICATION FOR CELLULAR PHONES
(RV5VE0×××:Optional Mask Version)
This Optional Mask Version's application operates as follows.
Regulator 1, 2
Regulator 3
Regulator 4
: Regulator 1 and 2 can be enabled and disabled through Toggle Input and CPU signal CSW1.
: Regulator 3 can be enabled and disabled through Toggle Input and CPU signal CSW2.
: Regulator 4 is always enabled by dry cells (when the VDD voltage is maintained higher than
minimum operating voltage). The output of Regulator 4 is not only the power source for
CPU but also the level shift voltage of CSW 1, 2 pins. Therefor CSW1, 2 pins can be direct-
ly connected to CPU.
Detector 1, 2
TFF
: Detector 1 and 2 monitor the VDD level and the output of Regulator 4 respectively.
Furthermore Detector 2 can generate the output-delay time (time delay to output rising
edge) by connecting a capacitor to CD pin.
: TFF can be reset by the output of power-on-reset and Detector 2 (through one shot pulse
generator), while TFF is in the reset state Regulator 1, Regulator 2 and Regulator 3 are dis-
abled.
one shot pulse generator operation
Input
Output
100µs
47
RV5VE0×××
Application for Cellular Phones (RV5VE0×××)
R1
IBC1
VDD
16
7
6
Tr
Regulator
2
ROUT1
Transmitter
Unit
T
Q
R
C1
R2
Mechanical
Switch
IBC2
9
Tr
Regulator
2
ROUT2
Receiver/Audio
Unit
R6
10
11
C2
R5
C6
Toggle Input
I Shot
Pulse
Generator
ROUT3
Regulator
3
Memory/Logic
Unit
15
CSW1
C3
Level
Shift
12
C5
SBD
ROUT4
RESET INT
R
egulator
4
1
Vcc
CSW2
CPU
Level
Shift
13
C4
I/O
I/O
VSEN1
DOUT
14
R4
CD
Detector
1
3
8
5
2
CD
VSEN2
RESET
R3
GND
Detector
2
4
C1,2,5=10µF/C3,4=0.1µF/C6=1µF/CD=0.1µF
R1,2,3,4=100kΩ/R5=10kΩ/R6=47Ω
Tr: 2SB799(NEC PNP type,hFE=100 to 200)
SBD: MA717(Panasonic)
48
相关型号：
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