RS5C317B-E2 [RICOH]
Real Time Clock, Volatile, 0 Timer(s), CMOS, PDSO14, 0.65 MM PITCH, SSOP-14;
| 型号： | RS5C317B-E2 |
| 厂家： | 
RICOH ELECTRONICS DEVICES DIVISION |
| 描述： | Real Time Clock, Volatile, 0 Timer(s), CMOS, PDSO14, 0.65 MM PITCH, SSOP-14 时钟 光电二极管 外围集成电路 |
| 文件： | 总40页 (文件大小：382K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ULTRA-COMPACT
HIGH PERFORMANCE
SERIAL REAL TIME CLOCK
RS5C317A/B
APPLICATION MANUAL
ELECTRONIC DEVICES DIVISION
NO.EA-036-9803
NOTICE
1. The products and the product specifications described in this application manual are subject to change or dis-
continuation of production without notice for reasons such as improvement. Therefore, before deciding to use
the products, please refer to Ricoh sales representatives for the latest information thereon.
2. This application manual may not be copied or otherwise reproduced in whole or in part without prior written con-
sent of Ricoh.
3. Please be sure to take any necessary formalities under relevant laws or regulations before exporting or other-
wise taking out of your country the products or the technical information described herein.
4. The technical information described in this application manual shows typical characteristics of and example
application circuits for the products. The release of such information is not to be construed as a warranty of or a
grant of license under Ricoh's or any third party's intellectual property rights or any other rights.
5. The products listed in this document are intended and designed for use as general electronic components in
standard applications (office equipment, computer equipment, measuring instruments, consumer electronic
products, amusement equipment etc.). Those customers intending to use a product in an application requiring
extreme quality and reliability, for example, in a highly specific application where the failure or misoperation of
the product could result in human injury or death (aircraft, spacevehicle, nuclear reactor control system, traffic
control system, automotive and transportation equipment, combustion equipment, safety devices, life support
system etc.) should first contact us.
6. We are making our continuous effort to improve the quality and reliability of our products, but semiconductor
products are likely to fail with certain probability. In order prevent any injury to persons or damages to property
resulting from such failure, customers should be careful enough to incorporate safety measures in their design,
such as redundancy feature, fire-containment feature and fail-safe feature. We do not assume any liability or
responsibility for any loss or damage arising from misuse or inappropriate use of the products.
7. Anti-radiation design is not implemented in the products described in this application manual.
8. Please contact Ricoh sales representatives should you have any questions or comments concerning the prod-
ucts or the technical information.
June 1995
RS5C317A/B
APPLICATION MANUAL
CONTENTS
......................................................................................................
OUTLINE
1
....................................................................................................
FEATURES
1
.......................................................................................
BLOCK DIAGRAMS
2
.............................................................................................
.......................................................................................
2
APPLICATIONS
2
SELECTION GUIDE
...................................................................................
PIN CONFIGURATION
2
......................................................................................
PIN DESCRIPTIONS
3
...................................................................
ABSOLUTE MAXIMUM RATINGS
4
.................................................
RECOMMENDED OPERATING CONDITIONS
4
................................................................................
................................................................................
DC CHARACTERISTICS
AC CHARACTERISTICS
5
5
.............................................................................................
TIMING CHART
6
.........................................................................
FUNCTIONAL DESCRIPTION
7
1. Addressing.................................................................................................
2. Registers...................................................................................................
7
8
3. Counters..................................................................................................
14
16
16
17
18
19
20
21
22
23
23
................................................................................................
OPERATION
1. Read Data (For the RS5C317A) ......................................................................
2. Write Data (For the RS5C317A).......................................................................
3. Read Data (For the RS5C317B) ......................................................................
4. Write Data (For the RS5C317B).......................................................................
5. CE Pin ....................................................................................................
6. Configuration of Oscillating Circuit ....................................................................
7. Oscillator Halt Sensing .................................................................................
8. Typical Power Supply Circuit...........................................................................
9. Oscillation Frequency Adjustment.....................................................................
10. Interrupt Operation ....................................................................................
11. Timer ....................................................................................................
12. 32kHz Clock Output ...................................................................................
13. Typical Application .....................................................................................
14. Typical Characteristic Measurements ...............................................................
15. Typical Software-based Operations .................................................................
25
27
27
28
29
31
35
35
................................................................................
PACKAGE DIMENSION
..............................................................................
TAPING SPECIFICATION
ULTRA-COMPACT HIGH PERFORMANCE
SERIAL REAL TIME CLOCK
RS5C317A/B
OUTLINE
The RS5C317A/B is a CMOS type real-time clock which is connected to the CPU via three signal lines and capa-
ble of serial transmission of clock and calendar data to the CPU.
The RS5C317A/B can generate various periodic interrupt clock pulses lasting for long period (one month), further
alarm interrupt can be made by days of the week, hours, and minutes. The function of 32kHz clock output and timer
counter for watch-dog-timer are also include. Driving an oscillation circuit at constant voltage, the circuit undergoes
few voltage fluctuations and consequently realizes low current consumption (0.6µA at 3V). It also provides an oscil-
lator halt sensing function for application to data validity at power-on and other occasions. Integrated into a compact
and thin 14pin SSOP (0.65mm pitch), the RS5C317A/B is the optimum choice for equipment requiring small size
and low power consumption.
The RS5C317A and the RS5C317B reads/writes data at falling and rising edge of serial clock respectively.
FEATURES
• Time keeping voltage 1.6V to 6.0V
• Lowest supply current 0.6µA TYP. (1.5µA MAX.) at 3V
• Connection to the CPU via only three pins: CE, SCLK/SCLK and SIO for addressing and data read/write
• A clock counter (counting hours, minutes, and seconds) and a calendar counter (counting leap years, years,
months, days, and days of the week) in BCD code
• Periodic interrupt pulses to the CPU with cycles ranging from one month to 1/1024Hz, with interrupt flags and
interrupt halt
• Alarm interrupt (days of the week, hours, minutes)
• Counter for timer with internal clock
• Oscillator halt sensing to judge internal data validity
• 32kHz clock output with enable switch
• Second digit adjustment by 30 seconds
• 12-hour or 24-hour time display selectable
• Automatic leap year recognition up to the year 2099
• CMOS logic
• Package: 14pin SSOP (0.65mm pitch)
1
RS5C317A/B
BLOCK DIAGRAMS
ALARM REGISTER
(WEEK,MIN,HOUR)
CLKC
32KHz OUTPUT
CONTROL
COMPARATOR
32KOUT
TMOUT
TIME COUNTER
(SEC,MIN,HOUR,WEEK,DAY,MONTH,YEAR)
OSCIN
OSCOUT
OSC
DIV
SCLK/SCLK*
SIO
OSC
DETECT
ADDRESS
DECODER
ADDRESS
REGISTER
ALRM
INTR
I/O
CONTROL
INTERRUPT
CONTROL
CE
SHIFT REGISTER
)
RS5C317A: SCLK RS5C317B: SCLK
*
APPLICATIONS
• Communication equipment (Multi-function telephone, portable telephone, PHS, pager)
• Business machine (Facsimile, portable facsimile)
• Personal computer (Desktop type, notebook type, word processor, PDA, electronic notebook, TV games)
• Audio visual equipment (Portable audio equipment, video camera, camera, digital camera, remote control equip-
ment)
• Home use (Rice cooker, microwave range)
SELECTION GUIDE
Taping type can be designated as follows:
Part Number RS5C317A-´´, RS5C317B-´´
´´: Designation of taping type E1 or E2 (The standard taping type is type E2.)
PIN CONFIGURATION
• 14pin SSOP (0.65mm pitch)
RS5C317A
RS5C317B
CE
CE
1
14
13
12
11
10
9
VDD
1
14
13
12
11
10
9
VDD
2
3
4
5
6
7
2
3
4
5
6
7
SCLK
SIO
32KOUT
NC
SCLK
SIO
32KOUT
NC
CLKC
ALRM
OSCIN
OSCOUT
CLKC
ALRM
OSCIN
OSCOUT
TMOUT
VSS
NC
TMOUT
VSS
NC
INTR
INTR
8
8
2
RS5C317A/B
PIN DESCRIPTIONS
Symbol
Name
Description
Pin No.
The CE pin is used to interface the CPU and is accessible when held at the high
level. This pin is connected to a pull-down resistor. It should be switched to the
low level or opened when not accessed or when powering off the system. Holding
the CE pin high for more than 2.5 seconds forces 1Hz interrupt pulses to be output
from the INTR pin for oscillation frequency measurement. (No “1Hz pulse” is out-
put for less than 1.5 seconds.)
CE
Chip enable input
1
SCLK
This pin is used to input shift clock pulses to synchronize data input to, and output
from, the SIO pin. SCLK and SCLK are for writing data at falling and rising edge of
clock pulses respectively and also reading data at rising and falling edge of clock
pulses respectively.
(A type)
Shift clock input
2
3
SCLK
(B type)
The SIO pin inputs and outputs written or read data in synchronization with shift
clock pulses from the SCLK/SCLK pin. The SIO pin causes high impedance when
SIO
Serial input/output CE pin is held at the low level (CMOS input/output). After the CE pin is switched
to the high level and the control bits and the address bits are input from the SIO,
the SIO pin performs serial input and output operations.
The INTR pin outputs periodic interrupt pulses and alarm interrupt to the CPU.
INTR
Interrupt output
Alarm output
This pin functions as an Nch open drain output even when the CE pin is held at the
low level.
8
5
The ALRM pin outputs alarm interrupt to the CPU. This pin functions as an Nch
open drain output even when the CE pin is held at the low level.
ALRM
TMOUT pin outputs timer counter output pulses for watch-dog-timer and free-run-
timer. This pin functions as an Nch open drain output even when the CE pin is
held at the low level. Timer function is disabled and TMOUT is OFF state when
the RS5C317 is in the oscillation halt sensing state.
TMOUT Timer output
6
These pins configure an oscillator circuit by connecting a 32.768kHz crystal oscilla-
tor between the OSCIN and OSCOUT pins and by connecting a capacitor between
the OSCIN and Vss pins. (Any other oscillator circuit components are built into
the RS5C317A/B.)
OSCIN Oscillator circuit
OSCOUT input/output
11
10
32kHz clock output pin for peripheral circuit.
The 32kHz clock output is controlled by CLKC pin and 32kHz control register.
The 32KOUT pin outputs 32kHz clock when the CLKC pin is held at high and
CLEN=0, and this pin is held at high impedance state when the CLKC pin and
CLEN is in any other states and even when the CLKC pin is open. CMOS output.
32KOUT 32kHz output
13
4
Control input for
CLKC
Control pin for an output of the 32KOUT pin. This pin incorporates a pull-down-
resistor.
32kHz output
VDD
VSS
Positive/Negative
power supply input
14
7
VDD and VSS is connected to power supply and ground respectively.
Ordinarily connected to VSS pin.
NC
No Connection
9, 12
3
RS5C317A/B
ABSOLUTE MAXIMUM RATINGS
(VSS=0V)
Symbol
VDD
VI
Item
Supply voltage
Conditions
Ratings
–0.3 to +7.0
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to +12
300
Unit
V
Input voltage
V
VO1
Output voltage 1
Output voltage 2
Power dissipation
Operating temperature
Storage temperature
SIO, 32KOUT
INTR, ALRM, TMOUT
Topt=25°C
V
VO2
V
PD
mW
˚C
˚C
Topt
Tstg
–40 to +85
–55 to +125
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum ratings are threshold limit values that must not be exceeded even for an instant under
any conditions. Moreover, such values for any two items must not be reached simultaneously. Operation
above these absolute maximum ratings may cause degradation or permanent damage to the device. These
are stress ratings only and do not necessarily imply functional operation below these limits.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V, Topt=–40 to +85˚C)
Symbol
VDD
Item
Supply voltage
Conditions
MIN.
2.5
TYP.
MAX.
6.0
Unit
V
VCLK
fXT
Time keeping voltage
Oscillation frequency
External oscillation capacitance
Pull-up voltage
1.6
6.0
V
32.768
10
kHz
pF
V
CG
CL value of crystal=6 to 8pF
INTR, ALRM, TMOUT
5
24
10
VPUP
4
RS5C317A/B
DC CHARACTERISTICS
Unless otherwise specified: VSS=0V, VDD=3V, Topt=–40 to +85˚C, Oscillation frequency=32.768kHz,(CL=6pF, R1=30k½), CG=10pF
Symbol
Item
Pin name
Conditions
MIN.
TYP.
MAX.
Unit
CE, SCLK/SCLK,
SIO, CLKC
VIH
“H” input voltage
0.8VDD
VDD
V
CE, SCLK/SCLK,
SIO, CLKC
VIL
“L” input voltage
“H” output current
“L” output current
0
0.2VDD
–0.5
V
IOH
IOL1
IOL2
RDN
IIH
SIO, 32KOUT
SIO, 32KOUT
INTR, ALARM, TMOUT
CE
VOH=VDD –0.5V
VOL1=0.5V
mA
mA
0.5
1
VOL2=0.4V
Pull-down resistance
Input current
45
150
1
450
5
k½
µA
µA
CLKC
VIH=3V
IILK
IOZ1
IOZ2
Input leakage current SCLK/SCLK
VI=VDD or VSS
VO=VDD or VSS
–1
–2
–5
1
SIO, 32KOUT
2
µA
µA
Output leakage current
INTR, ALARM, TMOUT
VO=10V
VDD=3V
5
0.6
1.5
2.0
IDD1
Standby current 1
Standby current 2
VDD
Input/output: open
VDD=6V
IDD2
CD
VDD
0.8
10
µA
pF
Input/output: open
Internal oscillation Cap. OSCOUT
AC CHARACTERISTICS
(VSS=0V, Topt=–40 to +85˚C, CL=50pF)
VDD³4.5V
MIN. MAX.
VDD³4.0V
VDD³2.5V
Symbol
Item
CE set-up time
Unit
MIN.
MAX.
MIN.
MAX.
tCES
tCEH
tCR
175
175
350
350
175
175
60
200
400
ns
ns
ns
ns
ns
ns
ns
CE hold time
200
400
400
200
200
80
400
800
800
400
400
120
CE inactive time
SCLK clock cycle time
SCLK high time
SCLK low time
tSCK
tCKH
tCKL
tCKS
SCLK to CE set-up time
Data output start time (from rising
of SCLK) (from falling of SCLK)
Data output delay time (from rising
of SCLK) (from falling of SCLK)
tRE
tRR
120
135
300
ns
ns
120
120
135
135
300
300
tRZ
tDS
tDH
Output floating time
Input data set-up time
Input data hold time
ns
ns
ns
50
50
60
50
120
80
5
RS5C317A/B
TIMING CHART
Input/output conditions: VIH=0.8´VDD, VIL=0.2´VDD, VOH=0.8´VDD, VOL=0.2´VDD
)
Any SCLK/SCLK state is allowed in the hatched area.
*
• RS5C317A
CE
tCES
tSCK
tCEH
tRZ
tCKS
tCR
SCLK
tCKL
tCKH
tRR
tRE
Read Data
Read cycle
Write cycle
SIO
SIO
tDS
tDH
Write Data
• RS5C317B
CE
tCES
tSCK
tCEH
tCKS
tCR
SCLK
tCKL
tCKH
tRR
tRE
tRZ
Read Data
Read cycle
Write cycle
SIO
SIO
tDS
tDH
Write Data
6
RS5C317A/B
FUNCTIONAL DESCRIPTION
1. Addressing
Address
Data *1
Registers
A3
A2
A1
A0
D3
D2
D1
D0
1-second counter
(BANK=0)
(BANK=1)
(BANK=0)
(BANK=1)
(BANK=0)
(BANK=1)
(BANK=0)
(BANK=1)
(BANK=0)
(BANK=1)
(BANK=0)
(BANK=1)
(BANK=0)
(BANK=0, 1)
(BANK=0)
(BANK=0)
(BANK=1)
(BANK=0)
(BANK=1)
(BANK=0)
(BANK=0)
(BANK=0)
(BANK=0, 1)
(BANK=0, 1)
S8
S4
S2
S1
0
1
2
3
4
5
0
0
0
0
Day-of-the-week alarm register 1
10-second counter
Day-of-the-week alarm register 2
1-minute counter
AW3
—*2
ALC
M8
AW2
S40
AW1
S20
AW0
S10
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
AW6
M4
AW5
M2
AW4
M1
1-minute alarm register
10-minute counter
10-minute alarm register
1-hour counter
AM8
—
AM4
M40
AM40
H4
AM2
M20
AM20
H2
AM1
M10
—
AM10
H1
H8
1-hour alarm register
10-hour counter
AH8
—
AH4
—
AH2
AH1
P/A, H20
H10
10-hour alarm register
Day-of-the-week counter
Interrupt cycle register
1-day counter
ALE
—
—
AP/A, AH20
W2
AH10
W1
6
7
8
0
0
1
1
1
0
1
1
0
0
1
0
W4
CT3
D8
CT2
D4
CT1
D2
CT0
D1
10-day counter
—
—
D20
D10
9
1
1
0
0
0
1
1
0
Timer register *7
TM3
MO8
—
TM2
MO4
—
TM1
MO2
—
TMCL
MO1
CLEN *8
MO10
Y1
1-month counter
A
32kHz control register *7
10-month counter
B
C
D
E
F
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
—
—
—
1-year counter
Y8
Y4
Y2
10-year counter
Y80
Y40
Y20
Y10
6
4
*
*
Control register 1
CTFG
12/24
ALFG
TMR
ADJ/BSY*3
TEST *6
WTEN/XSTP
Control register 2
BANK *5
1) All the listed data can be read and written.
*
2) The “—” mark indicates data which can be read only and set to “0” when read.
*
*
*
*
3) The ADJ/BSY bit of the control register is set to ADJ for write operation and BSY for read operation.
4) The WTEN/XSTP bit of the control register is set to WTEN for write operation and XSTP for read operation.
5) The clock/calendar counter and the alarm register can be selected when the BANK=0 and BANK=1 respectively. To designate the BANK is unnec-
essary for Interrupt cycle register and Control register 1/2.
6) The WTEN bit and TEST bit are set to “1” when CE is “Low”.
*
*
7) When the crystal oscillator is stopped after initial power-on or supply voltage drop, XSTP=1, the timer register and CLEN bit of the 32kHz control reg-
ister perform as follows:
CLEN=0
TM3=TM2=TM1=TMCL=0 (Timer halts)
8) The CLEN data can be read only and set to 0 when CLKC is “L”.
*
7
RS5C317A/B
2. Registers
2.1 Control Register 1 (at Eh)
D3
D2
D1
D0
CTFG
CTFG
ALFG
ALFG
WTEN
XSTP
ADJ
BSY
(For write operation)
(For read operation)
±30-second Adjustment Bit
ADJ
Description
0
1
Ordinary operation
Second digit adjustment
Clock/Counter Busy-state Indication Bit
BSY
Description
0
1
Ordinary operation
Second digit carry or adjustment
Clock Counter Enable/Disable Setting Bit
WTEN
Description
0
1
Disabling of 1-second digit carry for clock counter
Enabling of 1-second digit carry for clock counter
Oscillator Halt Sensing Bit
XSTP
Description
0
1
Ordinary oscillation
Oscillator halt sensing
Alarm Flag Bit
ALFG
Description
0
1
Unmatched alarm register with clock counter
Matched alarm register with clock counter
Interrupt Flag Bit
CTFG
Description
0
1
INTR=OFF enabling of write operation when CT3 bit is set to 1
INTR=L enabling of write operation when CT3 bit is set to 1
2.1-1 (ADJ)
The following operations are performed by setting the ADJ bit to 1.
After this bit is set to 1, the BSY bit is set to 1 for the maximum duration of 122.1µs.
If the WTEN bit is 0, these adjustment operations are started after the WTEN bit is set to 1.
1) For second digits ranging from “00” to “29” seconds:
Time counters smaller than seconds are reset and second digits are set to “00”.
2) For second digits ranging from “30” to “59” seconds:
Time counters smaller than seconds are reset and second digits are set to “00”. Minute digits are incremented by 1.
8
RS5C317A/B
2.1-2 (BSY)
When the BSY bit is 1, the clock and calendar counter are being updated. Consequently, write operation should
be performed for the counters when the BSY bit is 0. Meanwhile, read operation is normally performed for the
counters when the BSY bit is 0, but can be performed without checking the BSY bit as long as appropriate software
is provided for preventing read errors. (Refer to 15. Typical Software-based Operations.) The BSY bit is set to 1 in
the following three cases:
MAX.122.1µs
(I) Adjustment of second digits
by ±30 seconds
Setting of the
ADJ bit to 1
Completion of second
digit adjustment
MAX.91.6 µs
(II) Second digits increment by 1
(Subject to 1-sec digit carry when
the WTEN bit is switched from 0 to 1)
Setting of the End of second digit
WTEN bit to 1 increment by 1
91.6 µs
End of second digit carry pulse
(III) Ordinary 1-sec digit carry
2.1-3 (WTEN)
The WTEN bit should be set to 0 to check that the BSY bit is 0 when performing read and write operations for
the clock and calendar counters. For read operation, the WTEN bit may be left as 1 without checking the BSY bit as
long as appropriate measures such as read repetition are provided for preventing read errors. The WTEN bit
should be set to 1 after completing read and write operations, or will automatically be set to 1 by switching the CE
pin to the low level. If 1-second digit carry occurs when the WTEN bit is 0, a second digit increment by 1 occurs
when the WTEN bit is set to 1. There may be a possibility causing a time delay when it takes 1/1024 second or
more to set WTEN bit from 0 to 1, Read data in state of WTEN=1 in such a case. (Refer to the item 15.3)
2.1-4 (XSTP)
The XSTP bit senses the oscillator halt. When the CE pin is held at the low level, the XSTP bit is set to 1 once
the crystal oscillator is stopped after initial power-on or supply voltage drop and left to be 1 after it is restarted.
When the CE pin is held at the high level, the XSTP bit is left as it was when the CE pin was held at the low level
without checking oscillation stop. As such, the XSTP bit can be used to validate clock and calendar count data after
power-on or supply voltage drop. The XSTP bit is set to 0 when any data is written to the control register 1 (at Eh)
with ordinary oscillation.
2.1-5 (ALFG)
The ALFG bit can be set to 1 when the ALE bit set to 1 with alarm interruption (INTR=L).
ALFG
INTR
Matched alarm Matched alarm
register register
ALFG is written to 0 Matched alarm
register
9
RS5C317A/B
2.1-6 (CTFG)
The CTFG bit is set to 1 when interrupt pulses are output from the INTR pin held at the low level. There are two
interrupt modes selectable: the pulse mode (when the CT3 bit is set to 0) and the level mode (when the CT3 bit is set
to 1). The CTFG bit can be set only when the CT3 is set to 1. Setting the CTFG bit to 1 switches the INTR pin to the
low level while setting the CTFG bit to 0 turns off the INTR pin.
Interrupt cycle register
INTR output
Description
CT3
0
CT2
CT1
0
CT0
0
1
*
OFF
ON
Interrupt halt
*
*
*
0
0
1
Fixing the INTR pin at low level
Cycle: 0.977ms (1/1024Hz) Duty 50% *2
Cycle: 0.5s (1/2Hz) *3
0
1
0
0.977ms
0.5s
0
1
1
*
1
0
0
0
1s
Every second *4
Every 10 seconds *4
1
1
1
0
0
0
0
1
1
1
0
1
10s
(For display of second digits: 00, 10, 20, 30, 40 and 50)
Every minute (00 second) *4
1 minute
10 minutes
Every 10 minutes (00 second) *4
(For display of minute digits: 00, 10, 20, 30, 40 and 50)
Every hour (00 minute and 00 second) *4
Every day (0 hour, 00 minute and 00 second a.m.) *4
Every week *4
1
1
1
1
0
0
0
1
1 hour
1 day
1
1
1
1
1
1
0
1
1 week
(0 week, 0 hour, 00 minute and 00 second a.m.)
Every month *4
1 month
(1 day, 0 hour, 00 minute and 00 second a.m.)
1) The symbol “ ” in the above table indicates 0 or 1.
*
*
*
2)
0.977ms
CTFG
INTR
0.5s
3)
*
CTFG
INTR
0.488ms
CTFG
INTR
4)
*
Interrupt
Interrupt
Setting CTFG bit to 0
(Second count-up)(Second count-up)
10
RS5C317A/B
2.2 Control Register 2 (at Fh)
D3
D2
D1
D0
12/24
12/24
TMR
TMR
BANK
BANK
TEST
TEST
(For write operation)
(For read operation)
1
Bit for Testing
*
TEST
Description
Description
Description
0
1
Testing mode
Ordinary operation mode
2
Bank Selection Bit
*
BANK
0
1
Clock/calendar counter
Alarm register
3
Reset Bit for Timer Counter
*
TMR
0
1
Continuos timer operation
Resume timer operation after reset
4
12/24-hour Time Display System Selection Bit
*
12/24
Description
0
1
12-hour time display system (separate for mornings and afternoons)
24-hour time display system
1) (TEST) Set the TEST bit to 1 in ordinary operation. TEST bit is set automatically to 1 when the CE pin is “L”.
2) (BANK) There is no need to designate BANK bit for Interrupt cycle register and Control register 1/2.
*
*
*
*
3) (TMR)
The period for timer output is set in the “Timer register”.
4) (12/24) The 12/24 bit specifies time digit display in BCD code.
24-hour time display system 12-hour time display system 24-hour time display system 12-hour time display system
00
01
02
03
04
05
06
07
08
09
10
11
12 (AM12)
01 (AM 1)
02 (AM 2)
03 (AM 3)
04 (AM 4)
05 (AM 5)
06 (AM 6)
07 (AM 7)
08 (AM 8)
09 (AM 9)
10 (AM10)
11 (AM11)
12
13
14
15
16
17
18
19
20
21
22
23
32 (PM12)
21 (PM 1)
22 (PM 2)
23 (PM 3)
24 (PM 4)
25 (PM 5)
26 (PM 6)
27 (PM 7)
28 (PM 8)
29 (PM 9)
30 (PM10)
31 (PM11)
Either the 12-hour or 24-hour time display system should be selected before time setting.
11
RS5C317A/B
2.3 Interrupt cycle Register (at 7h)
D3
CT3
CT3
D2
CT2
CT2
D1
CT1
CT1
D0
CT0
CT0
(For write operation)
(For read operation)
1
Bits for selecting the interrupt cycle and output mode at the INTR pin
*
1) (CT3 to CT0)
*
The CT3 to CT0 bits are used to select the interrupt cycle and output mode at the INTR pin. There are two interrupt modes selectable: the pulse
mode (when the CT3 bit is set to 0) and the level mode (when the CT3 bit is set to 1). The interrupt cycle and output mode at the INTR pin are shown
in detail in the section on the CTFG bit in “2.1 Control Register 1 (at Eh)”.
2.4 Alarm registers for day-of-the-week, 1-minute, 10-minute, 1-hour, 10-hour (BANK1, at 0h-5h)
D3
D2
AW2
AW6
AM4
AM40
AH4
D1
AW1
D0
AW3
ALC
AM8
AW0
AW4
AM1
AM10
AH1
(For read/write) day-of-the-week 1 (at0h)
(For read/write) day-of-the-week 2 (at1h)
(For read/write) 1-minute time digit (at2h)
(For read/write) 10-minute time digit (at3h)
AW5
AM2
AM20
AH2
*
AH8
(For read/write) 1-hour time digit
(at4h)
ALE
AP/A, AH20
AH10
(For read/write) 10-hour time digit (at5h)
*
1) The “ ” mark in the above table indicates data which are set to 0 for read cycle and not set for write cycle.
*
*
*
*
2) 10-hour time digit indicates AP/A and AH20 with 12-hour and 24-hour time system respectively.
3) Make sure set an actual time-data to the alarm registers when the alarm function is activated as any imaginary alarm-data will never be match with
the actual time.
4) The INTR pin can output matched alarm interruption when the ALC bit is set 0 and halt output when the ALC bit is set to 1.
5) The alarm function is disabled when the ALE bit is set 0 and is enables when the ALE bit is set 1.
6) Examples of setting alarm time
*
*
*
Day-of-the-week
12-hour system
1- 10-
12-hour system
1- 10- 1-
Sun. Mon. Tue. Wed. Thu. Fri. Sat. 10-
1-
10-
Setting alarm time
AW0 AW1 AW2 AW3 AW4 AW5 AW6 hour hour min min hour hour min min
AM 00:00 every day
AM 01:30 every day
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
2
1
1
0
3
5
0
0
9
0
0
1
0
1
1
0
3
5
0
0
9
AM 11: 59 every day
PM 00:00
0
1
1
1
1
1
0
3
2
0
0
1
2
0
0
on Monday through Friday
PM 01:30 on Sunday
PM 11:59 on Monday,
Wednesday, and Friday
1
0
0
1
0
0
0
1
0
0
0
1
0
0
2
3
1
1
3
5
0
9
1
2
3
3
3
5
0
9
7) Hour digits show “12” and “32” when the time is AM 00:00 and PM 00:00 respectively in the 12-hour system.
8) No alarm interruption is output when all the bit from AW0 through AW6 is set to 0.
*
*
*
9) Each of the AW0 through AW6 corresponds to the day-of-the-week counter such as (W4, W2, W1)=(0, 0, 0) through (1, 1, 0). Designation of day-of-
the-week and AW0 through AW6 in the above table is one example.
12
RS5C317A/B
2.5 Timer register (BANK 1, at 9h)
D3
D2
D1
D0
TM3
TM2
TM1
TMCL
(For read/write)
1
Clock Frequency Selection Bit for the Timer Counter
*
TMCL
Description
0
1
Clock frequency=512Hz (1.953ms)
Clock frequency=16Hz (62.5ms)
2
Period Selection Bit for the Timer Counter
*
Cycle time setting table for the time counter (The “ ” mark indicates 0 or 1.)
*
T1 (cycle time for
watch-dog-timer) *3
T2 (time between setting
TMR=1 and TMOUT output) *4
T3 (cycle time for
free-run timer) *5
TM3
TM2
TM1
TMCL
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
Timer halts
1.953ms
5.859ms
9.765ms
13.67ms
17.57ms
21.48ms
25.39ms
62.5ms
Timer halts
Timer halts
3.906ms
7.812ms
11.719ms
15.625ms
19.531ms
23.437ms
27.344ms
125ms
*
0
1.953 to 3.907ms
5.859 to 7.813ms
9.765 to 11.72ms
13.67 to 15.63ms
17.57 to 19.54ms
21.48 to 23.44ms
25.39 to 27.35ms
62.5 to 125ms
0
0
0
0
0
0
1
1
1
1
1
1
1
187.5ms
312.5ms
437.5ms
562.5ms
687.5ms
812.5ms
187.5 to 250ms
312.5 to 375ms
437.5 to 500ms
562.5 to 625ms
687.5 to 750ms
812.5 to 875ms
250ms
375ms
500ms
625ms
750ms
875ms
1) (TMCL)
*
“512Hz” and “16Hz” are selectively available. When the “XSTP” bit is set to 1, the “TMCL” bit is automatically set to 0. There may be possibility to be
ahead or behind of the clock counter at maximum of a halt of clock frequency (512Hz or 16Hz), when the “ADJ” bit is set to 1 in the control register-1.
2) (TM3-TM1)
*
When the “XSTP” bit is set to 1 the “TM3, TM2”, and “TM1” is automatically set to 0, the timer counter halts.
3) T1: The maximum disable time for timer output, TMOUT=L, after setting the “TMR” bit to 1.
4) T2: Time between timer output and setting the “TMR” bit to 1, or setting the timer register to any value.
5) T3: Timer output cycle time without setting “TMR” bit to 1, cycle time for free-run-timer.
*
*
*
13
RS5C317A/B
6) Timing diagram for TMOUT
*
MAX. T1
T2
T3
TMOUT
TMR¬1
TMR¬1
0.977ms
7) Writing operation to the timer register makes the timer counter to start operation with resetting.
*
2.6 32kHz control register (BANK 1, at Ah)
D3
D2
D1
D0
CLEN
(For read/write)
*
*
*
1) The “ ” mark indicates data which are set to 0 for read cycle and not set for write cycle.
*
*
*
2) (CLEN) control bit for 32kHz output
The CLEN bit is set to 0 when the XSTP=1. CLEN is not writable and set to 0 when CLKC pin level low/open.
3) 32KOUT condition
*
CLKC pin
CLEN bit
32KOUT output
High impedance
32kHz clock output
High impedance
L (open)
0 (prohibited to write)
H
H
0
1
3. Counters
3.1 Clock counter (BANK 0, at 0h-5h)
D3
S8
D2
S4
D1
S2
D0
S1
(For read/write) 1-second time digit
(For read/write) 10-second time digit
(For read/write) 1-minute time digit
(For read/write) 10-minute time digit
(For read/write) 1-hour time digit
(For read/write) 10-hour time digit
(at0h)
(at1h)
(at2h)
(at3h)
(at4h)
(at5h)
S40
M4
M40
H4
S20
S10
M1
M10
H1
*
M8
M2
M20
*
H8
H2
P/A or H20
H10
*
*
1) The “ ” mark indicates data which are set to 0 for read cycle and not set for write cycle.
*
*
*
*
2) Any carry to 1-second digits from the second counter is disabled when the WTEN bit (of the control register 1) is set to 0.
3) Time digit display (BCD code):
Second digits : Range from 00 to 59 and carried to minute digits when incremented from 59 to 00.
Minute digits : Range from 00 to 59 and carried to hour digits when incremented from 59 to 00.
Hour digits : Range as shown in the section on the 12/24 bit and carried to day and day-of-the-week digits when incremented from 11 p.m. to 12
a.m. or 23 to 00.
4) Any registered imaginary time should be replaced with actual time as carrying to such registered imaginary time digits from lower-order ones cause
the clock counter to malfunction.
*
14
RS5C317A/B
3.2 Day-of-the-week counter (BANK 0, at 6h)
D3
D2
W4
D1
W2
D0
W1
(For read/write) Day-of-the-week counter
*
1) The “ ” mark indicates data which are set to 0 for read cycle and not set for write cycle.
*
*
*
*
2) Day-of-the-week digits are incremented by 1 when carried to 1-day digits.
3) Day-of-the-week digits display (incremented in septimal notation):
(W4, W2, W1)=(000) ® (001) ® ····· ® (110) ® (000)
The relation between days of the week and day-of-the-week digits is user changeable (e.g. Sunday=000).
4) The (W4, W2, W1) should not be set to (111).
*
3.3 Calendar counter (BANK 0, at 8h-Dh)
D3
D8
D2
D4
D1
D2
D0
D1
(For read/write) 1-day calendar digit
(For read/write) 10-day calendar digit
(For read/write) 1-month calendar digit
(For read/write) 10-month calendar digit
(For read/write) 1-year calendar digit
(For read/write) 10-year calendar digit
(at8h)
(at9h)
(atAh)
(atBh)
(atCh)
(atDh)
D20
MO2
D10
MO1
MO10
Y1
*
MO8
*
MO4
*
Y8
*
Y4
*
Y2
Y80
Y40
Y20
Y10
1) The “ ” mark indicates data which are set to 0 for read cycle and not set for write cycle.
*
*
*
2) The automatic calendar function provides the following calendar digit displays in BCD code.
Day digits
:
Range from 1 to 31 (for January, March, May, July, August, October, and December).
Range from 1 to 30 (for April, June, September, and November).
Range from 1 to 29 (for February in leap years).
Range from 1 to 28 (for February in ordinary years).
Carried to month digits when cycled to 1.
Month digits : Range from 1 to 12 and carried to year digits when cycled to 1.
Year digits Range from 00 to 99 and counted as 00, 04, 08, ..., 92, and 96 in leap years.
:
3) Any registered imaginary time should be replaced with actual time as carrying to such registered imaginary time digits from lower-order ones cause
the clock counter to malfunction.
*
15
RS5C317A/B
OPERATION
1. Read Data (For the RS5C317A)
The real-time clock becomes accessible by switching the CE pin from the low level to high level to enable inter-
facing with the CPU and then inputting setting data (control bits and address bits) to the SIO pin in synchronization
with shift clock pulses from the SCLK pin. The input data are registered in synchronization with the falling edge of
the SCLK. When the data is read, the read cycle shall be set by control bits then registered data can be read out
from SIO pin in synchronization with the rising edge of the SCLK.
• Control bits
R/W: Establishes the read mode when set to 1, and the write mode when set to 0.
AD: Writes succeeding addressing bits (A3-A0) to the address register when set to 1 with the
DT bit set to 0 and performs no such write operation in any other case.
DT: Writes data bits to counter or register specified by the address register set just before
when set to 1 with the R/W and AD bits set equally to 0 and performs no such write oper-
ation in any other case.
• Address bits A3-A0: Inputs the bits MSB to LSB in the address table describing the functions.
1.1 Read Cycle Flow
1. The CE pin is switched from “L” to “H”.
2. Four control bits (with the first bit ignored) and four read address bits are input from the SIO pin. At this time,
control bits R/W and AD are set equally to 1 while a control bit DT is set to 0. (see the SCLK 1A-8A)
3. The SIO pin enters the output mode at the rising edge of the shift clock pulse 2B from the SCLK pin while the
four read bits (MSB ® LSB) at designated addresses are output at the rising edge of the shift clock pulse 5B.
(see the figure below)
4. Then, the SIO pin returns to the input mode at the rising edge of the shift clock pulse 1C. Afterwards control bits
and address bits are input at the shift clock pulses 1C in the same manner as at the shift clock pulse 1A.
5. At the end of read cycle, the CE pin is switched from “H” to “L” (after tCEH from the falling edge of the eighth
shift clock pulse from the SCLK pin). Following on read cycle, write operation can be performed by setting con-
trol bits in the write mode at the shift clock pulse 1C and later with the CE pin held at “H”.
CE
1A 2A 3A 4A 5A 6A 7A 8A 1B 2B 3B 4B 5B 6B 7B 8B 1C 2C 3C
SCLK
Writing to shift
register
Setting of SIO Shifting data
pin in output
mode
Setting of SIO
pin in input
mode
Input to
SIO pin
(Hi-z)
AD DT A3 A2 A1 A0
AD
R/W
R/W
*
*
Control bits
Address bits
Output
from SIO
pin
–
–
–
D3 D2 D1 D0
Read data
(Hi-z)
(Hi-z)
Setting of
control bits
Writing to address
register
(Internal processing)
)
In the above figure, the “ ” mark indicates arbitrary data; the “–” mark indicates unknown data.
*
*
The “ ” mark indicates data which are available when the SIO pin is held at “H”, “L”, or Hiz level.
The diagonally shaded area of the CE and the SCLK pins indicate “H” or “L”.
16
RS5C317A/B
2. Write Data (For the RS5C317A)
Writing data to the real-time clock requires inputting setting data (control bits, address bits and data bits) to the
SIO pin and then establishing the write mode by using a control bit R/W in the same manner as in read operation.
)
Control bits and address bits are described in the previous section on read cycle.
*
• Data bits
D3-D0: Inputs the data bits MSB to LSB in the addressing table describing the functions.
2.1 Write Cycle Flow
1. The CE pin is switched from “L” to “H”.
2. Four control bits (with the first bit ignored) and four write address bits are input from the SIO pin. At this time,
control bits R/W and DT are set equally to 0 while a control bit AD is set to 1. (see the SCLK 1A-8A)
3. Four control bits and four bits of data to be written are input in the descending order of their significance.
At this time, control bits R/W and AD are set equally to 0 while a control bit DT is set to 1. (see the clock 1B-8B)
4. When write cycle is continued, control bits and address bits are input at the shift clock pulse 1C and later in the
same manner as at the shift clock pulse 1A.
5. At the end of write operation, control bits R/W, AD, and DT are set equally to 0 (at the falling edge of shift clock
pulse 5A and later from the SCLK pin) or the CE pin is switched from “H” to “L” (after tCEH from the falling edge
of the eighth shift clock pulse from the SCLK pin). Following on write cycle, read operation can be performed by
setting control bits in the read mode at the shift clock pulse 1C and later with the CE pin held at “H”.
CE
1A 2A 3A 4A 5A 6A 7A 8A 1B 2B 3B 4B 5B 6B 7B 8B 1C 2C 3C
SCLK
Writing to shift
register
Input to
SIO pin
AD DT A3 A2 A1 A0
R/W AD DT D3 D2 D1 D0
Control bits Data bits
AD
R/W
R/W
*
*
*
*
Control bits
Address bits
Output
from
SIO pin
(Hiz)
(Hiz)
Setting of
control bits
Writing to address
register
Setting of
control bits
End of write
operation
(Internal processing)
)
In the above figure, the “ ” mark indicates arbitrary data; and the diagonally shaded area of CE and SCLK indicates “H” or “L”.
*
*
17
RS5C317A/B
3. Read Data (For the RS5C317B)
The real-time clock becomes accessible by switching the CE pin from the low level to high level to enable inter-
facing with the CPU and then inputting setting data (control bits and address bits) to the SIO pin in synchronization
with shift clock pulses from the SCLK pin. The input data are registered in synchronization with the rising edge of
the SCLK. When the data is read, the read cycle shall be set by control bits then registered data can be read out
from SIO pin in synchronization with the falling edge of the SCLK.
• Control bits
R/W: Establishes the read mode when set to 1, and the write mode when set to 0.
AD: Writes succeeding addressing bits (A3-A0) to the address register when set to 1 with the
DT bit set to 0 and performs no such write operation in any other case.
DT: Writes data bits to counter or register specified by the address register set just before
when set to 1 with the R/W and AD bits set equally to 0 and performs no such write oper-
ation in any other case.
• Address bits A3-A0: Inputs the bits MSB to LSB in the address table describing the functions.
3.1 Read Cycle Flow
1. The CE pin is switched from “L” to “H”.
2. Four control bits (with the first bit ignored) and four read address bits are input from the SIO pin. At this time,
control bits R/W and AD are set equally to 1 while a control bit DT is set to 0. (see the SCLK 1A-8A)
3. The SIO pin enters the output mode at the falling edge of the shift clock pulse 2B from the SCLK pin while the
four read bits (MSB ® LSB) at designated addresses are output at the falling edge of the shift clock pulse 5B.
(see the figure below)
4. Then, the SIO pin returns to the input mode at the falling edge of the shift clock pulse 1C. Afterwards control
bits and address bits are input at the shift clock pulses 1C in the same manner as at the shift clock pulse 1A.
5. At the end of read cycle, the CE pin is switched from “H” to “L” (after tCEH from the rising edge of the eighth
shift clock pulse from the SCLK pin). Following on read cycle, write operation can be performed by setting con-
trol bits in the write mode at the shift clock pulse 1C and later with the CE pin held at “H”.
CE
1A 2A 3A 4A 5A 6A 7A 8A 1B 2B 3B 4B 5B 6B 7B 8B 1C 2C 3C
SCLK
Writing to shift
register
Setting of SIO Shifting data
pin in output
mode
Setting of SIO
pin in input
mode
Input to
SIO pin
(Hi-z)
AD DT A3 A2 A1 A0
AD
R/W
R/W
*
*
Control bits
Address bits
Output
from SIO
pin
–
–
–
D3 D2 D1 D0
Read data
(Hi-z)
(Hi-z)
Setting of
control bits
Writing to address
register
(Internal processing)
)
In the above figure, the “ ” mark indicates arbitrary data; the “–” mark indicates unknown data.
*
*
The “ ” mark indicates data which are available when the SIO pin is held at “H”, “L”, or Hiz level.
The diagonally shaded area of the CE and the SCLK pins indicate “H” or “L”.
18
RS5C317A/B
4. Write Data (For the RS5C317B)
Writing data to the real-time clock requires inputting setting data (control bits, address bits and data bits) to the
SIO pin and then establishing the write mode by using a control bit R/W in the same manner as in read operation.
)
Control bits and address bits are described in the previous section on read cycle.
*
• Data bits
D3-D0: Inputs the data bits MSB to LSB in the addressing table describing the functions
4.1 Write Cycle Flow
1. The CE pin is switched from “L” to “H”.
2. Four control bits (with the first bit ignored) and four write address bits are input from the SIO pin. At this time,
control bits R/W and DT are set equally to 0 while a control bit AD is set to 1. (see the SCLK 1A-8A)
3. Four control bits and four bits of data to be written are input in the descending order of their significance.
At this time, control bits R/W and AD are set equally to 0 while a control bit DT is set to 1. (see the SCLK 1B-8B)
4. When write cycle is continued, control bits and address bits are input at the shift clock pulse 1C and later in the
same manner as at the shift clock pulse 1A.
5. At the end of write operation, control bits R/W, AD, and DT are set equally to 0 (at the rising edge of shift clock
pulse 5A and later from the SCLK pin) or the CE pin is switched from “H” to “L” (after tCEH from the rising edge
of the eighth shift clock pulse from the SCLK pin). Following on write cycle, read operation can be performed by
setting control bits in the read mode at the shift clock pulse 1C and later with the CE pin held at “H”.
CE
1A 2A 3A 4A 5A 6A 7A 8A 1B 2B 3B 4B 5B 6B 7B 8B 1C 2C 3C
SCLK
Writing to shift
register
Input to
SIO pin
AD DT A3 A2 A1 A0
R/W AD DT D3 D2 D1 D0
Control bits Data bits
AD
R/W
R/W
*
*
*
*
Control bits
Address bits
Output
from SIO
pin
(Hiz)
(Hiz)
Setting of
control bits
Writing to address
register
Setting of
control bits
End of write
operation
(Internal process)
)
In the above figure, the “ ” mark indicates arbitrary data; and the diagonally shaded area of CE and SCLK indicates “H” or “L”.
*
*
19
RS5C317A/B
5. CE Pin
)
RS5C317A: SCLK
RS5C317B: SCLK
*
Shift clock pulses
SCLK/SCLK
SIO
*
Address Data
Write Data
Read Data
Read control bit
Control bit
CE
1) Switching the CE pin to the high level enables the SCLK/SCLK and SIO pins, allowing data to be serially read
from and written to the SIO pin in synchronization with shift clock pulses input from the SCLK/SCLK pin.
2) Switching the CE pin to the low level or opening disables the SCLK/SCLK and SIO pins, causing high imped-
ance and resetting the internal interfacing circuits such as the shift register. While data of the address register
and bank bit which have been written just before should be preserved.
3) The CE pin should be held at the low level or open state when no access is made to the RS5C317.
The CE pin incorporates a pull-down resistor.
4) During system power-down (being back-up battery powered), the low-level input of the CE pin should be brought
as close as possible to the VSS level to minimize the loss of charge in the battery.
5) Holding the CE pin at the high level for more than 2.5 seconds mainly forces 1Hz interrupt pulses to be output
from the INTR pin for oscillation frequency measurement. When the CE pin is held at the high level for less
than 1.5 seconds, no pulse is output.
6) The CE pin should be held at the low level in order to enable oscillator halt sensing. Holding the CE pin at the
high level, therefore, disables oscillator halt sensing, retaining the value of the XSTP (oscillator halt sensing) bit
which exists immediately before the CE pin is switched to the high level.
Considerations
When the power turns on from 0V, the CE pin should be set low or open once.
20
RS5C317A/B
6. Configuration of Oscillating Circuit
Typical external device:
X'tal : 32.768kHz
VDD
VDD
(R1=30k½ TYP.)
(CL=6pF to 8pF)
CG=8pF to 20pF
OSCIN
CG
32kHz
Typical values of internal devices
RF=15M½ (TYP.)
RF
RD
RD=60k½ (TYP.)
OSCOUT
CD=10pF (TYP.)
CD
VSS
A
)
The oscillation circuit is driven at a constant voltage of about 1.5V relative to the Vss level.
*
Consequently, it generates a wave form having a peak-to-peak amplitude of about 1.5V on the positive side of the Vss level.
Considerations in Mounting Components Surrounding Oscillating Circuit
1) Mount the crystal oscillators and CG in the closest possible position to the IC.
2) Avoid laying any signal or power line close to the oscillation circuit (particularly in the area marked with
“¬ A ®” in the above figure).
3) Apply the highest possible insulation resistance between the OSCIN or OSCOUT pin and the PCB.
4) Avoid using any long parallel line to wire the OSCIN or OSCOUT pin.
5) Take extreme care not to cause condensation, which leads to various problems such as oscillation halt.
Other Relevant Considerations
1) When applying an external input of clock pulses (32.768kHz) to the OSCIN pin:
DC coupling ............Prohibited due to mismatching input levels.
AC coupling.............Permissible except that unpredictable results may occur in oscillator halt sensing due
to possible sensing errors caused by noises, etc.
2) Avoid using the oscillator output of the RS5C317 (from the OSCOUT pin) to drive any other IC for the pur-
pose of ensuring stable oscillation.
21
RS5C317A/B
7. Oscillator Halt Sensing
Oscillation Halt can be sensed through monitoring the XSTP bit with preceding setting of the XSTP bit to 0 by
writing any data to the control register 1. Upon oscillator halt sensing, the XSTP bit is switched from 0 to 1. This
function can be applied to judge clock data validity.
When the XSTP bit is set to 1, the timer register bits and CLEN bit perform as follows:
CLEN=0
TM3=TM2=TM1=TMCL=0 (Timer halts)
XSTP
1
2
Power-on from 0V
Writing of data to
control register 1
Oscillation halt
Oscillation restart
*
*
(in the presence of oscillation)
1) While the CE pin is held at the low level, the XSTP bit is set to 1 upon power-on from 0V.
*
Note that any instantaneous power disconnection may cause operational failure. When the CE pin is held at the high level, oscillation halt is not
sensed and the value of the XSTP bit when the CE pin is held at the low level is retained.
2) Once oscillation halt has been sensed, the XSTP bit is held at 1 even if oscillation is restarted.
*
Considerations in Use of XSTP Bit
Ensure error-free oscillation halt sensing by preventing the following:
1) Instantaneous disconnection of VDD
2) Condensation on the crystal oscillator
3) Generation of noise on the PCB in the crystal oscillator
4) Application of voltage exceeding prescribed maximum ratings to the individual pins of the IC
22
RS5C317A/B
8. Typical Power Supply Circuit
1) Connect the capacitance of the oscillation circuit to the Vss pin.
2) Mount the high-and low-frequency by-pass capacitors in paral-
lel and very close to the RS5C317.
System
supply
voltage
RS5C317
3) Connect the pull-up resistor of the INTR pin to two different
positions depending on whether the resistor is in use during
battery back-up.
A
INTR
B
OSCIN
• When not in use during battery back-up
OSCOUT
VDD
...........Position A in the left figure
• When in use during battery back-up
...........Position B in the left figure
4) Timing of power-on, power-off and CE pin refer to following figure.
5) When a diode are in use in place of the components surround-
ed by dotted lines, note that applying voltage to any input pins
should be less than the rating of VDD +0.3V by using of schot-
tky diode.
VSS
System supply voltage
C
E
D
Battery voltage
VDD
CE
0V
0.2VDD 0.2VDD
0.2VDD
MIN. 0µs
MIN. 0µs
MIN. 0µs
C, D, E: Minimum operating voltage for CPU
9. Oscillation Frequency Adjustment
9.1 Oscillation Frequency Measurement
1) Switch the CE pin to the high level and use a frequen-
cy counter to measure a 1Hz interrupt pulse output
from the INTR pin about 2.5 seconds later.
+5V or +3V
VDD
32kHz
OSCIN
2) Ensure that the frequency counter has more than six
digits (on the order of 1 ppm).
CG
OSCOUT
3) Place the CG between the OSCIN pin and the VSS lev-
el and pull up the INTR pin output to the VDD.
Frequency
counter
INTR
CE
VSS
23
RS5C317A/B
9.2 Oscillation Frequency Adjustment
1
*
Select crystal oscillator
(For fixed capacitance)
Fix CG
(For variable capacitance)
3
*
Fix the capacitance of CG
Change CL
value of crystal
Change CL
value of crystal
2
3
*
*
Optimize central
variable capacitance value
Optimize CG
NO
NO
OK
OK
END
Make fine frequency adjustment
with variable capacitance.
END
1) To ensure that the crystal is matched to the IC, inquire its crystal supplier about its CL (load capacitance) and R1 (equivalent series resistance) values.
It is recommended that the crystal should have the CL value range of 6 to 8pF and the typical R1 value of 30k½.
*
*
2) To allow for the possible effects of floating capacitance, select the optimum capacitance of the CG on the mounted PCB. The standard and recom-
mendable capacitance values of the CG range from 5 to 24pF and 8 to 20pF, respectively. When you need to change the frequency to get higher
accuracy, change the CL value of the crystal.
3) Collate the central variable capacitance value of the CG with its oscillation frequency by adjusting the angle of rotation of the variable capacitance of
the CG in such a manner that the actual variable capacitance value is slightly smaller than the central variable capacitance value. (It is recommended
that the central variable capacitance value should be slightly less than one half of the actual variable capacitance value because the smaller is vari-
able capacitance, the greater are fluctuations in oscillation frequency.) In the case of an excessive deviation of the oscillation frequency from its
required value, change the CL value of the crystal.
*
After adjustment, oscillation frequency is subject to fluctuations of an ambient temperature and supply voltage. See
“14. Typical Characteristic Measurements”.
Note
Any rise or fall in ambient temperature from its reference value ranging from 20 to 25 degrees Celsius causes
a time delay for a 32kHz crystal oscillator. It is recommendable, therefore, to set slightly high oscillation fre-
quency at room temperature.
24
RS5C317A/B
10. Interrupt Operation
Two interrupt operations are available:
1) Alarm interrupt...........When a registered time for alarm (such as day-of-the-week, hour or minute) coincide with
calendar counter (such as day-of-the-week, hour or minute) interrupt to the CPU are
requested with INTR pin or ALRM pin being “L” (ON).
2) Periodic interrupt ......The INTR pin comes to a “L” (ON) state every registered period outputting interrupt
request.
Function diagram of alarm and periodic interrupts are shown as follows:
Alarm interrupt
INTR
ALRM
ALC
Periodic interrupt
1) Setting the ALC into 1 halt output of the alarm interrupt from INTR pin.
*
*
2) Both of alarm and periodic interrupt can operate regardless of the state of CE pin, “H” or “L”.
10.1 Alarm Interrupt
For setting an alarm time, designated time such as day-of the week, hour or minute should be set to the alarm
registers being ALE bit to 0. After that set the ALE bit to 1, from this moment onward when such registered alarm
time coincide with the value of calendar counter the ALRM comes down to Low (ON). The ALRM output can be
controlled by operating to the ALE and ALFG bits.
Alarm-calendar
coincident period
(1 min.)
MAX. 61.1µs
ALRM
ALE¬1
ALE¬1
ALE¬0 ALE¬1
ALE¬0
*
*
*
*
ALRM
ALFG¬0
1) The “ ” mark indicates the time when the registered alarm day-of-the-week and time coincide with calendar counter.
*
*
*
*
2) Above figure describes in case of no periodic interruption.
3) ALFG indicates a reverse state of ALRM output.
25
RS5C317A/B
10.2 Periodic (Clock) Interrupt
The INTR pin output, the interrupt cycle register, and the CTFG bit can be used to interrupt the CPU in a certain
cycle. The interrupt cycle register can be used to select either one of two interrupt output modes: the pulse mode
(when the CT3 bit is set to 0) and the level mode (when the CT3 bit is set to 1).
10.2-1 Interrupt Cycle Selection
Interrupt cycle register
INTR output
Description
CT3
0
CT2
CT1
0
CT0
0
1
*
OFF
ON
Interrupt halt
*
0
0
1
Fixing the INTR pin to the low level
Cycle: 0.977ms (1/1024Hz) Duty 50%
Cycle: 0.5s (1/2Hz)
*
*
*
0
1
0
0.977ms
0.5s
0
1
1
1
0
0
0
1s
Every second
Every 10 seconds
1
1
1
0
0
0
0
1
1
1
0
1
10s
(For display of second digits: 00, 10, 20, 30, 40 and 50)
Every minute (00 second)
1 min
10 min
Every 10 minutes
(For display of minute digits: 00, 10, 20, 30, 40 and 50)
Every hour (00 minute and 00 second)
Every day (0 hour, 00 minute and 00 second a.m.)
Every week (0 week, 0 hour, 00 minute and 00 second a.m.)
Every month (1st day, 0 hour, 00 minute and 00 second a.m.)
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
1 hour
1 day
1 week
1 month
1) The “ ” mark indicates 0 or 1.
*
*
10.2-2 Pulse mode Interrupt
When the CT3 bit is set to 0 and provides four interrupt cycles, off, on, 1024Hz, and 2Hz can be selected. The
CTFG bit cannot be set because it is used for output monitoring.
1024Hz : T1= 0.977ms
T1
2Hz
: T1= 500ms
CTFG
INTR
0.488ms
10.2-3 Level mode Interrupt
When the CT3 bit is set to 1, clock-interlocked cycles in increments of one second to one month can be selected.
The CTFG bit can be written; writing 1 to the CTFG bit switches the INTR pin to the low level while writing 0 to the
CTFG bit turns off the INTR pin.
CTFG
INTR
Interrupt
Interrupt
Writing 0 to CTFG bit
(Second count-up)(Second count-up)
26
RS5C317A/B
11. Timer
TMOUT outputs periodic pulses every registered time period (in BANK=1, at 9h). Setting TMR bit to 1 makes
the timer counter reset and possible to operate as a watch-dog-timer.
MAX. T1
T2
T3
TMOUT
TMR¬1
TMR¬1
0.977 ms
1) Timer counter is available when the CE pin is set 0.
*
*
2) Timer function is disabled when the XSTP bit is set to 1.
(TM3 to TM1 and TMCL of timer register become to 0)
3) Refer to “Timer register” in FUNCTON section regarding to T1, T2, and T3 in the above figure.
4) TMOUT will be OFF when the TMR bit is set to one with TMOUT=L (ON)
*
*
*
5) Write operation to the timer registers causes starting to operate of timer counter after resetting.
12. 32kHz Clock Output
Clock signal of 32kHz crystal oscillator can be output from the 32KOUT pin. When this function is disabled the
32KOUT pin is held at high impedance.
32kHz clock output can be controlled through CLKC pin and CLEN pin.
CLKC pin
CLEN bit
32KOUT output
High impedance
Output 32kHz clock
High impedance
L (open)
0 (disabled to write)
H
H
0
1
1) CLKC pin incorporates pulled down resistor.
*
*
2) The CLEN bit will be set to 0 when the XSTP bit is set to 1.
The conditions of the XSTP bit being set to 1 is as follows:
(I) Initial power-on
(II) Supply voltage drop
(III) Crystal oscillation halt
3) When CLKC pin is held at high level at initial power-on, 32kHz clock is output from the 32KOUT pin.
*
27
RS5C317A/B
13. Typical Application
System power supply
System power supply
CPU
VCC
RS5C317A/B
B
A
OSCIN
INTR
OSCOUT
ALRM
VDD
CE
System
power
supply
or
VDD
TMOUT
SCLK/SCLK
SIO
D
VSS
VSS
C
1) Connect the capacitance of the oscillation circuit to the VSS pin.
*
*
*
2) Mount the high-and low-frequency by-pass capacitors in parallel and very close to the RS5C317.
3) Connect the pull-up resistor of the INTR pin or ALRM pin to two different positions depending on whether the resistor is in use during battery back-up:
(I) When not in use during battery back-up.............Position A in the above figure
(II) When in use during battery back-up...................Position B in the above figure
4) When using a “D” circuit in place of “C”, note that forward voltage of diode should be minimized to eliminate applying excess voltage to input pins.
(Take the utmost care on system powering-ON and-OFF).
*
28
RS5C317A/B
14. Typical Characteristic Measurements
CG=10pF
VDD
CG
X'tal : R1=30k½
Topt=25˚C
VDD
OSCIN
Input Pin : VDD or VSS
Output Pin : Open
A
X'tal
OSCOUT
VSS
INTR
Frequency counter
14.1 Standby Current vs. CG
14.2 Standby Current vs. VDD
Topt = 25¡C
Topt = 25¡C
2.0
2.0
1.0
1.0
VDD = 5V
CG = 10pF
VDD = 3V
0.0
0.0
0
2
4
6
0
10
20
30
VDD (V)
CG (pF)
14.3 Operational Current vs. SCLK/SCLK Frequency 14.4 Standby Current vs. Temperature
CG = 10pF
Topt = 25¡C
2.0
1.0
0.0
1
0.1
VDD = 5V
VDD = 6V
0.01
VDD = 3V
VDD = 3V
0.001
–60 –40 –20
0
20 40 60 80 100
0.01
0.1
1
10
Temperature Topt (¡C)
SCLK/SCLK Frequency (MHz)
29
RS5C317A/B
14.5 Oscillation Frequency Deviation vs. CG
(f0: CG=10pF reference)
14.6 Oscillation Frequency Deviation vs. VDD
(f0: VDD=4V reference)
VDD = 3V, Topt = 25°C
80
CG = 10pF, Topt = 25¡C
1
60
40
0
–1
–2
20
0
–3
–4
–20
–40
0
5
10
15
20
25
30
0
1
2
3
4
5
6
CG (pF)
VDD (V)
14.7 Oscillation Frequency Deviation
14.8 Oscillation Start Time vs. VDD
vs. Temperature (f0: Topt=25°C reference)
VDD = 3V, CG = 10pF
10
Topt = 25¡C
1.0
0.5
0.0
0
–10
–20
–30
–40
–50
–60
CG = 20pF
–70
–80
–40 –20
CG = 10pF
0
20 40 60 80 100
0
1
2
3
4
5
6
Temperature Topt (°C)
VDD (V)
14.9 VDS vs. IDS for Nch Open Drain Output
14.10 IlH vs. VIH for CLKC pin
Topt = 25°C
Topt = 25¡C
10
8
50
40
6
4
2
0
30
VDD = 5V
VDD = 3V
20
10
0
0.0
0.5
1.0
1.5
2.0
0.0 1.0 2.0
3.0 4.0
5.0 6.0
VDS (V)
VIH = VDD (V)
30
RS5C317A/B
15. Typical Software-based Operations
15.1 Initialization upon Power-on
1) Switch the CE pin to the low level immediately after power-on.
*
Start
2) When not making oscillation halt sensing (data validity), the XSTP bit
need not be checked.
*
1
Power-on
*
*
*
YES
3) Turn off the INTR pin, whose output is uncertain at power-on.
2
3
XSTP=0?
NO
*
4) Set the ADJ bit to 1. When writing control register 1, if the oscillator has
operated, the XSTP bit is changed from 1 to 0.
*
Interrupt cycle register¬0h
Control register 2¬3h
(BANK¬1)
10-hour alarm register¬0h
(ALE¬0)
5) It takes about 0.1 to 2 seconds to be set the BSY bit to 0 from oscillation
starting upon power-on from 0V. Provide an exit from an oscillation start
loop to prepare for oscillation failure.
*
4
Control register 1¬3h
*
6) Set the XSTP bit to 0 by writing data to the control register 1, and set to
the control register 2,
*
NO
1h for the 12-hour time display system.
BSY=0?
5
*
9h for the 24-hour time display system.
6
YES
*
Wait or
other
operations.
When Using the XSTP Bit
Control register 2¬1h, 9h
Set clock and calendar
Ensure stable oscillation by preventing the following:
1) Condensation on the crystal oscillator
2) Instantaneous disconnection of power
3) Generation of clock noises, etc, in the crystal
oscillator
counters and interrupt cycles.
4) Charge of voltage exceeding prescribed maxi-
mum ratings to the individual pins of the IC
15.2 Write Operation to Clock and Calendar Counters
1) After switching the CE pin to the high level, hold it at the high level until
*
any subsequent operation requires switching it to the low level. (Note
that switching the CE pin to the low level sets the WTEN bit to 1.)
1
CE=H
*
2) WTEN bit is set to 0.
2
*
*
*
Control register 1¬0h
*
3) The BSY bit is held at 1 for a maximum duration of 122.1µs.
NO
BSY=0?
YES
4) Switch the CE pin to the low level to set the WTEN bit to 1. During write
operation to the clock and calendar counters, one 1-second digit carry
causes a 1-second increment while two 1-second digit carries also cause
only a 1-seconds increment, which, in turn, causes a time delay.
CE=L
Write to clock and
calendar counters.
3
*
Wait or
other
4
operations.
CE=L
*
31
RS5C317A/B
15.3 Read Operation from Clock and Calendar Counters
15.3-1
15.3-2
1
CE=H
*
5
*
Read 1-second
digit of clock counter.
2
Control register 1¬0h
*
Read from clock and
calendar counters.
NO
BSY=0?
YES
CE=L
5
5
*
Again read 1-second
digit of clock counter.
Read from clock and
calendar counters.
3
*
Wait or
other
operations.
4
CE=L
*
Two 1-second
digit readings
match?
NO
*
YES
Note
Read data as described in 15.3-2 or 15.3-3 when it takes (1/1024) sec or more to set the WTEN bit from 0 to 1
(CE=L), the read operation described in 15.3-1 is prohibited as such a case.
15.3-3
1) to 4) These notes are the same as 15.2 notes 1) to 4).
*
*
*
*
6
Interrupt to CPU
5) When needing any higher-order digits than the minute digits, replace
second digits with minute digits. (Reading LSD one of the required digits
twice.)
*
*
NO
CTFG=1?
YES
7
8
*
6) Select the level mode as an interrupt mode by setting the CT3 bit to 1.
7) Write 0 to CTFG bit for turning off INTR pin.
*
*
*
Control register 1¬2h
Interrupt
operation
from any
other IC
*
Read from clock and
calendar counters.
8) Complete read operation within an interrupt cycle after interrupt genera-
tion. (e.g. within 1 second)
32
RS5C317A/B
15.4 Write Operation to Alarm time
1) Non-existent alarm time can set in the alarm registers, but when it sets,
an alarm interrupt is disabled. To enable an alarm interrupt, existent
alarm time must be set in the alarm registers.
*
BANK¬1
Set alarm (hour or minute,
day-of the week)
1
*
ALE¬1
15.5 Second-digit Adjustment by ±30 seconds
1) Set the ADJ bit to 1.
*
1
(The BSY bit is held at 1 for a maximum duration of 122.1µs after the
ADJ bit is set to 1.)
Control register 1¬3h
*
15.6 Oscillation Start Judgment
1) The XSTP bit is set to 1 upon power-on from 0V.
*
2) It takes approximately 0.1 to 2 seconds to start oscillation. Provide an
exit from an oscillation start loop to prepare for oscillation failure.
*
Power-on
2
*
1
When Using the XSTP Bit
*
YES
XSTP=0?
NO
Wait or
other
operations.
Ensure stable oscillation by preventing the following:
1) Condensation on the crystal oscillator
2) Instantaneous disconnection of power
3) Generation of clock noises, etc, in the crystal
oscillator
Control register 1¬2h
4) Charge of voltage exceeding prescribed maxi-
mum ratings to the individual pins of the IC
Oscillation start
33
RS5C317A/B
15.7 Interrupt Operation
15.7-1 Cyclic Interrupt Operation
1) Set the interrupt cycle register to the level mode by setting the CT3 bit to
1.
*
1
Set interrupt cycle register
*
2) Write 0 to CTFG bit for turning off INTR pin.
*
Interrupt to CPU
CTFG=1?
NO
2
YES
*
Interrupt
operation
from any
other IC
Control register 1¬2h
Cyclic interrupt operation
15.7-2 Alarm Interrupt Operation
1) Write 0 to ALFG bit for turning off ALRM pin.
*
Set alarm (hour or minute,
day-of the week)
ALE¬1
Interrupt to CPU
ALFG=1?
NO
1
YES
*
Interrupt
operation
from any
other IC
ALFG¬0
Alarm interrupt operation
34
RS5C317A/B
PACKAGE DIMENSION(Unit: mm)
• RS5C317A/B (14pin SSOP)
5.0±0.3
0° to 10°
8
14
7
1
+0.1
0.15
0.65
-
0.05
0.55TYP.
0.15
0.22±0.1
M
0.15
TAPING SPECIFICATION(Unit: mm)
4.0±0.1
+0.1
–0
ø1.5
0.3±0.1
2.0±0.05
7.0
2.7 MAX.
8.0±0.1
E2
E1
User Direction of Feed
35
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