R2043K-E2_技术文档

’04.04.23

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4-wire Serial Interface

R2043K/T

ꢀ OUTLINE

The R2043K/T is a CMOS real-time clock IC connected to the CPU by four signal lines, CE, SCLK, SI, SO, and

configured to perform serial transmission of time and calendar data to the CPU. The periodic interrupt circuit is

configured to generate interrupt signals with six selectable interrupts ranging from 0.5 seconds to 1 month. The

2 alarm interrupt circuits generate interrupt signals at preset times. As the oscillation circuit is driven under

constant voltage, fluctuation of the oscillator frequency due to supply voltage is small, and the time keeping

current is small (TYP. 0.45µA at 3V). The oscillation halt sensing circuit can be used to judge the validity of

internal data in such events as power-on; The supply voltage monitoring circuit is configured to record a drop in

supply voltage below two selectable supply voltage monitoring threshold settings. The 32.768kHz clock output

function (N-channel open drain output) is intended to output sub-clock pulses for the external microcomputer.

The oscillation adjustment circuit is intended to adjust time counts with high precision by correcting deviations in

the oscillation frequency of the crystal oscillator. Since the package for these ICs are TSSOP10G (4.0x2.9x1.0:

R2043T) or FFP12 (2.0x2.0x1.0: R2043K), high density mounting of ICs on boards is possible.

ꢀ FEATURES

ꢁ

Minimum Timekeeping supply voltage TYP:0.66 to 5.5v (Worst: 1.00V to 5.5v); VDD pin

Low power consumption

0.45µA TYP at VDD=3V (1.00µA MAX.)

Four signal lines (CE, SCLK, SI, and SO) required for connection to the CPU.

Time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months, days,

and weeks) (in BCD format)

ꢁ

Interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1 month)

to the CPU and provided with an interrupt flag and an interrupt halt

2 alarm interrupt circuits (Alarm_W for week, hour, and minute alarm settings and Alarm_D for hour and

minute alarm settings)

ꢁ

With Power-on flag to prove that the power supply starts from 0V

32-kHz clock output pin (N-channel open drain output)

Supply voltage monitoring circuit with two supply voltage monitoring threshold settings

Automatic identification of leap years up to the year 2099

Selectable 12-hour and 24-hour mode settings

High precision oscillation adjustment circuit

Built-in oscillation stabilization capacitors (CG and CD)

Package TSSOP10G (4.0mm x 2.9mm x 1.0mm: R2043T) FFP12 (2.0mm x 2.0mm x 1.0mm: R2043K)

CMOS process

ꢀ PIN CONFIGURATION

R2043T(TSSOP10G)

R2043K(FFP12)

10

9

VDD

32KOUT

SCLK

SO

1

VDD

/INTR

VSS

SI

10

11

12

6

5

4

OSCIN

OSCOUT

CE

2

3

(VSS)

8

4

5

7

SI

6

VSS

/INTR

TOP VIEW

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Rev.2.06

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R2043K/T

ꢀ BLOCK DIAGRAM

ALARM_W REGISTER

(MIN,HOUR, WEEK)

32kHz

OUTPUT

CONTROL

COMPARATOR_W

COMPARATOR_D

32KOUT

VDD

VSS

VOLTAGE

DETECT

ALARM_D REGISTER

(MIN,HOUR)

POWER_ON

RESET

OSCIN

TIME COUNTER

(SEC,MIN,HOUR,WEEK,DAY,MONTH,YEAR)

DIVIDER

DIV

CORREC

-TION

OSC

OSCOUT

SCLK

ADDRESS

REGISTER

OSC

DETECT

ADDRESS

DECODER

I/O

CONTROL

SI

SO

/INTR

CE

INTERRUPT CONTROL

SHIFT REGISTER

ꢀ SELECTION GUIDE

Part Number is designated as follows:

R2043K-E2 ←Part Number

↑ ↑

R2043a-bb

Code

Description

Designation of the package.

K: FFP12

a

T: TSSOP10G

bb

Designation of the taping type. Only E2 is available.

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Rev.2.06

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R2043K/T

ꢀ PIN DESCRIPTION

Symbol

CE

Item

Chip enable

Input

Description

The CE pin is used for interfacing with the CPU. Should be held high to

allow access to the CPU. Incorporates a pull-down resistor. Should be

held low or open when the CPU is powered off. Allows a maximum input

voltage of 5.5v regardless of supply voltage.

SCLK

SI

Serial Clock

Input

The SCLK pin is used to input clock pulses synchronizing the input and

output of data to and from the SI and SO pins. Allows a maximum input

voltage of 5.5v regardless of supply voltage.

The SI pin is used to input data intended for writing in synchronization with

the SCLK pin. CMOS input. Allows a maximum input voltage of 5.5v

regardless of supply voltage.

Serial Input

SO

Serial Output

The SO pin is used to output data intended for reading in synchronization

with the SCLK pin. CMOS output. If the CE pin is low, the SO pin goes to a

high impedance state.

/INTR

Interrupt

Output

The /INTR pin is used to output alarm interrupt (Alarm_W) and alarm

interrupt (Alarm_D) and output periodic interrupt signals to the CPU signals.

Disabled at power-on from 0V. N-channel open drain output. Allows a

maximum pull-up voltage of 5.5v regardless of supply voltage.

The 32KOUT pin is used to output 32.768-kHz clock pulses. The pin is

N-channel open drain output. However it cannot be pulled up over

VDD+0.3v.

32KOUT

32kHz Clock

Output

OSCIN

OSCOUT

Oscillation

Circuit

Input / Output

Positive/Negative

Power

The OSCIN and OSCOUT pins are used to connect the 32.768-kHz crystal

oscillator (with all other oscillation circuit components built into the

R2043K/T).

VDD

VSS

The VDD pin is connected to the power supply. The VSS pin is grounded.

Supply Input

(VSS)

Please connect to ground line, or do not connect any lines.

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R2043K/T

ꢀ ABSOLUTE MAXIMUM RATINGS

(VSS=0V)

Description

-0.3 to +6.5

Symbol

VDD

VI

Item

Supply Voltage

Input Voltage

Pin Name

VDD

CE, SCLK, SI

Unit

V

VO

Output Voltage 1

Output Voltage 2

Power Dissipation

Operating Temperature

Storage Temperature

SO, 32KOUT

/INTR

Topt = 25°C

-0.3 to VDD + 0.3

-0.3 to +6.5

300

-40 to +85

-55 to +125

V

mW

PD

Topt

Tstg

°C

ꢀ RECOMMENDED OPERATING CONDITIONS

(VSS=0V, Topt=-40 to +85°C)

Symbol

Vaccess

Item

Supply Voltage

Pin Name

Power supply voltage 1.7

Min,

Typ.

Max.

5.5

Unit

V

for interfacing

with CPU

*1)

VCLK

Time keeping Voltage

CGout,CDout=0pF

*1), *2)

CGout,CDout=0pF

*1), *2)

1.00

5.50

1.00

V

VCLKL

Minimum Time keeping

Voltage

0.66

fXT

VPUP

Oscillation Frequency

Pull-up Voltage

32.768

kHz

V

/INTR

5.5

32KOUT

VDD

+0.3

*1) CGout is connected between OSCIN and VSS, CDout is connected between OSCOUT and VSS.

R2043K/T series incorporates the capacitors between OSCIN and VSS, between OSCOUT and VSS.

Then normally, CGout and CDout are not necessary. For more detail, see “P.28 ꢁAdjustment of Oscillation

frequency”

*2) Crystal oscillator: CL=6-9pF, R1=50KΩ

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R2043K/T

ꢀ DC ELECTRICAL CHARACTERISTICS

ꢁ

R2043K/T

(Unless otherwise specified:

VSS=0V, VDD=3.0V, Topt=-40 to +85°C, Crystal oscillator 32768Hz,CL=7pF,R1=50kΩ)

Symbol

VIH

Item

“H” Input Voltage

Pin Name

CE,

SCLK, SI

Conditions

VDD=1.7 to 5.5V

Min.

0.8x

VDD

Typ.

Max.

5.5

Unit

V

VIL

“L” Input Voltage

-0.3

0.2x

VDD

-0.5

IOH

“H” Output

Current

“L” Output

Current

SO

VOH=VDD-0.5V

VOL=0.4V

mA

IOL1

IOL2

/INTR

SO,

2.0

0.5

32KOUT

IIL

Input Leakage

Current

Pull-down Resistance

SI, SCLK

VI=5.5V or VSS

VDD=5.5V

-1.0

1.0

µA

kΩ

µA

RDNCE

IOZ1

CE

SO

40

-1

120

400

1

VO=5.5V or VSS

VDD=5.5V

VO=5.5V

VDD=5.5V

VO=5.5V

Output Off-state

Current

IOZ2

IOZ3

IDD

/INTR

32KOUT

VDD

-1

1

VDD=5.5V

VDD=3V,

Time Keeping Current

CE= OPEN

Output = OPEN

32KOUT=OFF

CGout=CDout=0pF

*1)

0.45

1.00

µA

VDETH

VDETL

Supply Voltage

Monitoring Voltage “H”

Supply Voltage

VDD

1.45

1.15

1.60

1.30

1.75

1.45

V

Topt=-30 to +70°C

Monitoring Voltage “L”

*1) For time keeping current when outputting 32.768kHz from the 32KOUT pin, see “P.43 ꢀTypical

Characteristics”. For time keeping current when CGOUT, CDOUT is not equal to 0pF, see “P.28

ꢁAdjustment of Oscillation frequency”.

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R2043K/T

ꢀ AC ELECTRICAL CHARACTERISTICS

Unless otherwise specified: VSS=0V,Topt=-40 to +85°C

Input and Output Conditions: VIH=0.8×VDD,VIL=0.2×VDD,VOH=0.8×VDD,VOL=0.2×VDD,CL=50pF

Symbol

Item

CE Set-up Time

CE Hold Time

CE Recovery Time

Condi-

tions

Unit

VDD≥1.7V

Min.

400

62

Typ.

Max.

t_CES

t_CEH

t_CR

ns

µs

f_SCLK

t_CKH

t_CKL

t_CKS

t_RD

SCLK Clock Frequency

SCLK Clock High Time

SCLK Clock Low Time

SCLK Set-up Time

Data Output Delay Time

Data Output Floating Time

Data Output Delay Time

After Falling of CE

1.0

MHz

400

200

ns

300

t_RZ

t_CEZ

t_DS

t_DH

Input Data Set-up Time

Input Data Hold Time

200

ns

t_CKH

t_CKL

CE

t_CEH

t_CR

t_CKSt_CES

SCLK

t_DS

t_DH

SI

t_CEZ

SO

t_RD

t_RZ

t_RD

*) For reading/writing timing, see “P.28 ꢁAdjustment of Oscillation frequency”.

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R2043K/T

ꢀ PACKAGE DIMENSIONS

ꢁ

R2043K

9

7

6

4

10

1PIN INDEX

0.05

12

1

3

0.35

0.25

1.0Max

2PIN INDEX

0.35

0.2±0.15

(BOTTOM VIEW)

0.17±0.1

0.27±0.15

2.0±0.1

unit: mm

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Rev.2.05

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R2043K/T

ꢁ

R2043T

0 to 10°

2.9±0.2

10

6

+0.1

-0.05

1

5

0.5

0.13

0.1

0.2±0.1

M

0.15

unit: mm

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R2043K/T

ꢀ GENERAL DESCRIPTION

ꢁ

Interface with CPU

The R2043K/T is connected to the CPU by four signal lines CE (Chip Enable), SCLK (Serial Clock), SI (Serial

Input), and SO (Serial Output), through which it reads and writes data from and to the CPU. The CPU can be

accessed when the CE pin is held high. Access clock pulses have a maximum frequency of 1 MHz allowing

high-speed data transfer to the CPU.

ꢁ

Clock and Calendar Function

The R2043K/T reads and writes time data from and to the CPU in units ranging from seconds to the last two

digits of the calendar year. The calendar year will automatically be identified as a leap year when its last two

digits are a multiple of 4. Consequently, leap years up to the year 2099 can automatically be identified as such.

*) The year 2000 is a leap year while the year 2100 is not a leap year.

ꢁ

Alarm Function

The R2043K/T incorporates the alarm interrupt circuit configured to generate interrupt signals to the CPU at

preset times. The alarm interrupt circuit allows two types of alarm settings specified by the Alarm_W registers

and the Alarm_D registers. The Alarm_W registers allow week, hour, and minute alarm settings including

combinations of multiple day-of-week settings such as "Monday, Wednesday, and Friday" and "Saturday and

Sunday". The Alarm_D registers allow hour and minute alarm settings. The Alarm_W outputs from /INTR pin, and

the Alarm_D outputs also from /INTR pin. Each alarm function can be checked from the CPU by using a polling

function.

ꢁ

High-precision Oscillation Adjustment Function

The R2043K/T has built-in oscillation stabilization capacitors (CG and CD), which can be connected to an

external crystal oscillator to configure an oscillation circuit. Two kinds of accuracy for this function are

alternatives. To correct deviations in the oscillator frequency of the crystal, the oscillation adjustment circuit is

configured to allow correction of a time count gain or loss (up to ±1.5ppm or ±0.5ppm at 25°C) from the CPU.

The maximum range is approximately ±189ppm (or ±63ppm) in increments of approximately 3ppm (or 1ppm).

Such oscillation frequency adjustment in each system has the following advantages:

*

Allows timekeeping with much higher precision than conventional RTCs while using a crystal oscillator

with a wide range of precision variations.

*

Corrects seasonal frequency deviations through seasonal oscillation adjustment.

Allows timekeeping with higher precision particularly with a temperature sensing function out of RTC,

through oscillation adjustment in tune with temperature fluctuations.

ꢁ

Power-on Reset, Oscillation Halt Sensing Function and Supply Voltage Monitoring Function

The R2043K/T incorporates an oscillation halt sensing circuit equipped with internal registers configured to

record any past oscillation halt.

Power on reset function reset the control resisters when the system is powered on from 0V. At the same time, the

fact is memorized to the resister as a flag, thereby identifying whether they are powered on from 0V or battery

backed-up.

The R2043K/T also incorporates a supply voltage monitoring circuit equipped with internal registers configured to

record any drop in supply voltage below a certain threshold value. Supply voltage monitoring threshold settings

can be selected between 1.6V and 1.3V through internal register settings. The sampling rate is normally 1s.

The oscillation halt sensing circuit and the power-on reset flag are configured to confirm the established

invalidation of time data in contrast to the supply voltage monitoring circuit intended to confirm the potential

invalidation of time data. Further, the supply voltage monitoring circuit can be applied to battery supply voltage

monitoring.

ꢁ

Periodic Interrupt Function

The R2043K/T incorporates the periodic interrupt circuit configured to generate periodic interrupt signals aside

from interrupt signals generated by the alarm interrupt circuit for output from the /INTR pin. Periodic interrupt

signals have five selectable frequency settings of 2 Hz (once per 0.5 seconds), 1 Hz (once per 1 second), 1/60

Hz (once per 1 minute), 1/3600 Hz (once per 1 hour), and monthly (the first day of every month). Further,

periodic interrupt signals also have two selectable waveforms, a normal pulse form (with a frequency of 2 Hz or 1

Hz) and special form adapted to interruption from the CPU in the level mode (with second, minute, hour, and

month interrupts). The condition of periodic interrupt signals can be monitored with using a polling function.

ꢁ

32kHz Clock Output

The R2043K/T incorporates a 32-kHz clock circuit configured to generate clock pulses with the oscillation

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R2043K/T

frequency of a 32.768kHz crystal oscillator for output from the 32KOUT pin. The 32-kHz clock output can be

disabled by certain register settings but cannot be disabled without manipulation of any two registers with

different addresses to prevent disabling in such events as the runaway of the CPU. The pin is N-channel open

drain output, however it cannot be pulled up over VDD+0.3v.

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R2043K/T

ꢀ Address Mapping

Address

A3A2A1A0

0 0 0 0 0

Register Name

D a t a

D3

D7

-

D6

S40

D5

S20

D4

S10

D2

S4

D1

S2

D0

S1

Second Counter

S8

*2)

1 0 0 0 1

2 0 0 1 0

Minute Counter

Hour Counter

-

M40

-

M20

H20

P⋅/A

-

D20

-

M10

H10

M8

H8

M4

H4

M2

H2

M1

H1

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

Day-of-week Counter

Day-of-month Counter

Month Counter and

Century Bit

-

D8

W4

D4

MO4 MO2

W2

D2

W1

D1

MO1

D10

MO10 MO8

/19⋅20

6 0 1 1 0

7 0 1 1 1

Year Counter

Oscillation Adjustment

Register *3)

Alarm_W

(Minute Register)

Alarm_W

(Hour Register)

Alarm_W

Y80

DEV

*4)

-

Y40

F6

Y20

F5

Y10

F4

Y8

F3

Y4

F2

Y2

F1

Y1

F0

8 1 0 0 0

9 1 0 0 1

A 1 0 1 0

WM40 WM20 WM10

WM8 WM4 WM2

WM1

WH1

WW0

-

WH20

WP⋅/ A

WW5

WH10 WH8

WH4 WH2

WW6

WW4

WW3 WW2 WW1

(Day-of-week

Register)

B 1 0 1 1

C 1 1 0 0

Alarm_D

(Minute Register)

Alarm_D

(Hour Register)

-

DM40

DM20

DM10

DH10

DM8

DH8

DM4 DM2

DM1

DH1

-

DH20

DP⋅/A

-

/12⋅24

/XST

*5)

DH4

DH2

D 1 1 0 1

E 1 1 1 0

F 1 1 1 1

-

/CLEN2

Control Register 1 *3)

Control Register 2 *3)

WALE DALE

VDSL VDET

TEST

/CLEN1

CT2

CT1

CT0

PON

*3)

CTFG WAFG DAFG

Notes:

* 1) All the data listed above accept both reading and writing.

* 2) The data marked with "-" is invalid for writing and reset to 0 for reading.

* 3) PON is a power-on-reset flag.

When the PON bit is set to 1 in Control Register 2, all the bits are reset to 0 in Oscillation Adjustment

Register, Control Register 1 and Control Register 2 excluding the /XST bit.

* 4) When DEV=0, the oscillation adjustment circuit is configured to allow correction of a time count gain or

loss up to ±1.5ppm.

When DEV=1, the oscillation adjustment circuit is configured to allow correction of a time count gain or

loss up to or ±0.5ppm.

* 5) /XST is an oscillation halt sensing monitor bit.

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R2043K/T

ꢀ Register Settings

ꢁ

Control Register 1 (ADDRESS Eh)

D7

D6

D5

D4

D3

D2

CT2

0

D1

CT1

0

D0

CT0

0

WALE

0

DALE

0

/CLEN2

0

TEST

0

(For Writing)

(For Reading)

Default Settings *)

/12⋅24

0

*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD

power-on from 0v.

(1) WALE, DALEAlarm_W Enable Bit, Alarm_D Enable Bit

WALE,DALE

0

Description

Disabling the alarm interrupt circuit (under the control of the settings

of the Alarm_W registers and the Alarm_D registers).

Enabling the alarm interrupt circuit (under the control of the settings

of the Alarm_W registers and the Alarm_D registers)

(Default)

1

(2) /12⋅24

/12-24-hour Mode Selection Bit

Description

/12⋅24

0

1

Selecting the 12-hour mode with a.m. and p.m. indications.

Selecting the 24-hour mode

(Default)

Setting the /12⋅24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively.

24-hour mode

12-hour mode

12 (AM12)

01 (AM 1)

02 (AM 2)

03 (AM 3)

04 (AM 4)

05 (AM 5)

06 (AM 6)

07 (AM 7)

08 (AM 8)

09 (AM 9)

10 (AM10)

11 (AM11)

24-hour mode

12-hour mode

32 (PM12)

21 (PM 1)

22 (PM 2)

23 (PM 3)

24 (PM 4)

25 (PM 5)

26 (PM 6)

27 (PM 7)

28 (PM 8)

29 (PM 9)

30 (PM10)

31 (PM11)

00

01

02

03

04

05

06

07

08

09

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Setting the /12⋅24 bit should precede writing time data

(3) /CLEN2 32kHz Clock Output Bit 2

/CLEN2

Description

0

1

Enabling the 32-kHz clock circuit

Disabling the 32-kHz clock circuit

(Default)

Setting the /CLEN2 bit or the /CLEN1 bit (D3 in the control register 2) to 0, specifies generating clock pulses

with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin.

Conversely, setting both the /CLEN1 and /CLEN2 bit to 1 disabling (”H”) such output.

(4) TEST

Test Bit

TEST

Description

0

1

Normal operation mode.

Test mode.

(Default)

The TEST bit is used only for testing in the factory and should normally be set to 0.

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R2043K/T

(5) CT2, CT1, and CT0

Periodic Interrupt Selection Bits

CT2

CT1

CT0

Description

Wave

form

Interrupt Cycle and Falling Timing

mode

0

1

0

1

0

-

OFF(H)

Fixed at “L”

2Hz (Duty50%)

(Default)

Pulse Mode

*1)

0

1

0

1

0

1

0

1

Pulse Mode

*1)

Level Mode

*2)

Level Mode

*2)

Level Mode

*2)

1Hz (Duty50%)

Once per 1 second (Synchronized with

second counter increment)

Once per 1 minute (at 00 seconds of

every minute)

Once per hour (at 00 minutes and 00

seconds of every hour)

Level Mode

*2)

Once per month (at 00 hours, 00

minutes,

and 00 seconds of first day of every

month)

* 1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the

second counter as illustrated in the timing chart below.

CTFG Bit

/INTR Pin

Approx. 92µs

(Increment of second counter)

Rewriting of the second counter

In the pulse mode, the increment of the second counter is delayed by approximately 92 µs from the

falling edge of clock pulses. Consequently, time readings immediately after the falling edge of clock

pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second.

Rewriting the second counter will reset the other time counters of less than 1 second, driving the

/INTR pin low.

* 2) Level Mode: Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1

minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the falling

edge of periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle

setting of 1 second are output in synchronization with the increment of the second counter as

illustrated in the timing chart below.

CTFG Bit

/INTR Pin

Setting CTFG bit to 0

(Increment of

second counter)

(Increment of

second counter)

(Increment of

second counter)

*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. or

60sec. as follows:

Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of ±3.784 ms. For

example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%.

Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of ±3.784 ms.

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R2043K/T

ꢁ

Control Register 2 (Address Fh)

D7

D6

D5

D4

D3

D2

D1

D0

VDSL

0

VDET

0

/XST

Indefinite

PON

1

/CLEN1

0

CTFG

0

WAFG

0

DAFG

0

(For Writing)

(For Reading)

Default Settings *)

*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD

power-on from 0v.

(1) VDSL

VDD Supply Voltage Monitoring Threshold Selection Bit

VDSL

0

Description

Selecting the VDD supply voltage monitoring threshold setting of

(Default)

1.6v.

1

Selecting the VDD supply voltage monitoring threshold setting of

1.3v.

The VDSL bit is intended to select the VDD supply voltage monitoring threshold settings.

(2) VDET

Supply Voltage Monitoring Result Indication Bit

Description

Indicating supply voltage above the supply voltage monitoring

threshold settings.

VDET

0

(Default)

1

Indicating supply voltage below the supply voltage monitoring

threshold settings.

Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will

hold the setting of 1. The VDET bit accepts only the writing of 0, which restarts the supply voltage

monitoring circuit. Conversely, setting the VDET bit to 1 causes no event.

(3) /XST

Oscillation Halt Sensing Monitor Bit

Description

/XST

0

1

Sensing a halt of oscillation

Sensing a normal condition of oscillation

The /XST accepts the reading and writing of 0 and 1. The /XST bit will be set to 0 when the oscillation halt

sensing. The /XST bit will hold 0 even after the restart of oscillation.

(4) PON

Power-on-reset Flag Bit

Description

PON

0

1

Normal condition

Detecting VDD power-on -reset

(Default)

The PON bit is for sensing power-on reset condition.

*

The PON bit will be set to 1 when VDD power-on from 0v. The PON bit will hold the setting of 1

even after power-on.

*

When the PON bit is set to 1, all bits will be reset to 0, in the Oscillation Adjustment Register, Control

Register 1, and Control Register 2, except /XST and PON. As a result, /INTR pin stops outputting.

The PON bit accepts only the writing of 0. Conversely, setting the PON bit to 1 causes no event.

*

(5) /CLEN1

32kHz Clock Output Bit 1

/CLEN1

Description

0

1

Enabling the 32-kHz clock circuit

Disabling the 32-kHz clock circuit

(Default)

Setting the /CLEN1 bit or the /CLEN2 bit (D4 in the control register 1) to 0, specifies generating clock pulses

with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin.

Conversely, setting both the /CLEN1 and /CLEN2 bit to 1 disabling (”H”) such output.

12345

Rev.2.06

- 14 -

R2043K/T

(6) CTFG

CTFG

Periodic Interrupt Flag Bit

Description

0

1

Periodic interrupt output = “H”

Periodic interrupt output = “L”

(Default)

The CTFG bit is set to 1 when the periodic interrupt signals are output from the /INTR pin (“L”). The CTFG

bit accepts only the writing of 0 in the level mode, which disables (“H”) the /INTR pin until it is enabled (“L”)

again in the next interrupt cycle. Conversely, setting the CTFG bit to 1 causes no event.

(7) WAFG,DAFG

Alarm_W Flag Bit and Alarm_D Flag Bit

WAFG,DAFG

Description

0

1

Indicating a mismatch between current time and preset alarm time

Indicating a match between current time and preset alarm time

(Default)

The WAFG and DAFG bits are valid only when the WALE and DALE have the setting of 1, which is caused

approximately 61µs after any match between current time and preset alarm time specified by the Alarm_W

registers and the Alarm_D registers. The WAFG (DAFG) bit accepts only the writing of 0. /INTR pin

outputs off (“H”) when this bit is set to 0. And /INTR pin outputs “L” again at the next preset alarm time.

Conversely, setting the WAFG and DAFG bits to 1 causes no event. The WAFG and DAFG bits will have

the reading of 0 when the alarm interrupt circuit is disabled with the WALE and DALE bits set to 0. The

settings of the WAFG and DAFG bits are synchronized with the output of the /INTR pin as shown in the

timing chart below.

Approx. 61µs

WAFG(DAFG) Bit

/INTR Pin

Writing of 0 to

WAFG(DAFG) bit

(Match between

current time and

preset alarm time)

12345

Rev.2.05

- 15 -

R2043K/T

ꢁ

Time Counter (Address 0-2h)

Second Counter (Address 0h)

D7

-

D6

S40

D5

S20

D4

S10

D3

S8

D2

S4

D1

S2

D0

S1

(For Writing)

0

S40

Indefinite

S20

Indefinite

S10

Indefinite

S8

Indefinite

S4

Indefinite

S2

Indefinite

S1

Indefinite

(For Reading)

Default Settings *)

Minute Counter (Address 1h)

D7

-

D6

M40

D5

M20

D4

M10

D3

M8

D2

M4

D1

M2

D0

M1

(For Writing)

0

M40

Indefinite

M20

Indefinite

M10

Indefinite

M8

Indefinite

M4

Indefinite

M2

Indefinite

M1

Indefinite

(For Reading)

Default Settings *)

Hour Counter (Address 2h)

D7

-

D6

-

D5

P⋅/A

D4

H10

D3

H8

D2

H4

D1

H2

D0

H1

(For Writing)

or H20

0

H10

H8

H4

H2

H1

(For Reading)

P⋅/A

or H20

Indefinite

Default Settings *)

*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD

power-on from 0v.

*

Time digit display (BCD format) as follows:

The second digits range from 00 to 59 and are carried to the minute digit in transition from 59 to 00.

The minute digits range from 00 to 59 and are carried to the hour digits in transition from 59 to 00.

The hour digits range as shown in "P12 ꢁ Control Register 1 (ADDRESS Eh) (2) /12⋅24: /12-24-hour

Mode Selection Bit" and are carried to the day-of-month and day-of-week digits in transition from

PM11 to AM12 or from 23 to 00.

*

Any writing to the second counter resets divider units of less than 1 second.

Any carry from lower digits with the writing of non-existent time may cause the time counters to

malfunction. Therefore, such incorrect writing should be replaced with the writing of existent time

data.

ꢁ

Day-of-week Counter (Address 3h)

D7

-

D6

-

D5

-

D4

-

D3

-

D2

W4

D1

W2

D0

W1

(For Writing)

0

W4

Indefinite

W2

Indefinite

W1

Indefinite

(For Reading)

Default Settings *)

*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD

power-on from 0v.

*

The day-of-week counter is incremented by 1 when the day-of-week digits are carried to the

day-of-month digits.

Day-of-week display (incremented in septimal notation):

(W4, W2, W1) = (0, 0, 0) → (0, 0, 1)→…→(1, 1, 0) → (0, 0, 0)

Correspondences between days of the week and the day-of-week digits are user-definable

(e.g. Sunday = 0, 0, 0)

The writing of (1, 1, 1) to (W4, W2, W1) is prohibited except when days of the week are unused.

12345

Rev.2.06

- 16 -

R2043K/T

ꢁ

Calendar Counter (Address 4-6h)

Day-of-month Counter (Address 4h)

D7

-

D6

-

D5

D20

D4

D10

D3

D8

D2

D4

D1

D2

D0

D1

(For Writing)

0

D20

Indefinite

D10

Indefinite

D8

Indefinite

D4

Indefinite

D2

Indefinite

D1

Indefinite

(For Reading)

Default Settings *)

Month Counter + Century Bit (Address 5h)

D7

D6

D5

D4

D3

D2

D1

D0

-

MO10

MO8

MO4

MO2

MO1

(For Writing)

/19⋅20

0

MO10

Indefinite

MO8

Indefinite

MO4

Indefinite

MO2

Indefinite

MO1

Indefinite

(For Reading)

Default Settings *)

/19⋅20

Indefinite

Year Counter (Address 6h)

D7

Y80

D6

Y40

D5

Y20

D4

Y10

D3

Y8

D2

Y4

D1

Y2

D0

Y1

(For Writing)

Y80

Indefinite

Y40

Indefinite

Y20

Indefinite

Y10

Indefinite

Y8

Indefinite

Y4

Indefinite

Y2

Indefinite

Y1

Indefinite

(For Reading)

Default Settings *)

*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD

power-on from 0v.

*

The calendar counters are configured to display the calendar digits in BCD format by using the

automatic calendar function as follows:

The day-of-month digits (D20 to D1) range from 1 to 31 for January, March, May, July, August,

October, and December; from 1 to 30 for April, June, September, and November; from 1 to 29 for

February in leap years; from 1 to 28 for February in ordinary years. The day-of-month digits are

carried to the month digits in reversion from the last day of the month to 1. The month digits (MO10

to MO1) range from 1 to 12 and are carried to the year digits in reversion from 12 to 1.

The year digits (Y80 to Y1) range from 00 to 99 (00, 04, 08, …, 92, and 96 in leap years) and are

carried to the /19⋅20 digits in reversion from 99 to 00.

The /19⋅20 digits cycle between 0 and 1 in reversion from 99 to 00 in the year digits.

Any carry from lower digits with the writing of non-existent calendar data may cause the calendar

counters to malfunction. Therefore, such incorrect writing should be replaced with the writing of

existent calendar data.

*

ꢁ

Oscillation Adjustment Register (Address 7h)

D7

D6

F6

0

D5

F5

0

D4

F4

0

D3

F3

0

D2

F2

0

D1

F1

0

D0

F0

0

DEV

0

(For Writing)

(For Reading)

Default Settings *)

*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD

power-on from 0v.

DEV bit

When DEV is set to 0, the Oscillation Adjustment Circuit operates 00, 20, 40 seconds.

When DEV is set to 1, the Oscillation Adjustment Circuit operates 00 seconds.

F6 to F0 bits

The Oscillation Adjustment Circuit is configured to change time counts of 1 second on the basis of the

settings of the Oscillation Adjustment Register at the timing set by DEV.

12345

Rev.2.05

- 17 -

R2043K/T

*

The Oscillation Adjustment Circuit will not operate with the same timing (00, 20, or 40 seconds)

as the timing of writing to the Oscillation Adjustment Register.

The F6 bit setting of 0 causes an increment of time counts by ((F5, F4, F3, F2, F1, F0) - 1) x 2.

The F6 bit setting of 1 causes a decrement of time counts by ((/F5, /F4, /F3, /F2, /F1, /F0) + 1) x 2.

The settings of "*, 0, 0, 0, 0, 0, *" ("*" representing either "0" or "1") in the F6, F5, F4, F3, F2, F1, and

F0

bits cause neither an increment nor decrement of time counts.

Example:

If (DEV, F6, F5, F4, F3, F2, F1, F0) is set to (0, 0, 0, 0, 0, 1, 1, 1), when the second digits read 00, 20,

or 40, an increment of the current time counts of 32768 + (7 - 1) x 2 to 32780 (a current time count

loss).

If (DEV, F6, F5, F4, F3, F2, F1, F0) is set to (0, 0, 0, 0, 0, 0, 0, 1), when the second digits read 00, 20,

40, neither an increment nor a decrement of the current time counts of 32768.

If (DEV, F6, F5, F4, F3, F2, F1, F0) is set to (1, 1, 1, 1, 1, 1, 1, 0), when the second digits read 00, a

decrement of the current time counts of 32768 + (- 2) x 2 to 32764 (a current time count gain).

An increase of two clock pulses once per 20 seconds causes a time count loss of approximately 3

ppm (2 / (32768 x 20 = 3.051 ppm). Conversely, a decrease of two clock pulses once per 20

seconds causes a time count gain of 3 ppm. Consequently, when DEV is set to “0”, deviations in

time counts can be corrected with a precision of ±1.5 ppm. In the same way, when DEV is set to “1”,

deviations in time counts can be corrected with a precision of ±0.5 ppm. Note that the oscillation

adjustment circuit is configured to correct deviations in time counts and not the oscillation frequency

of the 32.768-kHz clock pulses. For further details, see "P31 ꢁOscillation Adjustment Circuit".

12345

Rev.2.06

- 18 -

R2043K/T

ꢁ

Alarm_W Registers (Address 8-Ah)

Alarm_W Minute Register (Address 8h)

D7

D6

D5

D4

D3

D2

D1

D0

-

WM40

WM20

WM10

WM8

WM4

WM2

WM1

(For Writing)

0

WM40

Indefinite

WM20

Indefinite

WM10

Indefinite

WM8

Indefinite

WM4

Indefinite

WM2

Indefinite

WM1

Indefinite

(For Reading)

Default Settings *)

Alarm_W Hour Register (Address 9h)

D7

D6

D5

D4

D3

D2

D1

D0

-

WH20

WP⋅/A

WH20

WP⋅/A

Indefinite

WH10

WH8

WH4

WH2

WH1

(For Writing)

0

WH10

WH8

WH4

WH2

WH1

(For Reading)

Default Settings *)

Indefinite

Alarm_W Day-of-week Register (Address Ah)

D7

D6

D5

D4

D3

D2

D1

D0

-

WW6

WW5

WW4

WW3

WW2

WW1

WW0

(For Writing)

0

WW6

Indefinite

WW5

Indefinite

WW4

Indefinite

WW3

Indefinite

WW2

Indefinite

WW1

Indefinite

WW0

Indefinite

(For Reading)

Default Settings *)

*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD

power-on from 0v.

*

The D5 bit of the Alarm_W Hour Register represents WP/A when the 12-hour mode is selected (0 for

a.m. and 1 for p.m.) and WH20 when the 24-hour mode is selected (tens in the hour digits).

The Alarm_W Registers should not have any non-existent alarm time settings.

*

(Note that any mismatch between current time and preset alarm time specified by the Alarm_W registers

may disable the alarm interrupt circuit.)

*

When the 12-hour mode is selected, the hour digits read 12 and 32 for 0 a.m. and 0 p.m., respectively.

(See "P12 ꢁControl Register 1 (ADDRESS Eh) (2) /12⋅24: 12-/24-hour Mode Selection Bit")

WW0 to WW6 correspond to W4, W2, and W1 of the day-of-week counter with settings ranging from

(0, 0, 0) to (1, 1, 0).

WW0 to WW6 with respective settings of 0 disable the outputs of the Alarm_W Registers.

12345

Rev.2.05

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R2043K/T

Example of Alarm Time Setting

Alarm

Day-of-week

Sun. Mon.

12-hour mode

24-hour mode

10 10

hr. min. min. hr. hr. min. min.

Preset alarm time

Tue.

Wed. Th.

Fri.

Sat.

10

hr.

1

10

1

WW0 WW1 WW2 WW3 WW4 WW5 WW6

00:00 a.m. on all days

01:30 a.m. on all days

11:59 a.m. on all days

00:00 p.m. on Mon. to Fri.

01:30 p.m. on Sun.

11:59 p.m.

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

1

2

1

0

3

5

0

3

5

0

9

0

9

0

1

2

0

1

2

3

0

3

5

0

3

5

0

9

0

9

0

1

3

2

3

on Mon. ,Wed., and Fri.

Note that the correspondence between WW0 to WW6 and the days of the week shown in the above table is

only an example and not mandatory.

ꢁ

Alarm_D Register (Address B-Ch)

Alarm_D Minute Register (Address Bh)

D7

D6

D5

D4

D3

D2

D1

D0

-

DM40

DM20

DM10

DM8

DM4

DM2

DM1

(For Writing)

0

DM40

Indefinite

DM20

Indefinite

DM10

Indefinite

DM8

Indefinite

DM4

Indefinite

DM2

Indefinite

DM1

Indefinite

(For Reading)

Default Settings *)

Alarm_D Hour Register (Address Ch)

D7

D6

D5

D4

D3

D2

D1

D0

-

DH20

DP⋅/A

DH20

DP⋅/A

Indefinite

DH10

DH8

DH4

DH2

DH1

(For Writing)

0

DH10

DH8

DH4

DH2

DH1

(For Reading)

Indefinite

Default Settings *)

*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD

power-on from 0v.

*

The D5 bit represents DP/A when the 12-hour mode is selected (0 for a.m. and 1 for p.m.) and DH20

when the 24-hour mode is selected (tens in the hour digits).

The Alarm_D registers should not have any non-existent alarm time settings.

(Note that any mismatch between current time and preset alarm time specified by the Alarm_D registers

may disable the alarm interrupt circuit.)

*

When the 12-hour mode is selected, the hour digits read 12 and 32 for 0a.m. and 0p.m., respectively.

(See "P12 ꢁControl Register 1 (ADDRESS Eh) (2) /12⋅24: 12-/24-hour Mode Selection Bit")

12345

Rev.2.06

- 20 -

R2043K/T

ꢀ Interfacing with the CPU

ꢁ

DATA TRANSFER FORMATS

(1) Timing Between CE Pin Transition and Data Input / Output

The R2043K/T adopts a 4-wire serial interface by which they use the CE (Chip Enable), SCLK (Serial Clock), SI

(Serial Input), and SO (Serial Output) pins to receive and send data to and from the CPU. The 4-wire serial

interface provides two types of input/output timings with which the SO pin output and the SI pin input are

synchronized with the rising or falling edges of the SCLK pin input, respectively, and vice versa. The R2043K/T

is configured to select either one of two different input/output timings depending on the level of the SCLK pin in

the low to high transition of the CE pin. Namely, when the SCLK pin is held low in the low to high transition of

the CE pin, the models will select the timing with which the SO pin output is synchronized with the rising edge of

the SCLK pin input, and the SI pin input is synchronized with the falling edge of the SCLK pin input, as illustrated

in the timing chart below.

CE

t_CES

SCLK

t_DS

t_DH

t_RD

SI

SO

Conversely, when the SCLK pin is held high in the low to high transition of the CE pin, the models will select the

timing with which the SO pin output is synchronized with the falling edge of the SCLK pin input, and the SI pin

input is synchronized with the rising edge of the SCLK pin input, as illustrated in the timing chart below.

CE

t_CES

SCLK

t_DS

t_DH

t_RD

SI

SO

(2) Data Transfer Formats

Data transfer is commenced in the low to high transition of the CE pin input and completed in its high to low

transition. Data transfer is conducted serially in multiple units of 1 byte (8 bits). The former 4 bits are used to

specify in the Address Pointer a head address with which data transfer is to be commenced from the host. The

latter 4 bits are used to select either reading data transfer or writing data transfer, and to set the Transfer Format

Register to specify an appropriate data transfer format. All data transfer formats are designed to transfer the

most significant bit (MSB) first.

CE

1

2

3

4

5

6

7

8

1

2

3

SCLK

SI

A3 A2

A1

A0

C3

C2

C1

C0

D7

D6

D3

D2

D1

D0

Setting

the Address Pointer

Setting the Transfer

Format Register

Writing data transfer

D7

D6

D3

D2

SO

Reading data transfer

Two types of data transfer formats are available for reading data transfer and writing data transfer each.

12345

Rev.2.05

- 21 -

R2043K/T

ꢁ

Writing Data Transfer Formats

(1) 1-byte Writing Data Transfer Format

The first type of writing data transfer format is designed to transfer 1-byte data at a time and can be selected by

specifying in the address pointer a head address with which writing data transfer is to be commenced and then

writing the setting of 8h to the transfer format register. This 1-byte writing data transfer can be completed by

driving the CE pin low or continued by specifying a new head address in the address pointer and setting the data

transfer format.

Example of 1-byte Writing Data Transfer (For Writing Data to Addresses Fh and 7h)

CE

Data

SI

1 1 1 1 1 0 0 0

0 1 1 1 1 0 0 0

SO

Setting 8h in Writing data to

Specifying Fh

Specifying 7hSetting 8h in Writing data to

the Transfer

Format

address Fh

in the

the Transfer

Format

address 7h

in the

Address

Pointer

Address

Pointer

Register

Data transfer from the host

Data transfer from the RTCs

(2) Burst Writing Data Transfer Format

The second type of writing data transfer format is designed to transfer a sequence of data serially and can be

selected by specifying in the address pointer a head address with which writing data transfer is to be

commenced and then writing the setting of 0h to the transfer format register. The address pointer is

incremented for each transfer of 1-byte data and cycled from Fh to 0h. This burst writing data transfer can be

completed by driving the CE pin low.

Example of Burst Writing Data Transfer (For Writing Data to Addresses Eh, Fh, and 0h)

CE

Data

SI

Data

1 1 1 0 0 0 0 0

SO

Specifying EhSetting 0h in Writing data to

Writing data to

in the

the Transfer

Format

address Eh

address Fh

address 0h

Address

Pointer

Register

Data transfer from the host

Data transfer from the RTCs

12345

Rev.2.06

- 22 -

R2043K/T

ꢁ

Reading Data Transfer Formats

(1) 1-byte Reading Data Transfer Format

The first type of reading data transfer format is designed to transfer 1-byte data at a time and can be selected by

specifying in the Address Pointer a head address with which reading data transfer is to be commenced and then

the setting of writing Ch to the Transfer Format Register. This 1-byte reading data transfer can be completed by

driving the CE pin low or continued by specifying a new head address in the Address Pointer and selecting this

type of reading data Transfer Format.

Example of 1-byte Reading Data Transfer (For Reading Data from Addresses Eh and 2h)

CE

SI

1 1 1 0 1 1 0 0

0 0 1 0 1 1 0 0

Data

SO

Setting Ch in Reading data from

Specifying Eh

Specifying 2hSetting Ch in Reading data from

the Transfer

Format

address Eh

in the

the Transfer

Format

address 2h

in the

Address

Pointer

Address

Pointer

Register

Data transfer from the host

Data transfer from the RTCs

(2) Burst Reading Data Transfer Format

The second type of reading data transfer format is designed to transfer a sequence of data serially and can be

selected by specifying in the address pointer a head address with which reading data transfer is to be

commenced and then writing the setting of 4h to the transfer format register. The address pointer is

incremented for each transfer of 1-byte data and cycled from Fh to 0h. This burst reading data transfer can be

completed by driving the CE pin low.

Example of Burst Reading Data Transfer (For Reading Data from Addresses Fh, 0h, and 1h)

CE

SI

1 1 1 1 0 1 0 0

DATA

SO

Specifying FhSetting 4h in

Reading data from

address Fh

Reading data from

address 0h

Reading data from

address 1h

in the

the Transfer

Format

Address

Pointer

Register

Data transfer from the host

Data transfer from the RTCs

12345

Rev.2.05

- 23 -

R2043K/T

(3) Combination of 1-byte Reading and writing Data Transfer Formats

The 1-byte reading and writing data transfer formats can be combined together and further followed by any other

data transfer format.

Example of Reading Modify Writing Data Transfer

(For Reading and Writing Data from and to Address Fh)

CE

SI

DATA

1 1 1 1 1 1 0 0

Specifying FhSetting Ch in

1 1 1 1 1 0 0 0

Specifying FhSetting 8h in

SO

DATA

Reading data from

address Fh

Writing data to

in the

the Transfer

Format

in the

the Transfer

Format

address Fh

Address

Pointer

Address

Pointer

Register

Data transfer from the host

Data transfer from the RTCs

The reading and writing data transfer formats correspond to the settings in the transfer format register as shown

in the table below.

1 Byte

8h

(1,0,0,0)

Burst

0h

(0,0,0,0)

Writing data

transfer

Reading data

transfer

Ch

(1,1,0,0)

4h

(0,1,0,0)

12345

Rev.2.06

- 24 -

R2043K/T

ꢁ

Considerations in Reading and Writing Time Data under special condition

Any carry to the second digits in the process of reading or writing time data may cause reading or writing

erroneous time data. For example, suppose a carry out of 13:59:59 into 14:00:00 occurs in the process of

reading time data in the middle of shifting from the minute digits to the hour digits. At this moment, the second

digits, the minute digits, and the hour digits read 59 seconds, 59 minutes, and 14 hours, respectively (indicating

14:59:59) to cause the reading of time data deviating from actual time virtually 1 hour. A similar error also

occurs in writing time data. To prevent such errors in reading and writing time data, the R2043K/T has the

function of temporarily locking any carry to the second digits during the high interval of the CE pin and unlocking

such a carry in its high to low transition. Note that a carry to the second digits can be locked for only 1 second,

during which time the CE pin should be driven low.

13:59:59

14:00:00

14:00:01

Actual time

CE

Max.62µs

14:00:00

13:59:59

14:00:01

Time counts

within RTC

The effective use of this function requires the following considerations in reading and writing time data:

(1) Hold the CE pin high in each session of reading or writing time data.

(2) Ensure that the high interval of the CE pin lasts within 1 second. Should there be any possibility of the host

going down in the process of reading or writing time data, make arrangements in the peripheral circuitry as to

drive the CE pin low or open at the moment that the host actually goes down.

(3) Leave a time span of 31µs or more from the low to high transition of the CE pin to the start of access to

addresses 0h to 6h in order that any ongoing carry of the time digits may be completed within this time span.

(4) Leave a time span of 62µs or more from the high to low transition of the CE pin to its low to high transition in

order that any ongoing carry of the time digits during the high interval of the CE pin may be adjusted within this

time span.

The considerations listed in (1), (3), and (4) above are not required when the process of reading or writing time

data is obviously free from any carry of the time digits.

(e.g. reading or writing time data in synchronization with the periodic interrupt function in the level mode or the

alarm interrupt function).

Good and bad examples of reading and writing time data are illustrated on the next page.

12345

Rev.2.05

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R2043K/T

Good Example

Any address other than addresses 0h to 6h

permits of immediate reading or writing without

requiring a time span of 31 µs.

Time span of 31µs or more

CE

SI

SO

F4h

DATA

Address Pointer

Reading from

Address Fh

(control2)

Reading from

Address 0h

(sec.)

Reading from

Address 1h

(min.)

Reading from

Address 2h

(hr.)

= Fh

Transfer Format

Register = 4h

Bad Example (1)

(Where the CE pin is once driven low in the process of reading time data)

31µs or more

CE

SI

0Ch

14h

Data

SO

Data

Address Pointer

= 0h

Address Pointer

= 1h

Reading from

Address 0h

(sec.)

Reading from

Address 1h

(min.)

Reading from

Address 2h

(hr.)

Transfer Format

Register = Ch

Transfer Format

Register = 4h

Bad Example (2)

(Where a time span of less than 31µs is left until the start of the process of writing time data)

Time span of less than 31µs

CE

SI

F0h

Data

SO

Address Pointer

= Fh

Writing to

Address Fh

(contorl2)

Writing to

Address 0h

(sec.)

Writing to

Address 1h

(min.)

Writing to

Address 2h

(hr.)

Transfer Format

Register = 0h

Bad Example (3)

(Where a time span of less than 61µs is left between the adjacent processes of reading time data)

Less than 62µs

CE

0Ch

SI

0Ch

SO

Data

Address Pointer

= 0h

Address Pointer

= 0h

Reading from

Address 0h

(sec.)

Reading from

Transfer Format

Register = Ch

Transfer Format Address 0h

Register = Ch (sec.)

0Ch

Data transfer from the host

Data

Data transfer from RTCs

12345

Rev.2.06

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R2043K/T

ꢀ Configuration of Oscillation Circuit and Correction of Time Count Deviations

ꢁ

Configuration of Oscillation Circuit

Typical externally-equipped element

X’tal : 32.768kHz

OSCIN

(R1=50kΩ typ)

32kHz

CG

CD

Oscillator

Circuit

(CL=6pF to 9pF)

Standard values of internal elements

CG,CD 10pF typ

OSCOUT

A

The oscillation circuit is driven at a constant voltage of approximately 1.1v relative to the level of the VSS pin

input. As such, it is configured to generate an oscillating waveform with a peak-to-peak voltage on the order of

1.1v on the positive side of the VSS pin input.

< Considerations in Handling Crystal Oscillators >

Generally, crystal oscillators have basic characteristics including an equivalent series resistance (R1) indicating

the ease of their oscillation and a load capacitance (CL) indicating the degree of their center frequency.

Particularly, crystal oscillators intended for use in the R2043K/T are recommended to have a typical R1 value of

50kΩ and a typical CL value of 6 to 9pF. To confirm these recommended values, contact the manufacturers of

crystal oscillators intended for use in these particular models.

< Considerations in Installing Components around the Oscillation Circuit >

1)

2)

Install the crystal oscillator in the closest possible vicinity to the real-time clock ICs.

Avoid laying any signal lines or power lines in the vicinity of the oscillation circuit (particularly in the area

marked "A" in the above figure).

3) Apply the highest possible insulation resistance between the OSCIN and OSCOUT pins and the printed

circuit board.

4)

5)

Avoid using any long parallel lines to wire the OSCIN and OSCOUT pins.

Take extreme care not to cause condensation, which leads to various problems such as oscillation halt.

< Other Relevant Considerations >

1)

For external input of 32.768-kHz clock pulses to the OSCIN pin:

DC coupling: Prohibited due to an input level mismatch.

AC coupling: Permissible except that the oscillation halt sensing circuit does not guarantee perfect

operation because it may cause sensing errors due to such factors as noise.

To maintain stable characteristics of the crystal oscillator, avoid driving any other IC through 32.768-kHz

clock pulses output from the OSCOUT pin.

2)

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Rev.2.05

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R2043K/T

ꢁ

Measurement of Oscillation Frequency

VDD

OSCIN

32768Hz

OSCOUT

32KOUT

VSS

Frequency

Counter

* 1) The R2043K/T is configured to generate 32.768-kHz clock pulses for output from the 32KOUT pin.

* 2) A frequency counter with 6 (more preferably 7) or more digits on the order of 1ppm is recommended

for use in the measurement of the oscillation frequency of the oscillation circuit.

ꢁ

Adjustment of Oscillation frequency

The oscillation frequency of the oscillation circuit can be adjusted by varying procedures depending on the usage

of Model R2043K/T in the system into which they are to be built and on the allowable degree of time count errors.

The flow chart below serves as a guide to selecting an optimum oscillation frequency adjustment procedure for

the relevant system.

Start

YES

Allowable time count precision on order of oscillation

frequency variations of crystal oscillator (*1) plus

Use 32-kHz

Course (A)

Course (B)

Course (C)

NO

clock output?

frequency variations of RTC (*2)?

(*3)

YES

Use 32-kHz clock output without regard

to its frequency precision

NO

YES

NO

Allowable time count precision on order of oscillation

frequency variations of crystal oscillator (*1) plus

Course (D)

frequency variations of RTC (*2)?

(*3)

* 1) Generally, crystal oscillators for commercial use are classified in terms of their center frequency

depending on their load capacitance (CL) and further divided into ranks on the order of ±10, ±20, and

±50ppm depending on the degree of their oscillation frequency variations.

* 2) Basically, Model R2043K/T is configured to cause frequency variations on the order of ±5 to ±10ppm

at 25°C.

* 3) Time count precision as referred to in the above flow chart is applicable to normal temperature and

actually affected by the temperature characteristics and other properties of crystal oscillators.

12345

Rev.2.06

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R2043K/T

Course (A)

When the time count precision of each RTC is not to be adjusted, the crystal oscillator intended for use in that

RTC may have any CL value requiring no presetting. The crystal oscillator may be subject to frequency

variations which are selectable within the allowable range of time count precision. Several crystal oscillators

and RTCs should be used to find the center frequency of the crystal oscillators by the method described in "P.28

ꢁ Adjustment of Oscillation frequency" and then calculate an appropriate oscillation adjustment value by the

method described in "P.31 ꢁ Oscillation Adjustment Circuit" for writing this value to the R2043K/T.

Course (B)

When the time count precision of each RTC is to be adjusted within the oscillation frequency variations of the

crystal oscillator plus the frequency variations of the real-time clock ICs, it becomes necessary to correct

deviations in the time count of each RTC by the method described in " P.31 ꢁ Oscillation Adjustment Circuit".

Such oscillation adjustment provides crystal oscillators with a wider range of allowable settings of their oscillation

frequency variations and their CL values. The real-time clock IC and the crystal oscillator intended for use in

that real-time clock IC should be used to find the center frequency of the crystal oscillator by the method

described in " P28 ꢁ Measurement of Oscillation Frequency " and then confirm the center frequency thus

found to fall within the range adjustable by the oscillation adjustment circuit before adjusting the oscillation

frequency of the oscillation circuit. At normal temperature, the oscillation frequency of the oscillator circuit can

be adjusted by up to approximately ±0.5ppm.

Course (C)

Course (C) together with Course (D) requires adjusting the time count precision of each RTC as well as the

frequency of 32.768-kHz clock pulses output from the 32KOUT pin. Normally, the oscillation frequency of the

crystal oscillator intended for use in the RTCs should be adjusted by adjusting the oscillation stabilizing

capacitors CG and CD connected to both ends of the crystal oscillator. The R2043K/T, which incorporate the

CG and the CD, require adjusting the oscillation frequency of the crystal oscillator through its CL value.

Generally, the relationship between the CL value and the CG and CD values can be represented by the following

equation:

CL = (CG × CD)/(CG + CD) + CS where "CS" represents the floating capacity of the printed circuit board.

The crystal oscillator intended for use in the R2043K/T is recommended to have the CL value on the order of 6 to

9pF. Its oscillation frequency should be measured by the method described in " P.28 ꢁ Measurement of

Oscillation Frequency ". Any crystal oscillator found to have an excessively high or low oscillation frequency

(causing a time count gain or loss, respectively) should be replaced with another one having a smaller and

greater CL value, respectively until another one having an optimum CL value is selected. In this case, the bit

settings disabling the oscillation adjustment circuit (see " P.31 ꢁ Oscillation Adjustment Circuit") should be

written to the oscillation adjustment register.

Incidentally, the high oscillation frequency of the crystal oscillator can also be adjusted by adding an external

oscillation stabilization capacitor CGOUT or/and CDOUT as illustrated in the diagram below.

*1) The CGOUT or/and CDOUT should have a

capacitance ranging from 0 to 6 pF.

OSCIN

CG

RD

Oscillator

Circuit

32kHz

OSCOUT

CDOUT

CGOUT

CD

However, if adding CGOUT and/or CDOUT, Time keeping Voltage and Current will be worse, and it will be hard

to oscillate. For reference, the data of Time keeping voltage and current when adding CGOUT=CDOUT=5pF

are shown in the table below.

(Topt=-40 to 85°C, VSS=0v)

Vclk

Item

Time Keeping

Voltage

Condition

CGout=CDout=5pF

Min.

1.15

TYP.

MAX.

5.5

UNITS

V

IDD

Time Keeping

Current

VDD=3V, CE=OPEN, Output=OPEN

32KOUT=OFF

0.55

1.20

µA

CGout=CDout=5pF

12345

Rev.2.05

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R2043K/T

Course (D)

It is necessary to select the crystal oscillator in the same manner as in Course (C) as well as correct errors

in the time count of each RTC in the same manner as in Course (B) by the method described in " P.31

Oscillation Adjustment Circuit ".

ꢁ

12345

Rev.2.06

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R2043K/T

ꢁ

Oscillation Adjustment Circuit

The oscillation adjustment circuit can be used to correct a time count gain or loss with high precision by varying

the number of 1-second clock pulses once per 20 seconds or 60 seconds. When DEV bit in the Oscillation

Adjustment Register is set to 0, R2043K/T varies number of 1-second clock pulses once per 20 seconds. When

DEV bit is set to 1, R2043K/T varies number of 1-second clock pulses once per 60 seconds. The oscillation

adjustment circuit can be disabled by writing the settings of "*, 0, 0, 0, 0, 0, *" ("*" representing "0" or "1") to the

F6, F5, F4, F3, F2, F1, and F0 bits in the oscillation adjustment circuit. Conversely, when such oscillation

adjustment is to be made, an appropriate oscillation adjustment value can be calculated by the equation below

for writing to the oscillation adjustment circuit.

(1) When Oscillation Frequency (* 1) Is Higher Than Target Frequency (* 2) (Causing Time Count Gain)

When DEV=0:

Oscillation adjustment value (*3) = (Oscillation frequency - Target Frequency + 0.1)

Oscillation frequency × 3.051 × 10^-6

≈ (Oscillation Frequency – Target Frequency) × 10 + 1

When DEV=1:

Oscillation adjustment value (*3) = (Oscillation frequency - Target Frequency + 0.0333)

Oscillation frequency × 1.017 × 10^-6

≈ (Oscillation Frequency – Target Frequency) × 30 + 1

* 1) Oscillation frequency:

Frequency of clock pulse output from the 32KOUT pin at normal temperature in the manner described

in " P.28 ꢁ Measurement of Oscillation Frequency ".

* 2) Target frequency:

Desired frequency to be set. Generally, a 32.768-kHz crystal oscillator has such temperature

characteristics as to have the highest oscillation frequency at normal temperature. Consequently,

the crystal oscillator is recommended to have target frequency settings on the order of 32.768 to

32.76810 kHz (+3.05ppm relative to 32.768 kHz). Note that the target frequency differs depending

on the environment or location where the equipment incorporating the RTC is expected to be

operated.

* 3) Oscillation adjustment value:

Value that is to be finally written to the F0 to F6 bits in the Oscillation Adjustment Register and is

represented in 7-bit coded decimal notation.

(2) When Oscillation Frequency Is Equal To Target Frequency (Causing Time Count neither Gain nor Loss)

Oscillation adjustment value = 0, +1, -64, or –63

(3) When Oscillation Frequency Is Lower Than Target Frequency (Causing Time Count Loss)

When DEV=0:

Oscillation adjustment value = (Oscillation frequency - Target Frequency)

Oscillation frequency × 3.051 × 10^-6

≈ (Oscillation Frequency – Target Frequency) × 10

When DEV=1:

Oscillation adjustment value = (Oscillation frequency - Target Frequency)

Oscillation frequency × 1.017 × 10^-6

≈ (Oscillation Frequency – Target Frequency) × 30

Oscillation adjustment value calculations are exemplified below

(A) For an oscillation frequency = 32768.85Hz and a target frequency = 32768.05Hz

When setting DEV bit to 0:

Oscillation adjustment value = (32768.85 - 32768.05 + 0.1) / (32768.85 × 3.051 × 10^-6)

≈ (32768.85 - 32768.05) × 10 + 1

= 9.001 ≈ 9

In this instance, write the settings (DEV,F6,F5,F4,F3,F2,F1,F0)=(0,0,0,0,1,0,0,1) in the oscillation adjustment

register. Thus, an appropriate oscillation adjustment value in the presence of any time count gain represents a

distance from 01h.

When setting DEV bit to 1:

12345

Rev.2.05

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R2043K/T

Oscillation adjustment value = (32768.85 - 32768.05 + 0.0333) / (32768.85 × 1.017 × 10^-6)

≈ (32768.85 - 32768.05) × 30 + 1

= 23.51 ≈ 24

In this instance, write the settings (DEV,F6,F5,F4,F3,F2,F1,F0)=(1,0,0,1,1,0,0,0) in the oscillation adjustment

register.

(B) For an oscillation frequency = 32762.22Hz and a target frequency = 32768.05Hz

When setting DEV bit to 0:

Oscillation adjustment value = (32762.22 - 32768.05) / (32762.22 × 3.051 × 10^-6)

≈ (32762.22 - 32768.05) × 10

= -58.325 ≈ -58

To represent an oscillation adjustment value of - 58 in 7-bit coded decimal notation, subtract 58 (3Ah) from 128

(80h) to obtain 46h. In this instance, write the settings of (DEV,F6,F5,F4,F3,F2,F1,F0) = (0,1,0,0,0,1,1,0) in the

oscillation adjustment register. Thus, an appropriate oscillation adjustment value in the presence of any time

count loss represents a distance from 80h.

When setting DEV bit to 1:

Oscillation adjustment value = (32762.22 - 32768.05) / (32762.22 × 1.017 × 10^-6)

≈ (32762.22 - 32768.05) × 30

= -174.97 ≈ -175

Oscillation adjustment value can be set from -62 to 63. Then, in this case, Oscillation adjustment value is out of

range.

(4) Difference between DEV=0 and DEV=1

Difference between DEV=0 and DEV=1 is following,

DEV=0

DEV=1

Maximum value range

Minimum resolution

-189.2ppm to 189.2ppm

3ppm

--62ppm to 63ppm

1ppm

Notes:

1)

Oscillation adjustment does not affect the frequency of 32.768-kHz clock pulses output from the

32KOUT pin.

2)

If following 3 conditions are completed, actual clock adjustment value could be different from target

adjustment value that set by oscillator adjustment function.

1. Using oscillator adjustment function

2. Access to R2043K/T at random, or synchronized with external clock that has no relation to R2043K/T,

or synchronized with periodic interrupt in pulse mode.

3. Access to R2043K/T more than 2 times per each second on average.

For more details, please contact to Ricoh.

ꢁ

How to evaluate the clock gain or loss

The oscillator adjustment circuit is configured to change time counts of 1 second on the basis of the settings of

the oscillation adjustment register once in 20 seconds or 60 seconds. The oscillation adjustment circuit does

not effect the frequency of 32768Hz-clock pulse output from the 32KOUT pin. Therefore, after writing the

oscillation adjustment register, we cannot measure the clock error with probing 32KOUT clock pulses. The way

to measure the clock error as follows:

(1) Output a 1Hz clock pulse of Pulse Mode with interrupt pin

Set (0,0,x,x,0,0,1,1) to Control Register 1 at address Eh.

(2) After setting the oscillation adjustment register, 1Hz clock period changes every 20seconds ( or every 60

seconds) like next page figure.

12345

Rev.2.06

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R2043K/T

1Hz clock pulse

T0

T1

19 times

1 time

Measure the interval of T0 and T1 with frequency counter. A frequency counter with 7 or more digits is

recommended for the measurement.

(3) Calculate the typical period from T0 and T1

T = (19×T0+1×T1)/20

Calculate the time error from T.

12345

Rev.2.05

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R2043K/T

ꢀ Power-on Reset, Oscillation Halt Sensing, and Supply Voltage Monitoring

ꢁ

PON, /XST, and VDET

The power-on reset circuit is configured to reset control register1, 2, and clock adjustment register when VDD

power up from 0v. The oscillation halt sensing circuit is configured to record a halt on oscillation by 32.768-kHz

clock pulses. The supply voltage monitoring circuit is configured to record a drop in supply voltage below a

threshold voltage of 1.6 or 1.3v.

Each function has a monitor bit. I.e. the PON bit is for the power-on reset circuit, and /XST bit is for the

oscillation halt sensing circuit, and VDET is for the supply voltage monitoring circuit. PON and VDET bits are

activated to “H”. However, /XST bit is activated to “L”. The PON and VDET accept only the writing of 0, but

/XST accepts the writing of 0 and 1. The PON bit is set to 1, when VDD power-up from 0V, but VDET is set to 0,

and /XST is indefinite.

The functions of these three monitor bits are shown in the table below.

PON

/XST

VDET

Function

Monitoring

power-on reset function

for

the

Monitoring for the

oscillation halt sensing

function

a drop in supply voltage

below a threshold voltage

of 1.6 or 1.3v

Address

Activated

When VDD power

up from 0v

D4 in Address Fh

High

1

D5 in Address Fh

Low

indefinite

D6 in Address Fh

High

0

accept the writing

0 only

Both 0 and 1

0 only

The relationship between the PON, /XST, and VDET is shown in the table below.

PON

0

/XST

0

VDET

0

Conditions of supply voltage and

oscillation

Halt on oscillation, but no drop in

VDD supply voltage below threshold

voltage

Condition of oscillator, and back-up

status

Halt on oscillation cause of

condensation etc.

0

1

0

1

*

1

0

1

*

Halt on oscillation and drop in VDD

supply voltage below threshold

voltage, but no drop to 0V

No drop in VDD supply voltage below

threshold voltage and no halt in

oscillation

Drop in VDD supply voltage below

threshold voltage and no halt on

oscillation

Halt on oscillation cause of drop in

back-up battery voltage

Normal condition

No halt on oscillation, but drop in

back-up battery voltage

Drop in supply voltage to 0v

Power-up from 0v,

Threshold voltage (1.6v or 1.3v)

VDD

32768Hz Oscillation

Power-on reset flag

(PON)

Oscillation halt

sensing flag (/XST)

Supply voltage

monitor flag (VDET)

VDET←0

/XST←1

PON←0

VDET←0

/XST←1

PON←1

VDET←0

Internal initialization

/XST←1

Internal initialization

period (1 to 2 sec.)

PON←0

When the PON bit is set to 1 in the control register 2, the DEV, F6 to F0, WALE, DALE, /12⋅24, /CLEN2, TEST,

12345

Rev.2.06

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R2043K/T

CT2, CT1, CT0, VDSL, VDET, /CLEN1, CTFG, WAFG, and DAFG bits are reset to 0 in the oscillation adjustment

register, the control register 1, and the control register 2. The PON bit is also set to 1 at power-on from 0v.

< Considerations in Using Oscillation Halt Sensing Circuit >

Be sure to prevent the oscillation halt sensing circuit from malfunctioning by preventing the following:

1) Instantaneous power-down on the VDD

2) Condensation on the crystal oscillator

3) On-board noise to the crystal oscillator

4) Applying to individual pins voltage exceeding their respective maximum ratings

In particular, note that the /XST bit may fail to be set to 0 in the presence of any applied supply voltage as

illustrated below in such events as backup battery installation. Further, give special considerations to prevent

excessive chattering in the oscillation halt sensing circuit.

VDD

12345

Rev.2.05

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R2043K/T

ꢁ

Voltage Monitoring Circuit

The supply monitoring circuit is configured to conduct a sampling operation during an interval of 7.8ms per

second to check for a drop in supply voltage below a threshold voltage of 1.6 or 1.3v for the VDSL bit setting of 0

(the default setting) or 1, respectively, in the Control Register 2, thus minimizing supply current requirements as

illustrated in the timing chart below. This circuit suspends a sampling operation once the VDET bit is set to 1 in

the Control Register 2. The supply voltage monitor is useful for back-up battery checking.

VDD

1.6v or 1.3v

7.8ms

PON

Internal

initialization

period

1s

(1 to 2sec.)

Sampling timing for

VDD supply voltage

VDET

(D6 in Address Fh)

VDET←0

PON←0

VDET←0

12345

Rev.2.06

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R2043K/T

ꢀ Alarm and Periodic Interrupt

The R2043K/T incorporates the alarm interrupt circuit and the periodic interrupt circuit that are configured to

generate alarm signals and periodic interrupt signals for output from the /INTR pin as described below.

(1) Alarm Interrupt Circuit

The alarm interrupt circuit is configured to generate alarm signals for output from the /INTR, which is driven low

(enabled) upon the occurrence of a match between current time read by the time counters (the day-of-week,

hour, and minute counters) and alarm time preset by the alarm registers (the Alarm_W registers intended for the

day-of-week, hour, and minute digit settings and the Alarm_D registers intended for the hour and minute digit

settings).

(2) Periodic Interrupt Circuit

The periodic interrupt circuit is configured to generate either clock pulses in the pulse mode or interrupt signals in

the level mode for output from the /INTR pin depending on the CT2, CT1, and CT0 bit settings in the control

register 1.

The above two types of interrupt signals are monitored by the flag bits (i.e. the WAFG, DAFG, and CTFG bits in

the Control Register 2) and enabled or disabled by the enable bits (i.e. the WALE, DALE, CT2, CT1, and CT0

bits in the Control Register 1) as listed in the table below.

Flag bits

Enable bits

Alarm_W

WAFG

WALE

(D1 at Address Fh)

(D7 at Address Eh)

Alarm_D

DAFG

DALE

(D0 at Address Fh)

CTFG

(D6 at Address Eh)

CT2=CT1=CT0=0

Peridic interrupt

(D2 at Address Fh)

(These bit setting of “0” disable the Periodic Interrupt)

(D2 to D0 at Address Eh)

*

At power-on, when the WALE, DALE, CT2, CT1, and CT0 bits are set to 0 in the Control Register 1,

the /INTR pin is driven high (disabled).

When two types of interrupt signals are output simultaneously from the /INTR pin, the output from the

/INTR pin becomes an OR waveform of their negative logic.

Example: Combined Output to /INTR Pin Under Control of

/ALARM_D and Periodic Interrupt

/Alarm_D

Periodic Interrupt

/INTR

In this event, which type of interrupt signal is output from the /INTR pin can be confirmed by reading the

DAFG, and CTFG bit settings in the Control Register 2.

ꢁ

Alarm Interrupt

The alarm interrupt circuit is controlled by the enable bits (i.e. the WALE and DALE bits in the Control Register 1)

and the flag bits (i.e. the WAFG and DAFG bits in the Control Register 2). The enable bits can be used to

enable this circuit when set to 1 and to disable it when set to 0. When intended for reading, the flag bits can be

used to monitor alarm interrupt signals. When intended for writing, the flag bits will cause no event when set to

1 and will drive high (disable) the alarm interrupt circuit when set to 0.

The enable bits will not be affected even when the flag bits are set to 0. In this event, therefore, the alarm

interrupt circuit will continue to function until it is driven low (enabled) upon the next occurrence of a match

between current time and preset alarm time.

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Rev.2.05

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R2043K/T

The alarm function can be set by presetting desired alarm time in the alarm registers (the Alarm_W Registers for

the day-of-week digit settings and both the Alarm_W Registers and the Alarm_D Registers for the hour and

minute digit settings) with the WALE and DALE bits once set to 0 and then to 1 in the Control Register 1. Note

that the WALE and DALE bits should be once set to 0 in order to disable the alarm interrupts circuit upon the

coincidental occurrence of a match between current time and preset alarm time in the process of setting the

alarm function.

Interval (1min.) during which a match

between current time and preset alarm time

occurs

/INTR

current time =

preset alarm time

current time =

preset alarm time

WALE←1

(DALE)

WALE←1

(DALE)

WALE←0

(DALE)

/INTR

current time =

preset alarm time

current time =

preset alarm time

WALE←1

(DALE)

WAFG←0

(DAFG)

After setting WALE(DALW) to 0, Alarm registers is set to current time, and WALE(DALE) is set to 1, /INTR will be

not driven to “L” immediately, /INTR will be driven to “L” at next alarm setting time.

ꢁ

Periodic Interrupt

Setting of the periodic selection bits (CT2 to CT0) enables periodic interrupt to the CPU. There are two waveform

modes: pulse mode and level mode. In the pulse mode, the output has a waveform duty cycle of around 50%.

In the level mode, the output is cyclically driven low and, when the CTFG bit is set to 0, the output is return to

High (OFF).

CT2

CT1

CT0

Description

Wave form mode

-

Interrupt Cycle and Falling Timing

OFF(H)

0

1

0

1

0

1

0

1

0

(Default)

-

Fixed at “L”

2Hz(Duty50%)

1Hz(Duty50%)

Pulse Mode *1)

Level Mode *2)

Once per 1 second (Synchronized with

Second counter increment)

Once per 1 minute (at 00 seconds of every

Minute)

Once per hour (at 00 minutes and 00

Seconds of every hour)

1

0

1

0

1

Level Mode *2)

Once per month (at 00 hours, 00 minutes,

and 00 seconds of first day of every month)

*1) Pulse Mode:

2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second counter as

illustrated in the timing chart below.

CTFG Bit

/INTR Pin

Approx. 92µs

(Increment of second counter)

Rewriting of the second counter

12345

Rev.2.06

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R2043K/T

In the pulse mode, the increment of the second counter is delayed by approximately 92 µs from the

falling edge of clock pulses. Consequently, time readings immediately after the falling edge of clock

pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second.

Rewriting the second counter will reset the other time counters of less than 1 second, driving the

/INTR pin low.

*2) Level Mode:

Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1

hour, and 1 month. The increment of the second counter is synchronized with the falling edge of

periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of 1

second are output in synchronization with the increment of the second counter as illustrated in the

timing chart below.

CTFG Bit

/INTR Pin

Setting CTFG bit to 0

(Increment of

second counter)

(Increment of

second counter)

(Increment of

second counter)

*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. as

follows:

Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of ±3.784ms. For

example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%.

Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of ±3.784 ms.

ꢁ

32-kHz CLOCK OUTPUT

For the R2043K/T, 32.768-kHz clock pulses are output from the 32KOUT pin when either the /CLEN1 bit in

the Control Register 2 or the /CLEN2 bit in the Control Register 1 is set to 0. When both the /CLEN1 and

/CLEN2 bits are set to 0, the 32KOUT pin output is driven high (off).

/CLEN1

/CLEN2

32KOUT PIN

(N-channel Open Drain)

OFF(H)

(D3 at Address Fh)

(D4 at Address Eh)

1

0(Default)

*

Clock pulses

0(Default)

The 32KOUT pin output is synchronized with the /CLEN1 and /CLEN2 bit settings as illustrated in the timing

chart below.

/CLEN1or2

32KOUT PIN

Max.62.0µs

12345

Rev.2.05

- 39 -

R2043K/T

ꢀ Typical Applications

ꢁ

Typical Power Circuit Configurations

Sample circuit configuration 1

*1) Install bypass capacitors for high-frequency

and low-frequency applications in parallel in

close vicinity to the R2043K/T.

System power supply

OSCIN

32768Hz

OSCOUT

VDD

*1)

VSS

Sample circuit configuration 2

OSCIN

*1) When using an OR diode as a power supply for

the R2043K/T ensure that voltage exceeding

the absolute maximum rating of VDD+0.3v is

not applied the 32KOUT pin.

System power supply

32768Hz

OSCOUT

VDD

*1)

Primary

Battery

VSS

System power supply

OSCIN

32768Hz

OSCOUT

VDD

*1)

Secondary

Battery

VSS

12345

Rev.2.06

- 40 -

R2043K/T

ꢁ

Connection of /INTR and 32KOUT Pin

The /INTR pin follows the N-channel open drain output logic and contains no protective diode on the power

supply side. As such, it can be connected to a pull-up resistor of up to 5.5v regardless of supply voltage.

The 32KOUT pin follows the N-channel open drain output logic, too. However, it contains protective diode on the

power supply side. As such, it cannot be connected to a pull-up resistor over VDD+0.3v. Such connection

involves considerations for the supply current requirements of a pull-up resistor, which can be roughly calculated

by the following equation:

I = 0.5 × (VDD or VCC) / Rp

System power supply

(VDD)

*1) Depending on whether the /INTR or 32KOUT

pins are to be used during battery backup, it

should be connected to a pull-up resistor at

the following different positions:

(1) Position A in the left diagram when it is not to

be used during battery backup.

(2) Position B in the left diagram when it is to be

used during battery backup.

A

/INTR or 32KOUT

*1)

B

OSCIN

Backup power supply

(VCC)

32768Hz

OSCOUT

VSB

VSS

ꢁ

Connection of CE Pin

Connection of the CE pin requires the following considerations:

1) The CE pin is configured to enable the oscillation halt sensing circuit only when driven low. As such, it

should be driven low or open at power-on from 0v.

2) The CE pin should also be driven low or open immediately upon the host going down (see "P.25 ꢁ

Considerations in Reading and Writing Time Data under special condition").

SCLK

I/O

CONTROL

SI

Lower limit operating

voltage for the CPU

SO

VDD

Backup power supply

CE

0.2×VDD

Min.0µs

12345

Rev.2.05

- 41 -

R2043K/T

ꢁ

Connection With 3-Wire Serial Interface Bus

To connect the R2043K/T with 3-wire serial interface bus, shorten the SI and SO pins and connect them to the

data line as shown in the figure below.

CE0

CE1

CE

SCLK

Host

R2043

SCLK

DATA

SI

SO

CE

SCLK The other

Peripheral IC

SIO

12345

Rev.2.06

- 42 -

R2043K/T

ꢀ Typical Characteristics

Test circuit

X’tal : 32.768kHz

(R1=50kΩ typ)

(CL=6pF to 9pF)

Topt : 25°C

Output pins : Open

VDD

CGOUT

OSCIN

32768Hz

OSCOUT

CDOUT

Frequency

Counter

32KOUT

VSS

Timekeeping Current vs. Supply Voltage

(with no 32kHz clock output)

Timekeeping Current vs. Supply Voltage

(with 32kHz clock output)

(CE=Open, Output=Open, Topt=25°C)

1

1.4

1.2

0.8

1

(CGout, CDout)=(5pF, 5pF)

0.6

(CGout, CDout)=(5pF, 5pF)

0.8

0.6

0.4

(CGout, CDout)=(0pF, 0pF)

0.4

(CGout, CDout)=(0pF, 0pF)

0.2

0

0.2

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Supply Vlotage VDD(v)

Supply Voltage VDD(v)

CPU Access Current vs. SCLK Clock Frequency

(Output pins=Open, Topt=25°C, CGout=CDout=0pF)

Timekeeping Current vs. Operating Temperature

(CE=Open, Output pins=Open, CGout=CDout=0pF)

80

70

60

1.4

1.2

1

VDD=5v

50

0.8

with 32kHz clock output

0.6

40

30

VDD=3v

0.4

20

10

0

with no 32kHz clock output

0.2

0

200

400

600

800 1000

-50 -25

0

25

50

75 100

SCLK Clock Frequency (kHz)

Operating Temperature Topt(Celcius)

12345

Rev.2.05

- 43 -

R2043K/T

Oscillation Frequency Deviation vs. External CF, CD

Oscillation Frequency Deviation vs. Supply Voltage

(VDD=3v, Topt=25°C, CGout=CDout=0pF as standard)

(Topt=25°C,VDD=3v as standard)

0

-10

-20

5

4

3

2

1

CDout=0pF

CDout=5pF

-30

-40

-50

-60

-70

-80

-90

-100

0

-1

-2

-3

-4

-5

0

5

10

15

20

0

1

2

3

4

5

6

External CG (pF)

Supply Voltage VDD (v)

Oscillation Frequency Deviation vs.

Operating Temperature

VOL vs. IOL (32KOUT)

(Topt=25°C)

(VDD=3v, Topt=25°C as standard)

7

6

5

4

3

2

1

0

20

0

VDD=5v

VDD=3v

-20

-40

-60

-80

-100

-120

VDD=1.5v

-60 -40 -20 0 20 40 60 80 10

0

0.1

0.2

0.3

0.4

0.5

Operating TemperatureTopt(Celsius)

VOL (v)

VOL vs. IOL (/INTR pin)

(Topt=25°C)

30

25

20

15

10

5

VDD=5v

VDD=3v

VDD=1.5v

0

0.1

0.2

0.3

0.4

0.5

VOL(v)

12345

Rev.2.06

- 44 -

R2043K/T

ꢀ Typical Software-based Operations

ꢁ

Initialization at Power-on

Start

*1)

Power-on

*2)

*4)

No

PON=1?

Yes

*3)

VDET=0?

Yes

No

Set Oscillation Adjustment

Register and Control

Register 1 and 2, etc.

Warning Back-up

Battery Run-down

*1)

*2)

After power-on from 0 volt, the start of oscillation and the process of internal initialization require a

time span on 1to 2seconds, so that access should be done after the lapse of this time span or more.

The PON bit setting of 0 in the Control Register 1 indicates power-on from backup battery and not

from 0v. For further details, see "P.34 ꢁ PON, /XST, and VDET".

*3)

*4)

This step is not required when the supply voltage monitoring circuit is not used.

This step involves ordinary initialization including the Oscillation Adjustment Register and interrupt

cycle settings, etc.

ꢁ

Writing of Time and Calendar Data

*1)

CE ← H

*1) When writing to clock and calendar counters, do not drive CE to “L” until

all times from second to year have been written to prevent error in writing

time. (Detailed in "P.24 ꢁ Considerations in Reading and Writing

Time Data under special condition ".

*2)

Write to Time Counter and

Calendar Counter

*2) Any writing to the second counter will reset divider units lower than the

second digits.

*3)

CE ← L

*3) Take care so that process from CE driving to “H” to driving to “L” will be

complete within 1.0sec. (Detailed in "P.24 ꢁ Adjustment of Oscillation

frequency".

The R2043K/T may also be initialized not at power-on but in the process

of writing time and calendar data.

12345

Rev.2.05

- 45 -

R2043K/T

ꢁ

Reading Time and Calendar Data

(1) Ordinary Process of Reading Time and Calendar Data

*1)

*1) When writing to clock and calendar counters, do not insert Stop Condition

CE ← H

until all times from second to year have been written to prevent error in

writing time. (Detailed "P.24 ꢁ Considerations in Reading and Writing

Time Data under special condition".

Read from Time Counter

and Calendar Counter

*2) Take care so that process from Start Condition to Stop Condition will be

complete within 0.5sec. (Detailed in "P.24 ꢁ Considerations in

Reading and Writing Time Data under special condition".

*2)

CE ← L

(2) Basic Process of Reading Time and Calendar Data with Periodic Interrupt Function

*1) This step is intended to select the level mode as a

Set Periodic Interrupt

Cycle Selection Bits

*1)

waveform mode for the periodic interrupt function.

*2) This step must be completed within 1.0 second.

*3) This step is intended to set the CTFG bit to 0 in the

Control Register 2 to cancel an interrupt to the CPU.

Generate Interrupt in CPU

No

Other Interrupt

Processes

CTFG=1?

Yes

*2)

Read from Time Counter

and Calendar Counter

*3)

Control Register 2

←(X1X1X011)

12345

Rev.2.06

- 46 -

R2043K/T

(3) Applied Process of Reading Time and Calendar Data with Periodic Interrupt Function

Time data need not be read from all the time counters when used for such ordinary purposes as time count

indication. This applied process can be used to read time and calendar data with substantial reductions in the

load involved in such reading.

For Time Indication in "Day-of-Month, Day-of-week, Hour, Minute, and Second" Format:

Control Register 1←

(XXXX0100)

*1) This step is intended to select the level

mode as a waveform mode for the

periodic interrupt function.

Control Register 2←

*1)

(X1X1X011)

*2) This step must be completed within 1.0

sec.

*3) This step is intended to read time data

from all the time counters only in the

first session of reading time data after

writing time data.

*4) This step is intended to set the CTFG

bit to 0 in the Control Register 2 to

cancel an interrupt to the CPU.

Generate interrupt to CPU

CTFG=1?

Other interrupts

Processes

No

Yes

*2)

Sec.=00?

Yes

*3)

Read Min.,Hr.,Day,

and Day-of-week

Use previous Min.,Hr.,

Day, and Day-of-week data

*4)

Control Register 2←

(X1X1X011)

12345

Rev.2.05

- 47 -

R2043K/T

ꢁ

Interrupt Process

(1) Periodic Interrupt

Set Periodic Interrupt

Cycle Selection Bits

*1)

*1) This step is intended to select the level mode as a

waveform mode for the periodic interrupt function.

*2) This step is intended to set the CTFG bit to 0 in

the Control Register 2 to cancel an interrupt to the

CPU.

Generate Interrupt to CPU

No

Other Interrupt

Processes

CTFG=1?

Yes

Conduct

Periodic Interrupt

*2)

Control Register 2←

(X1X1X011)

(2) Alarm Interrupt

WALE or DALE←0

*1)

*1) This step is intended to once disable the alarm

interrupt circuit by setting the WALE or DALE bits to 0

in anticipation of the coincidental occurrence of a

match between current time and preset alarm time in

the process of setting the alarm interrupt function.

*2) This step is intended to enable the alarm interrupt

function after completion of all alarm interrupt

settings.

*3) This step is intended to once cancel the alarm

interrupt function by writing the settings of "X,1,X,

1,X,1,0,1" and "X,1,X,1,X,1,1,0" to the Alarm_W

Registers and the Alarm_D Registers, respectively.

Set Alarm Min., Hr., and

Day-of-week Registers

*2)

WALE or DALE←1

Generate Interrupt to CPU

No

Other Interrupt

Processes

WAFG or DAFG=1?

Yes

Conduct Alarm Interrupt

*3)

Control Register 2 ←

(X1X1X101)

12345

Rev.2.06

- 48 -


型号：	R2043K-E2
厂家：	RICOH ELECTRONICS DEVICES DIVISION
描述：	4-wire Serial Interface 4线串行接口计时器或实时时钟微控制器和处理器外围集成电路
文件：	总48页 (文件大小：467K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

R2043K-E2 [RICOH]

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