RT7257EN [RICHTEK]
3A, 17V, 340kHz Synchronous Step-Down Converter;
| 型号： | RT7257EN |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | 3A, 17V, 340kHz Synchronous Step-Down Converter |
| 文件： | 总15页 (文件大小：225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
智 新
Preliminary
RT7257E
SacPower
3A, 17V, 340kHz Synchronous Step-Down Converter
General Description
Features
z
1.5% High Accuracy Feedback Voltage
The RT7257E is a high efficiency, monolithic synchronous
step-down DC/DC converter that can deliver up to 3A
output current from a 4.5V to 17V input supply. The
RT7257E's current mode architecture and external
compensation allow the transient response to be
optimized over a wide range of loads and output capacitors.
Cycle-by-cycle current limit provides protection against
shorted outputs, and soft-start eliminates input current
surge during start-up. The RT7257E provides thermal
shutdown protection. The low current (<3μA) shutdown
mode provides output disconnection, enabling easy power
management in battery-powered systems. The RT7257E
is available in an SOP-8 (Exposed Pad) package.
z 4.5V to 17V Input Voltage Range
z 3A Output Current
z Integrated N-MOSFET Switches
z Current Mode Control
z Fixed Frequency Operation : 340kHz
z Output Adjustable from 0.8V to 15V
z Up to 95% Efficiency
z Programmable Soft-Start
z Stable with Low ESR Ceramic Output Capacitors
z Cycle-by-Cycle Over Current Protection
z Input Under Voltage Lockout
z Thermal Shutdown Protection
z RoHS Compliant and Halogen Free
Ordering Information
RT7257EN
Applications
z Wireless AP/Router
Package Type
SP : SOP-8 (Exposed Pad-Option 2)
z Set-Top-Box
z Industrial and Commercial Low Power Systems
z LCDMonitors and TVs
Lead Plating System
Z : ECO (Ecological Element with
Halogen Free and Pb free)
z Green Electronics/Appliances
z Point of Load Regulation of High-PerformanceDSPs
Note :
Richtek products are :
Pin Configurations
` RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes.
(TOP VIEW)
8
BOOT
VIN
SS
2
3
4
7
6
5
EN
GND
SW
COMP
FB
9
GND
Marking Information
SOP-8 (Exposed Pad)
For marking information, contact our sales representative
directly or through a Richtek distributor located in your
area.
http//www.sacpower.net
1
E-mail:nikozhong@hotmail.com
0755-83983280
系人: 先生
Preliminary
RT7257E
Typical Application Circuit
1
V
2
IN
VIN
BOOT
RT7257E
4.5V to 17V
C
100nF
C
BOOT
IN
L
10µF x 2
10µH
V
3
OUT
SW
3.3V
Chip Enable
R1
7
8
EN
SS
75k
C
OUT
5
6
FB
22µF x 2
C
C
C
R
SS
C
12k
R2
4.7nF
0.1µF
24k
4, 9 (Exposed Pad)
COMP
GND
C
P
Open
Table 1. Recommended Components Selection
VOUT (V) R1 (kΩ) R2 (kΩ) RC (kΩ) CC (nF)
L (μH)
22
COUT (μF)
8
27
62
3
11.8
24
12
24
18
12
8.2
3.6
3
4.7
4.7
4.7
4.7
4.7
4.7
4.7
22 x 2
22 x 2
22 x 2
22 x 2
22 x 2
22 x 2
22 x 2
5
15
10
6.8
3.6
3.6
3.6
3.3
2.5
1.5
1.2
1
75
25.5
10.5
12
12
24
12
3
2.7
Functional Pin Description
Pin No.
Pin Name
Pin Function
Bootstrap for High Side Gate Driver. Connect a 0.1μF or greater ceramic
capacitor from BOOT to SW pins.
1
BOOT
Input Supply Voltage, 4.5V to 17V. Must bypass with a suitably large ceramic
capacitor.
2
3
VIN
SW
Switch Node. Connect this pin to an external L-C filter.
4,
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
GND
9 (Exposed Pad)
Feedback Input. It is used to regulate the output of the converter to a set value
via an internal resistive voltage divider.
5
6
FB
Compensation Node. COMP is used to compensate the regulation control
loop. Connect a series RC network from COMP to GND. In some cases, an
additional capacitor from COMP to GND is required.
COMP
Enable Input. A logic high enables the converter; a logic low forces the
RT7257E into shutdown mode reducing the supply current to less than 3μA.
Attach this pin to VIN with a 100kΩ pull up resistor for automatic startup.
Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor
from SS to GND to set the soft-start period. A 0.1μF capacitor sets the
soft-start period to 13.5ms.
7
8
EN
SS
2
Preliminary
RT7257E
Function Block Diagram
VIN
Internal
Regulator
Oscillator
Current Sense
Amplifier
Slope Comp
Shutdown
Comparator
V
VA
VA
+
-
CC
Foldback
Control
1.2V
+
-
0.4V
+
BOOT
SW
Lockout
Comparator
-
110mΩ
90mΩ
S
Q
Q
UV
5k
Comparator
-
+
R
-
EN
+
1.8V
Current
GND
Comparator
V
CC
6µA
0.8V
+
+
-
EA
SS
FB
COMP
3
Preliminary
RT7257E
Absolute Maximum Ratings (Note 1)
z Supply Input Voltage, VIN ------------------------------------------------------------------------------------------ −0.3V to 20V
z Switch Voltage, SW ------------------------------------------------------------------------------------------------ −0.3V to (VIN + 0.3V)
z VBOOT − VSW ---------------------------------------------------------------------------------------------------------- −0.3V to 6V
z Other Pins Voltage ------------------------------------------------------------------------------------------------- −0.3V to 20V
z Power Dissipation, PD @ TA = 25°C
SOP-8 (Exposed Pad) --------------------------------------------------------------------------------------------- 1.333W
z Package Thermal Resistance (Note 2)
SOP-8 (Exposed Pad), θJA ---------------------------------------------------------------------------------------- 75°C/W
SOP-8 (Exposed Pad), θJC --------------------------------------------------------------------------------------- 15°C/W
z Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------- 260°C
z Junction Temperature ----------------------------------------------------------------------------------------------- 150°C
z Storage Temperature Range -------------------------------------------------------------------------------------- −65°C to 150°C
z ESD Susceptibility (Note 3)
HBM (Human Body Mode) ---------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ------------------------------------------------------------------------------------------------ 200V
Recommended Operating Conditions (Note 4)
z Supply Input Voltage, VIN ------------------------------------------------------------------------------------------ 4.5V to 17V
z Junction Temperature Range-------------------------------------------------------------------------------------- −40°C to 125°C
z Ambient Temperature Range-------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VIN = 12V, TA = 25°C, unless otherwise specified)
Parameter
Shutdown Supply Current
Supply Current
Symbol
Test Conditions
Min
--
Typ
0.5
0.8
0.8
Max
3
Unit
μA
mA
V
VEN = 0V
VEN = 3 V, VFB = 0.9V
--
1.2
Feedback Voltage
VFB
4.5V ≤ VIN ≤ 17V
0.788
0.812
Error Amplifier
GEA
ΔIC = ±10μA
--
--
--
940
110
90
--
--
--
μA/V
mΩ
Transconductance
High Side Switch
On-Resistance
Low Side Switch
On-Resistance
High Side Switch Leakage
Current
RDS(ON)1
RDS(ON)2
mΩ
VEN = 0V, VSW = 0V
--
--
0
10
--
μA
A
Upper Switch Current Limit
Min. Duty Cycle, VBOOT − VSW = 4.8V
5.1
4.7
340
100
COMP to Current Sense
Transconductance
GCS
--
--
A/V
kHz
kHz
Oscillation Frequency
fOSC1
fOSC2
300
--
380
--
Short Circuit Oscillation
Frequency
VFB = 0V
Maximum Duty Cycle
Minimum On Time
DMAX
tON
VFB = 0.7V
--
--
93
--
--
%
100
ns
To be continued
4
Preliminary
RT7257E
Parameter
Symbol
Test Conditions
Min
2
Typ
--
Max
5.5
0.4
4.5
--
Unit
Logic-High
Logic-Low
V
V
V
IH
EN Input Threshold
Voltage
V
--
--
IL
Input Under Voltage Lockout Threshold
V
V
Rising
3.8
--
4.2
320
6
V
UVLO
IN
Input Under Voltage Lockout Hysteresis ΔV
mV
μA
ms
°C
UVLO
Soft-Start Current
Soft-Start Period
Thermal Shutdown
I
t
= 0V
--
--
SS
SS
SS
C
= 0.1μF
--
13.5
150
--
SS
T
--
--
SD
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in natural convection at TA = 25°C on a high effective thermal conductivity four-layer test board of
JEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of the
package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
5
Preliminary
RT7257E
Typical Operating Characteristics
Efficiency vs. Load Current
Reference Voltage vs. Input Voltage
100
0.820
0.815
0.810
0.805
0.800
0.795
0.790
0.785
0.780
90
80
VIN = 4.5V
V
V
IN = 12V
IN = 17V
70
60
50
40
30
20
10
0
VOUT = 3.3V
10
VIN = 4.5V to 17V, VOUT = 3.3V, IOUT = 1A
0.01
0.1
1
4.5
7
9.5
12
14.5
17
Load Current (A)
Input Voltage (V)
Reference Voltage vs. Temperature
Output Voltage vs. Load Current
0.820
0.815
0.810
0.805
0.800
0.795
0.790
0.785
0.780
3.380
3.354
3.328
3.302
3.276
3.250
VIN = 4.5V
VIN = 12V
VIN = 17V
VOUT = 3.3V
2.5 3
VIN = 12V, VOUT = 3.3V, IOUT = 1A
-50
-25
0
25
50
75
100
125
0
0.5
1
1.5
2
Temperature (°C)
Load Current (A)
Switching Frequency vs. Input Voltage
Switching Frequency vs. Temperature
380
370
360
350
340
330
320
310
300
370
360
350
340
330
320
310
300
VOUT = 3.3V, IOUT = 0.3A
VIN = 12V, VOUT = 3.3V, IOUT = 0.5A
25 50 75 100 125
4.5
7
9.5
12
14.5
17
-50
-25
0
Input Voltage (V)
Temperature (°C)
6
Preliminary
RT7257E
Current Limit vs. Temperature
Load Transient Response
8
7
6
5
4
3
2
VOUT
(100mV/Div)
IOUT
(2A/Div)
VIN = 12V, VOUT = 3.3V
50 75 100 125
VIN = 12V, VOUT = 3.3V, IOUT = 0.2A to 3A
Time (250μs/Div)
-50
-25
0
25
Temperature (°C)
Load Transient Response
Switching
VOUT
(10mV/Div)
VOUT
(100mV/Div)
VSW
(10V/Div)
IOUT
(2V/Div)
IL
(2A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 1.5A to 3A
VIN = 12V, VOUT = 3.3V, IOUT = 3A
Time (250μs/Div)
Time (1μs/Div)
Power On from VIN
Power Off from VIN
VIN
VIN
(5V/Div)
(5V/Div)
VOUT
VOUT
(2V/Div)
(2V/Div)
IL
IL
(2A/Div)
(2A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 3A
Time (5ms/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 3A
Time (5ms/Div)
7
Preliminary
RT7257E
Power Off from EN
Power On from EN
VEN
VEN
(5V/Div)
(5V/Div)
VOUT
VOUT
(2V/Div)
(2V/Div)
IL
IL
(2A/Div)
(2A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 2A
Time (5ms/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 2A
Time (5ms/Div)
8
Preliminary
RT7257E
Application Information
The RT7257E is a synchronous high voltage buck converter
that can support the input voltage range from 4.5V to 17V
and the output current can be up to 3A.
Soft-Start
The RT7257E contains an external soft-start clamp that
gradually raises the output voltage. The soft-start timing
can be programmed by the external capacitor between
SS pin andGND. The chip provides a 6μAcharge current
for the external capacitor. If 0.1μF capacitor is used to
set the soft-start, it's period will be 13.5ms (typ.).
Output Voltage Setting
The resistive divider allows the FB pin to sense the output
voltage as shown in Figure 1.
V
OUT
Chip Enable Operation
The EN pin is the chip enable input. Pulling the EN pin
low (<0.4V) will shutdown the device. During shutdown
mode, the RT7257E quiescent current drops to lower than
3μA. Driving the EN pin high (>2V, < 17V) will turn on the
device again. For external timing control (e.g.RC), the EN
pin can also be externally pulled high by adding a REN*
resistor and CEN* capacitor from the VIN pin (see Figure
5).
R1
FB
RT7257E
GND
R2
Figure 1. Output Voltage Setting
The output voltage is set by an external resistive voltage
divider according to the following equation :
An external MOSFET can be added to implement digital
control on the EN pin when no system voltage above 2V
is available, as shown in Figure 3. In this case, a 100kΩ
pull-up resistor, REN, is connected between VIN and the
EN pin. MOSFET Q1 will be under logic control to pull
down the EN pin.
R1
R2
⎛
⎝
⎞
⎟
⎠
VOUT = VFB 1+
⎜
Where VFB is the feedback reference voltage (0.8V typ.).
External Bootstrap Diode
1
2
VIN
BOOT
V
Connect a 100nF low ESR ceramic capacitor between
the BOOT pin and SW pin. This capacitor provides the
gate driver voltage for the high side MOSFET.
IN
C
BOOT
V
OUT
C
IN
RT7257E
R
EN
100k
L
3
SW
7
Chip Enable
EN
R1
C
OUT
Q1
It is recommended to add an external bootstrap diode
between an external 5V and BOOT pin for efficiency
improvement when input voltage is lower than 5.5V or duty
ratio is higher than 65% .The bootstrap diode can be a
low cost one such as IN4148 or BAT54. The external 5V
can be a 5V fixed input from system or a 5V output of the
RT7257E. Note that the external boot voltage must be
5
6
FB
8
SS
C
C
R2
C
SS
R
4,
C
COMP
9 (Exposed Pad)
GND
C
P
Figure 3. Enable Control Circuit for Logic Control with
Low Voltage
lower than 5.5V
To prevent enabling circuit when VIN is smaller than the
VOUT target value, a resistive voltage divider can be placed
between the input voltage and ground and connected to
the EN pin to adjust IC lockout threshold, as shown in
Figure 4. For example, if an 8V output voltage is regulated
from a 12V input voltage, the resistor REN2 can be selected
to set input lockout threshold larger than 8V.
5V
BOOT
100nF
RT7257E
SW
Figure 2. External Bootstrap Diode
9
Preliminary
RT7257E
Table 2. Suggested Inductors for Typical
Application Circuit
1
3
2
V
12V
IN
VIN
EN
BOOT
V
OUT
8V
C
IN
C
R
100k
RT7257E
10µF x 2
BOOT
L
EN1
Component
Supplier
Dimensions
(mm)
7
SW
Series
R1
R2
C
R
OUT
EN2
TDK
TDK
VLF10045
SLF12565
10 x 9.7 x 4.5
5
6
FB
8
SS
12.5 x 12.5 x 6.5
C
C
C
SS
R
C
4,
COMP
9 (Exposed Pad)
TAIYO
YUDEN
GND
C
P
NR8040
8 x 8 x 4
Figure 4. The Resistors can be Selected to Set IC
Lockout Threshold
CIN and COUT Selection
The input capacitance, CIN, is needed to filter the
trapezoidal current at the source of the high side MOSFET.
To prevent large ripple current, a low ESR input capacitor
sized for the maximum RMS current should be used. The
RMS current is given by :
Inductor Selection
The inductor value and operating frequency determine the
ripple current according to a specific input and output
voltage. The ripple current ΔIL increases with higher VIN
and decreases with higher inductance.
V
OUT
V
IN
I
= I
−1
RMS
OUT(MAX)
V
IN
V
OUT
V
f ×L
VOUT
V
IN
⎡
OUT ⎤ ⎡
× 1−
⎥ ⎢
⎤
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT / 2. This simple worst case condition is
commonly used for design because even significant
deviations do not offer much relief.
ΔIL =
⎢
⎣
⎥
⎦
⎦ ⎣
Having a lower ripple current reduces not only the ESR
losses in the output capacitors but also the output voltage
ripple. High frequency with small ripple current can achieve
the highest efficiency operation. However, it requires a
large inductor to achieve this goal.
Choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design.
For the ripple current selection, the value of ΔIL= 0.24(IMAX
)
For the input capacitor, two 10μF low ESR ceramic
capacitors are recommended. For the recommended
capacitor, please refer to Table 3 for more details.
will be a reasonable starting point. The largest ripple
current occurs at the highest VIN. To guarantee that the
ripple current stays below the specified maximum, the
inductor value should be chosen according to the following
equation :
The selection of COUT is determined by the required ESR
to minimize voltage ripple.
Moreover, the amount of bulk capacitance is also a key
for COUT selection to ensure that the control loop is stable.
Loop stability can be checked by viewing the load transient
response as described in a later section.
⎡
⎤ ⎡
⎤
V
f × ΔI
V
OUT
V
IN(MAX)
OUT
L =
× 1−
⎢
⎥ ⎢
⎥
L(MAX)
⎣
⎦ ⎣
⎦
The inductor's current rating (caused a 40°C temperature
rising from 25°C ambient) should be greater than the
maximum load current and its saturation current should
be greater than the short circuit peak current limit. Please
see Table 2 for the inductor selection reference.
The output ripple, ΔVOUT , is determined by :
1
⎡
⎤
ΔVOUT ≤ ΔIL ESR +
⎢
⎣
⎥
⎦
8fCOUT
10
Preliminary
RT7257E
EMI Consideration
The output ripple will be the highest at the maximum input
Since parasitic inductance and capacitance effects in PCB
circuitry would cause a spike voltage on SW pin when
high side MOSFET is turned-on/off, this spike voltage on
SW may impact on EMI performance in the system. In
order to enhance EMI performance, there are two methods
to suppress the spike voltage. One is to place an R-C
snubber between SW and GND and make them as close
as possible to the SW pin (see Figure 5). Another method
is adding a resistor in series with the bootstrap
capacitor, CBOOT. But this method will decrease the driving
capability to the high side MOSFET. It is strongly
recommended to reserve the R-C snubber during PCB
layout for EMI improvement. Moreover, reducing the SW
trace area and keeping the main power in a small loop will
be helpful on EMI performance. For detailed PCB layout
guide, please refer to the section of Layout Consideration.
voltage since ΔIL increases with input voltage. Multiple
capacitors placed in parallel may be needed to meet the
ESR and RMS current handling requirement. Higher values,
lower cost ceramic capacitors are now becoming available
in smaller case sizes. Their high ripple current, high voltage
rating and low ESR make them ideal for switching regulator
applications. However, care must be taken when these
capacitors are used at input and output. When a ceramic
capacitor is used at the input and the power is supplied
by a wall adapter through long wires, a load step at the
output can induce ringing at the input, VIN. At best, this
ringing can couple to the output and be mistaken as loop
instability. At worst, a sudden inrush of current through
the long wires can potentially cause a voltage spike at
VIN large enough to damage the part.
R
*
BOOT
1
3
2
7
V
IN
BOOT
RT7257E
VIN
EN
4.5V to 17V
C
IN
10µF x 2
C
BOOT
L
10µH
100nF
R
*
EN
V
OUT
SW
Chip Enable
3.3V/3A
R *
S
C
*
EN
R1
C
OUT
22µFx2
75k
C *
S
8
SS
5
6
FB
C
0.1µF
SS
4,
C
C
R
C
R2
4.7nF
9 (Exposed Pad)
12k
GND
24k
COMP
C
P
* : Optional
NC
Figure 5. Reference Circuit with Snubber and Enable Timing Control
Thermal Considerations
For recommended operating conditions specification of
RT7257E, the maximum junction temperature is 125°C.
The junction to ambient thermal resistance θJA is layout
dependent. For SOP-8 (Exposed Pad) package, the
thermal resistance θJA is 75°C/W on the standard JEDEC
51-7 four-layers thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by following
formula :
For continuous operation, do not exceed the maximum
operation junction temperature 125°C. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W
PD(MAX) = (TJ(MAX) − TA ) / θJA
(min.copper area PCB layout)
Where TJ(MAX) is the maximum operation junction
temperature , TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
PD(MAX) = (125°C − 25°C) / (49°C/W) = 2.04W
(70mm2copper area PCB layout)
11
Preliminary
RT7257E
The thermal resistance θJA of SOP-8 (Exposed Pad) is
determined by the package architecture design and the
PCB layout design. However, the package architecture
design had been designed. If possible, it's useful to
increase thermal performance by the PCB layout copper
design. The thermal resistance θJA can be decreased by
adding copper area under the exposed pad of SOP-8
(Exposed Pad) package.
(a) Copper Area = (2.3 x 2.3) mm2,θJA = 75°C/W
As shown in Figure 6, the amount of copper area to which
the SOP-8 (Exposed Pad) is mounted affects thermal
performance. When mounted to the standard
SOP-8 (Exposed Pad) pad (Figure 6.a), θJA is 75°C/W.
Adding copper area of pad under the SOP-8 (Exposed
Pad) (Figure 6.b) reduces the θJA to 64°C/W. Even further,
increasing the copper area of pad to 70mm2 (Figure 6.e)
reduces the θJA to 49°C/W.
(b) Copper Area = 10mm2,θJA = 64°C/W
The maximum power dissipation depends on operating
ambient temperature for fixed TJ(MAX) and thermal
resistance θJA. For RT7257E packages, the Figure 7 of
derating curves allows the designer to see the effect of
rising ambient temperature on the maximum power
dissipation allowed.
(c) Copper Area = 30mm2 , θJA = 54°C/W
(d) Copper Area = 50mm2 ,θJA = 51°C/W
(e) Copper Area = 70mm2 ,θJA = 49°C/W
2.2
Four-Layer PCB
2.0
1.8
Copper Area
70mm2
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
50mm2
30mm2
10mm2
Min.Layout
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 7.Derating Curves for RT7257E Package
Figure 6. Themal Resistance vs. CopperArea Layout
Design
12
Preliminary
RT7257E
Layout Consideration
` Connect feedback network behind the output capacitors.
Keep the loop area small. Place the feedback
components near the RT7257E.
Follow the PCB layout guidelines for optimal performance
of the RT7257E.
` Connect all analog grounds to a command node and
then connect the command node to the power ground
behind the output capacitors.
` Keep the traces of the main current paths as short and
wide as possible.
` Put the input capacitor as close as possible to the device
` An example of PCB layout guide is shown in Figure 8
pins (VINandGND).
for reference.
` SW node is with high frequency voltage swing and
should be kept at small area. Keep analog components
away from the SW node to prevent stray capacitive noise
pick-up.
SW
C
V
V
GND
GND
IN
IN
The feedback components
must be connected as close
to the device as possible.
R
BOOT
EN
C
SS
Input capacitor must
be placed as close
to the IC as possible.
C
IN
C
C
8
7
6
5
BOOT
VIN
SS
2
3
4
R
C
EN
C
P
L
GND
V
OUT
SW
COMP
FB
9
R1
C *
S
GND
R *
S
R2
V
OUT
C
OUT
GND
SW nods is with high frequency voltage swing and should
be kept at small area. Keep analog components away from
the SW node to prevent stray capacitive noise pick-up
Figure 8. PCB Layout Guide
Table 3. Suggested Capacitors for CIN and COUT
Location
CIN
Component Supplier
MURATA
TDK
Part No.
Capacitance (μF)
Case Size
1206
GRM31CR61E106K
C3225X5R1E106K
TMK316BJ106ML
GRM31CR60J476M
C3225X5R0J476M
GRM32ER71C226M
C3225X5R1C22M
10
10
10
47
47
22
22
CIN
1206
CIN
TAIYO YUDEN
MURATA
TDK
1206
COUT
COUT
COUT
COUT
1206
1210
MURATA
TDK
1210
1210
13
Preliminary
RT7257E
Outline Dimension
H
A
M
Y
EXPOSED THERMAL PAD
(Bottom of Package)
J
B
X
F
C
I
D
Dimensions In Millimeters Dimensions In Inches
Symbol
Min
Max
5.004
4.000
1.753
0.510
1.346
0.254
0.152
6.200
1.270
2.300
2.300
2.500
3.500
Min
Max
A
B
C
D
F
H
I
4.801
3.810
1.346
0.330
1.194
0.170
0.000
5.791
0.406
2.000
2.000
2.100
3.000
0.189
0.150
0.053
0.013
0.047
0.007
0.000
0.228
0.016
0.079
0.079
0.083
0.118
0.197
0.157
0.069
0.020
0.053
0.010
0.006
0.244
0.050
0.091
0.091
0.098
0.138
J
M
X
Y
X
Y
Option 1
Option 2
8-Lead SOP (Exposed Pad) Plastic Package
14
Preliminary
RT7257E
Datasheet Revision History
Version
P00
Data
Page No.
Item
Description
2011/10/19
First Edition
15
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