概述
规格参数
数据手册3PECLH-1.5 概述
ECL Logic 3-Bit Programmable Delay Modules ECL逻辑3位可编程延迟模块 延迟线
3PECLH-1.5 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Active |
| 零件包装代码： | DIP | 包装说明： | DIP, GWDIP16,.9 |
| 针数： | 16/9 | Reach Compliance Code： | unknown |
| HTS代码： | 8542.39.00.01 | 风险等级： | 5.79 |
| Is Samacsys： | N | 其他特性： | MAX RISE TIME CAPTURED |
| 系列： | 10K | JESD-30 代码： | R-XDIP-T9 |
| 逻辑集成电路类型： | ACTIVE DELAY LINE | 功能数量： | 1 |
| 抽头/阶步数： | 7 | 端子数量： | 9 |
| 最高工作温度： | 75 °C | 最低工作温度： | |
| 输出极性： | TRUE | 封装主体材料： | UNSPECIFIED |
| 封装代码： | DIP | 封装等效代码： | GWDIP16,.9 |
| 封装形状： | RECTANGULAR | 封装形式： | IN-LINE |
| 电源： | -5.2 V | 最大电源电流（ICC）： | 85 mA |
| 可编程延迟线： | YES | Prop。Delay @ Nom-Sup： | 10.5 ns |
| 认证状态： | Not Qualified | 座面最大高度： | 7.62 mm |
| 子类别： | Delay Lines | 表面贴装： | NO |
| 技术： | ECL | 温度等级： | COMMERCIAL EXTENDED |
| 端子形式： | THROUGH-HOLE | 端子节距： | 2.54 mm |
| 端子位置： | DUAL | 总延迟标称（td）： | 12 ns |
| 宽度： | 7.62 mm | Base Number Matches： | 1 |
3PECLH-1.5 数据手册
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PDF下载PECL3 Series
10K ECL Logic 3-Bit Programmable Delay Modules
Electrical Specifications at 25OC
Initial
Delay (ns)
Error ref.
to 000
(ns)
Referenced to "000" - Delay (ns) per Program Setting (P3*P2*P1)
3-Bit 10K ECL
Part Number
Delay per
Step (ns)
000
000
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
001
0.5
010
1.0
011
1.5
100
2.0
101
2.5
110
3.0
111
3.5
PECL3-0.5
PECL3-0.75
PECL3-1
0.5 ± .25
0.75 ± .3
1.0 ± .4
1.2 ± .4
1.25 ± .5
1.3 ± .5
1.5 ± .5
1.75 ± .6
2.0 ± .7
2.5 ± .7
3.0 ± .7
5.0 ± 1.0
10.0 ± 1.5
± .30
± .50
± .50
± .60
± .70
± .70
± .70
± .80
± .80
± .90
± 1.0
± 1.5
± 3.0
3 ± 0.5
3 ± 0.5
3 ± 0.5
3 ± 0.5
3 ± 0.5
3 ± 0.5
3 ± 0.5
3 ± 0.5
3 ± 0.5
3 ± 0.5
3 ± 0.5
3 ± 0.5
3 ± 0.5
0.75
1.0
1.50
2.0
2.25
3.0
3.00
4.0
3.75
5.0
4.50
6.0
5.25
7.0
PECL3-1.2
PECL3-1.25
PECL3-1.3
PECL3-1.5
PECL3-1.75
PECL3-2
1.2
2.4
3.6
4.8
6.0
7.2
8.4
1.25
1.3
2.50
2.6
3.75
3.9
5.00
5.2
6.25
6.5
7.50
7.8
8.75
9.1
1.5
3.0
4.5
6.0
7.5
9.0
10.5
12.25
14.0
17.5
21.0
35.0
70.0
1.75
2.0
3.50
4.0
5.25
6.0
7.00
8.0
8.75
10.0
12.5
15.0
25.0
50.0
10.50
12.0
15.0
18.0
30.0
60.0
PECL3-2.5
PECL3-3
2.5
5.0
7.5
10.0
12.0
20.0
40.0
3.0
6.0
9.0
PECL3-5
PECL3-10
5.0
10.0
20.0
15.0
30.0
10.0
3PECLH Series
10KH ECL Logic 3-Bit Programmable Delay Modules
Electrical Specifications at 25OC
Initial
Delay (ns)
Error ref.
to 000
(ns)
Referenced to "000" - Delay (ns) per Program Setting (P3*P2*P1)
3-Bit 10KH ECL
Part Number
Delay per
Step (ns)
000
000
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
001
0.5
010
1.0
011
1.5
100
2.0
101
2.5
110
3.0
111
3.5
3PECLH-0.5
3PECLH0.75
3PECLH-1
0.5 ± .25
0.75 ± .3
1.0 ± .4
1.2 ± .4
1.25 ± .5
1.3 ± .5
1.5 ± .5
1.75 ± .6
2.0 ± .7
2.5 ± .7
3.0 ± .7
5.0 ± 1.0
10.0 ± 1.5
± .30
± .50
± .50
± .60
± .70
± .70
± .70
± .80
± .80
± .90
± 1.0
± 1.5
± 3.0
1.5 ± 0.5
1.5 ± 0.5
1.5 ± 0.5
1.5 ± 0.5
1.5 ± 0.5
1.5 ± 0.5
1.5 ± 0.5
1.5 ± 0.5
1.5 ± 0.5
1.5 ± 0.5
1.5 ± 0.5
1.5 ± 0.5
1.5 ± 0.5
0.75
1.0
1.50
2.0
2.25
3.0
3.00
4.0
3.75
5.0
4.50
6.0
5.25
7.0
3PECLH-1.2
3PECLH1.25
3PECLH-1.3
3PECLH-1.5
3PECLH1.75
3PECLH-2
1.2
2.4
3.6
4.8
6.0
7.2
8.4
1.25
1.3
2.50
2.6
3.75
3.9
5.00
5.2
6.25
6.5
7.50
7.8
8.75
9.1
1.5
3.0
4.5
6.0
7.5
9.0
10.5
12.25
14.0
17.5
21.0
35.0
70.0
1.75
2.0
3.50
4.0
5.25
6.0
7.00
8.0
8.75
10.0
12.5
15.0
25.0
50.0
10.50
12.0
15.0
18.0
30.0
60.0
3PECLH-2.5
3PECLH-3
3PECLH-5
2.5
5.0
7.5
10.0
12.0
20.0
40.0
3.0
6.0
9.0
5.0
10.0
20.0
15.0
30.0
3PECLH-10
10.0
CUMULATIVE TOLERANCES: "Error" Tolerance is for Programmed Delays
Referenced to Initial Delay, Setting "000." For example the setting "111" delay of
PECL3-2 is 14.0 ± 0.8 ns ref. to "000," and 17.0 ± 1.3 ns referenced to the input.
ECL 3-Bit 16-Pin Schematic
Vcc
16
P2
OUT
P3
9
15
10
ENABLE input, Pin 2, is active low. Output will be disabled ( low) when " E " is high.
Output
Buffer
3-Bit Programmable
Delay Line
INPUT LOADING: Input, Pin 6, internally connected to eight ECL gate inputs
terminated by Thevenin equivalent of 100 Ohms to -2V.
1
2
6
7
8
Vcc
E
Vee
IN
P1
Dimensions in Inches (mm)
.810
(20.57)
MAX.
.400
(10.16)
MAX.
GENERAL: For Operating Specifications and Test Conditions, see
Tables IV, V andVII on page 5 of this catalog. Delays specified for the
Leading Edge.
.260
(6.60)
TYP.
.300
(7.62)
MAX.
Operating Temp. Range ....................................... -30OC to +85OC
Temperature Coefficient ............................... < 300ppm/OC typical
Minimum Input Pulse Width ............................ 35% of max. Delay
Supply Current, IEE ................................. 75 mA typ., 85 mA max.
.120
(3.05)
MIN.
.010
(0.25)
TYP.
.300
(7.62)
.020
(0.51)
TYP.
.050 .100
(1.27) (2.54)
TYP.
TYP.
For other values & Custom Designs, contact factory.
Specifications subject to change without notice.
PECL3 4/98
15801 Chemical Lane, Huntington Beach, CA 92649-1595
Rhombus
Industries Inc.
Tel: (714) 898-0960 • Fax: (714) 896-0971
27
3PECLH-1.5 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| 3PECLH-10 | RHOMBUS-IND | ECL Logic 3-Bit Programmable Delay Modules | 获取价格 |
|
| 3PECLH-2 | RHOMBUS-IND | ECL Logic 3-Bit Programmable Delay Modules | 获取价格 |
|
| 3PECLH-2.5 | RHOMBUS-IND | ECL Logic 3-Bit Programmable Delay Modules | 获取价格 |
|
| 3PECLH-3 | RHOMBUS-IND | ECL Logic 3-Bit Programmable Delay Modules | 获取价格 |
|
| 3PECLH-5 | RHOMBUS-IND | ECL Logic 3-Bit Programmable Delay Modules | 获取价格 |
|
| 3PECLH0.5 | ETC | Logic IC | 获取价格 |
|
| 3PECLH0.75 | RHOMBUS-IND | ECL Logic 3-Bit Programmable Delay Modules | 获取价格 |
|
| 3PECLH1 | ETC | Logic IC | 获取价格 |
|
| 3PECLH1.25 | RHOMBUS-IND | ECL Logic 3-Bit Programmable Delay Modules | 获取价格 |
|
| 3PECLH1.5 | ETC | Logic IC | 获取价格 |
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