X9410WS24-2.7T1 [RENESAS]
DUAL 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24, PLASTIC, SOIC-24;型号: | X9410WS24-2.7T1 |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | DUAL 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24, PLASTIC, SOIC-24 光电二极管 转换器 电阻器 |
文件: | 总21页 (文件大小:388K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
X9410
Low Noise/Low Power/SPI Bus
®
Data Sheet
October 12, 2006
FN8193.2
DESCRIPTION
Dual Digitally Controlled Potentiometer
(XDCP™)
The X9410 integrates two digitally controlled
potentiometers (XDCPs) on a monolithic CMOS
integrated circuit.
FEATURES
• Two potentiometers per package
• SPI serial interface
• Register oriented format
- Direct read/write/transfer wiper positions
- Store as many as four positions per
potentiometer
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI
serial bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and four nonvolatile Data Registers (DR0:DR3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array through the switches.
Power-up recalls the contents of DR0 to the WCR.
• Power supplies
- V = 2.7V to 5.5V
CC
- V+ = 2.7V to 5.5V
- V- = -2.7V to -5.5V
• Low power CMOS
- Standby current < 1µA
- High reliability
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
- Endurance - 100,000 data changes per bit per
register
- Register data retention - 100 years
• 8-bytes of nonvolatile EEPROM memory
• 10kΩ resistor arrays
• Resolution: 64 taps each pot
• 24 Ld SOIC, 24 Ld TSSOP, and 24 Ld plastic DIP
packages
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
VCC
VSS
Pot 0
R0 R1
VH0/RH0
Wiper
Counter
Register
(WCR)
V+
V-
VL0/RL0
R2 R3
HOLD
CS
VW0/RW0
SCK
SO
SI
Interface
and
Control
8
Circuitry
A0
A1
VW1/RW1
Pot 1
Data
WP
R0 R1
R2 R3
V
H1/RH1
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot1
VL1/RL1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9410
Ordering Information
POTENTIOMETER
VCC LIMITS ORGANIZATION TEMP RANGE
PART NUMBER
X9410YS24I
PART MARKING
(V)
(kΩ)
(°C)
PACKAGE
PKG. DWG. #
X9410YS I
X9410YS ZI
X9410WP I
X9410WS I
X9410WS ZI
X9410WV I
X9410WV ZI
X9410YS G
5 ±10%
2.5
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
24 Ld SOIC (300 mil)
M24.3
X9410YS24IZ (Note)
X9410WP24I
24 Ld SOIC (300 mil) (Pb-free) MDP0027
10
24 Ld PDIP
E24.6
M24.3
X9410WS24I*
24 Ld SOIC (300 mil)
X9410WS24IZ* (Note)
X9410WV24I*
24 Ld SOIC (300 mil) (Pb-free) MDP0027
24 Ld TSSOP (4.4mm) MDP0044
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
24 Ld SOIC (300 mil) M24.3
24 Ld SOIC (300 mil) (Pb-free) MDP0027
X9410WV24IZ* (Note)
X9410YS24I-2.7
2.7 to 5.5
2.5
10
X9410YS24IZ-2.7 (Note) X9410YS ZG
X9410WP24I-2.7
X9410WS24I-2.7*
X9410WP G
X9410WS G
24 Ld PDIP
E24.6
M24.3
24 Ld SOIC (300 mil)
X9410WS24IZ-2.7* (Note) X9410WS ZG
X9410WV24-2.7* X9410WV F
X9410WV24Z-2.7* (Note) X9410WV ZF
X9410WV24I-2.7* X9410WV G
24 Ld SOIC (300 mil) (Pb-free) MDP0027
24 Ld TSSOP (4.4mm) MDP0044
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
24 Ld TSSOP (4.4mm) MDP0044
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
0 to 70
-40 to 85
-40 to 85
X9410WV24IZ-2.7* (Note) X9410WV ZG
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PIN DESCRIPTIONS
Host Interface Pins
Serial Output (SO)
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Hold (HOLD)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Serial Clock (SCK)
Device Address (A - A )
0
1
The SCK input is used to clock data into and out of the
X9410.
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9410. A maximum of 4 devices may occupy the
SPI serial bus.
Chip Select (CS)
When CS is HIGH, the X9410 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9410, placing it
FN8193.2
October 12, 2006
2
X9410
Potentiometer Pins
PIN NAMES
Symbol
V /R (V /R - V /R ), V /R (V /R - V /R )
Description
Serial Clock
H
H
H0 H0
H1 H1
L
L
L0 L0
L1 L1
The V /R and V /R inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
H
H
L
L
SCK
SI, SO
A0 - A1
Serial Data
Device Address
V /R (V /R - V /R
)
W1 W1
W
W
W0 W0
V
H0/RH0 - VH1/RH1
,
Potentiometer Pins
(terminal equivalent)
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
VL0/RL0 - VL1/RL1
VW0/RW0 - VW1/RW1
Potentiometer Pin
(wiper equivalent)
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
WP
Hardware Write Protection
Analog Supplies
V+,V-
VCC
VSS
NC
System Supply Voltage
System Ground
Analog Supplies (V+, V-)
The analog supplies V+, V- are the supply voltages for
the XDCP analog section.
No Connection
PIN CONFIGURATION
DEVICE DESCRIPTION
The X9410 is
a
highly integrated microcircuit
DIP/SOIC
incorporating two resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
VCC
VL0/RL0
1
2
24
23
22
21
20
19
18
17
16
15
V+
NC
VH0/RH0
VW0/RW0
3
NC
NC
4
Serial Interface
A0
5
CS
WP
SI
The X9410 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
SO
6
X9410
7
HOLD
SCK
A1
8
VL1/RL1
VH1/RH1
VW1/RW1
9
NC
NC
10
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
11
12
14
13
NC
V-
VSS
Array Description
The X9410 is comprised of two resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
TSSOP
SI
A1
1
2
24
23
22
21
20
19
18
17
16
15
WP
CS
potentiometer (V /R and V /R inputs).
H
H
L
L
VL1/RL1
VH1/RH1
3
VW0/RW0
VH0/RH0
VL0/RL0
4
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V /R ) output. Within each individual array only one
5
V
W1/RW1
VSS
VCC
NC
NC
NC
6
W
W
X9410
switch may be turned on at a time.
NC
NC
NC
7
8
These switches are controlled by a Wiper Counter
Register (WCR). The six bits of the WCR are decoded
to select, and enable, one of sixty-four switches.
9
10
V-
V+
A0
SCK
11
12
14
13
HOLD
SO
FN8193.2
October 12, 2006
3
X9410
Wiper Counter Register (WCR)
Data Registers
The X9410 contains two Wiper Counter Registers, one
for each XDCP potentiometer. The WCR is equivalent
to a serial-in, parallel-out register/counter with its
outputs decoded to select one of sixty-four switches
along its resistor array. The contents of the WCR can
be altered in four ways: it may be written directly by the
host via the Write Wiper Counter Register instruction
(serial load); it may be written indirectly by transferring
the contents of one of four associated Data Registers
via the XFR Data Register or Global XFR Data Register
instructions (parallel load); it can be modified one step
at a time by the Increment/ Decrement instruction.
Finally, it is loaded with the contents of its Data Register
zero (DR0) upon power-up.
Each potentiometer has four 6-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take
a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Data Register Detail
(MSB)
D5
(LSB)
D0
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9410 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
D4
NV
D3
NV
D2
NV
D1
NV
NV
NV
Figure 1. Detailed Potentiometer Block Diagram
(One of Two Arrays)
Serial Data Path
Serial
VH/RH
Bus
Input
From Interface
Circuitry
C
Register 0
Register 2
Register 1
o
u
n
t
e
r
8
6
Parallel
Bus
Input
Wiper
D
e
c
o
d
e
Register 3
Counter
Register
(WCR)
INC/DEC
Logic
If WCR = 00[H] then VW/RW = VL/RL
UP/DN
UP/DN
If WCR = 3F[H] then VW/RW = VH/RH
VL/RL
Modified SCL
CLK
VW/RW
FN8193.2
October 12, 2006
4
X9410
Write in Process
Figure 3. Instruction Byte Format
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a Write In Process bit
(WIP). The WIP bit is read with a Read Status
command.
Register
Select
I3
I2
I1
I0
R1 R0
0
P0
Pot Select
Instructions
INSTRUCTIONS
The four high order bits of the instruction byte specify
the operation. The next two bits (R and R ) select one
of the four registers that is to be acted upon when a
1
0
Identification (ID) Byte
The first byte sent to the X9410 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9410 this is fixed as 0101[B] (refer to Figure 2).
register oriented instruction is issued. The last bit (P )
selects which one of the two potentiometers is to be
affected by the instruction.
0
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte.
These instructions are:
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
– XFR Data Register to Wiper Counter Register—This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
address is defined by the state of the A - A input
0
1
pins. The X9410 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9410 to successfully
continue the command sequence. The A - A inputs
– XFR Wiper Counter Register to Data Register—This
transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
0
1
can be actively driven by CMOS input signals or tied to
or V
V
.
SS
CC
– Global XFR Data Register to Counter Register—This
transfers the contents of both specified Data Registers
to the associated Wiper Counter Registers.
The remaining two bits in the ID byte must be set to 0.
Figure 2. Identification Byte Format
– Global XFR Wiper Counter Register to Data
Register—This transfers the contents of both Wiper
Counter Registers to the specified associated Data
Registers.
Device Type
Identifier
0
1
0
1
0
0
A1
A0
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
Device Address
Instruction Byte
The next byte sent to the X9410 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the two pots and when applicable
they point to one of four associated registers. The
format is shown below in Figure 3.
wiper to this action will be delayed by t
. A transfer
WRL
from the WCR (current wiper position), to a data
register is a write to nonvolatile memory and takes a
minimum of t
to complete. The transfer can occur
WR
between one of the two potentiometers and one of its
associated registers; or it may occur globally, where
the transfer occurs between both potentiometers and
one associated register.
FN8193.2
October 12, 2006
5
X9410
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9410; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register. These instructions are:
The sequence of these operations is shown in Figure 5
and Figure 6.
The final command is Increment/Decrement. It is
different from the other commands because it’s length
is indeterminate. Once the command is issued, the
master can clock the selected wiper up and/or down in
one resistor segment steps, thereby providing a fine
tuning capability to the host. For each SCK clock pulse
– Read Wiper Counter Register—read the current
wiper position of the selected pot,
– Write Wiper Counter Register—change current
wiper position of the selected pot,
– Read Data Register—read the contents of the
selected data register;
– Write Data Register—write a new value to the
selected data register.
(t
) while SI is HIGH, the selected wiper will move
HIGH
one resistor segment towards the V /R terminal.
H
H
Similarly, for each SCK clock pulse while SI is LOW,
the selected wiper will move one resistor segment
towards the V /R terminal. A detailed illustration of the
L
L
– Read Status—This command returns the contents
of the WIP bit which indicates if the internal write
cycle is in progress.
sequence and timing for this operation are shown in
Figure 7 and Figure 8.
Figure 4. Two-Byte Instruction Sequence
CS
SCK
SI
0
1
0
1
0
0
A1 A0 I3 I2
I1 I0 R1 R0
0
P0
Figure 5. Three-Byte Instruction Sequence (Write)
CS
SCL
SI
0
0
0
1
0
1
A1 A0
I3 I2
I1 I0 R1 R0
0
P0
0
0
D5 D4 D3 D2 D1 D0
Figure 6. Three-Byte Instruction Sequence (Read)
CS
SCL
SI
Don’t Care
0
0
0
1
0
1
A1 A0
I3 I2
I1 I0 R1 R0
0
P0
S0
0
0
D5 D4 D3 D2 D1 D0
FN8193.2
October 12, 2006
6
X9410
Figure 7. Increment/Decrement Instruction Sequence
CS
SCK
SI
0
1
0
1
0
0
A1 A0
I3 I2
I1 I0
0
0
0
P0
I
I
D
E
C
1
I
D
E
C
n
N
C
1
N
C
2
N
C
n
Figure 8. Increment/Decrement Timing Limits
tWRID
SCK
SI
Voltage Out
VW/RW
INC/DEC CMD Issued
Table 1. Instruction Set
Instruction Set
Instruction
I
I
I
I
R
R
P
P
Operation
3
2
1
0
1
0
1
0
Read Wiper Counter Register
1
1
1
1
1
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
P0 Read the contents of the Wiper Counter
Register pointed to by P0
P0 Write new value to the Wiper Counter Register
pointed to by P0
P0 Read the contents of the Data Register pointed
to by P0 and R1 - R0
P0 Write new value to the Data Register pointed to
by P0 and R1 - R0
Write Wiper Counter Register
Read Data Register
0
0
0
0
0
0
R1 R0
R1 R0
R1 R0
Write Data Register
XFR Data Register to Wiper
Counter Register
P0 Transfer the contents of the Data Register
pointed to by R1 - R0 to the Wiper Counter
Register pointed to by P0
XFR Wiper Counter Register
to Data Register
1
0
1
1
0
0
1
0
0
0
1
0
R1 R0
R1 R0
R1 R0
0
0
0
P0 Transfer the contents of the Wiper Counter
Register pointed to by P0 to the Register
pointed to by R1 - R0
Global XFR Data Register to
Wiper Counter Register
0
Transfer the contents of the Data Registers
pointed to by R1 - R0 of both pots to their
respective Wiper Counter Register
Global XFR Wiper Counter
Register to Data Register
0
Transfer the contents of all Wiper Counter
Registers to their respective data Registers
pointed to by R1 - R0 of both pots
Increment/Decrement Wiper
Counter Register
0
0
0
1
1
0
0
1
0
0
0
0
0
0
P0 Enable Increment/decrement of the Wiper
Counter Register pointed to by P0
Read Status (WIP bit)
1
Read the status of the internal write cycle, by
checking the WIP bit.
FN8193.2
October 12, 2006
7
X9410
Instruction Format
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Counter Register
(2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
wiper position
(sent by X9410 on SO)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W
0 0 P P P P P P
A A
P
0
0
1
0
1
0
0
1
0
0
1
0
0
0
1
0
5
4 3 2 1 0
Write Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
Data Byte
(sent by Host on SI)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W
0 0 P P P P P P
A A
P
0
0
1
0
1
0
0
1
0
1
0
0
0
0
1
0
5
4 3 2 1 0
Read Data Register (DR)
device type
identifier
device
addresses
instruction DR and WCR
opcode addresses
Data Byte
(sent by X9410 on SO)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W
0 0 P P P P P P
A A
R
1
R
0
P
0
0
1
0
1
0
0
1
0
1
1
0
1
0
5
4 3 2 1 0
Write Data Register(DR)
device type
identifier
device
addresses
instruction DR and WCR
Data Byte
(sent by host on SI)
opcode
addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
W W W W W W
0 P P P P P P
A A
1
R
1
R
0
0
P
0
0
1
0
1
0
0
1
1
0
0
0
0
5
4 3 2 1 0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction DR and WCR
CS
Falling
Edge
CS
Rising
Edge
opcode
addresses
A A
1
R
1
R
0
0
P
0
0
1
0
1
0
0
1 1 0 1
0
Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
identifier
device
addresses
instruction DR and WCR
opcode addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
D D
0 A A 1
R
R
0
P
0
0
1
0
1
0
1
1
0
0
1
1
0
FN8193.2
October 12, 2006
8
X9410
Increment/Decrement Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
increment/decrement
CS
Falling
Edge
CS
Rising
Edge
addresses (sent by master on SDA)
A A
1
P
0
I/ I/
D D
I/ I/
D D
0
1
0
1
0
0
0
0
1
0
X X
0
.
.
.
.
0
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
DR
addresses
CS
Falling
Edge
CS
Rising
Edge
A
1
A
0
R R
1 0
0
1
0
1
0
0
0
0
0
1
0 0
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
identifier
device
addresses
instruction
opcode
DR
addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
A A
1
R R
1 0
0
1
0
1
0
0
1
0
0
0
0 0
0
Read Status
device type
identifier
device
addresses
instruction
opcode
wiper
addresses
Data Byte
(sent by X9410 on SO)
CS
CS
Falling
Edge
Rising
Edge
W
I
P
A A
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
FN8193.2
October 12, 2006
9
X9410
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias.................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SCK, SCL or any address
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
input with respect to V ......................... -1V to +7V
SS
Voltage on V+ (referenced to V ) ........................10V
SS
Voltage on V- (referenced to V ) ........................-10V
SS
(V+) - (V-) ..............................................................12V
Any V .....................................................................V+
H
Any V ......................................................................V-
L
Lead temperature (soldering, 10s) .................. +300°C
I
(10s) ............................................................±12mA
W
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
-40°C
Max.
+70°C
+85°C
Device
X9410
Supply Voltage (V ) Limits
CC
5V ± 10%
2.7V to 5.5V
X9410-2.7
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
End to end resistance
Power rating
Min.
Typ.
Max.
±20
50
Unit
%
Test Conditions
+25°C, each pot
RTOTAL
mW
mA
Ω
IW
Wiper current
±6
RW
Wiper resistance
150
40
250
Wiper Current = ± 1mA,
VCC = 3V
100
Ω
Wiper Current = ± 1mA,
V
CC = 5V
Vv+
Vv-
Voltage on V+ Pin
Voltage on V- Pin
X9410
+4.5
+2.7
-5.5
-5.5
V-
+5.5
+5.5
-4.5
-2.7
V+
V
X9410-2.7
X9410
V
X9410-2.7
VTERM
Voltage on any VH/RH or VL/RL Pin
Noise
Resolution (4)
V
dBV
-120
1.6
Ref: 1kHz
%
Absolute linearity (1)
Relative linearity (2)
±1
MI(3)
MI(3)
ppm/°C
ppm/°C
pF
Rw(n)(actual) - Rw(n)(expected)
±0.2
Rw(n + 1) - [Rw(n) + MI]
Temperature coefficient of RTOTAL
Ratiometric temp. coefficient
±300
±20
CH/CL/CW Potentiometer capacitances
10/10/25
See Circuit #3
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when
used as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (RH - RL)/63, single pot
(4) Individual array resolution
FN8193.2
October 12, 2006
10
X9410
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
ICC1
VCC supply current (Active)
400
µA
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ICC2
VCC supply current (Nonvolatile
Write)
1
mA
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ISB
ILI
VCC current (standby)
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
1
10
µA
µA
µA
V
SCK = SI = VSS, Addr. = VSS
VIN = VSS to VCC
ILO
VIH
VIL
VOL
10
VOUT = VSS to VCC
VCC x 0.7
-0.5
VCC + 0.5
VCC x 0.1
0.4
V
Output LOW voltage
V
IOL = 3mA
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit per register
years
CAPACITANCE
Symbol
Test
Max.
Unit
pF
Test Conditions
(5)
COUT
Output capacitance (SO)
8
6
VOUT = 0V
VIN = 0V
(5)
CIN
Input capacitance (A0, A1, SI, and SCK)
pF
POWER-UP TIMING
Symbol
Parameter
Min.
Max.
Unit
ms
(6)
tPUR
Power-up to initiation of read operation
Power-up to initiation of write operation
VCC Power-up ramp
1
5
1
5
(6)
tPUW
tR VCC
ms
0.2
50
V/msec
POWER-UP AND POWER-DOWN
EQUIVALENT A.C. LOAD CIRCUIT
There are no restrictions on the power-up or power-
5V
2.7V
down sequencing of the bias supplies V , V+, and V-
CC
provided that all three supplies reach their final values
within 1msec of each other. However, at all times, the
voltages on the potentiometer pins must be less than
V+ and more than V-. The recall of the wiper position
from nonvolatile memory is not in effect until all
supplies reach their final value.
1533Ω
SDA Output
100pF
100pF
FN8193.2
October 12, 2006
11
X9410
A.C. TEST CONDITIONS
Test Circuit #3 SPICE Macro Model
Input pulse levels
VCC x 0.1 to VCC x 0.9
10ns
RTOTAL
Input rise and fall times
Input and output timing level
RH
RL
CL
V
CC x 0.5
CH
CW
10pF
Notes: (5) This parameter is periodically sampled and not 100% tested
(6) tPUR and tPUW are the delays required from the time the
third (last) power supply (VCC, V+ or V-) is stable until
the specific instruction can be issued. These parameters
are periodically sampled and not 100% tested.
10pF
25pF
RW
AC TIMING
Symbol
Parameter
Min.
Max.
Unit
fSCK
tCYC
tWH
tWL
SSI/SPI clock frequency
SSI/SPI clock cycle time
SSI/SPI clock high time
SSI/SPI clock low time
Lead time
2.0
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
500
200
200
250
250
50
tLEAD
tLAG
tSU
Lag time
SI, SCK, HOLD and CS input setup time
SI, SCK, HOLD and CS input hold time
SI, SCK, HOLD and CS input rise time
SI, SCK, HOLD and CS input fall time
SO output disable time
tH
50
tRI
2
tFI
2
tDIS
tV
0
0
500
100
SO output valid time
tHO
SO output hold time
tRO
SO output rise time
50
50
tFO
SO output fall time
tHOLD
tHSU
tHH
HOLD time
400
100
100
HOLD setup time
HOLD hold time
tHZ
HOLD low to output in High Z
HOLD high to output in Low Z
100
100
20
tLZ
TI
Noise suppression time constant at SI, SCK, HOLD and CS inputs
CS deselect time
tCS
2
0
0
tWPASU
tWPAH
WP, A0 and A1 setup time
WP, A0 and A1 hold time
FN8193.2
October 12, 2006
12
X9410
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Unit
tWR
High-voltage write cycle time (store instructions)
5
10
ms
XDCP TIMING
Symbol
Parameter
Min. Max. Unit
tWRPO
tWRL
Wiper response time after the third (last) power supply is stable
Wiper response time after instruction issued (all load instructions)
10
10
µs
µs
ns
tWRID
Wiper response time from an active SCL/SCK edge (increment/decrement instruction)
450
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
TIMING DIAGRAMS
Input Timing
tCS
CS
tLEAD
tCYC
tLAG
SCK
...
tWH
tRI
tFI
tWL
tSU
tH
...
MSB
LSB
SI
High Impedance
SO
FN8193.2
October 12, 2006
13
X9410
Output Timing
CS
SCK
SO
...
...
tV
tHO
tDIS
MSB
LSB
ADDR
SI
Hold Timing
CS
tHSU
tHH
SCK
SO
...
tRO
tFO
tHZ
tLZ
SI
tHOLD
HOLD
XDCP Timing (for All Load Instructions)
CS
SCK
...
...
tWRL
MSB
LSB
SI
VW/RW
High Impedance
SO
FN8193.2
October 12, 2006
14
X9410
XDCP Timing (for Increment/Decrement Instruction)
CS
SCK
VW/RW
SI
...
tWRID
...
...
ADDR
Inc/Dec
Inc/Dec
High Impedance
SO
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
tWPAH
tWPASU
WP
A0
A1
FN8193.2
October 12, 2006
15
X9410
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
VR
VR
VW/RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
NONINVERTING AMPLIFIER
VOLTAGE REGULATOR
VS
+
–
VO
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
OFFSET VOLTAGE ADJUSTMENT
COMPARATOR WITH HYSTERESIS
R1
R2
VS
–
+
VS
VO
100kΩ
–
+
VO
TL072
R1
R2
10kΩ
10kΩ
+12V
VUL = {R1/(R1+R2)} VO(max)
LL = {R1/(R1+R2)} VO(min)
10kΩ
-12V
V
FN8193.2
October 12, 2006
16
X9410
Application Circuits (continued)
ATTENUATOR
FILTER
C
VS
+
–
R2
R1
–
R
VO
VS
+
R3
R2
R4
All RS = 10kΩ
R1
G
O = 1 + R2/R1
VO = G VS
-1/2 ≤ G ≤ +1/2
fc = 1/(2πRC)
INVERTING AMPLIFIER
EQUIVALENT L-R CIRCUIT
R1
R2
VS
R2
C1
–
+
VS
+
–
VO
R1
ZIN
VO = G VS
G = -R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
FUNCTION GENERATOR
C
R2
R1
–
+
–
+
R
R
}
}
A
B
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
FN8193.2
October 12, 2006
17
X9410
Dual-In-Line Plastic Packages (PDIP)
E24.6 (JEDEC MS-011-AA ISSUE B)
N
24 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
INCHES
MILLIMETERS
1 2
3
N/2
SYMBOL
MIN
MAX
0.250
-
MIN
-
MAX
6.35
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
D
E
0.015
0.125
0.014
0.030
0.008
1.150
0.005
0.600
0.485
0.39
3.18
0.356
0.77
0.204
4
BASE
PLANE
0.195
0.022
0.070
0.015
1.290
-
4.95
0.558
1.77
0.381
-
A2
A
-
SEATING
PLANE
L
C
L
B1
C
8
D1
B1
eA
A1
A
-
D1
e
eC
C
D
29.3
32.7
5
B
eB
D1
E
0.13
15.24
12.32
-
5
0.010 (0.25) M
C
B S
0.625
0.580
15.87
14.73
6
E1
e
5
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.600 BSC
2.54 BSC
15.24 BSC
-
eA
eB
L
6
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.700
0.200
-
17.78
5.08
7
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
N
24
24
JEDEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
eA
6. E and
ular to datum
7. eB and eC are measured at the lead tips with the leads unconstrained.
C must be zero or greater.
are measured with the leads constrained to be perpendic-
-C-
.
e
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
FN8193.2
October 12, 2006
18
X9410
Small Outline Plastic Packages (SOIC)
M24.3 (JEDEC MS-013-AD ISSUE C)
N
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.020
-
0.30
-
1
2
3
L
0.51
9
SEATING PLANE
A
0.0091
0.5985
0.2914
0.0125
0.32
-
-A-
0.6141 15.20
15.60
7.60
3
h x 45°
D
0.2992
7.40
4
-C-
0.05 BSC
1.27 BSC
-
α
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
24
24
7
0°
8°
0°
8°
-
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
FN8193.2
October 12, 2006
19
X9410
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
±0.003
±0.002
±0.003
±0.001
±0.004
±0.008
±0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
±0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN8193.2
October 12, 2006
20
X9410
Thin Shrink Small Outline Package Family (TSSOP)
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
0.25 M C A B
D
A
(N/2)+1
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
N
A
A1
A2
b
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
6.50
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
7.80
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
9.70
6.40
4.40
0.65
0.60
1.00
Max
±0.05
PIN #1 I.D.
E
E1
±0.05
+0.05/-0.06
+0.05/-0.06
±0.10
c
0.20 C B A
2X
1
(N/2)
D
N/2 LEAD TIPS
B
E
Basic
TOP VIEW
E1
e
±0.10
Basic
L
±0.15
0.05
H
e
L1
Reference
Rev. E 12/02
C
NOTES:
SEATING
PLANE
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
0.10 M C A B
b
0.10 C
N LEADS
SIDE VIEW
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
SEE DETAIL “X”
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A2
A
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8193.2
October 12, 2006
21
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