X9250US24Z-2.7
更新时间：2024-09-18 19:00:56
品牌：RENESAS
描述：Quad Digitally Controlled Potentiometer (XDCP™); SOIC24, TSSOP24; Temp Range: See Datasheet
概述
规格参数
数据手册
替代型号X9250US24Z-2.7 概述
Quad Digitally Controlled Potentiometer (XDCP™); SOIC24, TSSOP24; Temp Range: See Datasheet 数字电位计
X9250US24Z-2.7 规格参数
| 生命周期： | Unknown | 零件包装代码： | SOIC, TSSOP |
| 包装说明： | SOP, SOP24,.4 | 针数： | 24, 24 |
| Reach Compliance Code： | compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | Factory Lead Time： | 11 weeks |
| 风险等级： | 5.13 | Is Samacsys： | N |
| 其他特性： | NONVOLATILE MEMORY | 控制接口： | 3-WIRE SERIAL |
| 转换器类型： | DIGITAL POTENTIOMETER | JESD-30 代码： | R-PDSO-G24 |
| JESD-609代码： | e3 | 长度： | 15.4 mm |
| 湿度敏感等级： | 5 | 功能数量： | 4 |
| 位置数： | 256 | 端子数量： | 24 |
| 最高工作温度： | 70 °C | 最低工作温度： | |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | SOP |
| 封装等效代码： | SOP24,.4 | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE | 峰值回流温度（摄氏度）： | 260 |
| 电源： | 3/5 V | 认证状态： | Not Qualified |
| 电阻定律： | LINEAR | 最大电阻容差： | 20% |
| 最大电阻器端电压： | 5.5 V | 最小电阻器端电压： | -5.5 V |
| 座面最大高度： | 2.65 mm | 子类别： | Digital Potentiometers |
| 标称供电电压： | 2.7 V | 表面贴装： | YES |
| 技术： | CMOS | 标称温度系数： | 300 ppm/°C |
| 温度等级： | COMMERCIAL | 端子面层： | Matte Tin (Sn) - annealed |
| 端子形式： | GULL WING | 端子节距： | 1.27 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | 40 |
| 标称总电阻： | 50000 Ω | 宽度： | 7.5 mm |
| Base Number Matches： | 1 |
X9250US24Z-2.7 数据手册
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X9250
FN8165
Rev.3.00
August 29, 2006
Low Noise/Low Power/SPI Bus/256 Taps Quad Digitally Controlled
Potentiometers (XDCP™)
FEATURES
DESCRIPTION
The X9250 integrates
potentiometers (XDCP) on a monolithic CMOS
integrated circuit.
• Four potentiometers in one package
• 256 resistor taps/pot - 0.4% resolution
• SPI serial interface
4
digitally controlled
• Wiper resistance, 40 typical @ V
= 5V
CC
The digitally controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
SPI bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array though the switches. Power up recalls
the contents of DR0 to the WCR.
• Four nonvolatile data registers for each pot
• Nonvolatile storage of wiper position
• Standby current < 5µA max (total package)
• Power supplies
—V
= 2.7V to 5.5V
CC
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
• 100k, 50k total pot resistance
• High reliability
—Endurance – 100,000 data changes per bit per
register
—Register data retention - 100 years
• 24 Ld SOIC, 24 Ld TSSOP
• Dual supply version of X9251
• Pb-free plus anneal available (RoHS compliant)
The XDCP can be used as
a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
V
V
V+
V-
CC
Pot 0
SS
R
R
R
R
V
/R
H0 H0
R
R
R
R
0
1
0
1
Wiper
V
/R
H2 H2
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 2
Counter
Register
(WCR)
V
/R
L0 L0
HOLD
2
3
2
3
V
/R
L2 L2
CS
SCK
SO
V
V
/R
W0 W0
V
/R
W2 W2
Interface
and
Control
SI
8
Circuitry
A0
A1
/R
W1 W1
Data
V
V
/R
W3 W3
WP
R
R
R
R
0
1
R
R
R
R
V
/R
H1 H1
Wiper
Counter
Register
(WCR)
0
1
3
/R
Wiper
Counter
Register
(WCR)
H3 H3
Resistor
Array
Pot1
Resistor
Array
Pot 3
2
3
V
/R
L1 L1
2
V
/R
L3 H3
FN8165 Rev.3.00
August 29, 2006
Page 1 of 20
X9250
Ordering Information
PART
MARKING
POTENTIOMETER
ORGANIZATION (k)
TEMP. RANGE
(°C)
PART NUMBER
X9250TS24I
V
LIMITS (V)
PACKAGE
PKG. DWG. #
CC
X9250TS I
5 ±10%
100
-40 to +85
-40 to +85
24 Ld SOIC (300 mil) M24.3
X9250TS24IZ (Note)
X9250TS ZI
X9250TV I
X9250TV ZI
24 Ld SOIC (300 mil) M24.3
(Pb-free)
X9250TV24I
-40 to +85
-40 to +85
24 Ld TSSOP
(4.4mm)
MDP0044
X9250TV24IZ (Note)
24 Ld TSSOP
MDP0044
(4.4mm) (Pb-free)
X9250US24
X9250US
50
0 to +70
0 to +70
24 Ld SOIC (300 mil) M24.3
X9250US24Z (Note)
X9250US Z
24 Ld SOIC (300 mil) M24.3
(Pb-free)
X9250US24I
X9250US I
-40 to +85
-40 to +85
24 Ld SOIC (300 mil) M24.3
X9250US24IZ (Note)
X9250US ZI
24 Ld SOIC (300 mil) M24.3
(Pb-free)
X9250UV24I
X9250UV I
X9250UV ZI
X9250TS F
-40 to +85
-40 to +85
24 Ld TSSOP
(4.4mm)
MDP0044
X9250UV24IZ (Note)
X9250TS24-2.7
24 Ld TSSOP
(4.4mm) (Pb-free)
MDP0044
-2.7 to 5.5
100
0 to +70
0 to +70
24 Ld SOIC (300 mil) M24.3
X9250TS24Z-2.7 (Note) X9250TS ZF
24 Ld SOIC (300 mil) M24.3
(Pb-free)
X9250TS24I-2.7*
X9250TS G
-40 to +85
-40 to +85
24 Ld SOIC (300 mil) M24.3
X9250TS24IZ-2.7*
(Note)
X9250TS ZG
24 Ld SOIC (300 mil) M24.3
(Pb-free)
X9250TV24I-2.7
X9250TV G
-40 to +85
-40 to +85
24 Ld TSSOP
(4.4mm)
MDP0044
X9250TV24IZ-2.7 (Note) X9250TV ZG
24 Ld TSSOP
MDP0044
(4.4mm) (Pb-free)
X9250US24-2.7*
X9250US F
50
0 to +70
0 to +70
24 Ld SOIC (300 mil) M24.3
X9250US24Z-2.7* (Note) X9250US ZF
24 Ld SOIC (300 mil) M24.3
(Pb-free)
X9250US24I-2.7
X9250US G
-40 to +85
-40 to +85
24 Ld SOIC (300 mil) M24.3
X9250US24IZ-2.7 (Note) X9250US ZG
24 Ld SOIC (300 mil) M24.3
(Pb-free)
X9250UV24-2.7
X9250UV F
0 to +70
0 to +70
24 Ld TSSOP
(4.4mm)
MDP0044
X9250UV24Z-2.7 (Note) X9250UV ZF
24 Ld TSSOP
(4.4mm) (Pb-free)
MDP0044
MDP0044
MDP0044
X9250UV24I-2.7
X9250UV G
-40 to +85
-40 to +85
24 Ld TSSOP
(4.4mm)
X9250UV24IZ-2.7 (Note) X9250UV ZG
*Add "T1" suffix for tape and reel.
24 Ld TSSOP
(4.4mm) (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8165 Rev.3.00
August 29, 2006
Page 2 of 20
X9250
PIN DESCRIPTIONS
Serial Output (SO)
V /R (V /R )
V
/R
W
W
W0 W0 - W3 W3
The wiper pins are equivalent to the wiper terminal of a
mechanical potentiometer.
SO is a serial data output pin. During a read cycle, data
is shifted out on this pin. Data is clocked out by the
falling edge of the serial clock.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Analog Supplies (V+, V-)
The analog supplies V+, V- are the supply voltages for
the XDCP analog section.
PIN CONFIGURATION
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9250.
SOIC/TSSOP
S0
A0
1
2
24
23
22
21
20
19
18
17
16
15
HOLD
SCK
Chip Select (CS)
When CS is HIGH, the X9250 is deselected and the SO
pin is at high impedance, and (unless an internal write
cycle is underway) the device will be in the standby
state. CS LOW enables the X9250, placing it in the
active power mode. It should be noted that after a
power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.
V
/R
W3 W3
3
V
V
V
/R
L2 L2
V
/R
H3 H3
4
/R
H2 L2
/R
5
V
/R
W2 W2
L3 L3
V–
V+
6
X9250
V
7
V
V
V
CC
SS
V
/R
/R
8
L0 L0
W1 W1
/R
V
/R
9
H1 H1
H0 H0
Hold (HOLD)
V
/R
10
V
/R
W0 W0
L1 L1
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause the
serial communication with the controller without resetting
the serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH
at all times.
CS
11
12
14
13
A1
SI
WP
PIN NAMES
Symbol
Description
Serial Clock
SCK
Device Address (A - A )
0
1
SI, SO
A -A
Serial Data
The address inputs are used to set the least significant 2
bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with the
X9250. A maximum of 4 devices may occupy the SPI
serial bus.
Device Address
0
1
V
V
/R
V
V
/R
,
Potentiometer Pins
(terminal equivalent)
H0 H0– H3 H3
/R /R
L0 L0– L3 L3
V
/R /R
V
Potentiometer Pins
(wiper equivalent)
W0 W0– W3 W3
WP
Hardware Write Protection
Analog Supplies
Potentiometer Pins
V+,V-
V /R (V /R - V /R ), V /R (V /R - V /R
)
H
H
H0 H0 H3 H3 L0 L0 L3 L3
L
L
V
V
System Supply Voltage
System Ground
CC
SS
The R and R pins are equivalent to the terminal
H
L
connections on a mechanical potentiometer.
NC
No Connection
FN8165 Rev.3.00
August 29, 2006
Page 3 of 20
X9250
DEVICE DESCRIPTION
Serial Interface
Wiper Counter Register (WCR)
The X9250 contains four Wiper Counter Registers, one
for each XDCP potentiometer. The WCR is equivalent to
a serial-in, parallel-out register/counter with its outputs
decoded to select one of 256 switches along its resistor
array. The contents of the WCR can be altered in four
ways: it may be written directly by the host via the write
Wiper Counter Register instruction (serial load); it may
be written indirectly by transferring the contents of one of
four associated Data Registers via the XFR Data
Register or Global XFR Data Register instructions
(parallel load); it can be modified one step at a time by
the increment/decrement instruction. Finally, it is loaded
with the contents of its Data Register zero (DR0) upon
power-up.
The X9250 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be LOW
and the HOLD and WP pins must be HIGH during the
entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9250 is comprised of four resistor arrays. Each
array contains 255 discrete resistive segments that are
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical
The Wiper Counter Register is a volatile register; that is,
its contents are lost when the X9250 is powered-down.
Although the register is automatically loaded with the
value in R0 upon power-up, this may be different from
the value present at power-down.
potentiometer (V /R and V /R inputs).
H
H
L
L
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V /R ) output. Within each individual array only one
Data Registers
W
W
switch may be turned on at a time.
Each potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the Data
Registers is a nonvolatile operation and will take a
maximum of 10ms.
These switches are controlled by a Wiper Counter
Register (WCR). The 8 bits of the WCR are decoded to
select, and enable, one of 256 switches.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system
parameters or user preference data.
Data Register Detail
(MSB)
D7
(LSB)
D0
D6
D5
D4
NV
D3
NV
D2
NV
D1
NV
NV
NV NV
NV
FN8165 Rev.3.00
August 29, 2006
Page 4 of 20
X9250
Figure 1. Detailed Potentiometer Block Diagram
(One of Four Arrays)
Serial Data Path
V /R
H H
Serial
Bus
Input
From Interface
Circuitry
C
o
u
n
t
Register 0
Register 2
Register 1
8
8
Parallel
Bus
Input
e
r
Wiper
Counter
Register
(WCR)
D
e
c
o
d
e
Register 3
Inc/Dec
Logic
If WCR = 00[H] then V /R = V /R
L
W
W
L
UP/DN
UP/DN
If WCR = FF[H] then V /R = V /R
H
W
W
H
V /R
L
L
Modified SCK
CLK
V
/R
W
W
Write in Process
Figure 2. Identification Byte Format
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by the
device. The progress of this internal write operation can
be monitored by a write in process bit (WIP). The WIP bit
is read with a read status command.
Device Type
Identifier
0
1
0
1
0
0
A1
A0
Device Address
INSTRUCTIONS
Instruction Byte
Identification (ID) Byte
The next byte sent to the X9250 contains the instruction
and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of the four pots and, when applicable, they
point to one of four associated registers. The format is
shown below in Figure 3.
The first byte sent to the X9250 from the host, following
a CS going HIGH to LOW, is called the Identification
byte. The most significant four bits of the slave address
are a device type identifier, for the X9250 this is fixed as
0101[B] (refer to Figure 2).
The two least significant bits in the ID byte select one of
four devices on the bus. The physical device address is
Figure 3. Instruction Byte Format
defined by the state of the A - A input pins. The X9250
0
1
Register
Select
compares the serial data stream with the address input
state; a successful compare of both address bits is
required for the X9250 to successfully continue the
I3
I2
I1
I0
R1 R0
P1
P0
command sequence. The A - A inputs can be actively
0
1
driven by CMOS input signals or tied to V
or V
.
CC
SS
Instructions
Pot Select
The remaining two bits in the slave byte must be set to 0.
The four high order bits of the instruction byte specify the
register oriented instruction is issued. The last two bits
operation. The next two bits (R and R ) select one of
the four registers that is to be acted upon when a
(P1 and P ) selects which one of the four potentiometers
is to be affected by the instruction.
1
0
0
FN8165 Rev.3.00
August 29, 2006
Page 5 of 20
X9250
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte. These
instructions are:
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9250; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register. These instructions are:
– XFR Data Register to Wiper Counter Register—This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
– Read Wiper Counter Register—read the current wiper
position of the selected pot,
– XFR Wiper Counter Register to Data Register—This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.
– Write Wiper Counter Register—change current wiper
position of the selected pot,
– Global XFR Data Register to Wiper Counter Regiter—
This transfers the contents of all specified Data Regis-
ters to the associated Wiper Counter Registers.
– Read Data Register—read the contents of the
selected data register;
– Write Data Register—write a new value to the selected
data register.
– Global XFR Wiper Counter Register to Data Regiter—
This transfers the contents of all Wiper Counter Regis-
ters to the specified associated Data Registers.
– Read Status—This command returns the contents of
the WIP bit which indicates if the internal write cycle is
in progress.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper
The sequence of these operations is shown in Figure 5
and Figure 6.
The final command is Increment/Decrement. It is
different from the other commands, because it’s length is
indeterminate. Once the command is issued, the master
can clock the selected wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning
to this action will be delayed by t
. A transfer from the
WRL
WCR (current wiper position), to a Data Register is a
write to nonvolatile memory and takes a minimum of t
WR
capability to the host. For each SCK clock pulse (t
)
to complete. The transfer can occur between one of the
four potentiometers and one of its associated registers;
or it may occur globally, where the transfer occurs
between all potentiometers and one associated register.
HIGH
while SI is HIGH, the selected wiper will move one
resistor segment towards the V /R terminal. Similarly,
H
H
for each SCK clock pulse while SI is LOW, the selected
wiper will move one resistor segment towards the V /R
L
L
terminal. A detailed illustration of the sequence and timing
for this operation are shown in Figure 7 and Figure 8.
FN8165 Rev.3.00
August 29, 2006
Page 6 of 20
X9250
Figure 4. Two-Byte Instruction Sequence
CS
SCK
SI
0
1
0
1
0
0
A1 A0
I3 I2
I1 I0 R1 R0 P1 P0
Figure 5. Three-Byte Instruction Sequence (Write)
CS
SCL
SI
0
0
0
1
0
1
A1 A0
I3 I2
I1 I0 R1 R0 P1 P0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 6. Three-Byte Instruction Sequence (Read)
CS
SCL
SI
Don’t Care
0
0
0
1
0
1
A1 A0
I3 I2
I1 I0 R1 R0 P1 P0
S0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 7. Increment/Decrement Instruction Sequence
CS
SCK
SI
P1
0
1
0
1
0
0
A1 A0
I3 I2
I1 I0
0
0
P0
I
I
D
E
C
1
I
D
E
C
n
N
C
1
N
C
2
N
C
n
FN8165 Rev.3.00
August 29, 2006
Page 7 of 20
X9250
Figure 8. Increment/Decrement Timing Limits
t
WRID
SCK
SI
Voltage Out
V
/R
W
W
INC/DEC CMD Issued
Table 1. Instruction Set
Instruction
Instruction Set
I
I
I
I
R
R
P
P
Operation
Read the contents of the Wiper Counter
Register pointed to by P - P
3
2
1
0
1
0
1
0
Read Wiper Counter
Register
1
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
P
P
1
0
1
0
Write Wiper Counter
Register
1
1
1
1
0
0
P
P
P
P
P
P
P
P
Write new value to the Wiper Counter Register
pointed to by P - P
1
1
1
1
0
0
0
0
1
0
Read Data Register
R
R
Read the contents of the Data Register
pointed to by P - P and R - R
1
1
1
0
0
0
1
0
1
0
Write Data Register
R
R
R
R
Write new value to the Data Register pointed to
by P - P and R - R
1
0
1
0
XFR Data Register to
Wiper Counter Register
Transfer the contents of the Data Register
pointed to by R - R to the Wiper Counter
1
0
Register pointed to by P - P
1
0
XFR Wiper Counter
Register to Data Register
1
0
1
1
0
0
1
0
0
0
1
0
R
R
R
R
R
R
P
P
Transfer the contents of the Wiper Counter
Register pointed to by P - P to the Register
1
1
1
0
0
0
1
0
1
0
pointed to by R - R
1
0
Global XFR Data Register
to Wiper Counter Register
0
0
Transfer the contents of the Data Registers
pointed to by R - R of all four pots to their
1
0
respective Wiper Counter Register
Global XFR Wiper Counter
Register to Data Register
0
0
Transfer the contents of all Wiper Counter
Registers to their respective data Registers
pointed to by R - R of all four pots
1
0
Increment/Decrement
Wiper Counter Register
0
0
0
1
1
0
0
1
0
0
P
P
Enable Increment/decrement of the Wiper
Counter Register pointed to by P - P
1
0
1
0
Read Status (WIP bit)
0
0
0
1
Read the status of the internal write cycle, by
checking the WIP bit.
FN8165 Rev.3.00
August 29, 2006
Page 8 of 20
X9250
Instruction Format
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Counter Register
(2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register(WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
wiper position
(sent by X9250 on SO)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W W W
P P P P P P P P
A
1
A
0
P
1
P
0
0
1
0
1
0
0
1
0
0
1
0
0
7
6 5 4 3 2 1 0
Write Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
Data Byte
(sent by Host on SI)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W W W
P P P P P P P P
A
1
A
0
P
1
P
0
0
1
0
1
0
0
1
0
1
0
0
0
7
6 5 4 3 2 1 0
Read Data Register (DR)
device type
identifier
device
addresses
instruction DR and WCR
opcode addresses
Data Byte
(sent by X9250 on SO)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W W W
P P P P P P P P
A
1
A
0
R
1
R
0
P
1
P
0
0
1
0
1
0
0
1 0 1 1
7
6 5 4 3 2 1 0
Write Data Register (DR)
device type
identifier
device
addresses
instruction DR and WCR
opcode addresses
Data Byte
(sent by host on SI)
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
W W W W W W W W
P P P P P P P P
A
1
A
0
R
1
R
0
P
1
P
0
0
1
0
1
0
0
1 1 0 0
7
6
5 4 3 2 1 0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
DR and WCR
addresses
CS
Falling
Edge
CS
Rising
Edge
A
1
A
0
0
1
0
1
0
0
1 1 0 1 R1 R0 P1 P0
FN8165 Rev.3.00
August 29, 2006
Page 9 of 20
X9250
Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
identifier
device
addresses
instruction DR and WCR
opcode addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
A
1
A
0
R
1
R
0
P
1
P
0
0
1
0
1
0
0
1 1 1 0
Increment/Decrement Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
increment/decrement
(sent by master on SI)
CS
Falling
Edge
CS
Rising
Edge
A A
1
P P
X X
0
1
0
1
0
0
0
0
1
0
I/D I/D
.
.
.
. I/D I/D
0
1 0
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
DR
addresses
CS
Falling
Edge
CS
Rising
Edge
A
1
A
0
R R
1 0
0
1
0
1
0
0
0
0
0
1
0 0
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
identifier
device
addresses
instruction
opcode
DR
addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
A A
1
R R
1 0
0
1
0
1
0
0
1
0
0
0
0 0
0
Read Status
device type
identifier
device
addresses
instruction
opcode
Data Byte
(sent by X9250 on SO)
CS
CS
Falling
Edge
Rising
Edge
W
I
P
A A
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
FN8165 Rev.3.00
August 29, 2006
Page 10 of 20
X9250
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias........................ -65 to +135C
Storage temperature ............................. -65 to +150C
Voltage on SCK, SCL or any address input
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
with respect to V ................................. -1V to +7V
SS
Voltage on V+ (referenced to V )........................10V
SS
Voltage on V- (referenced to V )........................-10V
SS
(V+) - (V-) ..............................................................12V
Any V /R ..............................................................V+
H
H
Any V /R .................................................................V-
L
L
Lead temperature (soldering, 10s) .................. +300C
(10s)............................................................±15mA
I
W
RECOMMENDED OPERATING CONDITIONS
(4)
Temp
Min.
0C
-40C
Max.
+70C
+85C
Device
X9250
Supply Voltage (V ) Limits
CC
Commercial
Industrial
5V 10%
2.7V to 5.5V
X9250-2.7
POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
End to end resistance tolerance
Power rating
Min.
Typ.
Max.
±20
50
Unit
%
Test Conditions
mW
mA
+25°C, each pot
I
Wiper current
±7.5
250
+5.5
+5.5
-4.5
-2.7
V+
W
R
Wiper resistance
150
Wiper current = 1mA
W
Vv+
Voltage on V+ pin
X9250
+4.5
+2.7
-5.5
-5.5
V-
V
X9250-2.7
X9250
Vv-
Voltage on V- pin
V
X9250-2.7
V
Voltage on any V /R or V /R pin
V
dBV
%
TERM
H
H
L
L
Noise
-120
0.6
Ref: 1kHz
(4)
Resolution
(1)
(3)
Absolute linearity
Relative linearity
±1
MI
V
V
- V
w(n)(expected)
w(n)(actual)
[V
(2)
(3)
MI
±0.6
]
w(n + 1 - w(n) + MI
Temperature coefficient of R
300
ppm/°C
ppm/°C
TOTAL
Ratiometric Temperature
Coefficient
±20
C /C /C
W
Potentiometer Capacitances
10/10/25
pF
See Circuit #3
H
L
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiom-
eter. It is a measure of the error in step size.
(3) MI = RTOT/255 or (V /R - V /R )/255, single pot
H
H
L
L
(4) Individual array resolutions.
FN8165 Rev.3.00
August 29, 2006
Page 11 of 20
X9250
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
I
V
supply current
400
µA
f = 2MHz, SO = Open,
SCK
CC1
CC
(active)
Other Inputs = V
SS
I
V
supply current
1
mA
f
= 2MHz, SO = Open,
CC2
CC
(nonvolatile write)
SCK
Other Inputs = V
SS
I
V
current (standby)
CC
5
µA
µA
µA
V
SCK = SI = V , Addr. = V
SS SS
SB
I
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
10
10
V
V
= V to V
SS
LI
IN
CC
CC
I
= V to V
SS
LO
OUT
V
V
x 0.7
V
+ 0.1
IH
CC
-0.5
CC
V
V
x 0.3
V
IL
CC
0.4
V
V
I
= 3mA
OL
OL
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit per register
Years
CAPACITANCE
Symbol
Test
Output capacitance (SO)
Input capacitance (A0, A1, SI, and SCK, CS)
Max.
Unit
pF
Test Conditions
= 0V
(5)
C
8
6
V
OUT
OUT
(5)
C
pF
V
= 0V
IN
IN
POWER-UP TIMING
Symbol
Parameter
Min.
Max.
Unit
ms
(6)
t
Power-up to initiation of read operation
Power-up to initiation of write operation
1
5
PUR
(6)
t
ms
PUW
(7)
t
V
V power up ramp rate
CC
0.2
50
V/msec
R
CC
POWER UP AND DOWN REQUIREMENT
The are no restrictions on the sequencing of the bias supplies V , V+, and V- provided that all three supplies reach
CC
their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than V+
and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their
final value. The V
ramp rate spec is always in effect.
CC
Notes: (5) This parameter is periodically sampled and not 100% tested
(6) t and t are the delays required from the time the third (last) power supply (V , V+ or V-) is stable until the specific instruction can be
PUR PUW CC
issued. These parameters are periodically sampled and not 100% tested.
(7) Sample tested only.
A.C. TEST CONDITIONS
Input pulse levels
V
x 0.1 to V
x 0.9
CC
CC
10ns
Input rise and fall times
Input and output timing level
V
x 0.5
CC
FN8165 Rev.3.00
August 29, 2006
Page 12 of 20
X9250
Circuit #3 SPICE Macro Model
EQUIVALENT A.C. LOAD CIRCUIT
5V
2.7V
R
TOTAL
R
R
L
H
C
L
1533
C
H
C
W
10pF
SDA Output
10pF
25pF
100pF
100pF
R
W
AC TIMING
Symbol
Parameter
Min.
Max.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
f
SSI/SPI clock frequency
SSI/SPI clock cycle time
SSI/SPI clock high time
SSI/SPI clock low time
Lead time
2.0
SCK
t
500
200
200
250
250
50
CYC
t
WH
t
WL
t
LEAD
t
Lag time
LAG
t
SI, SCK, HOLD and CS input setup time
SI, SCK, HOLD and CS input hold time
SI, SCK, HOLD and CS input rise time
SI, SCK, HOLD and CS input fall time
SO output disable Time
SU
t
75
H
t
2
RI
t
2
FI
t
0
0
500
100
DIS
t
SO output valid time
V
t
SO output hold time
HO
RO
t
SO output rise time
50
50
t
SO output fall time
FO
t
HOLD time
400
100
100
HOLD
t
HOLD setup time
HSU
t
HOLD hold time
HH
t
HOLD low to output in high Z
HOLD high to output in low Z
Noise suppression time constant at SI, SCK, HOLD and CS inputs
CS deselect time
100
100
HZ
t
LZ
T
TBD
I
t
2
0
0
CS
t
WP, A0 and A1 setup time
WP, A0 and A1 hold time
WPASU
t
WPAH
FN8165 Rev.3.00
August 29, 2006
Page 13 of 20
X9250
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Unit
t
High-voltage write cycle time (store instructions)
5
10
ms
WR
XDCP TIMING
Symbol
Parameter
Min. Max. Unit
t
Wiper response time after the third (last) power supply is stable
Wiper response time after instruction issued (all load instructions)
10
10
40
µs
µs
µs
WRPO
t
WRL
t
Wiper response time from an active SCL/SCK edge (increment/decrement instruc-
tion)
WRID
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
TIMING DIAGRAMS
Input Timing
t
CS
CS
t
t
t
LAG
LEAD
CYC
SCK
...
WH
t
t
FI
t
RI
t
t
t
WL
SU
H
...
MSB
LSB
SI
High Impedance
SO
FN8165 Rev.3.00
August 29, 2006
Page 14 of 20
X9250
Output Timing
CS
SCK
SO
...
...
t
t
t
DIS
V
HO
MSB
LSB
ADDR
SI
Hold Timing
CS
t
t
HH
HSU
SCK
...
t
t
FO
RO
SO
SI
t
t
LZ
HZ
t
HOLD
HOLD
XDCP Timing (for all Load Instructions)
CS
SCK
...
...
t
WRL
MSB
LSB
SI
VWx
High Impedance
SO
FN8165 Rev.3.00
August 29, 2006
Page 15 of 20
X9250
XDCP Timing (for Increment/Decrement Instruction)
CS
SCK
VWx
...
t
WRID
...
...
ADDR
Inc/Dec
SI
Inc/Dec
High Impedance
SO
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
t
t
WPAH
WPASU
WP
A0
A1
FN8165 Rev.3.00
August 29, 2006
Page 16 of 20
X9250
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+V
R
V
R
V
/R
W
W
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
Voltage Regulator
V
+
–
S
V
V
V (REG)
O
317
O
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
adj 2
O
2
1
S
O
2
1
Offset Voltage Adjustment
Comparator with Hysterisis
R
R
2
1
V
–
+
S
V
V
S
O
100k
–
+
V
O
TL072
R
R
1
2
10k
10k
+12V
V
V
= {R /(R +R ) V (max)
1 1 2 O
UL
LL
10k
-12V
= {R /(R +R ) V (min)
1
1
2
O
FN8165 Rev.3.00
August 29, 2006
Page 17 of 20
X9250
Application Circuits (continued)
Attenuator
Filter
C
V
+
–
S
R
V
R
R
2
O
1
–
+
R
V
O
V
S
3
R
2
R
4
R
= R = R = R = 10k
2 3 4
1
R
1
G
= 1 + R /R
2 1
V
= G V
S
O
O
fc = 1/(2RC)
-1/2 G +1/2
Inverting Amplifier
Equivalent L-R Circuit
R
R
2
1
V
S
R
2
C
1
–
+
V
+
–
S
V
O
R
R
1
Z
IN
V
= G V
S
O
G = - R /R
2
1
3
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
C
R
R
1
2
–
+
–
+
R
}
}
A
R
B
frequency R , R , C
1
2
amplitude R , R
A
B
FN8165 Rev.3.00
August 29, 2006
Page 18 of 20
X9250
Thin Shrink Small Outline Package Family (TSSOP)
MDP0044
0.25 M C A B
N
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
D
A
(N/2)+1
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
A
A1
A2
b
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
6.50
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
7.80
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
9.70
6.40
4.40
0.65
0.60
1.00
Max
±0.05
PIN #1 I.D.
E
E1
±0.05
+0.05/-0.06
+0.05/-0.06
±0.10
c
0.20 C B A
2X
1
(N/2)
D
N/2 LEAD TIPS
B
E
Basic
TOP VIEW
E1
e
±0.10
Basic
L
±0.15
0.05
H
e
L1
Reference
Rev. E 12/02
C
NOTES:
SEATING
PLANE
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
0.10 M C A B
b
0.10 C
N LEADS
SIDE VIEW
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
SEE DETAIL “X”
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A2
A
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
FN8165 Rev.3.00
August 29, 2006
Page 19 of 20
X9250
Small Outline Plastic Packages (SOIC)
M24.3 (JEDEC MS-013-AD ISSUE C)
N
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.020
-
0.30
-
1
2
3
L
0.51
9
SEATING PLANE
A
0.0091
0.5985
0.2914
0.0125
0.32
-
-A-
0.6141 15.20
15.60
7.60
3
h x 45°
D
0.2992
7.40
4
-C-
0.05 BSC
1.27 BSC
-
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
24
24
7
0°
8°
0°
8°
-
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
© Copyright Intersil Americas LLC 2005-2006. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8165 Rev.3.00
August 29, 2006
Page 20 of 20
X9250US24Z-2.7 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| X9250US24-2.7 | INTERSIL | Low Noise/Low Power/SPI Bus/256 Taps | 类似代替 |
|
X9250US24Z-2.7 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| X9250US24Z-2.7T1 | RENESAS | Quad Digitally Controlled Potentiometer (XDCP&trade;); SOIC24, TSSOP24; Temp Range: See Datasheet | 获取价格 |
|
| X9250US24ZT1 | RENESAS | Quad Digitally Controlled Potentiometer (XDCP&trade;); SOIC24, TSSOP24; Temp Range: See Datasheet | 获取价格 |
|
| X9250UV24 | INTERSIL | Low Noise/Low Power/SPI Bus/256 Taps | 获取价格 |
|
| X9250UV24 | XICOR | Quad Digitally Controlled Potentiometers (XDCP) | 获取价格 |
|
| X9250UV24-2.7 | INTERSIL | Low Noise/Low Power/SPI Bus/256 Taps | 获取价格 |
|
| X9250UV24-2.7 | XICOR | Quad Digitally Controlled Potentiometers (XDCP) | 获取价格 |
|
| X9250UV24I | INTERSIL | Low Noise/Low Power/SPI Bus/256 Taps | 获取价格 |
|
| X9250UV24I | XICOR | Quad Digitally Controlled Potentiometers (XDCP) | 获取价格 |
|
| X9250UV24I-2.7 | INTERSIL | Low Noise/Low Power/SPI Bus/256 Taps | 获取价格 |
|
| X9250UV24I-2.7 | XICOR | Quad Digitally Controlled Potentiometers (XDCP) | 获取价格 |
|
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