X4043S8IZT1 [RENESAS]
CPU Supervisor with 4kbit EEPROM; MSOP8, SOIC8; Temp Range: See Datasheet;
| 型号： | X4043S8IZT1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | CPU Supervisor with 4kbit EEPROM; MSOP8, SOIC8; Temp Range: See Datasheet 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总24页 (文件大小：903K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
X4043, X4045
4k, 512 x 8 Bit CPU Supervisor with 4kbit EEPROM
FN8118
Rev 3.00
December 9, 2015
FEATURES
DESCRIPTION
• Selectable watchdog timer
The X4043/45 combines four popular functions,
Power-on Reset Control, Watchdog Timer, Supply
Voltage Supervision, and Block Lock Protect Serial
EEPROM Memory in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
• Low V detection and reset assertion
CC
—Five standard reset threshold voltages
—Adjust low V reset threshold voltage using
CC
special programming sequence
—Reset signal valid to V = 1V
CC
• Low power CMOS
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog OFF
—3mA active current
• 4kbits of EEPROM
—16-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 16, 32, 64 or 128 bytes
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
™
of EEPROM array with Block Lock protection
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—8 Ld SOIC
—8 Ld MSOP
The device’s low V
detection circuitry protects the
CC
user’s system from low voltage conditions, resetting the
system when V falls below the minimum V trip
CC
CC
point. RESET/RESET is asserted until V
returns to
CC
proper operating level and stabilizes. Five industry stan-
dard V thresholds are available, however, Intersil’s
—8 Ld PDIP
TRIP
• Pb-free plus anneal available (RoHS compliant)
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
BLOCK DIAGRAM
Watchdog Transition
Detector
Watchdog
Timer Reset
WP
Protect Logic
RESET (X4043)
RESET (X4045)
Data
Register
SDA
SCL
Status
Register
EEPROM Array
Command
Decode &
Control
Reset &
Watchdog
Timebase
Logic
VCC Threshold
Reset logic
Power-on and
Low Voltage
Reset
VCC
+
-
VTRIP
Generation
FN8118 Rev 3.00
December 9, 2015
Page 1 of 24
X4043, X4045
Ordering Information
VCC
RANGE RANGE RANGE
(V) (V) (°C)
VTRIP
TEMP
PART NUMBER RESET
(ACTIVE LOW)
PART
MARKING
PART NUMBER RESET
(ACTIVE HIGH)
PART
MARKING
PACKAGE
X4043S8Z-4.5A (Note)
X4043S8IZ-4.5A (Note)
X4043 Z AL X4045S8Z-4.5A (Note)
X4043 Z AM X4045S8IZ-4.5A (Note)
X4045 Z AL
X4045 Z AM
DBH
4.5-5.5 4.5-4.75 0 to 70 8 Ld SOIC (Pb-free)
-40 to 85 8 Ld SOIC (Pb-free)
X4043M8Z-4.5A (Note)
DAZ
X4045M8Z-4.5A (Note)
(No longer available,
recommended replacement:
X4045S8Z-4.5A)
0 to 70 8 Ld MSOP (Pb-free)
X4043M8IZ-4.5A (Note)
DAU
X4045M8IZ-4.5A (Note)
(No longer available,
recommended replacement:
X4045S8IZ-4.5A)
DBE
-40 to 85 8 Ld MSOP (Pb-free)
0 to 70 8 Ld PDIP (Pb-free)
-40 to 85 8 Ld PDIP (Pb-free)
X4043PZ-4.5A (Note)
(No longer available,
recommended replacement:
X4043M8Z-4.5A)
X4043P Z AL X4045PZ-4.5A (Note)
X4045P Z AL
X4045P Z AM
(No longer available,
recommended replacement:
X4045S8Z-4.5A)
X4043PIZ-4.5A (Note)
(No longer available,
recommended replacement:
X4043M8IZ-4.5A)
X4043P Z AM X4045PIZ-4.5A (Note)
(No longer available,
recommended replacement:
X4045S8IZ-4.5A)
X4045S8Z* (Note)
X4045S8IZ (Note)
X4043S8Z* (Note)
X4043S8IZ* (Note)
X4043M8Z* (Note)
X4043 Z
X4043 Z I
DAW
X4045 Z
X4045 Z I
DBD
4.5-5.5 4.25-4.5 0 to 70 8 Ld SOIC (Pb-free)
-40 to 85 8 Ld SOIC (Pb-free)
X4045M8Z (Note)
0 to 70 8 Ld MSOP (Pb-free)
(No longer available,
recommended replacement:
X4045S8Z)
X4043M8IZ (Note)
DAR
X4045M8IZ (Note)
DBA
-40 to 85 8 Ld MSOP (Pb-free)
0 to 70 8 Ld PDIP (Pb-free)
-40 to 85 8 Ld PDIP (Pb-free)
(No longer available,
recommended replacement:
X4045S8IZ)
X4043PZ (Note)
X4043P
X4043P Z I
X4045PZ (Note)
X4045P Z
X4045P Z I
(No longer available,
recommended replacement:
X4043M8Z)
(No longer available,
recommended replacement:
X4045S8Z)
X4043PIZ (Note)
X4045PIZ (Note)
(No longer available,
recommended replacement:
X4043M8IZ)
(No longer available,
recommended replacement:
X4045S8IZ)
FN8118 Rev 3.00
December 9, 2015
Page 2 of 24
X4043, X4045
Ordering Information
VCC
RANGE RANGE RANGE
(V) (V) (°C)
VTRIP
TEMP
PART NUMBER RESET
(ACTIVE LOW)
PART
MARKING
PART NUMBER RESET
(ACTIVE HIGH)
PART
MARKING
PACKAGE
X4043S8Z-2.7A* (Note)
X4043S8IZ-2.7A* (Note)
X4043 Z AN X4045S8Z-2.7A (Note)
X4043 Z AP X4045S8IZ-2.7A (Note)
X4045 Z AN
X4045 Z AP
DBG
2.7-5.5 2.85-3.0 0 to 70 8 Ld SOIC (Pb-free)
-40 to 85 8 Ld SOIC (Pb-free)
X4043M8Z-2.7A (Note)
DAY
X4045M8Z-2.7A (Note)
(No longer available,
recommended replacement:
X4045S8Z-2.7A)
0 to 70 8 Ld MSOP (Pb-free)
X4043M8IZ-2.7A (Note)
DAT
X4045M8IZ-2.7A (Note)
(No longer available,
recommended replacement:
X4045S8IZ-2.7A)
DBC
-40 to 85 8 Ld MSOP (Pb-free)
0 to 70 8 Ld PDIP (Pb-free)
-40 to 85 8 Ld PDIP (Pb-free)
X4043PZ-2.7A (Note)
(No longer available,
recommended replacement:
X4043M8Z-2.7A)
X4043P Z AN X4045PZ-2.7A (Note)
X4045P Z AN
X4045P Z AP
(No longer available,
recommended replacement:
X4045S8Z-2.7A)
X4043PIZ-2.7A (Note)
(No longer available,
recommended replacement:
X4043M8IZ-2.7A)
X4043P Z AP X4045PIZ-2.7A (Note)
(No longer available,
recommended replacement:
X4045S8IZ-2.7A)
X4043S8Z-2.7* (Note)
X4043S8IZ-2.7 (Note)
X4043M8Z-2.7 (Note)
X4043 Z F
X4043 Z G
DAX
X4045S8Z-2.7* (Note)
X4045S8IZ-2.7 (Note)
X4045 Z F
X4045 Z G
DBF
2.7-5.5 2.55-2.7 0 to 70 8 Ld SOIC (Pb-free)
-40 to 85 8 Ld SOIC (Pb-free)
X4045M8Z-2.7 (Note)
(No longer available,
recommended replacement:
X4045S8Z-2.7)
0 to 70 8 Ld MSOP (Pb-free)
X4043M8IZ-2.7(Note)
DAS
X4045M8IZ-2.7 (Note)
(No longer available,
recommended replacement:
X4045S8IZ-2.7)
DBB
-40 to 85 8 Ld MSOP (Pb-free)
0 to 70 8 Ld PDIP (Pb-free)
-40 to 85 8 Ld PDIP (Pb-free)
X4043PZ-2.7 (Note)
(No longer available,
recommended replacement:
X4043M8Z-2.7)
X4043P Z F X4045PZ-2.7 (Note)
X4045P Z F
X4045P Z G
(No longer available,
recommended replacement:
X4045S8Z-2.7)
X4043PIZ-2.7 (Note)
(No longer available,
recommended replacement:
X4043M8IZ-2.7)
X4043P Z G X4045PIZ-2.7 (Note)
(No longer available,
recommended replacement:
X4045S8IZ-2.7)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8118 Rev 3.00
December 9, 2015
Page 3 of 24
X4043, X4045
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s block lock protection. The
array is internally organized as x 8. The device features
an 2-wire interface and software protocol allowing oper-
PIN CONFIGURATION
8-Pin JEDEC SOIC, MSOP
(PDIP no longer available or supported)
2
ation on an I C bus.
VCC
1
2
3
4
8
7
6
5
NC
NC
™
WP
SCL
SDA
The device utilizes Intersil’s proprietary Direct Write
RESET
VSS
cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
Pin
(SOIC/MSOP/DIP)
Name
NC
Function
1
2
3
No internal connections
No internal connections
NC
RESET/RESET Reset Output. RESET is an active LOW, open drain output which goes active
whenever VCC falls below VTRIP. It will remain active until VCC rises above the
VTRIP for tPURST. RESET/RESET goes active if the Watchdog Timer is enabled
and SDA remains either HIGH or LOW longer than the selectable Watchdog time
out period. RESET/RESET goes active on power-uppower-up and remains
active for 250ms after the power supply stabilizes. RESET is an active high open
drain output. An external pull up resistor is required on the RESET/RESET pin.
4
5
VSS
Ground
SDA
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain
or open collector outputs. This pin requires a pull up resistor and the input buffer
is always active (not gated).
6
7
8
SCL
WP
Serial Clock. The Serial Clock input controls the serial bus timing for data input and
output.
Write Protect. WP HIGH prevents writes to any location in the device (including
the control register). Connect WP pin to VSS when it is not used.
VCC
Supply Voltage
FN8118 Rev 3.00
December 9, 2015
Page 4 of 24
X4043, X4045
PRINCIPLES OF OPERATION
Power-on Reset
nonvolatile control bits in the status register determine
the watchdog timer period. The microprocessor can
change these watchdog bits, or they may be “locked” by
tying the WP pin HIGH.
Application of power to the X4043/45 activates a Power-
on Reset Circuit that pulls the RESET/RESET pin active.
This signal provides several benefits.
Figure 1. Watchdog Restart
.6µs
– It prevents the system microprocessor from starting to
operate with insufficient voltage.
1.3µs
SCL
SDA
– It prevents the processor from operating prior to stabi-
lization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
Start
WDT Reset
Stop
When V exceeds the device V
threshold value for
CC
TRIP
200ms (nominal) the circuit releases RESET/RESET
allowing the system to begin operation.
EEPROM Inadvertent Write Protection
When RESET/RESET goes active as a result of a low
voltage condition (V < V ), any in-progress commu-
CC
TRIP
Low Voltage Monitoring
nications are terminated. While V
< V
, no new
CC
TRIP
During operation, the X4043/45 monitors the V
level
CC
communications are allowed and no nonvolatile write
operation can start. Nonvolatile writes in-progress when
RESET/RESET goes active are allowed to finish.
and asserts RESET/RESET if supply voltage falls below
a preset minimum V . The RESET/RESET signal
TRIP
prevents the microprocessor from operating in a power
fail or brownout condition. The RESET/RESET signal
remains active until the voltage drops below 1V. It also
Additional protection mechanisms are provided with
memory block lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
remains active until V
200ms.
returns and exceeds V
for
CC
TRIP
V
Programming
TRIP
Watchdog Timer
The X4043/45 is shipped with a standard V threshold
CC
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. A stan-
dard read or write sequence to any slave address byte
restarts the watchdog timer and prevents the
(RESET/RESET) signal going active. A minimum
sequence to reset the watchdog timer requires four
microprocessor intructions namely, a Start, Clock Low,
Clock High and Stop. (See Page 18) The state of two
(V
) voltage. This value will not change over normal
TRIP
operating and storage conditions. However, in applica-
tions where the standard V is not exactly right, or if
higher precision is needed in the V
X4043/45 threshold may be adjusted. The procedure is
described below, and uses the application of a high volt-
age control signal.
TRIP
value, the
TRIP
Figure 2. Set V
Level Sequence (V = desired V values WEL bit set)
TRIP
TRIP
CC
V
P = 15-18V
WP
0
1
2
3
4
5 6 7
0
1
2
3
4
5 6 7
0
1
2
3
4 5 6 7
SCL
SDA
A0h
01h
00h
FN8118 Rev 3.00
December 9, 2015
Page 5 of 24
X4043, X4045
Setting a V
Voltage
CASE B
TRIP
There are two procedures used to set the threshold
voltages (V ), depending if the threshold voltage to
Now if the V
(desired), perform the reset sequence as described in
the next section. The new V voltage to be applied to
(actual), is higher than the V
TRIP
TRIP
TRIP
be stored is higher or lower than the present value. For
example, if the present V is 2.9 V and the new
TRIP
TRIP
V
will now be: V
(desired) - (V
(actual) - V
CC
TRIP
TRIP TRIP
V
is 3.2 V, the new voltage can be stored directly
TRIP
(desired)).
into the V
cell. If however, the new setting is to be
TRIP
Note: This operation does not corrupt the memory
array.
lower than the present setting, then it is necessary to
“reset” the V voltage before setting the new value.
TRIP
Setting a Lower V
Voltage
Setting a Higher V
Voltage
TRIP
TRIP
In order to set V
ent value, then V
the procedure described below. Once V
to a lower voltage than the pres-
must first be “reset” according to
To set a V
threshold to a new voltage which is
TRIP
TRIP
higher than the present threshold, the user must apply
the desired V threshold voltage to the V . Then,
a programming voltage (Vp) must be applied to the
WP pin before a START condition is set up on SDA.
Next, issue on the SDA pin the Slave Address A0h,
TRIP
has been
TRIP
TRIP
CC
“reset”, then V
can be set to the desired voltage
TRIP
using the procedure described in “Setting a Higher
Voltage”.
V
TRIP
followed by the Byte Address 01h for V
and a 00h
TRIP
Resetting the V
Voltage
Data Byte in order to program V
. The STOP bit
TRIP
TRIP
following a valid write operation initiates the program-
ming sequence. WP pin must then be brought LOW to
complete the operation.
To reset a V
voltage, apply the programming volt-
TRIP
age (Vp) to the WP pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h fol-
To check if the V
has been set, first power-down
TRIP
lowed by 00h for the Data Byte in order to reset V
.
TRIP
the device. Slowly ramp up V and observe when the
CC
The STOP bit following a valid write operation initiates
the programming sequence. Pin WP must then be
brought LOW to complete the operation.
output, RESET (4043) or RESET (4045) switches. The
voltage at which this occurs is the V
Figure 2).
(actual) (see
TRIP
After being reset, the value of V
nal value of 1.7V or lesser.
becomes a nomi-
TRIP
CASE A
Now if the desired V
is greater than the V
Note: This operation does not corrupt the memory
array.
TRIP
TRIP
TRIP
(actual), then add the difference between V
(desired) - V (actual) to the original V
desired.
TRIP
TRIP
This is your new V
that should be applied to V
TRIP
CC
and the whole sequence should be repeated again
(see Figure 5).
FN8118 Rev 3.00
December 9, 2015
Page 6 of 24
X4043, X4045
Figure 3. Reset V
Level Sequence (V > 3V. WP = 15-18V, WEL bit set)
CC
TRIP
VP = 15-18V
WP
0
1 2 3 4 5 6 7
0
1
2
3
4
5 6 7
0
1 2 3 4 5 6 7
SCL
SDA
A0h
03h
00h
Figure 4. Sample V
Reset Circuit
TRIP
VP
Adjust
Run
4.7K
µC
1
8
7
6
5
RESET
2
3
4
X4043
VTRIP
Adj.
SCL
SDA
FN8118 Rev 3.00
December 9, 2015
Page 7 of 24
X4043, X4045
Figure 5. V
Programming Sequence
TRIP
VTRIP Programming
Desired
Let: MDE = Maximum Desired Error
No
VTRIP
<
MDE+
Acceptable
Present Value ?
Desired Value
YES
Error Range
MDE–
Execute
TRIP Reset Sequence
V
Error = Actual – Desired
Set VCC = desired VTRIP
New VCC applied =
V
Execute
Set Higher VTRIP Sequence
New
applied =
VCC
Old VCC applied – | Error |
Old CC applied + | Error |
Power-down
the Device
Execute Reset VTRIP
Sequence
Ramp VCC
NO
Output Switches?
(RESET)
YES
Error < MDE–
V
–
Error > MDE+
Actual
TRIP
VTRIP
= Error
Desired
| Error | < | MDE |
DONE
Control Register
The user must issue a stop after sending this byte to the
register to initiate the nonvolatile cycle that stores WD1,
WD0, BP2, BP1, and BP0. The X4043/45 will not
acknowledge any data bytes written after the first byte is
entered.
The control register provides the user a mechanism for
changing the block lock and watchdog timer settings.
The block lock and watchdog timer bits are nonvolatile
and do not change when power is removed.
The control register is accessed with a special preamble
in the slave byte (1011) and is located at address 1FFh.
It can only be modified by performing a byte write opera-
tion directly to the address of the register and only one
data byte is allowed for each register write operation.
Prior to writing to the control register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps. See "Writing to
the Control Register".
FN8118 Rev 3.00
December 9, 2015
Page 8 of 24
X4043, X4045
The state of the control register can be read at any time
by performing a random read at address 1FFh, using the
special preamble. Only one byte is read by each register
read operation. The X4043/45 resets itself after the first
byte is read. The master should supply a stop condition to
be consistent with the bus protocol, but a stop is not
required to end this operation.
WD1, WD0: Watchdog Timer Bits
The bits WD1 and WD0 control the period of the watch-
dog timer. The options are shown below.
WD1
WD0
Watchdog Time Out Period
1.4 seconds
0
0
1
1
0
1
0
1
600 milliseconds
7
6
5
4
3
2
1
0
200 milliseconds
0
WD1 WD0 BP1 BP0 RWEL WEL BP2
Disabled (factory setting)
RWEL: Register Write Enable Latch (Volatile)
Writing to the Control Register
The RWEL bit must be set to “1” prior to a write to the
Control Register.
Changing any of the nonvolatile bits of the control regis-
ter requires the following steps:
– Write a 02H to the control register to set the write
enable latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceeded
by a start and ended with a stop).
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a volatile
latch that powers up in the LOW (disabled) state. While
the WEL bit is LOW, writes to any address, including any
control registers will be ignored (no acknowledge will be
issued after the Data Byte). The WEL bit is set by writing
a “1” to the WEL bit and zeroes to the other bits of the
control register. Once set, WEL remains set until either it
is reset to 0 (by writing a “0” to the WEL bit and zeroes to
the other bits of the control register) or until the part pow-
ers up again. Writes to the WEL bit do not cause a non-
volatile write cycle, so the device is ready for the next
operation immediately after the stop condition.
– Write a 06H to the control register to set both the reg-
ister write enable latch (RWEL) and the WEL bit. This
is also a volatile cycle. The zeros in the data byte are
required. (Operation preceeded by a start and ended
with a stop).
– Write a value to the control register that has all the
control bits set to the desired state. This can be repre-
sented as 0xys t01r in binary, where xy are the WD
bits, and rst are the BP bits. (Operation preceeded by
a start and ended with a stop). Since this is a nonvola-
tile write cycle it will take up to 10ms to complete. The
RWEL bit is reset by this cycle and the sequence must
be repeated to change the nonvolatile bits again. If bit
2 is set to ‘1’ in this third step (0xys t11r) then the
RWEL bit is set, but the WD1, WD0, BP2, BP1 and
BP0 bits remain unchanged. Writing a second byte to
the control register is not allowed. Doing so aborts the
write operation and returns a NACK.
BP2, BP1, BP0: Block Protect Bits (Nonvolatile)
The block protect bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to a
protected block of memory is ignored. The block protect
bits will prevent write operations to one of eight seg-
ments of the array.
Protected Addresses
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write oper-
ation.
(Size)
Array Lock
None
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None (factory setting)
180h - 1FFh (128 bytes)
Upper 1/4 (Q4)
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write pro-
tected block.
100h - 1FFh (256 bytes) Upper 1/2 (Q3,Q4)
000h - 1FFh (512 bytes)
000h - 00Fh (16 bytes)
000h - 01Fh (32 bytes)
000h - 03Fh (64 bytes)
000h - 07Fh (128 bytes)
Full Array (All)
First Page (P1)
First 2 pgs (P2)
First 4 pgs (P4)
First 8 pgs (P8)
To illustrate, a sequence of writes to the device consist-
ing of [02H, 06H, 02H] will reset all of the nonvolatile bits
in the control register to 0. A sequence of [02H, 06H,
06H] will leave the nonvolatile bits unchanged and the
RWEL bit remains set.
FN8118 Rev 3.00
December 9, 2015
Page 9 of 24
X4043, X4045
SERIAL INTERFACE
fers, and provides the clock for both transmit and receive
operations. Therefore, the devices in this family operate
as slaves in all applications.
Serial Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data trans-
Serial Clock and Data
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 6.
Figure 6. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
Serial Start Condition
Serial Stop Condition
All commands are preceded by the start condition, which
is a HIGH to LOW transition of SDA when SCL is HIGH.
The device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any
command until this condition has been met. See Figure
7.
All communications must be terminated by a stop condi-
tion, which is a LOW to HIGH transition of SDA when SCL
is HIGH. The stop condition is also used to place the
device into the standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 6.
Figure 7. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Serial Acknowledge
acknowledge all incoming data and address bytes,
except for the slave address byte when the device iden-
tifier and/or select bits are incorrect.
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 8.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will con-
tinue to transmit data. The device will terminate further
data transmissions if an acknowledge is not detected.
The master must then issue a stop condition to return
the device to standby mode and place the device into a
known state.
The device will respond with an acknowledge after rec-
ognition of a start condition and if the correct device
identifier and select bits are contained in the slave
address byte. If a write operation is selected, the device
will respond with an acknowledge after the receipt of
each subsequent eight bit word. The device will
FN8118 Rev 3.00
December 9, 2015
Page 10 of 24
X4043, X4045
Figure 8. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from
Transmitter
Data Output
from Receiver
Start
Acknowledge
X4043/45 ADDRESSING
Slave Address Byte
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
Following a start condition, the master must output a
slave address byte. This byte consists of several parts:
– The WEL bit is set to ‘0’. In this state it is not possible
to write to the device.
– a device type identifier that is ‘1010’ to access the
array and ‘1011’ to access the control register.
– SDA pin is the input mode.
– RESET signal is active for t
.
PURST
– two bits of ‘0’.
– one bit that becomes the MSB of the address.
SERIAL WRITE OPERATIONS
Byte Write
– one bit of the slave command byte is a R/W bit. The
R/W bit of the slave address byte defines the opera-
tion to be performed. When the R/W bit is a one, then
a read operation is selected. A zero selects a write
operation. Refer to Figure 8.
For a write operation, the device requires the slave
address byte and a word address byte. This gives the
master access to any one of the words in the array. After
receipt of the word address byte, the device responds
with an acknowledge, and awaits the next eight bits of
data. After receiving the 8 bits of the data byte, the
device again responds with an acknowledge. The master
then terminates the transfer by generating a stop condition,
at which time the device begins the internal write cycle to
the nonvolatile memory. During this internal write cycle, the
device inputs are disabled, so the device will not respond to
any requests from the master. The SDA output is at high
impedance. See Figure 10.
– After loading the entire slave address byte from the SDA
bus, the device compares the input slave byte data to the
proper slave byte. Upon a correct compare, the device
outputs an acknowledge on the SDA line.
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter is
undefined on a power-up condition.
Slave Address Byte
Figure 9. X4043/45 Addressing
Slave Byte
A write to a protected block of memory will suppress the
acknowledge bit.
Array
1
0
1
0
0
0
A8 R/W
Control Reg.
1
0
1
1
Word Address
A7 A6
A5
A4
A3
A2 A1 A0
FN8118 Rev 3.00
December 9, 2015
Page 11 of 24
X4043, X4045
Figure 10. Byte Write Sequence
S
t
a
r
S
t
o
p
Signals from
the Master
Byte
Address
Slave
Address
Data
t
SDA Bus
0
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Page Write
the same page. This means that the master can write 16
bytes to the page starting at any location on that page. If
the master begins writing at location 10, and loads 12
bytes, then the first 5 bytes are written to locations 10
through 15, and the last 7 bytes are written to locations 0
through 6. Afterwards, the address counter would point
to location 7 of the page that was just written. If the mas-
ter supplies more than 16 bytes of data, then new data
over-writes the previous data, one byte at a time.
The device is capable of a page write operation. It is initi-
ated in the same manner as the byte write operation; but
instead of terminating the write cycle after the first data
byte is transferred, the master can transmit an unlimited
number of 8-bit bytes. After the receipt of each byte, the
device will respond with an acknowledge, and the
address is internally incremented by one. The page
address remains constant. When the counter reaches
the end of the page, it “rolls over” and goes back to ‘0’ on
Figure 11. Page Write Operation
(1 n 16)
S
t
a
r
S
t
o
p
Signals from
the Master
Data
(1)
Data
(n)
Slave
Address
Byte
Address
t
SDA Bus
0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Figure 12. Writing 12-bytes to a 16-byte page starting at location 10
5 Bytes
7 Bytes
Address Pointer
Ends Here
Addr = 7
Address
Address
= 6
Address
n-1
10
The master terminates the data byte loading by issuing a
stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation, all
inputs are disabled until completion of the internal write
cycle. See Figure 11 for the address, acknowledge, and
data transfer sequence.
Stops and Write Modes
Stop conditions (that terminate write operations) must be
sent by the master after sending at least 1 full data byte,
plus the subsequent ACK signal. If a stop is issued in the
middle of a data byte, or before 1 full data byte plus its
associated ACK is sent, then the device will reset itself
without performing the write. The contents of the array
will not be effected.
FN8118 Rev 3.00
December 9, 2015
Page 12 of 24
X4043, X4045
Acknowledge Polling
Figure 13. Acknowledge Polling Sequence
The disabling of the inputs during nonvolatile cycles can
be used to take advantage of the typical 5kHz write cycle
time. Once the stop condition is issued to indicate the
end of the master’s byte load operation, the device initi-
ates the internal nonvolatile cycle. Acknowledge polling
can be initiated immediately. To do this, the master
issues a start condition followed by the slave address
byte for a write or read operation. If the device is still
busy with the nonvolatile cycle then no ACK will be
returned. If the device has completed the write opera-
tion, an ACK will be returned and the host can then pro-
ceed with the read or write operation. Refer to the flow
chart in Figure 13.
Byte Load Completed
by Issuing STOP.
Enter ACK Polling
Issue START
Issue Slave Address
Byte (Read or Write)
Issue STOP
NO
ACK
Returned?
Serial Read Operations
YES
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the slave address byte is set to one. There are three
basic read operations: Current Address Reads, Random
Reads, and Sequential Reads.
NO
Nonvolatile Cycle
Complete. Continue
Command
Issue STOP
Current Address Read
YES
Internally the device contains an address counter that
maintains the address of the last word read incremented
by one. Therefore, if the last read was to address n, the
next read operation would access data from address
n+1. On power-up, the address of the address counter is
undefined, requiring a read or write operation for initial-
ization.
ContinueNormalRead
or Write Command
Sequence
PROCEED
Upon receipt of the slave address byte with the R/W bit
set to one, the device issues an acknowledge and then
transmits the eight bits of the data byte. The master termi-
nates the read operation when it does not respond with an
acknowledge during the ninth clock and then issues a
stop condition. Refer to Figure 13 for the address,
acknowledge, and data transfer sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read oper-
ation, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a stop condition.
Figure 14. Current Address Read Sequence
S
t
S
t
o
p
Slave
Address
Signals from
the Master
a
r
t
SDA Bus
1
A
C
Signals from
the Slave
Data
K
FN8118 Rev 3.00
December 9, 2015
Page 13 of 24
X4043, X4045
Random Read
bytes, the master immediately issues another start con-
dition and the slave address byte with the R/W bit set to
one. This is followed by an acknowledge from the device
and then by the eight bit word. The master terminates
the read operation by not responding with an acknowl-
edge and then issuing a stop condition. Refer to Figure
15 for the address, acknowledge, and data transfer
sequence.
Random read operation allows the master to access any
memory location in the array. Prior to issuing the slave
address byte with the R/W bit set to one, the master
must first perform a “dummy” write operation. The mas-
ter issues the start condition and the slave address byte,
receives an acknowledge, then issues the word address
bytes. After acknowledging receipts of the word address
Figure 15. Random Address Read Sequence
S
S
S
t
a
r
Slave
Address
Byte
Address
Slave
t
Signals from
the Master
t
a
r
t
Address
o
p
t
1
SDA Bus
0
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
There is a similar operation, called “Set Current
Address” where the device does no operation, but enters
a new address into the address counter if a stop is
issued instead of the second start shown in Figure 14.
The device goes into standby mode after the stop and all
bus activity will be ignored until a start is detected. The
next current address read operation reads from the
newly loaded address. This operation could be useful if
the master knows the next address it needs to read, but
is not ready for the data.
ter now responds with an acknowledge, indicating it
requires additional data. The device continues to output
data for each acknowledge received. The master termi-
nates the read operation by not responding with an
acknowledge and then issuing a stop condition.
The data output is sequential, with the data from address n
followed by the data from address n + 1. The address
counter for read operations increments through all page
and column addresses, allowing the entire memory con-
tents to be serially read during one operation. At the end of
the address space the counter “rolls over” to address
Sequential Read
0000 and the device continues to output data for each
H
Sequential reads can be initiated as either a current
address read or random address read. The first data byte
is transmitted as with the other modes; however, the mas-
acknowledge received. Refer to Figure 16 for the acknowl-
edge and data transfer sequence.
Figure 16. Sequential Read Sequence
S
Signals from
Slave
t
A
C
K
A
C
K
A
C
K
the Master
Address
o
p
SDA Bus
1
A
C
K
Signals from
the Slave
Data
(2)
Data
(n-1)
Data
(1)
Data
(n)
(n is any integer greater than 1)
FN8118 Rev 3.00
December 9, 2015
Page 14 of 24
X4043, X4045
Data Protection
Symbol Table
The following circuitry has been included to prevent
inadvertent writes:
WAVEFORM
INPUTS
OUTPUTS
– The WEL bit must be set to allow write operations.
Must be
steady
Will be
steady
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile write
cycle.
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
– A three step sequence is required before writing into
the control register to change watchdog timer or block
lock settings.
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
– The WP pin, when held HIGH, prevents all writes to
the array and the control register.
N/A
Center Line
is High
Impedance
– Communication to the device is inhibited as a result of
a low voltage condition (V < V
)any in-progress
CC
TRIP
communication is terminated.
– Block lock bits can protect sections of the memory
array from write operations.
FN8118 Rev 3.00
December 9, 2015
Page 15 of 24
X4043, X4045
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ................... -65°Cto+135°C
Storage temperature ........................ -65°C to+150°C
Voltage on any pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; the functional operation of the device
(at these or any other conditions above those listed in the
operational sections of this specification) is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
respect to V ...................................... -1.0V to +7V
SS
D.C. output current...............................................5mA
Lead temperature (soldering, 10 seconds)........ 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
70°C
Option
Supply Voltage Limits
2.7V to 5.5V
-2.7 and -2.7A
Blank and -4.5A
-40°C
+85°C
4.5V to 5.5V
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
= 2.7 to 5.5V
V
CC
Symbol
Parameter
Active supply current read
Active supply current write
Standby current AC (WDT off)
Min.
Max.
1.0
3.0
1
Unit
Test Conditions
(1)
ICC1
mA VIL = VCC x 0.1, VIH = VCC x 0.9
fSCL = 400kHz
(1)
ICC2
mA
(2)
ISB1
µA
VIL = VCC x 0.1, VIH = VCC x 0.9
fSCL= 400kHz, SDA = open
VCC = 1.22 x VCC min
(2)
ISB2
Standby current DC (WDT off)
Standby current DC (WDT on)
1
µA
µA
VSDA = VSCL = VSB
Others = GND or VSB
(2)
ISB3
20
VSDA =VSCL = VSB
Others = GND or VSB
ILI
Input leakage current
Output leakage current
10
10
µA
µA
VIN = GND to VCC
ILO
VSDA = GND to VCC
device is in standby
(3)
VIL
Input LOW voltage
Input nonvolatile
-0.5
VCC x 0.3
V
V
(3)
VIH
VCC x 0.7 VCC + 0.5
VHYS
Schmitt trigger input hysteresis
Fixed input level
0.2
.05 x VCC
V
V
VCC related level
VOL
Output LOW voltage
0.4
V
IOL = 3.0mA (2.7-5.5V)
IOL = 1.8mA (2.0-3.6V)
Notes: (1) The device enters the active state after any start, and remains active until: 9 clock cycles later if the device select bits in the slave
address byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation.
(2) The device goes into standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop that initiates a
nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave address byte.
(3) VIL min. and VIH max. are for reference only and are not tested.
FN8118 Rev 3.00
December 9, 2015
Page 16 of 24
X4043, X4045
CAPACITANCE (T = 25°C, f = 1.0 MHz, V = 5V)
A
CC
Symbol
Parameter
Max.
Unit
pF
Test Conditions
VOUT = 0V
(4)
COUT
Output capacitance (SDA, RESET/RESET)
Input capacitance (SCL, WP)
8
6
(4)
CIN
pF
VIN = 0V
Notes: (4) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
Input pulse levels
0.1 VCC to 0.9 VCC
10ns
5V
5V
Input rise and fall times
Input and output timing levels
Output load
0.5 VCC
For VOL= 0.4V
and IOL = 3 mA
4.6k
1533
Standard output load
SDA
RESET
100pF
100pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
100kHz
400kHz
Symbol
fSCL
Parameter
Min. Max.
Min.
0
Max.
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
s
s
pF
SCL clock frequency
0
100
n/a
0.9
400
tIN
Pulse width suppression time at inputs
SCL LOW to SDA data out valid
Time the bus free before start of new transmission
Clock LOW time
n/a
0.1
4.7
4.7
4.0
4.7
4.0
250
5.0
0.6
50
50
tAA
0.1
1.3
1.3
0.6
0.6
0.6
100
0
0.9
tBUF
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
Clock HIGH time
Start condition setup time
Start condition hold time
Data in setup time
Data in hold time
Stop condition setup time
Data output hold time
0.6
50
tR
SDA and SCL rise time
SDA and SCL fall time
WP setup time
1000 20 + .1Cb(6)
300 20 + .1Cb(6)
300
300
tF
tSU:WP
tHD:WP
Cb
0.4
0
0.6
WP hold time
0
Capacitive load for each bus line
400
400
Notes: (5) Typical values are for TA = 25°C and VCC = 5.0V
(6) Cb = total capacitance of one bus line in pF.
FN8118 Rev 3.00
December 9, 2015
Page 17 of 24
X4043, X4045
TIMING DIAGRAMS
Bus Timing
tF
tHIGH
tLOW
tR
SCL
tSU:STA
SDA IN
tSU:DAT
tHD:DAT
tSU:STO
tHD:STA
tAA
tDH
tBUF
SDA OUT
WP Pin Timing
START
SCL
SDA IN
WP
Clk 1
Clk 9
Slave Address Byte
tSU:WP
tHD:WP
Write Cycle Timing
SCL
8th Bit of Last Byte
ACK
SDA
tWC
Stop
Start
Condition
Condition
Nonvolatile Write Cycle Timing
(7)
Symbol
Parameter
Write cycle time
Min.
Typ.
Max.
Unit
(7)
tWC
5
10
ms
Notes: (7) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used.
FN8118 Rev 3.00
December 9, 2015
Page 18 of 24
X4043, X4045
Power-Up and Power-Down Timing
VTRIP
VCC
tPURST
0 Volts
tPURST
tF
tR
tRPD
VRVALID
RESET
(X4043)
VRVALID
RESET
(X4045)
RESET Output Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
VTRIP
Reset trip point voltage, X4043/45-4.5A
Reset trip point voltage, X4043/45
Reset trip point voltage, X4043/45-2.7A
Reset trip point voltage, X4043/45-2.7
4.5
4.62
4.38
2.92
2.62
4.75
4.5
3.0
V
4.25
2.85
2.55
2.7
tPURST
Power-up reset time out
VCC detect to RESET/RESET
VCC fall time
100
200
10
400
20
ms
µs
(8)
tRPD
(8)
tF
20
20
1
mV/µs
mV/µs
V
(8)
tR
VCC rise time
VRVALID
tWDO
Reset valid VCC
Watchdog time out period,
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
100
450
1
200
600
1.4
300
800
2
ms
ms
sec
tRSP
tRST
Watchdog Time Restart pulse width
Reset time out
1
µs
100
200
400
ms
Notes: (8) This parameter is periodically sampled and not 100% tested.
FN8118 Rev 3.00
December 9, 2015
Page 19 of 24
X4043, X4045
Watchdog Time Out For 2-Wire Interface
Start
Start
Clockin (0 or 1)
tRSP
< tWDO
SCL
SDA
tRST
tWDO
tRST
(4043) RESET
WDT
Restart
Start
Minimum Sequence to Reset WDT
SCL
SDA
V
Set/Reset Conditions
TRIP
(VTRIP
)
VCC
tTHD
VP
tTSU
WP
tVPS
tVPO
tVPH
7
SCL
SDA
0
0
7
0
7
tWC
A0h
00h
01h*
03h*
sets VTRIP
resets VTRIP
Start
* all others reserved
FN8118 Rev 3.00
December 9, 2015
Page 20 of 24
X4043, X4045
Programming Specifications: V = 2.0-5.5V; Temperature = 25°C
V
TRIP
CC
Parameter
tVPS
Description
Min.
10
10
10
10
10
1
Max. Unit
WP Program Voltage Setup time
WP Program Voltage Hold time
VTRIP Level Setup time
µs
µs
tVPH
tTSU
µs
tTHD
VTRIP Level Hold (stable) time
VTRIP Program Cycle
µs
tWC
ms
ms
tVPO
VP
VTRAN
Vtv
Program Voltage Off time before next cycle
Programming Voltage
15
2.0
-25
10
18
V
V
VTRIP Set Voltage Range
4.75
+25
VTRIP Set Voltage variation after programming (-40 to +85°C).
WP Program Voltage Setup time
mV
µs
tVPS
REVISION HISTORY
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
FN8118.3
CHANGE
Updated Ordering Information Table on page 2.
December 9, 2015
Added Revision History and About Intersil sections.
ABOUT INTERSIL
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
© Copyright Intersil Americas LLC 2005-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8118 Rev 3.00
December 9, 2015
Page 21 of 24
X4043, X4045
PACKAGING INFORMATION
8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
0.050" Typical
X 45°
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
Typical
8 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
FN8118 Rev 3.00
December 9, 2015
Page 22 of 24
X4043, X4045
PACKAGING INFORMATION
8-Lead Miniature Small Outline Gull Wing Package Type M
0.118 ± 0.002
(3.00 ± 0.05)
0.012 + 0.006 / -0.002
(0.30 + 0.15 / -0.05)
0.0256 (0.65) Typ.
R 0.014 (0.36)
0.118 ± 0.002
(3.00 ± 0.05)
0.030 (0.76)
0.0216 (0.55)
7° Typ.
0.036 (0.91)
0.032 (0.81)
0.040 ± 0.002
(1.02 ± 0.05)
0.008 (0.20)
0.004 (0.10)
0.0256" Typical
0.025"
Typical
0.150 (3.81)
0.007 (0.18)
0.005 (0.13)
Ref.
0.193 (4.90)
Ref.
0.220"
0.020"
Typical
8 Places
FOOTPRINT
NOTE:
1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
FN8118 Rev 3.00
December 9, 2015
Page 23 of 24
X4043, X4045
PACKAGING INFORMATION
8-Lead Plastic Dual In-Line Package Type P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
Pin 1 Index
Pin 1
0.060 (1.52)
0.020 (0.51)
0.300
(7.62) Ref.
Half Shoulder Width On
All End Pins Optional
0.145 (3.68)
0.128 (3.25)
Seating
Plane
0.025 (0.64)
0.015 (0.38)
0.065 (1.65)
0.150 (3.81)
0.125 (3.18)
0.045 (1.14)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
.073 (1.84)
Max.
0°
Typ. 0.010 (0.25)
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
FN8118 Rev 3.00
December 9, 2015
Page 24 of 24
相关型号：
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