X28HC64PM-12 [RENESAS]
8KX8 EEPROM 5V, 120ns, PDIP28, PLASTIC, DIP-28;
| 型号： | X28HC64PM-12 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 8KX8 EEPROM 5V, 120ns, PDIP28, PLASTIC, DIP-28 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总16页 (文件大小：301K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X28HC64
®
64K, 8K x 8 Bit
Data Sheet
June 1, 2005
FN8109.0
• High reliability
—Endurance: 1 million cycles
—Data retention: 100 years
5 Volt, Byte Alterable EEPROM
FEATURES
• JEDEC approved byte-wide pin out
• 70ns access time
• Simple byte and page write
—Single 5V supply
—No external high voltages or V control circuits
—Self-timed
—No erase before write
—No complex programming algorithms
—No overerase problem
• Low power CMOS
DESCRIPTION
The X28HC64 is an 8K x 8 EEPROM, fabricated with
Intersil’s proprietary, high performance, floating gate
CMOS technology. Like all Intersil programmable non-
volatile memories, the X28HC64 is a 5V only device. It
features the JEDEC approved pinto for byte-wide mem-
ories, compatible with industry standard RAMs.
PP
—40mA active current max.
—200µA standby current max.
• Fast write cycle times
—64-byte page write operation
—Byte or page write cycle: 2ms typical
—Complete memory rewrite: 0.25 sec. typical
—Effective byte write cycle time: 32µs typical
• Software data protection
• End of write detection
The X28HC64 supports a 64-byte page write operation,
effectively providing a 32µs/byte write cycle, and
enabling the entire memory to be typically written in 0.25
seconds. The X28HC64 also features DATA Polling and
Toggle Bit Polling, two methods providing early end of
write detection. In addition, the X28HC64 includes a
user-optional software data protection mode that further
enhances Intersil’s hardware write protect capability.
—DATA polling
—Toggle bit
Intersil EEPROMs are designed and tested for appli-
cations requiring extended endurance. Inherent data
retention is greater than 100 years.
PIN CONFIGURATIONS
TSOP
LCC
PLCC
Plastic DIP
A
A
A
I/O
I/O
I/O
NC
SS
NC
I/O
I/O
I/O
A
A
A
A
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
Flat Pack
CERDIP
SOIC
3
4
5
6
7
2
1
0
0
1
2
1
28
27
26
25
24
23
VCC
NC
A12
A7
4
3
2
1
32 31 30
12
2
NC
NC
V
WE
NC
A8
V
A6
A5
A4
A3
A2
A1
A0
5
29
A8
A9
X28HC64
3
CC
6
7
28
27
NC
WE
NC
4
A6
3
4
5
6
7
A11
NC
OE
A10
22
21
5
A9
A5
8
9
26
25
A
A
9
A
I/O
I/O
20
19
18
17
8
6
A11
A4
X28HC64
(Top View)
7
X28HC64 22
A3
OE
A10
CE
11
10
11
24
23
A
OE
10
8
21
20
19
18
17
16
15
A2
CE
9
A1
CE
I/O7
I/O6
12
13
22
21
NC
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
A0
I/O0
PGA
14 15 16 17 18 19 20
I/O0
I/O1
I/O1
12
I/O2
13
I/O3
15
I/O5
I/O4
I/O6
18
17
I/O2
VSS
I/O0
11
A0
10
VSS
14
I/O7
19
16
A1
A3
A2
8
CE
20
A10
21
9
7
5
X28HC64
A4
6
OE
22
A11
23
(BOTTOM
VIEW)
A5
A6
A12
2
VCC
28
A9
24
A8
25
A7
3
WE
27
NC
26
NC
1
4
Bottom View
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X28HC64
PIN DESCRIPTIONS
Addresses (A -A )
PIN NAMES
Symbol
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
0
12
A0-A12
I/O0-I/O7
WE
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
CE
The Chip Enable input must be LOW to enable all
read/write operations. When CE is HIGH, power con-
sumption is reduced.
OE
VCC
VSS
Ground
Output Enable (OE)
NC
No Connect
The Output Enable input controls the data output buff-
ers and is used to initiate read operations.
Data In/Data Out (I/O -I/O )
0
7
Data is written to or read from the X28HC64 through
the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to
the X28HC64.
BLOCK DIAGRAM
65,536-Bit
X Buffers
Latches and
Decoder
EEPROM
Array
A0–A12
Address
Inputs
Y Buffers
Latches
and
I/O Buffers
and Latches
Decoder
CE
Control
Logic and
Timing
I/O0–I/O7
Data Inputs/Outputs
OE
WE
VCC
VSS
FN8109.0
June 1, 2005
2
X28HC64
DEVICE OPERATION
Read
Write Operation Status Bits
The X28HC64 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Read operations are initiated by both OE and CE
LOW. The read operation is terminated by either CE or
OE returning HIGH. This two line control architecture
eliminates bus contention in a system environment.
The data bus will be in a high impedance state when
either OE or CE is HIGH.
Figure 1. Status Bit Assignment
I/O DP TB
5
4
3
2
1
0
Write
Write operations are initiated when both CE and WE
are LOW and OE is HIGH. The X28HC64 supports
both a CE and WE controlled write cycle. That is, the
address is latched by the falling edge of either CE or
WE, whichever occurs last. Similarly, the data is
latched internally by the rising edge of either CE or
WE, whichever occurs first. A byte write operation,
once initiated, will automatically continue to comple-
tion, typically within 2ms.
Reserved
Toggle Bit
DATA Polling
DATA Polling (I/O )
7
The X28HC64 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a sim-
ple bit test operation to determine the status of the
X28HC64, eliminating additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will pro-
Page Write Operation
The page write feature of the X28HC64 allows the
entire memory to be written in 0.25 seconds. Page write
allows two to sixty-four bytes of data to be consecu-
tively written to the X28HC64 prior to the commence-
ment of the internal programming cycle. The host can
fetch data from another device within the system during
a page write operation (change the source address),
duce the complement of that data on I/O (i.e. write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
7
programming cycle is complete, I/O will reflect true data.
7
but the page address (A through A ) for each subse-
quent valid write cycle to the part during this operation
must be the same as the initial page address.
6
12
Toggle Bit (I/O )
6
The X28HC64 also provides another method for deter-
mining when the internal write cycle is complete. Dur-
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the
host can write an additional one to sixty-three bytes in
the same manner. Each successive byte load cycle,
started by the WE HIGH to LOW transition, must begin
within 100µs of the falling edge of the preceding WE. If
a subsequent WE HIGH to LOW transition is not
detected within 100µs, the internal automatic program-
ming cycle will commence. There is no page write win-
dow limitation. Effectively the page write window is
infinitely wide, so long as the host continues to access
the device within the byte load cycle time of 100µs.
ing the internal programming cycle I/O will toggle
6
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
FN8109.0
3
June 1, 2005
X28HC64
DATA POLLING I/O
7
Figure 2. DATA Polling Bus Sequence
Last
Write
WE
CE
OE
VIH
VOH
HIGH Z
I/O7
VOL
X28HC64
Ready
A0–A12
An
An
An
An
An
An
An
Figure 3. DATA Polling Software Flow
DATA Polling can effectively reduce the time for writ-
ing to the X28HC64. The timing diagram in Figure 2
illustrates the sequence of events on the bus. The
software flow diagram in Figure 3 illustrates one
method of implementing the routine.
Write Data
No
Writes
Complete?
Yes
Save Last Data
and Address
Read Last
Address
IO7
No
Compare?
Yes
Ready
FN8109.0
4
June 1, 2005
X28HC64
THE TOGGLE BIT I/O
6
Figure 4. Toggle Bit Bus Sequence
Last
Write
WE
CE
OE
VOH
HIGH Z
I/O6
*
*
VOL
X28HC64
Ready
* Beginning and ending state of I/O6 will vary.
Figure 5. Toggle Bit Software Flow
The Toggle Bit can eliminate the chore of saving and
fetching the last address and data in order to implement
DATA Polling. This can be especially helpful in an array
comprised of multiple X28HC64 memories that is fre-
quently updated. Toggle Bit Polling can also provide a
method for status checking in multiprocessor applica-
tions. The timing diagram in Figure 4 illustrates the
sequence of events on the bus. The software flow dia-
gram in Figure 5 illustrates a method for polling the
Toggle Bit.
Last Write
Yes
Load Accum
From Addr N
Compare
Accum with
Addr N
No
Compare
Ok?
Yes
Ready
FN8109.0
5
June 1, 2005
X28HC64
HARDWARE DATA PROTECTION
The X28HC64 can be automatically protected during
power-up and power-down without the need for exter-
nal circuits by employing the software data protection
feature. The internal software data protection circuit is
enabled after the first write operation utilizing the soft-
ware algorithm. This circuit is nonvolatile and will
remain set for the life of the device, unless the reset
command is issued.
The X28HC64 provides two hardware features that
protect nonvolatile data from inadvertent writes.
– Default V Sense—All write functions are inhibited
CC
when V is 3V typically.
CC
– Write Inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle dur-
ing power-up and power-down, maintaining data
integrity.
Once the software protection is enabled, the X28HC64
is also protected from inadvertent and accidental
writes in the powered-up state. That is, the software
algorithm must be issued prior to writing additional
data to the device.
SOFTWARE DATA PROTECTION
The X28HC64 offers a software controlled data pro-
tection feature. The X28HC64 is shipped from Intersil
with the software data protection NOT ENABLED; that
is, the device will be in the standard operating mode.
In this mode data should be protected during power-
up/-down operations through the use of external cir-
cuits. The host would then have open read and write
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific
addresses. Refer to Figure 6 and 7 for the sequence.
The three-byte sequence opens the page write window,
enabling the host to write from one to sixty-four bytes
of data. Once the page load cycle has been com-
pleted, the device will automatically be returned to the
data protected state.
access of the device once V was stable.
CC
FN8109.0
6
June 1, 2005
X28HC64
SOFTWARE DATA PROTECTION
Figure 6. Timing Sequence—Byte or Page Write
VCC
0V
(VCC
)
Data
ADDR
AAA
1555
55
0AAA
A0
1555
Writes
OK
Write
Protected
tWC
CE
Byte
or
Page
≤tBLC MAX
WE
Figure 7. Write Sequence for Software
Data Protection
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used, the X28HC64 will automatically dis-
able further writes unless another command is issued
to deactivate it. If no further commands are issued the
X28HC64 will be write protected during power-down
and after any subsequent power-up.
Write Data AA
to Address
1555
Write Data 55
to Address
0AAA
Note: Once initiated, the sequence of write operations
should not be interrupted.
Write Data A0
to Address
1555
Byte/Page
Load Enabled
Write Data XX
to Any
Address
Optional
Byte/Page
Load Operation
Write Last
Byte to
Last Address
After tWC
Re-Enters Data
Protected State
FN8109.0
7
June 1, 2005
X28HC64
RESETTING SOFTWARE DATA PROTECTION
Figure 8. Reset Software Data Protection Timing Sequence
VCC
AAA
1555
55
0AAA
80
1555
AA
1555
55
0AAA
20
1555
Standard
Operating
Mode
Data
ADDR
≥tWC
CE
WE
Figure 9. Software Sequence to Deactivate Software
Data Protection
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an EEPROM programmer, the following six step algo-
Write Data AA
to Address
1555
rithm will reset the internal protection circuit. After t
the X28HC64 will be in standard operating mode.
,
WC
Note: Once initiated, the sequence of write operations
should not be interrupted.
Write Data 55
to Address
0AAA
Write Data 80
to Address
1555
Write Data AA
Address
1555
Write Data 55
to Address
0AAA
Write Data 20
to Address
1555
FN8109.0
8
June 1, 2005
X28HC64
SYSTEM CONSIDERATIONS
Because the X28HC64 has two power modes,
standby and active, proper decoupling of the memory
array is of prime concern. Enabling CE will cause tran-
sient current spikes. The magnitude of these spikes is
dependent on the output capacitive loading of the
I/Os. Therefore, the larger the array sharing a common
bus, the larger the transient spikes. The voltage peaks
associated with the current transients can be sup-
pressed by the proper selection and placement of
decoupling capacitors. As a minimum, it is recom-
mended that a 0.1µF high frequency ceramic capacitor
Because the X28HC64 is frequently used in large
memory arrays, it is provided with a two-line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipa-
tion, and eliminate the possibility of contention where
multiple I/O pins share the same bus.
To gain the most benefit, it is recommended that CE
be decoded from the address bus, and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation, this assures that all deselected
devices are in their standby mode, and that only the
selected device(s) is/are outputting data on the bus.
be used between V
and V
at each device.
CC
SS
Depending on the size of the array, the value of the
capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between V
and V
for
CC
SS
each eight devices employed in the array. This bulk
capacitor is employed to overcome the voltage droop
caused by the inductive effects of the PC board traces.
Normalized I (RD) by Temperature
Normalized I (RD) @ 25% Over
CC
CC
Over Frequency
the V Range and Frequency
CC
1.4
1.2
1.0
0.8
0.6
0.4
0.2
1.4
1.2
1.0
0.8
0.6
0.4
0.2
5.5 VCC
- 55°C
5.5 V
5.0 V
CC
CC
+ 25°C
+ 125°C
4.5 V
CC
0
10
20
0
10
20
Frequency (MHz)
Frequency (MHz)
FN8109.0
June 1, 2005
9
X28HC64
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those indi-
cated in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
X28HC64 ......................................... -10°C to +85°C
X28HC64I, X28HC64M.................. -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on any pin with
respect to V ......................................... -1V to +7V
SS
D.C. output current...............................................5mA
Lead temperature
(soldering, 10 seconds).................................. 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
+125°C
Supply Voltage
Limits
X28HC64
5V ±10%
-40°C
-55°C
Military
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
(1)
Symbol
Parameter
Min. Typ.
Max.
Unit
Test Conditions
ICC
VCC current (active)
(TTL inputs)
15
40
mA CE = OE = VIL, WE = VIH, All I/O’s = open,
address inputs = TTL levels @ f = 10 MHz
ISB1
ISB2
VCC current (standby)
(TTL inputs)
1
2
mA CE = VIH, OE = VIL All I/O’s = open,
other inputs = VIH
VCC current (standby)
(CMOS inputs)
100
200
µA
CE = VCC - 0.3V, OE = GND, All I/O’s = open,
other inputs = VCC - 0.3V
ILI
Input leakage current
Output leakage current
Input LOW voltage
±10
±10
µA
µA
V
VIN = VSS to VCC
ILO
VOUT = VSS to VCC, CE = VIH
(2)
VlL
-1
2
0.8
(2)
VIH
Input HIGH voltage
Output LOW voltage
Output HIGH voltage
VCC + 1
0.4
V
VOL
VOH
V
IOL = 5mA
2.4
V
IOH = -5mA
Notes: (1) Typical values are for TA = 25°C and nominal supply voltage
(2) VIL min. and VIH max. are for reference only and are not tested.
FN8109.0
June 1, 2005
10
X28HC64
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Max.
Unit
Cycles
Years
POWER-UP TIMING
(1)
Symbol
Parameter
Typ.
Unit
(3)
tPUR
Power-up to read operation
Power-up to write operation
100
5
µs
(3)
tPUW
ms
CAPACITANCE T = +25°C, f = 1MHz, V = 5V
A
CC
Symbol
Parameter
Max.
10
Unit
Test Conditions
VI/O = 0V
(3)
CI/O
Input/output capacitance
Input capacitance
pF
pF
(3)
CIN
6
VIN = 0V
A.C. CONDITIONS OF TEST
MODE SELECTION
CE OE WE
Input pulse levels
0V to 3V
5ns
Mode
Read
Write
I/O
DOUT
DIN
Power
Input rise and fall times
Input and output timing levels
L
L
L
H
X
H
L
Active
Active
1.5V
H
X
Standby and
write inhibit
High Z
Standby
X
X
L
X
H
Write inhibit
Write inhibit
—
—
—
—
X
Note: (3) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUITS
SYMBOL TABLE
5V
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
1.92kΩ
Output
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
1.37kΩ
30pF
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
FN8109.0
11
June 1, 2005
X28HC64
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Read Cycle Limits
X28HC64-70
X28HC64-90
X28HC64-12
-55°C to +125°C -55°C to +125°C -55°C to +125°C
Symbol
tRC
Parameter
Read cycle time
Min.
Max.
Min.
Max.
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
90
120
tCE
Chip enable access time
Address access time
70
70
35
90
90
40
120
120
50
tAA
tOE
Output enable access time
CE LOW to active output
OE LOW to active output
CE HIGH to high Z output
OE HIGH to high Z output
Output hold from address change
(4)
tLZ
0
0
0
0
0
0
(4)
tOLZ
(4)
tHZ
30
30
30
30
30
30
(4)
tOHZ
tOH
0
0
0
Read Cycle
tRC
Address
CE
tCE
tOE
OE
VIH
WE
tOLZ
tOHZ
tLZ
tOH
tHZ
HIGH Z
Data I/O
Data Valid
Data Valid
tAA
Note: (4) tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured from the point
when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
FN8109.0
12
June 1, 2005
X28HC64
WRITE CYCLE LIMITS
(1)
Symbol
Parameter
Min.
Typ.
Max.
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
µs
(5)
tWC
Write cycle time
Address setup time
2
5
tAS
tAH
tCS
0
50
0
Address hold time
Write setup time
Write hold time
CE pulse width
OE High setup time
OE High hold time
WE pulse width
WE HIGH recovery
Data valid
tCH
0
tCW
tOES
tOEH
tWP
50
0
0
50
50
(6)
tWPH
(6)
tDV
tDS
tDH
1
Data setup
50
0
Data hold
(6)
tDW
tBLC
Delay to next write
Byte load cycle
10
0.15
100
WE Controlled Write Cycle
tWC
Address
tAS
tAH
tCS
tCH
CE
OE
tOES
tOEH
tWP
WE
tDV
Data In
Data Out
Data Valid
tDS
tDH
HIGH Z
Notes: (5) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time
the device requires to automatically complete the internal write operation.
(6) tWPH and tDW are periodically sampled and not 100% tested.
FN8109.0
13
June 1, 2005
X28HC64
CE CONTROLLED WRITE CYCLE
tWC
Address
tAS
tAH
tCW
CE
tOES
OE
tOEH
tCS
tCH
WE
tDV
Data Valid
Data In
tDS
HIGH Z
tDH
Data Out
Page Write Cycle
OE(7)
CE
tWP
tBLC
WE
tWPH
Address*(8)
I/O
Last Byte
Byte n+2
Byte 0
Byte 1
Byte 2
Byte n
Byte n+1
tWC
*For each successive write within the page write operation, A6–A12 should be the same or
writes to an unknown address could occur.
Notes: (7) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH
to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a
polling operation.
(8) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to
either the CE or WE controlled write cycle timing.
FN8109.0
14
June 1, 2005
X28HC64
(9)
DATA Polling Timing Diagram
Address
CE
An
An
An
WE
tOEH
tOES
OE
tDW
DOUT = X
DIN = X
I/O7
DOUT = X
tWC
(9)
Toggle Bit Timing Diagram
CE
WE
tOES
tOEH
OE
tDW
HIGH Z
I/O*6
*
*
tWC
* I/O6 beginning and ending state will vary, depending upon actual tWC
.
Note: (9) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
FN8109.0
15
June 1, 2005
X28HC64
Ordering Information
Device
X28HC64
X
X
-X
Access Time
-70 = 70ns
-90 = 90ns
-12 = 120ns
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
M = Military = -55°C to +125°C
MB = MIL-STD-883
Package
P = 28-Lead Plastic DIP
D = 28-Lead Cerdip
J = 32-Lead PLCC
S = 28-Lead Plastic SOIC
E = 32-Pad LCC
K = 28-Lead Pin Grid Array
F = 28-Lead Flat Pack
T = 32-Lead TSOP
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8109.0
16
June 1, 2005
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