X28HC64JZ-70-T1 [RENESAS]
EEPROM, 8KX8, 70ns, Parallel, CMOS, PQCC32;
| 型号： | X28HC64JZ-70-T1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | EEPROM, 8KX8, 70ns, Parallel, CMOS, PQCC32 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总18页 (文件大小：436K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
64k, 8k x 8-Bit 5 Volt, Byte Alterable EEPROM
X28HC64
Features
The X28HC64 is an 8k x 8 EEPROM, fabricated with Intersil’s
proprietary, high performance, floating gate CMOS technology.
Like all Intersil programmable nonvolatile memories, the
X28HC64 is a 5V only device. It features the JEDEC approved
pinout for byte-wide memories, compatible with industry
standard RAMs.
• 70ns access time
• Simple byte and page write
- Single 5V supply
- No external high voltages or VP-P control circuits
- Self-timed
- No erase before write
The X28HC64 supports a 64-byte page write operation, effectively
providing a 32µs/byte write cycle, and enabling the entire
memory to be typically written in 0.25 seconds. The X28HC64
also features DATA Polling and Toggle Bit Polling, two methods
providing early end of write detection. In addition, the X28HC64
includes a user-optional software data protection mode that
further enhances Intersil’s hardware write protect capability.
- No complex programming algorithms
- No overerase problem
• Low power CMOS
- 40mA active current maximum
• 200µA standby current maximum
• Fast write cycle times
Intersil EEPROMs are designed and tested for applications
requiring extended endurance. Inherent data retention is
greater than 100 years.
- 64-byte page write operation
- Byte or page write cycle: 2ms typical
- Complete memory rewrite: 0.25s typical
- Effective byte write cycle time: 32µs typical
• Software data protection
• End of write detection
- DATA polling
- Toggle bit
• High reliability
- Endurance: 100,000 cycles
- Data retention: 100 years
• JEDEC approved byte-wide pinout
• Pb-free available (RoHS compliant)
Pin Configurations
X28HC64
(28 LD PDIP, SOIC)
TOP VIEW
X28HC64
(32 LD PLCC)
TOP VIEW
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
NC
WE
NC
A
12
4
3
2
1 32 31 30
29
A
A
A
A
A
A
A
A
7
6
5
4
3
2
1
0
A
A
A
A
A
A
A
5
6
7
8
9
A
8
6
5
4
3
2
1
0
A
8
28
27
26
25
24
23
22
21
A
9
A
9
A
11
A
11
NC
OE
OE
X28HC64
X28HC64
A
10
A
10
11
12
13
10
CE
I/O
CE
I/O
10
11
12
13
14
7
NC
I/O
7
I/O
I/O
I/O
I/O
I/O
I/O
6
5
4
3
0
1
2
I/O
0
6
14 15 16 17 18 19 20
I/O
V
SS
June 27, 2016
FN8109.4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2005, 2006, 2009, 2015, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
X28HC64
Ordering Information
TEMPERATURE
RANGE (°C)
ACCESS TIME
(ns)
PKG.
DWG. #
PART NUMBER
PART MARKING
PACKAGE
32 Ld PLCC
X28HC64J-70 (Notes 1, 6)
X28HC64J-70 CY
0 to +70
70
N32.45x55
(No longer available, recommended
replacement: X28HC64JZ-70)
X28HC64JIZ-70 (Notes 1, 4, 6)
X28HC64JZ-70 (Notes 1, 4, 6)
X28HC64SIZ-70 (Notes 4, 6)
X28HC64JI-70 ZCY
X28HC64J-70 ZCY
X28HC64SI-70 CYZ
-40 to +85
0 to +70
32 Ld PLCC (RoHS Compliant)
32 Ld PLCC (RoHS Compliant)
N32.45x55
N32.45x55
M28.3
-40 to +85
28 Ld SOIC (300 mil) (RoHS
Compliant)
X28HC64SZ-70 (Notes 4, 6)
X28HC64S-70 CYZ
X28HC64J-90 CY
0 to +70
0 to +70
28 Ld SOIC (300 mil) (RoHS
Compliant)
M28.3
X28HC64J-90 (Notes 1, 6)
90
32 Ld PLCC
N32.45x55
(No longer available, recommended
replacement: X28HC64JIZ-90)
X28HC64JI-90 (Notes 1, 3, 6)
(No longer available, recommended
replacement: X28HC64JIZ-90)
X28HC64JI-90 CY
-40 to +85
32 Ld PLCC
N32.45x55
X28HC64JIZ-90 (Notes 1, 4, 6)
X28HC64PIZ-90 (Notes 4, 5)
X28HC64PZ-90 (Notes 4, 5)
X28HC64JI-90 ZCY
X28HC64PI-90 CYZ
X28HC64P-90 CYZ
X28HC64J-12 CY
-40 to +85
-40 to +85
0 to +70
32 Ld PLCC (RoHS Compliant)
28 Ld PDIP (RoHS Compliant)
28 Ld PDIP (RoHS Compliant)
32 Ld PLCC
N32.45x55
E28.6
E28.6
X28HC64J-12 (Notes 1, 6)
0 to +70
120
N32.45x55
(No longer available, recommended
replacement: X28HC64JZ-12)
X28HC64JI-12 (Notes 1, 6)
X28HC64JI-12 CY
-40 to +85
32 Ld PLCC
N32.45x55
(No longer available, recommended
replacement: X28HC64JIZ-12)
X28HC64JIZ-12 (Notes 1, 4, 6)
X28HC64JZ-12* (Notes 1, 4, 6)
X28HC64PIZ-12 (Notes 4, 5)
X28HC64PZ-12 (Notes 4, 5)
X28HC64SIZ-12 (Notes 2, 4, 6)
X28HC64JI-12 ZCY
X28HC64J-12 ZCY
X28HC64PI-12 CYZ
X28HC64P-12 CYZ
X28HC64SI-12 CYZ
-40 to +85
0 to +70
32 Ld PLCC (RoHS Compliant)
32 Ld PLCC (RoHS Compliant)
28 Ld PDIP (RoHS Compliant)
28 Ld PDIP (RoHS Compliant)
N32.45x55
N32.45x55
E28.6
-40 to +85
0 to +70
E28.6
-40 to +85
28 Ld SOIC (300 mil) (RoHS
Compliant)
M28.3
X28HC64SZ-12 (Notes 4, 6)
NOTES:
X28HC64S-12 CYZ
0 to +70
28 Ld SOIC (300 mil) (RoHS
Compliant)
M28.3
1. Add “T1” suffix for 750 unit tape and reel option.
2. Add “T1” suffix for 1000 unit tape and reel option.
3. Add “T2” suffix for 750 unit tape and reel option.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
6. For Moisture Sensitivity Level (MSL), please see product information page for X28HC64. For more information on MSL, please see tech brief TB363.
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X28HC64
Write
Pin Descriptions
Write operations are initiated when both CE and WE are LOW and
SYMBOL
DESCRIPTION
OE is HIGH. The X28HC64 supports both a CE and WE controlled
write cycle. That is, the address is latched by the falling edge of
either CE or WE, whichever occurs last. Similarly, the data is
latched internally by the rising edge of either CE or WE, whichever
occurs first. A byte write operation, once initiated, will
A0-A12
Address Inputs. The Address inputs
select an 8-bit memory location
during a read or write operation.
I/O0-I/O7
WE
Data Input/Output. Data is written
to or read from the X28HC64
through the I/O pins.
automatically continue to completion, typically within 2ms.
Page Write Operation
Write Enable. The Write Enable
input controls the writing of data to
the X28HC64.
The page write feature of the X28HC64 allows the entire memory
to be written in 0.25 seconds. Page write allows two to sixty-four
bytes of data to be consecutively written to the X28HC64 prior to
the commencement of the internal programming cycle. The host
can fetch data from another device within the system during a
page write operation (change the source address), but the page
address (A6 through A12) for each subsequent valid write cycle to
the part during this operation must be the same as the initial page
address.
CE
Chip Enable. The Chip Enable input
must be LOW to enable all
read/write operations. When CE is
HIGH, power consumption is
reduced.
OE
Output Enable. The Output Enable
input controls the data output
buffers and is used to initiate read
operations.
The page write mode can be initiated during any write operation.
Following the initial byte write cycle, the host can write an
additional one to sixty-three bytes in the same manner. Each
successive byte load cycle, started by the WE HIGH to LOW
transition, must begin within 100µs of the falling edge of the
preceding WE. If a subsequent WE HIGH to LOW transition is not
detected within 100µs, the internal automatic programming
cycle will commence. There is no page write window limitation.
Effectively the page write window is infinitely wide, so long as the
host continues to access the device within the byte load cycle
time of 100µs.
VCC
VSS
NC
+5V
Ground
No Connect
Block Diagram
65,536-BIT
X BUFFERS
LATCHES AND
DECODER
EEPROM
ARRAY
Write Operation Status Bits
The X28HC64 provides the user two write operation status bits.
These can be used to optimize a system write cycle time. The
status bits are mapped onto the I/O bus as shown in Figure 2.
A –A
0
12
ADDRESS
INPUTS
Y BUFFERS
LATCHES
AND
I/O BUFFERS
AND LATCHES
I/O
DP
TB
5
4
3
2
1
0
DECODER
RESERVED
TOGGLE BIT
DATA POLLING
CE
CONTROL
LOGIC AND
TIMING
I/O –I/O
DATA INPUTS/OUTPUTS
0
7
OE
FIGURE 2. STATUS BIT ASSIGNMENT
WE
V
CC
SS
V
FIGURE 1. BLOCK DIAGRAM
Device Operation
Read
Read operations are initiated by both OE and CE LOW. The read
operation is terminated by either CE or OE returning HIGH. This
two line control architecture eliminates bus contention in a
system environment. The data bus will be in a high impedance
state when either OE or CE is HIGH.
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X28HC64
produce the complement of that data on I/O7 (i.e., write data =
0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is
complete, I/O7 will reflect true data.
DATA Polling (I/O )
7
The X28HC64 features DATA Polling as a method to indicate to
the host system that the byte write or page write cycle has
completed. DATA Polling allows a simple bit test operation to
determine the status of the X28HC64, eliminating additional
interrupt inputs or external hardware. During the internal
programming cycle, any attempt to read the last byte written will
DATA Polling can effectively reduce the time for writing to the
X28HC64. The timing diagram in Figure 3 illustrates the
sequence of events on the bus. The software flow diagram in
Figure 4 illustrates one method of implementing the routine.
LAST
WRITE
WE
CE
OE
V
IH
V
OH
HIGH Z
I/O
7
V
OL
X28HC64
READY
A –A
0
12
An
An
An
An
An
An
An
FIGURE 3. DATA POLLING BUS SEQUENCE
WRITE DATA
NO
WRITES
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO
NO
7
COMPARE?
YES
READY
FIGURE 4. DATA POLLING SOFTWARE FLOW
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X28HC64
The Toggle Bit can eliminate the chore of saving and fetching the
Toggle Bit (I/O )
6
last address and data in order to implement DATA Polling. This
can be especially helpful in an array comprised of multiple
X28HC64 memories that is frequently updated. Toggle Bit Polling
can also provide a method for status checking in multiprocessor
applications. The timing diagram in Figure 5 illustrates the
sequence of events on the bus. The software flow diagram in
Figure 6 illustrates a method for polling the Toggle Bit.
The X28HC64 also provides another method for determining
when the internal write cycle is complete. During the internal
programming cycle I/O6 will toggle from HIGH to LOW and LOW
to HIGH on subsequent attempts to read the device. When the
internal cycle is complete, the toggling will cease and the device
will be accessible for additional read or write operations.
LAST
WRITE
WE
CE
OE
V
OH
HIGH Z
I/O
6
*
*
V
OL
X28HC64
READY
* BEGINNING AND ENDING STATE OF I/O WILL VARY.
6
FIGURE 5. TOGGLE BIT BUS SEQUENCE
LAST WRITE
YES
LOAD ACCUM
FROM ADDR N
COMPARE
ACCUM WITH
ADDR N
NO
COMPARE
OK?
YES
READY
FIGURE 6. TOGGLE BIT SOFTWARE FLOW
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X28HC64
nonvolatile and will remain set for the life of the device, unless
the reset command is issued.
Hardware Data Protection
The X28HC64 provides two hardware features that protect
nonvolatile data from inadvertent writes.
Once the software protection is enabled, the X28HC64 is also
protected from inadvertent and accidental writes in the
powered-up state. That is, the software algorithm must be issued
prior to writing additional data to the device.
• Default VCC Sense—All write functions are inhibited when VCC is
3V typically.
• Write Inhibit—Holding either OE LOW, WE HIGH, or CE HIGH will
prevent an inadvertent write cycle during power-up and
power-down, maintaining data integrity.
Software Algorithm
Selecting the software data protection mode requires the host
system to precede data write operations by a series of three write
operations to three specific addresses. Refer to Figures 7 and 8
for the sequence. The 3-byte sequence opens the page write
window, enabling the host to write from 1 to 64 bytes of data.
Once the page load cycle has been completed, the device will
automatically be returned to the data protected state.
Software Data Protection
The X28HC64 offers a software controlled data protection feature.
The X28HC64 is shipped from Intersil with the software data
protection NOT ENABLED; that is, the device will be in the standard
operating mode. In this mode data should be protected during
power-up/power-down operations through the use of external
circuits. The host would then have open read and write access of the
device once VCC was stable.
Regardless of whether the device has previously been protected
or not, once the software data protection algorithm is used, the
X28HC64 will automatically disable further writes unless another
command is issued to deactivate it. If no further commands are
issued, the X28HC64 will be write protected during power-down
and after any subsequent power-up.
The X28HC64 can be automatically protected during power-up
and power-down without the need for external circuits by
employing the software data protection feature. The internal
software data protection circuit is enabled after the first write
operation utilizing the software algorithm. This circuit is
Note: Once initiated, the sequence of write operations should not
be interrupted.
V
CC
(V
)
CC
0V
DATA
ADDR
AAA
1555
55
0AAA
A0
1555
WRITES
OK
WRITE
PROTECTED
t
WC
CE
BYTE
OR
PAGE
≤t
BLC MAX
WE
FIGURE 7. TIMING SEQUENCE—BYTE OR PAGE WRITE
WRITE DATA AA
TO ADDRESS
1555
WRITE DATA 55
TO ADDRESS
0AAA
WRITE DATA A0
TO ADDRESS
1555
BYTE/PAGE
LOAD ENABLED
WRITE DATA XX
TO ANY
ADDRESS
OPTIONAL
BYTE/PAGE
LOAD OPERATION
WRITE LAST
BYTE TO
LAST ADDRESS
AFTER T
WC
RE-ENTERS DATA
PROTECTED STATE
FIGURE 8. WRITE SEQUENCE FOR SOFTWARE DATA PROTECTION
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X28HC64
Resetting Software Data Protection
V
CC
AAA
1555
55
0AAA
80
1555
AA
1555
55
0AAA
20
1555
STANDARD
OPERATING
MODE
DATA
ADDR
t
WC
CE
WE
FIGURE 9. RESET SOFTWARE DATA PROTECTION TIMING SEQUENCE
WRITE DATA AA
TO ADDRESS
1555
WRITE DATA 55
TO ADDRESS
0AAA
WRITE DATA 80
TO ADDRESS
1555
WRITE DATA AA
ADDRESS
1555
WRITE DATA 55
TO ADDRESS
0AAA
WRITE DATA 20
TO ADDRESS
1555
FIGURE 10. SOFTWARE SEQUENCE TO DEACTIVATE SOFTWARE DATA PROTECTION
In the event the user wants to deactivate the software data
protection feature for testing or reprogramming in an EEPROM
programmer, the following six step algorithm will reset the
internal protection circuit. After tWC, the X28HC64 will be in
standard operating mode.
Note: Once initiated, the sequence of write operations should not
be interrupted.
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X28HC64
concern. Enabling CE will cause transient current spikes. The
System Considerations
magnitude of these spikes is dependent on the output capacitive
loading of the I/Os. Therefore, the larger the array sharing a
common bus, the larger the transient spikes. The voltage peaks
associated with the current transients can be suppressed by the
proper selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1µF high frequency
ceramic capacitor be used between VCC and VSS at each device.
Depending on the size of the array, the value of the capacitor
may have to be larger.
Because the X28HC64 is frequently used in large memory arrays,
it is provided with a two-line control architecture for both read
and write operations. Proper usage can provide the lowest
possible power dissipation, and eliminate the possibility of
contention where multiple I/O pins share the same bus.
To gain the most benefit, it is recommended that CE be decoded
from the address bus, and be used as the primary device
selection input. Both OE and WE would then be common among
all devices in the array. For a read operation, this assures that all
deselected devices are in their standby mode, and that only the
selected device(s) is/are outputting data on the bus.
In addition, it is recommended that a 4.7µF electrolytic bulk
capacitor be placed between VCC and VSS for each eight devices
employed in the array. This bulk capacitor is employed to
overcome the voltage droop caused by the inductive effects of
the PC board traces.
Because the X28HC64 has two power modes, standby and
active, proper decoupling of the memory array is of prime
1.4
1.4
5.5V
CC
5.5V
CC
1.2
1.0
0.8
0.6
0.4
0.2
1.2
1.0
0.8
0.6
0.4
0.2
- 55°C
+ 25°C
5.0V
CC
+ 125°C
4.5V
CC
0M
10M
FREQUENCY (Hz)
20M
0M
10M
FREQUENCY (Hz)
20M
FIGURE 12. NORMALIZED ICC(RD) AT 25% OVER THE VCC RANGE
AND FREQUENCY
FIGURE 11. NORMALIZED ICC(RD) BY TEMPERATURE
OVER FREQUENCY DATA PROTECTION
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X28HC64
Absolute Maximum Ratings
Thermal Information
Temperature Under Bias
Thermal Resistance (Typical)
JA (°C/W)
JC (°C/W)
X28HC64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +85°C
X28HC64I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on any Pin with Respect to VSS . . . . . . . . . . . . . . . . . . . . .-1V to +7V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
32 Ld PLCC Package (Notes 7, 9) . . . . . . .
28 Ld SOIC Package (Notes 7, 9) . . . . . . . .
28 Ld PDIP Package (Notes 8, 9). . . . . . . .
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
*Pb-free PDIPs can be used for through hole wave solder processing only.
They are not intended for use in Reflow solder processing applications.
41
46
53
19
19
21
Recommended Operating Conditions
Commercial Temperature Range . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage Range
X28HC64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
7. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
8. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
9. For JC, the “case temp” location is taken at the package top center.
DC Electrical Specifications Over recommended operating conditions, unless otherwise specified.
MIN
TYP
MAX
PARAMETER
SYMBOL
ICC
TEST CONDITIONS
(Note 10) (Note 11) (Note 10) UNIT
V
CC Current (Active) (TTL Inputs)
CE = OE = VIL, WE = VIH, All I/O’s = open, address
inputs = TTL levels at f = 10MHz
15
40
mA
VCC Current (Standby) (TTL Inputs)
CC Current (Standby) (CMOS Inputs)
ISB1
ISB2
CE = VIH, OE = VIL All I/O’s = open, other inputs = VIH
1
2
mA
µA
V
CE = VCC - 0.3V, OE = GND, All I/O’s = open, other
inputs = VCC - 0.3V
100
200
Input Leakage Current
Output Leakage Current
Input LOW Voltage (Note 12)
Input HIGH Voltage (Note 12)
Output LOW Voltage
Output HIGH Voltage
NOTES:
ILI
ILO
VIN = VSS to VCC
±10
±10
µA
µA
V
VOUT = VSS to VCC, CE = VIH
VlL
-1
2
0.8
VIH
VOL
VOH
VCC + 1
0.4
V
IOL = 5mA
IOH = -5mA
V
2.4
V
10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
11. Typical values are for TA = +25°C and nominal supply voltage.
12. VIL minimum and VIH maximum are for reference only and are not tested.
Endurance and Data Retention The endurance and data retention specifications are established by characterization and are not
production tested.
PARAMETER
Minimum Endurance
MIN
100,000
100
MAX
UNIT
Cycles
Years
Data Retention
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X28HC64
Power-Up Timing
TYP
PARAMETER
SYMBOL
tPUR
(Note 11)
UNIT
µs
Power-Up to Read Operation (Note 13)
Power-Up to Write Operation (Note 13)
100
5
tPUW
ms
Capacitance TA = +25°C, f = 1MHz, VCC = 5V
PARAMETER
Input/output Capacitance (Note 13)
Input Capacitance (Note 13)
NOTE:
SYMBOL
TEST CONDITIONS
VI/O = 0V
MAX
10
6
UNIT
pF
CI/O
CIN
VIN = 0V
pF
13. This parameter is periodically sampled and not 100% tested.
Symbol Table
TABLE 1. AC CONDITIONS OF TEST
WAVEFORM
INPUTS
OUTPUTS
Input Pulse Levels
0V to 3V
5ns
Input Rise and Fall Times
Input and Output Timing Levels
Must be
steady
Will be
steady
1.5V
Ma y change
from LOW
to HIGH
Will change
from LOW
to HIGH
TABLE 2. MODE SELECTION
MODE I/O
Ma y change
from HIGH
to LOW
Will change
from HIGH
to LOW
CE
L
OE
L
WE
H
POWER
Active
Read
Write
DOUT
DIN
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
L
H
L
Active
H
X
X
Standby and write High Z
inhibit
Standby
N/A
Center Line
is High
Impedance
-
X
X
L
X
Write inhibit
-
-
X
H
Write inhibit
-
Equivalent AC Load Circuits
5V
1.92kΩ
OUTPUT
1.37kΩ
30pF
FIGURE 13. EQUIVALENT AC LOAD CIRCUITS
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X28HC64
AC Electrical Specifications
Read Cycle Limits Over the recommended operating conditions unless otherwise specified.
X28HC64-70 X28HC64-90
MIN MAX MIN MAX
X28HC64-12
MIN MAX
PARAMETER
SYMBOL
(Note 10) (Note 10) (Note 10) (Note 10) (Note 10) (Note 10)
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
tRC
70
90
120
Chip Enable Access Time
Address Access Time
tCE
70
70
35
90
90
40
120
120
50
tAA
Output Enable Access Time
CE LOW to Active Output (Note 14)
OE LOW to Active Output (Note 14)
CE HIGH to High Z Output (Note 14)
OE HIGH to High Z Output (Note 14)
Output Hold from Address Change
NOTE:
tOE
tLZ
0
0
0
0
0
0
tOLZ
tHZ
tOHZ
tOH
30
30
30
30
30
30
0
0
0
14. tLZ minimum, tHZ, tOLZ minimum, and tOHZ are periodically sampled and not 100% tested. tHZ maximum and tOHZ maximum are measured from the
point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
Read Cycle
t
RC
ADDRESS
t
CE
CE
t
OE
OE
V
IH
WE
t
t
OHZ
OLZ
t
t
t
t
LZ
OH
AA
HZ
HIGH Z
DATA I/O
DATA VALID
DATA VALID
FIGURE 14. READ CYCLE
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X28HC64
Write Cycle Limits
MIN
TYP
MAX
PARAMETER
SYMBOL
tWC
tAS
(Note 10)
(Note 11)
(Note 10)
UNIT
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
µs
Write Cycle Time (Note 15)
Address Set-Up Time
Address Hold Time
Write Set-Up Time
Write Hold Time
2
5
0
50
0
tAH
tCS
tCH
0
CE Pulse Width
tCW
tOES
tOEH
tWP
tWPH
tDV
50
0
OE High Set-Up Time
OE High Hold Time
WE Pulse Width
0
50
50
WE HIGH Recovery (Note 16)
Data Valid (Note 16)
Data Setup
1
tDS
50
0
Data Hold
tDH
Delay to Next Write (Note 16)
Byte Load Cycle
tDW
tBLC
10
0.15
100
NOTES:
15. tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device
requires to automatically complete the internal write operation.
16. tWPH and tDW are periodically sampled and not 100% tested.
WE Controlled Write Cycle
t
WC
ADDRESS
t
t
AH
AS
t
t
CS
CH
CE
OE
t
t
OEH
OES
t
WP
WE
t
DV
DATA IN
DATA OUT
DATA VALID
HIGH Z
t
t
DH
DS
FIGURE 15. WE CONTROLLED WRITE CYCLE
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X28HC64
t
WC
ADDRESS
CE
t
t
AH
AS
t
CW
t
OES
OE
t
OEH
t
t
CH
CS
WE
t
DV
DATA VALID
DATA IN
t
t
DH
DS
HIGH Z
DATA OUT
FIGURE 16. CE CONTROLLED WRITE CYCLE
OE
Note 17
CE
t
t
BLC
WP
WE
t
WPH
ADDRESS
Note 18
LAST BYTE
Byte n+2
I/O
Byte 0
Byte 1
Byte 2
Byte n
Byte n+1
t
WC
*For each successive write within the page write operation, A –A should be the same or
6
12
writes to an unknown address could occur.
FIGURE 17. PAGE WRITE CYCLE
NOTES:
17. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from
another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
18. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE
or WE controlled write cycle timing.
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X28HC64
ADDRESS
CE
A
A
A
n
n
n
WE
t
t
OEH
OES
OE
t
DW
D
= X
D
= X
OUT
I/O
7
D
= X
OUT
IN
t
WC
FIGURE 18. DATA POLLING TIMING DIAGRAM (Note 19)
CE
WE
OE
t
OES
t
OEH
t
DW
HIGH Z
I/O*
*
6
*
t
WC
* I/O beginning and ending state will vary, depending upon actual t
6
.
WC
FIGURE 19. TOGGLE BIT TIMING DIAGRAM (Note 19)
NOTE:
19. Polling operations are by definition read cycles and are therefore subject to read cycle timings.
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X28HC64
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to the web to make sure that you have the latest revision.
DATE
REVISION
FN8109.4
CHANGE
June 27, 2016
Updated entire datasheet applying Intersil’s new standards.
Updated the Ordering Information table by adding Note 2, updated other tape and reel notes, updated all of the
part marking and added Note 6.
Added Thermal Information (Theta JA, Theta JC, and applicable notes) on page 9.
Added “The endurance and data retention specifications are established by characterization and are not
production tested” to the “Endurance and Data Retention” table.
August 18, 2015
FN8109.3
- Updated Ordering Information Table on page 2.
- Added Revision History and About Intersil sections.
- Updated POD M28.3 to latest revision changes are as follow:
Added land pattern.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
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X28HC64
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.056 (1.42)
PIN (1)
IDENTIFIER
0.004 (0.10)
C
N32.45x55 (JEDEC MS-016AE ISSUE A)
0.042 (1.07)
0.048 (1.22)
32 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
0.050 (1.27) TP
ND
0.025 (0.64)
0.045 (1.14)
R
INCHES
MILLIMETERS
C
L
SYMBOL
A
MIN
MAX
MIN
3.18
MAX
3.55
NOTES
0.125
0.060
0.485
0.447
0.188
0.585
0.547
0.238
0.140
0.095
0.495
0.453
0.223
0.595
0.553
0.273
-
A1
D
1.53
2.41
-
D2/E2
D2/E2
12.32
11.36
4.78
12.57
11.50
5.66
-
C
L
D1
D2
E
3
E1
E
4, 5
NE
14.86
13.90
6.05
15.11
14.04
6.93
-
VIEW “A”
E1
E2
N
3
4, 5
0.015 (0.38)
MIN
28
7
28
7
6
A1
ND
NE
7
7
D1
D
A
9
9
SEATING
PLANE
0.020 (0.51) MAX
3 PLCS
-C-
Rev. 0 7/98
NOTES:
0.026 (0.66)
0.032 (0.81)
0.050 (1.27)
MIN
1. Controlling dimension: INCH. Converted millimeter
dimensions are not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions.
Allowable mold protrusion is 0.010 inch (0.25mm) per side.
Dimensions D1 and E1 include mold mismatch and are
measured at the extreme material condition at the body
parting line.
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
(0.12)
0.005
M
A S - B S D S
-C-
4. To be measured at seating plane
contact point.
VIEW “A” TYP.
5. Centerline to be determined where center leads exit plastic
body.
6. “N” is the number of terminal positions.
7. ND denotes the number of leads on the two shorts sides of the
package, one of which contains pin #1. NE denotes the
number of leads on the two long sides of the package.
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X28HC64
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
0.25(0.010)
M
B M
H
AREA
INCHES MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
NOTES
-B-
A
A1
B
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
0.30
-
1
2
3
L
0.51
9
SEATING PLANE
A
C
0.0091
0.6969
0.2914
0.32
-
-A-
D
E
0.7125 17.70
18.10
7.60
3
h x 45o
D
0.2992
7.40
4
e
0.05 BSC
1.27 BSC
-
-C-
a
0.394
0.01
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
H
e
A1
C
5
h
B
0.10(0.004)
L
0.016
6
0.25(0.010) M
C
A M B S
N
28
28
7
0o
8o
0o
8o
-
Rev. 1, 1/13
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
TYPICAL RECOMMENDED LAND PATTERN
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
(1.50mm)
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
(9.38mm)
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
(1.27mm TYP)
(0.51mm TYP)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
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X28HC64
Dual-In-Line Plastic Packages (PDIP)
E28.6 (JEDEC MS-011-AB ISSUE B)
28 LEAD DUAL-IN-LINE PLASTIC PACKAGE
N
E1
INCHES MILLIMETERS
MIN
INDEX
1 2
3
N/2
AREA
SYMBOL
MAX
0.250
-
MIN
-
MAX
6.35
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
0.015
0.125
0.014
0.030
0.008
1.380
0.005
0.600
0.485
0.39
3.18
0.356
0.77
0.204
4
D
E
0.195
0.022
0.070
0.015
1.565
-
4.95
0.558
1.77
0.381
-
BASE
PLANE
A2
A
-
SEATING
PLANE
B1
C
8
L
C
L
-
D1
B1
eA
A1
A
D1
e
D
35.1
39.7
5
eC
C
B
D1
E
0.13
15.24
12.32
-
5
eB
0.010 (0.25) M
C
B S
0.625
0.580
15.87
14.73
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.600 BSC
2.54 BSC
15.24 BSC
-
eA
eB
L
6
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.700
0.200
-
17.78
5.08
7
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in JEDEC
seating plane gauge GS-3.
N
28
28
Rev. 1 12/00
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed 0.010 inch (0.25mm).
eA
6. E and
are measured with the leads constrained to be
-C-
perpendicular to datum
.
7. eB and eC are measured at the lead tips with the leads unconstrained. eC
must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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