UPD789417AGC-XXX-8BT [RENESAS]
Microcontroller, 8-Bit, MROM, 5MHz, CMOS, PQFP80, 14 X 14 MM, PLASTIC, QFP-80;
| 型号： | UPD789417AGC-XXX-8BT |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Microcontroller, 8-Bit, MROM, 5MHz, CMOS, PQFP80, 14 X 14 MM, PLASTIC, QFP-80 时钟 微控制器 外围集成电路 |
| 文件： | 总320页 (文件大小：2424K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
User’s Manual
µPD789407A, 789417A
Subseries
8-Bit Single-Chip Microcontrollers
µPD789405A
µPD789406A
µPD789407A
µPD789415A
µPD789416A
µPD789417A
µPD78F9418A
Document No. U13952EJ3V1UD00 (3rd edition)
Date Published October 2005 N CP(K)
1999, 2003
Printed in Japan
[MEMO]
2
User’s Manual U13952EJ3V1UD
NOTES FOR CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
1
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is
fixed, and also in the transition period when the input level passes through the area between VIL (MAX)
and VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or
GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins
must be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
User’s Manual U13952EJ3V1UD
3
EEPROM and FIP are trademarks of NEC Electronics Corporation.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
•
The information in this document is current as of August, 2005. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
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representative for availability and additional information.
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Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
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The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
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(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
4
User’s Manual U13952EJ3V1UD
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
•
•
•
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Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
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J05.6
User’s Manual U13952EJ3V1UD
5
Major Revisions in This Edition
Page
Description
U13952EJ2V0UD00 → U13952EJ3V0UD00
pp.38, 39, 41
p.92
Modification of pin handling of AVREF pin and VPP pin in CHAPTER 2 PIN FUNCTIONS
Addition of Note related to feedback resistor in Figure 5-3 Format of Suboscillation Mode Register
Addition of 6.5 Cautions on Using 16-Bit Timer 50
pp.112, 113
pp.151, 164
Addition of (8) Input impedance of ANI0 to ANI6 pins in 10.5 Cautions on Using 8-Bit A/D Converter and
11.5 Cautions on Using 10-Bit A/D Converter
p.154
p.196
Modification of description of (2) A/D conversion result register 0 (ADCR0) in 11.2 Configuration of 10-Bit
A/D Converter
Addition of description on reading receive data of UART in 13.4.2 Asynchronous serial interface (UART)
mode
p.232
p.237
p.256
Addition of Caution in Figure 15-2 Format of Interrupt Request Flag Register
Addition of Caution in Figure 15-7 Format of Key Return Mode Register 00
Addition of description on pull-up resistor and divider resistor for LCD driving in Table 18-1 Differences
Between µPD78F9418A and Mask ROM Versions
pp.257 to 266
pp.278 to 292
pp.293 to 295
pp.296, 297
Overall revision of contents related to flash memory programming as 18.1 Flash Memory Characteristics
Addition of CHAPTER 21 ELECTRICAL SPECIFICATIONS
Addition of CHAPTER 22 CHARACTERISTICS CURVES (REFERENCE VALUES)
Addition of CHAPTER 23 PACKAGE DRAWINGS
pp.298, 299
Addition of CHAPTER 24 RECOMMENDED SOLDERING CONDITIONS
pp.301 to 310
Overall revision of contents of APPENDIX A DEVELOPMENT TOOLS
Deletion of embedded software
pp.311 to 314
Addition of APPENDIX B NOTES ON TARGET SYSTEM DESIGN
U13952EJ3V0UD00 → U13952EJ3V1UD00
Modification of 1.3 Ordering Information
p. 24
Addition of Table 24-1. Surface Mounting Type Soldering Conditions (3/3)
p. 300
The mark shows major revised points.
6
User’s Manual U13952EJ3V1UD
INTRODUCTION
Target Readers
This manual is intended for users who wish to understand the functions of the
µPD789407A and µPD789417A Subseries and to design and develop application
systems and programs using these microcontrollers.
Target products:
• µPD789407A Subseries: µPD789405A, µPD789406A, and µPD789407A
• µPD789417A Subseries: µPD789415A, µPD789416A, µPD789417A, and
µPD78F9418A
Purpose
This manual is intended to give users an understanding of the functions described in
the Organization below.
Organization
The µPD789407A and µPD789417A Subseries User’s Manual is divided into two
parts: this manual and instructions (common to the 78K/0S Series).
µPD789407A and µPD789417A
Subseries
78K/0S Series
User’s Manual
Instructions
User’s Manual
• Pin functions
• CPU function
• Internal block functions
• Interrupt functions
• Instruction set
• Explanation of each
instruction
• Other on-chip peripheral functions
• Electrical specifications
How to Read This Manual
It is assumed that the reader of this manual has general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
• To understand the functions in general:
→ Read this manual in the order of the CONTENTS.
• How to interpret the register formats:
→ The name of a bit whose number is enclosed in brackets is reserved for the
assembler and is defined for the C compiler by the header file sfrbit.h.
• When you know a register name and want to confirm its details:
→ Read APPENDIX C REGISTER INDEX.
• To know the 78K/0S Series instructions functions in detail:
→ Refer to 78K/0S Series Instructions User’s Manual (U11047E).
• To learn the electrical specifications of the µPD789407A and µPD789417A
Subseries
→ Refer to CHAPTER 21 ELECTRICAL SPECIFICATIONS.
User’s Manual U13952EJ3V1UD
7
Conventions
Data significance:
Active low representation:
Note:
Higher digits on the left and lower digits on the right
xxx (overscore over pin or signal name)
Footnote for item marked with Note in the text
Information requiring particular attention
Supplementary information
Caution:
Remark:
Numerical representation:
Binary ... xxxx or xxxxB
Decimal ... xxxx
Hexadecimal ... xxxxH
Related Documents
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
This manual
U11047E
µPD789407A, 789417A Subseries User’s Manual
78K/0S Series Instructions User’s Manual
Documents Related to Development Software Tools (User’s Manuals)
Document Name
Document No.
U14876E
U14877E
U11623E
U14871E
U14872E
U15373E
U15802E
U15185E
U14610E
RA78K0S Assembler Package
Operation
Language
Structured Assembly Language
Operation
CC78K0S C Compiler
Language
SM78K Series System Simulator Ver. 2.30 or Later
Operation (WindowsTM Based)
External Part User Open Interface Specifications
Operation (Windows Based)
ID78K Series Integrated Debugger Ver. 2.30 or Later
Project Manager Ver. 3.12 or Later (Windows Based)
Documents Related to Development Hardware Tools (User’s Manuals)
Document Name
IE-78K0S-NS In-Circuit Emulator
Document No.
U13549E
IE-78K0S-NS-A In-Circuit Emulator
U15207E
IE-789418-NS-EM1 Emulation Board
U14364E
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
8
User’s Manual U13952EJ3V1UD
Documents Related to Flash Memory Writing
Document Name
Document No.
U13502E
PG-FP3 Flash Memory Programmer User’s Manual
PG-FP4 Flash Memory Programmer User’s Manual
U15260E
Other Related Documents
Document Name
Document No.
X13769X
Note
SEMICONDUCTOR SELECTION GUIDE - Products and Packages -
Semiconductor Device Mount Manual
Quality Grades on NEC Semiconductor Devices
C11531E
C10983E
C11892E
NEC Semiconductor Device Reliability/Quality Control System
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html)
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
User’s Manual U13952EJ3V1UD
9
CONTENTS
CHAPTER 1 GENERAL...........................................................................................................................23
1.1 Features.........................................................................................................................................23
1.2 Applications ..................................................................................................................................23
1.3 Ordering Information....................................................................................................................24
1.4 Pin Configuration (Top View) ......................................................................................................25
1.5 78K/0S Series Lineup...................................................................................................................27
1.6 Block Diagram...............................................................................................................................30
1.7 Overview of Functions.................................................................................................................31
CHAPTER 2 PIN FUNCTIONS...............................................................................................................33
2.1 List of Pin Functions ....................................................................................................................33
2.2 Description of Pin Functions.......................................................................................................36
2.2.1 P00 to P03 (Port 0)............................................................................................................................36
2.2.2 P20 to P27 (Port 2)............................................................................................................................36
2.2.3 P40 to P47 (Port 4)............................................................................................................................37
2.2.4 P50 to P53 (Port 5)............................................................................................................................37
2.2.5 P60 to P66 (Port 6)............................................................................................................................37
2.2.6 P80 to P87 (Port 8)............................................................................................................................38
2.2.7 P90 to P93 (Port 9)............................................................................................................................38
2.2.8 S0 to S15 ..........................................................................................................................................38
2.2.9 COM0 to COM3 ................................................................................................................................38
2.2.10 VLC0 to VLC2 .....................................................................................................................................38
2.2.11 BIAS................................................................................................................................................38
2.2.12 AVREF ..............................................................................................................................................38
2.2.13 AVDD ...............................................................................................................................................38
2.2.14 AVSS ...............................................................................................................................................39
2.2.15 RESET ............................................................................................................................................39
2.2.16 X1, X2 .............................................................................................................................................39
2.2.17 XT1, XT2.........................................................................................................................................39
2.2.18 VDD0, VDD1 .......................................................................................................................................39
2.2.19 VSS0, VSS1 .......................................................................................................................................39
2.2.20 VPP (µPD78F9418A only) ................................................................................................................39
2.2.21 IC (mask ROM version only) ...........................................................................................................40
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ...........................................41
CHAPTER 3 CPU ARCHITECTURE......................................................................................................44
3.1 Memory Space ..............................................................................................................................44
3.1.1 Internal program memory space........................................................................................................48
3.1.2 Internal data memory space..............................................................................................................49
3.1.3 Special function register (SFR) area .................................................................................................49
3.1.4 Data memory addressing ..................................................................................................................50
3.2 Processor Registers.....................................................................................................................54
3.2.1 Control registers................................................................................................................................54
10
User’s Manual U13952EJ3V1UD
3.2.2 General-purpose registers................................................................................................................. 57
3.2.3 Special function registers (SFR)........................................................................................................ 58
3.3 Instruction Address Addressing.................................................................................................61
3.3.1 Relative addressing........................................................................................................................... 61
3.3.2 Immediate addressing....................................................................................................................... 62
3.3.3 Table indirect addressing .................................................................................................................. 63
3.3.4 Register addressing .......................................................................................................................... 63
3.4 Operand Address Addressing ....................................................................................................64
3.4.1 Direct addressing .............................................................................................................................. 64
3.4.2 Short direct addressing ..................................................................................................................... 65
3.4.3 Special function register (SFR) addressing....................................................................................... 66
3.4.4 Register addressing .......................................................................................................................... 67
3.4.5 Register indirect addressing.............................................................................................................. 68
3.4.6 Based addressing ............................................................................................................................. 69
3.4.7 Stack addressing............................................................................................................................... 69
CHAPTER 4 PORT FUNCTIONS...........................................................................................................70
4.1 Function of Port............................................................................................................................70
4.2 Configuration of Ports .................................................................................................................72
4.2.1 Port 0 ................................................................................................................................................ 72
4.2.2 Port 2 ................................................................................................................................................ 73
4.2.3 Port 4 ................................................................................................................................................ 78
4.2.4 Port 5 ................................................................................................................................................ 80
4.2.5 Port 6 ................................................................................................................................................ 81
4.2.6 Port 8 ................................................................................................................................................ 83
4.2.7 Port 9 ................................................................................................................................................ 84
4.3 Registers Controlling Ports.........................................................................................................85
4.4 Operation of Ports........................................................................................................................88
4.4.1 Writing to I/O port.............................................................................................................................. 88
4.4.2 Reading from I/O port........................................................................................................................ 88
4.4.3 Arithmetic operation of I/O port ......................................................................................................... 88
CHAPTER 5 CLOCK GENERATOR......................................................................................................89
5.1 Functions of Clock Generator.....................................................................................................89
5.2 Configuration of Clock Generator ..............................................................................................89
5.3 Registers Controlling Clock Generator......................................................................................91
5.4 System Clock Oscillators ............................................................................................................94
5.4.1 Main system clock oscillator.............................................................................................................. 94
5.4.2 Subsystem clock oscillator ................................................................................................................ 95
5.4.3 Examples of incorrect resonator connection ..................................................................................... 96
5.4.4 Divider............................................................................................................................................... 97
5.4.5 When no subsystem clock is used .................................................................................................... 97
5.5 Operation of Clock Generator.....................................................................................................98
5.6 Changing Setting of System Clock and CPU Clock..................................................................99
5.6.1 Time required for switching between system clock and CPU clock................................................... 99
5.6.2 Switching between system clock and CPU clock ............................................................................ 100
User’s Manual U13952EJ3V1UD
11
CHAPTER 6 16-BIT TIMER 50.............................................................................................................101
6.1 Function of 16-Bit Timer 50 .......................................................................................................101
6.2 Configuration of 16-Bit Timer 50...............................................................................................102
6.3 Registers Controlling 16-Bit Timer 50......................................................................................104
6.4 Operation of 16-Bit Timer 50 .....................................................................................................107
6.4.1 Operation as timer interrupt.............................................................................................................107
6.4.2 Operation as timer output................................................................................................................109
6.4.3 Capture operation............................................................................................................................110
6.4.4 16-bit timer counter 50 readout .......................................................................................................111
6.5 Cautions on Using 16-Bit Timer 50...........................................................................................112
6.5.1 Restrictions when rewriting 16-bit compare register 50...................................................................112
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02 .............................................................114
7.1 Function of 8-Bit Timer/Event Counters 00 to 02....................................................................114
7.2 Configuration of 8-Bit Timer/Event Counters 00 to 02 ...........................................................115
7.3 Registers Controlling 8-Bit Timer/Event Counters 00 to 02...................................................118
7.4 Operation of 8-Bit Timer/Event Counters 00 to 02..................................................................122
7.4.1 Operation as interval timer ..............................................................................................................122
7.4.2 Operation as external event counter (timer 00 and timer 01 only)...................................................125
7.4.3 Operation as square-wave output (timer 02 only)............................................................................126
7.5 Cautions on Using 8-Bit Timer/Event Counters 00 to 02........................................................128
CHAPTER 8 WATCH TIMER ...............................................................................................................129
8.1 Functions of Watch Timer .........................................................................................................129
8.2 Configuration of Watch Timer...................................................................................................130
8.3 Register Controlling Watch Timer ............................................................................................131
8.4 Operation of Watch Timer..........................................................................................................132
8.4.1 Operation as watch timer ................................................................................................................132
8.4.2 Operation as interval timer ..............................................................................................................132
CHAPTER 9 WATCHDOG TIMER .......................................................................................................134
9.1 Functions of Watchdog Timer...................................................................................................134
9.2 Configuration of Watchdog Timer ............................................................................................135
9.3 Registers Controlling Watchdog Timer....................................................................................136
9.4 Operation of Watchdog Timer...................................................................................................138
9.4.1 Operation as watchdog timer...........................................................................................................138
9.4.2 Operation as interval timer ..............................................................................................................139
CHAPTER 10 8-BIT A/D CONVERTER (µPD789407A SUBSERIES).............................................140
10.1 Function of 8-Bit A/D Converter..............................................................................................140
10.2 Configuration of 8-Bit A/D Converter .....................................................................................140
10.3 Registers Controlling 8-Bit A/D Converter.............................................................................143
10.4 Operation of 8-Bit A/D Converter............................................................................................145
10.4.1 Basic operation of 8-bit A/D converter...........................................................................................145
10.4.2 Input voltage and conversion result...............................................................................................146
10.4.3 Operation mode of 8-bit A/D converter..........................................................................................148
12
User’s Manual U13952EJ3V1UD
10.5 Cautions on Using 8-Bit A/D Converter .................................................................................149
CHAPTER 11 10-BIT A/D CONVERTER (µPD789417A SUBSERIES)...........................................153
11.1 Function of 10-Bit A/D Converter ...........................................................................................153
11.2 Configuration of 10-Bit A/D Converter...................................................................................153
11.3 Registers Controlling 10-Bit A/D Converter ..........................................................................156
11.4 Operation of 10-Bit A/D Converter..........................................................................................158
11.4.1 Basic operation of 10-bit A/D converter......................................................................................... 158
11.4.2 Input voltage and conversion result............................................................................................... 160
11.4.3 Operation mode of 10-bit A/D converter........................................................................................ 161
11.5 Cautions on Using 10-Bit A/D Converter ...............................................................................162
CHAPTER 12 COMPARATOR..............................................................................................................166
12.1 Functions of Comparator ........................................................................................................166
12.2 Configuration of Comparator..................................................................................................167
12.3 Register Controlling Comparator ...........................................................................................168
12.4 Operation of Comparator.........................................................................................................169
CHAPTER 13 SERIAL INTERFACE 00..............................................................................................171
13.1 Functions of Serial Interface 00..............................................................................................171
13.2 Configuration of Serial Interface 00 .......................................................................................172
13.3 Registers Controlling Serial Interface 00...............................................................................176
13.4 Operation of Serial Interface 00 ..............................................................................................183
13.4.1 Operation stopped mode............................................................................................................... 183
13.4.2 Asynchronous serial interface (UART) mode ................................................................................ 185
13.4.3 3-wire serial I/O mode................................................................................................................... 198
CHAPTER 14 LCD CONTROLLER/DRIVER.......................................................................................202
14.1 Functions of LCD Controller/Driver........................................................................................202
14.2 Configuration of LCD Controller/Driver .................................................................................203
14.3 Registers Controlling LCD Controller/Driver.........................................................................205
14.4 Setting LCD Controller/Driver .................................................................................................208
14.5 LCD Display Data Memory.......................................................................................................208
14.6 Common and Segment Signals ..............................................................................................209
14.7 Supplying LCD Drive Voltages VLC0, VLC1, and VLC2 .............................................................213
14.8 Display Modes ..........................................................................................................................215
14.8.1 Static display example................................................................................................................... 215
14.8.2 Two-time-slice display example .................................................................................................... 218
14.8.3 Three-time-slice display example.................................................................................................. 221
14.8.4 Four-time-slice display example.................................................................................................... 225
CHAPTER 15 INTERRUPT FUNCTIONS............................................................................................228
15.1 Interrupt Function Types.........................................................................................................228
15.2 Interrupt Sources and Configuration .....................................................................................228
15.3 Registers Controlling Interrupt Function...............................................................................231
15.4 Operation of Interrupt Servicing.............................................................................................238
15.4.1 Non-maskable interrupt acknowledgment operation ..................................................................... 238
User’s Manual U13952EJ3V1UD
13
15.4.2 Maskable interrupt acknowledgment operation .............................................................................240
15.4.3 Multiple interrupt servicing.............................................................................................................241
15.4.4 Putting interrupt requests on hold..................................................................................................243
CHAPTER 16 STANDBY FUNCTION..................................................................................................244
16.1 Standby Function and Configuration.....................................................................................244
16.1.1 Standby function............................................................................................................................244
16.1.2 Standby function control register...................................................................................................245
16.2 Operation of Standby Function...............................................................................................246
16.2.1 HALT mode...................................................................................................................................246
16.2.2 STOP mode ..................................................................................................................................249
CHAPTER 17 RESET FUNCTION .......................................................................................................252
CHAPTER 18 µPD78F9418A................................................................................................................256
18.1 Flash Memory Characteristics ................................................................................................257
18.1.1 Programming environment ............................................................................................................257
18.1.2 Communication mode ...................................................................................................................258
18.1.3 On-board pin connections .............................................................................................................261
18.1.4 Connection when using flash memory writing adapter ..................................................................264
CHAPTER 19 MASK OPTIONS ...........................................................................................................267
19.1 Mask Option for Pins................................................................................................................267
19.2 Mask Option for Voltage Division Resistor for LCD Driver..................................................267
CHAPTER 20 INSTRUCTION SET ......................................................................................................268
20.1 Operation...................................................................................................................................268
20.1.1 Operand identifiers and description methods ................................................................................268
20.1.2 Description of “Operation” column.................................................................................................269
20.1.3 Description of “Flag” column..........................................................................................................269
20.2 Operation List ...........................................................................................................................270
20.3 Instructions Listed by Addressing Type................................................................................275
CHAPTER 21 ELECTRICAL SPECIFICATIONS.................................................................................278
CHAPTER 22 CHARACTERISTICS CURVES (REFERENCE VALUES).........................................293
22.1 Characteristics Curves for Mask ROM Versions...................................................................293
22.2 Characteristics Curves for µPD78F9418A .............................................................................295
CHAPTER 23 PACKAGE DRAWINGS................................................................................................296
CHAPTER 24 RECOMMENDED SOLDERING CONDITIONS...........................................................298
APPENDIX A DEVELOPMENT TOOLS...............................................................................................301
A.1 Software Package ......................................................................................................................303
A.2 Language Processing Software ...............................................................................................303
A.3 Control Software ........................................................................................................................304
14
User’s Manual U13952EJ3V1UD
A.4 Flash Memory Writing Tools.....................................................................................................304
A.5 Debugging Tools (Hardware)....................................................................................................305
A.6 Debugging Tools (Software).....................................................................................................306
A.7 Package Drawings of Conversion Socket and Conversion Adapter....................................307
A.7.1 Package drawing and recommended footprint of conversion socket (EV-9200GC-80) .................. 307
A.7.2 Package drawing of conversion adapter (TGK-080SDW)............................................................... 309
A.7.3 Package drawing of conversion adapter (TGC-080SBP)................................................................ 310
APPENDIX B NOTES ON TARGET SYSTEM DESIGN...................................................................311
APPENDIX C REGISTER INDEX.........................................................................................................315
C.1 Register Index (Alphabetic Order of Register Name) ............................................................315
C.2 Register Index (Alphabetic Order of Register Symbol) .........................................................317
APPENDIX D REVISION HISTORY.....................................................................................................319
User’s Manual U13952EJ3V1UD
15
LIST OF FIGURES (1/5)
Figure No.
2-1
Title
Page
Pin I/O Circuits .............................................................................................................................................42
3-1
Memory Map (µPD789405A and µPD789415A)...........................................................................................44
Memory Map (µPD789406A and µPD789416A)...........................................................................................45
Memory Map (µPD789407A and µPD789417A)...........................................................................................46
Memory Map (µPD78F9418A)......................................................................................................................47
Data Memory Addressing (µPD789405A and µPD789415A) .......................................................................50
Data Memory Addressing (µPD789406A and µPD789416A) .......................................................................51
Data Memory Addressing (µPD789407A and µPD789417A) .......................................................................52
Data Memory Addressing (µPD78F9418A) ..................................................................................................53
Program Counter Configuration....................................................................................................................54
Program Status Word Configuration.............................................................................................................54
Stack Pointer Configuration..........................................................................................................................56
Data Saved to Stack Memory.......................................................................................................................56
Data Restored from Stack Memory ..............................................................................................................56
General-Purpose Register Configuration......................................................................................................57
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
4-1
Port Types....................................................................................................................................................70
Block Diagram of P00 to P03 .......................................................................................................................72
Block Diagram of P20...................................................................................................................................73
Block Diagram of P21...................................................................................................................................74
Block Diagram of P22 and P24 ....................................................................................................................75
Block Diagram of P23...................................................................................................................................76
Block Diagram of P25 to P27 .......................................................................................................................77
Block Diagram of P40 to P45 .......................................................................................................................78
Block Diagram of P46 and P47 ....................................................................................................................79
Block Diagram of P50 to P53 .......................................................................................................................80
Block Diagram of P60 and P61 ....................................................................................................................81
Block Diagram of P62 to P66 .......................................................................................................................82
Block Diagram of P80 to P87 .......................................................................................................................83
Block Diagram of P90 to P93 .......................................................................................................................84
Format of Port Mode Register ......................................................................................................................86
Format of Pull-Up Resistor Option Register 0 ..............................................................................................86
Format of Pull-Up Resistor Option Register 1 ..............................................................................................87
Format of Pull-Up Resistor Option Register 2 ..............................................................................................87
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
Block Diagram of Clock Generator ...............................................................................................................90
Format of Processor Clock Control Register ................................................................................................91
Format of Suboscillation Mode Register.......................................................................................................92
Format of Subclock Control Register............................................................................................................93
External Circuit of Main System Clock Oscillator..........................................................................................94
External Circuit of Subsystem Clock Oscillator.............................................................................................95
Examples of Incorrect Resonator Connection ..............................................................................................96
Switching Between System Clock and CPU Clock.....................................................................................100
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User’s Manual U13952EJ3V1UD
LIST OF FIGURES (2/5)
Figure No.
Title
Page
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
Block Diagram of 16-Bit Timer 50...............................................................................................................102
Format of 16-Bit Timer Mode Control Register 50......................................................................................105
Format of Port Mode Register 2.................................................................................................................106
Settings of 16-Bit Timer Mode Control Register 50 for Timer Interrupt Operation......................................107
Timing of Timer Interrupt Operation ...........................................................................................................108
Settings of 16-Bit Timer Mode Control Register 50 for Timer Output Operation.........................................109
Timer Output Timing...................................................................................................................................109
Settings of 16-Bit Timer Mode Control Register 50 for Capture Operation.................................................110
Capture Operation Timing (Both Edges of CPT5 Pin Are Specified)..........................................................110
Readout Timing of 16-Bit Timer Counter 50...............................................................................................111
7-1
Block Diagram of 8-Bit Timer/Event Counter 00.........................................................................................116
Block Diagram of 8-Bit Timer/Event Counter 01.........................................................................................116
Block Diagram of 8-Bit Timer 02.................................................................................................................117
Format of 8-Bit Timer Mode Control Register 00........................................................................................118
Format of 8-Bit Timer Mode Control Register 01........................................................................................119
Format of 8-Bit Timer Mode Control Register 02........................................................................................120
Format of Port Mode Register 2.................................................................................................................121
Interval Timer Operation Timing of Timer 00 and Timer 01........................................................................123
Interval Timer Operation Timing of Timer 02..............................................................................................124
External Event Counter Operation Timing (with Rising Edge Specified) ....................................................125
Square-Wave Output Timing......................................................................................................................127
Start Timing of 8-Bit Timer Counters 00, 01, and 02 ..................................................................................128
External Event Counter Operation Timing..................................................................................................128
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
8-1
8-2
8-3
Block Diagram of Watch Timer...................................................................................................................129
Format of Watch Timer Mode Control Register..........................................................................................131
Watch Timer/Interval Timer Operation Timing............................................................................................133
9-1
9-2
9-3
Block Diagram of Watchdog Timer.............................................................................................................135
Format of Timer Clock Selection Register 2...............................................................................................136
Format of Watchdog Timer Mode Register ................................................................................................137
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
Block Diagram of 8-Bit A/D Converter........................................................................................................141
Format of A/D Converter Mode Register 0.................................................................................................143
Format of A/D Input Selection Register 0...................................................................................................144
Basic Operation of 8-Bit A/D Converter......................................................................................................146
Relationship Between Analog Input Voltage and A/D Conversion Result...................................................147
Software-Started A/D Conversion ..............................................................................................................148
How to Reduce Current Consumption in Standby Mode ............................................................................149
Conversion Result Readout Timing (When Conversion Result Is Undefined Value)..................................150
Conversion Result Readout Timing (When Conversion Result Is Normal Value).......................................150
Analog Input Pin Processing ......................................................................................................................151
A/D Conversion End Interrupt Request Generation Timing........................................................................152
User’s Manual U13952EJ3V1UD
17
LIST OF FIGURES (3/5)
Figure No.
10-12
Title
Page
AVDD Pin Processing ..................................................................................................................................152
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
11-11
11-12
Block Diagram of 10-Bit A/D Converter ......................................................................................................154
Format of A/D Converter Mode Register 0 .................................................................................................156
Format of A/D Input Selection Register 0 ...................................................................................................157
Basic Operation of 10-Bit A/D Converter....................................................................................................159
Relationship Between Analog Input Voltage and A/D Conversion Result...................................................160
Software-Started A/D Conversion...............................................................................................................161
How to Reduce Current Consumption in Standby Mode ............................................................................162
Conversion Result Readout Timing (When Conversion Result Is Undefined Value) ..................................163
Conversion Result Readout Timing (When Conversion Result Is Normal Value).......................................163
Analog Input Pin Processing ......................................................................................................................164
A/D Conversion End Interrupt Request Generation Timing........................................................................165
AVDD Pin Processing ..................................................................................................................................165
12-1
12-2
12-3
12-4
12-5
Block Diagram of Comparator ....................................................................................................................167
Format of Comparator Mode Register 0.....................................................................................................168
Settings of Comparator Mode Register 0 for Comparator Operation..........................................................169
Settings of External Interrupt Mode Register 1 at INTCMP0 Occurrence...................................................169
Comparator Operation Timing....................................................................................................................170
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
13-10
13-11
Block Diagram of Serial Interface 00 ..........................................................................................................173
Block Diagram of Baud Rate Generator .....................................................................................................174
Format of Serial Operation Mode Register 00............................................................................................176
Format of Asynchronous Serial Interface Mode Register 00 ......................................................................177
Format of Asynchronous Serial Interface Status Register 00.....................................................................179
Format of Baud Rate Generator Control Register 00 .................................................................................180
Format of Asynchronous Serial Interface Transmit/Receive Data ..............................................................191
Asynchronous Serial Interface Transmission Completion Interrupt Timing.................................................193
Asynchronous Serial Interface Reception Completion Interrupt Timing......................................................194
Receive Error Timing..................................................................................................................................195
3-Wire Serial I/O Mode Timing ...................................................................................................................201
14-1
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
14-10
14-11
Block Diagram of LCD Controller/Driver.....................................................................................................204
Format of LCD Display Mode Register 0....................................................................................................205
Format of LCD Port Selector 0 ...................................................................................................................206
Format of LCD Clock Control Register 0 ....................................................................................................207
Relationship Between LCD Display Data Memory Contents and Segment/Common Outputs ...................208
Common Signal Waveforms.......................................................................................................................211
Voltages and Phases of Common and Segment Signals ...........................................................................212
Examples of LCD Drive Power Connections (with On-Chip Voltage Divider Resistors) .............................214
Static LCD Display Pattern and Electrode Connections .............................................................................215
Example of Connecting Static LCD Panel ..................................................................................................216
Static LCD Drive Waveform Examples.......................................................................................................217
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User’s Manual U13952EJ3V1UD
LIST OF FIGURES (4/5)
Figure No.
Title
Page
14-12
14-13
14-14
14-15
14-16
14-17
14-18
14-19
14-20
14-21
Two-Time-Slice LCD Display Pattern and Electrode Connections .............................................................218
Example of Connecting Two-Time-Slice LCD Panel ..................................................................................219
Two-Time-Slice LCD Drive Waveform Examples (1/2 Bias Method)..........................................................220
Three-Time-Slice LCD Display Pattern and Electrode Connections...........................................................221
Example of Connecting Three-Time-Slice LCD Panel................................................................................222
Three-Time-Slice LCD Drive Waveform Examples (1/2 Bias Method) .......................................................223
Three-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method) .......................................................224
Four-Time-Slice LCD Display Pattern and Electrode Connections.............................................................225
Example of Connecting Four-Time-Slice LCD Panel..................................................................................226
Four-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method) .........................................................227
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
15-10
15-11
15-12
15-13
15-14
Basic Configuration of Interrupt Function ...................................................................................................230
Format of Interrupt Request Flag Register.................................................................................................232
Format of Interrupt Mask Flag Register......................................................................................................233
Format of External Interrupt Mode Register 0 ............................................................................................234
Format of External Interrupt Mode Register 1 ............................................................................................235
Configuration of Program Status Word.......................................................................................................236
Format of Key Return Mode Register 00....................................................................................................237
Block Diagram of Falling Edge Detector.....................................................................................................237
Flowchart of Non-Maskable Interrupt Request Acknowledgment...............................................................239
Timing of Non-Maskable Interrupt Request Acknowledgment....................................................................239
Non-Maskable Interrupt Request Acknowledgment ...................................................................................239
Interrupt Acknowledgment Program Algorithm...........................................................................................240
Interrupt Request Acknowledgment Timing (Example: MOV A, r)..............................................................241
Interrupt Request Acknowledgment Timing (When Interrupt Request Flag
Is Generated in Final Clock Under Execution)............................................................................................241
Example of Multiple Interrupt......................................................................................................................242
15-15
16-1
16-2
16-3
16-4
16-5
Format of Oscillation Stabilization Time Selection Register .......................................................................245
Releasing HALT Mode by Interrupt ............................................................................................................247
Releasing HALT Mode by RESET Input.....................................................................................................248
Releasing STOP Mode by Interrupt............................................................................................................250
Releasing STOP Mode by RESET Input....................................................................................................251
17-1
17-2
17-3
17-4
Block Diagram of Reset Function...............................................................................................................252
Reset Timing by RESET Input ...................................................................................................................253
Reset Timing by Overflow in Watchdog Timer ...........................................................................................253
Reset Timing by RESET Input in STOP Mode...........................................................................................253
18-1
18-2
18-3
18-4
18-5
Environment for Writing Program to Flash Memory....................................................................................257
Communication Mode Selection Format ....................................................................................................258
Example of Connection with Dedicated Flash Programmer .......................................................................259
VPP Pin Connection Example......................................................................................................................261
Signal Conflict (Serial Interface Input Pin)..................................................................................................262
User’s Manual U13952EJ3V1UD
19
LIST OF FIGURES (5/5)
Figure No.
Title
Page
18-6
18-7
18-8
18-9
18-10
Malfunction of Another Device....................................................................................................................262
Signal Conflict (RESET Pin).......................................................................................................................263
Example of Flash Memory Writing Adapter Connection When Using 3-Wire Serial I/O Mode....................264
Example of Flash Memory Writing Adapter Connection When Using UART Mode ....................................265
Example of Flash Memory Writing Adapter Connection When Using Pseudo 3-Wire Mode
(When P0 Is Used).....................................................................................................................................266
A-1
A-2
A-3
A-4
A-5
Development Tools.....................................................................................................................................302
Package Drawing of EV-9200GC-80 (for Reference).................................................................................307
Recommended Footprint of EV-9200GC-80 (for Reference)......................................................................308
Package Drawing of TGK-080SDW (for Reference)...................................................................................309
Package Drawing of TGC-080SBP (for Reference)....................................................................................310
B-1
B-2
B-3
B-4
Distance Between In-Circuit Emulator and Conversion Socket (80GC) .....................................................311
Connection Condition of Target System (NP-80GC-TQ)............................................................................312
Distance Between In-Circuit Emulator and Conversion Adapter (80GK)....................................................313
Connection Condition of Target System (NP-80GK) ..................................................................................314
20
User’s Manual U13952EJ3V1UD
LIST OF TABLES (1/2)
Table No.
2-1
Title
Page
Types of Pin I/O Circuits...............................................................................................................................41
3-1
3-2
3-3
Internal ROM Capacity.................................................................................................................................48
Vector Table.................................................................................................................................................48
Special Function Register List......................................................................................................................59
4-1
4-2
4-3
Port Functions..............................................................................................................................................71
Configuration of Port ....................................................................................................................................72
Port Mode Register and Output Latch Settings When Using Alternate Functions........................................85
5-1
5-2
Configuration of Clock Generator.................................................................................................................89
Maximum Time Required for Switching CPU Clock .....................................................................................99
6-1
6-2
6-3
Configuration of 16-Bit Timer 50.................................................................................................................102
Interval Time of 16-Bit Timer 50.................................................................................................................107
Settings of Capture Edge ...........................................................................................................................110
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
Interval Time of 8-Bit Timer/Event Counter 00 ...........................................................................................114
Interval Time of 8-Bit Timer/Event Counter 01 ...........................................................................................114
Interval Time of 8-Bit Timer 02...................................................................................................................114
Square-Wave Output Range of 8-Bit Timer 02...........................................................................................115
Configuration of 8-Bit Timer/Event Counters 00 to 02................................................................................115
Interval Time of 8-Bit Timer/Event Counter 00 ...........................................................................................122
Interval Time of 8-Bit Timer/Event Counter 01 ...........................................................................................122
Interval Time of 8-Bit Timer 02...................................................................................................................123
Square-Wave Output Range of 8-Bit Timer 02...........................................................................................126
8-1
8-2
8-3
Interval Time of Interval Timer....................................................................................................................130
Configuration of Watch Timer.....................................................................................................................130
Interval Time of Interval Timer....................................................................................................................132
9-1
9-2
9-3
9-4
9-5
Program Loop Detection Time of Watchdog Timer ....................................................................................134
Interval Time ..............................................................................................................................................134
Configuration of Watchdog Timer...............................................................................................................135
Program Loop Detection Time of Watchdog Timer ....................................................................................138
Interval Time of Interval Timer....................................................................................................................139
10-1
11-1
12-1
13-1
Configuration of 8-Bit A/D Converter..........................................................................................................140
Configuration of 10-Bit A/D Converter........................................................................................................153
INTCMP0 Valid Edges ...............................................................................................................................169
Configuration of Serial Interface 00............................................................................................................172
User’s Manual U13952EJ3V1UD
21
LIST OF TABLES (2/2)
Table No.
Title
Page
13-2
13-3
13-4
13-5
13-6
13-7
Operation Mode Settings of Serial Interface 00..........................................................................................178
Example of Relationship Between Main System Clock and Baud Rate......................................................181
Relationship Between ASCK Pin Input Frequency and Baud Rate (When BRGC00 Is Set to 80H)...........182
Example of Relationship Between Main System Clock and Baud Rate......................................................189
Relationship Between ASCK Pin Input Frequency and Baud Rate (When BRGC00 Is Set to 80H)...........190
Receive Error Causes ................................................................................................................................195
14-1
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
14-10
Maximum Number of Pixels........................................................................................................................202
Configuration of LCD Controller/Driver.......................................................................................................203
Frame Frequencies (Hz).............................................................................................................................207
COM Signals ..............................................................................................................................................209
LCD Drive Voltage......................................................................................................................................210
LCD Drive Voltages (with On-Chip Voltage Divider Resistors)...................................................................213
Select and Deselect Voltages (COM0).......................................................................................................215
Select and Deselect Voltages (COM0 and COM1).....................................................................................218
Select and Deselect Voltages (COM0 to COM2)........................................................................................221
Select and Deselect Voltages (COM0 to COM3)........................................................................................225
15-1
15-2
15-3
Interrupt Source List ...................................................................................................................................229
Flags Corresponding to Interrupt Request Signal Name ............................................................................231
Time from Generation of Maskable Interrupt Request to Servicing ............................................................240
16-1
16-2
16-3
16-4
HALT Mode Operating Status ....................................................................................................................246
Operation After Release of HALT Mode.....................................................................................................248
STOP Mode Operating Status....................................................................................................................249
Operation After Release of STOP Mode ....................................................................................................251
17-1
Hardware Status After Reset......................................................................................................................254
18-1
18-2
18-3
Differences Between µPD78F9418A and Mask ROM Versions .................................................................256
Communication Mode List..........................................................................................................................258
Pin Connection List.....................................................................................................................................260
19-1
19-2
Selection of Mask Option for Pins ..............................................................................................................267
Combination of Selectable Voltage Division Resistor.................................................................................267
20-1
24-1
Operand Identifiers and Description Methods.............................................................................................268
Surface Mounting Type Soldering Conditions.............................................................................................298
22
User’s Manual U13952EJ3V1UD
CHAPTER 1 GENERAL
1.1 Features
• ROM and RAM capacities
Item
Program Memory
Data Memory
Internal High-Speed LCD Data RAM
RAM
Part Number
µPD789405A, 789415A
µPD789406A, 789416A
µPD789407A, 789417A
µPD78F9418A
28 × 4 bits
ROM
12 KB
16 KB
24 KB
512 bytes
Flash memory
32 KB
•
Minimum instruction execution time can be changed from high speed (0.4 µs: @ 5.0 MHz operation with main
system clock) to ultra low speed (122 µs: @ 32.768 kHz operation with subsystem clock)
• 43 I/O ports
• Serial interface channel: Switchable between 3-wire serial I/O and UART modes
• LCD controller/driver:
• Up to 28 segment signal outputs
• Up to 4 common signal outputs
• Bias switchable between 1/2 and 1/3
• Seven A/D converters with an 8-bit resolution (for µPD789407A Subseries only)
• Seven A/D converters with a 10-bit resolution (for µPD789417A Subseries only)
• Six timers:
• 16-bit timer
• Two 8-bit timer/event counters
• 8-bit timer
• Watch timer
• Watchdog timer
• 17 vectored interrupt sources
• Power supply voltage: VDD = 1.8 to 5.5 V
• Operating ambient temperature: TA = –40 to +85°C
1.2 Applications
APS compact cameras, manometers, rice cookers, etc.
User’s Manual U13952EJ3V1UD
23
CHAPTER 1 GENERAL
1.3 Ordering Information
Part Number
Package
Internal ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Flash memory
Flash memory
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Flash memory
Flash memory
µPD789405AGC-xxx-8BT
µPD789405AGK-xxx-9EU
µPD789406AGC-xxx-8BT
µPD789406AGK-xxx-9EU
µPD789407AGC-xxx-8BT
µPD789407AGK-xxx-9EU
µPD789415AGC-xxx-8BT
µPD789415AGK-xxx-9EU
µPD789416AGC-xxx-8BT
µPD789416AGK-xxx-9EU
µPD789417AGC-xxx-8BT
µPD789417AGK-xxx-9EU
µPD78F9418AGC-8BT
80-pin plastic QFP (14 x 14)
80-pin plastic TQFP (fine pitch) (12 x 12)
80-pin plastic QFP (14 x 14)
80-pin plastic TQFP (fine pitch) (12 x 12)
80-pin plastic QFP (14 x 14)
80-pin plastic TQFP (fine pitch) (12 x 12)
80-pin plastic QFP (14 x 14)
80-pin plastic TQFP (fine pitch) (12 x 12)
80-pin plastic QFP (14 x 14)
80-pin plastic TQFP (fine pitch) (12 x 12)
80-pin plastic QFP (14 x 14)
80-pin plastic TQFP (fine pitch) (12 x 12)
80-pin plastic QFP (14 x 14)
µPD78F9418AGK-9EU
80-pin plastic TQFP (fine pitch) (12 x 12)
80-pin plastic QFP (14 x 14)
µPD789405AGC-xxx-8BT-A
µPD789405AGK-xxx-9EU-A
µPD789406AGC-xxx-8BT-A
µPD789406AGK-xxx-9EU-A
µPD789407AGC-xxx-8BT-A
µPD789407AGK-xxx-9EU-A
µPD789415AGC-xxx-8BT-A
µPD789415AGK-xxx-9EU-A
µPD789416AGC-xxx-8BT-A
µPD789416AGK-xxx-9EU-A
µPD789417AGC-xxx-8BT-A
µPD789417AGK-xxx-9EU-A
µPD78F9418AGC-8BT-A
µPD78F9418AGK-9EU-A
80-pin plastic TQFP (fine pitch) (12 x 12)
80-pin plastic QFP (14 x 14)
80-pin plastic TQFP (fine pitch) (12 x 12)
80-pin plastic QFP (14 x 14)
80-pin plastic TQFP (fine pitch) (12 x 12)
80-pin plastic QFP (14 x 14)
80-pin plastic TQFP (fine pitch) (12 x 12)
80-pin plastic QFP (14 x 14)
80-pin plastic TQFP (fine pitch) (12 x 12)
80-pin plastic QFP (14 x 14)
80-pin plastic TQFP (fine pitch) (12 x 12)
80-pin plastic QFP (14 x 14)
80-pin plastic TQFP (fine pitch) (12 x 12)
Remarks 1. xxx indicates ROM code suffix.
2. Products that have the part numbers suffixed by "-A" are lead-free products.
24
User’s Manual U13952EJ3V1UD
CHAPTER 1 GENERAL
1.4 Pin Configuration (Top View)
•
•
80-pin plastic QFP (14 x 14)
80-pin plastic TQFP (fine pitch) (12 x 12)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
V
DD1
1
2
3
4
5
6
7
8
9
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P50
BIAS
P51
V
V
V
V
LC0
LC1
LC2
SS1
P52
P53
P20/SCK/ASCK
P21/SO/TxD
P22/SI/RxD
P23/CMPTOUT0/TO2
P24/INTP0/TI0
P25/INTP1/TI1
P26/INTP2/TO5
P27/INTP3/CPT5
AVSS
COM0
COM1
COM2
COM3
S0
10
11
12
13
14
15
16
17
18
19
20
S1
S2
S3
P60/ANI0/CMPIN0
P61/ANI1/CMPREF0
P62/ANI2
S4
S5
S6
P63/ANI3
S7
P64/ANI4
S8
P65/ANI5
S9
P66/ANI6
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.
2. Connect the AVDD pin to VDD0.
3. Connect the AVSS pin to VSS0.
Remark The parenthesized values apply to the µPD78F9418A.
User’s Manual U13952EJ3V1UD
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CHAPTER 1 GENERAL
ANI0 to ANI6:
ASCK:
Analog input
P60 to P66:
P80 to P87:
P90 to P93:
RESET:
Port 6
Asynchronous serial input
Analog power supply
Analog reference voltage
Analog ground
Port 8
AVDD:
Port 9
AVREF:
Reset
AVSS:
RxD:
Receive data
Segment output
Serial clock
BIAS:
LCD power supply bias control
Comparator input
S0 to S27:
SCK:
CMPIN0:
CMPREF0:
CMPTOUT0:
Comparator reference
Comparator output
SI:
Serial input
SO:
Serial output
Timer input
COM0 to COM3: Common output
TI0, TI1:
TO2, TO5:
TxD:
CPT5:
IC:
Capture trigger input
Internally connected
Timer output
Transmit data
Power supply
LCD power supply
Programming power supply
Ground
INTP0 to INTP3: Interrupt from peripherals
VDD0, VDD1:
VLC0 to VLC2:
VPP:
KR0 to KR5:
P00 to P03:
P20 to P27:
P40 to P47:
P50 to P53:
Key return
Port 0
Port 2
VSS0, VSS1:
X1, X2:
XT1, XT2:
Port 4
Crystal (main system clock)
Crystal (subsystem clock)
Port 5
26
User’s Manual U13952EJ3V1UD
CHAPTER 1 GENERAL
1.5 78K/0S Series Lineup
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
Products in mass
production
Products under
development
Y subseries supports SMB.
Small-scale package, general-purpose applications
µ
µ
µ
44-pin
PD789074 with subsystem clock added
µ
µ
µ
µ
µ
µ
µ
PD789046
PD789026
PD789088
PD789074
PD789014
PD789062
PD789052
42-/44-pin
PD789014 with enhanced timer function and expanded ROM and RAM
30-pin
30-pin
28-pin
PD789074 with enhanced timer function and expanded ROM and RAM
PD789026 with enhanced timer function
µ
On-chip UART and capable of low-voltage (1.8 V) operation
20-pin
20-pin
RC oscillation version of PD789052
µ
µ
PD789860 without EEPROMTM, POC, and LVI
Small-scale package, general-purpose applications and A/D function
PD789177Y
µ
µ
PD789167 with 10-bit A/D
44-pin
44-pin
30-pin
30-pin
30-pin
30-pin
30-pin
30-pin
µ
µ
PD789177
PD789167
PD789156
PD789146
PD789134A
PD789124A
PD789114A
PD789104A
µ
µ
PD789104A with enhanced timer function
PD789146 with 10-bit A/D
PD789104A with EEPROM added
PD789124A with 10-bit A/D
PD789167Y
µ
µ
µ
µ
µ
µ
µ
µ
µ
RC oscillation version of PD789104A
µ
µ
PD789104A with 10-bit A/D
PD789026 with 8-bit A/D and multiplier added
µ
LCD drive
144-pin
88-pin
80-pin
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
PD789835
UART + 8-bit A/D + dot LCD (total display outputs: 96)
UART + dot LCD (40 × 16)
SIO + 10-bit A/D + internal voltage boosting method LCD (28 × 4)
SIO + 8-bit A/D + resistance division method LCD (28 × 4)
PD789830
PD789489
PD789479
PD789417A
PD789407A
PD789456
PD789446
PD789436
PD789426
PD789316
PD789306
PD789467
PD789327
80-pin
80-pin
µ
PD789407A with 10-bit A/D
SIO + 8-bit A/D + resistance division method LCD (28 × 4)
PD789446 with 10-bit A/D
78K/0S
Series
80-pin
64-pin
64-pin
64-pin
64-pin
64-pin
µ
SIO + 8-bit A/D + internal voltage boosting method LCD (15 × 4)
µ
PD789426 with 10-bit A/D
SIO + 8-bit A/D + internal voltage boosting method LCD (5 × 4)
RC oscillation version of PD789306
µ
SIO + internal voltage boosting method LCD (24 × 4)
8-bit A/D + internal voltage boosting method LCD (23 × 4)
SIO + resistance division method LCD (24 × 4)
64-pin
52-pin
52-pin
µ
USB
44-pin
µ
PD789800
For PC keyboard. On-chip USB function
Inverter control
µ
PD789842
44-pin
30-pin
On-chip inverter controller and UART
On-chip CAN controller
On-chip bus controller
PD789850
µ
Keyless entry
30-pin
20-pin
20-pin
µ
µ
µ
µ
PD789860 with enhanced timer function, SIO, and expanded ROM and RAM
RC oscillation version of PD789860
PD789862
PD789861
PD789860
µ
On-chip POC and key return circuit
VFD drive
µ
PD789871
52-pin
64-pin
On-chip VFD controller (total display outputs: 25)
Meter control
µ
PD789881
UART + resistance division method LCD (26 × 4)
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.
User’s Manual U13952EJ3V1UD
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CHAPTER 1 GENERAL
The major functional differences between the subseries are listed below.
Series for general-purpose applications and LCD drive
Function
ROM
Capacity
(Bytes)
Timer
8-Bit 10-Bit
Serial Interface
I/O
VDD
Remarks
A/D
A/D
Subseries
8-Bit 16-Bit Watch WDT
MIN.Value
Small-
scale
µPD789046
16 K
1 ch 1 ch 1 ch 1 ch
−
−
1 ch (UART: 1 ch) 34
1.8 V
−
µPD789026
µPD789088
µPD789074
µPD789014
µPD789062
4Kto16K
−
package,
general-
purpose
applica-
tions
16 K to 32 K 3 ch
2 K to 8 K 1 ch
2 K to 4 K 2 ch
4 K
24
−
22
−
14
RC-oscillation
version
µPD789052
µPD789177
µPD789167
µPD789156
µPD789146
−
−
Small-
scale
16 K to 24 K 3 ch 1 ch 1 ch 1 ch
−
8 ch
−
8 ch 1 ch (UART: 1 ch) 31
1.8 V
−
package,
general-
purpose
applica-
tions +
A/D
8 K to 16 K 1 ch
−
4 ch
−
20
On-chip
EEPROM
4 ch
−
µPD789134A 2 K to 8 K
µPD789124A
4 ch
−
RC-oscillation
version
4 ch
−
converter
µPD789114A
4 ch
−
−
µPD789104A
4 ch
LCD
drive
µPD789835
µPD789830
µPD789489
µPD789479
24 K to 60 K 6 ch
−
1 ch 1 ch 3 ch
−
1 ch (UART: 1 ch) 37 1.8 VNote Dot LCD
supported
24 K
1 ch 1 ch
−
30 2.7 V
32 K to 48 K 3 ch
24 K to 48 K
8 ch 2 ch (UART: 1 ch) 45 1.8 V
−
8 ch
−
−
µPD789417A 12 K to 24 K
µPD789407A
7 ch 1 ch (UART: 1 ch) 43
7 ch
−
−
µPD789456
µPD789446
µPD789436
µPD789426
µPD789316
12 K to 16 K 2 ch
6 ch
−
30
40
6 ch
−
6 ch
−
6 ch
−
8 K to 16 K
4 K to 24 K
2 ch (UART: 1 ch) 23
RC-oscillation
version
µPD789306
µPD789467
µPD789327
−
−
1 ch
−
18
21
−
1 ch
Note Flash memory version: 3.0 V
28
User’s Manual U13952EJ3V1UD
CHAPTER 1 GENERAL
Series for ASSP
Function
ROM
Capacity
(Bytes)
Timer
8-Bit 16-Bit Watch WDT
8-Bit 10-Bit
Serial Interface
2 ch (USB: 1 ch)
I/O
VDD
Remarks
A/D
A/D
Subseries
USB
MIN.Value
µPD789800
µPD789842
8 K
2 ch
−
−
1 ch
−
−
−
31 4.0 V
−
−
Inverter
control
8 K to 16 K 3 ch Note 1 1 ch 1 ch 8 ch
1 ch (UART: 1 ch) 30 4.0 V
On-chip
bus
µPD789850
16 K
4 K
1 ch 1 ch
−
−
1 ch 4 ch
−
2 ch (UART: 1 ch) 18 4.0 V
−
controller
Keyless µPD789861
entry
2 ch
−
1 ch
−
−
−
14 1.8 V
RC-oscillation
version,
on-chip
EEPROM
µPD789860
µPD789862
On-chip
EEPROM
16 K
1 ch 2 ch
1 ch (UART: 1 ch) 22
VFD
drive
µPD789871
4 K to 8 K 3 ch
−
1 ch 1 ch
1 ch
−
−
−
−
1 ch
33 2.7 V
−
−
Meter
µPD789881
16 K 2 ch 1 ch
−
1 ch (UART: 1 ch) 28 2.7 VNote 2
control
Notes 1. 10-bit timer: 1 channel
2. Flash memory version: 3.0 V
User’s Manual U13952EJ3V1UD
29
CHAPTER 1 GENERAL
1.6 Block Diagram
8-bit timer
event/counter 00
TI0/P24
P00 to P03
P20 to P27
P40 to P47
P50 to P53
P60 to P66
P80 to P87
P90 to P93
Port 0
Port 2
Port 4
Port 5
Port 6
Port 8
Port 9
8-bit timer
event/counter 01
TI1/P25
TO2/P23
8-bit timer 02
16-bit timer 50
TO5/P26
CPT5/P27
ROM
78K/0S
Watch timer
(flash
CPU core
memory)
Watchdog timer
SCK/ASCK/P20
SO/TxD/P21
SI/RxD/P22
Serial
interface
RAM
RESET
X1
ANI0/P60
ANI1/P61
System control
X2
XT1
XT2
ANI2/P62 to
ANI6/P66
A/D converter
AVDD
AVSS
INTP0/P24
AVREF
INTP1/P25
Interrupt
control
INTP2/P26
INTP3/P27
S0 to S15
S16/P93 to S19/P90
S20/P87 to S27/P80
COM0 to COM3
KR0/P40 to KR5/P45
LCD
controller/driver
CMPTOUT0/P23
CMPIN0/P60
Comparator
CMPREF0/P61
V
LC0 to VLC2
V
V
DD0
DD1
V
V
SS0
IC
BIAS
SS1 (VPP
)
Remarks 1. The internal ROM capacity varies depending on the product.
2. The parenthesized values apply to the µPD78F9418A.
30
User’s Manual U13952EJ3V1UD
CHAPTER 1 GENERAL
1.7 Overview of Functions
µPD789405A
µPD789415A
µPD789406A
µPD789416A
µPD789407A
µPD789417A
µPD78F9418A
Part Number
Item
Internal memory
ROM
Mask ROM
12 KB
Flash memory
32 KB
16 KB
24 KB
High-speed RAM
LCD data RAM
512 bytes
28 × 4 bits
• 0.4/1.6 µs (@ 5.0 MHz operation with main system clock)
• 122 µs (@ 32.768 kHz operation with subsystem clock)
Minimum instruction execution time
8 bits × 8 registers
General-purpose registers
Instruction set
• 16-bit operations
• Bit manipulation (set, reset, and test)
I/O ports
Total of 43 port pins
• 7 CMOS input pins
• 32 CMOS I/O pins
• 4 N-ch open-drain pins (12 V withstanding voltage)
• Seven channels with 8-bit resolution (for µPD789407A Subseries)
• Seven channels with 10-bit resolution (for µPD789417A Subseries)
A/D converters
Comparator
With timer output control function
Serial interface
LCD controller/driver
Switchable between 3-wire serial I/O and UART modes
• Up to 28 segment signal outputs
• Up to 4 common signal outputs
• Bias switchable between 1/2 and 1/3
Timers
• 16-bit timer:
1 channel
1 channel
2 channels
1 channel
1 channel
• 8-bit timer:
• 8-bit timer/event counters:
• Watch timer:
• Watchdog timer:
Timer output
2 outputs
Maskable
Internal: 11, external: 5
Internal: 1
Vectored interrupt
sources
Non-maskable
Power supply voltage
VDD = 1.8 to 5.5 V
TA = −40 to +85°C
• 80-pin plastic QFP (14 x 14)
Operating ambient temperature
Package
• 80-pin plastic TQFP (fine pitch) (12 x 12)
User’s Manual U13952EJ3V1UD
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CHAPTER 1 GENERAL
An outline of the timer is shown below.
16-Bit
8-Bit
8-Bit
Watch Timer
Watchdog
Timer
Timer 50
Timer/Event
Counters 00, 01
Timer 02
Operation
mode
Interval timer
–
–
1 channel
1 channel
1 channel
–
1 channelNote 1
–
1 channelNote 2
–
External event
counter
Function
Timer outputs
1
–
–
–
1
1
–
–
–
–
Square-wave
outputs
Capture
1 input
1
–
1
–
1
–
2
–
2
Interrupt
sources
Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.
2. The watchdog timer has watchdog timer and interval timer functions. However, use the watchdog timer
by selecting either the watchdog timer function or interval timer function.
32
User’s Manual U13952EJ3V1UD
CHAPTER 2 PIN FUNCTIONS
2.1 List of Pin Functions
(1) Port pins
Pin Name
I/O
I/O
Function
After Reset
Input
Alternate Function
−
P00 to P03
Port 0.
4-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, use of an on-chip pull-up resistor
can be specified by setting pull-up resistor option register 0
(PU0).
P20
I/O
Port 2.
Input
SCK/ASCK
SO/TxD
8-bit I/O port.
P21
Input/output can be specified in 1-bit units.
When used as an input port, use of an on-chip pull-up resistor
can be specified by setting pull-up resistor option register 1
(PU1).
P22
SI/RxD
P23
CMPTOUT0/TO2
INTP0/TI0
INTP1/TI1
INTP2/TO5
INTP3/CPT5
KR0 to KR5
P24
P25
P26
P27
P40 to P45
I/O
I/O
Port 4.
Input
Input
8-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, use of an on-chip pull-up resistor
can be specified by setting pull-up resistor option register 0
(PU0).
−
−
P46, P47
P50 to P53
Port 5.
4-bit N-ch open-drain I/O port.
Input/output can be specified in 1-bit units.
For a mask ROM version, use of an on-chip pull-up resistor can
be specified by the mask option.
P60
Input
I/O
Port 6.
Input
Input
ANI0/CMPIN0
ANI1/CMPREF0
ANI2 to ANI6
S27 to S20
7-bit input port.
P61
P62 to P66
P80 to P87
Port 8.
8-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, use of an on-chip pull-up resistor
can be specified by setting pull-up resistor option register 2
(PU2).
P90 to P93
I/O
Port 9.
Input
S19 to S16
4-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, use of an on-chip pull-up resistor
can be specified by setting pull-up resistor option register 2
(PU2).
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CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins (1/2)
Pin Name
INTP0
I/O
Function
After Reset
Input
Alternate Function
Input
External interrupt input for which the valid edge (rising edge,
falling edge, or both rising and falling edges) can be specified
P24/TI0
P25/TI1
P26/TO5
P27/CPT5
P40 to P45
P22/RxD
P21/TxD
P20/ASCK
P20/SCK
P22/SI
INTP1
INTP2
INTP3
KR0 to KR5
SI
Input
Input
Key return signal detection
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Serial interface serial data input
SO
Output Serial interface serial data output
SCK
I/O
Serial interface serial clock input/output
ASCK
RxD
Input
Input
Serial clock input for asynchronous serial interface
Serial data input for asynchronous serial interface
TxD
Output Serial data output for asynchronous serial interface
P21/SO
P24/INTP0
P25/INTP1
P23/CMPTOUT0
P26/INTP2
P27/INTP3
P23/TO2
P60/ANI0
P61/ANI1
P60/CMPIN0
P61/CMPREF0
P62 to P66
•−•
TI0
Input
Input
External count clock input to 8-bit timer (TM00)
External count clock input to 8-bit timer (TM01)
TI1
TO2
Output 8-bit timer (TM02) output
Output 16-bit timer (TM50) output
TO5
CPT5
Input
Capture edge input
CMPTOUT0
CMPIN0
CMPREF0
ANI0
Output Comparator output
Input
Input
Input
Comparator input
Comparator reference voltage input
A/D converter analog input
ANI1
ANI2 to ANI6
AVREF
−
−
−
−
−
A/D converter reference voltage
A/D converter ground potential
A/D converter analog power supply
•−•
AVSS
−
•−•
AVDD
•−•
S0 to S15
S16 to S19
S20 to S27
Output LCD controller/driver segment signal output
Output
Input
P93 to P90
P87 to P80
−
COM0 to COM3 Output LCD controller/driver common signal output
Output
−
−
−
•−•
VLC0 to VLC2
BIAS
X1
LCD driving voltage
−
•−•
Supply voltage for LCD driving
−
•−•
Input
−
Connecting crystal resonator for main system clock oscillation
−
•−•
X2
−
−
•−•
XT1
Input
−
Connecting crystal resonator for subsystem clock oscillation
System reset input
•−•
XT2
•−•
RESET
Input
Input
34
User’s Manual U13952EJ3V1UD
CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins (2/2)
Pin Name
I/O
−
Function
After Reset
Alternate Function
−
−
−
−
−
−
•−•
•−•
•−•
•−•
•−•
•−•
VDD0
Positive power supply for ports
−
VDD1
VSS0
VSS1
IC
Positive power supply for circuits other than ports
Ground potential for ports
−
−
Ground potential of circuits other than ports
Internally connected. Connect directly to VSS0 or VSS1.
−
−
VPP
Sets flash memory programming mode.
Applies high voltage when a program is written or verified.
User’s Manual U13952EJ3V1UD
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CHAPTER 2 PIN FUNCTIONS
2.2 Description of Pin Functions
2.2.1 P00 to P03 (Port 0)
These pins constitute a 4-bit I/O port and can be set to input or output port mode in 1-bit units by using port mode
register 0 (PM0). When these pins are used as input port pins, an on-chip pull-up resistor can be used by setting pull-
up resistor option register 0 (PU0).
2.2.2 P20 to P27 (Port 2)
These pins constitute an 8-bit I/O port. In addition to I/O port pins, these pins can also function as the data and
clock I/O of the serial interface, external interrupt input, and timer I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
In this mode, P20 to P27 function as an 8-bit I/O port. These pins can be set to input or output mode in 1-bit
units by using port mode register 2 (PM2). When used as input port pins, an on-chip pull-up resistor can be
used by setting pull-up resistor option register 1 (PU1).
(2) Control mode
In this mode, P20 to P27 function as the data I/O and the clock I/O of the serial interface, the external
interrupt input, and timer I/O.
(a) SI, SO
These are the serial data I/O pins of the serial interface.
(b) SCK
This is the serial clock I/O pin of the serial interface.
(c) RxD, TxD
These are the serial data I/O pins of the asynchronous serial interface.
(d) ASCK
This is the serial clock input pin of the asynchronous serial interface.
(e) TI0, TI1
These are external clock input pins for the 8-bit timer/event counter.
(f) TO2
This is the output pin of the 8-bit timer.
(g) TO5
This is the output pin of the 16-bit timer.
(h) CPT5
This is the capture edge input pin.
36
User’s Manual U13952EJ3V1UD
CHAPTER 2 PIN FUNCTIONS
(i) INTP0 to INTP3
These are external interrupt input pins for which a valid edge (rising edge, falling edge, or both rising
and falling edges) can be specified.
(j) CMPTOUT0
This is the comparator output pin.
Caution When using P20 to P27 as serial interface pins, the I/O mode and output latch must be set
according to the function to be used. For details of the setting, refer to Table 13-2.
2.2.3 P40 to P47 (Port 4)
These pins constitute an 8-bit I/O port. In addition to I/O port pins, these pins can also function as key return
signal detection pins.
The following operation modes can be specified in 1-bit units.
(1) Port mode
In this mode, P40 to P47 function as an 8-bit I/O port. These pins can be set to input or output mode in 1-bit
units by using port mode register 4 (PM4). When used as input port pins, an on-chip pull-up resistor can be
used by setting pull-up resistor option register 0 (PU0).
(2) Control mode
In this mode, the pins function as key return signal detection pins (KR0 to KR5).
2.2.4 P50 to P53 (Port 5)
These pins constitute a 4-bit N-channel open-drain I/O port. In the mask ROM version, it is possible to specify that
pull-up resistors be used, via a mask option.
2.2.5 P60 to P66 (Port 6)
These pins constitute a 7-bit input-only port. In addition to general-purpose input port pins, these pins can also
function as A/D converter analog input pins and comparator input pins.
(1) Port mode
In this port mode, P60 to P66 function as a 7-bit input-only port.
(2) Control mode
In this mode, the pins can be used as A/D converter analog inputs and comparator inputs.
(a) ANI0 to ANI6
These are the A/D converter analog input pins.
(b) CMPIN0
This is the comparator input pin.
(c) CMPREF0
This is the comparator reference voltage input pin.
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CHAPTER 2 PIN FUNCTIONS
2.2.6 P80 to P87 (Port 8)
These pins constitute an 8-bit I/O port. In addition to I/O port pins, these pins can also function as LCD
controller/driver segment signal.
The following operation modes can be specified in 1-bit units.
(1) Port mode
In this port mode, P80 to P87 function as an 8-bit I/O port. These pins can be set to input or output mode in
1-bit units by using port mode register 8 (PM8). When used as an input port pins, an on-chip pull-up resistor
can be used by setting pull-up resistor option register 2 (PU2).
(2) Control mode
In this mode, P80 to P87 function as segment signal output pins (S20 to S27) for the LCD controller/driver.
2.2.7 P90 to P93 (Port 9)
These pins constitute a 4-bit I/O port. In addition to I/O port pins, these pins can also function as LCD
controller/driver segment signal.
The following operation modes can be specified in 1-bit units.
(1) Port mode
In this mode, P90 to P93 function as a 4-bit I/O port. These pins can be set to input or output mode in 1-bit
units by using port mode register 9 (PM9). When used as input port pins, an on-chip pull-up resistor can be
used by setting pull-up resistor option register 2 (PU2).
(2) Control mode
In this mode, P90 to P93 function as segment signal output pins (S16 to S19) for the LCD controller/driver.
2.2.8 S0 to S15
These pins are segment signal output pins for the LCD controller/driver.
2.2.9 COM0 to COM3
These pins are common signal output pins for the LCD controller/driver.
2.2.10 VLC0 to VLC2
These pins are power supply voltage pins to drive the LCD.
2.2.11 BIAS
This pin supplies power to drive the LCD.
2.2.12 AVREF
This pin is the A/D converter reference voltage pin. Connect it to VDD0, VDD1, VSS0, or VSS1 when not using the A/D
converter.
2.2.13 AVDD
This pin is the A/D converter analog circuit power supply pin. Always keep it at the same potential as the VDD0 pin
(even when the A/D converter is not used).
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CHAPTER 2 PIN FUNCTIONS
2.2.14 AVSS
This pin is the A/D converter ground potential pin. Always keep it at the same potential as the VSS0 pin (even when
the A/D converter is not used).
2.2.15 RESET
This pin inputs an active-low system reset signal.
2.2.16 X1, X2
These pins are used to connect a crystal resonator for main system clock oscillation.
To supply an external clock, input the clock to X1 and input the inverted signal to X2.
2.2.17 XT1, XT2
These pins are used to connect a crystal resonator for subsystem clock oscillation.
To supply an external clock, input the clock to XT1 and input the inverted signal to XT2.
2.2.18 VDD0, VDD1
VDD0 is the positive power supply pin for ports, while VDD1 is the positive power supply pin for other than ports.
2.2.19 VSS0, VSS1
VSS0 is the ground potential pin for ports, while the VSS1 is the ground potential pin for other than ports.
2.2.20 VPP (µPD78F9418A only)
A high voltage should be applied to this pin when the flash memory programming mode is set and when the
program is written or verified.
Handle the pins in either of the following ways.
• Independently connect a 10 kΩ pull-down resistor.
• Switch this pin to be directly connected to the dedicated flash programmer in programming mode or to VSS0 or
VSS1 in normal operation mode using a jumper on the board.
If the wiring between the VPP pin and VSS0 or VSS1 pin is long, or external noise is superimposed on the VPP pin, the
user program may not run correctly.
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CHAPTER 2 PIN FUNCTIONS
2.2.21 IC (mask ROM version only)
The IC (internally connected) pin is used to set the µPD789407A and µPD789417A Subseries in the test mode
before shipment. In the normal operation mode, directly connect this pin to the VSS0 or VSS1 pin with as short a wiring
length as possible.
If a potential difference is generated between the IC pin and VSS0 or VSS1 pin due to a long wiring length between
these pin, or due to external noise superimposed on the IC pin, the user program may not run correctly.
• Directly connect the IC pin to the VSS0 or VSS1 pin.
V
SS0
,
IC
V
SS1
Keep short
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2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 2-1.
For the I/O circuit configuration of each type, see Figure 2-1.
Table 2-1. Types of Pin I/O Circuits
Pin Name
I/O Circuit
Type
I/O
Recommended Connection of Unused Pins
P00 to P03
5-H
8-C
I/O
Input: Independently connect to VDD0, VDD1, VSS0, or VSS1 via a resistor.
Output: Leave open.
P20/SCK/ASCK
P21/SO/TxD
P22/SI/RxD
P23/CMPTOUT0/TO2
P24/INTP0/TI0
10-B
8-C
Input: Independently connect to VSS0 or VSS1 via a resistor.
Output: Leave open.
P25/INTP1/TI1
P26/INTP2/TO5
P27/INTP3/CPT5
P40/KR0 to P45/KR5
P46, P47
Input: Independently connect to VDD0, VDD1, VSS0, or VSS1 via a resistor.
Output: Leave open.
5-H
13-U
13-T
9-D
P50 to P53 (Mask ROM version)
P50 to P53 (µPD78F9418A)
P60/ANI0/CMPIN0
P61/ANI1/CMPREF0
P62/ANI2 to P66/ANI6
P80/S27 to P87/S20
P90/S19 to P93/S16
S0 to S15
Input: Independently connect to VDD0 or VDD1 via a resistor.
Output: Leave open.
Input
I/O
Connect directly to VDD0, VDD1, VSS0, or VSS1.
9-C
17-F
Input: Independently connect to VDD0, VDD1, VSS0, or VSS1 via a resistor.
Output: Leave open.
17-B
18-A
−
Output Leave open.
COM0 to COM3
VLC0 to VLC2
•−•
BIAS
Leave open. However, independently connect to VSS0 or VSS1 via a resistor
when none of VLC0 to VLC2 are used.
Connect directly to VDD0 or VDD1.
Connect directly to VDD0, VDD1, VSS0, or VSS1.
Connect directly to VSS0 or VSS1.
Connect directly to VSS0 or VSS1.
Leave open.
AVDD
AVREF
AVSS
XT1
Input
−
XT2
−
RESET
2
Input
•−•
−
IC (Mask ROM version)
VPP (µPD78F9418A)
Connect directly to VSS0 or VSS1.
Independently connect to a 10 kΩ pull-down resistor or connect directly
to VSS0 or VSS1.
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CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuits (1/2)
Type 2
IN
Type 9-D
P-ch
+
–
IN
N-ch
AVSS
VREF
(Threshold voltage)
Schmitt-triggered input with hysteresis characteristics
Type 5-H
Input
enable
Comparator
Type 10-B
V
DD0
V
DD0
Pull-up
enable
Pull-up
enable
P-ch
P-ch
VDD0
V
DD0
Data
P-ch
Data
P-ch
IN/OUT
IN/OUT
Open drain
Output disable
N-ch
Output
disable
N-ch
VSS0
V
SS0
Input
enable
Type 8-C
Type 13-T
V
DD0
IN/OUT
Data
Output disable
N-ch
Pull-up
enable
P-ch
V
SS0
V
DD0
Data
P-ch
IN/OUT
Input
Output
disable
N-ch
enable
Middle-voltage
input buffer
V
SS0
Type 9-C
IN
Type 13-U
V
DD0
Comparator
P-ch
N-ch
Pull-up resistor
(mask option)
+
–
AVSS
IN/OUT
VREF
(Threshold voltage)
Output data
Output disable
N-ch
V
SS0
Input
enable
Input enable
Middle-voltage
input buffer
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Figure 2-1. Pin I/O Circuits (2/2)
Type 17-B
Type 17-F
V
DD0
V
LC0
LC1
Pull-up
enable
P-ch
N-ch
P-ch
V
V
DD0
P-ch
N-ch
Data
OUT
P-ch
SEG
data
IN/OUT
Output
disable
N-ch
P-ch
N-ch
V
LC2
V
SS0
Input
enable
VSS1
Type 18-A
V
LC0
LC1
P-ch
V
V
LC0
LC1
V
P-ch
N-ch
SEG
data
P-ch
N-ch
P-ch
N-ch
N-ch
P-ch
OUT
SEG
output
COM
data
disable
P-ch
N-ch
V
LC2
V
LC2
N-ch
V
SS1
V
SS1
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CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
The µPD789407A and µPD789417A Subseries can access 64 KB of memory space. Figures 3-1 through 3-4
show the memory maps.
Figure 3-1. Memory Map (µPD789405A and µPD789415A)
FFFFH
Special function registers
256 × 8 bits
FF00H
FEFFH
Internal high-speed RAM
512 × 8 bits
FD00H
FCFFH
Reserved
FA1CH
FA1BH
RAM space for LCD data
28 × 4 bits
Data
FA00H
F9FFH
memory space
Reserved
2FFFH
3000H
2FFFH
Program area
0080H
007FH
Internal ROM
12288 × 8 bits
Program
memory space
CALLT table area
Program area
0040H
003FH
0024H
0023H
Vector table area
0000H
0000H
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Figure 3-2. Memory Map (µPD789406A and µPD789416A)
FFFFH
Special function registers
256 × 8 bits
FF00H
FEFFH
Internal high-speed RAM
512 × 8 bits
FD00H
FCFFH
Reserved
FA1CH
FA1BH
RAM space for LCD data
28 × 4 bits
Data
FA00H
F9FFH
memory space
Reserved
3FFFH
4000H
3FFFH
Program area
0080H
007FH
Internal ROM
16384 × 8 bits
Program
memory space
CALLT table area
Program area
0040H
003FH
0024H
0023H
Vector table area
0000H
0000H
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-3. Memory Map (µPD789407A and µPD789417A)
FFFFH
Special function registers
256 × 8 bits
FF00H
FEFFH
Internal high-speed RAM
512 × 8 bits
FD00H
FCFFH
Reserved
FA1CH
FA1BH
RAM space for LCD data
28 × 4 bits
Data
FA00H
F9FFH
memory space
Reserved
5FFFH
6000H
5FFFH
Program area
0080H
007FH
Internal ROM
24576 × 8 bits
Program
memory space
CALLT table area
Program area
0040H
003FH
0024H
0023H
Vector table area
0000H
0000H
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Figure 3-4. Memory Map (µPD78F9418A)
FFFFH
Special function registers
256 × 8 bits
FF00H
FEFFH
Internal high-speed RAM
512 × 8 bits
FD00H
FCFFH
Reserved
FA1CH
FA1BH
RAM space for LCD data
28 × 4 bits
Data
FA00H
F9FFH
memory space
Reserved
7FFFH
8000H
7FFFH
Program area
0080H
007FH
Flash memory
32768 × 8 bits
Program
memory space
CALLT table area
Program area
0040H
003FH
0024H
0023H
Vector table area
0000H
0000H
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CHAPTER 3 CPU ARCHITECTURE
3.1.1 Internal program memory space
The internal program memory space stores programs and table data. This space is usually addressed by the
program counter (PC).
The products in the µPD789407A and µPD789417A Subseries contain the following internal ROM (or flash
memory) capacities.
Table 3-1. Internal ROM Capacity
Part Number
Internal ROM
Structure
Mask ROM
Capacity
12288 × 8 bits
µPD789405A, 789415A
µPD789406A, 789416A
µPD789407A, 789417A
µPD78F9418A
16384 × 8 bits
24576 × 8 bits
32768 × 8 bits
Flash memory
The following areas are allocated to the internal program memory space.
(1) Vector table area
The 36-byte area of addresses 0000H to 0023H is reserved as a vector table area. This area stores program
start addresses to be used when branching by RESET input or interrupt request generation. Of a 16-bit
program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd
address.
Table 3-2. Vector Table
Vector Table Address
0000H
Interrupt Request
RESET input
Vector Table Address
0014H
Interrupt Request
INTWTI
0004H
0006H
0008H
000AH
000CH
000EH
0010H
0012H
INTWDT
INTP0
0016H
0018H
001AH
001CH
001EH
0020H
0022H
INTTM00
INTTM01
INTTM02
INTTM50
INTKR00
INTAD0
INTP1
INTP2
INTP3
INTSR00/INTCSI00
INTST00
INTWT
INTCMP0
(2) CALLT instruction table area
The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of
addresses 0040H to 007FH.
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3.1.2 Internal data memory space
The µPD789407A and µPD789417A Subseries products incorporate the following RAM:
(1) Internal high-speed RAM
An internal high-speed RAM is allocated to the area between FD00H and FEFFH.
The internal high-speed RAM is also used as a stack.
(2) LCD data RAM
An LCD data RAM is allocated to the area between FA00H and FA1BH.
The LCD display RAM can also be used as ordinary RAM.
3.1.3 Special function register (SFR) area
Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (see
Table 3-3).
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CHAPTER 3 CPU ARCHITECTURE
3.1.4 Data memory addressing
The µPD789407A and µPD789417A Subseries are provided with a variety of addressing modes to make memory
manipulation as efficient as possible. In the area that holds data memory (FD00H to FFFFH) especially, specific
modes of addressing that correspond to the particular function of an area, such as the special function registers (SFR)
or general-purpose registers, are available. Figures 3-5 through 3-8 show the data memory addressing modes.
Figure 3-5. Data Memory Addressing (µPD789405A and µPD789415A)
FFFFH
Special function registers (SFR)
SFR addressing
256 × 8 bits
FF20H
FF1FH
FF00H
FEFFH
Short direct
Internal high-speed RAM
addressing
512 × 8 bits
FE20H
FE1FH
FD00H
FCFFH
Direct addressing
Reserved
Register indirect
addressing
FA1CH
FA1BH
Based addressing
RAM space for LCD data
28 × 4 bits
FA00H
F9FFH
Reserved
3000H
2FFFH
Internal ROM
12288 × 8 bits
0000H
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Figure 3-6. Data Memory Addressing (µPD789406A and µPD789416A)
FFFFH
Special function registers (SFR)
SFR addressing
256 × 8 bits
FF20H
FF1FH
FF00H
FEFFH
Short direct
Internal high-speed RAM
addressing
512 × 8 bits
FE20H
FE1FH
FD00H
FCFFH
Direct addressing
Reserved
Register indirect
addressing
FA1CH
FA1BH
Based addressing
RAM space for LCD data
28 × 4 bits
FA00H
F9FFH
Reserved
4000H
3FFFH
Internal ROM
16384 × 8 bits
0000H
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-7. Data Memory Addressing (µPD789407A and µPD789417A)
FFFFH
Special function registers (SFR)
SFR addressing
256 × 8 bits
FF20H
FF1FH
FF00H
FEFFH
Short direct
Internal high-speed RAM
addressing
512 × 8 bits
FE20H
FE1FH
FD00H
FCFFH
Direct addressing
Reserved
Register indirect
addressing
FA1CH
FA1BH
Based addressing
RAM space for LCD data
28 × 4 bits
FA00H
F9FFH
Reserved
6000H
5FFFH
Internal ROM
24576 × 8 bits
0000H
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Figure 3-8. Data Memory Addressing (µPD78F9418A)
FFFFH
Special function registers (SFR)
SFR addressing
256 × 8 bits
FF20H
FF1FH
FF00H
FEFFH
Short direct
addressing
Internal high-speed RAM
512 × 8 bits
FE20H
FE1FH
FD00H
FCFFH
Direct addressing
Reserved
Register indirect
addressing
FA1CH
FA1BH
Based addressing
RAM space for LCD data
28 × 4 bits
FA00H
F9FFH
Reserved
8000H
7FFFH
Flash memory
32768 × 8 bits
0000H
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CHAPTER 3 CPU ARCHITECTURE
3.2 Processor Registers
The µPD789407A and µPD789417A Subseries are provided with the following on-chip processor registers.
3.2.1 Control registers
The control registers contains special functions to control the program sequence statuses and stack memory. A
program counter, a program status word, and a stack pointer constitute the control registers.
(1) Program counter (PC)
The program counter is a 16-bit register that holds the address information of the next program to be
executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction
to be fetched. When a branch instruction is executed, immediate data or register contents are set.
RESET input sets the program counter to the reset vector table values at addresses 0000H and 0001H.
Figure 3-9. Program Counter Configuration
15
0
PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction
execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions.
RESET input sets the PSW to 02H.
Figure 3-10. Program Status Word Configuration
7
0
IE
Z
0
AC
0
0
1
CY
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(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledgment operations of the CPU.
When 0, IE is set to the interrupt disable status (DI), and all interrupt requests other than non-maskable
interrupts are disabled.
When 1, IE is set to the interrupt enable status (EI). At this time, interrupt request acknowledgment is
controlled by an interrupt mask flag corresponding to the interrupt source.
IE is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all
other cases.
(d) Carry flag (CY)
This flag stores an overflow or underflow upon add/subtract instruction execution. It stores the shift-out
value upon rotate instruction execution and functions as a bit accumulator during bit manipulation
instruction execution.
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(3) Stack pointer (SP)
This is a 16-bit register used to hold the start address of the memory stack area. Only the internal high-
speed RAM area can be set as the stack area.
Figure 3-11. Stack Pointer Configuration
15
0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore)
from the stack memory.
Each stack operation saves/restores data as shown in Figures 3-12 and 3-13.
Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before
instruction execution.
Figure 3-12. Data Saved to Stack Memory
Interrupt
PUSH rp
instruction
CALL, CALLT
instructions
_
_
_
_
SP SP
SP
3
3
2
1
_
_
_
_
_
_
SP SP
SP
2
2
1
SP SP
SP
2
2
1
PC7 to PC0
PC15 to PC8
PSW
Lower
register pairs
SP
PC7 to PC0
Higher
register pairs
SP
SP
PC15 to PC8
SP
SP
SP
SP
Figure 3-13. Data Restored from Stack Memory
POP rp
RET instruction
RETI instruction
instruction
Lower
register pairs
SP
SP
SP + 1
PC7 to PC0
SP
SP + 1
PC7 to PC0
PC15 to PC8
PSW
Higher
register pairs
PC15 to PC8
SP + 1
SP SP + 2
SP SP + 2
SP + 2
SP SP + 3
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3.2.2 General-purpose registers
The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, and two 8-bit registers can be used in pairs as a 16-bit register (AX,
BC, DE, and HL).
General-purpose registers can be described in terms of functional names (X, A, C, B, E, D, L, H, AX, BC, DE, and
HL) and absolute names (R0 to R7 and RP0 to RP3).
Figure 3-14. General-Purpose Register Configuration
(a) Absolute names
16-bit processing
RP3
8-bit processing
R7
R6
R5
R4
RP2
RP1
RP0
R3
R2
R1
R0
15
0
7
0
(b) Functional names
16-bit processing
HL
8-bit processing
H
L
D
E
DE
BC
AX
B
C
A
X
15
0
7
0
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CHAPTER 3 CPU ARCHITECTURE
3.2.3 Special function registers (SFR)
Unlike a general-purpose register, each special function register has a special function.
SFRs are allocated in the 256-byte area FF00H to FFFFH.
A special function register can be manipulated, like a general-purpose register, using operation, transfer, and bit
manipulation instructions. The manipulatable bit unit (1, 8, or 16) differs depending on the special function register
type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describes a symbol reserved by assembler for the 1-bit manipulation instruction operand (sfr.bit). This
manipulation can also be specified by an address.
• 8-bit manipulation
Describes a symbol reserved by assembler for the 8-bit manipulation instruction operand (sfr). This
manipulation can also be specified by an address.
• 16-bit manipulation
Describes a symbol reserved by assembler for the 16-bit manipulation instruction operand. When addressing an
address, describe an even address.
Table 3-3 lists the special function registers. The meanings of the symbols in this table are as follows:
• Symbol
Indicates the address of the special function register. The symbols shown in this column are reserved words in
the assembler, and have been defined in the header file named “sfrbit.h” in the C compiler. Therefore, these
symbols can be used as instruction operands if an assembler or integrated debugger is used.
• R/W
Indicates whether the special function register in question can be read or written.
R/W: Read/write
R:
Read only
Write only
W:
• Manipulatable bit unit
Indicates the bit units (1, 8, 16) in which the special function register in question can be manipulated.
• After reset
Indicates the status of the special function register when the RESET signal is input.
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Table 3-3. Special Function Register List (1/2)
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulatable Bit Unit
After Reset
00H
1 Bit
8 Bits
16 Bits
√
√
√
√
√
√
√
−
−
−
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
FF00H
FF02H
FF04H
FF05H
FF06H
FF08H
FF09H
FF10H
Port 0
P0
P2
P4
P5
P6
P8
P9
R/W
Port 2
Port 4
Port 5
Port 6
R
Port 8
R/W
Port 9
Transmit shift register 00
Receive buffer register 00
A/D conversion result register 0
TXS00 SIO00
RXB00
W
R
FFH
−
Undefined
Note 1
Note 2
√
√
FF14H
FF15H
FF16H
FF17H
FF18H
FF19H
FF1AH
FF1BH
FF20H
FF22H
FF24H
FF25H
FF28H
FF29H
FF42H
FF48H
FF4AH
FF4EH
ADCR0
Notes 2, 3
Notes 2, 3
Notes 2, 3
−
−
−
−
−
−
√
√
√
16-bit compare register 50
16-bit timer counter 50
16-bit capture register 50
CR50L CR50
CR50H
TM50L TM50
TM50H
TCP50L TCP50
TCP50H
PM0
W
R
FFFFH
0000H
Undefined
FFH
√
√
√
√
√
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
−
−
Port mode register 0
R/W
Port mode register 2
PM2
Port mode register 4
PM4
Port mode register 5
PM5
Port mode register 8
PM8
Port mode register 9
PM9
Timer clock selection register 2
16-bit timer mode control register 50
Watch timer mode control register
Comparator mode register 0
TCL2
00H
TMC50
WTM
CMPRM0
Notes 1. If the A/D conversion result register is used for the 8-bit A/D converter (µPD789407A Subseries), it can
be accessed only in 8-bit units. In this case, it is considered to have been mapped at address FF15H.
If the register is used for the 10-bit A/D converter (µPD789417A Subseries), it can be accessed only in
16-bit units. If the µPD78F9418A is used as the flash memory version of the µPD789405A,
µPD789406A, or µPD789407A, 8-bit access is also possible, provided that the object file has been
assembled using the µPD789405A, µPD789406A, or µPD789407A.
2. 16-bit access is possible only in short direct addressing.
3. Although CR50, TM50, and TCP50 are 16-bit access dedicated registers, an 8-bit access is also
possible. When performing an 8-bit access, use direct addressing.
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CHAPTER 3 CPU ARCHITECTURE
Table 3-3. Special Function Register List (2/2)
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulatable Bit Unit
After Reset
1 Bit
8 Bits
16 Bits
−
−
√
−
−
√
−
−
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
−
−
FF50H
FF51H
FF53H
FF54H
FF55H
FF57H
FF58H
FF59H
FF5BH
FF70H
8-bit compare register 00
8-bit timer counter 00
CR00
W
R
Undefined
00H
TM00
8-bit timer mode control register 00
8-bit compare register 01
8-bit timer counter 01
TMC00
CR01
R/W
W
Undefined
00H
TM01
R
8-bit timer mode control register 01
8-bit compare register 02
8-bit timer counter 02
TMC01
CR02
R/W
W
Undefined
00H
TM02
R
8-bit timer mode control register 02
TMC02
ASIM00
R/W
Asynchronous serial interface mode register
00
√
√
−
FF71H
Asynchronous serial interface status register
00
ASIS00
R
√
−
√
√
√
√
√
√
√
√
√
−
−
√
√
√
√
√
√
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FF72H
FF73H
FF80H
FF84H
FFB0H
FFB1H
FFB2H
FFE0H
FFE1H
FFE4H
FFE5H
FFECH
FFEDH
FFF0H
FFF2H
FFF3H
FFF4H
FFF5H
FFF7H
FFF9H
FFFAH
Serial operation mode register 00
Baud rate generator control register 00
A/D converter mode register 0
A/D input selection register 0
LCD display mode register 0
LCD port selector 0
CSIM00
BRGC00
ADM0
ADS0
LCDM0
LPS0
LCDC0
IF0
R/W
LCD clock control register 0
Interrupt request flag register 0
Interrupt request flag register 1
Interrupt mask flag register 0
Interrupt mask flag register 1
External interrupt mode register 0
External interrupt mode register 1
Suboscillation mode register
Subclock control register
IF1
MK0
FFH
00H
MK1
INTM0
INTM1
SCKM
CSS
Pull-up resistor option register 1
Pull-up resistor option register 2
Key return mode register 00
Pull-up resistor option register 0
Watchdog timer mode register
PU1
PU2
KRM00
PU0
WDTM
OSTS
Oscillation stabilization time selection
register
04H
02H
√
√
−
FFFBH
Processor clock control register
PCC
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3.3 Instruction Address Addressing
An instruction address is determined by program counter (PC) contents. PC contents are normally incremented
(+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another
instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and
branched by the following addressing (for details of each instruction, refer to the 78K/0S Series Instructions User’s
Manual (U11047E)).
3.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the
start address of the following instruction is transferred to the program counter (PC) and branched. The
displacement value is treated as signed two’s complement data (−128 to +127) and bit 7 becomes a sign bit.
This means that information is relatively branched to a location between −128 and +127, from the start address
of the next instruction when relative addressing is used.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15
15
0
0
...
PC is the start address of
the next instruction of
a BR instruction.
PC
+
8
7
6
α
S
jdisp8
15
0
PC
When S = 0, α indicates all bits 0.
When S = 1, α indicates all bits 1.
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3.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed.
The CALL !addr16 and BR !addr16 instructions can be branched to any location in the memory space.
[Illustration]
In case of CALL !addr16 and BR !addr16 instructions
7
0
CALL or BR
Low addr.
High addr.
15
8 7
0
PC
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3.3.3 Table indirect addressing
[Function]
The table contents (branch destination address) of the particular location to be addressed by the lower 5-bit
immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and
branched.
This function is carried out when the CALLT [addr5] instruction is executed. The instruction enables a branch
to any location in the memory space by referring to the addresses stored in the memory table at 40H to 7FH.
[Illustration]
7
6
1
5
1
0
0
Instruction code
Effective address
0
ta4–0
15
8
0
7
0
6
1
5
1
0
0
0
0
0
0
0
0
0
7
Memory (table)
Low addr.
0
High addr.
Effective address + 1
15
8
7
0
PC
3.3.4 Register addressing
[Function]
The register pair (AX) contents to be specified with an instruction word are transferred to the program counter
(PC) and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
7
0
8
7
7
0
0
rp
A
X
15
PC
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3.4 Operand Address Addressing
The following methods are available to specify the register and memory (addressing) to undergo manipulation
during instruction execution.
3.4.1 Direct addressing
[Function]
The memory indicated with immediate data in an instruction word is directly addressed.
[Operand format]
Identifier
addr16
Description
Label or 16-bit immediate data
[Description example]
MOV A, !FE00H; When setting !addr16 to FE00H
Instruction code
0
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
0
Opcode
00H
FEH
[Illustration]
7
0
Opcode
addr16 (low)
addr16 (high)
Memory
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3.4.2 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
The fixed space is the 256-byte space FE20H to FF1FH where the addressing is applied. An internal high-
speed RAM and special function registers (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH,
respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the whole SFR area.
Ports that are frequently accessed in a program and a compare register of the timer/event counter are mapped
in this area, and these SFRs can be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,
bit 8 is set to 1. See [Illustration] below.
[Operand format]
Identifier
saddr
Description
Label or FE20H to FF1FH immediate data
saddrp
Label or FE20H to FF1FH immediate data (even address only)
[Description example]
MOV FE30H, #50H; When setting saddr to FE30H and the immediate data to 50H
Instruction code
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
1
0
0
0
0
0
1
0
0
Opcode
30H (saddr-offset)
50H (Immediate data)
[Illustration]
7
0
Opcode
saddr-offset
Short direct memory
15
1
8
0
Effective
address
1
1
1
1
1
1
α
When 8-bit immediate data is 20H to FFH, α = 0.
When 8-bit immediate data is 00H to 1FH, α = 1.
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3.4.3 Special function register (SFR) addressing
[Function]
A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction
word.
This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the
SFRs mapped at FF00H to FF1FH can be accessed using short direct addressing.
[Operand format]
Identifier
sfr
Description
Special function register name
[Description example]
MOV PM0, A; When selecting PM0 for sfr
Instruction code
1
0
1
1
1
0
0
0
0
1
0
1
0
1
0
0
[Illustration]
7
0
Opcode
sfr-offset
SFR
15
1
8 7
0
Effective
Address
1
1
1
1
1
1
1
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3.4.4 Register addressing
[Function]
In the register addressing mode, general-purpose registers are accessed as operands. The general-purpose
register to be accessed is specified by the register specification code or functional name in the instruction code.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
[Operand format]
Identifier
Description
r
X, A, C, B, E, D, L, H
AX, BC, DE, HL
rp
r and rp can be described using absolute names (R0 to R7 and RP0 to RP3) as well as functional names (X, A,
C, B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; When selecting the C register for r
Instruction code
0
0
0
0
0
1
0
0
1
0
0
1
1
0
0
1
Register specification code
INCW DE; When selecting the DE register pair for rp
Instruction code
1
0
0
0
1
0
0
0
Register specification code
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3.4.5 Register indirect addressing
[Function]
In the register indirect addressing mode, memory is manipulated according to the contents of a register pair
specified as an operand. The register pair to be accessed is specified by the register pair specification code in
an instruction code.
This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
Description
−
[DE], [HL]
[Description example]
MOV A, [DE]; When selecting register pair [DE]
Instruction code
0
0
1
0
1
0
1
1
[Illustration]
15
8
7
7
0
0
DE
D
E
Memory address
specified with
register pair DE.
Addressed memory
contents are
transferred.
7
0
A
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3.4.6 Based addressing
[Function]
8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is
used to address the memory. Addition is performed by expanding the offset data as a positive number to 16
bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
Description
−
[HL+byte]
[Description example]
MOV A, [HL+10H]; When setting byte to 10H
Instruction code
0
0
0
0
1
0
0
1
1
0
1
0
0
0
1
0
3.4.7 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call, and return
instructions are executed or the register is saved/restored upon generation of an interrupt request.
Stack addressing can only be used to access the internal high-speed RAM area.
[Description example]
In the case of PUSH DE
Instruction code
1
0
1
0
1
0
1
0
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CHAPTER 4 PORT FUNCTIONS
4.1 Function of Port
The µPD789407A and µPD789417A Subseries are provided with the ports shown in Figure 4-1, enabling various
methods of control.
Numerous other functions are provided that can be used in addition to the digital I/O port function. For more
information on these additional functions, see CHAPTER 2 PIN FUNCTIONS.
Figure 4-1. Port Types
P50
P53
P60
P00
P03
P20
Port 5
Port 0
Port 6
Port 2
P66
P80
P27
P40
Port 8
Port 4
P87
P90
P47
Port 9
P93
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Table 4-1. Port Functions
Pin Name
I/O
Function
After Reset
Input
Alternate Function
−
P00 to P03
I/O
I/O
Port 0.
4-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, use of an on-chip pull-up
resistor can be specified by setting pull-up resistor
option register 0 (PU0).
P20
Port 2.
Input
SCK/ASCK
SO/TxD
8-bit I/O port.
P21
Input/output can be specified in 1-bit units.
When used as an input port, use of an on-chip pull-up
resistor can be specified by setting pull-up resistor
option register 1 (PU1).
P22
SI/RxD
P23
CMPTOUT0/TO2
INTP0/TI0
INTP1/TI1
INTP2/TO5
INTP3/CPT5
KR0 to KR5
P24
P25
P26
P27
P40 to P45
I/O
I/O
Port 4.
Input
Input
8-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, use of an on-chip pull-up
resistor can be specified by setting pull-up resistor
option register 0 (PU0).
−
−
P46, P47
P50 to P53
Port 5.
4-bit N-ch open-drain I/O port.
Input/output can be specified in 1-bit units.
For a mask ROM version, use of an on-chip pull-up
resistor can be specified by the mask option.
P60
Input
I/O
Port 6.
Input
Input
ANI0/CMPIN0
ANI1/CMPREF0
ANI2 to ANI6
S27 to S20
7-bit input port.
P61
P62 to P66
P80 to P87
Port 8.
8-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, use of an on-chip pull-up
resistor can be specified by setting pull-up resistor
option register 2 (PU2).
P90 to P93
I/O
Port 9.
Input
S19 to S16
4-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, use of an on-chip pull-up
resistor can be specified by setting pull-up resistor
option register 2 (PU2).
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4.2 Configuration of Ports
The ports consist of the following hardware.
Table 4-2. Configuration of Port
Item
Control registers
Configuration
Port mode registers (PMm: m = 0, 2, 4, 5, 8, 9)
Pull-up resistor option registers (PUm: m = 0 to 2)
Ports
Total: 43 (input: 7, I/O: 36)
• Mask ROM version
Pull-up resistors
Total: 36 (software control: 32, mask option control: 4)
• Flash memory version
Total: 32 (software control only)
4.2.1 Port 0
This is a 4-bit I/O port with an output latch. Port 0 can be specified as input or output in 1-bit units by using port
mode register 0 (PM0). When the P00 to P03 pins are used as input port pins, on-chip pull-up resistors can be
connected in 4-bit units by setting pull-up resistor option register 0 (PU0).
Port 0 is set to input mode when the RESET signal is input.
Figure 4-2 shows a block diagram of port 0.
Figure 4-2. Block Diagram of P00 to P03
V
DD0
WRPU0
PU00
P-ch
RD
WRPORT
Output latch
(P00 to P03)
P00 to P03
WRPM
PM00 to PM03
PU0: Pull-up resistor option register 0
PM: Port mode register
RD: Port 0 read signal
WR: Port 0 write signal
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4.2.2 Port 2
This is an 8-bit I/O port with an output latch. Port 2 can be specified as input or output in 1-bit units by using port
mode register 2 (PM2). When using the P20 to P27 pins as input port pins, on-chip pull-up resistors can be connected
in 1-bit units by setting pull-up resistor option register 1 (PU1).
Port 2 is also used as a data I/O and clock I/O to and from the serial interface, timer I/O, and external interrupt.
Port 2 is set to input mode when the RESET signal is input.
Figures 4-3 through 4-7 show block diagrams of port 2.
Caution When using the pins of port 2 for the serial interface, the I/O or output latch must be set
according to the function to be used. For how to set the latches, see Table 13-2 Operation Mode
Settings of Serial Interface 00.
Figure 4-3. Block Diagram of P20
V
DD0
WRPU1
PU120
P-ch
Alternate
function
RD
WRPORT
Output latch
(P20)
P20/ASCK/
SCK
WRPM
PM20
Alternate
function
PU1: Pull-up resistor option register 1
PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal
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CHAPTER 4 PORT FUNCTIONS
Figure 4-4. Block Diagram of P21
V
DD0
WRPU1
PU121
P-ch
RD
WRPORT
Output latch
(P21)
P21/TxD/
SO
WRPM
PM21
Alternate
function
PU1: Pull-up resistor option register 1
PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal
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Figure 4-5. Block Diagram of P22 and P24
VDD0
WRPU1
PU122, PU124
P-ch
Alternate
function
RD
WRPORT
Output latch
(P22, P24)
P22/RxD/SI
P24/INTP0/TI0
WRPM
PM22, PM24
PU1: Pull-up resistor option register 1
PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal
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CHAPTER 4 PORT FUNCTIONS
Figure 4-6. Block Diagram of P23
VDD0
WRPU1
PU123
P-ch
RD
VDD0
WRPORT
Output latch
(P23)
P-ch
OPDR
P23/TO2
/CMPTOUT0
WRPM
N-ch
PM23
Alternate
function
Alternate
function
OPDR: Bit 1 of comparator mode register 0, selection of N-ch open-drain output
PU1:
PM:
RD:
Pull-up resistor option register 1
Port mode register
Port 2 read signal
WR:
Port 2 write signal
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Figure 4-7. Block Diagram of P25 to P27
V
DD0
WRPU1
PU125 to PU127
P-ch
Alternate
function
RD
WRPORT
Output latch
(P25 to P27)
P25/INTP1/TI1
P26/INTP2/TO5
P27/INTP3/CPT5
WRPM
PM25 to PM27
Alternate
function
PU1: Pull-up resistor option register 1
PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal
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4.2.3 Port 4
This is an 8-bit I/O port with an output latch. Port 4 can be specified as input or output in 1-bit units by using port
mode register 4 (PM4). When using the P40 to P47 pins as input port pins, on-chip pull-up resistors can be connected
in 8-bit units by setting pull-up resistor option register 0 (PU0).
Port 4 is also used as a key return input.
Port 4 is set to input mode when the RESET signal is input.
Figures 4-8 and 4-9 show block diagrams of port 4.
Caution When using the pins of port 4 as the key return, the key return mode register must be set
according to the function to be used. For how to set the registers, see 15.3 (6) Key return mode
register 00 (KRM00).
Figure 4-8. Block Diagram of P40 to P45
V
DD0
WRPU0
PU04
P-ch
RD
WRKRM
WRPORT
WRPM
KRM000 to
KRM005
Output latch
(P40 to P45)
P40/KR0 to
P45/KR5
PM40 to PM45
Alternate
function
KRM00: Key return mode register 00
PU0:
PM:
RD:
Pull-up resistor option register 0
Port mode register
Port 4 read signal
WR:
Port 4 write signal
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Figure 4-9. Block Diagram of P46 and P47
V
DD0
WRPU0
PU04
P-ch
RD
WRPORT
Output latch
(P46, P47)
P46, P47
WRPM
PM46, PM47
PU0: Pull-up resistor option register 0
PM: Port mode register
RD: Port 4 read signal
WR: Port 4 write signal
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CHAPTER 4 PORT FUNCTIONS
4.2.4 Port 5
This is a 4-bit N-ch open-drain I/O port with an output latch. Port 5 can be specified as input or output in 1-bit units
by using port mode register 5 (PM5). For a mask ROM version, whether a pull-up resistor is to be incorporated can be
specified by a mask option.
Port 5 is set to input mode when the RESET signal is input.
Figure 4-10 shows a block diagram of port 5.
Figure 4-10. Block Diagram of P50 to P53
V
DD0
RD
Mask option resistor
Mask ROM version only.
For the flash memory version,
a pull-up resistor is not
incorporated.
P50 to P53
WRPORT
Output latch
(P50 to P53)
N-ch
WRPM
PM50 to PM53
PM: Port mode register
RD: Port 5 read signal
WR: Port 5 write signal
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4.2.5 Port 6
This is a 7-bit input port.
Port 6 is also used as an analog input to the A/D converter or comparator input.
Port 6 is set to input mode when the RESET signal is input.
Figures 4-11 and 4-12 show block diagrams of port 6.
Figure 4-11. Block Diagram of P60 and P61
RD
+
P60/ANI0/CMPIN0
P61/ANI1/CMPREF0
A/D converter
–
VREF
Comparator
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CHAPTER 4 PORT FUNCTIONS
Figure 4-12. Block Diagram of P62 to P66
RD
P62/ANI2 to
P66/ANI6
+
–
A/D converter
VREF
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4.2.6 Port 8
This is an 8-bit I/O port with an output latch. Port 8 can be specified as input or output in 1-bit units by using port
mode register 8 (PM8). When using the P80 to P87 pins as input port pins, internal pull-up resistors can be connected
in 2-bit units by using pull-up resistor option register 2 (PU2).
Port 8 is also used to output segment signals for the LCD controller/driver.
Port 8 is set to input mode when the RESET signal is input.
Figure 4-13 shows a block diagram of port 8.
Figure 4-13. Block Diagram of P80 to P87
VDD0
WRPU2
PU28n
P-ch
RD
WRPORT
Output latch
(P8m)
WRPM
WRLPS
P80/S27 to P87/S20
PM8m
LPS0
Segment output
PU2:
PM:
RD:
Pull-up resistor option register 2
Port mode register
Port 8 read signal
WR:
Port 8 write signal
LPS0: LCD port selector 0
n = 0, 2, 4, 6, m = 0 to 7
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CHAPTER 4 PORT FUNCTIONS
4.2.7 Port 9
This is a 4-bit I/O port with an output latch. Port 9 can be specified as input or output in 1-bit units by using port
mode register 9 (PM9). When using the P90 to P93 pins as input port pins, on-chip pull-up resistors can be connected
in 2-bit units by using pull-up resistor option register 2 (PU2).
Port 9 is also used to output segment signals for the LCD controller/driver.
Port 9 is set to input mode when the RESET signal is input.
Figure 4-14 shows a block diagram of port 9.
Figure 4-14. Block Diagram of P90 to P93
V
DD0
WRPU2
PU29n
P-ch
RD
WRPORT
Output latch
(P9m)
WRPM
WRLPS
P90/S19 to P93/S16
PM9m
LPS0
Segment output
PU2:
PM:
RD:
Pull-up resistor option register 2
Port mode register
Port 9 read signal
WR:
Port 9 write signal
LPS0: LCD port selector 0
n = 0, 2, m = 0 to 3
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4.3 Registers Controlling Ports
The following two registers control the ports.
• Port mode registers (PM0, PM2, PM4, PM5, PM8, and PM9)
• Pull-up resistor option registers (PU0 to PU2)
(1) Port mode registers (PM0, PM2, PM4, PM5, PM8, and PM9)
These registers are used to set port input/output in 1-bit units.
The port mode registers are independently set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets these registers to FFH.
When port pins are used as alternate-function pins, set the port mode register and output latch according to
Table 4-3.
Caution As port 2 has an alternate function as the external interrupt input, when the port function
output mode is specified and the output level is changed, the interrupt request flag is set.
When the output mode is used, therefore, the interrupt mask flag should be set to 1
beforehand.
Table 4-3. Port Mode Register and Output Latch Settings When Using Alternate Functions
Pin Name
Alternate Function
Name
PMxx
Pxx
I/O
P23
CMPTOUT0
Output
0
0
1
1
1
1
1
0
1
1
1
0
0
0
0
x
x
x
x
x
0
x
x
x
0
0
TO2
Output
Input
P24
P25
P26
P27
INTP0
TI0
Input
INTP1
TI1
Input
Input
INTP2
TO5
Input
Output
Input
INTP3
CPT5
Input
P40 to P45Note KR0 to KR5
Input
P80 to P87
P90 to P93
S27 to S20
S19 to S16
Output
Output
Note Set key return mode register 00 (KRM00) to 1 when using the alternate function (see 15.3 (6) Key return
mode register 00 (KRM00)).
Caution When port 2 is used for the serial interface, the I/O or output latch must be set according to the
function used. For the setting method, see Table 13-2 Operation Mode Settings of Serial
Interface 00.
Remark x:
PMxx: Port mode register
Pxx: Port output latch
Don’t care
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Figure 4-15. Format of Port Mode Register
Symbol
PM0
7
1
6
1
5
1
4
1
3
2
1
0
Address
FF20H
After reset
FFH
R/W
R/W
PM03 PM02 PM01 PM00
PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20
FF22H
FF24H
FF25H
FF28H
FF29H
FFH
FFH
FFH
FFH
FFH
R/W
R/W
R/W
R/W
R/W
PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40
PM4
PM5
PM8
PM9
1
1
1
1
PM53 PM52 PM51 PM50
PM87 PM86 PM85 PM84 PM83 PM82 PM81 PM80
1
1
1
1
PM93 PM92 PM91 PM90
Pmn pin I/O mode selection
m = 0, 5, 9: n = 0 to 3
m = 2, 4, 8: n = 0 to 7
PMmn
0
1
Output mode (output buffer on)
Input mode (output buffer off)
(2) Pull-up resistor option registers (PU0 to PU2)
The pull-up resistor option registers (PU0 to PU2) set whether an on-chip pull-up resistor is used on each
port.
On a port specified by PU0 to PU2 to use an on-chip pull-up resistor, the pull-up resistor can be internally
used only for the bits set in the input mode. No on-chip pull-up resistors can be used for the bits set in the
output mode regardless of the setting of PU0 to PU2. This also applies when using the pins for alternate
functions.
PU0 to PU2 are set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PU0 to PU2 to 00H.
Figure 4-16. Format of Pull-Up Resistor Option Register 0
Symbol
PU0
7
0
6
0
5
0
<4>
3
0
2
0
1
0
<0>
Address
FFF7H
After reset
00H
R/W
R/W
PU04
PU00
Pm on-chip pull-up resistor selectionNote
(m = 0 or 4)
PU0m
0
1
On-chip pull-up resistor not used
On-chip pull-up resistor used
Note PU0 selects whether on-chip pull-up resistors are to be used in 8-bit units, except for port 0, for which on-
chip pull-up resistors can be used only for four bits (P00 to P03).
Caution Bits 1, 2, 3, 5, 6, and 7 must be fixed to 0.
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Figure 4-17. Format of Pull-Up Resistor Option Register 1
Symbol
PU1 PU127 PU126 PU125 PU124 PU123 PU122 PU121 PU120
<7> <6> <5> <4> <3> <2> <1> <0>
Address
FFF3H
After reset
00H
R/W
R/W
PU12m
P2 on-chip pull-up resistor selectionNote
(m = 0 to 7)
0
1
On-chip pull-up resistor not used
On-chip pull-up resistor used
Note PU1 selects whether on-chip pull-up resistors are to be used in 1-bit units.
Figure 4-18. Format of Pull-Up Resistor Option Register 2
Symbol
PU2
7
0
6
0
<5> <4> <3> <2> <1> <0>
PU292 PU290 PU286 PU284 PU282 PU280
Address
FFF4H
After reset
00H
R/W
R/W
PU2mn
Pm on-chip pull-up resistor selectionNote
(m = 8 or 9; n = 0, 2, 4, or 6)
On-chip pull-up resistor not used
On-chip pull-up resistor used
0
1
Note PU2 selects whether on-chip pull-up resistors are to be used in 2-bit units (bit n and bit n+1).
Caution Bits 6 and 7 must be fixed to 0.
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4.4 Operation of Ports
The operation of a port differs depending on whether the port is set in the input or output mode, as described
below.
4.4.1 Writing to I/O port
(1) In output mode
A value can be written to the output latch of a port by using a transfer instruction. The contents of the output
latch can be output from the pins of the port.
Once data is written to the output latch, it is retained until new data is written to the output latch.
(2) In input mode
A value can be written to the output latch by using a transfer instruction. However, the status of the port pin
is not changed because the output buffer is off.
Once data is written to the output latch, it is retained until new data is written to the output latch.
Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port.
However, this instruction accesses the port in 8-bit units. When this instruction is
executed to manipulate a bit of an I/O port, therefore, the contents of the output latch of the
pin that is set in the input mode and not subject to manipulation become undefined.
4.4.2 Reading from I/O port
(1) In output mode
The contents of the output latch can be read by using a transfer instruction. The contents of the output latch
are not changed.
(2) In input mode
The status of a pin can be read by using a transfer instruction. The contents of the output latch are not
changed.
4.4.3 Arithmetic operation of I/O port
(1) In output mode
An arithmetic operation can be performed on the contents of the output latch. The result of the operation is
written to the output latch. The contents of the output latch are output from the port pins.
Once data is written to the output latch, it is retained until new data is written to the output latch.
(2) In input mode
The contents of the output latch become undefined. However, the status of the pin is not changed because
the output buffer is off.
Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port.
However, this instruction accesses the port in 8-bit units. When this instruction is
executed to manipulate a bit of an I/O port, therefore, the contents of the output latch of the
pin that is set in the input mode and not subject to manipulation become undefined.
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5.1 Functions of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following two types of system clock oscillators are used.
• Main system clock oscillator
This circuit oscillates at 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting
the processor clock control register (PCC).
• Subsystem clock oscillator
This circuit oscillates at 32.768 kHz. Oscillation can be stopped by the suboscillation mode register (SCKM).
5.2 Configuration of Clock Generator
The clock generator consists of the following hardware.
Table 5-1. Configuration of Clock Generator
Item
Configuration
Control registers
Processor clock control register (PCC)
Suboscillation mode register (SCKM)
Subclock control register (CSS)
Oscillators
Main system clock oscillator
Subsystem clock oscillator
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Figure 5-1. Block Diagram of Clock Generator
Internal bus
FRC SCC Suboscillation mode register
(SCKM)
Subsystem
clock
oscillator
XT1
XT2
fXT
Watch timer
LCD controller/driver
Prescaler
1/2
Clock to
peripheral
hardware
fXT
2
X1
X2
Main system
clock
oscillator
Prescaler
fX
f
X
22
Wait
controller
Standby
controller
CPU clock
(fCPU
)
STOP
MCC PCC1
CLS CSS0
Processor clock
control register
(PCC)
Subclock control
register (CSS)
Internal bus
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5.3 Registers Controlling Clock Generator
The clock generator is controlled by the following registers.
• Processor clock control register (PCC)
• Suboscillation mode register (SCKM)
• Subclock control register (CSS)
(1) Processor clock control register (PCC)
PCC selects the CPU clock and sets the division ratio.
PCC is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PCC to 02H.
Figure 5-2. Format of Processor Clock Control Register
Symbol
7
6
0
5
0
4
0
3
0
2
0
1
0
0
Address
FFFBH
After reset
02H
R/W
R/W
PCC MCC
PCC1
MCC
Control of main system clock oscillator operation
0
1
Operation enabled
Operation disabled
Note
CSS0 PCC1
Selection of CPU clock (fCPU)
Minimum instruction execution time: 2/fCPU
fX = 5.0 MHz or fXT = 32.768 kHz operation
0
0
1
1
0
1
0
1
f
X
X
0.4
1.6
s
s
µ
µ
f
/22
122 s
µ
f
XT/2
Note The CPU clock is selected according to a combination of the PCC1 flag in the processor clock control
register (PCC) and the CSS0 flag in the subclock control register (CSS). See 5.3 (3) Subclock control
register (CSS).
Cautions 1. Bits 0 and 2 to 6 must be fixed to 0.
2. The MCC bit can be set only when the subsystem clock has been selected as the CPU clock.
Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
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(2) Suboscillation mode register (SCKM)
SCKM selects whether a feedback resistor is used for the subsystem clock, and controls the oscillation of the
clock.
SCKM is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets SCKM to 00H.
Figure 5-3. Format of Suboscillation Mode Register
Symbol
SCKM
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Address
FFF0H
After reset
00H
R/W
R/W
FRC SCC
FRC
Feedback resistor selectionNote
0
1
On-chip feedback resistor used
On-chip feedback resistor not used
SCC
Control of subsystem clock oscillator operation
0
1
Operation enabled
Operation disabled
Note The feedback resistor is necessary to adjust the bias point of the oscillation waveform to close to the mid
point of the supply voltage. Only when the subclock is not used, the power consumption in STOP mode
can be further reduced by setting FRC = 1.
Cautions 1. Bits 2 to 7 must be fixed to 0.
2. Do not set the SCC bit when an external clock pulse is input, because the XT2 pin is pulled
up to VDD0 or VDD1.
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(3) Subclock control register (CSS)
CSS specifies whether the main system or subsystem clock oscillator is to be selected. It also specifies how
the CPU clock operates.
CSS is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CSS to 00H.
Figure 5-4. Format of Subclock Control Register
Symbol
CSS
7
0
6
0
5
4
3
0
2
0
1
0
0
0
Address
FFF2H
After reset
00H
R/W
CLS CSS0
R/WNote
CLS
0
CPU clock operation status
Operation based on the output of the divided main system clock
Operation based on the subsystem clock
1
CSS0
Selection of main system or subsystem clock oscillator
0
1
Divided output from the main system clock oscillator
Output from the subsystem clock oscillator
Note Bit 5 is read only.
Caution Bits 0, 1, 2, 3, 6, and 7 must be fixed to 0.
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5.4 System Clock Oscillators
5.4.1 Main system clock oscillator
The main system clock oscillator is oscillated by a crystal or ceramic resonator (5.0 MHz TYP.) connected across
the X1 and X2 pins.
An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the
inverted signal to the X2 pin.
Figure 5-5 shows the external circuit of the main system clock oscillator.
Figure 5-5. External Circuit of Main System Clock Oscillator
(a) Crystal or ceramic oscillation
(b) External clock
External
clock
V
SS0, VSS
1
X1
X1
X2
X2
Crystal
or
ceramic resonator
Caution
When using the main system or subsystem clock oscillator, wire as follows in the area enclosed
by the broken lines in Figures 5-5 and 5-6 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS0 and VSS1.
Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
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5.4.2 Subsystem clock oscillator
The subsystem clock oscillator is oscillated by a crystal resonator (32.768 kHz TYP.) connected across the XT1
and XT2 pins.
An external clock can also be input to the circuit. In this case, input the clock signal to the XT1 pin, and input the
inverted signal to the XT2 pin.
Figure 5-6 shows the external circuit of the subsystem clock oscillator.
Figure 5-6. External Circuit of Subsystem Clock Oscillator
(a) Crystal oscillation
(b) External clock
External
clock
V
XT1
SS0,VSS1
XT1
32.768
kHz
XT2
XT2
Crystal resonator
Caution
When using the main system or subsystem clock oscillator, wire as follows in the area enclosed
by the broken lines in Figures 5-5 and 5-6 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS0 and VSS1.
Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
When using the subsystem clock oscillator, pay special attention because the subsystem clock
oscillator has low amplification to minimize current consumption.
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5.4.3 Examples of incorrect resonator connection
Figure 5-7 shows examples of incorrect resonator connection.
Figure 5-7. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring
(b) Crossed signal line
PORTn
(n = 0, 2, 4, 5, 6, 8, 9)
V
V
SS0
SS1
,
VSS0,
VSS1
X1
X2
X1
X2
(c) Wiring near high fluctuating current
(d) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
V
DD0, VDD1
Pmn
V
V
SS0
SS1
,
X1
X2
V
V
SS0
SS1
,
X1
X2
High current
A
B
C
High current
Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect resistors
to the XT2 side in series.
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Figure 5-7. Examples of Incorrect Resonator Connection (2/2)
(e) Signal is fetched
(f) Signal lines of main system clock and subsystem
clock are parallel and close together
V
V
SS0
,
V
V
SS0
SS1
,
X2
X1
XT2
XT1
SS1
X1
X2
XT2 is wired parallel to X1.
Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect resistors
to the XT2 side in series.
Caution If the X1 wire is parallel with the XT2 wire, crosstalk noise may occur between X1 and XT2,
resulting in a malfunction.
To avoid this, do not place the X1 and XT2 wires in parallel.
5.4.4 Divider
The divider divides the output of the main system clock oscillator (fX) to generate various clocks.
5.4.5 When no subsystem clock is used
If a subsystem clock is not necessary, for example, for low-power consumption operation or clock operation,
handle the XT1 and XT2 pins as follows:
XT1: Connect directly to VSS0 or VSS1
XT2: Leave open
In this case, however, a small current leaks via the on-chip feedback resistor in the subsystem clock oscillator
when the main system clock is stopped. To avoid this, set bit 1 (FRC) of the suboscillation mode register (SCKM) so
that the on-chip feedback resistor will not be used. Also in this case, handle the XT1 and XT2 pins as stated above.
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5.5 Operation of Clock Generator
The clock generator generates the following clocks and controls the operation modes of the CPU, such as the
standby mode.
• Main system clock
• Subsystem clock
fX
fXT
• CPU clock
fCPU
• Clock to peripheral hardware
The operation of the clock generator is determined by the processor clock control register (PCC), suboscillation
mode register (SCKM), and subclock control register (CSS), as follows.
(a) The slow mode (1.6 µs at 5.0 MHz operation) of the main system clock is selected when the RESET
signal is generated (PCC = 02H). While a low level is being input to the RESET pin, oscillation of the
main system clock is stopped.
(b) Three types of minimum instruction execution time (0.4 µs and 1.6 µs main system clock (at 5.0 MHz
operation), 122 µs subsystem clock (at 32.768 kHz operation)) can be selected by the PCC, SCKM, and
CSS settings.
(c) Two standby modes, STOP and HALT, can be used with the main system clock selected. In a system
where no subsystem clock is used, setting bit 1 (FRC) of SCKM so that the on-chip feedback resistor
cannot be used reduces current consumption in the STOP mode. In a system where a subsystem clock
is used, setting bit 0 of SCKM to 1 can cause the subsystem clock to stop oscillation.
(d) Bit 4 (CSS0) of CSS can be used to select the subsystem clock so that low current consumption
operation is used (at 122 µs, 32.768 kHz operation).
(e) With the subsystem clock selected, it is possible to cause the main system clock to stop oscillating by
setting bit 7 (MCC) of PCC. The HALT mode can be used, but the STOP mode cannot.
(f) The clock pulse for the peripheral hardware is generated by dividing the frequency of the main system
clock. The subsystem clock pulse is supplied to 8-bit timer 02, the watch timer, and the LCD
controller/driver only. As a result, 8-bit timer 02 (when watch timer output is selected for the count clock
when the subsystem clock is running) and the watch function can continue running even in the standby
mode. The other hardware stops when the main system clock stops, because it runs based on the main
system clock (except for external input clock pulses).
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5.6 Changing Setting of System Clock and CPU Clock
5.6.1 Time required for switching between system clock and CPU clock
The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit 4
(CSS0) of the subclock control register (CSS).
Actually, the specified clock is not selected immediately after the setting of PCC has been changed; the old clock
is used for the duration of several instructions after that (see Table 5-2).
Table 5-2. Maximum Time Required for Switching CPU Clock
Set Value Before Switching
Set Value After Switching
CSS0
PCC1
CSS0
0
PCC1
0
CSS0
0
PCC1
1
CSS0
1
PCC1
x
0
0
1
x
4 clocks
2 clocks
2fX/fXT clocks
(306 clocks)
2 clocks
2 clocks
fX/2fXT clocks
(76 clocks)
1
Remarks 1. Two clocks is the minimum instruction execution time of the CPU clock before switching.
2. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
3. x: Don’t care
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5.6.2 Switching between system clock and CPU clock
The following figure illustrates how the CPU clock and system clock are switched.
Figure 5-8. Switching Between System Clock and CPU Clock
VDD
RESET
Interrupt request signal
f
X
f
X
f
XT
f
X
System clock
CPU clock
Low-speed
operation
High-speed
operation
High-speed
operation
Subsystem clock
operation
Wait (6.55 ms: at 5.0 MHz operation)
Internal reset operation
<1> The CPU is reset when the RESET pin is made low on power application. Reset is released when the
RESET pin is later made high, and the main system clock starts oscillating. At this time, the oscillation
stabilization time (215/fX) is automatically secured.
After that, the CPU starts instruction execution at the low speed of the main system clock (1.6 µs at
5.0 MHz operation).
<2> After the time required for the VDD voltage to rise to the level at which the CPU can operate at the high speed
has elapsed, bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock
control register (CSS) are rewritten so that the high-speed operation can be selected.
<3> A drop of the VDD voltage is detected by an interrupt request signal. The clock is switched to the subsystem
clock (at this moment, the subsystem clock must be in the stable oscillation status).
<4> Recovery of the VDD voltage is detected by an interrupt request signal. Bit 7 (MCC) of PCC is set to 0, and
the main system clock starts oscillating. After the time required for the oscillation to stabilize has elapsed,
PCC1 and CSS0 are rewritten so that high-speed operation can be selected again.
Caution
When the main system clock is stopped and the device is operating on the subsystem
clock, wait until the oscillation stabilization time has been secured by the program before
switching back to the main system clock.
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CHAPTER 6 16-BIT TIMER 50
16-bit timer 50 references the free-running counter and provides functions such as timer interrupt and timer output.
In addition, the count value can be captured by a trigger pin.
6.1 Function of 16-Bit Timer 50
16-bit timer 50 has the following functions.
• Timer interrupt
• Timer output
• Count value capture
(1) Timer interrupt
An interrupt is generated when the count value and compare value match.
(2) Timer output
Timer output control is possible when the count value and compare value match.
(3) Count value capture
The count value of 16-bit timer counter 50 (TM50) is latched to the capture register in synchronization with
the capture trigger and retained.
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6.2 Configuration of 16-Bit Timer 50
16-bit timer 50 consists of the following hardware.
Table 6-1. Configuration of 16-Bit Timer 50
Item
Timer counter
Registers
Configuration
16 bits × 1 (TM50)
Compare register: 16 bits × 1 (CR50)
Capture register: 16 bits × 1 (TCP50)
Timer outputs
1 (TO5)
Control registers
16-bit timer mode control register 50 (TMC50)
Port mode register 2 (PM2)
Figure 6-1. Block Diagram of 16-Bit Timer 50
Internal bus
16-bit timer mode
control register 50
(TMC50)
P26
output latch
PM26
TOF50 CPT501 CPT500 TOC50 TCL501 TCL500 TOE50
TO5/P26/
INTP2
F/F
TOD50
16-bit compare register 50 (CR50)
16-bit timer mode
control register 50
Match
INTTM50
fX
OVF
16-bit timer counter 50 (TM50)
fX/25
CPT5/P27/
INTP3
Edge
detector
16-bit capture
register 50 (TCP50)
16-bit counter
read buffer
Internal bus
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(1) 16-bit compare register 50 (CR50)
This register compares the value set to CR50 with the count value of 16-bit timer counter 50 (TM50), and
when they match, generates an interrupt request (INTTM50).
CR50 is set using a 16-bit memory manipulation instruction. Values from 0000H to FFFFH can be set.
RESET input sets CR50 to FFFFH.
Cautions 1. Although this register is manipulated by a 16-bit memory manipulation instruction, an 8-
bit memory manipulation instruction can also be used. When manipulated by an 8-bit
memory manipulation instruction, the accessing method should be direct addressing.
2. When rewriting CR50 during a count operation, preset CR50 to interrupt disabled using
interrupt mask flag register 1 (MK1). Also, set the timer output data to inversion
disabled using 16-bit timer mode control register 50 (TMC50).
If CR50 is rewritten while interrupts are enabled, an interrupt request may be generated
at the time of the rewrite.
(2) 16-bit timer counter 50 (TM50)
This is a 16-bit register that counts count pulses.
TM50 is read using a 16-bit memory manipulation instruction.
TM50 is in free-running mode during count clock input.
RESET input sets TM50 to 0000H, after which it enters free-running mode again.
Cautions 1. The count value after releasing stop becomes undefined because the count operation is
executed during the oscillation stabilization time.
2. Although this register is manipulated by a 16-bit memory manipulation instruction, an 8-
bit memory manipulation instruction can also be used. When manipulated by an 8-bit
memory manipulation instruction, the accessing method should be direct addressing.
3. When manipulated by an 8-bit memory manipulation instruction, readout should be
performed in order from lower byte to higher byte and must be in pairs.
(3) 16-bit capture register 50 (TCP50)
This is a 16-bit register that captures the contents of 16-bit timer counter 50 (TM50).
TCP50 is set using a 16-bit memory manipulation instruction.
RESET input makes TCP50 undefined.
Caution Although this register is manipulated by a 16-bit memory manipulation instruction, an 8-bit
memory manipulation instruction can also be used. When manipulated by an 8-bit memory
manipulation instruction, the accessing method should be direct addressing.
(4) 16-bit counter read buffer
This buffer latches the counter value of 16-bit timer counter 50 (TM50) and retains the count value.
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CHAPTER 6 16-BIT TIMER 50
6.3 Registers Controlling 16-Bit Timer 50
The following two registers are used to control 16-bit timer 50.
• 16-bit timer mode control register 50 (TMC50)
• Port mode register 2 (PM2)
(1) 16-bit timer mode control register 50 (TMC50)
16-bit timer mode control register 50 (TMC50) controls the setting of the count clock, capture edge, etc.
TMC50 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets TMC50 to 00H.
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CHAPTER 6 16-BIT TIMER 50
Figure 6-2. Format of 16-Bit Timer Mode Control Register 50
7
<6>
5
4
3
2
1
<0>
Symbol
Address
FF48H
After reset
00H
R/W
TMC50 TOD50 TOF50 CPT501 CPT500 TOC50 TCL501 TCL500 TOE50
R/WNote 1
TOD50
Timer output data
0
1
Timer output is “0”
Timer output is “1”
TOF50
Overflow flag set
0
1
Clear by reset and software
Set by overflow of 16-bit timer
CPT501 CPT500
Capture edge selection
0
0
1
1
0
1
0
1
Capture operation disabled
Rising edge of CPT5
Falling edge of CPT5
Both edges of CPT5
TOC50
Timer output data inverse control
0
1
Inverse disabled
Inverse enabled
TCL501 TCL500
16-bit timer 50 count clock selection
0
0
0
1
f
X
X
(5.0 MHz)Note 2
f
/25 (156.3 kHz)Note 3
Other than
above
Setting prohibited
TOE50
16-bit timer 50 output control
0
1
Output disabled (port mode)
Output enabled
Notes 1. Bit 7 is read-only.
2. If the count clock is set to fX (TCL501 = 0, TCL500 = 0), the capture function cannot be used. When
reading, set the CPU clock to the main system clock high-speed mode (PCC1 = 0, CSS0 = 0) (see
Figure 5-2).
3. When reading, specify the main system clock as the CPU clock (PCC1 = 0, CSS0 = 0 or PCC1 = 1,
CSS0 = 0) (see Figure 5-2).
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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CHAPTER 6 16-BIT TIMER 50
(2) Port mode register 2 (PM2)
This register sets input/output of port 2 in 1-bit units.
To use the P26/INTP2/TO5 pin for timer output, set PM26 and the output latch of P26 to 0.
PM2 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM2 to FFH.
Figure 6-3. Format of Port Mode Register 2
7
6
5
4
3
2
1
0
Symbol
Address
FF22H
After reset
FFH
R/W
R/W
PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20
PM26
P26 pin I/O mode selection
0
1
Output mode (output buffer on)
Input mode (output buffer off)
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CHAPTER 6 16-BIT TIMER 50
6.4 Operation of 16-Bit Timer 50
6.4.1 Operation as timer interrupt
In the timer interrupt function, interrupts are repeatedly generated at the count value set to 16-bit compare register
50 (CR50) in advance at the interval set in TCL501 and TCL500.
To operate the 16-bit timer as a timer interrupt, the following settings are required.
• Set the count value to CR50
• Set 16-bit timer mode control register 50 (TMC50) as shown in Figure 6-4.
Figure 6-4. Settings of 16-Bit Timer Mode Control Register 50 for Timer Interrupt Operation
TOD50 TOF50 CPT501 CPT500 TOC50 TCL501 TCL500 TOE50
TMC50
–
0/1
0/1
0/1
0/1
0
0/1
0/1
Setting of count clock (see Table 6-2)
Caution If both the CPT501 flag and CPT500 flag are set to 0, the capture edge becomes operation
prohibited.
When the count value of 16-bit timer counter 50 (TM50) matches the value set to CR50, counting of TM50
continues and an interrupt request signal (INTTM50) is generated.
Table 6-2 shows the interval time, and Figure 6-5 shows the timing of the timer interrupt operation.
Caution Be sure to process as follows when rewriting CR50 during a count operation.
<1> Set interrupts to disabled (TMMK50 (bit 4 of interrupt mask flag register 1 (MK1)) = 1)
<2> Set the inversion control of timer output data to disabled (TOC50 = 0)
If CR50 is rewritten while interrupts are enabled, an interrupt request may be generated at the
time of rewrite.
Table 6-2. Interval Time of 16-Bit Timer 50
TCL501
TCL500
Count Clock
1/fX (0.2 µs)
Interval Time
216/fX (13.1 ms)
221/fX (419.4 ms)
0
0
0
1
25/fX (6.4 µs)
Other than above
Setting prohibited
Remarks 1. f : Main system clock oscillation frequency
X
2. The parenthesized values apply to operation at f = 5.0 MHz.
X
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CHAPTER 6 16-BIT TIMER 50
Figure 6-5. Timing of Timer Interrupt Operation
t
Count clock
TM50 count value
CR50
0000H
0001H
N
FFFFH 0000H 0001H
N
FFFFH
N
N
N
N
N
INTTM50
Interrupt acknowledged
Interrupt acknowledged
TO5
TOF50
Overflow flag set
Remark N = 0000H to FFFFH
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CHAPTER 6 16-BIT TIMER 50
6.4.2 Operation as timer output
Timer outputs are repeatedly generated at the count value set to 16-bit compare register 50 (CR50) in advance at
the interval set in TCL501 and TCL500.
To operate 16-bit timer as a timer output, the following settings are required.
• Set P26 to output mode (PM26 = 0)
• Set the output latch of P26 to 0
• Set the count value to CR50
• Set 16-bit timer mode control register 50 (TMC50) as shown in Figure 6-6
Figure 6-6. Settings of 16-Bit Timer Mode Control Register 50 for Timer Output Operation
TOD50 TOF50 CPT501 CPT500 TOC50 TCL501 TCL500 TOE50
–
0/1
0/1
0/1
1
0
0/1
TMC50
1
TO5 output enable
Setting of count clock (see Table 6-2)
Inverse enable of timer output data
Caution
If both the CPT501 flag and CPT500 flag are set to 0, the capture edge becomes operation
prohibited.
When the count value of 16-bit timer counter 50 (TM50) matches the value set in CR50, the output status of the
TO5/INTP2/P26 pin is inverted. This enables timer output. At that time, TM50 counting continues and an interrupt
request signal (INTTM50) is generated.
Figure 6-7 shows the timing of timer output (see Table 6-2 for the interval time of 16-bit timer 50).
Figure 6-7. Timer Output Timing
t
Count clock
TM50 count value
CR50
0000H
0001H
N
FFFFH 0000H 0001H
N
FFFFH
N
N
N
N
N
INTTM50
Interrupt acknowledged
Interrupt acknowledged
TO5Note
TOF50
Overflow flag set
Note The TO5 initial value becomes low level when output is enabled (TOE50 = 1).
Remark N = 0000H to FFFFH
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CHAPTER 6 16-BIT TIMER 50
6.4.3 Capture operation
In a capture operation, the count value of 16-bit timer counter 50 (TM50) is captured and latched to the capture
register in synchronization with a capture trigger.
Set as shown in Figure 6-8 to allow the 16-bit timer to start a capture operation.
Figure 6-8. Settings of 16-Bit Timer Mode Control Register 50 for Capture Operation
TOD50 TOF50 CPT501 CPT500 TOC50 TCL501 TCL500 TOE50
–
0/1
0/1
0/1
0/1
0
0/1
TMC50
0/1
Count clock selection
Capture edge selection (see Table 6-3)
16-bit capture register 50 (TCP50) starts a capture operation after the CPT5 capture trigger edge is defected, and
latches and retains the count value of 16-bit timer counter 50 (TM50). TCP50 fetches the count value within 2 clocks
and retains the count value until the next capture edge detection.
Table 6-3 and Figure 6-9 shows the settings of the capture edge and the capture operation timing, respectively.
Table 6-3. Settings of Capture Edge
CPT501
CPT500
Capture Edge Selection
Capture operation prohibited
0
0
1
1
0
1
0
1
CPT5 pin rising edge
CPT5 pin falling edge
CPT5 pin both edges
Caution Because TCP50 is rewritten when a capture trigger edge is detected during TCP50 read, disable
capture trigger edge detection during TCP50 read.
Figure 6-9. Capture Operation Timing (Both Edges of CPT5 Pin Are Specified)
Count clock
TM50
16-bit counter read buffer
TCP50
0000H 0001H
0000H 0001H
N
N
M – 1
M
M
Undefined
N
M
Capture start
Capture start
CPT5
Capture edge detection
Capture edge detection
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CHAPTER 6 16-BIT TIMER 50
6.4.4 16-bit timer counter 50 readout
The count value of 16-bit timer counter 50 (TM50) is read out by a 16-bit manipulation instruction.
TM50 readout is performed via a 16-bit counter read buffer. The 16-bit counter read buffer latches the TM50 count
value, the buffer operation is held pending at the CPU clock falling edge after the read signal of the TM50 lower byte
rises, and the count value is retained. The 16-bit counter read buffer value in the retention state can be read out as
the count value.
Cancellation of pending is performed at the CPU clock falling edge after the read signal of the TM50 higher byte
falls.
RESET input sets TM50 to 0000H and then to free-running mode again.
Figure 6-10 shows the timing of 16-bit timer counter 50 readout.
Cautions 1. The count value after releasing stop becomes undefined because the count operation is
executed during the oscillation stabilization time.
2. AIthough TM50 is manipulated by a 16-bit transfer instruction, 8-bit transfer instruction can
also be used.
When using an 8-bit transfer instruction, execute by direct addressing.
3. When using an 8-bit transfer instruction, execute in order from lower byte to higher byte in
pairs. If the only lower byte is read, the pending state of the 16-bit counter read buffer is not
canceled, and if the only higher byte is read, an undefined count value is read.
Figure 6-10. Readout Timing of 16-Bit Timer Counter 50
CPU clock
Count clock
TM50
16-bit counter read buffer
TM50 read signal
0000H
0000H
0001H
0001H
N
N + 1
N
Read signal latch
prohibited period
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CHAPTER 6 16-BIT TIMER 50
6.5 Cautions on Using 16-Bit Timer 50
6.5.1 Restrictions when rewriting 16-bit compare register 50
(1) Disable interrupts (TMMK50 = 1) and the inversion control of timer output (TOC50 = 0) before rewriting the
compare register (CR50).
If CR50 is rewritten with interrupts enabled, an interrupt request may be generated immediately.
(2) Depending on the timing of rewriting the compare register (CR50), the interval time may become twice as
long as the intended time. Similarly, a shorter waveform or twice-longer waveform than the intended timer
output waveform may be output.
To avoid this problem, rewrite the compare register using either of the following procedures.
<Countermeasure A> When rewriting using 8-bit access
<1> Disable interrupts (TMMK50 = 1) and the inversion control of timer output (TOC50 = 0).
<2> First rewrite the higher 1 byte of CR50 (16 bits).
<3> Then rewrite the lower 1 byte of CR50 (16 bits).
<4> Clear the interrupt request flag (TMIF50).
<5> Enable timer interrupts/timer output inversion after half a cycle or more of the count clock has elapsed from
the beginning of the interrupt.
<Program example A> (count clock = 32/fX, CPU clock = fX)
TM50_VCT:SET1 TMMK50
CLR1 TMC50.3
MOV A,#xxH
;
;
;
;
;
;
;
;
;
Disable timer interrupts (6 clocks)
Disable timer output inversion (6 clocks)
Set the rewrite value of higher byte (6 clocks)
Rewrite CR50 higher byte (8 clocks)
Set the rewrite value of lower byte (6 clocks)
Rewrite CR50 lower byte (8 clocks)
Clear interrupt request flag (6 clocks)
Enable timer interrupts (6 clocks)
MOV !0FF17H,A
MOV A,#yyH
Total: 16 clocks or
moreNote
MOV !0FF16H,A
CLR1 TMIF50
CLR1 TMMK50
SET1 TMC50.3
Enable timer output inversion
Note Because the INTTM50 signal becomes high level for half a cycle of the count clock after an interrupt is
generated, the output is inverted if TOC50 is set to 1 during this period.
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CHAPTER 6 16-BIT TIMER 50
<Countermeasure B> When rewriting using 16-bit access
<1> Disable interrupts (TMMK50 = 1) and the inversion control of timer output (TOC50 = 0).
<2> Rewrite CR50 (16 bits).
<3> Wait for one cycle or more of the count clock.
<4> Clear the interrupt request flag (TMIF50).
<5> Enable timer interrupts/timer output inversion.
<Program example B> (count clock = 32/fX, CPU clock = fX)
TM50_VCT
SET1 TMMK50
CLR1 TMC50.3
MOVW AX,#xxyyH
MOVW CR50,AX
NOP
;
;
;
;
Disable timer interrupts
Disable timer output inversion
Set the rewrite value of CR50
Rewrite CR50
NOP
:
;
16 NOP instructions (wait for 32/fX)Note
NOP
NOP
CLR1 TMIF50
CLR1 TMMK50
SET1 TMC50.3
;
;
;
Clear interrupt request flag
Enable timer interrupts
Enable timer output inversion
Note Clear the interrupt request flag (TMIF50) after waiting for one cycle or more of the count clock from the
instruction rewriting CR50 (MOVW CR50, AX).
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02
7.1 Function of 8-Bit Timer/Event Counters 00 to 02
8-bit timer/event counters 00 to 02 have the following functions.
• Interval timer (timer 00, timer 01, and timer 02)
• External event counter (timer 00 and timer 01 only)
• Square-wave output (timer 02 only)
The µPD789407A and µPD789417A Subseries are provided with two 8-bit timer/event counter channels (timer 00
and timer 01) and one 8-bit timer channel (timer 02). When reading the description of timer 02, timer/event counter
should be read as a timer.
(1) 8-bit interval timer
When the 8-bit timer/event counter is used as an interval timer, it generates an interrupt at an arbitrary time
interval set in advance.
Table 7-1. Interval Time of 8-Bit Timer/Event Counter 00
Minimum Interval Time
26/fX (12.8 µs)
29/fX (102.4 µs)
Maximum Interval Time
214/fX (3.28 ms)
217/fX (26.2 ms)
Resolution
Resolution
Resolution
26/fX (12.8 µs)
29/fX (102.4 µs)
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
Table 7-2. Interval Time of 8-Bit Timer/Event Counter 01
Minimum Interval Time
24/fX (3.2 µs)
28/fX (51.2 µs)
Maximum Interval Time
212/fX (819.2 µs)
24/fX (3.2 µs)
28/fX (51.2 µs)
216/fX (13.1 ms)
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
Table 7-3. Interval Time of 8-Bit Timer 02
Minimum Interval Time
23/fX (1.6 µs)
Maximum Interval Time
211/fX (409.6 µs)
23/fX (1.6 µs)
27/fX (25.6 µs)
1/fXT (30.5 µs)
27/fX (25.6 µs)
215/fX (6.55 ms)
28/fXT (7.81 ms)
1/fXT (30.5 µs)
Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02
(2) External event counter
The number of pulses of an externally input signal can be measured.
(3) Square-wave output
A square wave of any frequency can be output.
Table 7-4. Square-Wave Output Range of 8-Bit Timer 02
Minimum Pulse Width
23/fX (1.6 µs)
Maximum Pulse Width
211/fX (409.6 µs)
Resolution
23/fX (1.6 µs)
27/fX (25.6 µs)
1/fXT (30.5 µs)
27/fX (25.6 µs)
215/fX (6.55 ms)
28/fXT (7.81 ms)
1/fXT (30.5 µs)
Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
7.2 Configuration of 8-Bit Timer/Event Counters 00 to 02
8-bit timer/event counters 00 to 02 consist of the following hardware.
Table 7-5. Configuration of 8-Bit Timer/Event Counters 00 to 02
Item
Configuration
8 bits × 3 (TM00, TM01, and TM02)
Timer counter
Register
Compare register: 8 bits × 3 (CR00, CR01, and CR02)
Timer output
1 (TO2)
Control registers
8-bit timer mode control registers 00, 01, and 02 (TMC00, TMC01, and TMC02)
Port mode register 2 (PM2)
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02
Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter 00
Internal bus
8-bit compare register 00
(CR00)
Match
INTTM00
f
X
/26
/29
8-bit timer counter 00
(TM00)
f
X
Clear
TI0/P24/INTP0
Selector
2
TCE00 TCL001 TCL000
8-bit timer mode
control register 00 (TMC00)
Internal bus
Figure 7-2. Block Diagram of 8-Bit Timer/Event Counter 01
Internal bus
8-bit compare register 01
(CR01)
Match
INTTM01
f
f
X
/24
/28
X
8-bit timer counter 01 (TM01)
Clear
TI1/P25/INTP1
Selector
2
TCE01 TCL011 TCL010
8-bit timer mode
control register 01 (TMC01)
Internal bus
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02
Figure 7-3. Block Diagram of 8-Bit Timer 02
Internal bus
8-bit compare register 02
(CR02)
P23 output
latch
PM23
Match
INTTM02
f
f
X
/23
/27
8-bit timer counter 02
(TM02)
TO2/CMPTOUT0/
P23
X
F/F
Clear
Selector
f
XT
ComparatorNote
2
TCE02 TCL021 TCL020 TOE02
8-bit timer mode
control register 02 (TMC02)
Internal bus
Note See CHAPTER 12 COMPARATOR for details of the comparator.
(1) 8-bit compare register 0n (CR0n)
This is an 8-bit register that compares the value set to CR0n with the 8-bit timer counter 0n (TM0n) count
value, and if they match, an interrupt request (INTTM0n) is generated.
CR0n is set using an 8-bit memory manipulation instruction. Values from 00H to FFH can be set.
RESET input makes CR0n undefined.
Caution Be sure to stop the operation of the timer before rewriting CR0n. If CR0n is rewritten while
the timer is operation-enabled, an interrupt request match signal may be generated at the
time of the rewrite.
Remark n = 0 to 2
(2) 8-bit timer counter 0n (TM0n)
This is an 8-bit register that counts pulses.
TM0n is read using an 8-bit memory manipulation instruction.
RESET input sets TM0n to 00H.
Remark n = 0 to 2
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02
7.3 Registers Controlling 8-Bit Timer/Event Counters 00 to 02
The following two registers are used to control 8-bit timer/event counters 00 to 02.
• 8-bit timer mode control registers 00, 01, and 02 (TMC00, TMC01, and TMC02)
• Port mode register 2 (PM2)
(1) 8-bit timer mode control register 00 (TMC00)
TMC00 enables/stops operation of 8-bit timer counter 00 (TM00) and sets the count clock of TM00.
TMC00 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets TMC00 to 00H.
Figure 7-4. Format of 8-Bit Timer Mode Control Register 00
<7>
6
0
5
0
4
0
3
0
2
1
0
0
Symbol
Address
FF53H
After reset
00H
R/W
R/W
TMC00 TCE00
TCL001 TCL000
TCE00
Operation control of 8-bit timer counter 00
0
1
Operation stopped (TM00 is cleared to 00H)
Operation enabled
TCL001 TCL000
Count clock selection of 8-bit timer/event counter 00
/26 (
)
0
0
1
1
0
1
0
1
f
X
78.1 kHz
fX
/29 (9.76 kHz)
Rising edge of TI0
Falling edge of TI0
Caution Be sure to stop the operation of the timer before setting TMC00.
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02
(2) 8-bit timer mode control register 01 (TMC01)
TMC01 determines whether to enable or stop operation of 8-bit timer counter 01 (TM01) and specifies the
count clock for 8-bit timer/event counter 01.
TMC01 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets TMC01 to 00H.
Figure 7-5. Format of 8-Bit Timer Mode Control Register 01
Symbol <7>
6
0
5
0
4
0
3
0
2
1
0
0
Address
FF57H
After reset
00H
R/W
R/W
TMC01 TCE01
TCL011 TCL010
TCE01
Operation control of 8-bit timer counter 01
0
1
Operation stopped (TM01 is cleared to 00H)
Operation enabled
TCL011 TCL010
Count clock selection of 8-bit timer/event counter 01
/24 (312.5 kHz)
/28 (19.5 kHz)
0
0
1
1
0
1
0
1
f
X
X
f
Rising edge of TI1
Falling edge of TI1
Caution Be sure to stop the operation of the timer before setting TMC01.
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02
(3) 8-bit timer mode control register 02 (TMC02)
TMC02 determines whether to enable or stop operation of 8-bit timer counter 02 (TM02) and specifies the
count clock for 8-bit timer 02. It also controls the operation of the output controller.
TMC02 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets TMC02 to 00H.
Figure 7-6. Format of 8-Bit Timer Mode Control Register 02
Symbol <7>
6
0
5
0
4
0
3
0
2
1
<0>
Address
FF5BH
After reset
00H
R/W
R/W
TMC02 TCE02
TCL021 TCL020 TOE02
TCE02
Operation control of 8-bit timer counter 02
0
1
Operation stopped (TM02 is cleared to 00H)
Operation enabled
TCL021 TCL020
Count clock selection of 8-bit timer 02
/23 (625 kHz)
/27 (39.1 kHz)
0
0
1
1
0
1
0
1
f
f
f
X
X
XT (32.768 kHz)
Setting prohibited
TOE02
Output control of 8-bit timer 02
0
1
Output disabled (port mode)
Output enabled
Caution Be sure to stop the operation of the timer before setting TMC02.
Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02
(4) Port mode register 2 (PM2)
This register sets port 2 to input/output in 1-bit units.
When using the P23/COMPTOUT0/TO2 pin for timer output, set PM23 and the output latch of P23 to 0.
PM2 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM2 to FFH.
Figure 7-7. Format of Port Mode Register 2
7
6
5
4
3
2
1
0
Symbol
Address
FF22H
After reset
FFH
R/W
R/W
PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20
PM23
P23 pin I/O mode selection
0
1
Output mode (output buffer on)
Input mode (output buffer off)
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02
7.4 Operation of 8-Bit Timer/Event Counters 00 to 02
7.4.1 Operation as interval timer
The interval timer repeatedly generates an interrupt at time intervals specified by the count value set to 8-bit
compare registers 00, 01, and 02 (CR00, CR01, and CR02) in advance.
To operate the 8-bit timer/event counter as an interval timer, make the settings in the following order.
<1> Set 8-bit timer counter 0n (TM0n) to operation-disabled (TCE0n (bit 7 of 8-bit timer mode control register 0n
(TMC0n)) = 0)
<2> Select the count clock of the 8-bit timer/event counter (see Tables 7-6 to 7-8)
<3> Set the count value to CR0n
<4> Set TM0n to operation-enabled (TCE0n = 1)
When the count value of 8-bit timer counter 0n (TM0n) matches the value set to CR0n, the value of TM0n is
cleared to 00H and TM0n continues counting. At the same time, an interrupt request signal (INTTM0n) is generated.
Tables 7-6 through 7-8 show the interval time, and Figures 7-8 and 7-9 show the timing of interval timer operation.
Caution When the setting of the count clock using TMC0n and the setting of the TM0n to operation-
enable using an 8-bit memory manipulation instruction are performed at the same time, an error
of one clock or more may occur in the first cycle after the timer is started. Because of this,
when the 8-bit timer/event counter operates as an interval timer, be sure to make the settings in
the order described above.
Remark n = 0 to 2
Table 7-6. Interval Time of 8-Bit Timer/Event Counter 00
TCL001
TCL000
Minimum Interval Time
26/fX (12.8 µs)
Maximum Interval Time
Resolution
26/fX (12.8 µs)
0
0
1
1
0
1
0
1
214/fX (3.28 ms)
29/fX (102.4 µs)
TI0 input cycle
TI0 input cycle
29/fX (102.4 µs)
217/fX (26.2 ms)
28 × TI0 input cycle
28 × TI0 input cycle
TI0 input edge cycle
TI0 input edge cycle
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
Table 7-7. Interval Time of 8-Bit Timer/Event Counter 01
TCL011
TCL010
Minimum Interval Time
24/fX (3.2 µs)
Maximum Interval Time
212/fX (819.2 µs)
Resolution
24/fX (3.2 µs)
0
0
1
1
0
1
0
1
28/fX (51.2 µs)
TI1 input cycle
TI1 input cycle
28/fX (51.2 µs)
216/fX (13.1 ms)
28 × TI1 input cycle
28 × TI1 input cycle
TI1 input edge cycle
TI1 input edge cycle
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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Table 7-8. Interval Time of 8-Bit Timer 02
TCL021
TCL020
Minimum Interval Time
23/fX (1.6 µs)
Maximum Interval Time
211/fX (409.6 µs)
Resolution
23/fX (1.6 µs)
0
0
1
1
0
1
0
1
27/fX (25.6 µs)
27/fX (25.6 µs)
215/fX (6.55 ms)
28/fXT (7.81 ms)
1/fXT (30.5 µs)
Setting prohibited
1/fXT (30.5 µs)
Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
Figure 7-8. Interval Timer Operation Timing of Timer 00 and Timer 01
t
Count clock
TM0n count value
00
01
N
00
01
N
00
01
N
Clear
Clear
CR0n
N
N
N
N
TCE0n
Count start
INTTM0n
Interrupt acknowledged
Interval time
Interrupt acknowledged
Interval time
Interval time
Remarks 1. Interval time = (N + 1) × t where N = 00H to FFH
2. n = 0, 1
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02
Figure 7-9. Interval Timer Operation Timing of Timer 02
t
Count clock
TM02 count value
00
01
N
00
01
N
00
01
N
Clear
Clear
CR02
N
N
N
N
TCE02
Count start
INTTM02
Interrupt acknowledged
Interval time
Interrupt acknowledged
Interval time
TO2
Interval time
Remark Interval time = (N + 1) × t where N = 00H to FFH
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02
7.4.2 Operation as external event counter (timer 00 and timer 01 only)
The external event counter counts the number of external clock pulses input to the TI0/P24/INTP0 and
TI1/P25/INTP1 pins by using 8-bit timer counters 00 and 01 (TM00 and TM01).
To operate 8-bit timer/event counters 00 and 01 as an external event counter, make the settings in the following
order.
<1> Set P24 and P25 to input mode (PM24 = 1, PM25 = 1)
<2> Set 8-bit timer counter 0n (TM0n) to operation-disabled (TCE0n (bit 7 of 8-bit timer mode control register 0n
(TMC0n)) = 0)
<3> Specify the rising edge/falling edge of TIn (see Tables 7-6 and 7-7)
<4> Set the count value to CR0n
<5> Set TM0n to operation-enabled (TCE0n = 1)
Each time the valid edge specified by bit 1 (TCL0n0) of TMC0n is input, the value of 8-bit timer counter 0n (TM0n)
is incremented.
When the count value of TM0n matches the value set to CR0n, the value of TM0n is cleared to 00H and TM0n
continues counting. At the same time, an interrupt request signal (INTTM0n) is generated.
Figure 7-10 shows the timing of external event counter operation (with rising edge specified).
Caution When the setting of the count clock using TMC0n and the setting of the TM0n to operation-
enable using an 8-bit memory manipulation instruction are performed at the same time, an error
of one clock or more may occur in the first cycle after the timer is started. Because of this,
when the 8-bit timer/event counter operates as an external event counter, be sure to make the
settings in the order described above.
Remark n = 0, 1
Figure 7-10. External Event Counter Operation Timing (with Rising Edge Specified)
TIn pin input
TM0n count value
CR0n
00
01
02
03
04
05
N
N – 1
N
00
01
02
03
TCE0n
INTTM0n
Remarks 1. N = 00H to FFH
2. n = 0, 1
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02
7.4.3 Operation as square-wave output (timer 02 only)
The 8-bit timer can generate a square-wave output of any frequency at intervals specified by the count value
preset to 8-bit compare register 02 (CR02).
To operate 8-bit timer 02 as a square-wave output, make the settings in the following order.
<1> Set P23 to output mode (PM23 = 0), and set the output latch of P23 to 0
<2> Disable 8-bit timer counter 02 (TM02) operation (TCE02 (bit 0 of 8-bit timer mode control register 02
(TMC02)) = 1)
<3> Set the count clock of 8-bit timer 02 (see Table 7-9), and enable TO2 to output (TOE02 (bit 0 of TMC02) = 1)
<4> Set the count value to CR02
<5> Enable TM02 operation (TCE02 = 1)
When the count value of 8-bit timer counter 02 (TM02) matches the value set in CR02, the TO2/P23/CMPTOUT0
pin output is inverted. Through application of this mechanism, square waves of any frequency can be output. As
soon as a match occurs, the TM02 value is cleared to 00H, then counting continues count and an interrupt request
signal (INTTM02) is generated.
Setting bit 7 of TMC02 (TCE02) to 0 clears the square-wave output to 0.
Table 7-9 lists the square-wave output range, and Figure 7-11 shows the timing of square-wave output.
Caution When the setting of the count clock using TMC02 and the setting of the TM02 to operation-
enable using an 8-bit memory manipulation instruction are performed at the same time, an error
of one clock or more may occur in the first cycle after the timer is started. Because of this,
when the 8-bit timer operates as a square-wave output, be sure to make the settings in the order
described above.
Table 7-9. Square-Wave Output Range of 8-Bit Timer 02
TCL021
TCL020
Minimum Pulse Width
23/fX (1.6 µs)
Maximum Pulse Width
211/fX (409.6 µs)
Resolution
23/fX (1.6 µs)
0
0
1
1
0
1
0
1
27/fX (25.6 µs)
27/fX (25.6 µs)
215/fX (6.55 ms)
28/fXT (7.81 ms)
1/fXT (30.5 µs)
Setting prohibited
1/fXT (30.5 µs)
Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
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Figure 7-11. Square-Wave Output Timing
Count clock
TM02 count value
00
01
N
00
01
N
00
01
N
Clear
Clear
CR02
N
N
N
N
TCE02
Count start
INTTM02
Interrupt acknowledged
Interrupt acknowledged
TO2Note
Note The initial value of TO2 when output is enabled (TOE02 = 1) becomes low level.
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02
7.5 Cautions on Using 8-Bit Timer/Event Counters 00 to 02
(1) Error on starting timer
An error of up to 1 clock occurs after the timer has been started until a match signal is generated. This is
because 8-bit timer counters 00, 01, and 02 (TM00, TM01, and TM02) are started asynchronous to the count
pulse.
Figure 7-12. Start Timing of 8-Bit Timer Counters 00, 01, and 02
Count pulse
TM00, TM01, TM02
count value
00H
01H
02H
03H
04H
Timer starts
(2) Setting of 8-bit compare register
8-bit compare registers 00, 01, and 02 (CR00, CR01, and CR02) can be set to 00H.
Therefore, one pulse can be counted when an 8-bit timer/event counter operates as an event counter.
Figure 7-13. External Event Counter Operation Timing
TI0, TI1 input
CR00, CR01
00H
00H
00H
00H
00H
TM00, TM01
count value
Interrupt request flag
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CHAPTER 8 WATCH TIMER
8.1 Functions of Watch Timer
The watch timer has the following functions.
• Watch timer
• Interval timer
The watch and interval timers can be used at the same time.
Figure 8-1 is a block diagram of the watch timer.
Figure 8-1. Block Diagram of Watch Timer
Clear
f
/27
X
5-bit counter
Clear
INTWT
INTWTI
9-bit prescaler
f
W
f
W
f
W
f
W
f
W
f
W
f
W
29
24 25 26 27 28
f
XT
WTM7 WTM6 WTM5 WTM4 WTM1 WTM0
Watch timer mode
control register (WTM)
Internal bus
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CHAPTER 8 WATCH TIMER
(1) Watch timer
The 4.19 MHz main system clock or 32.768 kHz subsystem clock is used to issue an interrupt request
(INTWT) at 0.5-second intervals.
Caution When the main system clock is operating at 5.0 MHz, it cannot be used to generate a
0.5-second interval. In this case, the subsystem clock, which operates at 32.768 kHz,
should be used instead.
(2) Interval timer
The interval timer is used to generate an interrupt request (INTWT) at specified intervals.
Table 8-1. Interval Time of Interval Timer
Interval
Operation at fX = 5.0 MHz
409.6 µs
Operation at fX = 4.19 MHz
Operation at fXT = 32.768 kHz
24 × 1/fW
25 × 1/fW
26 × 1/fW
27 × 1/fW
28 × 1/fW
29 × 1/fW
489 µs
488 µs
819.2 µs
978 µs
977 µs
1.64 ms
1.96 ms
3.91 ms
7.82 ms
15.6 ms
1.95 ms
3.91 ms
7.81 ms
15.6 ms
3.28 ms
6.55 ms
13.1 ms
Remark fW: Watch timer clock frequency (fX/27 or fXT)
fX: Main system clock oscillation frequency
fXT: Subsystem clock oscillation frequency
8.2 Configuration of Watch Timer
The watch timer consists of the following hardware.
Table 8-2. Configuration of Watch Timer
Item
Counter
Configuration
5 bits × 1
9 bits × 1
Prescaler
Control register
Watch timer mode control register (WTM)
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CHAPTER 8 WATCH TIMER
8.3 Register Controlling Watch Timer
The watch timer mode control register (WTM) is used to control the watch timer.
•
Watch timer mode control register (WTM)
WTM selects a count clock for the watch timer and specifies whether to enable operation of the timer. It also
specifies the prescaler interval and how the 5-bit counter is controlled.
WTM is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets WTM to 00H.
Figure 8-2. Format of Watch Timer Mode Control Register
Symbol
7
6
5
4
3
0
2
0
1
0
Address
FF4AH
After reset
00H
R/W
R/W
WTM WTM7 WTM6 WTM5 WTM4
WTM1 WTM0
WTM7
Watch timer count clock selection
7 (39.1 kHz)
0
1
f
X
/2
f
XT (32.768 kHz)
WTM6 WTM5 WTM4
Prescaler interval selection
24/f
25/f
26/f
27/f
28/f
29/f
W
W
W
W
W
W
(488
(977
µ
µ
s)
s)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
(1.95 ms)
(3.91 ms)
(7.81 ms)
(15.6 ms)
Other than above
Setting prohibited
WTM1
Control of 5-bit counter operation
0
1
Cleared after stop
Started
WTM0
Watch timer operation
0
1
Operation stopped (both prescaler and timer cleared)
Operation enabled
Remarks 1. fW: Watch timer clock frequency (fX/27 or fXT)
2. fX: Main system clock oscillation frequency
3. fXT: Subsystem clock oscillation frequency
4. The parenthesized values apply to operation at fW = 32.768 kHz.
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CHAPTER 8 WATCH TIMER
8.4 Operation of Watch Timer
8.4.1 Operation as watch timer
The main system clock (4.19 MHz) or subsystem clock (32.768 kHz) is used as a watch timer that generates
interrupts at 0.5-second intervals.
By setting bits 0 and 1 (WTM0 and WTM1) of the watch timer mode control register (WTM) to 1, the watch timer
starts counting. By setting them to 0, the 5-bit counter is cleared and the watch timer stops counting.
When the interval timer also operates at the same time by setting WTM1 to 0, only the watch timer can be started
from 0 seconds. However, an error of up to 29 × 1/fW seconds may occur for the first overflow of the watch timer
(INTWT) after a 0-second start, because the 9-bit prescaler is not cleared in this case.
8.4.2 Operation as interval timer
The interval timer is used to repeatedly generate an interrupt request at the interval specified by a preset count
value.
The interval time can be selected by bits 4 to 6 (WTM4 to WTM6) of the watch timer mode control register (WTM).
Table 8-3. Interval Time of Interval Timer
WTM6
WTM5
WTM4
Interval
Operation at
fX = 5.0 MHz
Operation at
Operation at
fX = 4.19 MHz
fXT = 32.768 kHz
24 × 1/fW
409.6 µs
489 µs
488 µs
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
25 × 1/fW
819.2 µs
1.64 ms
3.28 ms
6.55 ms
13.1 ms
978 µs
977 µs
26 × 1/fW
1.96 ms
3.91 ms
7.82 ms
15.6 ms
1.95 ms
3.91 ms
7.81 ms
15.6 ms
27 × 1/fW
28 × 1/fW
29 × 1/fW
Other than above
Setting prohibited
Remark fX: Main system clock oscillation frequency
fXT: Subsystem clock oscillation frequency
fW: Watch timer clock frequency
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Figure 8-3. Watch Timer/Interval Timer Operation Timing
5-bit counter
0H
Overflow
Start
Overflow
Count clock
/29
fW
Watch timer
interrupt
INTWT
Watch timer interrupt time (0.5 s)
Watch timer interrupt time (0.5 s)
Interval timer
interrupt
INTWTI
Interval
T
timer (T)
Remark fW: Watch timer clock frequency
The parenthesized values apply to operation at fW = 32.768 kHz.
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CHAPTER 9 WATCHDOG TIMER
9.1 Functions of Watchdog Timer
The watchdog timer has the following functions.
• Watchdog timer
• Interval timer
Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode
register (WDTM).
(1) Watchdog timer
The watchdog timer is used to detect an inadvertent program loop. When the program loop is detected, a
non-maskable interrupt or the RESET signal can be generated.
Table 9-1. Program Loop Detection Time of Watchdog Timer
Program Loop Detection Time
Operation at fX = 5.0 MHz
410 µs
211 × 1/fX
213 × 1/fX
215 × 1/fX
217 × 1/fX
1.64 ms
6.55 ms
26.2 ms
fX: Main system clock oscillation frequency
(2) Interval timer
The interval timer generates an interrupt at any intervals set in advance.
Table 9-2. Interval Time
Interval Time
Operation at fX = 5.0 MHz
211 × 1/fX
213 × 1/fX
215 × 1/fX
217 × 1/fX
410 µs
1.64 ms
6.55 ms
26.2 ms
fX: Main system clock oscillation frequency
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CHAPTER 9 WATCHDOG TIMER
9.2 Configuration of Watchdog Timer
The watchdog timer consists of the following hardware.
Table 9-3. Configuration of Watchdog Timer
Item
Configuration
Control registers
Timer clock selection register 2 (TCL2)
Watchdog timer mode register (WDTM)
Figure 9-1. Block Diagram of Watchdog Timer
Internal bus
f
X
24
TMMK4
Prescaler
f
X
26
f
X
28
f
X
210
INTWDT
maskable
TMIF4
interrupt request
7-bit counter
Clear
Controller
RESET
INTWDT
non-maskable
interrupt request
3
TCL22 TCL21 TCL20
RUN WDTM4 WDTM3
Timer clock selection register 2
(TCL2)
Watchdog timer mode register
(WDTM)
Internal bus
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CHAPTER 9 WATCHDOG TIMER
9.3 Registers Controlling Watchdog Timer
The following two registers are used to control the watchdog timer.
• Timer clock selection register 2 (TCL2)
• Watchdog timer mode register (WDTM)
(1) Timer clock selection register 2 (TCL2)
This register sets the watchdog timer count clock.
TCL2 is set using an 8-bit memory manipulation instruction.
RESET input sets TCL2 to 00H.
Figure 9-2. Format of Timer Clock Selection Register 2
Symbol
TCL2
7
0
6
0
5
0
4
0
3
0
2
1
0
Address
FF42H
After reset
00H
R/W
R/W
TCL22 TCL21TCL20
Watchdog timer count clock selection
Interval time
TCL22 TCL21 TCL20
fX/24
211/fX
(410 µs)
0
0
1
1
0
1
0
1
0
0
0
0
(312.5 kHz)
(78.1 kHz)
(19.5 kHz)
(4.88 kHz)
fX/26
fX/28
fX/210
213/fX
215/fX
217/fX
(1.64 ms)
(6.55 ms)
(26.2 ms)
Other than above Setting prohibited
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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(2) Watchdog timer mode register (WDTM)
This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog
timer.
WDTM is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets WDTM to 00H.
Figure 9-3. Format of Watchdog Timer Mode Register
<7>
6
0
5
0
4
3
2
0
1
0
0
0
Address
FFF9H
After reset
00H
R/W
R/W
Symbol
WDTM RUN
WDTM4 WDTM3
Selection of operation of watchdog timerNote 1
RUN
0
1
Stop counting
Clear counter and start counting
Selection of operation mode of watchdog timerNote 2
WDTM4 WDTM3
0
0
1
1
0
1
0
1
Operation stopped
Interval timer mode (overflow and maskable interrupt occur)Note 3
Watchdog timer mode 1 (overflow and non-maskable interrupt occur)
Watchdog timer mode 2 (overflow occurs and reset operation started)
Notes 1. Once RUN has been set to (1), it cannot be cleared to (0) by software. Therefore, when counting is
started, it cannot be stopped by any means other than RESET input.
2. Once WDTM3 and WDTM4 have been set to (1), they cannot be cleared to (0) by software.
3. The watchdog timer starts operation as an interval timer when RUN is set to 1.
Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up to
0.8% shorter than the time set by timer clock selection register 2 (TCL2).
2. In watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming that TMIF4 (bit 0 of interrupt
request flag register 0 (IF0)) is set to 0. While TMIF4 is 1, a non-maskable interrupt is
generated upon write completion if watchdog timer mode 1 or 2 is selected.
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CHAPTER 9 WATCHDOG TIMER
9.4 Operation of Watchdog Timer
9.4.1 Operation as watchdog timer
The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register
(WDTM) is set to 1.
The count clock (program loop detection time interval) of the watchdog timer can be selected by bits 0 to 2 (TCL20
to TCL22) of timer clock selection register 2 (TCL2). By setting bit 7 (RUN) of WDTM to 1, the watchdog timer is
started. Set RUN to 1 within the set program loop detection time interval after the watchdog timer has been started.
By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and the program
loop detection time is exceeded, the system is reset or a non-maskable interrupt is generated by the value of bit 3
(WDTM3) of WDTM.
The watchdog timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1
before entering the STOP mode to clear the watchdog timer, and then execute the STOP instruction.
Cautions 1. The actual program loop detection time may be up to 0.8% shorter than the set time.
2. When the subsystem clock is selected as the CPU clock, the watchdog timer stops counting.
Table 9-4. Program Loop Detection Time of Watchdog Timer
TCL22
TCL21
TCL20
Program Loop Detection Time
211 × 1/fX
Operation at fX = 5.0 MHz
410 µs
0
0
1
1
0
1
0
1
0
0
0
0
213 × 1/fX
215 × 1/fX
217 × 1/fX
1.64 ms
6.55 ms
26.2 ms
fX: Main system clock oscillation frequency
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CHAPTER 9 WATCHDOG TIMER
9.4.2 Operation as interval timer
When bit 4 (WDTM4) and bit 3 (WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1,
respectively, the watchdog timer also operates as an interval timer that repeatedly generates an interrupt at time
intervals specified by a preset count value.
Select the count clock (or interval time) by setting bits 0 to 2 (TCL20 to TCL22) of timer clock selection register 2
(TCL2). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set to 1.
In the interval timer mode, the interrupt mask flag (TMMK4) is valid, and a maskable interrupt (INTWDT) can be
generated. The priority of INTWDT is set as the highest of all the maskable interrupts.
The interval timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1
before entering the STOP mode to clear the interval timer, and then execute the STOP instruction.
Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when the watchdog timer mode is selected), the
interval timer mode is not set, unless the RESET signal is input.
2. The interval time immediately after the setting by WDTM may be up to 0.8% shorter than the
set time.
Table 9-5. Interval Time of Interval Timer
TCL22
TCL21
TCL20
Interval Time
Operation at fX = 5.0 MHz
410 µs
211 × 1/fX
213 × 1/fX
215 × 1/fX
217 × 1/fX
0
0
1
1
0
1
0
1
0
0
0
0
1.64 ms
6.55 ms
26.2 ms
fX: Main system clock oscillation frequency
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CHAPTER 10 8-BIT A/D CONVERTER (µPD789407A SUBSERIES)
10.1 Function of 8-Bit A/D Converter
The 8-bit A/D converter converts input analog voltages to digital signals with an 8-bit resolution. It can control up
to seven analog input channels (ANI0 to ANI6).
A/D conversion can be started only by software.
One of analog inputs ANI0 to ANI6 is selected for A/D conversion. A/D conversion is performed repeatedly, with
an interrupt request (INTAD0) being issued each time an A/D conversion is completed.
10.2 Configuration of 8-Bit A/D Converter
The 8-bit A/D converter consists of the following hardware.
Table 10-1. Configuration of 8-Bit A/D Converter
Item
Analog inputs
Registers
Configuration
7 channels (ANI0 to ANI6)
Successive approximation register (SAR)
A/D conversion result register 0 (ADCR0)
Control registers
A/D converter mode register 0 (ADM0)
A/D input selection register 0 (ADS0)
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Figure 10-1. Block Diagram of 8-Bit A/D Converter
Series resistor string
AVDD
AVREF
P-ch
ANI0/P60
ANI1/P61
ANI2/P62
ANI3/P63
ANI4/P64
ANI5/P65
ANI6/P66
Sample & hold circuit
Voltage comparator
AVSS
AVSS
Successive
approximation
register (SAR)
Controller
INTAD0
A/D conversion result
register 0 (ADCR0)
3
ADS02 ADS01 ADS00
ADCS0 FR02 FR01 FR00
A/D input selection
register 0 (ADS0)
A/D converter mode
register 0 (ADM0)
Internal bus
(1) Successive approximation register (SAR)
The SAR receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison
voltage), received from the series resistor string, starting from the most significant bit (MSB).
Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D
conversion, the SAR sends its contents to A/D conversion result register 0 (ADCR0).
(2) A/D conversion result register 0 (ADCR0)
ADCR0 holds the result of A/D conversion. Each time A/D conversion ends, the conversion result received
from the successive approximation register is loaded into ADCR0, which is an 8-bit register that holds the
result of A/D conversion.
ADCR0 is read using an 8-bit memory manipulation instruction.
RESET input makes ADCR0 undefined.
(3) Sample & hold circuit
The sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends
them to the voltage comparator. The sampled analog input voltage is held during A/D conversion.
(4) Voltage comparator
The voltage comparator compares an analog input with the voltage output by the series resistor string.
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CHAPTER 10 8-BIT A/D CONVERTER (µPD789407A SUBSERIES)
(5) Series resistor string
The series resistor string is configured between AVREF and AVSS. It generates the reference voltages against
which analog inputs are compared.
(6) ANI0 to ANI6 pins
The ANI0 to ANI6 pins are analog input pins for the seven-channel A/D converter. They are used to receive
the analog signals to be subject to A/D conversion.
Caution Do not supply the ANI0 to ANI6 pins with voltages that fall outside the rated range. If a
voltage greater than AVREF or less than AVSS (even if within the absolute maximum rating) is
supplied to any of these pins, the conversion value for the corresponding channel will be
undefined. Furthermore, the conversion values for the other channels may also be
affected.
(7) AVREF pin
The AVREF pin is a reference voltage pin for the A/D converter.
Signals received at the ANI0 to ANI6 pins are converted to digital signals based on the voltage across the
AVREF and AVSS pins.
(8) AVSS pin
The AVSS pin is a ground potential pin for the A/D converter. This pin must be held at the same potential as
the VSS0 pin, even while the A/D converter is not being used.
(9) AVDD pin
The AVDD pin is an analog power supply pin for the A/D converter. This pin must be held at the same
potential as the VDD0 pin, even while the A/D converter is not being used.
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10.3 Registers Controlling 8-Bit A/D Converter
The following two registers are used to control the 8-bit A/D converter.
• A/D converter mode register 0 (ADM0)
• A/D input selection register 0 (ADS0)
(1) A/D converter mode register 0 (ADM0)
ADM0 specifies the conversion time for analog inputs. It also specifies whether to enable conversion.
ADM0 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ADM0 to 00H.
Figure 10-2. Format of A/D Converter Mode Register 0
Symbol <7>
6
0
5
4
3
2
0
1
0
0
0
Address
FF80H
After reset
00H
R/W
R/W
ADM0 ADCS0
FR02 FR01 FR00
ADCS0
A/D conversion control
0
1
Conversion stopped
Conversion enabled
FR02 FR01 FR00
A/D conversion time selectionNote 1
0
0
0
1
1
1
0
0
1
0
0
1
0
1
0
0
1
0
144/fx (28.8
120/fx (24
µ
s)
µ
s)
96/fx
72/fx
60/fx
48/fx
(19.2
(14.4
µ
µ
s)
s)
(Setting prohibitedNote 2
(Setting prohibitedNote 2
)
)
Other than above
Setting prohibited
Notes 1. The specifications of FR02, FR01, and FR00 must be such that the A/D conversion time is at least
14 µs.
2. These bit combinations must not be used, as the A/D conversion time will fall below 14 µs.
Cautions 1. The result of conversion performed immediately after bit 7 (ADCS0) is set is undefined.
2. The result of conversion performed after ADCS0 is cleared may be undefined (see 10.5 (5)
Timing that makes the A/D conversion result undefined for details).
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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CHAPTER 10 8-BIT A/D CONVERTER (µPD789407A SUBSERIES)
(2) A/D input selection register 0 (ADS0)
ADS0 register specifies the port used to input the analog voltages to be converted to a digital signal.
ADS0 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ADS0 to 00H.
Figure 10-3. Format of A/D Input Selection Register 0
Symbol
ADS0
7
0
6
0
5
0
4
0
3
0
2
1
0
Address
FF84H
After reset
00H
R/W
R/W
ADS02 ADS01 ADS00
Analog input channel specification
ADS02 ADS01 ADS00
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Setting prohibited
Caution Bits 3 to 7 must be fixed to 0.
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10.4 Operation of 8-Bit A/D Converter
10.4.1 Basic operation of 8-bit A/D converter
<1> Select a channel for A/D conversion, using A/D input selection register 0 (ADS0).
<2> The voltage supplied to the selected analog input channel is sampled using the sample & hold circuit.
<3> After sampling continues for a certain period of time, the sample & hold circuit is put on hold to keep the input
analog voltage until A/D conversion is completed.
<4> Bit 7 of the successive approximation register (SAR) is set. The series resistor string voltage tap at the tap
selector is set to half of AVREF.
<5> The series resistor string tap voltage is compared with the analog input voltage using the voltage comparator.
If the analog input voltage is higher than half of AVREF, the MSB of the SAR remains set. If it is lower than
half of AVREF, the MSB is reset.
<6> Bit 6 of the SAR is set automatically, and comparison shifts to the next stage. The next voltage tap of the
series resistor string is selected according to bit 7, which reflects the previous comparison result, as follows:
• Bit 7 = 1: Three quarters of AVREF
• Bit 7 = 0: One quarter of AVREF
The tap voltage is compared with the analog input voltage. Bit 6 is set or reset according to the result of
comparison.
• Analog input voltage ≥ tap voltage: Bit 6 = 1
• Analog input voltage < tap voltage: Bit 6 = 0
<7> Comparison is repeated until bit 0 of the SAR is reached.
<8> When comparison is completed for all of the 8 bits, a significant digital result is left in the SAR. This value is
sent to and latched in A/D conversion result register 0 (ADCR0). At the same time, it is possible to generate
an A/D conversion end interrupt request (INTAD0).
Cautions 1. The first A/D conversion value immediately following the start of A/D conversion may be
undefined.
2. When the A/D converter enters the standby mode, it stops operating.
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Figure 10-4. Basic Operation of 8-Bit A/D Converter
Conversion
time
Sampling
time
A/D converter
operation
Sampling
A/D conversion
C0H
or 40H
Conversion
result
Undefined
SAR
ADCR0
INTAD0
80H
Conversion
result
A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software.
If an attempt is made to write to ADM0 or A/D input selection register 0 (ADS0) during A/D conversion, the current
A/D conversion is canceled. In this case, A/D conversion is restarted from the beginning, if the ADCS0 bit is set (1).
RESET makes A/D conversion result register 0 (ADCR0) undefined.
10.4.2 Input voltage and conversion result
The relationship between the analog input voltage at the analog input pins (ANI0 to ANI6) and the A/D conversion
result (A/D conversion result register 0 (ADCR0)) is represented by:
VIN
ADCR0 = INT (
or
× 256 + 0.5)
AVREF
AVREF
AVREF
(ADCR0 – 0.5) ×
≤ VIN < (ADCR0 + 0.5) ×
256
256
INT( ): Function that returns the integer part of a parenthesized value
VIN: Analog input voltage
AVREF: AVREF pin voltage
ADCR0: Value in A/D conversion result register 0 (ADCR0)
Figure 10-5 shows the relationship between the analog input voltage and the A/D conversion result.
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Figure 10-5. Relationship Between Analog Input Voltage and A/D Conversion Result
255
254
253
A/D conversion
result (ADCR0)
3
2
1
0
1
1
3
2
5
3
507 254 509 255 511
512 256 512 256 512
1
512 256 512 256 512 256
Input voltage/AVREF
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10.4.3 Operation mode of 8-bit A/D converter
The 8-bit A/D converter is initially in the select mode. In this mode, A/D input selection register 0 (ADS0) is used
to select an analog input channel from ANI0 to ANI6 for A/D conversion.
A/D conversion can be started only by software, that is, by setting A/D converter mode register 0 (ADM0).
The A/D conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt
request signal (INTAD0) is generated.
• Software-started A/D conversion
Setting bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) triggers A/D conversion for a voltage applied to
the analog input pin specified in A/D input selection register 0 (ADS0). Upon completion of A/D conversion, the
conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt request
signal (INTAD0) is generated. Once A/D conversion is activated, and completed, another session of A/D
conversion is started. A/D conversion is repeated until new data is written to ADM0. If data where the ADCS0
bit is 1 is written to ADM0 again during A/D conversion, the current session of A/D conversion is discontinued,
and a new session of A/D conversion begins for the new data. If data where the ADCS0 bit is 0 is written to
ADM0 again during A/D conversion, A/D conversion is stopped immediately.
Figure 10-6. Software-Started A/D Conversion
Rewriting ADM0
ADCS0 = 1
Rewriting ADM0
ADCS0 = 1
ADCS0 = 0
A/D conversion
ANIn
ANIn
ANIn
ANIm
ANIm
Conversion is
discontinued;
no conversion
Stop
result is preserved.
ADCR0
INTAD0
ANIn
ANIn
ANIm
Remarks 1. n = 0, 1, ..., 6
2. m = 0, 1, ..., 6
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10.5 Cautions on Using 8-Bit A/D Converter
(1) Current consumption in the standby mode
When the A/D converter enters the standby mode, it stops operating. Stopping conversion (bit 7 (ADCS0) of
A/D converter mode register 0 (ADM0) = 0) can reduce the current consumption.
Figure 10-7 shows how to reduce the current consumption in the standby mode.
Figure 10-7. How to Reduce Current Consumption in Standby Mode
AVREF
ADCS0
P-ch
Series resistor string
AVSS
(2) Input range for the ANI0 to ANI6 pins
Be sure to keep the input voltage at ANI0 to ANI6 within the rated range. If a voltage greater than AVREF or
less than AVSS (even within the absolute maximum rating) is input to a conversion channel, the conversion
output of the channel becomes undefined, and the conversion output of the other channels may also be
affected.
(3) Conflict
<1> Conflict between writing to A/D conversion result register 0 (ADCR0) at the end of conversion and reading
from the ADCR0 bit
Reading from the ADCR0 bit takes precedence. After reading, the new conversion result is written to the
ADCR0 bit.
<2> Conflict between writing to the ADCR0 bit at the end of conversion and writing to A/D converter mode
register 0 (ADM0) or A/D input selection register 0 (ADS0)
Writing to ADM0 or ADS0 takes precedence. A request to write to the ADCR0 bit is ignored. No A/D
conversion end interrupt request signal (INTAD0) is generated.
(4) Conversion results immediately following start of A/D conversion
The first A/D conversion value immediately following the start of A/D conversion may be undefined. Be sure
to poll the A/D conversion end interrupt request (INTAD0) and perform processing such as discarding the first
conversion result.
(5) Timing that makes the A/D conversion result undefined
If the timing of the end of A/D conversion and the timing of the stop of operation of the A/D converter conflict,
the A/D conversion value may be undefined. Because of this, be sure to read out the A/D conversion result
while the A/D converter is in operation. Furthermore, when reading out an A/D conversion result after A/D
conversion has stopped, be sure to have done so by the time the next conversion result is complete.
The conversion result readout timing is shown in Figures 10-8 and 10-9.
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Figure 10-8. Conversion Result Readout Timing (When Conversion Result Is Undefined Value)
A/D conversion end
A/D conversion end
ADCR0
INTAD0
ADCS0
Normal conversion result
Undefined value
Normal conversion result read out
A/D operation stopped
Undefined
value read out
Figure 10-9. Conversion Result Readout Timing (When Conversion Result Is Normal Value)
A/D conversion end
Normal conversion result
ADCR0
INTAD0
ADCS0
A/D operation stopped
Normal conversion
result read out
(6) Noise elimination
To maintain a resolution of 8 bits, it is necessary to avoid noise at the AVREF and ANI0 to ANI6 pins. The
higher the output impedance of the analog input source, the larger the effect by noise. To eliminate noise,
attach an external capacitor to the relevant pins as shown in Figure 10-10.
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Figure 10-10. Analog Input Pin Processing
If noise greater than AVREF or less than
AVSS is likely to come to the AVREF pin, clamp
the voltage at the pin by attaching a diode with a
small V (0.3 V or lower).
F
Reference voltage
input
AVREF
V
DD0
AVDD
C = 100 to 1000 pF
AVSS
V
SS0
(7) ANI0 to ANI6
The analog input pins (ANI0 to ANI6) are alternate-function pins. They are also used as port pins (P60 to
P66).
If any of ANI0 to ANI6 has been selected for A/D conversion, do not execute input instructions for the ports.
Otherwise, the conversion resolution may become lower.
If a digital pulse is applied to a pin adjacent to the analog input pins during A/D conversion, coupling noise
may occur which prevents an A/D conversion result from being attained as expected. Avoid applying a digital
pulse to pins adjacent to the analog input pins during A/D conversion.
(8) Input impedance of ANI0 to ANI6 pins
This A/D converter charges the internal sampling capacitor for about 1/10 of the conversion time, and
performs sampling.
Therefore at times other than sampling, only the leak current is output. During sampling, the current for
charging the capacitor is also output, so the input impedance fluctuates and has no meaning.
However, to ensure adequate sampling, it is recommended that the output impedance of the analog input
source be set to below 10 kΩ, or a 100 pF capacitor be connected to the ANI0 to ANI6 pins (see Figure 10-
10).
(9) Input impedance of the AVREF pin
A series resistor string of several tens of kΩ is connected across the AVREF and AVSS pins.
If the output impedance of the reference voltage source is high, this high impedance is eventually connected
in parallel with the series resistor string across the AVREF and AVSS pins, leading to a higher reference
voltage error.
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(10) Interrupt request flag (ADIF0)
Changing the contents of A/D converter mode register 0 (ADM0) does not clear the interrupt request flag
(ADIF0).
If the voltage at the analog input pins is changed during A/D conversion, therefore, the A/D conversion result
and the conversion end interrupt request flag may reflect the previous analog input just before writing to
ADM0. In this case, the ADIF0 may appear to be set if it is read-accessed just after ADM0 is write-accessed,
even when A/D conversion has not been completed for the new analog input.
In addition, ADIF0 must be cleared before A/D conversion is restarted.
Figure 10-11. A/D Conversion End Interrupt Request Generation Timing
Rewriting to ADM0
(to begin conversion
for ANIn)
Rewriting to ADM0
(to begin conversion
for ANIm)
ADIF0 has been set, but conversion
for ANIm has not been completed.
A/D conversion
ANIn
ANIn
ANIm
ANIm
ANIn
ANIn
ANIm
ANIm
ADCR0
INTAD0
Remarks 1. n = 0, 1, ..., 6
2. m = 0, 1, ..., 6
(11) AVDD pin
The AVDD pin is used to supply power to the analog circuit. It is also used to supply power to the ANI0 to
ANI6 input circuit.
If your application is designed to be switched to backup power, the AVDD pin must be supplied with the same
voltage level as for the VDD0 pin, as shown in Figure 10-12.
Figure 10-12. AVDD Pin Processing
VDD0
AVDD
Main power
source
Backup
capacitor
VSS0
AVSS
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CHAPTER 11 10-BIT A/D CONVERTER (µPD789417A SUBSERIES)
11.1 Function of 10-Bit A/D Converter
The 10-bit A/D converter converts input analog voltages to digital signals with a 10-bit resolution. It can control up
to seven analog input channels (ANI0 to ANI6).
A/D conversion can be started only by software.
One of analog inputs ANI0 to ANI6 is selected for A/D conversion. A/D conversion is performed repeatedly, with
an interrupt request (INTAD0) being issued each time an A/D conversion is completed.
11.2 Configuration of 10-Bit A/D Converter
The A/D converter consists of the following hardware.
Table 11-1. Configuration of 10-Bit A/D Converter
Item
Analog inputs
Registers
Configuration
7 channels (ANI0 to ANI6)
Successive approximation register (SAR)
A/D conversion result register 0 (ADCR0)
Control registers
A/D converter mode register 0 (ADM0)
A/D input selection register 0 (ADS0)
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Figure 11-1. Block Diagram of 10-Bit A/D Converter
Series resistor string
AVDD
AVREF
P-ch
ANI0/P60
ANI1/P61
ANI2/P62
ANI3/P63
ANI4/P64
ANI5/P65
ANI6/P66
Sample & hold circuit
Voltage comparator
AVSS
AVSS
Successive
approximation
register (SAR)
Controller
INTAD0
A/D conversion result
register 0 (ADCR0)
3
ADS02 ADS01 ADS00
ADCS0 FR02 FR01 FR00
A/D input selection
register 0 (ADS0)
A/D converter mode
register 0 (ADM0)
Internal bus
(1) Successive approximation register (SAR)
The SAR receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison
voltage), received from the series resistor string, starting from the most significant bit (MSB).
Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D
conversion, the SAR sends its contents to A/D conversion result register 0 (ADCR0).
(2) A/D conversion result register 0 (ADCR0)
ADCR0 is a 16-bit register that holds the result of A/D conversion. Lower 6 bits are fixed to 0. Each time A/D
conversion ends, the conversion result in the successive approximation register is loaded into ADCR0. The
conversion results are stored in ADCR0 starting from the most significant bit (MSB). The higher 8 bits of the
conversion results are stored in FF15H and the lower 2 bits of the conversion results are stored in FF14H.
ADCR0 is read using a 16-bit memory manipulation instruction.
RESET input makes ADCR0 undefined.
FF14H
FF15H
Address
After reset R/W
Symbol
ADCR0
FF14H,
FF15H
0
0
0
0
0
0
Undefined
R
Caution When the µPD78F9418A is used as the flash memory version of the µPD789405A, 789406A,
and 789407A, 8-bit access is possible, providing an object file has been assembled in the
µPD789405A, 789406A, and 789407A.
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(3) Sample & hold circuit
The sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends
them to the voltage comparator. The sampled analog input voltage is held during A/D conversion.
(4) Voltage comparator
The voltage comparator compares an analog input with the voltage output by the series resistor string.
(5) Series resistor string
The series resistor string is configured between AVREF and AVSS. It generates the reference voltages against
which analog inputs are compared.
(6) ANI0 to ANI6 pins
The ANI0 to ANI6 pins are analog input pins for the seven-channel A/D converter. They are used to receive
the analog signals to be subject to A/D conversion.
Caution Do not supply the ANI0 to ANI6 pins with voltages that fall outside the rated range. If a
voltage greater than AVREF or less than AVSS (even if within the absolute maximum rating) is
supplied to any of these pins, the conversion value for the corresponding channel will be
undefined. Furthermore, the conversion values for the other channels may also be
affected.
(7) AVREF pin
The AVREF pin is a reference voltage pin for the A/D converter.
Signals received at the ANI0 to ANI6 pins are converted to digital signals based on the voltage across the
AVREF and AVSS pins.
(8) AVSS pin
The AVSS pin is a ground potential pin for the A/D converter. This pin must be held at the same potential as
the VSS0 pin, even while the A/D converter is not being used.
(9) AVDD pin
The AVDD pin is an analog power supply pin for the A/D converter. This pin must be held at the same
potential as the VDD0 pin, even while the A/D converter is not being used.
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11.3 Registers Controlling 10-Bit A/D Converter
The following two registers are used to control the 10-bit A/D converter.
• A/D converter mode register 0 (ADM0)
• A/D input selection register 0 (ADS0)
(1) A/D converter mode register 0 (ADM0)
ADM0 specifies the conversion time for analog inputs. It also specifies whether to enable conversion.
ADM0 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ADM0 to 00H.
Figure 11-2. Format of A/D Converter Mode Register 0
Symbol <7>
6
0
5
4
3
2
0
1
0
0
0
Address
FF80H
After reset
00H
R/W
R/W
ADM0 ADCS0
FR02 FR01 FR00
ADCS0
A/D conversion control
0
1
Conversion stopped
Conversion enabled
FR02 FR01 FR00
A/D conversion time selectionNote 1
0
0
0
1
1
1
0
0
1
0
0
1
0
1
0
0
1
0
144/fx (28.8
120/fx (24
µ
s)
µ
s)
96/fx
72/fx
60/fx
48/fx
(19.2
(14.4
µ
µ
s)
s)
(Setting prohibitedNote 2
(Setting prohibitedNote 2
)
)
Other than above
Setting prohibited
Notes 1. The specifications of FR02, FR01, and FR00 must be such that the A/D conversion time is at least
14 µs.
2. These bit combinations must not be used, as the A/D conversion time will fall below 14 µs.
Cautions 1. The result of conversion performed immediately after bit 7 (ADCS0) is set is undefined.
2. The result of conversion performed after ADCS0 is cleared may be undefined (see 11.5 (5)
Timing that makes the A/D conversion result undefined for details).
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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(2) A/D input selection register 0 (ADS0)
ADS0 register specifies the port used to input the analog voltages to be converted to a digital signal.
ADS0 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ADS0 to 00H.
Figure 11-3. Format of A/D Input Selection Register 0
Symbol
ADS0
7
0
6
0
5
0
4
0
3
0
2
1
0
Address
FF84H
After reset
00H
R/W
R/W
ADS02 ADS01 ADS00
Analog input channel specification
ADS02 ADS01 ADS00
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Setting prohibited
Caution Bits 3 to 7 must be fixed to 0.
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CHAPTER 11 10-BIT A/D CONVERTER (µPD789417A SUBSERIES)
11.4 Operation of 10-Bit A/D Converter
11.4.1 Basic operation of 10-bit A/D converter
<1> Select a channel for A/D conversion, using A/D input selection register 0 (ADS0).
<2> The voltage supplied to the selected analog input channel is sampled using the sample & hold circuit.
<3> After sampling continues for a certain period of time, the sample & hold circuit is put on hold to keep the input
analog voltage until A/D conversion is completed.
<4> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap at the tap
selector is set to half of AVREF.
<5> The series resistor string tap voltage is compared with the analog input voltage using the voltage comparator.
If the analog input voltage is higher than half of AVREF, the MSB of the SAR remains set. If it is lower than
half of AVREF, the MSB is reset.
<6> Bit 8 of the SAR is set automatically, and comparison shifts to the next stage. The next voltage tap of the
series resistor string is selected according to bit 9, which reflects the previous comparison result, as follows:
• Bit 9 = 1: Three quarters of AVREF
• Bit 9 = 0: One quarter of AVREF
The tap voltage is compared with the analog input voltage. Bit 8 is set or reset according to the result of
comparison.
• Analog input voltage ≥ tap voltage: Bit 8 = 1
• Analog input voltage < tap voltage: Bit 8 = 0
<7> Comparison is repeated until bit 0 of the SAR is reached.
<8> When comparison is completed for all of the 10 bits, a significant digital result is left in the SAR. This value is
sent to and latched in A/D conversion result register 0 (ADCR0). At the same time, it is possible to generate
an A/D conversion end interrupt request (INTAD0).
Cautions 1. The first A/D conversion value immediately following the start of A/D conversion may be
undefined.
2. When the A/D converter enters the standby mode, it stops operating.
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Figure 11-4. Basic Operation of 10-Bit A/D Converter
Conversion
time
Sampling
time
A/D converter
operation
A/D conversion
Sampling
C0H
or 40H
Conversion
result
SAR
ADCR0
INTAD0
Undefined
80H
Conversion
result
A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software.
If an attempt is made to write to ADM0 or A/D input selection register 0 (ADS0) during A/D conversion, the current
A/D conversion is canceled. In this case, A/D conversion is restarted from the beginning, if the ADCS0 bit is set (1).
RESET makes A/D conversion result register 0 (ADCR0) undefined.
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CHAPTER 11 10-BIT A/D CONVERTER (µPD789417A SUBSERIES)
11.4.2 Input voltage and conversion result
The relationship between the analog input voltage at the analog input pins (ANI0 to ANI6) and the A/D conversion
result (A/D conversion result register 0 (ADCR0)) is represented by:
V
IN
ADCR0 = INT (
or
× 1024 + 0.5)
AVREF
AVREF
AVREF
(ADCR0 – 0.5) ×
≤ VIN < (ADCR0 + 0.5) ×
1024
1024
INT( ): Function that returns the integer part of a parenthesized value
VIN: Analog input voltage
AVREF: AVREF pin voltage
ADCR0: Value in A/D conversion result register 0 (ADCR0)
Figure 11-5 shows the relationship between the analog input voltage and the A/D conversion result.
Figure 11-5. Relationship Between Analog Input Voltage and A/D Conversion Result
1023
1022
1021
A/D conversion
result (ADCR0)
3
2
1
0
1
1
3
2
5
3
2043 1022 2045 1023 2047
2048 1024 2048 1024 2048
1
2048 1024 2048 1024 2048 1024
Input voltage/AVREF
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CHAPTER 11 10-BIT A/D CONVERTER (µPD789417A SUBSERIES)
11.4.3 Operation mode of 10-bit A/D converter
The 10-bit A/D converter is initially in the select mode. In this mode, A/D input selection register 0 (ADS0) is used
to select an analog input channel from ANI0 to ANI6 for A/D conversion.
A/D conversion can be started only by software, that is, by setting A/D converter mode register 0 (ADM0).
The A/D conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt
request signal (INTAD0) is generated.
• Software-started A/D conversion
Setting bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) triggers A/D conversion for a voltage applied to
the analog input pin specified in A/D input selection register 0 (ADS0). Upon completion of A/D conversion, the
conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt request
signal (INTAD0) is generated. Once A/D conversion is activated, and completed, another session of A/D
conversion is started. A/D conversion is repeated until new data is written to ADM0. If data where the ADCS0
bit is 1 is written to ADM0 again during A/D conversion, the current session of A/D conversion is discontinued,
and a new session of A/D conversion begins for the new data. If data where the ADCS0 bit is 0 is written to
ADM0 again during A/D conversion, A/D conversion is stopped immediately.
Figure 11-6. Software-Started A/D Conversion
Rewriting ADM0
ADCS0 = 1
Rewriting ADM0
ADCS0 = 1
ADCS0 = 0
A/D conversion
ANIn
ANIn
ANIn
ANIm
ANIm
Conversion is
discontinued;
no conversion
Stop
result is preserved.
ADCR0
INTAD0
ANIn
ANIn
ANIm
Remarks 1. n = 0, 1, ..., 6
2. m = 0, 1, ..., 6
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CHAPTER 11 10-BIT A/D CONVERTER (µPD789417A SUBSERIES)
11.5 Cautions on Using 10-Bit A/D Converter
(1) Current consumption in the standby mode
When the A/D converter enters the standby mode, it stops operating. Setting the bit 7 (ADCS0) of A/D
converter mode register 0 (ADM0) = 0 can reduce the current consumption.
Figure 11-7 shows how to reduce the current consumption in the standby mode.
Figure 11-7. How to Reduce Current Consumption in Standby Mode
AVREF
ADCS0
P-ch
Series resistor string
AVSS
(2) Input range for the ANI0 to ANI6 pins
Be sure to keep the input voltage at ANI0 to ANI6 within the rated range. If a voltage greater than AVREF or
less than AVSS (even within the absolute maximum rating) is input a conversion channel, the conversion
output of the channel becomes undefined, and the conversion output of the other channels may be affected.
(3) Conflict
<1> Conflict between writing to A/D conversion result register 0 (ADCR0) at the end of conversion and reading
from the ADCR0 bit
Reading from the ADCR0 bit takes precedence. After reading, the new conversion result is written to
ADCR0 bit.
<2> Conflict between writing to the ADCR0 bit at the end of conversion and writing to A/D converter mode
register 0 (ADM0) or A/D input selection register 0 (ADS0)
Writing to ADM0 or ADS0 takes precedence. A request to write to the ADCR0 bit is ignored. No A/D
conversion end interrupt request signal (INTAD0) is generated.
(4) Conversion results immediately following start of A/D conversion
The first A/D conversion value immediately following the start of A/D conversion may be undefined. Be sure
to poll the A/D conversion end interrupt request (INTAD0) and perform processing such as discarding the first
conversion result.
(5) Timing that makes the A/D conversion result undefined
If the timing of the end of A/D conversion and the timing of the stop of operation of the A/D converter conflict,
the A/D conversion value may be undefined. Because of this, be sure to read out the A/D conversion result
while the A/D converter is in operation. Furthermore, when reading out an A/D conversion result after A/D
conversion has stopped, be sure to have done so by the time the next conversion result is complete.
The conversion result readout timing is shown in Figures 11-8 and 11-9.
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Figure 11-8. Conversion Result Readout Timing (When Conversion Result Is Undefined Value)
A/D conversion end
A/D conversion end
ADCR0
INTAD0
ADCS0
Normal conversion result
Undefined value
Normal conversion result read out
A/D operation
stopped
Undefined value
read out
Figure 11-9. Conversion Result Readout Timing (When Conversion Result Is Normal Value)
A/D conversion end
ADCR0
Normal conversion result
INTAD0
ADCS0
A/D operation stopped
Normal conversion
result read out
(6) Noise elimination
To maintain a resolution of 10 bits, it is necessary to avoid for noise at the AVREF and ANI0 to ANI6 pins. The
higher the output impedance of the analog input source, the larger the effect by noise. To eliminate noise,
attach an external capacitor to the relevant pins as shown in Figure 11-10.
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CHAPTER 11 10-BIT A/D CONVERTER (µPD789417A SUBSERIES)
Figure 11-10. Analog Input Pin Processing
If noise greater than AVREF or less than
AVSS is likely to come to the AVREF pin, clamp
the voltage at the pin by attaching a diode with
a small V (0.3 V or lower).
F
Reference voltage
input
AVREF
V
DD0
AVDD
C = 100 to 1000 pF
AVSS
V
SS0
(7) ANI0 to ANI6
The analog input pins (ANI0 to ANI6) are alternate-function pins. They are also used as port pins (P60 to
P66).
If any of ANI0 to ANI6 has been selected for A/D conversion, do not execute input instructions for the ports.
Otherwise, the conversion resolution may become lower.
If a digital pulse is applied to a pin adjacent to the analog input pins during A/D conversion, coupling noise
may occur which prevents an A/D conversion result from being attained as expected. Avoid applying a digital
pulse to pins adjacent to the analog input pins during A/D conversion.
(8) Input impedance of ANI0 to ANI6 pins
This A/D converter charges the internal sampling capacitor for about 1/10 of the conversion time, and
performs sampling.
Therefore at times other than sampling, only the leak current is output. During sampling, the current for
charging the capacitor is also output, so the input impedance fluctuates and has no meaning.
However, to ensure adequate sampling, it is recommended that the output impedance of the analog input
source be set to below 10 kΩ, or a 100 pF capacitor be connected to the ANI0 to ANI6 pins (see Figure 11-
10).
(9) Input impedance of the AVREF pin
A series resistor string of 10 kΩ is connected across the AVREF and AVSS pins.
If the output impedance of the reference voltage source is high, this high impedance is eventually connected
in parallel with the series resistor string across the AVREF and AVSS pins, leading to a higher reference
voltage error.
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(10) Interrupt request flag (ADIF0)
Changing the contents of A/D converter mode register 0 (ADM0) does not clear the interrupt request flag
(ADIF0).
If the voltage at the analog input pins is changed during A/D conversion, therefore, the A/D conversion result
and the conversion end interrupt request flag may reflect the previous analog input just before writing to
ADM0. In this case, the ADIF0 may appear to be set if it is read-accessed just after ADM0 is write-accessed,
even when A/D conversion has not been completed for the new analog input.
In addition, ADIF0 must be cleared before A/D conversion is restarted.
Figure 11-11. A/D Conversion End Interrupt Request Generation Timing
Rewriting to ADM0
(to begin conversion
for ANIn)
Rewriting to ADM0
(to begin conversion
for ANIm)
ADIF0 has been set, but conversion
for ANIm has not been completed.
A/D conversion
ANIn
ANIn
ANIm
ANIm
ANIn
ANIn
ANIm
ANIm
ADCR0
INTAD0
Remarks 1. n = 0, 1, ..., 6
2. m = 0, 1, ..., 6
(11) AVDD pin
The AVDD pin is used to supply power to the analog circuit. It is also used to supply power to the ANI0 to
ANI6 input circuit.
If your application is designed to be changed to backup power, the AVDD pin must be supplied with the same
voltage level as for the VDD0 pin, as shown in Figure 11-12.
Figure 11-12. AVDD Pin Processing
VDD0
AVDD
Backup
Main power
source
capacitor
V
SS0
AVSS
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CHAPTER 12 COMPARATOR
12.1 Functions of Comparator
The comparator has the following functions.
(1) Input voltage comparison by comparator
The comparator compares an input voltage at the reference voltage input pin (CMPREF0) with an input
voltage at the comparator input pin (CMPIN0). The comparison result can be read using memory
manipulation instructions.
(2) Interrupt generation by comparator output
The comparator output is used to generate an interrupt request signalNote (INTCMP0).
Note The rising edge, falling edge, or both rising and falling edges can be specified by setting external
interrupt mode register 1 (INTM1).
(3) Clock output
When CMPREF0 > CMPIN0, the output of 8-bit timer counter 02 (TM02) is directed to the CMPTOUT0 pin.
(4) Open-drain output selection
Comparator mode register 0 (CMPRM0) is used to specify a port as an N-ch open-drain output.
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12.2 Configuration of Comparator
The comparator consists of the following hardware.
(1) CMPIN0
This is the comparator input pin.
(2) CMPTOUT0
This is the comparator output pin.
(3) CMPREF0
This is the comparator reference voltage input pin.
Figure 12-1 is a block diagram of the comparator.
Figure 12-1. Block Diagram of Comparator
Internal bus
P23
output latch
PM23
CMPTOUT0/P23/
TO2
8-bit timer 02
(TM02) output
_
+
CMPIN0
CMPREF0
Edge selector
INTCMP0
ES61
CMPOUT0
CMPON0
ES60
SELCMP0
OPDR0
Comparator mode
register 0 (CMPRM0)
External interrupt mode
register 1 (INTM1)
Internal bus
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CHAPTER 12 COMPARATOR
12.3 Register Controlling Comparator
The comparator is controlled by the following register.
(1) Comparator mode register 0 (CMPRM0)
CMPRM0 controls the power supply and clock output of the comparator. It also selects an open-drain output
for the comparator.
CMPRM0 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CMPRM0 to 00H.
Figure 12-2. Format of Comparator Mode Register 0
Symbol
7
0
6
0
5
0
4
0
3
2
1
0
Address
FF4EH
After reset
00H
R/W
CMPRM0
CMPON0 SELCMP0 OPDR0 CMPOUT0
R/WNote
CMPON0
Comparator power supply on/off control
0
1
Comparator power supply off
Comparator power supply on
SELCMP0
Clock output control
0
1
8-bit timer 02 (TM02) output
8-bit timer counter 02 (TM02) output if CMPREF0 > CMPIN0
OPDR0
Open-drain output selection
0
1
CMOS output
N-ch open-drain output
CMPOUT0
The comparator output is read.
Note Bit 0 is read-only.
Cautions 1. Bits 4 to 7 must be fixed to 0.
2. If the comparator is enabled (CMPON0 = 1), noise may be induced. If it is necessary to
generate an interrupt request signal (INTCMP0) from the output of the comparator, enable the
comparator (CMPON0 = 1), then clear the interrupt request flag (CMPIF0) to 0, before
enabling interrupts.
3. Similarly, if it is necessary to direct the output of the comparator to the port, enable the
comparator (CMPON0 = 1) in advance.
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12.4 Operation of Comparator
The output of 8-bit timer 02 (TM02) can be controlled and directed to the CMPTOUT0/P23/TO2 pin via the
comparator.
To run the comparator, set as follows:
• Set P23 to output mode (PM23 = 0).
• Set comparator mode register 0 (CMPRM0) as shown in Figure 12-3.
• Set external interrupt mode register 1 (INTM1) as shown in Figure 12-4 and select the valid edge of INTCMP0.
Figure 12-3. Settings of Comparator Mode Register 0 for Comparator Operation
CMPON0 SELCMP0 OPDR0 CMPOUT0
CMPRM0
0
0
0
0
1
1
0/1
–
Outputs TM02.
Switches on the
comparator power.
Figure 12-4. Settings of External Interrupt Mode Register 1 at INTCMP0 Occurrence
ES61
0/1
ES60
0/1
ES31
0/1
ES30
0/1
INTM1
0
0
1
1
Selects the valid edge
(see Table 12-1).
Table 12-1 lists the selection of INTCMP0 valid edges, and Figure 12-5 shows the timing chart of the comparator.
Table 12-1. INTCMP0 Valid Edges
ES61
ES60
INTCMP0 Valid Edge Selection
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
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CHAPTER 12 COMPARATOR
Figure 12-5. Comparator Operation Timing (1/2)
Timer (TM02)
output
CMPOUT0
CMPTOUT0
SELCMP0
Timer (TM02)
output enable
signal
<1> CMPOUT0 is latched on the rising edge of the TM02 output to generate a signal to enable output to the
CMPTOUT0/P23/TO2 pin. If CMPOUT0 is high, the TM02 output waveform is output to the
CMPTOUT0/P23/TO2 pin on the rising edge of the TM02 output. If CMPOUT0 is low, CMPTOUT0 is not
output.
<2> If SELCMP0 is low, the TM02 output is sent to the CMPTOUT0/P23/TO2 pin no matter which level
CMPOUT0 is on.
Figure 12-5. Comparator Operation Timing (2/2)
Timer (TM02)
output
CMPOUT0
CMPTOUT0
SELCMP0
Timer (TM02)
output enable
signal
<3> If the high level of CMPOUT0 is latched on the rising edge of the TM02 output, CMPTOUT0 is output to the
CMPTOUT0/P23/TO2 pin for at least two clock pulses even if it falls immediately.
<4> Switching SELCMP0 from high to low during CMPTOUT0 output may disturb the output waveform of
CMPTOUT0.
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CHAPTER 13 SERIAL INTERFACE 00
13.1 Functions of Serial Interface 00
Serial interface 00 has the following three modes.
• Operation stopped mode
• Asynchronous serial interface (UART) mode
• 3-wire serial I/O mode
(1) Operation stopped mode
This mode is used to reduce power consumption when serial transfer is not carried out.
(2) Asynchronous serial interface (UART) mode
In this mode, one byte of data following the start bit is transmitted/received, and full-duplex operation is
possible.
A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud
rates. In addition, the baud rate can be defined by dividing the clock input to the ASCK pin.
(3) 3-wire serial I/O mode (MSB/LSB start bit switchable)
In this mode, 8-bit data transfer is carried out using three lines, one for the serial clock (SCK) and two for
serial data (SI, SO).
The 3-wire serial I/O mode supports simultaneous transmit and receive operations, reducing data transfer
processing time.
It is possible to switch the start bit of 8-bit data to be transmitted between the MSB and the LSB, thus
allowing connection to devices with either start bit.
The 3-wire serial I/O mode is effective for connecting display controllers and peripheral I/Os such as the
75XL Series, 78K Series, and 17K Series, which have conventional clock synchronous serial interfaces.
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CHAPTER 13 SERIAL INTERFACE 00
13.2 Configuration of Serial Interface 00
Serial interface 00 consists of the following hardware.
Table 13-1. Configuration of Serial Interface 00
Item
Configuration
Registers
Transmit shift register 00 (TXS00)
Receive shift register 00 (RXS00)
Receive buffer register 00 (RXB00)
Control registers
Serial operation mode register 00 (CSIM00)
Asynchronous serial interface mode register 00 (ASIM00)
Asynchronous serial interface status register 00 (ASIS00)
Baud rate generator control register 00 (BRGC00)
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Figure 13-1. Block Diagram of Serial Interface 00
Internal bus
Asynchronous serial interface
mode register 00 (ASIM00)
Asynchronous serial interface
status register 00 (ASIS00)
Receive buffer
register 00 (RXB00/SIO00)
Direction controller
TXE00 RXE00 PS001 PS000 CL00 SL00
PE00 FE00 OVE00
Transmit shift
register 00 (TXS00/SIO00)
Direction controller
Receive shift
register 00 (RXS00)
RxD/SI/P22
TxD/SO/P21
PM21
SCK output controller
INTST00
Transmit
controller
Receive
controller
PM20
INTSR00/INTCSI00
ASCK/SCK/P20
Note
Baud rate generator
fX
/2 to f
/28
X
4
CSIE00
TXE00
RXE00
CSCK00
CSIE00 DIR00 CSCK00
TPS003 TPS002 TPS001 TPS000
Serial operation mode
register 00 (CSIM00)
Baud rate generator
control register 00 (BRGC00)
Internal bus
Note For the baud rate generator configuration, see Figure 13-2.
Figure 13-2. Block Diagram of Baud Rate Generator
CSIE00
TXE00
RXE00
Stop
Prescaler
BRGC00 write
TXE00
f
X
f
X
f
X
f
X
f
X
f
X
f
X
f
2
X
28 27 26 25 24 23 22
Clear
Clear
Transmit clock
Receive clock
3-bit counter
1/2
ASCK/SCK/P20
4
1/2
3-bit counter
Clear
CSIE00
CSCK00
Clear
RXE00
CSIE00
Start bit detection
BRGC00 write
TPS003 TPS002 TPS001 TPS000
RXE00
Baud rate generator
control register 00 (BRGC00)
Internal bus
CHAPTER 13 SERIAL INTERFACE 00
(1) Transmit shift register 00 (TXS00)
This register is used to specify data to be transmitted. Data written to TXS00 is transmitted as serial data.
If the data length is specified as 7 bits, bits 0 to 6 of the data written to TXS00 are transferred as the transmit
data. The transmit operation is started by writing data to TXS00.
TXS00 is written to using an 8-bit memory manipulation instruction. It cannot be read.
RESET input sets TXS00 to FFH.
Caution Do not write to TXS00 during a transmit operation.
TXS00 and receive buffer register 00 (RXB00) are allocated to the same address, and when
reading is performed, RXB00 values are read.
(2) Receive shift register 00 (RXS00)
This register is used to convert serial data input to the RxD pin into parallel data. Each time one byte of data
is received, it is transferred to receive buffer register 00 (RXB00).
RXS00 cannot be manipulated directly by program.
(3) Receive buffer register 00 (RXB00)
This register is used to hold received data. Each time one byte of data is received, a new byte of data is
transferred from receive shift register 00 (RXS00).
If the data length is specified as 7 bits, receive data is transferred to bits 0 to 6 of RXB00, and the MSB of
RXB00 always becomes 0.
RXB00 can be read using an 8-bit memory manipulation instruction. It cannot be written to.
RESET input makes RXB00 undefined.
Caution RXB00 and transmit shift register 00 (TXS00) are allocated to the same address, and when
writing is performed, the values are written to TXS00.
(4) Transmit controller
This circuit controls transmit operations by adding a start bit, parity bit, and stop bit to data written to transmit
shift register 00 (TXS00), according to the data set to asynchronous serial interface mode register 00
(ASIM00).
(5) Receive controller
This circuit controls receive operations according to the data set to asynchronous serial interface mode
register 00 (ASIM00). It also performs a parity error check, etc., during receive operations, and when an error
is detected, it sets a value to asynchronous serial interface status register 00 (ASIS00) in accordance with
the nature of the error.
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CHAPTER 13 SERIAL INTERFACE 00
13.3 Registers Controlling Serial Interface 00
The following four registers are used to control serial interface 00.
• Serial operation mode register 00 (CSIM00)
• Asynchronous serial interface mode register 00 (ASIM00)
• Asynchronous serial interface status register 00 (ASIS00)
• Baud rate generator control register 00 (BRGC00)
(1) Serial operation mode register 00 (CSIM00)
This register is set when using serial interface 00 in the 3-wire serial I/O mode.
CSIM00 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CSIM00 to 00H.
Figure 13-3. Format of Serial Operation Mode Register 00
<7>
6
0
5
0
4
0
3
0
2
1
0
0
Address
FF72H
After reset
00H
R/W
R/W
Symbol
CSIM00 CSIE00
DIR00 CSCK00
CSIE00
Operation control in 3-wire serial I/O mode
0
1
Operation stopped
Operation enabled
DIR00
Start bit specification
MSB
LSB
0
1
CSCK00
Clock selection in 3-wire serial I/O mode
0
1
Clock input to SCK pin from external
Dedicated baud rate generator output
Cautions 1. Bits 0 and 3 to 6 must be fixed to 0.
2. Set CSIM00 to 00H in the UART mode.
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(2) Asynchronous serial interface mode register 00 (ASIM00)
This register is set when using serial interface 00 in the asynchronous serial interface mode.
ASIM00 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ASIM00 to 00H.
Figure 13-4. Format of Asynchronous Serial Interface Mode Register 00
Symbol <7> <6>
5
4
3
2
1
0
0
0
Address
FF70H
After reset
00H
R/W
R/W
ASIM00 TXE00 RXE00 PS001 PS000 CL00 SL00
TXE00
Transmit operation control
0
1
Transmit operation stopped
Transmit operation enabled
RXE00
Receive operation control
0
1
Receive operation stopped
Receive operation enabled
PS001 PS000
Parity bit specification
0
0
0
1
No parity
0 parity always added at transmission
Parity check is not performed at reception (no parity error occurs)
Odd parity
Even parity
1
1
0
1
CL00
Character length specification
0
1
7 bits
8 bits
SL00
Transmit data stop bit length specification
0
1
1 bit
2 bits
Cautions 1. Bits 0 and 1 must be fixed to 0.
2. Set ASIM00 to 00H in the 3-wire serial I/O mode.
3. Switching operation modes must be performed after the serial transmit/receive operation is
stopped.
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Table 13-2. Operation Mode Settings of Serial Interface 00
(1) Operation stopped mode
CSIM00
PM22 P22 PM21 P21
PM20 P20 Start Shift
P22/SI/RxD
Pin Function
P21/SO/TxD
Pin Function
P20/SCK/ASCK
Pin Function
ASIM00
Clock
—
Bit
CSCK00
TXE00 RXE00 CSIE00 DIR00
0
0
0
x
x
xNote 1
x
Note 1 xNote 1 xNote 1
x
Note 1 xNote 1
—
P22
P21
P20
Other than above
Setting prohibited
(2) Asynchronous serial interface mode
P22
Start
Bit
ASIM00
CSIM00
PM22
PM21 P21 PM20 P20
Shift
P22/SI/RxD
Pin Function
P22
P21/SO/TxD
Pin Function
P20/SCK/ASCK
Pin Function
ASCK input
Clock
TXE00 RXE00 CSIE00 DIR00 CSCK00
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
xNote 1 xNote 1
0
1
1
x
LSB
TxD
External
clock
(CMOS output)
x
Note 1 xNote 1
Internal
clock
P20
1
1
x
x
xNote 1 xNote 1
1
x
RxD
P21
ASCK input
P20
External
clock
xNote 1 xNote 1
Internal
clock
0
1
1
x
TxD
ASCK input
P20
External
clock
(CMOS output)
xNote 1 xNote 1
Internal
clock
Other than above
Setting prohibited
(3) 3-wire serial I/O mode
P22
Start
Bit
ASIM00
CSIM00
PM22
PM21 P21 PM20 P20
Shift
P22/SI/RxD
Pin Function
P21/SO/TxD
Pin Function
SO
P20/SCK/ASCK
Pin Function
SCK input
Clock
TXE00 RXE00 CSIE00 DIR00 CSCK00
0
0
1
0
0
1
0
1
1Note 2 xNote 2
0
1
1
0
1
0
x
1
x
1
MSB External SINote 2
clock
(CMOS output)
Internal
clock
SCK output
SCK input
SCK output
1
1
LSB External
clock
Internal
clock
Other than above
Setting prohibited
Notes 1. Can be used as port function.
2. If used only for transmission, can be used as P22 (CMOS I/O).
Remark x: Don’t care
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(3) Asynchronous serial interface status register 00 (ASIS00)
This register indicates the type of error when a reception error occurs in the asynchronous serial interface
mode.
ASIS00 is read using a 1-bit or 8-bit memory manipulation instruction.
The contents of ASIS00 become undefined in the 3-wire serial I/O mode.
RESET input sets ASIS00 to 00H.
Figure 13-5. Format of Asynchronous Serial Interface Status Register 00
Symbol
ASIS00
7
0
6
0
5
0
4
0
3
0
2
1
0
Address
FF71H
After reset
00H
R/W
R
PE00 FE00 OVE00
PE00
Parity error flag
0
1
Parity error did not occur
Parity error occurred (when the transmit parity and receive parity did not match)
Framing error flag
FE00
0
1
Framing error did not occur
Framing error occurred (when stop bit was not detected)Note 1
OVE00
Overrun error flag
Overrun error did not occur
0
1
Overrun error occurredNote 2
(when the next receive operation was completed before the data was read from receive buffer register 00)
Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL00) of asynchronous serial interface
mode register 00 (ASIM00), only one stop bit is detected during reception.
2. Be sure to read receive buffer register 00 (RXB00) when an overrun error occurs. If not, an overrun
error will occur every time the data is received.
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(4) Baud rate generator control register 00 (BRGC00)
This register is used to set the serial clock of serial interface 00.
BRGC00 is set using an 8-bit memory manipulation instruction.
RESET input sets BRGC00 to 00H.
Figure 13-6. Format of Baud Rate Generator Control Register 00
7
6
5
4
3
0
2
0
1
0
0
0
Address
FF73H
After reset
00H
R/W
R/W
Symbol
BRGC00 TPS003 TPS002 TPS001 TPS000
n
1
2
3
4
5
6
7
8
–
TPS003 TPS002 TPS001 TPS000
3-bit counter source clock selection
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fX
fX
fX
fX
fX
fX
fX
fX
/2 (2.5 MHz)
/22 (1.25 MHz)
/23 (625 kHz)
/24 (313 kHz)
/25 (156 kHz)
/26 (78.1 kHz)
/27 (39.1 kHz)
/28 (19.5 kHz)
Clock input from external to ASCK pinNote
Setting prohibited
Other than above
Note Only used in the UART mode.
Cautions 1. When BRGC00 is written during a communication operation, the output of the baud rate
generator is disrupted and communications cannot be performed normally. Be sure not to
write to BRGC00 during a communication operation.
2. Do not select n = 1 during fX = 5.0 MHz operation because the baud rate rating is exceeded.
Remarks 1. fX: Main system clock oscillation frequency
2. n: Value determined in the settings of TPS000 to TPS003 (1 ≤ n ≤ 8)
3. The parenthesized values apply to operation at fX = 5.0 MHz.
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The baud rate transmit/receive clock to be generated is either a signal divided from the main system clock, or
a signal divided from the clock input from the ASCK pin.
(a) Generation of baud rate transmit/receive clock from main system clock
The transmit/receive clock is generated by dividing the main system clock. The baud rate generated
from the main system clock is estimated by using the following expression.
fX
[Baud rate] =
[Hz]
2n + 1 × 8
fX: Main system clock oscillation frequency
n: Value in Figure 13-6 that is determined in the settings of TPS000 to TPS003 (2 ≤ n ≤ 8)
Table 13-3. Example of Relationship Between Main System Clock and Baud Rate
Baud Rate
(bps)
BRGC00 Set Value
Error (%)
fX = 4.9152 MHz
fX = 5.0 MHz
1.73
1200
2400
4800
9600
70H
60H
50H
40H
30H
20H
10H
0
19200
38400
76800
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(b) Generation of baud rate transmit/receive clock from external clock of ASCK pin
The transmit/receive clock is generated by dividing the clock input from the ASCK pin. The baud rate
generated from the clock input from the ASCK pin is estimated by using the following expression.
fASCK
[Baud rate] =
[Hz]
16
fASCK: Frequency of clock input to the ASCK pin
Table 13-4. Relationship Between ASCK Pin Input Frequency
and Baud Rate (When BRGC00 Is Set to 80H)
Baud Rate (bps)
75
ASCK Pin Input Frequency (kHz)
1.2
2.4
150
300
4.8
600
9.6
1200
19.2
38.4
76.8
153.6
307.2
500.0
614.4
2400
4800
9600
19200
31250
38400
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13.4 Operation of Serial Interface 00
Serial interface 00 has the following three modes.
• Operation stopped mode
• Asynchronous serial interface (UART) mode
• 3-wire serial I/O mode
13.4.1 Operation stopped mode
Serial transfer is not executed in the operation stopped mode, therefore the power consumption can be reduced.
The P20/SCK/ASCK, P21/SO/TxD, and P22/SI/RxD pins can be used as normal I/O port pins.
(1) Register setting
Operation stopped mode is set by serial operation mode register 00 (CSIM00) and asynchronous serial
interface mode register 00 (ASIM00).
(a) Serial operation mode register 00 (CSIM00)
CSIM00 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CSIM00 to 00H.
<7>
6
0
5
0
4
0
3
0
2
1
0
0
Address
FF72H
After reset
00H
R/W
R/W
Symbol
CSIM00 CSIE00
DIR00 CSCK00
CSIE00
Operation control in 3-wire serial I/O mode
0
1
Operation stopped
Operation enabled
Caution Bits 0 and 3 to 6 must be fixed to 0.
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(b) Asynchronous serial interface mode register 00 (ASIM00)
ASIM00 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ASIM00 to 00H.
Symbol <7> <6>
5
4
3
2
1
0
0
0
Address
FF70H
After reset
00H
R/W
R/W
ASIM00 TXE00 RXE00 PS001 PS000 CL00 SL00
TXE00
Transmit operation control
0
1
Transmit operation stopped
Transmit operation enabled
RXE00
Receive operation control
0
1
Receive operation stopped
Receive operation enabled
Caution Bits 0 and 1 must be fixed to 0.
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13.4.2 Asynchronous serial interface (UART) mode
In this mode, the one-byte data following the start bit is transmitted/received and thus full-duplex communications
are possible.
This device incorporates a UART-dedicated baud rate generator, enabling communication at the desired baud
rate. In addition, the baud rate can also be defined by dividing the clock input to the ASCK pin.
The UART-dedicated baud rate generator can also output a 31.25 kbps baud rate, which complies with the MIDI
standard.
(1) Register setting
UART mode is set by serial operation mode register 00 (CSIM00), asynchronous serial interface mode
register 00 (ASIM00), asynchronous serial interface status register 00 (ASIS00), and baud rate generator
control register 00 (BRGC00).
(a) Serial operation mode register 00 (CSIM00)
CSIM00 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CSIM00 to 00H.
Set CSIM00 to 00H in the UART mode.
<7>
6
0
5
0
4
0
3
0
2
1
0
0
Address
FF72H
After reset
00H
R/W
R/W
Symbol
CSIM00 CSIE00
DIR00 CSCK00
CSIE00
Operation control in 3-wire serial I/O mode
0
1
Operation stopped
Operation enabled
DIR00
Start bit specification
MSB
LSB
0
1
CSCK00
Clock selection in 3-wire serial I/O mode
0
1
Clock input to SCK pin from external
Dedicated baud rate generator output
Caution Bits 0 and 3 to 6 must be fixed to 0.
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(b) Asynchronous serial interface mode register 00 (ASIM00)
ASIM00 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ASIM00 to 00H.
Symbol <7> <6>
5
4
3
2
1
0
0
0
Address
FF70H
After reset
00H
R/W
R/W
ASIM00 TXE00 RXE00 PS001 PS000 CL00 SL00
TXE00
Transmit operation control
0
1
Transmit operation stopped
Transmit operation enabled
RXE00
Receive operation control
0
1
Receive operation stopped
Receive operation enabled
PS001 PS000
Parity bit specification
0
0
0
1
No parity
0 parity always added at transmission
Parity check is not performed at reception (no parity error occurs)
Odd parity
Even parity
1
1
0
1
CL00
Character length specification
0
1
7 bits
8 bits
SL00
Transmit data stop bit length specification
0
1
1 bit
2 bits
Cautions 1. Bits 0 and 1 must be fixed to 0.
2. Switching operation modes must be performed after the serial transmit/receive
operation is stopped.
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(c) Asynchronous serial interface status register 00 (ASIS00)
ASIS00 is read using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ASIS00 to 00H.
Symbol
ASIS00
7
0
6
0
5
0
4
0
3
0
2
1
0
Address
FF71H
After reset
00H
R/W
R
PE00 FE00 OVE00
PE00
Parity error flag
0
1
Parity error did not occur
Parity error occurred (when the transmit parity and receive parity did not match)
Framing error flag
FE00
0
1
Framing error did not occur
Framing error occurred (when stop bit was not detected)Note 1
OVE00
Overrun error flag
Overrun error did not occur
0
1
Overrun error occurredNote 2
(when the next receive operation was completed before the data was read from receive buffer register 00)
Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL00) of asynchronous serial
interface mode register 00 (ASIM00), only one stop bit will be detected during reception.
2. Be sure to read receive buffer register 00 (RXB00) when an overrun error occurs. If not,
every time the data is received an overrun error occurs.
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(d) Baud rate generator control register 00 (BRGC00)
BRGC00 is set using an 8-bit memory manipulation instruction.
RESET input sets BRGC00 to 00H.
7
6
5
4
3
0
2
0
1
0
0
0
Address
FF73H
After reset
00H
R/W
R/W
Symbol
BRGC00 TPS003 TPS002 TPS001 TPS000
n
1
2
3
4
5
6
7
8
TPS003 TPS002 TPS001 TPS000
3-bit counter source clock selection
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fX
fX
fX
fX
fX
fX
fX
fX
/2 (2.5 MHz)
/22 (1.25 MHz)
/23 (625 kHz)
/24 (313 kHz)
/25 (156 kHz)
/26 (78.1 kHz)
/27 (39.1 kHz)
/28 (19.5 kHz)
Clock input from external to ASCK pin
Setting prohibited
Other than above
Cautions 1. When BRGC00 is written during a communication operation, the output of the baud
rate generator is disrupted and communications cannot be performed normally.
Be sure not to write to BRGC00 during a communication operation.
2. Do not select n = 1 during fX = 5.0 MHz operation because the baud rate rating is
exceeded.
Remarks 1. fX: Main system clock oscillation frequency
2. n: Value determined in the settings of TPS000 to TPS003 (1 ≤ n ≤ 8)
3. The parenthesized values apply to operation at fX = 5.0 MHz.
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The baud rate transmit/receive clock to be generated is either a signal divided from the main system
clock, or a signal divided from the clock input from the ASCK pin.
(i) Generation of baud rate transmit/receive clock from main system clock
The transmit/receive clock is generated by dividing the main system clock. The baud rate
generated from the main system clock is estimated by using the following expression.
fX
[Baud rate] =
[Hz]
2n + 1 × 8
fX: Main system clock oscillation frequency
n: Value in the above table that is determined in the settings of TPS000 to TPS003 (2 ≤ n ≤
8)
Table 13-5. Example of Relationship Between Main System Clock and Baud Rate
Baud Rate
(bps)
BRGC00 Set Value
Error (%)
fX = 4.9152 MHz
fX = 5.0 MHz
1.73
1200
2400
4800
9600
70H
60H
50H
40H
30H
20H
10H
0
19200
38400
76800
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(ii) Generation of baud rate transmit/receive clock from external clock of ASCK pin
The transmit/receive clock is generated by dividing the clock input from the ASCK pin. The baud
rate generated from the clock input from the ASCK pin is estimated by using the following
expression.
fASCK
[Baud rate] =
[Hz]
16
fASCK: Frequency of clock input to the ASCK pin
Table 13-6. Relationship Between ASCK Pin Input Frequency
and Baud Rate (When BRGC00 Is Set to 80H)
Baud Rate (bps)
75
ASCK Pin Input Frequency (kHz)
1.2
2.4
150
300
4.8
600
9.6
1200
19.2
38.4
76.8
153.6
307.2
500.0
614.4
2400
4800
9600
19200
31250
38400
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(2) Communication operation
(a) Data format
The transmit/receive data format is as shown in Figure 13-7. One data frame consists of a start bit,
character bits, parity bit and stop bit(s).
The specification of character bit length, parity selection, and specification of stop bit length for each
data frame is carried out using asynchronous serial interface mode register 00 (ASIM00).
Figure 13-7. Format of Asynchronous Serial Interface Transmit/Receive Data
One data frame
Start
bit
Parity
bit
D0 D1 D2 D3 D4 D5 D6 D7
Stop bit
• Start bit ......................
• Character bits.............
• Parity bits ...................
• Stop bit(s)...................
1 bit
7 bits/8 bits
Even parity/odd parity/0 parity/no parity
1 bit/2 bits
When 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; the
most significant bit (bit 7) is ignored in transmission, and the most significant bit (bit 7) is always 0 in
reception.
The serial transfer rate is selected using ASIM00 and baud rate generator control register 00
(BRGC00).
If a serial data receive error occurs, the receive error contents can be determined by reading the status
of asynchronous serial interface status register 00 (ASIS00).
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(b) Parity types and operation
The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity
bit is used on the transmitting side and the receiving side. With even parity and odd parity, a “1” bit (odd
number) error can be detected. With 0 parity and no parity, an error cannot be detected.
(i) Even parity
• At transmission
The transmission operation is controlled so that the number of bits with a value of 1 in the
transmit data including the parity bit may be even. The parity bit value should be as follows.
The number of bits with a value of 1 is an odd number in transmit data:
The number of bits with a value of 1 is an even number in transmit data:
1
0
• At reception
The number of bits with a value of 1 in the receive data including the parity bit is counted, and if
the number is odd, a parity error occurs.
(ii) Odd parity
• At transmission
Conversely to even parity, the transmission operation is controlled so that the number of bits with
a value of 1 in the transmit data including the parity bit may be odd. The parity bit value should
be as follows.
The number of bits with a value of 1 is an odd number in transmit data:
The number of bits with a value of 1 is an even number in transmit data:
0
1
• At reception
The number of bits with a value of 1 in the receive data including the parity bit is counted, and if
the number is even, a parity error occurs.
(iii) 0 Parity
When transmitting, the parity bit is set to 0 irrespective of the transmit data.
At reception, a parity bit check is not performed. Therefore, a parity error does not occur,
irrespective of whether the parity bit is set to 0 or 1.
(iv) No parity
A parity bit is not added to the transmit data. At reception, data is received assuming that there is
no parity bit. Since there is no parity bit, a parity error does not occur.
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(c) Transmission
A transmit operation is started by writing transmit data to transmit shift register 00 (TXS00). The start
bit, parity bit and stop bit(s) are added automatically.
When the transmit operation starts, the data in TXS00 is shifted out, and when TXS00 is empty, a
transmission completion interrupt (INTST00) is generated.
Figure 13-8. Asynchronous Serial Interface Transmission Completion Interrupt Timing
(a) Stop bit length: 1
Stop
D0
D1
D2
D6
D7
Parity
TxD (Output)
INTST00
Start
(b) Stop bit length: 2
D0
D1
D2
D6
D7
Parity
TxD (Output)
INTST00
Stop
Start
Caution Do not rewrite asynchronous serial interface mode register 00 (ASIM00) during a
transmit operation. If ASIM00 is rewritten during transmission, subsequent
transmission may not operate correctly (the normal state is restored by RESET input).
Whether transmission is in progress or not can be judged by software using a
transmission completion interrupt (INTST00) or the interrupt request flag (STIF00) set
by INTST00.
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(d) Reception
When bit 6 (RXE00) of asynchronous serial interface mode register 00 (ASIM00) is set (1), a receive
operation is enabled and sampling of the RxD pin input is performed.
RxD pin input sampling is performed using the serial clock specified by ASIM00.
When the RxD pin input becomes low, the 3-bit counter starts counting, and when half the time
determined by the specified baud rate has passed, the data sampling start timing signal is output. If the
RxD pin input sampled again as a result of this start timing signal is low, it is identified as a start bit, the
3-bit counter is initialized and starts counting, and data sampling is performed. When character data, a
parity bit and one stop bit are detected after the start bit, reception of one frame of data ends.
When one frame of data has been received, the receive data in the shift register is transferred to receive
buffer register 00 (RXB00), and a reception completion interrupt (INTSR00) is generated.
If an error occurs, the receive data in which the error occurred is still transferred to RXB00, and
INTSR00 is generated.
If the RXE00 bit is reset (0) during the receive operation, the receive operation is stopped immediately.
In this case, the contents of RXB00 and asynchronous serial interface status register 00 (ASIS00) are
not changed, and INTSR00 is not generated.
Figure 13-9. Asynchronous Serial Interface Reception Completion Interrupt Timing
Stop
D0
D1
D2
D6
D7
Parity
RxD (Input)
INTSR00
Start
Caution Be sure to read receive buffer register 00 (RXB00) even if a receive error occurs. If
RXB00 is not read, an overrun error will occur when the next data is received, and the
receive error state will continue indefinitely.
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(e) Receive errors
The following three errors may occur during a receive operation: a parity error, framing error, or overrun
error. The data reception result error flag is set in asynchronous serial interface status register 00
(ASIS00). Receive error causes are shown in Table 13-7.
What kind of error occurred during reception can be judged by reading the contents of ASIS00 in the
receive error interrupt servicing (see Figures 13-9 and 13-10).
The contents of ASIS00 are reset (0) by reading receive buffer register 00 (RXB00) or receiving the next
data (if there is an error in the next data, the corresponding error flag is set).
Table 13-7. Receive Error Causes
Receive Errors
Cause
Parity error
The parity specified at transmission and the reception data parity do not match.
A stop bit is not detected.
Framing error
Overrun error
Reception of the next data is completed before data is read from the receive buffer register.
Figure 13-10. Receive Error Timing
(a) Parity error occurs
Stop
D0
D1
D2
D6
D7
Parity
RxD (input)
Start
INTSR00
(b) Framing error or overrun error occurs
Stop
D0
D1
D2
D6
D7
Parity
RxD (input)
INTSR00
Start
Cautions 1. The contents of the ASIS00 register are reset (0) by reading receive buffer register
00 (RXB00) or receiving the next data. To ascertain the error contents, read ASIS00
before reading RXB00.
2. Be sure to read receive buffer register 00 (RXB00) even if a receive error occurs. If
RXB00 is not read, an overrun error will occur when the next data is received, and
the receive error state will continue indefinitely.
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(f) Reading receive data
When the reception completion interrupt (INTSR00) is generated, receive data can be read by reading
the value of receive buffer register 00 (RXB00).
To read the receive data stored in receive buffer register 00 (RXB00), read while reception is enabled
(RXE00 = 1).
Remark However, if it is necessary to read receive data after reception has stopped (RXE00 = 0),
read using either of the following methods.
(a) Read after setting RXE00 = 0 after waiting for one cycle or more of the source clock
selected by BRGC00.
(b) Read after bit 2 (DIR00) of serial operation mode register 00 (CSIM00) is set (1).
Program example of (a) (BRGC00 = 00H (source clock = fx/2))
INTRXE:
NOP
;<Reception completion interrupt routine>
;2 clocks
CLR1 RXE00
;Reception stopped
MOV A, RXB00
;Read receive data
Program example of (b)
INTRXE:
;<Reception completion interrupt routine>
;DIR00 flag is set to LSB first
;Reception stopped
SET1 CSIM00.2
CLR1 RXE00
MOV A, RXB00
;Read receive data
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(3) Cautions on UART mode
(a) When bit 7 (TXE00) of asynchronous serial interface mode register 00 (ASIM00) is cleared during
transmission, be sure to set transmit shift register 00 (TXS00) to FFH, then set the TXE00 bit to 1
before executing the next transmission.
(b) When bit 6 (RXE00) of asynchronous serial interface mode register 00 (ASIM00) is cleared during
reception, receive buffer register 00 (RXB00) and the reception completion interrupt (INTSR00) are as
follows.
RxD pin
Parity
RXB00
INTSR00
<1>
<3>
<2>
When RXE00 is set to 0 at the timing indicated by <1>, RXB00 holds the previous data and does not
generate INTSR00.
When RXE00 is set to 0 at the timing indicated by <2>, RXB00 renews the data and does not generate
INTSR00.
When RXE00 is set to 0 at the timing indicated by <3>, RXB00 renews the data and generates INTSR00.
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CHAPTER 13 SERIAL INTERFACE 00
13.4.3 3-wire serial I/O mode
The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which
incorporate a conventional synchronous serial interface, such as the 75XL Series, 78K Series, and 17K Series.
Communication is performed using three lines: the serial clock (SCK), serial output (SO), and serial input (SI).
(1) Register setting
3-wire serial I/O mode settings are performed using serial operation mode register 00 (CSIM00),
asynchronous serial interface mode register 00 (ASIM00), and baud rate generator control register 00
(BRGC00).
(a) Serial operation mode register 00 (CSIM00)
CSIM00 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CSIM00 to 00H.
<7>
6
0
5
0
4
0
3
0
2
1
0
0
Address
FF72H
After reset
00H
R/W
R/W
Symbol
CSIM00 CSIE00
DIR00 CSCK00
CSIE00
Operation control in 3-wire serial I/O mode
0
1
Operation stopped
Operation enabled
DIR00
Start bit specification
MSB
LSB
0
1
CSCK00
Clock selection in 3-wire serial I/O mode
0
1
Clock input to SCK pin from external
Dedicated baud rate generator output
Caution Bits 0 and 3 to 6 must be fixed to 0.
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(b) Asynchronous serial interface mode register 00 (ASIM00)
ASIM00 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ASIM00 to 00H.
ASIM00 must be set to 00H in the 3-wire serial I/O mode.
Symbol <7> <6>
5
4
3
2
1
0
0
0
Address
FF70H
After reset
00H
R/W
R/W
ASIM00 TXE00 RXE00 PS001 PS000 CL00 SL00
TXE00
Transmit operation control
0
1
Transmit operation stopped
Transmit operation enabled
RXE00
Receive operation control
0
1
Receive operation stopped
Receive operation enabled
PS001 PS000
Parity bit specification
0
0
0
1
No parity
0 parity always added at transmission
Parity check is not performed at reception (no parity error occurs.)
Odd parity
Even parity
1
1
0
1
CL00
Character length specification
0
1
7 bits
8 bits
SL00
Transmit data stop bit length specification
0
1
1 bit
2 bits
Cautions 1. Bits 0 and 1 must be fixed to 0.
2. Switching operation modes must be performed after the serial transmit/receive
operation is stopped.
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CHAPTER 13 SERIAL INTERFACE 00
(c) Baud rate generator control register 00 (BRGC00)
BRGC00 is set using an 8-bit memory manipulation instruction.
RESET input sets BRGC00 to 00H.
7
6
5
4
3
0
2
0
1
0
0
0
Address
FF73H
After reset
00H
R/W
R/W
Symbol
BRGC00 TPS003 TPS002 TPS001 TPS000
n
1
2
3
4
5
6
7
8
TPS003 TPS002 TPS001 TPS000
3-bit counter source clock selection
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fX
fX
fX
fX
fX
fX
fX
fX
/2 (2.5 MHz)
/22 (1.25 MHz)
/23 (625 kHz)
/24 (313 kHz)
/25 (156 kHz)
/26 (78.1 kHz)
/27 (39.1 kHz)
/28 (19.5 kHz)
Other than above
Setting prohibited
Cautions 1. When BRGC00 is written during a communication operation, the output of the baud
rate generator is disrupted and communications cannot be performed normally.
Be sure not to write to BRGC00 during a communication operation.
2. Do not select n = 1 during fX = 5.0 MHz operation because the baud rate rating is
exceeded.
Remarks 1. fX: Main system clock oscillation frequency
2. n: Value in the above table that is determined in the settings of TPS000 to TPS003 (1 ≤
n ≤ 8)
3. The parenthesized values apply to operation at fX = 5.0 MHz.
If the internal clock is used as the serial clock for the 3-wire serial I/O mode, set the TPS000 to TPS003
bits to set the frequency of the serial clock. To obtain the frequency to be set, use the following formula.
When the serial clock is input from off-chip, setting BRGC00 is unnecessary.
fX
2n + 1
Serial clock frequency =
[Hz]
fX: Main system clock oscillation frequency
n: Value in the above table that is determined in the settings of TPS000 to TPS003 (1 ≤ n ≤ 8)
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CHAPTER 13 SERIAL INTERFACE 00
(2) Communication operation
In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units.
transmitted/received bit by bit in synchronization with the serial clock.
Data is
Transmit shift register 00 (TXS00/SIO00) and receive shift register 00 (RXS00) shift operations are
performed in synchronization with the fall of the serial clock (SCK). Then transmit data is held in the SO latch
and output from the SO pin. Also, receive data input to the SI pin is latched in receive buffer register 00
(RXB00/SIO00) on the rise of SCK.
At the end of an 8-bit transfer, the operation of TXS00/SIO00 or RXS00 stops automatically, and the interrupt
request signal (INTCSI00) is generated.
Figure 13-11. 3-Wire Serial I/O Mode Timing
SCK
SI
1
2
3
4
5
6
7
8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SO
INTCSI00
End of transfer
Transfer start at the falling edge of SCK
(3) Transfer start
Serial transfer is started by setting transfer data to transmit shift register 00 (TXS00/SIO00) when the
following two conditions are satisfied.
• Bit 7 (CSIE00) of serial operation mode register 00 (CSIM00) = 1
• Internal serial clock is stopped or SCK is a high level after 8-bit serial transfer.
Caution If CSIE00 is set to 1 after data is written to TXS00/SIO00, transfer does not start.
Termination of 8-bit transfer stops the serial transfer automatically and generates the interrupt request signal
(INTCSI00).
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CHAPTER 14 LCD CONTROLLER/DRIVER
14.1 Functions of LCD Controller/Driver
The functions of the LCD controller/driver of the µPD789407A and 789417A Subseries are as follows.
(1) Automatic output of segment and common signals based on automatic display data memory read
(2) Five different display modes:
• Static
• 1/2 duty (1/2 bias)
• 1/3 duty (1/2 bias)
• 1/3 duty (1/3 bias)
• 1/4 duty (1/3 bias)
(3) Four different frame frequencies, selectable in each display mode
(4) Up to 28 segment signal outputs (S0 to S27) and four common signal outputs (COM0 to COM3)
Of these segment signal outputs, 12 outputs can be switched to I/O ports in 2-output units (P80/S27 to
P87/S20 and P90/S19 to P93/S16).
(5) Voltage divider resistors (for LCD drive voltage generation) that a port itself can contain if so specified with a
mask option
(6) Operation with a subsystem clock
Table 14-1 lists the maximum number of pixels that can be displayed in each display mode.
Table 14-1. Maximum Number of Pixels
Bias Mode
Number of Time Slices
Common Signals
Used
Maximum Number of Pixels
28 (28 segment signals, 1 common signal)Note 1
−
Static
COM0 (COM1 to
COM3)
1/2
2
3
3
4
COM0, COM1
COM0 to COM2
COM0 to COM2
COM0 to COM3
56 (28 segment signals, 2 common signals)Note 2
84 (28 segment signals, 3 common signals)Note 3
1/3
112 (28 segment signals, 4 common signals)Note 4
Notes 1. Three-digit LCD panel, each digit having an 8-segment
2. Seven-digit LCD panel, each digit having a 4-segment
3. Nine-digit LCD panel, each digit having a 3-segment
configuration.
configuration.
configuration.
4. Fourteen-digit LCD panel, each digit having a 2-segment
configuration.
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CHAPTER 14 LCD CONTROLLER/DRIVER
14.2 Configuration of LCD Controller/Driver
The LCD controller/driver consists of the following hardware.
Table 14-2. Configuration of LCD Controller/Driver
Item
Configuration
Display outputs
28 segment signals (16 dedicated segment signals and 12 segment and I/O port signals)
4 common signals (COM0 to COM3)
Control registers
LCD display mode register 0 (LCDM0)
LCD port selector 0 (LPS0)
LCD clock control register 0 (LCDC0)
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Figure 14-1. Block Diagram of LCD Controller/Driver
Internal bus
LCD display mode
register 0 (LCDM0)
LCD clock control register 0
(LCDC0)
LCD port selector 0
(LPS0)
Display data
memory
P8×
P9×
F×××H
F×××H
F×××H
LCDC03 LCDC02 LCDC01 LCDC00
LCDON0 VAON0 LIPS0 LCDM02 LCDM01 LCDM00 LPS05 LPS04 LPS03 LPS02 LPS01 LPS00
Output latch Output latch
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
2
2
3
6
fX
fX
fX
/23
/25
/27
Segment selector
f
LCD
Prescaler
f
LCD
26
f
LCD
f
LCD
f
LCD
29
f
XT
27
28
LCD
3 2 1 0
3 2 1 0
3 2 1 0
LCDCL
Timing
controller
clock
Selector
Selector
Selector
selector
LCDON
LCDON
LCDON
LCD drive
voltage controller
P8
×
output
Segment
driver
P9
×
output Segment
Segment
driver
Common driver
buffer
buffer
driver
V
LC2
V
LC1
V
LC0 BIAS COM0 COM1 COM2 COM3
S×/P8×
S×/P9×
S×
CHAPTER 14 LCD CONTROLLER/DRIVER
14.3 Registers Controlling LCD Controller/Driver
The following three registers are used to control the LCD controller/driver.
• LCD display mode register 0 (LCDM0)
• LCD port selector 0 (LPS0)
• LCD clock control register 0 (LCDC0)
(1) LCD display mode register 0 (LCDM0)
LCDM0 specifies whether to enable display operation. It also specifies the operation mode, LCD drive power
supply, and display mode.
LCDM0 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets LCDM0 to 00H.
Figure 14-2. Format of LCD Display Mode Register 0
Symbol
7
6
5
0
4
3
0
2
1
0
Address
FFB0H
After reset
00H
R/W
R/W
LCDM0 LCDON0 VAON0
LIPS0
LCDM02 LCDM01 LCDM00
LCDON0
Control of LCD display
0
1
Display off (all segment outputs are deselected.)
Display on
VAON0
LCD controller/driver operation modeNote
0
1
Normal operation
Low-voltage operation
LIPS0
LCD drive power supply selection
0
1
LCD drive power is not supplied.
LCD drive power is supplied to the BIAS pin.
LCD controller/driver display mode selection
Number of time slices Bias mode
LCDM02 LCDM01 LCDM00
4
1/3
1/3
1/2
1/2
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
3
2
3
Static
Setting prohibited
Other than above
Note When the LCD display panel is not used, VAON0 and LIPS0 must be fixed to 0 to conserve power.
Caution Before attempting to manipulate VAON0, set LIPS0 and LCDON0 to 0 to turn off the LCD.
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CHAPTER 14 LCD CONTROLLER/DRIVER
(2) LCD port selector 0 (LPS0)
LPS0 controls port and segment signal output switching.
LPS0 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets LPS0 to 00H.
Figure 14-3. Format of LCD Port Selector 0
Symbol
LPS0
7
0
6
0
5
4
3
2
1
0
Address
FFB1H
After reset
00H
R/W
R/W
LPS05 LPS04 LPS03 LPS02 LPS01 LPS00
LPS05
LPS04
LPS03
LPS02
LPS01
LPS00
P93/S16, P92/S17 P91/S18, P90/S19 P87/S20, P86/S21 P85/S22, P84/S23 P83/S24, P82/S25 P81/S26, P80/S27
Used as ports (Pmn)
0
1
Used as segments (S×)
Cautions 1. Bits 6 and 7 must be fixed to 0.
2. Be sure to use segments in sequence from the smallest segment value (LPS05 → LPS04 →
… → LPS00).
Remark m = 8 n = 0 to 7
m = 9 n = 0 to 3
× = 16 to 27
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CHAPTER 14 LCD CONTROLLER/DRIVER
(3) LCD clock control register 0 (LCDC0)
LCDC0 specifies the LCD source clock and LCD clock.
The frame frequency is determined according to the LCD clock and the number of time slices.
LCDC0 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets LCDC0 to 00H.
Figure 14-4. Format of LCD Clock Control Register 0
Symbol
LCDC0
7
0
6
0
5
0
4
3
2
1
0
Address
FFB2H
After reset
00H
R/W
R/W
0
LCDC03 LCDC02 LCDC01 LCDC00
Note
LCDC03 LCDC02
Selection of LCD source clock frequency (fLCD)
0
0
1
1
0
1
0
1
f
f
f
f
X
/27 (39.1 kHz)
XT (32.768 kHz)
X
X
/25 (156.3 kHz)
/23 (625 kHz)
LCDC01 LCDC00
Selection of LCD clock (LCDCL) frequency
0
0
1
1
0
1
0
1
f
f
f
f
LCD/26
LCD/27
LCD/28
LCD/29
Note Specify an LCD source clock (fLCD) frequency of at least 32 kHz.
Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
For example, Table 14-3 lists the frame frequencies used when fXT (32.768 kHz) is supplied to the LCD
source clock (fLCD).
Table 14-3. Frame Frequencies (Hz)
LCD Clock (LCDCL)
fXT/29
fXT/28
fXT/27
fXT/26
Frequency
(64 Hz)
(128 Hz)
(256 Hz)
(512 Hz)
Number of Time Slices
Static
64
32
21
16
128
64
256
128
85
512
256
171
128
2
3
4
43
32
64
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CHAPTER 14 LCD CONTROLLER/DRIVER
14.4 Setting LCD Controller/Driver
Set the LCD controller/driver using the following procedure.
<1> Set the initial values in the LCD display data memory (FA00H to FA1BH).
<2> Set the pins to be used for segment output in LCD port selector 0 (LPS0).
<3> Set the display and operation modes in LCD display mode register 0 (LCDM0).
<4> Set the LCD clock in LCD clock control register 0 (LCDC0).
Subsequent to this procedure, set the data to be displayed in the data memory.
14.5 LCD Display Data Memory
The LCD display data memory is mapped at addresses FA00H to FA1BH. Data in the LCD display data memory
can be displayed on the LCD panel using the LCD controller/driver.
Figure 14-5 shows the relationship between the contents of the LCD display data memory and the
segment/common outputs.
The part of the display data memory not used for display can be used as ordinary RAM.
Figure 14-5. Relationship Between LCD Display Data Memory Contents and Segment/Common Outputs
b7
b6
b5
b4
b3
b2
b1
b0
Address
FA00H
S0
S1
S2
S3
FA01H
FA02H
FA03H
FA09H
FA1AH
FA1BH
S25/P82
S26/P81
S27/P80
COM3 COM2 COM1 COM0
Caution No memory is allocated to the higher 4 bits of the LCD display data memory. Be sure to fix there
bits to 0.
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CHAPTER 14 LCD CONTROLLER/DRIVER
14.6 Common and Segment Signals
Each pixel of the LCD panel turns on when the potential difference between the corresponding common and
segment signals becomes higher than a specific voltage (LCD drive voltage, VLCD). The pixels turn off when the
potential difference becomes lower than VLCD.
Applying DC voltage to the common and segment signals of an LCD panel causes deterioration. To avoid this
problem, this LCD panel is driven by AC voltage.
(1) Common signals
Each common signal is selected sequentially according to a specified number of time slices at the timing
listed in Table 14-4. In the static display mode, the same signal is output to COM0 to COM3.
In the two-time-slice mode, leave the COM2 and COM3 pins open. In the three-time-slice mode, leave the
COM3 pin open.
Table 14-4. COM Signals
COM Signal
Number of Time Slices
COM0
COM1
COM2
COM3
Static display mode
Two-time-slice mode
Three-time-slice mode
Four-time-slice mode
Open
Open
Open
(2) Segment signals
The segment signals correspond to 28 bytes of LCD display data memory (FA00H to FA1BH). Bits 0, 1, 2,
and 3 of each byte are read in synchronization with COM0, COM1, COM2, and COM3, respectively. If a bit
is 1, it is converted to the select voltage, and if it is 0, it is converted to the deselect voltage. The conversion
results are output to the segment pins (S0 to S27). Note that S16 to S27 can also be used as I/O port pins.
Check, with the information given above, what combination of front-surface electrodes (corresponding to the
segment signals) and rear-surface electrodes (corresponding to the common signals) forms display patterns
in the LCD display data memory, and write the bit data that corresponds to the desired display pattern on a
one-to-one basis.
LCD display data memory bits 1 and 2, bits 2 and 3, and bit 3 are not used for LCD display in the static
display, two-time slot, and three-time slot modes, respectively. So these bits can be used for purposes other
than display.
LCD display data memory bits 4 to 7 are fixed to 0.
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CHAPTER 14 LCD CONTROLLER/DRIVER
(3) Output waveforms of common and segment signals
The voltages listed in Table 14-5 are output as common and segment signals.
When both common and segment signals are at the select voltage, a display on-voltage of VLCD is obtained.
The other combinations of the signals correspond to the display off-voltage.
Table 14-5. LCD Drive Voltage
(a) Static display mode
Segment Signal
Select Signal Level
Deselect Signal Level
Common Signal
VSS0/VLC0
VLC0/VSS0
VLC0/VSS0
–VLCD/+VLCD
0 V/0 V
(b) 1/2 bias method
Segment Signal
Select Signal Level
Deselect Signal Level
Common Signal
VSS0/VLC0
VLC0/VSS0
Select signal level
VLC0/VSS0
–VLCD/+VLCD
0 V/0 V
1
+
1
1
2
1
2
Deselect signal level
VLC1 = VLC2
–
VLCD/+
VLCD
VLCD/–
VLCD
2
2
(c) 1/3 bias method
Segment Signal
Select Signal Level
Deselect Signal Level
Common Signal
VSS0/VLC0
VLC1/VLC2
1
1
Select signal level
VLC0/VSS0
VLC2/VLC1
–VLCD/+VLCD
–
–
VLCD/+
VLCD
3
3
1
3
1
3
1
1
Deselect signal level
–
VLCD/+
VLCD
VLCD/+
VLCD
3
3
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Figure 14-6 shows the common signal waveforms, and Figure 14-7 shows the voltages and phases of the common
and segment signals.
Figure 14-6. Common Signal Waveforms
(a) Static display mode
V
V
LC0
SS0
COMn
V
LCD
(Static display)
TF = T
T: One LCD clock period
TF: Frame frequency
(b) 1/2 bias method
V
V
V
LC0
COMn
LC2
SS0
V
LCD
(Two-time slot mode)
TF = 2 × T
V
V
V
LC0
LC2
SS0
COMn
V
LCD
(Three-time slot mode)
TF = 3 × T
T: One LCD clock period
TF: Frame frequency
(c) 1/3 bias method
V
V
V
V
LC0
LC1
LC2
SS0
COMn
V
LCD
(Three-time slot mode)
TF = 3 × T
V
V
V
V
LC0
COMn
LC1
LC2
SS0
V
LCD
(Four-time slot mode)
TF = 4 × T
T: One LCD clock period
TF: Frame frequency
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CHAPTER 14 LCD CONTROLLER/DRIVER
Figure 14-7. Voltages and Phases of Common and Segment Signals
(a) Static display mode
Select
Deselect
V
LC0
V
V
LCD
Common signal
Segment signal
V
V
SS0
LC0
LCD
V
SS0
T
T
T: One LCD clock period
(b) 1/2 bias method
Select
Deselect
VLC0
VLC2
VSS0
VLCD
Common signal
Segment signal
VLC0
VLC2
VSS0
VLCD
T
T
T: One LCD clock period
(c) 1/3 bias method
Select
Deselect
V
LC0
V
LC1
LC2
V
LCD
Common signal
Segment signal
V
VSS0
VLC0
VLC1
VLC2
VLCD
VSS0
T
T
T: One LCD clock period
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14.7 Supplying LCD Drive Voltages VLC0, VLC1, and VLC2
The mask ROM versions (except the µPD78F9418A) of the LCD display can incorporate voltage divider resistors
for generating LCD drive power as specified using a mask option. Incorporating voltage divider resistors can generate
LCD drive voltages that meet each bias method listed in Table 14-6, without using external voltage divider resistors.
The LCD drive voltage can be supplied to the BIAS pin to support various LCD drive voltage levels.
Table 14-6. LCD Drive Voltages (with On-Chip Voltage Divider Resistors)
Bias Method
No Bias (Static)
1/2 Bias Method
1/3 Bias Method
LCD Drive Voltage Pin
VLC0
VLCD
VLCD
VLCD
Note
VLC1
VLC2
VLCD
VLCD
VLCD
2
1
2
2
3
1
3
3
1
3
VLCD
VLCD
Note For the 1/2 bias method, it is necessary to connect the VLC1 and VLC2 pins externally.
Remarks 1. If the BIAS and VLC0 pins are open, VLCD = VDD (if voltage divider resistors are included).
3
5
2. If the BIAS and VLC0 pins are connected, VLCD = VDD.
Figure 14-8 shows examples of generating LCD drive voltages internally according to Table 14-6.
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CHAPTER 14 LCD CONTROLLER/DRIVER
Figure 14-8. Examples of LCD Drive Power Connections (with On-Chip Voltage Divider Resistors)
(a) 1/3 bias method and static display mode
(VDD = 5 V and VLCD = 3 V)
(b) 1/2 bias method
(VDD = 5 V and VLCD = 5 V)
V
DD
VDD
P-ch
2 R
R
P-ch
2 R
LIPS0
LIPS0
BIAS pin
BIAS pin
VLC0
VLC1
VLC2
VLC0
VLC1
VLC2
R
R
R
VLCD
VLCD
R
R
V
SS0
VSS0
V
SS
VSS
V
LCD = 3/5
V
DD
VLCD
=
VDD
(c) 1/3 bias method and static display mode
(VDD = 5 V and VLCD = 5 V)
VDD
P-ch
2 R
R
LIPS0
BIAS pin
VLC0
VLC1
VLC2
VLCD
R
R
VSS0
VSS
VLCD
=
VDD
LIPS0: Bit 4 of LCD display mode register 0 (LCDM0)
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14.8 Display Modes
14.8.1 Static display example
Figure 14-10 shows how the three-digit LCD panel having the display pattern shown in Figure 14-9 is connected to
the segment signals (S0 to S23) and the common signal (COM0) of the µPD789407A or 789417A Subseries chip.
This example displays data "12.3" in the LCD panel. The contents of the display data memory (addresses FA00H to
FA17H) correspond to this display.
The following description focuses on numeral "2." ( ) displayed in the second digit. To display "2." in the LCD
panel, it is necessary to apply the select or deselect voltage to the S8 to S15 pins according to Table 14-7 at the
timing of the common signal COM0; see Figure 14-9 for the relationship between the segment signals and LCD
segments.
Table 14-7. Select and Deselect Voltages (COM0)
Segment
S8
S9
S10
S11
S12
S13
S14
S15
Common
COM0
Select
Deselect
Select
Select
Deselect
Select
Select
Select
According to Table 14-7, it is determined that the bit-0 pattern of the display data memory locations (FA08H to
FA0FH) must be 10110111.
Figure 14-11 shows the LCD drive waveforms of S11 and S12, and COM0. When the select voltage is applied to
S11 at the timing of COM0, an alternate rectangle waveform, +VLCD/−VLCD, is generated to turn on the corresponding
LCD segment.
COM1 to COM3 are supplied with the same waveform as for COM0. So, COM0 to COM3 may be connected
together to increase the driving capacity.
Figure 14-9. Static LCD Display Pattern and Electrode Connections
S8n+3
S
8n+4
S
S
S
S
8n+2
8n+5
COM0
S
8n+6
8n+1
8n
S8n+7
Remark n = 0 to 2
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CHAPTER 14 LCD CONTROLLER/DRIVER
Figure 14-10. Example of Connecting Static LCD Panel
COM 3
COM 2
COM 1
COM 0
Can be connected
together
S 0
FA00H
S 1
1
S 2
2
S 3
3
S 4
4
S 5
5
S 6
6
S 7
7
S 8
8
S 9
9
S 10
S 11
S 12
S 13
S 14
S 15
S 16
S 17
S 18
S 19
S 20
S 21
S 22
S 23
A
B
C
D
E
F
FA10H
1
2
3
4
5
6
7
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Figure 14-11. Static LCD Drive Waveform Examples
TF
V
LC0
SS0
COM0
V
VLC0
VSS0
VLC0
VSS0
S11
S12
+VLCD
COM0 to S11
0
–VLCD
+VLCD
COM0 to S12
0
–VLCD
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14.8.2 Two-time-slice display example
Figure 14-13 shows how the seven-digit LCD panel having the display pattern shown in Figure 14-12 is connected
to the segment signals (S0 to S27) and the common signals (COM0 and COM1) of the µPD789407A or 789417A
Subseries chip. This example displays data "123456.7" in the LCD panel. The contents of the display data memory
(addresses FA00H to FA1BH) correspond to this display.
The following description focuses on numeral "3" ( ) displayed in the fifth digit. To display "3" in the LCD panel, it
is necessary to apply the select or deselect voltage to the S16 to S19 pins according to Table 14-8 at the timing of the
common signals COM0 and COM1; see Figure 14-12 for the relationship between the segment signals and LCD
segments.
Table 14-8. Select and Deselect Voltages (COM0 and COM1)
Segment
S16
S17
S18
S19
Common
COM0
Select
Select
Select
Deselect
Select
Deselect
Select
COM1
Deselect
According to Table 14-8, it is determined that the display data memory location (FA13H) that corresponds to S19
must contain xx10.
Figure 14-14 shows examples of LCD drive waveforms between the S19 signal and each common signal. When
the select voltage is applied to S19 at the timing of COM1, an alternate rectangle waveform, +VLCD/−VLCD, is generated
to turn on the corresponding LCD segment.
Figure 14-12. Two-Time-Slice LCD Display Pattern and Electrode Connections
COM0
S
4n+2
S
4n+1
S
4n+3
S
4n
COM1
Remark n = 0 to 6
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Figure 14-13. Example of Connecting Two-Time-Slice LCD Panel
COM 3
Open
COM 2
Open
COM 1
COM 0
S 0
FA00H
S 1
S 2
S 3
S 4
S 5
S 6
S 7
S 8
S 9
S 10
S 11
S 12
S 13
S 14
S 15
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
S 16
FA10H
S 17
S 18
S 19
S 20
S 21
S 22
S 23
S 24
S 25
S 26
S 27
1
2
3
4
5
6
7
8
9
A
B
×: Can always be used to store any data because the two-time-slice mode is being used.
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Figure 14-14. Two-Time-Slice LCD Drive Waveform Examples (1/2 Bias Method)
T
F
V
V
V
LC0
LC1,2
SS0
COM0
V
V
V
LC0
LC1,2
COM1
SS0
V
V
V
LC0
LC1,2
S19
SS0
+VLCD
+1/2VLCD
COM0 to S19
0
–1/2VLCD
–VLCD
+VLCD
+1/2VLCD
COM1 to S19
0
–1/2VLCD
–VLCD
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14.8.3 Three-time-slice display example
Figure 14-16 shows how the nine-digit LCD panel having the display pattern shown in Figure 14-15 is connected to
the segment signals (S0 to S26) and the common signals (COM0 to COM2) of the µPD789407A or 789417A
Subseries chip. This example displays data "123456.789" in the LCD panel. The contents of the display data memory
(addresses FA00H to FA1AH) correspond to this display.
The following description focuses on numeral "6." ( ) displayed in the fourth digit. To display "6." in the LCD
panel, it is necessary to apply the select or deselect voltage to the S9 to S11 pins according to Table 14-9 at the
timing of the common signals COM0 to COM2; see Figure 14-15 for the relationship between the segment signals and
LCD segments.
Table 14-9. Select and Deselect Voltages (COM0 to COM2)
Segment
S9
S10
S11
Common
COM0
Deselect
Select
Select
Select
Select
Select
Select
−
COM1
COM2
Select
According to Table 14-9, it is determined that the display data memory location (FA09H) that corresponds to S9
must contain x110.
Figures 14-17 and 14-18 show examples of LCD drive waveforms between the S9 signal and each common signal
in the 1/2 and 1/3 bias methods, respectively. When the select voltage is applied to S9 at the timing of COM1 or
COM2, an alternate rectangle waveform, +VLCD/−VLCD, is generated to turn on the corresponding LCD segment.
Figure 14-15. Three-Time-Slice LCD Display Pattern and Electrode Connections
COM0
S3n+1
S3n+2
S3n
COM1
COM2
Remark n = 0 to 8
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CHAPTER 14 LCD CONTROLLER/DRIVER
Figure 14-16. Example of Connecting Three-Time-Slice LCD Panel
COM 3
Open
COM 2
COM 1
COM 0
S 0
FA00H
S 1
S 2
S 3
S 4
S 5
S 6
S 7
S 8
S 9
S 10
S 11
S 12
S 13
S 14
S 15
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
S 16
FA10H
S 17
S 18
S 19
S 20
S 21
S 22
S 23
S 24
S 25
S 26
1
2
3
4
5
6
7
8
9
A
x’: Can be used to store any data because there is no corresponding segment in the LCD panel.
×: Can always be used to store any data because the three-time-slice mode is being used.
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Figure 14-17. Three-Time-Slice LCD Drive Waveform Examples (1/2 Bias Method)
T
F
V
V
V
LC0
LC1,2
SS0
COM0
COM1
V
V
V
LC0
LC1,2
SS0
V
V
V
LC0
LC1,2
SS0
COM2
S9
V
V
V
LC0
LC1,2
SS0
+VLCD
+1/2VLCD
COM0 to S9
COM1 to S9
COM2 to S9
0
–1/2VLCD
–VLCD
+VLCD
+1/2VLCD
0
–1/2VLCD
–VLCD
+VLCD
+1/2VLCD
0
–1/2VLCD
–VLCD
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Figure 14-18. Three-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method)
T
F
V
V
V
V
LC0
LC1
LC2
SS0
COM0
COM1
COM2
S9
V
V
V
V
LC0
LC1
LC2
SS0
V
V
V
V
LC0
LC1
LC2
SS0
V
V
V
V
LC0
LC1
LC2
SS0
+VLCD
+1/3VLCD
0
COM0 to S9
COM1 to S9
COM2 to S9
–1/3VLCD
–VLCD
+VLCD
+1/3VLCD
0
–1/3VLCD
–VLCD
+VLCD
+1/3VLCD
0
–1/3VLCD
–VLCD
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14.8.4 Four-time-slice display example
Figure 14-20 shows how the 14-digit LCD panel having the display pattern shown in Figure 14-19 is connected to
the segment signals (S0 to S27) and the common signals (COM0 to COM3) of the µPD789407A or 789417A
Subseries chip. This example displays data "123456.78901234" in the LCD panel. The contents of the display data
memory (addresses FA00H to FA1BH) correspond to this display.
The following description focuses on numeral "6." ( ) displayed in the ninth digit. To display "6." in the LCD panel,
it is necessary to apply the select or deselect voltage to the S16 and S17 pins according to Table 14-10 at the timing
of the common signals COM0 to COM3; see Figure 14-19 for the relationship between the segment signals and LCD
segments.
Table 14-10. Select and Deselect Voltages (COM0 to COM3)
Segment
S16
S17
Common
COM0
COM1
COM2
COM3
Select
Deselect
Select
Select
Select
Select
Select
Select
According to Table 14-10, it is determined that the display data memory location (FA16H) that corresponds to S16
must contain 1101.
Figure 14-21 shows examples of LCD drive waveforms between the S16 signal and each common signal. When
the select voltage is applied to S16 at the timing of COM0, an alternate rectangle waveform, +VLCD/−VLCD, is generated
to turn on the corresponding LCD segment.
Figure 14-19. Four-Time-Slice LCD Display Pattern and Electrode Connections
S2n
COM0
COM2
COM1
COM3
S2n+1
Remark n = 0 to 13
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Figure 14-20. Example of Connecting Four-Time-Slice LCD Panel
COM 3
COM 2
COM 1
COM 0
S 0
FA00H
S 1
S 2
S 3
S 4
S 5
S 6
S 7
S 8
S 9
S 10
S 11
S 12
S 13
S 14
S 15
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
S 16
FA10H
S 17
S 18
S 19
S 20
S 21
S 22
S 23
S 24
S 25
S 26
S 27
1
2
3
4
5
6
7
8
9
A
B
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Figure 14-21. Four-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method)
TF
V
V
V
V
LC0
LC1
LC2
SS0
COM0
COM1
COM2
COM3
S16
VLC0
VLC1
VLC2
VSS0
VLC0
VLC1
VLC2
VSS0
VLC0
VLC1
VLC2
VSS0
VLC0
VLC1
VLC2
VSS0
+VLCD
+1/3VLCD
0
COM0 to S16
–1/3VLCD
–VLCD
+VLCD
+1/3VLCD
0
COM1 to S16
–1/3VLCD
–VLCD
Remark The waveforms for COM2 to S16 and COM3 to S16 are omitted.
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CHAPTER 15 INTERRUPT FUNCTIONS
15.1 Interrupt Function Types
The following two types of interrupt functions are used.
(1) Non-maskable interrupt
This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top
priority over all other interrupt requests.
A standby release signal is generated.
One interrupt source from the watchdog timer is incorporated as a non-maskable interrupt.
(2) Maskable interrupt
These interrupts undergo mask control. If two or more interrupts with the same priority are simultaneously
generated, each interrupt has a predetermined priority as shown in Table 15-1.
A standby release signal is generated.
Five external interrupt and 11 internal interrupt sources are incorporated as maskable interrupts.
15.2 Interrupt Sources and Configuration
A total of 17 non-maskable and maskable interrupts are incorporated as interrupt sources (see Table
15-1).
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CHAPTER 15 INTERRUPT FUNCTIONS
Table 15-1. Interrupt Source List
Interrupt Type
PriorityNote 1
Interrupt Source
Internal/
External
Vector
Table
Basic
Configuration
TypeNote 2
Address
Name
Trigger
−
Non-maskable
Maskable
INTWDT
Watchdog timer overflow (with
watchdog timer mode 1 selected)
Internal
0004H
(A)
(B)
(C)
0
INTWDT
Watchdog timer overflow (with interval
timer mode selected)
1
2
3
4
5
INTP0
INTP1
INTP2
INTP3
INTSR00
Pin input edge detection
External
0006H
0008H
000AH
000CH
000EH
End of serial interface 00 UART
reception
Internal
(B)
INTCSI00
INTST00
End of serial interface 00 3-wire SIO
transfer reception
6
End of serial interface 00 UART
transmission
0010H
7
8
9
INTWT
Watch timer interrupt
Interval timer interrupt
0012H
0014H
0016H
INTWTI
INTTM00
Generation of matching signal of 8-bit
timer/event counter 00
10
11
12
INTTM01
INTTM02
INTTM50
Generation of matching signal of 8-bit
timer/event counter 01
0018H
001AH
001CH
Generation of matching signal of 8-bit
timer 02
Generation of matching signal of 16-bit
timer 50
13
14
15
INTKR00
INTAD0
Key return signal detection
A/D conversion completion signal
Comparator signal
External
Internal
001EH
0020H
0022H
(C)
(B)
INTCMP0
Notes 1. “Priority” is the priority order when several maskable interrupts are generated at the same time. 0 is the
highest and 15 is the lowest.
2. Basic configuration types (A) to (C) correspond to (A) to (C) in Figure 15-1.
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CHAPTER 15 INTERRUPT FUNCTIONS
Figure 15-1. Basic Configuration of Interrupt Function
(A) Internal non-maskable interrupt
Internal bus
Vector table
address generator
Interrupt request
Standby release signal
(B) Internal maskable interrupt
Internal bus
IE
MK
Vector table
address generator
IF
Interrupt request
Standby release signal
(C) External maskable interrupt
Internal bus
External interrupt mode
register (INTM0, INTM1)
MK
IE
Vector table
address generator
Interrupt
request
Edge
detector
IF
Standby
release signal
IF: Interrupt request flag
IE: Interrupt enable flag
MK: Interrupt mask flag
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15.3 Registers Controlling Interrupt Function
The following five registers are used to control the interrupt functions.
• Interrupt request flag registers 0, 1 (IF0 and IF1)
• Interrupt mask flag registers 0, 1 (MK0 and MK1)
• External interrupt mode registers 0, 1 (INTM0 and INTM1)
• Program status word (PSW)
• Key return mode register 00 (KRM00)
Table 15-2 lists the interrupt request flag and interrupt mask flag names corresponding to interrupt requests.
Table 15-2. Flags Corresponding to Interrupt Request Signal Name
Interrupt Request Signal Name
INTWDT
Interrupt Request Flag
Interrupt Mask Flag
TMIF4
PIF0
TMMK4
PMK0
INTP0
INTP1
PIF1
PMK1
INTP2
PIF2
PMK2
INTP3
PIF3
PMK3
INTSR00/INTCSI00
INTST00
INTWT
SRIF00
STIF00
WTIF
SRMK00
STMK00
WTMK
INTWTI
WTIIF
TMIF00
TMIF01
TMIF02
TMIF50
KRIF00
ADIF0
CMPIF0
WTIMK
TMMK00
TMMK01
TMMK02
TMMK50
KRMK00
ADMK0
CMPMK0
INTTM00
INTTM01
INTTM02
INTTM50
INTKR00
INTAD0
INTCMP0
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CHAPTER 15 INTERRUPT FUNCTIONS
(1) Interrupt request flag registers 0, 1 (IF0 and IF1)
The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction
is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request
or upon RESET input.
IF0 and IF1 are set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets IF0 and IF1 to 00H.
Figure 15-2. Format of Interrupt Request Flag Register
Address
FFE0H
After reset
00H
R/W
R/W
<7> <6> <5> <4> <3> <2> <1> <0>
WTIF STIF00 SRIF00 PIF3 PIF2 PIF1 PIF0 TMIF4
Symbol
IF0
<7> <6> <5> <4> <3> <2> <1> <0>
CMPIF0 ADIF0 KRIF00 TMIF50 TMIF02 TMIF01 TMIF00 WTIIF
IF1
FFE1H
00H
R/W
Interrupt request flag
XXIFX
0
1
No interrupt request signal is generated
Interrupt request signal is generated; Interrupt request state
Cautions 1. The TMIF4 flag is R/W enabled only when the watchdog timer is used as an interval timer. If
watchdog timer mode 1 or 2 is used, set the TMIF4 flag to 0.
2. Because port 2 has an alternate function as an external interrupt input, when the output level
is changed by specifying the output mode of the port function, an interrupt request flag is
set. Therefore, the interrupt mask flag should be set to 1 before using the output mode.
3. If an interrupt is acknowledged, the interrupt request flag is automatically cleared before the
interrupt routine is entered.
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(2) Interrupt mask flag registers 0, 1 (MK0 and MK1)
The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service.
MK0 and MK1 are set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets MK0 and MK1 to FFH.
Figure 15-3. Format of Interrupt Mask Flag Register
<7> <6> <5> <4> <3> <2> <1> <0>
WTMK STMK00 SRMK00 PMK3 PMK2 PMK1 PMK0 TMMK4
Address
FFE4H
After reset
FFH
R/W
R/W
Symbol
MK0
<7> <6> <5> <4> <3> <2> <1> <0>
MK1
CMPMK0 ADMK0 KRMK00 TMMK50 TMMK02 TMMK01 TMMK00 WTIMK
FFE5H
FFH
R/W
XXMKX
Interrupt servicing control
0
1
Interrupt servicing enabled
Interrupt servicing disabled
Cautions 1. If the TMMK4 flag is read when the watchdog timer is used in watchdog timer mode 1 or 2, its
value becomes undefined.
2. Because port 2 has an alternate function as an external interrupt input, when the output level
is changed by specifying the output mode of the port function, an interrupt request flag is
set. Therefore, the interrupt mask flag should be set to 1 before using the output mode.
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CHAPTER 15 INTERRUPT FUNCTIONS
(3) External interrupt mode register 0 (INTM0)
This register is used to specify a valid edge for INTP0 to INTP2.
INTM0 is set using an 8-bit memory manipulation instruction.
RESET input sets INTM0 to 00H.
Figure 15-4. Format of External Interrupt Mode Register 0
Address
FFECH
After reset
00H
R/W
R/W
7
6
5
4
3
2
1
0
0
0
Symbol
INTM0
ES21 ES20 ES11 ES10 ES01 ES00
ES21 ES20
INTP2 valid edge selection
INTP1 valid edge selection
INTP0 valid edge selection
Falling edge
0
0
1
1
0
1
0
1
Rising edge
Setting prohibited
Both rising and falling edges
ES11 ES10
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
ES00
ES01
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
Cautions 1. Bits 0 and 1 must be fixed to 0.
2. Before setting the INTM0 register, be sure to set xxMKx of the relevant interrupt mask flag to
1 to disable interrupts. After that, clear the interrupt mask flag (xxMKx = 0) to enable
interrupts after clearing the interrupt request flag (xxIFx = 0).
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(4) External interrupt mode register 1 (INTM1)
INTM1 is used to specify a valid edge for INTP3 and INTCMP0.
INTM1 is set using an 8-bit memory manipulation instruction.
RESET input sets INTM1 to 00H.
Figure 15-5. Format of External Interrupt Mode Register 1
Symbol
7
6
5
0
4
0
3
0
2
0
1
0
Address
FFEDH
After reset
00H
R/W
R/W
INTM1 ES61 ES60
ES31 ES30
ES61 ES60
INTCMP0 valid edge selection
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
ES31 ES30
INTP3 valid edge selection
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
Cautions 1. Bits 2 to 5 must be fixed to 0.
2. Before setting INTM1, set the corresponding interrupt mask flag register to 1 to disable
interrupts. After that, clear (0) the corresponding interrupt request flag to enable interrupts,
then clear the corresponding interrupt mask flag register.
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CHAPTER 15 INTERRUPT FUNCTIONS
(5) Program status word (PSW)
The program status word is a register used to hold the instruction execution result and the current status for
interrupt requests. The IE flag to set maskable interrupt enable/disable is mapped to the PSW.
Besides 8-bit unit read/write, this register can carry out operations via bit manipulation instructions and
dedicated instructions (EI, DI). When a vectored interrupt is acknowledged, the PSW is automatically saved
into a stack, and the IE flag is reset to 0.
RESET input sets the PSW to 02H.
Figure 15-6. Configuration of Program Status Word
After reset
02H
7
6
Z
5
0
4
3
0
2
0
1
1
0
Symbol
PSW
IE
AC
CY
Used when normal instruction is executed
IE
0
Interrupt acknowledge enable/disable
Disabled
Enabled
1
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(6) Key return mode register 00 (KRM00)
This register sets the pin that detects a key return signal (falling edge of port 4).
KRM00 is set using a 1-bit or 8-bit memory manipulation instruction.
Bit 0 (KRM000) is set in 4-bit units for KR0/P40 to KR3/P43 pins. Bits 4 and 5 (KRM004 and KRM005) are
set in 1-bit units for KR4/P44 and KR5/P45 pins, respectively.
RESET input sets KRM00 to 00H.
Figures 15-7 and 15-8 show the format of key return mode register 00 and the block diagram of the falling
edge detector, respectively.
Figure 15-7. Format of Key Return Mode Register 00
7
0
6
0
5
4
3
0
2
0
1
0
0
Symbol
KRM00
Address
FFF5H
After reset
00H
R/W
R/W
KRM005 KRM004
KRM000
KRM00n
Key return signal detection selection
0
1
No detection
Detection (detecting falling edge of port 4)
Cautions 1. Bits 1 to 3, 6, and 7 must be fixed to 0.
2. When the KRM00 register is set to 1, a pull-up resistor is connected automatically. However,
the pull-up resistor is cut if the pin is in output mode.
3. Before setting KRM00, always set bit 5 of MK1 (KRMK00 = 1) to disable interrupts in advance.
After setting KRM00, clear bit 5 of MK1 (KRMK00 = 0) after clearing bit 5 of IF1 (KRIF00 = 0) to
enable interrupts.
4. The key return signal cannot be detected while even one of the pins that specify detection of
the key return signal is low, even if a falling edge is generated at other key return pins.
Remark n = 0, 4, 5
Figure 15-8. Block Diagram of Falling Edge Detector
Key return mode register 00 (KRM00)
Note
P40/KR0
P41/KR1
P42/KR2
P43/KR3
P44/KR4
P45/KR5
Falling edge detector
KRMK
KRIF00 set signal
Standby release
signal
Note Selector that selects the pin used for falling edge input
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CHAPTER 15 INTERRUPT FUNCTIONS
15.4 Operation of Interrupt Servicing
15.4.1 Non-maskable interrupt acknowledgment operation
The non-maskable interrupt is unconditionally acknowledged even when interrupts are disabled. It is not subject to
interrupt priority control and takes precedence over all other interrupts.
When the non-maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order,
the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.
Caution During non-maskable interrupt servicing program execution, do not input another non-maskable
interrupt request; if it is input, the servicing program will be interrupted and the new non-
maskable interrupt request will be acknowledged.
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Figure 15-9. Flowchart of Non-Maskable Interrupt Request Acknowledgment
Start
WDTM4 = 1
No
(watchdog timer mode
is selected)
Interval timer
Yes
No
No
WDT
overflows
Yes
WDTM3 = 0
(non-maskable interrupt
is selected)
Reset processing
Yes
Interrupt request is generated
Interrupt servicing is started
WDTM: Watchdog timer mode register
WDT: Watchdog timer
Figure 15-10. Timing of Non-Maskable Interrupt Request Acknowledgment
Saving PSW and PC, and
jump to interrupt servicing
CPU processing
TMIF4
Instruction
Instruction
Interrupt servicing program
Figure 15-11. Non-Maskable Interrupt Request Acknowledgment
Main routine
First interrupt servicing
NMI request
(second)
NMI request
(first)
Second interrupt servicing
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CHAPTER 15 INTERRUPT FUNCTIONS
15.4.2 Maskable interrupt acknowledgment operation
A maskable interrupt can be acknowledged when the interrupt request flag is set to 1 and the corresponding
interrupt mask flag is cleared to 0. A vectored interrupt is acknowledged in the interrupt enabled status (when the IE
flag is set to 1).
The time required to start the interrupt servicing after a maskable interrupt request has been generated is as
follows:
Table 15-3. Time from Generation of Maskable Interrupt Request to Servicing
Minimum Time
Maximum TimeNote
19 clocks
9 clocks
Note The wait time is maximum when an interrupt request is generated immediately before
the BT or BF instruction.
1
Remark 1 clock:
(fCPU: CPU clock)
fCPU
When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting
from the one assigned the highest priority by the priority specification flag.
An interrupt held pending is acknowledged when the status in which it can be acknowledged is set.
Figure 15-12 shows the algorithm of acknowledging interrupts.
When a maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order, the IE
flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the PC, and
execution branches.
To restore from interrupt servicing, use the RETI instruction.
Figure 15-12. Interrupt Acknowledgment Program Algorithm
Start
No
xxIF = 1 ?
Yes (interrupt request generated)
No
xxMK = 0 ?
Yes
Interrupt request pending
Interrupt request pending
No
IE = 1 ?
Yes
Vectored interrupt
servicing
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Figure 15-13. Interrupt Request Acknowledgment Timing (Example: MOV A, r)
8 clocks
Clock
Saving PSW and PC, and
jump to interrupt servicing
MOV A, r
Interrupt servicing program
CPU
Interrupt request
If the interrupt request has generated an interrupt request flag (XXIF) by the time the instruction clocks under
execution, n clocks (n = 4 to 10), are n − 1, interrupt request acknowledgment processing will start following the
completion of the instruction under execution. Figure 15-13 shows an example using the 8-bit data transfer instruction
MOV A, r. Because this instruction is executed in 4 clocks, if an interrupt request is generated between the start of
execution and the 3rd clock, interrupt request acknowledgment processing will take place following the completion of
MOV A, r.
Figure 15-14. Interrupt Request Acknowledgment Timing
(When Interrupt Request Flag Is Generated in Final Clock Under Execution)
8 clocks
Clock
Interrupt servicing
program
Saving PSW and PC, and
jump to interrupt servicing
NOP
MOV A, r
CPU
Interrupt request
If the interrupt request flag (XXIF) is generated in the final clock of the instruction, interrupt request
acknowledgment processing will begin after execution of the next instruction is complete.
Figure 15-14 shows an example whereby an interrupt request was generated in the 2nd clock of NOP (a 2-clock
instruction). In this case, the interrupt request will be processed after execution of MOV A, r, which follows NOP, is
complete.
Caution When interrupt request flag registers 0 and 1 (IF0 and IF1) or interrupt mask flag registers 0 and
1 (MK0 and MK1) are being accessed, interrupt requests will be held pending.
15.4.3 Multiple interrupt servicing
Processing in which another interrupt request is acknowledged while an interrupt request is serviced is called
multiple interrupt servicing.
Multiple interrupts are not performed unless an interrupt request is enabled (IE = 1) (except non-maskable interrupt
request). The other interrupt request is disabled (IE = 0) at the time when an interrupt request is acknowledged.
Therefore, it is necessary to set (1) the IE flag to realize the interrupt enable state using an EI instruction during
interrupt request servicing in order to enable multiple interrupt servicing.
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CHAPTER 15 INTERRUPT FUNCTIONS
Figure 15-15. Example of Multiple Interrupt
Example 1. Acknowledging multiple interrupts
INTxx processing
INTyy processing
Main processing
IE = 0
IE = 0
EI
EI
INTxx
INTyy
RETI
RETI
The interrupt request INTyy is acknowledged and multiple interrupts are performed during the interrupt INTxx
processing. Before each interrupt request is acknowledged, the EI instruction is issued and the interrupt request is
enabled.
Example 2. Multiple interrupts are not performed because interrupts are disabled
INTxx processing
INTyy processing
Main processing
EI
IE = 0
INTyy is held pending
INTyy
RETI
INTxx
IE = 0
RETI
Interrupt requests are disabled (the EI instruction is not issued) in the interrupt INTxx processing. The interrupt
request INTyy is not acknowledged and multiple interrupts are not performed. INTyy is held pending and is
acknowledged after INTxx servicing is completed.
IE = 0: Interrupt request disabled
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15.4.4 Putting interrupt requests on hold
If an interrupt (such as a maskable, non-maskable, or external interrupt) is requested when a certain type of
instruction is being executed, the interrupt request will not be acknowledged until the instruction is completed. Such
instructions include:
• Instructions that manipulate interrupt request flag registers 0, 1 (IF0 and IF1)
• Instructions that manipulate interrupt mask flag registers 0, 1 (MK0 and MK1)
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CHAPTER 16 STANDBY FUNCTION
16.1 Standby Function and Configuration
16.1.1 Standby function
The standby function is used to reduce the power consumption of the system and can be effected in the following
two modes:
(1) HALT mode
This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the
CPU. The system clock oscillator continues oscillating. This mode does not reduce the power consumption
as much as the STOP mode, but is useful for resuming processing immediately when an interrupt request is
generated, or for intermittent operations.
(2) STOP mode
This mode is set when the STOP instruction is executed. The STOP mode stops the main system clock
oscillator and stops the entire system. The power consumption of the CPU can be substantially reduced in
this mode.
The data memory can be retained at the low voltage (VDD = 1.8 V). Therefore, this mode is useful for
retaining the contents of the data memory at an extremely low current.
The STOP mode can be released by an interrupt request, so that this mode can be used for intermittent
operation. However, some time is required until the system clock oscillator stabilizes after the STOP mode
has been released. If processing must be resumed immediately by using an interrupt request, therefore, use
the HALT mode.
In both modes, the previous contents of the registers, flags, and data memory before setting the standby mode are
all retained. In addition, the statuses of the output latch of the I/O ports and output buffer are also retained.
Caution To set the STOP mode, be sure to stop the operations of the peripheral hardware, and then
execute the STOP instruction.
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CHAPTER 16 STANDBY FUNCTION
16.1.2 Standby function control register
The wait time after the STOP mode is released upon interrupt request until oscillation stabilizes is controlled by the
oscillation stabilization time selection register (OSTS).
OSTS is set using an 8-bit memory manipulation instruction.
RESET input sets OSTS to 04H. However, it takes 215/fX, not 217/fX, until the STOP mode is released by RESET
input.
Figure 16-1. Format of Oscillation Stabilization Time Selection Register
7
0
6
0
5
0
4
0
3
0
2
1
0
Symbol
OSTS
Address
FFFAH
After reset
04H
R/W
R/W
OSTS2 OSTS1 OSTS0
OSTS2 OSTS1 OSTS0
Oscillation stabilization time selection
212/f
215/f
217/f
X
X
X
µ
(819 s)
0
0
1
0
1
0
0
0
0
(6.55 ms)
(26.2 ms)
Other than above
Setting prohibited
Caution The wait time after the STOP mode is released does not include the time from STOP mode
release to clock oscillation start (“a” in the figure below), regardless of release by RESET input
or by interrupt generation.
STOP mode release
X1 pin voltage
waveform
a
VSS0, VSS1
Remarks 1. f
X
: Main system clock oscillation frequency
2. The parenthesized values apply to operation at f
X
= 5.0 MHz.
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CHAPTER 16 STANDBY FUNCTION
16.2 Operation of Standby Function
16.2.1 HALT mode
(1) HALT mode
The HALT mode is set by executing the HALT instruction.
The operation status in the HALT mode is shown in the following table.
Table 16-1. HALT Mode Operating Status
Item
HALT Mode Operation Status While
Main System Clock Is Running
HALT Mode Operation Status While
Subsystem Clock Is Running
While the subsystem
clock is running
While the subsystem
clock is not running
While the main system
clock is running
While the main system
clock is not running
Main system clock
generator
Oscillation enabled
Does not run.
CPU
Operation stopped
Port (output latch)
16-bit timer (TM50)
Remains in the state existing before the selection of HALT mode.
Operation enabled
Operation stopped
8-bit timer/event counters Operation enabled
(TM00 and TM01)
Operation enabledNote 1
8-bit timer (TM02)
Watch timer
Operation enabled
Operation enabled
Operation enabled
Operation enabled
Operation stopped
Operation enabled
Operation enabledNote 5
Operation enabledNote 6
Operation enabledNote 2
Operation enabledNote 2
Operation enabled
Operation enabled
Operation enabledNote 3
Operation enabledNote 3
Operation stopped
Operation enabledNote 4
Watchdog timer
Serial interface
A/D converter
LCD controller/driver
Comparator
Operation enabledNote 2
Operation enabled
Operation enabledNote 3
External interrupt
Notes 1. Operation is enabled only when TI0 or TI1 is selected as the count clock.
2. Operation is enabled while the main system clock is selected.
3. Operation is enabled while the subsystem clock is selected.
4. Operation is enabled in both 3-wire serial I/O and UART modes while an external clock is being used.
5. Operation is enabled while TM02 is operating, or as an external interrupt.
6. Maskable interrupt that is not masked
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(2) Releasing HALT mode
The HALT mode can be released by the following three types of sources:
(a) Releasing by unmasked interrupt request
The HALT mode is released by an unmasked interrupt request. In this case, if interrupts are enabled to
be acknowledged, vectored interrupt servicing is performed. If interrupts are disabled, the instruction at
the next address is executed.
Figure 16-2. Releasing HALT Mode by Interrupt
HALT
instruction
Wait
Wait
Standby
release signal
Operation
mode
HALT mode
Operation mode
Oscillation
Clock
Remarks 1. The broken lines indicate the case where the interrupt request that has released the standby mode
is acknowledged.
2. The wait time is as follows:
• When vectored interrupt servicing is performed:
• When vectored interrupt servicing is not performed:
9 to 10 clocks
1 to 2 clocks
(b) Releasing by non-maskable interrupt request
The HALT mode is released regardless of whether interrupts are enabled or disabled, and vectored
interrupt servicing is performed.
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CHAPTER 16 STANDBY FUNCTION
(c) Releasing by RESET input
When the HALT mode is released by the RESET signal, execution branches to the reset vector address
in the same manner as the ordinary reset operation, and program execution is started.
Figure 16-3. Releasing HALT Mode by RESET Input
Wait
X
HALT
instruction
(215/f
: 6.55 ms)
RESET
signal
Oscillation
stabilization
wait status
Reset
period
Operation
mode
Operation
mode
HALT mode
Oscillation
Oscillation
stops
Oscillation
Clock
Remarks 1. f
X
: Main system clock oscillation frequency
2. The parenthesized values apply to operation at f
X
= 5.0 MHz.
Table 16-2. Operation After Release of HALT Mode
Releasing Source
MKxx
IE
Operation
Maskable interrupt request
0
0
0
1
x
x
−
Executes next address instruction
Executes interrupt servicing
Retains HALT mode
1
−
Non-maskable interrupt request
RESET input
Executes interrupt servicing
Reset processing
-−-
x: Don’t care
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16.2.2 STOP mode
(1) Setting and operation status of STOP mode
The STOP mode is set by executing the STOP instruction.
Caution Because the standby mode can be released by an interrupt request signal, the standby
mode is released as soon as it is set if there is an interrupt source whose interrupt request
flag is set and interrupt mask flag is reset. When the STOP mode is set, therefore, the
HALT mode is set immediately after the STOP instruction has been executed, the wait time
set by the oscillation stabilization time selection register (OSTS) elapses, and then an
operation mode is set.
The operation status in the STOP mode is shown in the following table.
Table 16-3. STOP Mode Operating Status
Item
STOP Mode Operation Status While Main System Clock Is Running
While the subsystem clock is running While the subsystem clock is not running
Main system clock generator Oscillation stopped
CPU
Operation stopped
Port (output latch)
16-bit timer (TM50)
Remains in the state existing before the selection of STOP mode.
Operation stopped
8-bit timer/event counter
(TM00 and TM01)
Operation enabledNote 1
8-bit timer (TM02)
Watch timer
Operation enabledNote 2
Operation enabledNote 2
Operation stopped
Operation stopped
Operation stopped
Watchdog timer
Serial interface
A/D converter
Operation enabledNote 3
Operation stopped
LCD controller/driver
Comparator
Operation enabledNote 2
Operation enabledNotes 5, 6
Operation enabledNote 4
Operation stopped
Operation enabledNote 6
External interrupt
Notes 1. Operation is enabled only when TI0 or TI1 is selected as the count clock.
2. Operation is enabled while the subsystem clock is selected.
3. Operation is enabled in both 3-wire serial I/O and UART modes while an external clock is being used.
4. Maskable interrupt that is not masked
5. Operation is enabled while TM02 is running.
6. Operation is enabled as an external interrupt.
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CHAPTER 16 STANDBY FUNCTION
(2) Releasing STOP mode
The STOP mode can be released by the following two types of sources:
(a) Releasing by unmasked interrupt request
The STOP mode can be released by an unmasked interrupt request. In this case, if interrupts are
enabled to be acknowledged, vectored interrupt servicing is performed, after the oscillation stabilization
time has elapsed. If interrupts are disabled, the instruction at the next address is executed.
Figure 16-4. Releasing STOP Mode by Interrupt
Wait
STOP
instruction
(set time by OSTS)
Standby
release signal
Oscillation stabilization
Operation
mode
Operation
mode
wait status
STOP mode
Oscillation
stops
Oscillation
Oscillation
Clock
Remark The broken lines indicate the case where the interrupt request that has released the standby mode is
acknowledged.
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CHAPTER 16 STANDBY FUNCTION
(b) Releasing by RESET input
When the STOP mode is released by the RESET signal, the reset operation is performed after the
oscillation stabilization time has elapsed.
Figure 16-5. Releasing STOP Mode by RESET Input
Wait
X
STOP
instruction
(215/f
: 6.55 ms)
RESET
signal
Oscillation
stabilization
wait status
Operation
mode
Reset
period
Operation
mode
STOP mode
Oscillation
Oscillation
stops
Oscillation
Clock
Remarks 1. f
X
: Main system clock oscillation frequency
2. The parenthesized values apply to operation at f
X
= 5.0 MHz.
Table 16-4. Operation After Release of STOP Mode
Releasing Source
MKxx
IE
Operation
Maskable interrupt request
0
0
1
−
0
1
Executes next address instruction
Executes interrupt servicing
Retains STOP mode
x
-−-
RESET input
Reset processing
x: Don’t care
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CHAPTER 17 RESET FUNCTION
The following two operations are available to generate reset signals.
(1) External reset input via RESET pin
(2) Internal reset by program loop time detected by the watchdog timer
The external and internal resets have no functional differences. In both cases, program execution starts at the
address at 0000H and 0001H by RESET input.
When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware
item is set to the status shown in Table 17-1. Each pin is high impedance during reset input or during the oscillation
stabilization time just after reset release.
When a high level is input to the RESET pin, the reset is released and program execution is started after the
oscillation stabilization time (215/fx) has elapsed. The reset applied by the watchdog timer overflow is automatically
released after reset, and program execution is started after the oscillation stabilization time (215/fx) has elapsed (see
Figures 17-2 through 17-4).
Cautions 1. For an external reset, input a low level for 10 µs or more to the RESET pin.
2. When the STOP mode is released by reset, the STOP mode contents are held during reset
input. However, the port pins become high impedance.
Figure 17-1. Block Diagram of Reset Function
RESET
Reset signal
Reset controller
Over-
flow
Interrupt function
Count clock
Watchdog timer
Stop
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CHAPTER 17 RESET FUNCTION
Figure 17-2. Reset Timing by RESET Input
X1
Oscillation
During normal
operation
Reset period
stabilization
Normal operation
(reset processing)
(oscillation stops)
time wait
RESET
Internal
reset signal
Delay
Delay
Hi-Z
Port pin
Figure 17-3. Reset Timing by Overflow in Watchdog Timer
X1
Oscillation
stabilization
time wait
Reset period
(oscillation
continues)
During normal
operation
Normal operation
(reset processing)
Overflow in
watchdog timer
Internal
reset signal
Hi-Z
Port pin
Figure 17-4. Reset Timing by RESET Input in STOP Mode
X1
STOP instruction execution
Oscillation
During normal
operation
Stop status
Reset period
Normal operation
(reset processing)
stabilization
time wait
(oscillation stops)
(oscillation stops)
RESET
Internal
reset signal
Delay
Delay
Hi-Z
Port pin
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CHAPTER 17 RESET FUNCTION
Table 17-1. Hardware Status After Reset (1/2)
Hardware
Status After Reset
Program counter (PC)Note 1
The contents of reset
vector tables (0000H
and 0001H) are set.
Stack pointer (SP)
Program status word (PSW)
RAM
Undefined
02H
Data memory
UndefinedNote 2
UndefinedNote 2
00H
General-purpose registers
Ports (P0, P2, P4, P5, P8, and P9) (Output latch)
Port mode registers (PM0, PM2, PM4, PM5, PM8, and PM9)
Pull-up resistor option registers (PU0 to PU2)
Processor clock control register (PCC)
FFH
00H
02H
Suboscillation mode register (SCKM)
00H
Subclock control register (CSS)
00H
Oscillation stabilization time selection register (OSTS)
04H
16-bit timer
Timer counter (TM50)
0000H
FFFFH
Undefined
00H
Compare register (CR50)
Capture register (TCP50)
Mode control register (TMC50)
Timer counters (TM00, TM01, and TM02)
Compare registers (CR00, CR01, and CR02)
Mode control registers (TMC00, TMC01, and TMC02)
Mode control register (WTM)
8-bit timer/event counter
00H
Undefined
00H
Watch timer
00H
Watchdog timer
Timer clock selection register (TCL2)
Mode register (WDTM)
00H
00H
A/D converter
Comparator
Mode register (ADM0)
00H
A/D input selection register (ADS0)
A/D conversion result register (ADCR0)
Mode register (CMPRM0)
00H
Undefined
00H
Notes 1. During reset input and oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined.
All other hardware remains unchanged after reset.
2. The post-reset values are retained in the standby mode.
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Table 17-1. Hardware Status After Reset (2/2)
Hardware
Status After Reset
00H
Serial interface
Mode register (CSIM00)
Asynchronous serial interface mode register (ASIM00)
Asynchronous serial interface status register (ASIS00)
Baud rate generator control register (BRGC00)
Transmit shift register (TXS00)
00H
00H
00H
FFH
Undefined
00H
Receive buffer register (RXB00)
LCD controller/driver
Interrupts
LCD display mode register (LCDM0)
LCD port selector (LPS0)
00H
LCD clock control register (LCDC0)
Request flag registers (IF0 and IF1)
Mask flag registers (MK0 and MK1)
External interrupt mode registers (INTM0 and INTM1)
Key return mode register (KRM00)
00H
00H
FFH
00H
00H
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CHAPTER 18 µPD78F9418A
The µPD78F9418A is a version with the internal ROM of the mask ROM version replaced by flash memory. The
differences between the µPD78F9418A and the mask ROM versions are shown in Table 18-1.
Table 18-1. Differences Between µPD78F9418A and Mask ROM Versions
Item
Flash Memory Version
Mask ROM Version
µPD78F9418A
µPD789405A
µPD789415A
µPD789406A
µPD789416A
µPD789407A
µPD789417A
Internal memory
Pull-up resistor
ROM
32 KB (Flash memory)
512 bytes
12 KB
16 KB
24 KB
High-speed RAM
LCD data RAM
28 bytes
32 (software control only)
Not provided
36 (software control: 32, mask option control: 4)
Can be specified on-chip by mask option
Provided
Divider resistor for LCD driving
IC pin
Not provided
VPP pin
Provided
Not provided
Electrical specifications
Refer to CHAPTER 21 ELECTRICAL SPECIFICATIONS.
Cautions 1. There are differences in noise immunity and noise radiation between the flash memory and
mask ROM versions. When pre-producing an application set with the flash memory version
and then mass-producing it with the mask ROM version, be sure to conduct sufficient
evaluations for the commercial samples (not engineering samples) of the mask ROM version.
2. When A/D conversion result register 0 (ADCR0) is used as the 8-bit A/D converter
(µPD789407A Subseries), ADCR0 will be manipulated by an 8-bit memory manipulation
instruction. When used as the 10-bit A/D converter (µPD789417A Subseries), ADCR0 will be
manipulated by a 16-bit memory manipulation instruction.
However, when the µPD78F9418A is used as the flash memory version of the µPD789405A,
789406A, and 789407A, ADCR0 can be manipulated by an 8-bit memory manipulation
instruction. In this case, use the object file assembled in the µPD789405A, 789406A, and
789407A.
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CHAPTER 18 µPD78F9418A
18.1 Flash Memory Characteristics
Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FL-
PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the µPD78F9418A mounted on the
target system (on-board). A flash memory program adapter (FA adapter), which is a target board used exclusively for
programming, is also provided.
Remark FL-PR3, FL-PR4, and the program adapter are products made by Naito Densei Machida Mfg. Co., Ltd.
(TEL +81-45-475-4191).
Programming using flash memory has the following advantages.
• Software can be modified after the microcontroller is solder-mounted on the target system.
• Distinguishing software facilities small-quantity, varied model production
• Easy data adjustment when starting mass production
18.1.1 Programming environment
The following shows the environment required for µPD78F9418A flash memory programming.
When Flashpro III (part no. FL-PR3, PG-FP3) or Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated
flash programmer, a host machine is required to control the dedicated flash programmer. Communication between the
host machine and flash programmer is performed via RS-232C/USB (Rev. 1.1).
For details, refer to the manuals for Flashpro III/Flashpro IV.
Remark USB is supported by Flashpro IV only.
Figure 18-1. Environment for Writing Program to Flash Memory
V
PP
V
DD
SS
RS-232C
USB
V
RESET
3-wire serial I/O,
UART
Dedicated flash
programmer
µ
PD78F9418A
or pseudo 3-wire
Host machine
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CHAPTER 18 µPD78F9418A
18.1.2 Communication mode
Use the communication mode shown in Table 18-2 to perform communication between the dedicated flash
programmer and µPD78F9418A.
Table 18-2. Communication Mode List
Communication
Mode
TYPE SettingNote 1
CPU Clock
In Flashpro On Target Board
Pins Used
Number of VPP
Pulses
COMM PORT
SIO ch-0
SIO Clock
100 Hz to
Multiple
Rate
3-wire serial
I/O
1, 2, 4, 5
MHzNotes 2, 3
1 to 5 MHzNote 2 1.0
SI/RxD/P22
0
8
(3-wire, sync.) 1.25 MHzNote 2
SO/TxD/P21
SCK/ASCK/P20
UART
UART ch-0
(Async.)
4,800 to
5 MHzNote 5
4.91 or
5 MHzNote 2
1.0
RxD/SI/P22
TxD/SO/P21
76,800 bps
Notes 2, 4
Pseudo 3-wire
Port A
100 Hz to
1 kHz
1, 2, 4, 5
MHzNotes 2, 3
1 to 5 MHzNote 2 1.0
P01
P02
P00
12
13
(Pseudo-
3 wire)
Port B
P40/KR0
P41/KR1
P42/KR2
(Pseudo-
3 wire)
Notes 1. Selection items for TYPE settings on the dedicated flash programmer (Flashpro III (part no. FL-PR3,
PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)).
2. The possible setting range differs depending on the voltage. For details, refer to CHAPTER 21
ELECTRICAL SPECIFICATIONS.
3. 2 or 4 MHz only for Flashpro III
4. Because signal wave slew also affects UART communication, in addition to the baud rate error,
thoroughly evaluate the slew and baud rate error.
5. Only for Flashpro IV. However, when using Flashpro III, be sure to select the clock of the resonator on
the board. UART cannot be used with the clock supplied by Flashpro III.
Figure 18-2. Communication Mode Selection Format
10 V
VPP
VDD
1
2
n
VSS
VPP pulses
VDD
VSS
RESET
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Figure 18-3. Example of Connection with Dedicated Flash Programmer
(a) 3-wire serial I/O
Dedicated flash programmer
PD78F9418A
µ
VPP1
VDD
V
PP
V
DD0, VDD1
RESET
SCK
RESET
SCK
SI
SO
SI
SO
CLKNote 1
X1
GND
V
SS0, VSS1
(b) UART
Dedicated flash programmer
PD78F9418A
µ
VPP1
VDD
V
PP
DD0, VDD1
V
RESET
SO
RESET
RXD
SI
TXD
CLKNotes 1, 2
X1
GND
V
SS0, VSS1
(c) Pseudo 3-wire (when P0 is used)
Dedicated flash programmer
µ
PD78F9418A
VPP1
VDD
VPP
VDD0, VDD1
RESET
SCK
RESET
P00 (serial clock)
P02 (serial input)
P01 (serial output)
X1
SO
SI
CLKNote 1
GND
VSS0, VSS1
Notes 1. Connect this pin when the system clock is supplied from the dedicated flash programmer. If a resonator
is already connected to the X1 pin, do not connect to the CLK pin.
2. When using UART with Flashpro III, the clock of the resonator connected to the X1 pin must be used,
so do not connect to the CLK pin.
Caution The VDD pin, if already connected to the power supply, must be connected to the VDD pin of the
dedicated flash programmer. When using the power supply connected to the VDD pin, supply
voltage before starting programming.
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CHAPTER 18 µPD78F9418A
If Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated flash
programmer, the following signals are generated for the µPD78F9418A. For details, refer to the manual of Flashpro
III/Flashpro IV.
Table 18-3. Pin Connection List
Signal Name
I/O
Pin Function
Pin Name
3-Wire Serial I/O
UART
Pseudo
3-Wire
VPP1
VPP2
VDD
Output
−
Write voltage
VPP
×
Note
×
Note
×
Note
−
−
I/O
VDD voltage generation/ VDD0, VDD1
voltage monitoring
−
GND
CLK
RESET
SI
Ground
VSS0, VSS1
X1
Output
Output
Input
Clock output
Reset signal
Receive signal
Transmit signal
Transfer clock
Handshake signal
RESET
SO/TxD/P01/P41
SI/RxD/P02/P42
SCK/P00/P40
−
SO
Output
Output
Input
×
×
SCK
HS
×
×
Note VDD voltage must be supplied before programming is started.
Remark : Pin must be connected.
: If the signal is supplied on the target board, pin does not need to be connected.
×: Pin does not need to be connected.
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18.1.3 On-board pin connections
When programming on the target system, provide a connector on the target system to connect to the dedicated
flash programmer.
There may be cases in which an on-board function that switches from the normal operation mode to flash memory
programming mode is required.
<VPP pin>
Input 0 V to the VPP pin in the normal operation mode. A write voltage of 10.0 V (TYP.) is supplied to the VPP
pin in the flash memory programming mode. Therefore, connect the VPP pin using method (1) or (2) below.
(1) Connect a pull-down resistor of RVPP = 10 kΩ to the VPP pin.
(2) Set the jumper on the board to switch the input of VPP pin to the programmer side or directly to GND.
The following shows an example of VPP pin connection.
Figure 18-4. VPP Pin Connection Example
PD78F9418A
µ
Connection pin of dedicated flash programmer
VPP
Pull-down resistor (RVPP
)
<Serial interface pins>
The following shows the pins used by each serial interface.
Serial Interface
Pins Used
3-wire serial I/O
UART
SI, SO, SCK
RxD, TxD
Pseudo 3-wire
P00, P01, P02
P40, P41, P42
Note that signal conflict or malfunction of other devices may occur when an on-board serial interface pin that is
connected to another device is connected to the dedicated flash programmer.
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CHAPTER 18 µPD78F9418A
(1) Signal conflict
A signal conflict occurs if the dedicated flash programmer (output) is connected to a serial interface pin
(input) connected to another device (output). To prevent this signal conflict, isolate the connection with the
other device or put the other device in the output high impedance status.
Figure 18-5. Signal Conflict (Serial Interface Input Pin)
µ
PD78F9418A
Input pin
Connection pin of dedicated flash
programmer
Signal conflict
Other device
Output pin
In the flash memory programming mode, the signal
output by another device and the signal sent by the
dedicated flash programmer conflict. To prevent this,
isolate the signal on the device side.
(2) Malfunction of another device
When the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output)
connected to another device (input), a signal may be output to the device, causing a malfunction. To prevent
such malfunction, isolate the connection with other device or set so that the input signal to the device is
ignored.
Figure 18-6. Malfunction of Another Device
µ
PD78F9418A
Pin
Connection pin of dedicated flash
programmer
Other device
Input pin
If the signal output by the
flash memory programming mode, isolate the signal on the device side.
µ
PD78F9418A affects another device in the
µ
PD78F9418A
Pin
Connection pin of dedicated flash
programmer
Other device
Input pin
If the signal output by the dedicated flash programmer affects another
device, isolate the signal on the device side.
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CHAPTER 18 µPD78F9418A
<RESET pin>
When the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset
signal generator on the board, a signal conflict occurs. To prevent this signal conflict, isolate the connection with
the reset signal generator.
If a reset signal is input from the user system in the flash memory programming mode, a normal programming
operation will not be performed. Do not input signals other than reset signals from the dedicated flash programmer
during this period.
Figure 18-7. Signal Conflict (RESET Pin)
µ
PD78F9418A
RESET
Connection pin of dedicated
flash programmer
Signal conflict
Reset signal generator
Output pin
In the flash memory programming mode, the signal output
by the reset signal generator and the signal output by the
dedicated flash programmer conflict, therefore, isolate the
signal on the reset signal generator side.
<Port pins>
Shifting to the flash memory programming mode sets all the pins except those used for flash memory
programming communication to the status immediately after reset.
Therefore, if the external device does not acknowledge an initial status such as the output high impedance
status, connect the external device to VDD0, VDD1, VSS0, or VSS1 via a resistor.
<Oscillation pins>
When using an on-board clock, connection of X1, X2, XT1, and XT2 must conform to the methods in the normal
operation mode.
When using the clock output of the flash programmer, directly connect it to the X1 pin with the on-board main
oscillator disconnected, and leave the X2 pin open. For the subclock, connection conforms to that in the normal
operation mode.
<Power supply>
To use the power output of the flash programmer, connect the VDD0 and VDD1 pins to VDD of the flash
programmer, and the VSS0 and VSS1 pins to GND of the flash programmer.
To use the on-board power supply, connection must conform to that in the normal operation mode. However,
because the voltage is monitored by the flash programmer, therefore, VDD of the flash programmer must be
connected.
For the other power supply pins (AVDD, AVREF, AVSS), supply the same power supply as in the normal operation
mode.
<Other pins>
Handle the other pins (S0 to S15, COM0 to COM3, VLC0 to VLC2, BIAS) in the same way as in the normal
operation mode.
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CHAPTER 18 µPD78F9418A
18.1.4 Connection when using flash memory writing adapter
The following shows an example of the recommended connection when using the flash memory writing adapter.
Figure 18-8. Example of Flash Memory Writing Adapter Connection When Using 3-Wire Serial I/O Mode
VDD (2.7 to 5.5 V)
GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
µ
PD78F9418A
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
GND
VDD
VDD2 (LVDD)
SI
SO SCK CLKOUT RESET VPP RESERVE/HS
Writer interface
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CHAPTER 18 µPD78F9418A
Figure 18-9. Example of Flash Memory Writing Adapter Connection When Using UART Mode
VDD (2.7 to 5.5 V)
GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
µ
PD78F9418A
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
GND
VDD
VDD2 (LVDD)
SI
SO SCK CLKOUT RESET VPP RESERVE/HS
Writer interface
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CHAPTER 18 µPD78F9418A
Figure 18-10. Example of Flash Memory Writing Adapter Connection When Using Pseudo 3-Wire Mode
(When P0 Is Used)
VDD (2.7 to 5.5 V)
GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
µ
PD78F9418A
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
GND
VDD
VDD2 (LVDD)
SI
SO SCK CLKOUT RESET VPP RESERVE/HS
Writer interface
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CHAPTER 19 MASK OPTIONS
The mask ROM versions of the µPD789407A and µPD789417A Subseries have the following mask options.
Caution The flash memory version does not have a mask option.
19.1 Mask Option for Pins
Table 19-1. Selection of Mask Option for Pins
Pin
P50 to P53
Mask Option
Whether a pull-up resistor is to be incorporated can be specified in 1-bit units.
For P50 to P53 (port 5), a mask option is used to specify whether a pull-up resistor is to be incorporated. The
mask option is selectable in 1-bit units.
19.2 Mask Option for Voltage Division Resistor for LCD Driver
A mask option is used to specify whether a voltage division resistor is to be incorporated for the LCD driver, as
listed below:
Table 19-2. Combination of Selectable Voltage Division Resistor
RLC1 (2 × RLC2)
20 kΩ
200 kΩ
None
{
−
−
−
RLC2
None
10 kΩ
100 kΩ
{
{
−
{
{
{: Selectable
−: Not selectable
VDD
LIPS0
P-ch
BIAS
R
R
R
R
LC1
LC2
LC2
LC2
VLC0
VLC1
VLC2
V
LCD
V
SS
LIPS0: Bit 4 of LCD display mode register 0 (LCDM0)
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CHAPTER 20 INSTRUCTION SET
This chapter lists the instruction set of the µPD789407A and 789417A Subseries. For details of the operation and
machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual
(U11047E).
20.1 Operation
20.1.1 Operand identifiers and description methods
Operands are described in the Operands column of each instruction in accordance with the description method of
the instruction operand identifier (refer to the assembler specifications for details). When there are two or more
description methods, select one of them. Uppercase letters and the symbols #, !, $, and [ ] are keywords and are
described as they are. Each symbol has the following meaning.
• #: Immediate data specification
• !: Absolute address specification
• $: Relative address specification
• [ ]: Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #, !, $ and [ ] symbols.
For operand register identifiers r and rp, either functional names (X, A, C, etc.) or absolute names (names in
parentheses in the table below, R0, R1, R2, etc.) can be used for description.
Table 20-1. Operand Identifiers and Description Methods
Identifier
Description Method
r
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special function register symbol
rp
sfr
saddr
FE20H to FF1FH Immediate data or label
saddrp
FE20H to FF1FH Immediate data or label (even addresses only)
addr16
addr5
0000H to FFFFH Immediate data or label (only even addresses for 16-bit data transfer instructions)
0040H to 007FH Immediate data or label (even addresses only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
Remark See Table 3-3 for symbols of special function registers.
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CHAPTER 20 INSTRUCTION SET
20.1.2 Description of “Operation” column
A:
A register; 8-bit accumulator
X register
X:
B:
B register
C:
C register
D:
D register
E:
E register
H:
H register
L:
L register
AX:
BC:
DE:
HL:
PC:
SP:
AX register pair; 16-bit accumulator
BC register pair
DE register pair
HL register pair
Program counter
Stack pointer
PSW: Program status word
CY:
AC:
Z:
Carry flag
Auxiliary carry flag
Zero flag
IE:
Interrupt request enable flag
NMIS: Flag indicating non-maskable interrupt servicing in progress
( ): Memory contents indicated by address or register contents in parenthesis
XH, XL: Higher 8 bits and lower 8 bits of 16-bit register
∧:
∨:
V:
Logical product (AND)
Logical sum (OR)
Exclusive logical sum (exclusive OR)
Inverted data
:
addr16: 16-bit immediate data or label
jdisp8: Signed 8-bit data (displacement value)
20.1.3 Description of “Flag” column
(Blank): Unchanged
0:
1:
x:
Cleared to 0
Set to 1
Set/cleared according to the result
Previously saved value is restored
R:
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CHAPTER 20 INSTRUCTION SET
20.2 Operation List
Mnemonic
Operands
Bytes Clocks
Operation
Flag
Z
AC CY
r ← byte
MOV
r, #byte
3
3
3
2
2
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
2
2
2
1
1
2
6
6
6
4
4
4
4
4
4
8
8
6
4
4
6
6
6
6
6
6
4
6
6
6
8
8
8
(saddr) ← byte
sfr ← byte
A ← r
saddr, #byte
sfr, #byte
A, rNote 1
r, ANote 1
r ← A
A ← (saddr)
(saddr) ← A
A ← sfr
A, saddr
saddr, A
A, sfr
sfr ← A
sfr, A
A ← (addr16)
(addr16) ← A
PSW ← byte
A ← PSW
PSW ← A
A ← (DE)
(DE) ← A
A ← (HL)
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
x
x
x
x
x
x
[DE], A
A, [HL]
(HL) ← A
[HL], A
A ← (HL + byte)
(HL + byte) ← A
A ↔ X
A, [HL+byte]
[HL+byte], A
A, X
XCH
A, rNote 2
A ↔ r
A ↔ (saddr)
A ↔ sfr
A, saddr
A, sfr
A ↔ (DE)
A ↔ (HL)
A ↔ (HL + byte)
A, [DE]
A, [HL]
A, [HL+byte]
Notes 1. Except r = A.
2. Except r = A, X.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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CHAPTER 20 INSTRUCTION SET
Mnemonic
Operands
Bytes Clocks
Operation
Flag
Z
AC CY
rp ← word
MOVW
rp, #word
3
2
2
1
1
1
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
6
6
8
4
4
8
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
AX ← (saddrp)
(saddrp) ← AX
AX ← rp
AX, saddrp
saddrp, AX
AX, rpNote
rp, AXNote
AX, rpNote
A, #byte
saddr, #byte
A, r
rp ← AX
AX ↔ rp
XCHW
ADD
A, CY ← A + byte
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
(saddr), CY ← (saddr) + byte
A, CY ← A + r
A, CY ← A + (saddr)
A, saddr
A, !addr16
A, [HL]
A, CY ← A + (addr16)
A, CY ← A + (HL)
A, CY ← A + (HL + byte)
A, CY ← A + byte + CY
(saddr), CY ← (saddr) + byte + CY
A, CY ← A + r + CY
A, [HL+byte]
A, #byte
saddr, #byte
A, r
ADDC
A, CY ← A + (saddr) + CY
A, CY ← A + (addr16) + CY
A, CY ← A + (HL) + CY
A, CY ← A + (HL + byte) + CY
A, CY ← A − byte
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
A, #byte
saddr, #byte
A, r
SUB
(saddr), CY ← (saddr) − byte
A, CY ← A − r
A, CY ← A − (saddr)
A, saddr
A, !addr16
A, [HL]
A, CY ← A − (addr16)
A, CY ← A − (HL)
A, CY ← A − (HL + byte)
A, [HL+byte]
Note Only when rp = BC, DE, or HL.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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CHAPTER 20 INSTRUCTION SET
Mnemonic
Operands
Bytes Clocks
Operation
Flag
Z
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
AC CY
A, CY ← A − byte − CY
SUBC
A, #byte
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
(saddr), CY ← (saddr) − byte − CY
A, CY ← A − r − CY
A, CY ← A − (saddr) − CY
A, CY ← A − (addr16) − CY
A, CY ← A − (HL) − CY
A, CY ← A− (HL + byte) − CY
A ← A ∧ byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
A, #byte
saddr, #byte
A, r
AND
(saddr) ← (saddr) ∧ byte
A ← A ∧ r
A ← A ∧ (saddr)
A, saddr
A, !addr16
A, [HL]
A ← A ∧ (addr16)
A ← A ∧ (HL)
A ← A ∧ (HL + byte)
A ← A ∨ byte
A, [HL+byte]
A, #byte
saddr, #byte
A, r
OR
(saddr) ← (saddr) ∨ byte
A ← A ∨ r
A ← A ∨ (saddr)
A, saddr
A, !addr16
A, [HL]
A ← A ∨ (addr16)
A ← A ∨ (HL)
A ← A ∨ (HL + byte)
A ← A V byte
A, [HL+byte]
A, #byte
saddr, #byte
A, r
XOR
(saddr) ← (saddr) V byte
A ← A V r
A ← A V (saddr)
A, saddr
A, !addr16
A, [HL]
A ← A V (addr16)
A ← A V (HL)
A ← A V (HL + byte)
A, [HL+byte]
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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CHAPTER 20 INSTRUCTION SET
Mnemonic
Operands
Bytes Clocks
Operation
Flag
Z
x
x
x
x
x
x
x
x
x
x
x
x
x
x
AC CY
A − byte
CMP
A, #byte
2
3
2
2
3
1
2
3
3
3
2
2
2
2
1
1
1
1
1
1
3
3
2
3
2
3
3
2
3
2
1
1
1
4
6
4
4
8
6
6
6
6
6
4
4
4
4
4
4
2
2
2
2
6
6
4
6
10
6
6
4
6
10
2
2
2
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
(saddr) − byte
A − r
saddr, #byte
A, r
A − (saddr)
A − (addr16)
A − (HL)
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
AX, #word
AX, #word
AX, #word
r
A − (HL + byte)
AX, CY ← AX + word
AX, CY ← AX − word
AX − word
ADDW
SUBW
CMPW
INC
r ← r + 1
(saddr) ← (saddr) + 1
r ← r − 1
saddr
r
DEC
(saddr) ← (saddr) − 1
rp ← rp + 1
saddr
rp
INCW
DECW
ROR
rp ← rp − 1
rp
(CY, A7 ← A0, Am−1 ← Am) × 1
(CY, A0 ← A7, Am+1 ← Am) × 1
(CY ← A0, A7 ← CY, Am−1 ← Am) × 1
(CY ← A7, A0 ← CY, Am+1 ← Am) × 1
(saddr.bit) ← 1
sfr.bit ← 1
A, 1
x
x
x
x
ROL
A, 1
RORC
ROLC
SET1
A, 1
A, 1
saddr.bit
sfr.bit
A.bit ← 1
A.bit
PSW.bit ← 1
PSW.bit
[HL].bit
saddr.bit
sfr.bit
x
x
x
(HL).bit ← 1
(saddr.bit) ← 0
sfr.bit ← 0
CLR1
A.bit ← 0
A.bit
PSW.bit ← 0
PSW.bit
[HL].bit
CY
x
x
x
(HL).bit ← 0
CY ← 1
SET1
CLR1
NOT1
1
0
x
CY ← 0
CY
CY ← CY
CY
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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CHAPTER 20 INSTRUCTION SET
Mnemonic
Operands
Bytes Clocks
Operation
Flag
Z
AC CY
(SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,
PC ← addr16, SP ← SP − 2
CALL
!addr16
[addr5]
3
1
6
8
(SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
CALLT
PCL ← (00000000, addr5), SP ← SP − 2
PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2
RET
1
1
6
8
PCH ← (SP + 1), PCL ← (SP),
RETI
R
R
R
R
R
R
PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0
(SP − 1) ← PSW, SP ← SP − 1
(SP − 1) ← rpH, (SP − 2) ← rpL, SP ← SP − 2
PSW ← (SP), SP ← SP + 1
PUSH
POP
PSW
1
1
1
1
2
2
3
2
1
2
2
2
2
4
4
3
4
4
4
3
4
2
2
3
2
4
rp
PSW
4
rpH ← (SP + 1), rpL ← (SP), SP ← SP + 2
SP ← AX
rp
6
MOVW
BR
SP, AX
AX, SP
!addr16
$addr16
AX
8
AX ← SP
6
PC ← addr16
6
PC ← PC + 2 + jdisp8
6
PCH ← A, PCL ← X
6
PC ← PC + 2 + jdisp8 if CY = 1
PC ← PC + 2 + jdisp8 if CY = 0
PC ← PC + 2 + jdisp8 if Z = 1
PC ← PC + 2 + jdisp8 if Z = 0
PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
PC ← PC + 4 + jdisp8 if sfr.bit = 1
PC ← PC + 3 + jdisp8 if A.bit = 1
PC ← PC + 4 + jdisp8 if PSW.bit = 1
PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
PC ← PC + 4 + jdisp8 if sfr.bit = 0
PC ← PC + 3 + jdisp8 if A.bit = 0
PC ← PC + 4 + jdisp8 if PSW.bit = 0
B ← B−1, then PC ← PC + 2 + jdisp8 if B ≠ 0
C ← C−1, then PC ← PC + 2 + jdisp8 if C ≠ 0
BC
$saddr16
$saddr16
$saddr16
$saddr16
6
BNC
BZ
6
6
BNZ
BT
6
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
B, $addr16
10
10
8
10
10
10
8
BF
10
6
DBNZ
C, $addr16
6
(saddr) ← (saddr) − 1, then
saddr, $addr16
8
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
NOP
EI
1
3
3
1
1
2
6
6
2
2
No Operation
IE ← 1 (Enable interrupt)
IE ← 0 (Disable interrupt)
Set HALT mode
DI
HALT
STOP
Set STOP mode
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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CHAPTER 20 INSTRUCTION SET
20.3 Instructions Listed by Addressing Type
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,
POP, DBNZ
2nd Operand
1st Operand
#byte
A
r
sfr
saddr !addr16 PSW
[DE]
[HL]
[HL+byte] $addr1
6
1
None
ADD
ADDC
SUB
SUBC
AND
OR
MOVNote MOV
XCHNote XCH
ADD
MOV
XCH
ADD
MOV
ADD
MOV
MOV
XCH
MOV
XCH
ADD
MOV
XCH
ADD
ROR
A
ROL
RORC
ROLC
ADDC
SUB
ADDC ADDC
SUB SUB
SUBC SUBC
ADDC ADDC
SUB SUB
SUBC SUBC
SUBC
XOR
CMP
AND
AND
OR
AND
OR
AND
OR
AND
OR
OR
XOR
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
CMP
r
MOV
MOV
INC
DEC
B, C
sfr
DBNZ
DBNZ
MOV
MOV
MOV
saddr
MOV
ADD
ADDC
SUB
SUBC
AND
OR
INC
DEC
XOR
CMP
!addr16
PSW
MOV
MOV
MOV
PUSH
POP
[DE]
MOV
MOV
MOV
[HL]
[HL+byte]
Note Except r = A.
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CHAPTER 20 INSTRUCTION SET
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
1st Operand
#word
AX
rpNote
saddrp
SP
None
AX
ADDW
MOVW
XCHW
MOVW
MOVW
SUBW
CMPW
rp
MOVW
MOVWNote
INCW
DECW
PUSH
POP
saddrp
SP
MOVW
MOVW
Note Only when rp = BC, DE, or HL.
(3) Bit manipulation instructions
SET1, CLR1, NOT1, BT, BF
2nd Operand
$addr16
None
1st Operand
A.bit
BT
BF
SET1
CLR1
sfr.bit
BT
BF
SET1
CLR1
saddr.bit
PSW.bit
[HL].bit
CY
BT
BF
SET1
CLR1
BT
BF
SET1
CLR1
SET1
CLR1
SET1
CLR1
NOT1
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CHAPTER 20 INSTRUCTION SET
(4) Call instructions/branch instructions
CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ
2nd Operand
1st Operand
AX
!addr16
[addr5]
$addr16
Basic Instructions
BR
CALL
BR
CALLT
BR
BC
BNC
BZ
BNZ
Compound Instructions
DBNZ
(5) Other instructions
RET, RETI, NOP, EI, DI, HALT, STOP
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CHAPTER 21 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
Conditions
Ratings
Unit
V
AVDD − 0.3 V ≤ VDD ≤ AVDD + 0.3 V
AVREF ≤ VDD + 0.3 V
−0.3 to +6.5
VDD
AVDD
AVREF
VPP
VI1
AVREF ≤ AVDD + 0.3 V
µPD78F9418A only Note
–0.3 to +10.5
−0.3 to VDD + 0.3
−0.3 to +13
−0.3 to VDD + 0.3
−10
V
V
Input voltage
Pins other than P50 to P53
VI2
P50 to P53
N-ch open drain
V
Output voltage
VO
V
Output current, high
IOH
1 pin
mA
mA
mA
mA
°C
°C
°C
°C
−30
Total for all pins
1 pin
Output current, low
IOL
TA
30
Total for all pins
160
−40 to +85
10 to 40
Operating ambient
temperature
In normal operation mode
During flash memory programming
Mask ROM version
Storage temperature
Tstg
–65 to +150
–40 to +125
µPD78F9418A
Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
VPP must exceed VDD 10 µs or more after VDD has reached the lower-limit value (1.8 V) of the operating
voltage range (see a in the figure below).
• When supply voltage drops
VDD must be lowered 10 µs or more after VPP falls below the lower-limit value (1.8 V) of the operating
voltage range of VDD (see b in the figure below).
1.8 V
V
DD
0 V
a
b
VPP
1.8 V
0 V
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 21 ELECTRICAL SPECIFICATIONS
Main System Clock Oscillator Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Recommended Circuit
Parameter
Conditions
MIN.
1.0
TYP. MAX.
5.0
Unit
X1
X2
V
SS0
Ceramic
Oscillation frequency
(fX)Note 1
VDD = Oscillation voltage
range
MHz
resonator
Oscillation stabilization After VDD has reached MIN. of
4
ms
C1
C2
timeNote 2
oscillation start voltage
Crystal
V
SS0 X1
X2
Oscillation frequency
(fX)Note 1
1.0
5.0
MHz
resonator
Oscillation stabilization VDD = 4.5 to 5.5 V
10
30
ms
ms
C1
C2
timeNote 2
VDD = 1.8 to 5.5 V
External
clock
X1 input frequency
(fX)Note 1
1.0
85
5.0
MHz
X1
X2
X1 input high-/low-level
500
ns
widths (tXH, tXL
)
X1 input frequency
V
DD = 2.7 to 5.5 V
1.0
85
5.0
MHz
ns
X1
X2
Note 1
(fX)
X1 input high-/low-level VDD = 2.7 to 5.5 V
widths (tXH, tXL)
500
OPEN
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release. Use a resonator whose
oscillation is stabilized within the oscillation wait time.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS0
.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the device is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
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CHAPTER 21 ELECTRICAL SPECIFICATIONS
Subsystem Clock Oscillator Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Recommended Circuit
Parameter
Conditions
MIN.
32
TYP. MAX.
Unit
kHz
Crystal
Oscillation frequency
(fXT)Note 1
32.768
35
VSS0 XT1 XT2
resonator
R
Oscillation stabilization VDD = 4.5 to 5.5 V
1.2
2
s
s
C3
C4
timeNote 2
VDD = 1.8 to 5.5 V
10
35
External
clock
XT1 input frequency
(fXT)Note 1
32
kHz
XT1
XT2
µs
XT1 input high-/low-
level widths (tXTH, tXTL)
14.3
15.6
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release. Use a resonator whose
oscillation is stabilized within the oscillation wait time.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figure to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS0.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
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DC Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V) (1/3)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
−1
Unit
mA
mA
mA
mA
V
Output current,
high
IOH
Per pin
−15
Total for all pins
Per pin
Output current,
low
IOL
10
Total for all pins
80
Input voltage,
high
VIH1
VIH2
P00 to P03, P46, P47, P60 to P66, VDD = 2.7 to 5.5 V
P80 to P87, P90 to P93
VDD = 1.8 to 5.5 V
0.7VDD
0.9VDD
0.7VDD
0.9VDD
0.7VDD
0.9VDD
0.8VDD
0.9VDD
VDD − 0.1
0
VDD
VDD
V
P50 to P53 N-ch open drain
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
12
V
12
V
On-chip pull-up
resistor
VDD
V
VDD
V
VIH3
RESET, P20 to P27, P40 to P45 VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD
V
VDD
V
VIH4
X1, X2, XT1, XT2
VDD = 1.8 to 5.5 V
VDD
V
Input voltage,
low
VIL1
P00 to P03, P46, P47, P60 to P66, VDD = 2.7 to 5.5 V
P80 to P87, P90 to P93
VDD = 1.8 to 5.5 V
0.3VDD
0.1VDD
0.3VDD
0.1VDD
0.2VDD
0.1VDD
0.1
V
0
V
VIL2
VIL3
P50 to P53
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0
V
0
V
RESET, P20 to P27, P40 to P45 VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0
V
0
V
VIL4
X1, X2, XT1, XT2
IOH = −1 mA
VDD = 1.8 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 1.8 to 5.5 V
0
V
VDD − 1.0
VDD − 0.5
Output voltage,
high
VOH
V
IOH = −100 µA
V
Output voltage,
low
VOL1
VOL2
ILIH1
Pins other than P50 to P53
VDD = 4.5 to 5.5 V
IOL = 10 mA
1.0
0.5
1.0
0.4
3
V
VDD = 1.8 to 5.5 V
IOL = 400 µA
V
V
P50 to P53
VIN = VDD
VDD = 4.5 to 5.5 V
IOL = 10 mA
VDD = 1.8 to 5.5 V
IOL = 1.6 mA
V
µA
Input leakage
current, high
Pins other than P50 to P53
(N-ch open drain), X1, X2,
XT1, and XT2
µA
µA
µA
ILIH2
ILIH3
ILIL1
X1, X2, XT1, XT2
20
20
−3
VIN = 12 V
VIN = 0 V
P50 to P53 (N-ch open drain)
Input leakage
current, low
Pins other than P50 to P53
(N-ch open drain), X1, X2,
XT1, and XT2
−20
−3Note
µA
µA
ILIL2
X1, X2, XT1, XT2
ILIL3
P50 to P53 (N-ch open drain)
Note A low-level input leakage current of −30 µA (MAX.) flows only during the 1-cycle time after a read instruction
is executed to P50 to P53 when on-chip pull-up resistors are not connected to P50 to P53 (specified by
mask option) and P50 to P53 are set to input mode. At times other than this, a −3 µA (MAX.) current flows.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 21 ELECTRICAL SPECIFICATIONS
DC Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V) (2/3)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
3
Unit
µA
Output leakage
current, high
ILOH
VOUT = VDD
VOUT = 0 V
−3
200
60
µA
kΩ
kΩ
Output leakage
current, low
ILOL
Software pull-up R1
resistor
VIN = 0 V, pins other than P50 to P53
VIN = 0 V, P50 to P53
50
15
100
30
Mask option pull- R2
up resistorNote 1
VDD = 5.0 V 10%Note 5
VDD = 3.0 V 10%Note 6
VDD = 2.0 V 10%Note 6
VDD = 5.0 V 10%Note 5
VDD = 3.0 V 10%Note 6
VDD = 2.0 V 10%Note 6
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
VDD = 5.0 V 10%
VDD = 3.0 V 10%
TA = 25°C
Note 2
Note 2
Note 2
Note 2
Note 2
Supply current
(mask ROM
version)
IDD1
5.0 MHz crystal oscillation operating
mode
2.0
0.6
0.3
1.1
0.4
0.2
30
4.0
1.2
0.6
2.2
0.8
0.4
90
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
mA
(C1 = C2 = 22 pF)
IDD2
IDD3
IDD4
IDD5
5.0 MHz crystal oscillation HALT
mode
(C1 = C2 = 22 pF)
32.768 kHz crystal oscillation
operating modeNote 4
9
50
(C3 = C4 = 22 pF, R1 = 220 kΩ)
4
25
32.768 kHz crystal oscillation HALT
modeNote 4
25
55
5
25
(C3 = C4 = 22 pF, R1 = 220 kΩ)
2.5
0.1
0.05
0.05
0.05
2.6
1.2
0.9
12.5
10
32.768 kHz crystal oscillation STOP
mode
5.0
3.0
3.0
6.0
3.6
2.7
VDD = 2.0 V 10%
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
Note 3
IDD6
5.0 MHz crystal oscillation
A/D operating mode
(C1 = C2 = 22 pF)
Notes 1. Mask ROM version only
2. The current flowing to AVREF (A/D operation ON (ADCS0 = 1)), AVDD current, and the port current
(including the current flowing through the on-chip pull-up resistors) is not included.
3. The current flowing to AVREF (A/D operation ON (ADCS0 = 1)) and the port current (including the current
flowing through the on-chip pull-up resistors) is not included. For the current flowing to AVREF, refer to
the parameter of “Resistance between AVREF and AVSS” in the 8-Bit A/D Converter Characteristics
and 10-Bit A/D Converter Characteristics.
4. When the main system clock is stopped
5. High-speed mode operation (when processor clock control register (PCC) is set to 00H)
6. Low-speed mode operation (when PCC is set to 02H)
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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DC Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V) (3/3)
Parameter
Symbol
Conditions
MIN.
TYP.
5.0
2.0
1.5
2.0
1.0
0.7
200
150
100
50
MAX.
14.0
5.0
3.0
6.0
3.0
2.0
600
450
300
150
90
Unit
VDD = 5.0 V 10%Note 4
VDD = 3.0 V 10%Note 5
VDD = 2.0 V 10%Note 5
VDD = 5.0 V 10%Note 4
VDD = 3.0 V 10%Note 5
VDD = 2.0 V 10%Note 5
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
VDD = 5.0 V 10%
VDD = 3.0 V 10%
TA = 25°C
Note 1
IDD1
Supply current
5.0 MHz crystal oscillation operating
mode
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
mA
(µPD78F9418A)
(C1 = C2 = 22 pF)
Note 1
IDD2
5.0 MHz crystal oscillation HALT
mode
(C1 = C2 = 22 pF)
Note 1
IDD3
32.768 kHz crystal oscillation
operating modeNote 3
(C3 = C4 = 22 pF, R1 = 220 kΩ)
Note 1
IDD4
32.768 kHz crystal oscillation HALT
modeNote 3
30
(C3 = C4 = 22 pF, R1 = 220 kΩ)
20
60
Note 1
IDD5
32.768 kHz crystal oscillation STOP
mode
0.1
0.05
0.05
0.05
6.0
3.0
2.5
10
5.0
3.0
3.0
16.0
7.0
5.0
VDD = 2.0 V 10%
VDD = 5.0 V 10%Note 4
VDD = 3.0 V 10%Note 5
VDD = 2.0 V 10%Note 5
Note 2
IDD6
5.0 MHz crystal oscillation
A/D operating mode
(C1 = C2 = 22 pF)
Notes 1. The current flowing to AVREF (A/D operation ON (ADCS0 = 1)), AVDD current, and the port current
(including the current flowing through the on-chip pull-up resistors) is not included.
2. The current flowing to AVREF (A/D operation ON (ADCS0 = 1)) and the port current (including the
current flowing through the on-chip pull-up resistors) is not included. For the current flowing to AVREF,
refer to the parameter of “Resistance between AVREF and AVSS” in the 8-Bit A/D Converter
Characteristics and 10-Bit A/D Converter Characteristics.
3. When the main system clock is stopped
4. High-speed mode operation (when processor clock control register (PCC) is set to 00H)
5. Low-speed mode operation (when PCC is set to 02H)
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 21 ELECTRICAL SPECIFICATIONS
LCD Characteristics (TA = −40 to +85°C, VDD = 2.2 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
2.2
2.7
3.0
100
10
TYP.
MAX.
Unit
LCD drive voltage
VLCD
VAON0 = 1
VAON0 = 0Note 1
VDD
VDD
VDD
400
40
V
V
At 1/3 bias
At 1/2 bias
V
When selecting 100 kΩ by mask option
When selecting 10 kΩ by mask option
kΩ
kΩ
V
LCD divider
resistorNote 2
RLCD
200
20
IO = 5 µA
0.2
LCD output voltage
deviationNote 3 (common)
VODC
VLCD0 = VLCD
0
VLCD1 = VLCD × 2/3
IO = 1 µA
2.2 V ≤ VLCD ≤ VDD
0.2
LCD output voltage
deviationNote 3 (segment)
VODS
0
V
VLCD2 = VLCD × 1/3Note 1
Notes 1. TA = −10 to +85°C in the normal mode (VAON0 = 0)
2. For mask ROM version, 10 kΩ, 100 kΩ, or no divider resistor can be selected by mask option. The
µPD78F9418A has no divider resistor.
3. Voltage deviation is the voltage difference between the ideal value of the segment or common output
(VLCDn: n = 0 to 2) and the output voltage.
Flash Memory Write/Erase Characteristics (µPD78F9418A only)
(TA = 10 to 40°C, VDD = 1.8 to 5.5 V, in 5.0 MHz crystal oscillation operating mode)
Parameter
Symbol
IDDW
Conditions
MIN.
TYP.
MAX.
18
Unit
mA
Write currentNote
(VDD pin)
When VPP supply voltage = VPP1
Write currentNote
(VPP pin)
IPPW
IDDE
IPPE
When VPP supply voltage = VPP1
When VPP supply voltage = VPP1
When VPP supply voltage = VPP1
22.5
18
mA
mA
mA
Erase currentNote
(VDD pin)
Erase currentNote
(VPP pin)
115
Unit erase time
Total erase time
Write count
ter
0.5
1
1
20
s
tera
s
Times
V
Erase/write are regarded as 1 cycle
In normal operation
20
VPP supply voltage
VPP0
0
0.2VDD
10.3
VPP1
During flash memory programming
9.7
10.0
V
Note The current flowing to the ports (including the current flowing through the on-chip pull-up resistors) is not
included.
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AC Characteristics
(1) Basic operation (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
MIN.
0.4
1.6
114
0
TYP.
122
MAX.
8
Unit
µs
Cycle time (minimum TCY
instruction execution
time)
Operating with main
system clock
µs
8
µs
Operating with subsystem clock
VDD = 2.7 to 5.5 V
125
4
TI0, TI1 input
frequency
fTI
MHz
kHz
µs
VDD = 1.8 to 5.5 V
0
275
TI0, TI1 input high-/
low-level widths
tTIH, tTIL
VDD = 2.7 to 5.5 V
0.1
1.8
10
µs
VDD = 1.8 to 5.5 V
µs
Interrupt input high-/
low-level widths
tINTH,
INTP0 to INTP3
tINTL
µs
RESET input
tRSL
10
low-level width
TCY vs VDD (Main system clock)
60
10
µ
Guaranteed
operating
range
1.0
0.4
0.1
1
2
3
4
5
6
Supply voltage VDD [V]
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(2) Serial interface (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
(a) 3-wire serial I/O mode (SCK ... Internal clock output)
Parameter
Symbol
Conditions
MIN.
TYP.
TYP.
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK cycle time
tKCY1
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
800
3200
tKCY1/2−50
tKCY1/2−150
150
SCK high-/low-level
widths
tKH1, tKL1 VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
SI setup time
tSIK1
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
(to SCK↑)
500
SI hold time
tKSI1
400
(from SCK↑)
600
R = 1 kΩ,
SO output delay time tKSO1
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0
250
C = 100 pFNote
from SCK↓
0
1000
Note R and C are the load resistance and load capacitance of the SO output line.
(b) 3-wire serial I/O mode (SCK ... External clock input)
Parameter
Symbol
Conditions
MIN.
900
3500
400
1600
100
150
400
600
0
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK cycle time
tKCY2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
SCK high-/low-level
widths
tKH2, tKL2 VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
SI setup time
tSIK2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
(to SCK↑)
SI hold time
tKSI2
(from SCK↑)
R = 1 kΩ,
SO output delay time tKSO2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
300
C = 100 pFNote
from SCK↓
0
1000
Note R and C are the load resistance and load capacitance of the SO output line.
(c) UART mode (dedicated baud rate generator output)
Parameter
Transfer rate
Symbol
Conditions
MIN.
MAX.
78125
19531
Unit
bps
bps
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
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CHAPTER 21 ELECTRICAL SPECIFICATIONS
(d) UART mode (external clock input)
Parameter
Symbol
Conditions
MIN.
900
TYP.
MAX.
Unit
ASCK cycle time
tKCY3
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
ns
ns
3500
400
ASCK high-/low-level tKH3, tKL3 VDD = 2.7 to 5.5 V
ns
widths
VDD = 1.8 to 5.5 V
1600
ns
Transfer rate
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
39063
9766
1
bps
bps
µs
ASCK rise/fall times
tR, tF
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CHAPTER 21 ELECTRICAL SPECIFICATIONS
AC Timing Test Points (Excluding X1 and XT1 Inputs)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Test points
Clock Timing
1/fX
t
XL
t
XH
V
IH4 (MIN.)
X1 input
V
IL4 (MAX.)
1/fXT
tXTL
tXTH
V
IH4 (MIN.)
XT1 input
V
IL4 (MAX.)
TI Timing
1/fTI
tTIL
tTIH
TI0, TI1
Interrupt Input Timing
tINTL
tINTH
INTP0 to INTP3
RESET Input Timing
tRSL
RESET
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CHAPTER 21 ELECTRICAL SPECIFICATIONS
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
t
KLm
t
KHm
SCK
t
SIKm
t
KSIm
SI
Input data
t
KSOm
Output data
SO
Remark m = 1 or 2
UART mode (external clock input):
t
KCY3
t
KL3
t
KH3
t
R
t
F
ASCK
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CHAPTER 21 ELECTRICAL SPECIFICATIONS
8-Bit A/D Converter Characteristics (µPD789405A, 789406A, 789407A)
(TA = −40 to +85°C, 1.8 V ≤ AVREF ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
8
TYP.
MAX.
Unit
Resolution
8
8
bit
%FSR
%FSR
µs
Overall errorNote
2.7 V ≤ AVREF ≤ AVDD ≤ 5.5 V
2.7 V ≤ AVREF ≤ AVDD ≤ 5.5 V
0.4
0.8
0.6
1.2
Conversion time
tCONV
14
28
0
100
100
AVREF
AVDD
µs
Analog input voltage
VIAN
V
Reference voltage
AVREF
RADREF
1.8
20
V
kΩ
Resistance between AVREF and AVSS
40
Note Excludes quantization error ( 0.2%FSR).
Remark FSR: Full-scale range
10-Bit A/D Converter Characteristics (µPD789415A, 789416A, 789417A, 78F9418A)
(TA = −40 to +85°C, 1.8 V ≤ AVREF ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
10
TYP.
MAX.
Unit
Resolution
10
10
0.4
bit
%FSR
%FSR
%FSR
µs
Overall errorNote
4.5 V ≤ AVREF ≤ AVDD ≤ 5.5 V
2.7 V ≤ AVREF ≤ AVDD ≤ 5.5 V
1.8 V ≤ AVREF ≤ AVDD ≤ 5.5 V
4.5 V ≤ AVREF ≤ AVDD ≤ 5.5 V
2.7 V ≤ AVREF ≤ AVDD ≤ 5.5 V
1.8 V ≤ AVREF ≤ AVDD ≤ 5.5 V
4.5 V ≤ AVREF ≤ AVDD ≤ 5.5 V
2.7 V ≤ AVREF ≤ AVDD ≤ 5.5 V
1.8 V ≤ AVREF ≤ AVDD ≤ 5.5 V
4.5 V ≤ AVREF ≤ AVDD ≤ 5.5 V
2.7 V ≤ AVREF ≤ AVDD ≤ 5.5 V
1.8 V ≤ AVREF ≤ AVDD ≤ 5.5 V
4.5 V ≤ AVREF ≤ AVDD ≤ 5.5 V
2.7 V ≤ AVREF ≤ AVDD ≤ 5.5 V
1.8 V ≤ AVREF ≤ AVDD ≤ 5.5 V
4.5 V ≤ AVREF ≤ AVDD ≤ 5.5 V
2.7 V ≤ AVREF ≤ AVDD ≤ 5.5 V
1.8 V ≤ AVREF ≤ AVDD ≤ 5.5 V
0.2
0.4
0.8
0.6
1.2
Conversion time
tCONV
AINL
AINL
INL
14
14
28
100
100
100
0.4
µs
µs
Zero-scale errorNote
Full-scale errorNote
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
LSB
LSB
LSB
LSB
LSB
LSB
V
0.6
1.2
0.4
0.6
1.2
Non-integral linearityNote
Non-differential linearityNote
2.5
4.5
8.5
1.5
DNL
2.0
3.5
Analog input voltage
VIAN
0
AVREF
AVDD
Reference voltage
AVREF
RADREF
1.8
20
V
kΩ
Resistance between AVREF and AVSS
40
Note Excludes quantization error ( 0.05%FSR).
Remark FSR: Full-scale range
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CHAPTER 21 ELECTRICAL SPECIFICATIONS
Comparator Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Analog input range
Symbol
Conditions
MIN.
0
TYP.
MAX.
Unit
V
VCIN
VCREF
VDD
1.85
1.45
100
Reference voltage input range
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
1.35
1.35
1.6
1.4
V
V
Accuracy
mV
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°C)
Parameter
Symbol
VDDDR
tSREL
Conditions
MIN.
1.8
0
TYP.
MAX.
5.5
Unit
Data retention power supply voltage
Release signal set time
V
µs
Oscillation stabilization wait timeNote 1
215/fX
tWAIT
Release by RESET
Release by interrupt request
ms
ms
Note 2
Notes 1. The oscillation stabilization wait time is the time after oscillation has started during which the CPU is
stopped to prevent unstable operation.
2. Selection of 212/fX, 215/fX, or 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time selection register (OSTS).
Remark fx: Main system clock oscillation frequency
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CHAPTER 21 ELECTRICAL SPECIFICATIONS
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
STOP mode
Operation mode
Data retention mode
V
DD
V
DDDR
t
SREL
STOP instruction execution
RESET
t
WAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode
STOP mode
Operation mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
Standby release signal
(interrupt request)
t
WAIT
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CHAPTER 22 CHARACTERISTICS CURVES (REFERENCE VALUES)
22.1 Characteristics Curves for Mask ROM Versions
(TA = 25°C)
10.0
PCC = 00H
PCC = 02H
PCC = 00H
(HALT mode)
1.0
0.5
PCC = 02H
(HALT mode)
0.1
0.05
Subsystem clock
operation mode (CSS0 = 1)
Subsystem clock
operation HALT mode (CSS0 = 1)
0.01
0.005
X1
X2 XT1
XT2
Crystal resonator Crystal resonator
5.0 MHz
32.768 kHz
220 kΩ
22 pF
V
33 pF
22 pF
33 pF
SS
V
SS
0.001
0
1
2
3
4
5
6
7
8
Supply voltage VDD (V)
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CHAPTER 22 CHARACTERISTICS CURVES (REFERENCE VALUES)
-
I
OH vs VDD
V
OH
I
OL vs VOL
(T
A
= 25°C)
(TA = 25°C)
V
DD = 5.5 V
V
DD = 5.5 V
30
20
10
0
VDD = 3.5 V
20
10
0
V
DD = 3.5 V
V
DD = 3.0 V
V
DD = 3.0 V
DD = 4.0 V
DD = 4.5 V
VDD = 5.0 V
V
DD = 4.0 V
DD = 4.5 V
DD = 5.0 V
V
V
V
V
V
DD = 2.5 V
VDD = 2.5 V
V
DD = 2.0 V
DD = 1.8 V
V
DD = 2.0 V
DD = 1.8 V
V
V
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-
VDD
VOH (V)
Low-level output voltage VOL (V)
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CHAPTER 22 CHARACTERISTICS CURVES (REFERENCE VALUES)
22.2 Characteristics Curves for µPD78F9418A
(TA = 25˚C)
10.0
Main system clock
operation mode
(PCC1 = 0, CSS0 = 0)
Main system clock
operation mode
(PCC1 = 1, CSS0 = 0)
1.0
0.5
Main system clock
operation HALT mode
(PCC1 = 0, CSS0 = 0)
Main system clock
operation HALT mode
(PCC1 = 1, CSS0 = 0)
Subsystem clock
operation mode
(CSS0 = 1, MCC = 1)
0.1
0.05
Subsystem clock
operation HALT mode
(CSS0 = 1, MCC = 1)
0.01
XT1
X1
X2
XT2
0.005
Crystal resonator
Crystal resonator
32.768 kHz 220 kΩ
5.0 MHz
22 pF
22 pF
33 pF
33 pF
V
SS
V
SS
0.001
0
1
2
3
4
5
6
7
8
Supply voltage VDD (V)
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CHAPTER 23 PACKAGE DRAWINGS
80-PIN PLASTIC QFP (14x14)
A
B
60
61
41
40
detail of lead end
S
C
D
R
Q
80
21
20
1
F
J
M
G
H
I
P
K
S
N
S
L
M
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
C
D
F
G
H
I
17.20 0.20
14.00 0.20
14.00 0.20
17.20 0.20
0.825
0.825
0.32 0.06
0.13
J
0.65 (T.P.)
1.60 0.20
0.80 0.20
K
L
+0.03
0.17
M
−0.07
N
P
0.10
1.40 0.10
0.125 0.075
Q
+7°
3°
R
S
−3°
1.70 MAX.
P80GC-65-8BT-1
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CHAPTER 23 PACKAGE DRAWINGS
80-PIN PLASTIC TQFP (FINE PITCH) (12x12)
A
B
60
41
61
40
detail of lead end
S
C
D
P
T
R
80
21
L
1
20
U
Q
F
M
G
J
H
I
K
S
M
N
S
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
C
D
F
G
H
I
14.0 0.2
12.0 0.2
12.0 0.2
14.0 0.2
1.25
1.25
0.22 0.05
0.08
J
0.5 (T.P.)
1.0 0.2
0.5
K
L
M
N
P
Q
0.145 0.05
0.08
1.0
0.1 0.05
+4°
3°
R
−3°
S
T
1.1 0.1
0.25
U
0.6 0.15
P80GK-50-9EU-1
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CHAPTER 24 RECOMMENDED SOLDERING CONDITIONS
The µPD789407A and µPD789417A Subseries should be soldered and mounted under the following
recommended conditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 24-1. Surface Mounting Type Soldering Conditions (1/3)
µPD789405AGC-×××-8BT: 80-pin plastic QFP (14 × 14)
µPD789406AGC-×××-8BT: 80-pin plastic QFP (14 × 14)
µPD789407AGC-×××-8BT: 80-pin plastic QFP (14 × 14)
µPD789415AGC-×××-8BT: 80-pin plastic QFP (14 × 14)
µPD789416AGC-×××-8BT: 80-pin plastic QFP (14 × 14)
µPD789417AGC-×××-8BT: 80-pin plastic QFP (14 × 14)
µPD78F9418AGC-8BT:
80-pin plastic QFP (14 × 14)
Recommended Condition
Symbol
Soldering Method
Infrared reflow
Soldering Conditions
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C
IR35-00-2
VP15-00-2
WS60-00-1
or higher), Count: Twice or less
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C
VPS
or higher), Count: Twice or less
Soldering bath temperature: 260°C max., Time: 10 seconds max.,
Count: 1, Preheating temperature: 120°C max. (package surface
temperature)
Wave soldering
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
−
Partial heating
Caution Do not use different soldering methods together (except for partial heating).
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CHAPTER 24 RECOMMENDED SOLDERING CONDITIONS
Table 24-1. Surface Mounting Type Soldering Conditions (2/3)
µPD789405AGK-×××-9EU: 80-pin plastic TQFP (fine pitch) (12 × 12)
µPD789406AGK-×××-9EU: 80-pin plastic TQFP (fine pitch) (12 × 12)
µPD789407AGK-×××-9EU: 80-pin plastic TQFP (fine pitch) (12 × 12)
µPD789415AGK-×××-9EU: 80-pin plastic TQFP (fine pitch) (12 × 12)
µPD789416AGK-×××-9EU: 80-pin plastic TQFP (fine pitch) (12 × 12)
µPD789417AGK-×××-9EU: 80-pin plastic TQFP (fine pitch) (12 × 12)
µPD78F9418GK-9EU:
80-pin plastic TQFP (fine pitch) (12 × 12)
Recommended Condition
Symbol
Soldering Method
Infrared reflow
Soldering Conditions
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C
or higher), Count: Twice or less, Exposure limit: 7 daysNote (after that,
prebake at 125°C for 10 hours)
IR35-107-2
VP15-107-2
−
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C
or higher), Count: Twice or less, Exposure limit: 7 daysNote (after that,
prebake at 125°C for 10 hours)
VPS
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
Partial heating
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
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CHAPTER 24 RECOMMENDED SOLDERING CONDITIONS
Table 24-1. Surface Mounting Type Soldering Conditions (3/3)
µPD789405AGC-×××-8BT-A: 80-pin plastic QFP (14 × 14)
µPD789406AGC-×××-8BT-A: 80-pin plastic QFP (14 × 14)
µPD789407AGC-×××-8BT-A: 80-pin plastic QFP (14 × 14)
µPD789415AGC-×××-8BT-A: 80-pin plastic QFP (14 × 14)
µPD789416AGC-×××-8BT-A: 80-pin plastic QFP (14 × 14)
µPD789417AGC-×××-8BT-A: 80-pin plastic QFP (14 × 14)
µPD78F9418AGC-8BT-A:
80-pin plastic QFP (14 × 14)
µPD789405AGK-×××-9EU-A: 80-pin plastic TQFP (fine pitch) (12 × 12)
µPD789406AGK-×××-9EU-A: 80-pin plastic TQFP (fine pitch) (12 × 12)
µPD789407AGK-×××-9EU-A: 80-pin plastic TQFP (fine pitch) (12 × 12)
µPD789415AGK-×××-9EU-A: 80-pin plastic TQFP (fine pitch) (12 × 12)
µPD789416AGK-×××-9EU-A: 80-pin plastic TQFP (fine pitch) (12 × 12)
µPD789417AGK-×××-9EU-A: 80-pin plastic TQFP (fine pitch) (12 × 12)
µPD78F9418GK-9EU-A:
80-pin plastic TQFP (fine pitch) (12 × 12)
Recommended Condition
Symbol
Soldering Method
Infrared reflow
Soldering Conditions
Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C
or higher), Count: Three times or less, Exposure limit: 7 daysNote (after
that, prebake at 125°C for 20 to 72 hours)
IR60-207-3
−
Wave soldering
Partial heating
When the pin pitch of the package is 0.65 mm or more, wave soldering
can also be performed.
For details, contact an NEC Electronics sales representative.
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
−
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Remark Products that have the part numbers suffixed by "-A" are lead-free products.
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APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for development of systems using the µPD789407A and
µPD789417A Subseries.
Figure A-1 shows development tools.
• Support of PC98-NX series
Unless specified otherwise, the products supported by IBM PC/AT™ compatibles can be used in the PC98-NX
series. When using the PC98-NX series, refer to the explanation of IBM PC/AT compatibles.
• Windows
Unless specified otherwise, “Windows” indicates the following operating systems.
• Windows 3.1
• Windows 95, 98, 2000
• Windows NT™ Ver.4.0
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Figure A-1. Development Tools
Software package
·
Software package
Language processing software
Debugging software
· Assembler package
· C compiler package
· Device file
· Integrated debugger
· System simulator
· C library source fileNote 1
Control software
·
Project Manager
(Windows version only)Note 2
Host machine
(PC or EWS)
Interface adapter
Power supply unit
Flash memory writing environment
Flash programmer
In-circuit emulator
Emulation board
Flash memory
writing adapter
Flash memory
Emulation probe
Conversion socket or
conversion adapter
Target system
Notes 1. C library source file is not included in the software package.
2. Project Manager is included in the assembler package.
Project Manager is used only in the Windows environment.
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APPENDIX A DEVELOPMENT TOOLS
A.1 Software Package
SP78K0S
Software tools for development of the 78K/0S Series are combined in this package.
The following tools are included.
Software package
RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S, and device files
Part number: µS××××SP78K0S
Remark ×××× in the part number differs depending on the operating system to be used.
µS××××SP78K0S
××××
AB17
BB17
Host Machine
OS
Supply Medium
CD-ROM
PC-9800 series, IBM PC/AT
compatibles
Japanese Windows
English Windows
A.2 Language Processing Software
RA78K0S
Program that converts program written in mnemonic into object codes that can be executed
by microcontroller.
Assembler package
In addition, automatic functions to generate a symbol table and optimize branch instructions
are also provided.
Used in combination with a device file (DF789418) (sold separately).
<Caution when used in PC environment>
The assembler package is a DOS-based application but may be used in the Windows
environment by using the Project Manager of Windows (included in the assembler package).
Part number: µS××××RA78K0S
CC78K0S
Program that converts program written in C language into object codes that can be executed
by microcontroller.
C compiler package
Used in combination with an assembler package (RA78K0S) and device file (DF789418)
(both sold separately).
<Caution when used in PC environment>
The C compiler package is a DOS-based application but may be used in the Windows
environment by using the Project Manager of Windows (included in the assembler package).
Part number: µS××××CC78K0S
DF789418Note 1
Device file
File containing the information inherent to the device.
Used in combination with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S (all sold
separately).
Part number: µS××××DF789418
CC78K0S-LNote 2
Source file of functions for generating object library included in C compiler package.
Necessary for changing object library included in C compiler package according to
customer’s specifications. Since this is a source file, its working environment does not
depend on any particular operating system.
C library source file
Part number: µS××××CC78K0S-L
Notes 1. DF789418 is a common file that can be used with RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S.
2. CC78K0S-L is not included in the software package (SP78K0S).
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Remark ×××× in the part number differs depending on the host machine and operating system to be used.
µS××××RA78K0S
µS××××CC78K0S
××××
AB13
BB13
AB17
BB17
3P17
3K17
Host Machine
PC-9800 series,
OS
Supply Medium
3.5-inch 2HD FD
Japanese Windows
English Windows
Japanese Windows
English Windows
HP-UXTM (Rel. 10.10)
IBM PC/AT compatibles
CD-ROM
HP9000 series 700TM
SPARCstationTM
SunOSTM (Rel. 4.1.4),
SolarisTM (Rel. 2.5.1)
µS××××DF789418
µS××××CC78K0S-L
××××
Host Machine
OS
Supply Medium
AB13
BB13
3P16
3K13
3K15
PC-9800 series,
Japanese Windows
English Windows
HP-UX (Rel. 10.10)
3.5-inch 2HD FD
IBM PC/AT compatibles
HP9000 series 700
SPARCstation
DAT
SunOS (Rel. 4.1.4),
Solaris (Rel. 2.5.1)
3.5-inch 2HD FD
1/4-inch CGMT
A.3 Control Software
Project Manager
Control software created for efficient development of the user program in the Windows
environment. User program development operations such as editor startup, build, and
debugger startup can be performed from the Project Manager.
<Caution>
The Project Manager is included in the assembler package (RA78K0S).
The Project Manager is used only in the Windows environment.
A.4 Flash Memory Writing Tools
Flashpro III (FL-PR3, PG-FP3)
Flashpro IV (FL-PR4, PG-FP4)
Flash programmer
Dedicated flash programmer for microcontrollers incorporating flash memory
FA-80GC-8BT
Adapter for writing to flash memory and connected to Flashpro III or Flashpro IV.
• FA-80GC-8BT: For 80-pin plastic QFP (GC-8BT type)
FA-80GK-9EU
• FA-80GK-9EU: For 80-pin plastic TQFP (GK-9EU type)
Flash memory writing adapter
Remark The FL-PR3, FL-PR4, FA-80GC-8BT, and FA-80GK-9EU are products made by Naito Densei Machida
Mfg. Co., Ltd. (TEL +81-45-475-4191).
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A.5 Debugging Tools (Hardware)
IE-78K0S-NS
In-circuit emulator for debugging a hardware and software of application system using the
78K/0S Series. Supports an integrated debugger (ID78K0S-NS). Used in combination with an
AC adapter, emulation probe, and interface adapter for connecting the host machine.
In-circuit emulator
IE-78K0S-NS-A
In-circuit emulator with functions expanded from the IE-78K0S-NS.
The debug function has been further enhanced with the addition of a coverage function, and
enhancement of the tracer function and timer function.
In-circuit emulator
IE-70000-MC-PS-B
AC adapter
Adapter for supplying power from AC 100 to 240 V outlet.
IE-70000-98-IF-C
Interface adapter
Adapter necessary when using a PC-9800 series PC (except notebook type) as the host
machine of the IE-78K0S-NS (C bus supported)
IE-70000-CD-IF-A
PC card interface
PC card and interface cable necessary when using a notebook PC as the host machine of the
IE-78K0S-NS (PCMCIA socket supported)
IE-70000-PC-IF-C
Interface adapter
Adapter necessary when using an IBM PC/AT compatible as the host machine of the
IE-78K0S-NS (ISA bus supported)
IE-70000-PCI-IF-A
Interface adapter
Adapter necessary when using a personal computer incorporating the PCI bus as the host
machine of the IE-78K0S-NS
IE-789418-NS-EM1
Emulation board
Board for emulating the peripheral hardware specific to the device. Used in combination with
an in-circuit emulator.
NP-80GC
Cable to connect an in-circuit emulator to the target system. Used in combination with the
EV-9200GC-80.
Emulation probe
EV-9200GC-80
Conversion socket
NP-80GC-TQ
Conversion socket to connect the NP-80GC to a target system board on which an 80-pin plastic
QFP (GC-8BT type) can be mounted.
Cable to connect an in-circuit emulator to the target system. Used in combination with the TGC-
080SBP.
NP-H80GC-TQ
Emulation probe
TGC-080SBP
Conversion adapter
Conversion adapter to connect the NP-80GC-TQ or NP-H80GC-TQ to a target system board on
which an 80-pin plastic QFP (GC-8BT type) can be mounted.
NP-80GK
Cable to connect an in-circuit emulator to the target system. Used in combination with the TGK-
080SDW.
NP-H80GK-TQ
Emulation probe
TGK-080SDW
Conversion adapter
Conversion adapter to connect the NP-80GK or NP-H80GK-TQ to a target system board on
which an 80-pin plastic TQFP (fine pitch) (GK-9EU type) can be mounted.
Remarks 1. The NP-80GC, NP-80GC-TQ, NP-H80GC-TQ, NP-80GK, and NP-H80GK-TQ are products made by
Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191).
2. The TGC-080SBP and TGK-080SDW are products made by TOKYO ELETECH CORPORATION.
For further information, contact: Daimaru Kogyo, Ltd.
Tokyo Electronics Department (TEL +81-3-3820-7112)
Osaka Electronics Department (TEL +81-6-6244-6672)
3. The EV-9200GC-80 is sold in five units as a set.
4. The TGC-080SBP and TGK-080SDW are sold in one set units.
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APPENDIX A DEVELOPMENT TOOLS
A.6 Debugging Tools (Software)
ID78K0S-NS
Integrated debugger
This debugger supports the in-circuit emulators IE-78K0S-NS and IE-78K0S-NS-A for the
78K/0S Series. The ID78K0S-NS is Windows-based software.
It has improved C-compatible debugging functions and can display the results of tracing with
the source program using an integrating window function that associates the source
program, disassemble display, and memory display with the trace result.
Used in combination with a device file (DF789418) (sold separately).
Part number: µS××××ID78K0S-NS
SM78K0S
System simulator
This is a system simulator for the 78K/0S Series. The SM78K0S is Windows-based software.
It can be used to debug the target system at C source level or assembler level while
simulating the operation of the target system on the host machine.
Using SM78K0S, the logic and performance of the application can be verified independently
of hardware development. Therefore, the development efficiency can be enhanced and the
software quality can be improved.
Used
in combination with a device file (DF789418) (sold separately).
Part number: µS××××SM78K0S
DF789418Note
Device file
File containing the information inherent to the device.
Used in combination with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S (all sold
separately).
Part number: µS××××DF789418
Note DF789418 is a common file that can be used with RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S.
Remark ×××× in the part number differs depending on the operating system and supply medium to be used.
µS××××ID78K0S-NS
µS××××SM78K0S
××××
AB13
BB13
AB17
BB17
Host Machine
PC-9800 series,
IBM PC/AT compatibles
OS
Japanese Windows
English Windows
Japanese Windows
English Windows
Supply Medium
3.5-inch 2HD FD
CD-ROM
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APPENDIX A DEVELOPMENT TOOLS
A.7 Package Drawings of Conversion Socket and Conversion Adapter
A.7.1 Package drawing and recommended footprint of conversion socket (EV-9200GC-80)
Figure A-2. Package Drawing of EV-9200GC-80 (for Reference)
Based on EV-9200GC-80
(1) Package drawing (in mm)
A
B
M
N
E
O
F
EV-9200GC-80
1
No.1 pin index
P
G
H
I
EV-9200GC-80-G1E
ITEM
A
MILLIMETERS
18.0
14.4
14.4
18.0
4-C 2.0
0.8
INCHES
0.709
0.567
0.567
0.709
4-C 0.079
0.031
0.236
0.63
B
C
D
E
F
G
H
I
6.0
16.0
18.7
6.0
0.736
0.236
0.63
J
K
16.0
18.7
8.2
L
0.736
0.323
0.315
0.098
0.079
0.014
0.091
0.059
M
N
O
P
8.0
2.5
2.0
Q
R
S
0.35
2.3
1.5
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APPENDIX A DEVELOPMENT TOOLS
Figure A-3. Recommended Footprint of EV-9200GC-80 (for Reference)
Based on EV-9200GC-80
(2) Pad drawing (in mm)
G
J
K
L
C
B
A
EV-9200GC-80-P1E
ITEM
MILLIMETERS
INCHES
0.776
A
B
C
D
E
F
G
H
I
19.7
15.0
0.591
+0.001
+0.003
–0.002
0.65 0.02 × 19=12.35 0.05 0.026
×
×
0.748=0.486
0.748=0.486
–0.002
+0.001
–0.002
+0.003
–0.002
0.65 0.02 × 19=12.35 0.05 0.026
15.0
0.591
0.776
0.236
0.236
19.7
+0.003
–0.002
6.0 0.05
6.0 0.05
0.35 0.02
+0.003
–0.002
+0.001
–0.001
0.014
+0.001
φ
φ
φ
φ
J
2.36 0.03
2.3
0.093–0.002
φ
φ
K
L
0.091
+0.001
1.57 0.03
0.062–0.002
Dimensions of mount pad for EV-9200 and that for
target device (QFP) may be different in some parts.
For the recommended mount pad dimensions for
QFP, refer to "Semiconductor Device Mount Manual"
(http://www.necel.com/pkg/en/mount/index.html).
Caution
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APPENDIX A DEVELOPMENT TOOLS
A.7.2 Package drawing of conversion adapter (TGK-080SDW)
Figure A-4. Package Drawing of TGK-080SDW (for Reference)
TGK-080SDW (TQPACK080SD + TQSOCKET080SDW)
Package dimension (unit: mm)
A
B
C
U
V
T
D
R
Q
Q
Q
e
c
M2 screw
b
H
G F E
P
a
S
O
O
O
N
d
Z
K
f
W
X
Y
I J JJ
L LLM
g
v
k
u
t
r
j
i
s
q
h
p
Protrusion : 4 places
o
l
n
m
ITEM MILLIMETERS
INCHES
0.709
0.463
ITEM MILLIMETERS
INCHES
0.020x0.748=0.374 0.004
0.010
A
B
C
D
E
F
18.0
11.77
0.5x19=9.5
0.5
a
b
c
d
e
f
0.5x19=9.5 0.10
0.25
φ
φ
φ
φ
φ
φ
φ
φ
φ
φ
0.020x0.748=0.374
0.020
5.3
5.3
1.3
3.55
0.3
0.209
0.209
0.051
0.140
0.012
0.5x19=9.5
11.77
18.0
0.5
0.020x0.748=0.374
0.463
G
H
I
0.709
g
h
i
0.020
1.85 0.2
0.073 0.008
1.58
1.2
0.062
3.5
0.138
J
0.047
j
2.0
0.079
K
L
7.64
1.2
0.301
k
l
3.0
0.118
0.25
0.010
0.047
M
N
O
P
Q
R
S
T
1.58
1.58
1.2
0.062
m
n
o
p
q
r
14.0
0.551
0.062
1.4 0.2
1.4 0.2
0.055 0.008
0.055 0.008
0.047
φ
φ
7.64
1.2
0.301
h=1.8 1.3
h=0.071 0.051
0.047
0~5°
5.9
0.8
2.4
2.7
3.9
0.000~0.197°
0.232
1.58
0.062
φ
φ
3.55
0.140
s
t
0.031
C 2.0
12.31
10.17
6.8
C 0.079
0.094
U
V
W
X
Y
Z
0.485
u
v
0.106
0.400
0.154
0.268
TGK-080SDW-G1E
8.24
0.324
14.8
0.583
1.4 0.2
0.055 0.008
note: Product by TOKYO ELETECH CORPORATION.
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APPENDIX A DEVELOPMENT TOOLS
A.7.3 Package drawing of conversion adapter (TGC-080SBP)
Figure A-5. Package Drawing of TGC-080SBP (for Reference)
Reference diagram: TGC-080SBP (TQPACK080SB+TQSOCKET080SBP)
Package dimension (unit: mm)
J
A
B
I
K
C
W
N
R
G F E D
L
V
S
Protrusion height
T
U
M
O
P
Q
H
X
Y
Z
g
m
l
c
f
a
ITEM MILLIMETERS
INCHES
0.827
ITEM MILLIMETERS
INCHES
(0.667)
A
B
C
D
E
F
21.0
a
b
c
d
e
f
(16.95)
7.35
1.2
b
e
d
0.65x19=12.35
0.65
0.026x0.748=0.486
0.026
0.289
0.047
0.407
1.85
3.5
0.073
10.35
12.75
15.15
17.55
14.47
C 2.0
14.95
13.95
13.7
0.502
0.138
j
k
h
0.596
2.0
0.079
i
G
H
I
0.691
g
h
i
6.0
0.236
0.570
0.25
13.95
1.025
1.025
2.4
0.010
0.549
C 0.079
0.589
j
0.040
J
K
L
0.549
k
l
0.040
0.539
0.094
M
N
O
P
Q
R
S
T
1.15
0.045
m
2.7
0.106
1.15
0.045
TGC-080SBP-G0E
12.62
17.52
21.0
0.497
0.690
0.827
5.0
0.197
4-
φ
1.3
4-
φ0.051
1.8
0.071
U
V
W
X
Y
Z
φ
7.7
5.3
φ
0.209
0.303
4-C 1.0
4-C 0.039
φ
φ
φ
3.55
0.9
φ
φ
φ
0.140
0.035
0.012
0.3
note: Product by TOKYO ELETECH CORPORATION.
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APPENDIX B NOTES ON TARGET SYSTEM DESIGN
Figures B-1 to B-4 show the conditions when connecting the emulation probe to the conversion adapter or
conversion socket. Follow the configuration below and consider the shape of parts to be mounted on the target
system when designing a system.
(1) NP-80GC, NP-80GC-TQ, NP-H80GC-TQ
Figure B-1. Distance Between In-Circuit Emulator and Conversion Socket (80GC)
In-circuit emulator
IE-78K0S-NS or IE-78K0S-NS-A
Target system
Emulation board
IE-789418-NS-EM1
170 mmNote
CN1
Emulation probe
NP-80GC, NP-80GC-TQ
NP-H80GC-TQ
Conversion socket: EV-9200GC-80 or
Conversion adapter: TGC-080SBP
Note When NP-H80GC-TQ is used, the distance is 370 mm.
Remark NP-80GC, NP-80GC-TQ, and NP-H80GC-TQ are products of Naito Densei Machida Mfg. Co., Ltd.
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APPENDIX B NOTES ON TARGET SYSTEM DESIGN
Figure B-2. Connection Condition of Target System (NP-80GC-TQ)
Emulation board
IE-789418-NS-EM1
Extension probe
NP-80GC-TQ
23 mm
Conversion
adapter
TGC-080SBP
11 mm
40 mm
34 mm
Target system
Remark NP-80GC-TQ is a product of Naito Densei Machida Mfg. Co., Ltd.
TGC-080SBP is a product of TOKYO ELETECH CORPORATION.
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APPENDIX B NOTES ON TARGET SYSTEM DESIGN
(2) NP-80GK, NP-H80GK-TQ
Figure B-3. Distance Between In-Circuit Emulator and Conversion Adapter (80GK)
In-circuit emulator
IE-78K0S-NS or IE-78K0S-NS-A
Target system
Emulation board
IE-789418-NS-EM1
170 mmNote
CN1
Emulation probe
NP-80GK, NP-H80GK-TQ
Conversion adapter
TGK-080SDW
Note When NP-H80GK-TQ is used, the distance is 370 mm.
Remark NP-80GK and NP-H80GK-TQ are products of Naito Densei Machida Mfg. Co., Ltd.
TGK-080SDW is a product of TOKYO ELETECH CORPORATION.
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APPENDIX B NOTES ON TARGET SYSTEM DESIGN
Figure B-4. Connection Condition of Target System (NP-80GK)
Emulation board
IE-789418-NS-EM1
Extension probe
NP-80GK
23 mm
Conversion
adapter
TGK-080SDW
11 mm
40 mm
34 mm
Target system
Remark NP-80GK is a product of Naito Densei Machida Mfg. Co., Ltd.
TGK-080SDW is a product of TOKYO ELETECH CORPORATION.
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APPENDIX C REGISTER INDEX
C.1 Register Index (Alphabetic Order of Register Name)
[A]
A/D conversion result register 0 (ADCR0).................................................................................................... 141, 154
A/D converter mode register 0 (ADM0) ........................................................................................................ 143, 156
A/D input selection register 0 (ADS0)........................................................................................................... 144, 157
Asynchronous serial interface mode register 00 (ASIM00)........................................................... 177, 184, 186, 199
Asynchronous serial interface status register 00 (ASIS00)........................................................................... 179, 187
[B]
Baud rate generator control register 00 (BRGC00) .............................................................................. 180, 188, 200
[C]
Comparator mode register 0 (CMPRM0)..............................................................................................................168
[E]
8-bit compare register 00 (CR00).........................................................................................................................117
8-bit compare register 01 (CR01).........................................................................................................................117
8-bit compare register 02 (CR02).........................................................................................................................117
8-bit timer counter 00 (TM00)...............................................................................................................................117
8-bit timer counter 01 (TM01)...............................................................................................................................117
8-bit timer counter 02 (TM02)...............................................................................................................................117
8-bit timer mode control register 00 (TMC00).......................................................................................................118
8-bit timer mode control register 01 (TMC01).......................................................................................................119
8-bit timer mode control register 02 (TMC02).......................................................................................................120
External interrupt mode register 0 (INTM0) ..........................................................................................................234
External interrupt mode register 1 (INTM1) ..........................................................................................................235
[ I ]
Interrupt mask flag register 0 (MK0).....................................................................................................................233
Interrupt mask flag register 1 (MK1).....................................................................................................................233
Interrupt request flag register 0 (IF0)....................................................................................................................232
Interrupt request flag register 1 (IF1)....................................................................................................................232
[K]
Key return mode register 00 (KRM00)..................................................................................................................237
[L]
LCD clock control register 0 (LCDC0) ..................................................................................................................207
LCD display mode register 0 (LCDM0).................................................................................................................205
LCD port selector 0 (LPS0) ..................................................................................................................................206
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APPENDIX C REGISTER INDEX
[O]
Oscillation stabilization time selection register (OSTS).........................................................................................245
[P]
Port 0 (P0)..............................................................................................................................................................72
Port 2 (P2)..............................................................................................................................................................73
Port 4 (P4)..............................................................................................................................................................78
Port 5 (P5)..............................................................................................................................................................80
Port 6 (P6)..............................................................................................................................................................81
Port 8 (P8)..............................................................................................................................................................83
Port 9 (P9)..............................................................................................................................................................84
Port mode register 0 (PM0) ....................................................................................................................................85
Port mode register 2 (PM2) ....................................................................................................................85, 106, 121
Port mode register 4 (PM4) ....................................................................................................................................85
Port mode register 5 (PM5) ....................................................................................................................................85
Port mode register 8 (PM8) ....................................................................................................................................85
Port mode register 9 (PM9) ....................................................................................................................................85
Processor clock control register (PCC)...................................................................................................................91
Pull-up resistor option register 0 (PU0)...................................................................................................................86
Pull-up resistor option register 1 (PU1)...................................................................................................................86
Pull-up resistor option register 2 (PU2)...................................................................................................................86
[R]
Receive buffer register 00 (RXB00)......................................................................................................................175
[S]
Serial operation mode register 00 (CSIM00) ................................................................................176, 183, 185, 198
16-bit capture register 50 (TCP50) .......................................................................................................................103
16-bit compare register 50 (CR50) .......................................................................................................................103
16-bit timer counter 50 (TM50) .............................................................................................................................103
16-bit timer mode control register 50 (TMC50).....................................................................................................104
Subclock control register (CSS)..............................................................................................................................93
Suboscillation mode register (SCKM).....................................................................................................................92
[T]
Timer clock selection register 2 (TCL2)................................................................................................................136
Transmit shift register 00 (TXS00)........................................................................................................................175
[W]
Watch timer mode control register (WTM)............................................................................................................131
Watchdog timer mode register (WDTM)...............................................................................................................137
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User’s Manual U13952EJ3V1UD
APPENDIX C REGISTER INDEX
C.2 Register Index (Alphabetic Order of Register Symbol)
[A]
ADCR0:
ADM0:
A/D conversion result register 0 ............................................................................................... 141, 154
A/D converter mode register 0 ................................................................................................. 143, 156
A/D input selection register 0 ................................................................................................... 144, 157
Asynchronous serial interface mode register 00 ...................................................... 177, 184, 186, 199
Asynchronous serial interface status register 00...................................................................... 179, 187
ADS0:
ASIM00:
ASIS00:
[B]
BRGC00: Baud rate generator control register 00............................................................................ 180, 188, 200
[C]
CMPRM0: Comparator mode register 0 ............................................................................................................168
CR00:
CR01:
CR02:
CR50:
CSIM00:
CSS:
8-bit compare register 00 .................................................................................................................117
8-bit compare register 01 .................................................................................................................117
8-bit compare register 02 .................................................................................................................117
16-bit compare register 50 ...............................................................................................................103
Serial operation mode register 00 ............................................................................ 176, 183, 185, 198
Subclock control register....................................................................................................................93
[ I ]
IF0:
Interrupt request flag register 0........................................................................................................232
Interrupt request flag register 1........................................................................................................232
External interrupt mode register 0....................................................................................................234
External interrupt mode register 1....................................................................................................235
IF1:
INTM0:
INTM1:
[K]
KRM00:
Key return mode register 00.............................................................................................................237
[L]
LCDC0:
LCDM0:
LPS0:
LCD clock control register 0.............................................................................................................207
LCD display mode register 0............................................................................................................205
LCD port selector 0 ..........................................................................................................................206
[M]
MK0:
MK1:
Interrupt mask flag register 0 ...........................................................................................................233
Interrupt mask flag register 1 ...........................................................................................................233
[O]
OSTS:
Oscillation stabilization time selection register .................................................................................245
[P]
P0:
P2:
P4:
P5:
P6:
Port 0 .................................................................................................................................................72
Port 2 .................................................................................................................................................73
Port 4 .................................................................................................................................................78
Port 5 .................................................................................................................................................80
Port 6 .................................................................................................................................................81
User’s Manual U13952EJ3V1UD
317
APPENDIX C REGISTER INDEX
P8:
Port 8..................................................................................................................................................83
Port 9..................................................................................................................................................84
Processor clock control register .........................................................................................................91
Port mode register 0...........................................................................................................................85
Port mode register 2...........................................................................................................85, 106, 121
Port mode register 4...........................................................................................................................85
Port mode register 5...........................................................................................................................85
Port mode register 8...........................................................................................................................85
Port mode register 9...........................................................................................................................85
Pull-up resistor option register 0.........................................................................................................86
Pull-up resistor option register 1.........................................................................................................86
Pull-up resistor option register 2.........................................................................................................86
P9:
PCC:
PM0:
PM2:
PM4:
PM5:
PM8:
PM9:
PU0:
PU1:
PU2:
[R]
RXB00:
Receive buffer register 00 ................................................................................................................175
Suboscillation mode register ..............................................................................................................92
[S]
SCKM:
[T]
TCL2:
Timer clock selection register 2........................................................................................................136
16-bit capture register 50 .................................................................................................................103
8-bit timer counter 00 .......................................................................................................................117
8-bit timer counter 01 .......................................................................................................................117
8-bit timer counter 02 .......................................................................................................................117
16-bit timer counter 50 .....................................................................................................................103
8-bit timer mode control register 00..................................................................................................118
8-bit timer mode control register 01..................................................................................................119
8-bit timer mode control register 02..................................................................................................120
16-bit timer mode control register 50................................................................................................104
Transmit shift register 00..................................................................................................................175
TCP50:
TM00:
TM01:
TM02:
TM50:
TMC00:
TMC01:
TMC02:
TMC50:
TXS00:
[W]
WDTM:
WTM:
Watchdog timer mode register .........................................................................................................137
Watch timer mode control register....................................................................................................131
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User’s Manual U13952EJ3V1UD
APPENDIX D REVISION HISTORY
Here is the revision history of this manual. The “Applied to:” column indicates the chapters of each edition in which
the revision was applied.
(1/2)
Edition
2nd
Revision from Previous Edition
Applied to:
Throughout
Modification of packages
• Deletion of 80-pin plastic TQFP (fine pitch) (GK-BE9 type)
• Addition of 80-pin plastic TQFP (fine pitch) (GK-9EU type)
Modification of Table 2-1 Types of Pin I/O Circuits
CHAPTER 2 PIN FUNCTIONS
Modification of Table 4-3 Port Mode Register and Output Latch Settings When
CHAPTER 4 PORT
FUNCTIONS
Using Alternate Functions
Modification of Caution 2 in 6.2 Configuration of 16-Bit Timer (1) 16-bit compare CHAPTER 6 16-BIT TIMER
register 50 (CR50)
Modification of Figure 6-2 Format of 16-Bit Timer Mode Control Register 50
Addition of Caution in 6.4.1 Operation as timer interrupt
Modification of Figure 6-8 Settings of 16-Bit Timer Mode Control Register 50 for
Capture Operation
Addition of Caution in 7.4.3 Operation as square-wave output
CHAPTER 7 8-BIT TIMER/
EVENT COUNTER
Addition of Caution in 10.4.1 Basic operation of 8-bit A/D converter
CHAPTER 10 8-BIT A/D
CONVERTER (µPD789407A
SUBSERIES)
Addition of Caution in 11.4.1 Basic operation of 10-bit A/D converter
CHAPTER 11 10-BIT A/D
CONVERTER (µPD789417A
SUBSERIES)
Addition of Caution in Table 18-1 Differences Between µPD78F9418A and Mask
CHAPTER 18 µPD78F9418A
ROM Versions
Modification of Table 18-2 Communication Mode and addition of Note in it
Modification of Figure 18-4 Flashpro III Connection Example in Pseudo 3-Wire
Mode (When P0 Is Used)
Modification of Table 18-4 Example of Settings for PG-FP3
Modification of product name of flash memory programming adapter in A.2 Flash
APPENDIX A DEVELOPMENT
TOOLS
Memory Programming Tools
Addition of product name of conversion adapter corresponding to each emulation
probe in A.3.1 Hardware
3rd
Modification of pin handling of AVREF pin and VPP pin
Addition of Note related to feedback resistor
CHAPTER 2 PIN FUNCTIONS
CHAPTER 5 CLOCK
GENERATOR
Addition of 6.5 Cautions on Using 16-Bit Timer 50
CHAPTER 6 16-BIT TIMER 50
Addition of (8) Input impedance of ANI0 to ANI6 pins in 10.5 Cautions on Using CHAPTER 10 8-BIT A/D
CONVERTER (µPD789407A
8-Bit A/D Converter
SUBSERIES)
319
User’s Manual U13952EJ3V1UD
(2/2)
Edition
3rd
Revision from Previous Edition
Applied to:
Modification of description of (2) A/D conversion result register 0 (ADCR0) in
CHAPTER 11 10-BIT A/D
CONVERTER (µPD789417A
11.2 Configuration of 10-Bit A/D Converter
SUBSERIES)
Addition of (8) Input impedance of ANI0 to ANI6 pins in 11.5 Cautions on Using
10-Bit A/D Converter
Addition of description on reading receive data of UART
CHAPTER 13 SERIAL
INTERFACE 00
Addition of Caution in Figure 15-2 Format of Interrupt Request Flag Register
Addition of Caution in Figure 15-7 Format of Key Return Mode Register 00
CHAPTER 15 INTERRUPT
FUNCTIONS
CHAPTER 18 µPD78F9418A
Addition of description on pull-up resistor and divider resistor for LCD driving in
Table 18-1 Differences Between µPD78F9418A and Mask ROM Versions
Overall revision of contents related to flash memory programming as 18.1 Flash
Memory Characteristics
Addition of electrical specifications
CHAPTER 21 ELECTRICAL
SPECIFICATIONS
Addition of characteristics curves (reference values)
CHAPTER 22
CHARACTERISTICS CURVES
(REFERENCE VALUES)
Addition of package drawings
CHAPTER 23 PACKAGE
DRAWINGS
Addition of recommended soldering conditions
CHAPTER 24
RECOMMENDED SOLDERING
CONDITIONS
Overall revision of contents of development tools
Deletion of embedded software
APPENDIX A DEVELOPMENT
TOOLS
Addition of notes on target system design
APPENDIX B NOTES ON
TARGET SYSTEM DESIGN
3rd Edition Modification of 1.3 Ordering Information
CHAPTER 1 GENERAL
(Modification
Version)
Addition of Table 24-1. Surface Mounting Type Soldering Conditions (3/3)
CHAPTER 24
RECOMMENDED SOLDERING
CONDITIONS
320
User’s Manual U13952EJ3V1UD
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