UPD6461GS-102 [RENESAS]
IC,TV/VIDEO CIRCUIT,ON-SCREEN DISPLAY CIRCUIT,CMOS,SSOP,20PIN,PLASTIC;
| 型号： | UPD6461GS-102 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC,TV/VIDEO CIRCUIT,ON-SCREEN DISPLAY CIRCUIT,CMOS,SSOP,20PIN,PLASTIC 光电二极管 外围集成电路 电视 |
| 文件： | 总60页 (文件大小：489K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD6461, 6462
CMOS LSI CHIP FOR CAMCORDER ON-SCREEN CHARACTER DISPLAY
(12 ROWS × 24 COLUMNS)
The µPD6461, 6462 are CMOS LSI chips designed to provide on-screen character display for camcorders. When
combined with a microcontroller, the µPD6461, 6462 control the display of the characters displayed in the viewfinder (count,
time, date, etc.) and the recording of characters onto video tape (time, date, etc.).
Each character is created using 12 (width) × 18 (height) dots. Kanji characters and graphic symbols can also be displayed
by using two or more characters. The µPD6461, 6462 are compatible with color viewfinders and can output character signals
to three channels, the RGB channel for the color viewfinder and the VC1 and VC2 channels for the recording system and
monitor terminal.
The µPD6461, 6462 also have a power-on clear function and video RAM batch clear command, enabling the number
of operations assigned to the microcontroller to be reduced.
FEATURES
• Maximum number of characters: 12 rows × 24 columns (288 characters)
• Number of character patterns : 256 (µPD6461)/128 (µPD6462) (stored in ROM). Each pattern can be changed by
specifying a mask code option.
• Character size
: One dot per line or one dot per two lines (field)
• Number of character colors
• Background
: 8
: No background, minimum background, or overall background can be selected for the
entire screen, together with rimming ON/OFF function. Any one of 8 different colors
is selectable as the background color and together with the rim color (black or white)
selectable per screen.
• Dot matrix
• Blinking
: Each character consists of 12 (width) × 18 (height) dots. There is no gap between
adjacent characters.
: Blinking can be turned on/off for each character. The blinking ratio is 1:1. The blinking
frequency can be selected from approx. 1 Hz, 2 Hz, and 0.5 Hz for the entire screen.
: Specified characters can be displayed in reverse video.
• Reversed characters
• Character signal output
: Character signals can be output to three channels. Output mode (1) (RGB + BLK, VC1
+ VBLK1, and VC2 + VBLK2) or output mode (2) (R + RBLK, B + BBLK, and G + GBLK) can
be selected by specifying a mask option. For output mode 1, three output formats are
available for the VC1 and VC2 channels (options A, B, and C).
: Video RAM batch clear command and power-on clear function
• Clearing of video RAM
• Interface with a microcontroller : 8-bit serial input supporting variable word length (LSB first or MSB first can be selected
by specifying a mask option.)
• Supply voltage
: Low-voltage operation possible (supply voltage range: 2.7 to 5.5 V)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
The mark
shows major revised points.
Document No. S13320EJ2V0DS00 (2nd edition)
Date Published April 2001 N CP(K)
Printed in Japan
1998
©
µPD6461, 6462
ORDERING INFORMATION
Part number
Package
µPD6461GS-xxx
µPD6461GT-xxx
µPD6462GS-xxx
20-pin plastic SSOP (7.62 mm (300))
24-pin plastic SOP (9.53 mm (375))
20-pin plastic SSOP (7.62 mm(300))
Remarks 1. xxx is a ROM code suffix.
2. NEC’s standard models are the µPD6461GS-101/102, µPD6462GS-001. For the details of the
character generator ROM, refer to 5. CHARACTER PATTERNS.
µPD6461GS-101: MSB first/Specified in three-line units/RGB+3BLK/Option B/LC oscillation
µPD6461GS-102: MSB first/Specified in three-line units/RGB+VC1+VC2/Option B/LC oscillation
µPD6462GS-001: MSB first/Specified in three-line units/RGB+VC1+VC2/Option C/LC oscillation
2
Data Sheet S13320EJ2V0DS
TEST
V
DD
DATA
CLK
Data input shift
register
Instruction decoder
Control signals
GND
PCL
CS
Horizontal address
register for
display position
Character size
register
Write address
counter
Video RAM
Back-
Display
ground control
control data
Char- Color Blink Re-
acter data data verse put
data 3 bits 1 bit data speci-
Out-
data
register
register
8 bits × 288 × 288 1 bit
fication
Horizontal size
counter
Horizontal
position counter
Horizontal address
counter
CKOUT
× 288 words words × 288 data
words
words 1 bit
× 288
words
OSCIN
Vertical address
register for
display position
Character
generator ROM
12 × 18 bits
× 256 words
Oscil-
lator
OSCOUT
(
µ
PD6461)
/ × 128 words
PD6462)
(
µ
Synchro-
nization
protection
circuit
Hsync
Vsync
Vertical size
counter
Vertical position
counter
Vertical address
counter
Output controller
µ
VR
VG
V
B
V
BLK
V
C1 BLK1
(BBLK
(RBLK
VC2 BLK2
)
(BBLK
)
)
Remark Signals in (
) are set by a mask option (RGB + RGB compatible blanking).
µPD6461, 6462
PIN CONFIGURATION (TOP VIEW)
20-pin plastic SSOP (7.62 mm (300))
µPD6461GS-xxx
µPD6462GS-xxx
CLK
CS
1
2
20
19
18
17
16
15
14
13
12
11
Hsync
Vsync
VB
DATA
PCL
3
4
VG
VDD
5
VR
CKOUT
OSCOUT
OSCIN
TEST
GND
6
VBLK (BBLK)
VC2 (GBLK)
BLK2 (RBLK)
VC1
7
8
9
10
BLK1
24-pin plastic SOP (9.53 mm (375))
µPD6461GT-xxx
CLK
CS
1
24
23
22
21
20
19
18
17
16
15
14
13
Hsync
Vsync
N.C.
2
N.C.
DATA
PCL
3
4
V
V
V
V
V
B
5
G
V
DD
6
R
CKOUT
OSCOUT
OSCIN
7
BLK (BBLK
)
8
C2 (GBLK
)
9
BLK2 (RBLK
)
TEST
GND
10
11
12
V
C1
BLK1
N.C.
N.C.
Remarks 1. xxx indicates a ROM code suffix.
2. Signals in ( ) are set by a mask option (RGB + RGB compatible blanking).
4
Data Sheet S13320EJ2V0DS
µPD6461, 6462
BBLK
: Blanking B
BLK1, BLK2: Blanking Output 1, 2
CKOUT
CLK
: Clock Output
: Clock Input
CS
: Chip Select
DATA
GBLK
GND
Hsync
N.C.
OSCIN
OSCOUT
PCL
: Data Input
: Blanking G
: Ground
: Horizontal Synchronous Signal Input
: No Connection
: Oscillator Input
: Oscillator Output
: Power-on Clear
RBLK
: Blanking R
TEST
VB
: Test
: Character Signal Output
: Blanking Signal Output for VR, VG, VB
: Character Signal Output 1, 2
: Power Supply
VBLK
VC1, VC2
VDD
VG
: Character Signal Output
: Character Signal Output
: Vertical Synchronous Signal Input
VR
Vsync
Data Sheet S13320EJ2V0DS
5
µPD6461, 6462
PIN FUNCTIONS
Note 1
Note 2
Note 2
Pin No.
1
Symbol
Function
Clock input
Description
CLK
Input pin for the data read clock. The data input to the DATA pin is read at
rising edges of the clock.
2
CS
Chip select input
Serial data input
Serial transfer is accepted when this pin is low.
3 (4)
DATA
Input pin for control data. Data is read in synchronization with the clock input
to the CLK pin.
4 (5)
PCL
Power-on clear
Pin used for the power-on clear function. After power-on, set this pin from low
to high to initialize the IC.
5 (6)
6 (7)
VDD
Power supply
Clock output
Power supply pin
CKOUT
N-ch open-drain output pin used to check the oscillation frequency
7 (8)
8 (9)
OSCOUT
OSCIN
LC oscillator input/
output
Input and output pins for the oscillator for generating a dot clock. Connect
the oscillation coil and capacitors to these pins.
OSCIN: External clock
input
(When an external clock input is selected by specifying a mask option, input
an external clock (synchronized with Hsync) to the OSCIN pin. Leave the
OSCOUT pin open.)
9 (10)
TEST
Test pin
Pin used for testing the IC. Usually, connect this pin to ground. The IC cannot
enter test mode while this pin is connected to ground.
10 (11)
11 (14)
GND
Ground pin
Connect this pin to the system ground.
BLK1
Blanking signal output 1
Pin used to output the blanking signal for the video signal output from the VC1
pin. The blanking signal is high active.
(When RGB compatible blanking has been selected by specifying a mask
option, this pin outputs the logical OR of RBLK, GBLK, and BBLK.)
12 (15)
13 (16)
VC1
Character signal output
1
Pin used to output a high-active character signal.
(When RGB compatible blanking has been selected by specifying a mask
option, this pin outputs the logical OR of VR, VG, and VB.)
BLK2
Blanking signal output 2
(blanking R)
Pin used to output the blanking signal for the video signal output from the VC2
pin. The blanking signal is high active.
(RBLK)
(This pin outputs the blanking signal for the video signal output from the VR
pin. The blanking signal is high active.)
14 (17)
15 (18)
VC2
Character signal output
Pin used to output a high-active character signal.
(GBLK)
2
(This pin outputs the blanking signal for the video signal output from the VG
pin. The blanking signal is high active.)
(blanking G)
VBLK
Blanking signal output
(blanking B)
Pin used to output the blanking signal for the video signals output from the
VR, VG, and VB pins. The blanking signal is high active.
(BBLK)
(This pin outputs the blanking signal for the video signal output from the VB
pin. The blanking signal is high active.)
16 (19)
17 (20)
18 (21)
VR
VG
VB
Character signal output
Pins used to output high-active character signals.
19 (23)
Vsync
Hsync
N.C.
Vertical synchronizing
signal input
Input a low-active vertical synchronizing signal to this pin.
20 (24)
Horizontal synchroniz-
ing signal input
Input a low-active horizontal synchronizing signal to this pin.
(3, 12, 13, 22)
No connection
Vacant pin
Notes 1. Pin numbers indicated in (
) are that of the µPD6461GT-xxx.
2. Signals in (
) are set by a mask option (RGB + RGB compatible blanking).
6
Data Sheet S13320EJ2V0DS
µPD6461, 6462
CONTENTS
1. MASK CODE OPTIONS ...........................................................................................................................
8
8
9
1.1
1.2
1.3
1.4
MASK CODE OPTIONS..................................................................................................................................
HOW TO SELECT MASK OPTIONS .............................................................................................................
APPLICATION BLOCK DIAGRAMS.............................................................................................................. 10
DISPLAY IN RGB+VC1+VC2 MODE ................................................................................................................ 11
1.4.1 Character Signal Output When Option A is Selected .................................................................. 14
1.4.2 Character Signal Output When Option B is Selected .................................................................. 15
1.4.3 Character Signal Output When Option C is Selected .................................................................. 16
1.4.4 Display of VC2-Specified Characters ............................................................................................... 17
OUTPUTTING BACKGROUND ...................................................................................................................... 18
1.5
2. COMMANDS ............................................................................................................................................. 19
2.1
2.2
2.3
COMMAND FORMAT ..................................................................................................................................... 19
COMMANDS AND THEIR BITS ..................................................................................................................... 19
POWER-ON CLEAR FUNCTION ................................................................................................................... 21
3. COMMAND DETAILS............................................................................................................................... 22
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
VIDEO RAM BATCH CLEAR COMMAND .................................................................................................... 22
CHARACTER DISPLAY CONTROL COMMAND.......................................................................................... 23
BACKGROUND/RIM COLOR CONTROL COMMAND ................................................................................. 24
3-CHANNEL INDEPENDENT DISPLAY ON/OFF COMMAND .................................................................... 25
CHARACTER REVERSE ON/OFF COMMAND ............................................................................................ 26
CHARACTER DISPLAY POSITION CONTROL COMMAND ....................................................................... 28
WRITE ADDRESS CONTROL COMMAND ................................................................................................... 30
OUTPUT PIN CONTROL COMMAND ........................................................................................................... 31
CHARACTER SIZE CONTROL COMMAND ................................................................................................. 32
3.10 3-CHANNEL INDEPENDENT BACKGROUND CONTROL COMMAND ..................................................... 33
3.11 TEST MODE COMMAND................................................................................................................................ 35
3.12 DISPLAYED CHARACTER CONTROL COMMAND .................................................................................... 35
4. COMMAND TRANSFER .......................................................................................................................... 38
4.1
4.2
4.3
4.4
1-BYTE COMMANDS...................................................................................................................................... 38
2-BYTE COMMANDS...................................................................................................................................... 38
2-BYTE CONTINUOUS COMMAND .............................................................................................................. 38
CONTINUOUS INPUT OF COMMAND .......................................................................................................... 39
4.4.1 When End Code is Not Used ............................................................................................................. 39
4.4.2 When End Code is Used .................................................................................................................... 39
5. CHARACTER PATTERNS ....................................................................................................................... 40
6. ELECTRICAL CHARACTERISTICS ....................................................................................................... 50
7. APPLICATION CIRCUIT EXAMPLE ....................................................................................................... 54
8. PACKAGE DRAWINGS ........................................................................................................................... 55
9. RECOMMENDED SOLDERING CONDITIONS .................................................................................... 57
Data Sheet S13320EJ2V0DS
7
µPD6461, 6462
1. MASK CODE OPTIONS
1.1 MASK CODE OPTIONS
The µPD6461, µPD6462 provide mask options for selecting the following items:
Item
Selections
Data transfer
LSB first
MSB first
(1)
(2)
(3)
(4)
(5)
Vertical display start position
Pin selection
Specified in three-line units
RGB+VC1+VC2
Specified in nine-line units
RGB+3BLK
Output distribution format
Dot clock
Option A
Option B
Option C
LC oscillation
External clock input
(1) Data transfer
Select the command transfer format.
(2) Vertical display start position
Select the units used for specifying the vertical display start position of the character display area. In three-line units,
the vertical display start position can be set more finely than in nine-line units.
(3) Pin selection
Select the pins used to output character signals. In RGB+VC1+VC2 mode, character signals are output from the VR,
VG, VB, VBLK, VC1, BLK1, VC2, and BLK2 pins. In RGB+3BLK mode, character signals are output from the VR, VG, VB,
RBLK, GBLK, BBLK, VC1, and BLK1 pins.
When displaying colored characters in a color viewfinder, select RGB+VC1+VC2 mode. When assigning a separate
character signal for each color, select RGB+3BLK mode.
(4) Output distribution format
Select the format to be used to distribute character signals to the VC1 and VC2 channels when RGB+VC1+VC2 mode
is selected. (When RGB+3BLK mode is selected, select option A as the output distribution format. Options B and C
are invalid.)
When an on-screen IC is used in a camcorder, some information is displayed in the viewfinder and recorded onto
video tape (such as a date and title). Other information, however, need only be displayed in the viewfinder (battery
or focus alarm and tape count). The µPD6461, 6462 can distribute such information to different output channels in
units of rows or half rows. You can select option A, option B, and option C as the output distribution format (only when
RGB+VC1+VC2 mode is selected).
(5) Dot clock
Select the dot clock to be used to display characters. When an external clock input is selected, refer to EXTERNAL
CLOCK INPUT in 6. ELECTRICAL CHARACTERISTICS.
8
Data Sheet S13320EJ2V0DS
µPD6461, 6462
1.2 HOW TO SELECT MASK OPTIONS
To select mask options, use the option setting command (OC) of the Character Pattern Editor, a tool designed for editing
character pattern data.
Activate the Character Pattern Editor, then display the following setting menu:
OC (COMMAND INPUT)
OPTION DATA (0---LSB FAST , 1---MSB FAST
OPTION DATA (0---V:9H , 1---V:3H
) :
) :
......... (1)
......... (2)
......... (3)
......... (4)
......... (5)
......... (6)
......... (7)
OPTION DATA (0---RGB+3BLK , 1---RGB+VC1+VC2 ) :
OPTION DATA (0---OUTPUT 20, 1---OUTPUT 21 ) :
OPTION DATA (0---OUTPUT 10, 1---OUTPUT 11 ) :
OPTION DATA (0---EXT CLK , 1---LC
OPTION DATA (0---LC , 1---EXT CLK
) :
) :
Actually, the above menu is displayed one line at a time. Once you have selected an option, the next line is displayed.
Select 0 or 1 for lines (1), (2), (3), (6), and (7), according to the setting to be made. For the dot clock, however, make
the same settings (different values) for lines (6) and (7). For example, when selecting LC oscillation, select “LC” for both
lines (1 for (6) and 0 for (7)). Don’t select external clock input for lines (6) and/or (7).
When selecting the output distribution format, select the values on lines (4) and (5) as follows:
(4)
(5)
Option A
Option B
Option C
1(OUTPUT 21)
0(OUTPUT 20)
1(OUTPUT 21)
0(OUTPUT 10)
0(OUTPUT 10)
1(OUTPUT 11)
The settings are valid only when RGB+VC1+VC2 mode has been selected. Select option A (1, 0) when RGB+3BLK mode
has been selected.
The following table lists the correspondence between the command bits and the lines of the setting menu. Specify 0
or 1 for each bit.
D7
0
D6
(1)
D5
(2)
D4
(3)
D3
(4)
D2
(5)
D1
(6)
D0
(7)
Command OD displays the result of the selection, as a hexadecimal number.
Example: When the mask options are selected as follows:
Mask option
Bit
D6
D5
D4
D3
D2
D1
D0
Command
MSB first
1
1
0
1
0
1
0
Specification in three-line units
RGB+3BLK
Option A (only option A can be
specified in RGB+3BLK mode)
LC oscillation
The command bits are set as follows:
D7
0
D6
1
D5
1
D4
0
D3
1
D2
0
D1
1
D0
0
→Command OD displays 6AH.
Data Sheet S13320EJ2V0DS
9
µPD6461, 6462
1.3 APPLICATION BLOCK DIAGRAMS
Example of application to a camcorder (1) (in RGB+VC1+VC2 mode)
(The VR, VG, VB, VBLK, VC1, BLK1, VC2, and BLK2 pins are used.)
Hsync
Vsync
DATA
CLK
CS
PCL
Character addition
circuit
Color viewfinder
RGB channel
Image
µ
PD6461, 6462
VC2 channel Character addition circuit
Image + characters
Recording system
(deck)
Character addition
circuit
Monitor terminal
(video signal output)
V
C1 channel
RGB channel: V
R
, VG
, VB
, VBLK
VC1 channel: VC1, BLK1 VC2 channel: VC2, BLK2
Example of application to a camcorder (2) (in RGB+3BLK mode for RGB compatible blanking)
(The VR, VG, VB, RBLK, GBLK, and BBLK pins are used.)
Hsync
Vsync
DATA
CLK
CS
PCL
Character addition
circuit
Color viewfinder
R channel
Image
µ
PD6461, 6462
G channel
B channel
Character addition circuit
Image + characters
Recording system
(deck)
Character addition
circuit
Monitor terminal
(video signal output)
R channel: V
R, RBLK
G channel: V
G, GBLK
B channel: V , BBLK
B
10
Data Sheet S13320EJ2V0DS
µPD6461, 6462
1.4 DISPLAY IN RGB+VC1+VC2 MODE
The µPD6461, 6462 provide three options, A, B, and C, for the output distribution format. This section describes how
character signals are output when each option is selected. Output is controlled with the output pin control command (refer
to 3.8 OUTPUT PIN CONTROL COMMAND for details).
Output pin control command for MSB-first transfer (Command bits are input starting from the most significant bit (MSB),
D15.)
(This command is a 2-byte command. 16 bits must be input for each command, even for continuous input.)
(MSB)
D15
1
(LSB)
D0
D14
0
D13
0
D12
1
D11
1
D10
1
D9
0
D8
0
D7
D6
D5
0
D4
0
D3
D2
D1
VC2
VC1
AR3
AR2
AR1
AR0
Row specification bits
AR0
AR3 AR2
AR1
0
Function
0
0
0
0
0
1
Specifies row 0.
Specifies row 1.
0
1
0
1
1
Specifies row 11.
Other values are invalid.
Option A
Option B
Option C
Output pin control bits
Output from each pin
V
C2
V
C1
0
0
0
1
V
C1: Outputs a specified row. VC2: Fixed to low level.
C1: Fixed to low level. VC2: Outputs a specified row.
V
Output pin control bits
Output from each pin
VC2
V
C1
0
0
0
1
V
C1: Outputs all rows. VC2: Fixed to low level.
C1: Outputs all rows. VC2: Outputs a specified row.
V
Output pin control bits
Output from each pin
VC2
V
C1
0
0
1
1
0
1
0
1
VC1: Outputs columns 0 to 23. VC2: Fixed to low level.
V
V
C1: Outputs columns 0 to 11. VC2: Outputs columns 12 to 23.
C1: Outputs columns 12 to 23. VC2: Outputs columns 0 to 11.
VC1: Fixed to low level. VC2: Outputs columns 0 to 23.
•
•
Row specification
You can specify whether the VC1 or VC2 pin is used to output the character signals for each row (or each 12 columns).
Output pin control
The signals output from the VC1 and VC2 pins depend on whether option A, B, or C is selected (the corresponding
blanking signals are output in the same way).
Data Sheet S13320EJ2V0DS
11
µPD6461, 6462
Option A output
Output pin control bits
Output from each pin
VC2
0
VC1
0
VC1: Outputs the specified row. VC2: Fixed to low level.
VC1: Fixed to low level. VC2: Outputs specified row.
(1)
(2)
0
1
Output
channel
Character signal
Background signal (if specified)
For case
(1) above
VC1 channel
Outputs the logical OR of the character signals at Outputs a background signal for areas other than
the VR, VG, and VB pins (for the specified rows),
excluding those characters for which the VC2 chan-
nel has been specified.
those for which the VC2 channel has been specified.
VC2 channel
VC1 channel
VC2 channel
Fixed to low level (for the specified rows)
Outputs a background signal for those the areas for
which the VC2 channel has been specified.
Fixed to low level (for the specified rows)
Outputs a background signal for areas other than those
for which the VC2 channel has been specified.
For case
(2) above
Outputs those characters for which the VC2 chan-
nel has been specified (for the specified rows).
Outputs a background signal for those the areas for
which the VC2 channel has been specified.
Option B output
Output pin control bits
VC2
0
VC1
0
Output from each pin
VC1: Outputs all rows. VC2: Fixed to low level.
VC1: Outputs all rows. VC2: Outputs a specified row.
(1)
(2)
0
1
Output
channel
Character signal
Background signal (if specified)
For case
(1) above
VC1 channel
Outputs the logical OR of the character signals at Outputs a background signal for areas other than
the VR, VG, and VB pins (for all rows), excluding
those characters for which the VC2 channel has
been specified.
those for which the VC2 channel has been specified.
VC2 channel
VC1 channel
Fixed to low level (for the specified rows)
Outputs a background signal for those areas for
which the VC2 channel has been specified.
Outputs the logical OR of the character signals at Outputs a background signal for areas other than
For case
(2) above
the VR, VG, and VB pins (for all rows), excluding
those characters for which the VC2 channel has
been specified.
those for which the VC2 channel has been specified.
VC2 channel
Outputs the characters for which the VC2 channel
is specified (for the specified rows).
Outputs a background signal for those areas for
which the VC2 channel has been specified.
12
Data Sheet S13320EJ2V0DS
µPD6461, 6462
Option C output
Output pin control bits
Output from each pin
VC2
0
VC1
0
VC1: Outputs columns 0 to 23. VC2: Fixed to low level.
VC1: Outputs columns 0 to 11. VC2: Outputs columns 12 to 23.
VC1: Outputs columns 12 to 23. VC2: Outputs columns 0 to 11.
VC1: Fixed to low level. VC2: Outputs columns 0 to 23.
(1)
(2)
(3)
(4)
0
1
1
0
1
1
Output
channel
Character signal
Background signal (if specified)
For case
(1) above
VC1 channel
Outputs the logical OR of the character signals at Outputs a background signal for areas other than
the VR, VG, and VB pins (for columns 0 to 23 in the
specified rows), excluding those characters for
which the VC2 channel has specified.
those for which the VC2 channel has been specified.
VC2 channel
VC1 channel
Fixed to low level (for the specified rows)
Outputs a background signal for those areas for
which the VC2 channel has been specified.
Outputs the logical OR of the character signals at Outputs a background signal for areas other than
For case
(2) above
the VR, VG, and VB pins (for columns 0 to 11 of the
specified rows), excluding those characters for
which the VC2 channel has been specified.
those for which the VC2 channel has been specified.
VC2 channel
VC1 channel
Outputs the characters for which the VC2 channel
has been specified (for columns 12 to 23 of the
specified rows).
Outputs a background signal for those areas for
which the VC2 channel has been specified.
Outputs the logical OR of the character signals at Outputs a background signal for areas other than
For case
(3) above
the V
R
, V
G
, and V
B
pins (for columns 12 to 23 of the
those for which the VC2 channel has been specified.
specifiedrows),excludingthosecharactersforwhich
the VC2 channel has been specified.
VC2 channel
Outputs the characters for which the VC2 channel
has been specified (for columns 0 to 11 of the
specified rows).
Outputs a background signal for those areas for
which the VC2 channel has been specified.
VC1 channel
VC2 channel
Fixed to low level (for the specified rows)
Outputs a background signal for areas other than
those for which the VC2 channel has been specified.
For case
(4) above
Outputs the characters for which the VC2 channel
has been specified (for columns 0 to 23 in the
specified rows).
Outputs a background signal for those areas for
which the VC2 channel has been specified.
The RGB and VC1 channels do not output character signals for characters for which the VC2 channel has been specified.
Background signals are output separately as listed above.
In addition, the µPD6461, 6462, when set to RGB+VC1+VC2 mode, provide the following output control:
•
•
Independent on/off control of character display for each channel (3-channel independent display on/off command)
Independent control of the background for each channel (3-channel independent background control command)
Data Sheet S13320EJ2V0DS
13
µPD6461, 6462
1.4.1 Character Signal Output When Option A is Selected
Option A
The VC1 bit of the output pin control command can be used to specify whether the characters of each row are output to
the VC1 channel. Each character can be specified to be output to the VC2 channel, and the VC1 channel outputs only
characters for which the VC2 channel in the rows for which the VC1 bit is set to 1. Characters for which the VC2 channel
is specified are not output to the RGB or VC1 channel.
Display example (when the VC2 channel is used for information to be recorded)
Display in viewfinder
(RGB output and VC2 output)
Information that is only to be displayed,
such as alarms and tape count
REC
TAPE
BATT
1/1000
YOKOHAMA
BAY BRIDGE
0000
Information that is also to be recorded onto
the video tape, such as the date and title
AM 11:30
1991. 2.22
Output example with mask code option A specified
Characters output via RGB channel
(colored characters)
Characters output via VC1 channel
Characters output via VC2 channel
(specified characters of specified rows)
(specified rows)
REC
TAPE
BATT
REC
TAPE
BATT
1/1000
1/1000
YOKOHAMA
BAY BRIDGE
0000
0000
AM 11:30
1991. 2.22
• The RGB channel does not output
the characters for which the VC2
channel has been specified.
• The VC1 channel outputs the
characters in the rows for which the
• Rows for which the VC1 bit is set to 0
are not output (the VC2 pin is fixed to
low level).
V
C1 bit is set to 0, excluding the
characters for which the VC2 channel
is specified.
• Rows for which the VC1 bit is set to 1
are not output (the VC1 pin is fixed to
low level).
• The VC2 channel outputs only those
characters for which the VC2 channel
has been specified in the rows for
which the VC1 bit is set to 1.
14
Data Sheet S13320EJ2V0DS
µPD6461, 6462
1.4.2 Character Signal Output When Option B is Selected
Option B
The VC1 channel outputs characters of all rows regardless of setting of the VC1 and VC2 bits. Each character can be
specified to be output to the VC2 channel, and the VC2 channel outputs only characters for which the VC2 channel in the rows
for which the VC1 bit is set to 1. Characters for which the VC2 channel is specified are not output to the RGB or VC1 channel.
Display example (when the VC2 channel is used for information to be recorded)
Display in viewfinder
(RGB output and VC2 output)
Information that is only to be displayed, such
as alarms and tape count
REC
TAPE
BATT
← Information that is also to be recorded onto the
video tape is displayed on the left (weather in
this example).
RAIN
1/1000
YOKOHAMA
BAY BRIDGE
0000
Information that is also to be recorded onto the
video tape, such as the date and title
AM 11:30
1991. 2.22
Output example with mask code option B specified
Characters output via RGB channel
(colored characters)
Characters output via VC1 channel
Characters output via VC2 channel
(specified characters of specified rows)
(all rows)
REC
TAPE
BATT
REC
TAPE
BATT
1/1000
1/1000
RAIN
YOKOHAMA
BAY BRIDGE
0000
0000
AM 11:30
1991. 2.22
• The RGB channel does not output
the characters for which the VC2
channel has been specified.
• The VC1 channel outputs the
• The VC2 channel outputs only those
characters for which the VC2 channel
has been specified in those rows for
which the VC1 bit has been set to 1.
• The VC2 channel outputs no
characters of all rows regardless of
the setting of the VC1 bit, excluding
the characters for which the VC2
channel is specified.
characters in those rows for which
the VC1 bit has been set to 0.
Data Sheet S13320EJ2V0DS
15
µPD6461, 6462
1.4.3 Character Signal Output When Option C is Selected
Option C
The VC1 and VC2 bits of the output pin control command can be used to specify whether the characters in columns 0 to
11 of each row and those in columns 12 to 23 are output to the VC1 channel or to the VC2 channel.
Display example
Display in viewfinder
0
11 12
23
TAPE
Information that is only to be displayed,
such as alarms and tape count
BATT
1/1000
YOKOHAMA
BAY BRIDGE
Information that is also to be recorded
onto the video tape, such as date and title
0000
REC
AM 11:30
1991. 2.22
Output example with mask code option C specified
Characters output via RGB channel
(colored characters)
Characters output via VC1 channel
Characters output via VC2 channel
(specified characters)
(specified rows)
TAPE
BATT
TAPE
BATT
1/1000
1/1000
YOKOHAMA
BAY BRIDGE
0000
REC
0000
REC
AM 11:30
1991. 2.22
• The RGB channel does not output
the characters for which the VC2
channel has been specified.
• In the case of setting VC2 bit to 0, the
C1 channel outputs the characters
of columns 0 to 23 in specified rows
for which the VC1 bit is set to 0, or the
characters of columns 0 to 11 in
specified rows for which the VC1 bit is
set to 1, excluding the characters for
which the VC2 channel specified.
• In the case of setting VC1 bit to 0, the
C2 channel outputs the characters
V
V
of columns 0 to 11 in specified rows
for which the VC2 bit is set to 1, and
the rows for which the VC2 bit is set
to 0 are not output (the VC2 pin is
fixed to low level).
• In the case of setting VC1 bit to 1, the
• In the case of setting VC2 bit to 1, the
VC2 channel outputs the characters
V
C1 channel outputs the characters
of columns 12 to 23 in specified rows
for which the VC2 bit is set to 0, or the
characters of columns 0 to 23 in
specified rows for which the VC2 bit is
set to 1.
of columns 12 to 23 in specified rows
for which the VC1 bit is set to 0, and
the rows for which the VC1 bit is set
to 1 are not output (the VC1 pin is
fixed to low level), excluding the
characters for which the VC2 channel
specified.
16
Data Sheet S13320EJ2V0DS
µPD6461, 6462
1.4.4 Display of VC2-Specified Characters
When the displayed character control command specifies the VC2 channel for a character, that character is not output
to the RGB or VC1 channel (display for the RGB and VC1 channels is usually the same as when display-off data is writtenNote).
If background display (overall/minimum) is specified for the RGB or VC1 channel, no background is displayed for those
characters for which the VC2 channel has been specified.
Note In some cases, the display will differ slightly from the display-off data.
Solid data: Character for which all 12 × 18 dots are filled
Solid
data
Display-
off data
Solid
data
•
When display-off data is displayed for the RGB, VC1, or VC2 channel
If a character adjacent to the display-off data is rimmed or has a
background, the rim or background encroaches into the area for the display-
off data by one dot (minimum size). (The rim encroaches only at the filled
dots at the left or right edge of the rimmed character.)
V
fied
character
area
C2-speci-
Solid
data
Solid
data
•
•
Display of VC2-specified character area for the RGB or VC1 channel
If a character adjacent to a VC2-specified character is rimmed, the rim
encroaches into the area for the VC2-specified character by one dot (mini-
mum size). If the adjacent character has a background, however, the
background does not encroach into the VC2-specified character area.
Display of VC2-specified character area for the VC2 channel
If a rimmed VC2-specified character is adjacent to another VC2-specified
character, the rim encroaches into the area for the latter VC2-specified
character. The background does not encroach into the adjacent area (The
rim encroaches only at the filled dots on the left or right edge of the rimmed
character).
•
When a VC2-specified character area exists at the right or left edge of the
entire display area
(The figure shows an area at the left edge. The case of an area at the
right edge is similar).
VC2-speci-
fied
charac-
Solid
data
(1)
ter area
Encroachment of rim or background
Display-
(with a width of one dot for the minimum character size)
Solid
data
Solid
data
(2)
(3)
off
(4)
data
Display-
Encroachment of rim
Encroachment of background
Solid
data
off
(5)
(1) – (5)
(2) – (5)
data
Background does not encroach into the VC2-specified character area.
Data Sheet S13320EJ2V0DS
17
µPD6461, 6462
1.5 OUTPUTTING BACKGROUND
The figures below show the screen display when minimum background or overall background is specified for each output
channel in RGB+VC1+VC2 mode.
(1) Minimum background
RGB channel
VC1 output (character signal)
V
C2 output (character signal)
VBLK1 output (background signal)
VBLK2 output (background signal)
A
B
C
D
F
A
B
C
D
F
E
0 1 2 3 4 5
YOKOHAMA
YOKOHAMA
1991. 9. 2
AM 10:00
1991. 9. 2
AM 10:00
0000
No background for
C2-specified areas
No background for
C2-specified areas
Background only for
VC2-specified areas
V
V
(2) Overall background
RGB channel
VC1 output (character signal)
V
C2 output (character signal)
VBLK1 output (background signal)
VBLK2 output (background signal)
A
B
C
D
F
A
B
C
D
F
E
0 1 2 3 4 5
YOKOHAMA
YOKOHAMA
1991. 9. 2
AM 10:00
1991. 9. 2
AM 10:00
0000
No background for
C2-specified areas
No background for
C2-specified areas
Background only for
VC2-specified areas
V
V
Remarks 1. The above figures are only examples. Actually, the background can be controlled independently for each
output channel (only in RGB+VC1+VC2 mode), for example, by applying background (overall/minimum) for
the RGB channel but not for the other channels.
2. No background is applied to the VC2-specified areas for the RGB or VC1 channel. If a character adjacent
to a VC2-specified character is rimmed, the rim encroaches into the area for the VC2-specified character
by one dot (minimum size) only at the filled dots at the left or right edge of the area of the rimmed character,
in the same way as for display-off data. The background, however, does not encroach into the adjacent
area.
18
Data Sheet S13320EJ2V0DS
µPD6461, 6462
2. COMMANDS
2.1 COMMAND FORMAT
Control commands are serially input in 8-bit units with a variable word length. There are three types of commands: 1-
byte commands consisting of eight bits including an instruction and data, 2-byte commands consisting of sixteen bits
including an instruction and data, and a 2-byte continuous command which can be input in an abbreviated format.
Commands are input with the MSB first or LSB first according to the specified mask option.
2.2 COMMANDS AND THEIR BITS
(1) For MSB first
1-byte commands
(MSB)
Function
Video RAM batch clear
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Character display control
Background/rim color control
3-channel independent display on/off
Character reverse on/off
0
0
0
1
D0
R
LC
G
BL1
B
BL0
BFC
DOC
BCRE
0
0
1
0
0
1
1
1
0
DOA
0
DOB
0
0
0
1
1
1
2-byte commands
(MSB)
Function
Character display position control
Write address control
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
1
1
1
0
0
0
0
1
0
0
0
V4 V3 V2 V1 V0 H4 H3 H2 H1 H0
0
0
0
1
0
AR3 AR2 AR1 AR0 AC4 AC3 AC2 AC1 AC0
Output pin control
0
0
VC2 VC1
0
0
0
0
AR3 AR2 AR1 AR0
AR3 AR2 AR1 AR0
Character size control
0
S
3-channel independent background control
BA1 BA0 BFA BB1 BB0 BFB BC1 BC0 BFC
T8 T7 T6 T5 T4 T3 T2 T1 T0
Note
Test mode
Note Not to be used
2-byte continuous command
(MSB)
Function
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Displayed character control
1
1
RV
R
G
B
BL VC2 C7 C6 C5 C4 C3 C2 C1 C0
Note
Note C7 bit is “don’t care” at the µPD6462. However, this data sheet explains the µPD6462 with “0” in the C7 bit.
Data Sheet S13320EJ2V0DS
19
µPD6461, 6462
(2) For LSB first
1-byte commands
(LSB)
Function
D0
0
D1
0
D2
0
D3
0
D4
0
D5
0
D6
0
D7
0
Video RAM batch clear
Character display control
BL0
BFC
DOC
BCRE
BL1
B
LC
G
DO
R
1
0
0
0
Background/rim color control
3-channel independent display on/off
Character reverse on/off
0
1
0
0
DOB
0
DOA
0
0
1
1
1
0
1
1
1
0
0
2-byte commands
(LSB)
Function
Character display position control
Write address control
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
V3 V4
0
0
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
H0 H1 H2 H3 H4 V0 V1 V2
AC0 AC1 AC2 AC3 AR4 AR0 AR1 AR2
AR3
0
0
0
0
1
0
Output pin control
AR0 AR1 AR2 AR3
AR0 AR1 AR2 AR3
0
0
0
0
VC1 VC2
Character size control
0
S
0
3-channel independent background control
BA1
T8
BFC BC0 BC1 BFB BB0 BB1 BFA BA0
T0 T1 T2 T3 T4 T5 T6 T7
Note
Test mode
Note Not to be used
2-byte continuous command
(LSB)
Function
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
Displayed character control
VC2 BL
B
G
R
RV
1
1
C0 C1 C2 C3 C4 C5 C6 C7
Note
Note C7 bit is “don’t care” at the µPD6462. However, this data sheet explains the µPD6462 with “0” in the C7 bit.
20
Data Sheet S13320EJ2V0DS
µPD6461, 6462
2.3 POWER-ON CLEAR FUNCTION
The internal state of the IC is unstable immediately after the power is turned on. It is therefore necessary to keep the
PCL pin low for the time shown below to allow the system to initialize. This power-on clear places the system in the following
state:
•
•
Test mode is not specified.
All character data in video RAM (12 rows × 24 columns) is cleared (to display-off data (FEH: µPD6461/7EH: µPD6462)) and
blinking is turned off.
•
•
•
•
The video RAM write address is (row 0, column 0).
The character size is single (minimum) for all rows.
The output distribution format is set to the default (the VC1 and VC2 bits are set to 0).
Display is turned off and LC oscillation is turned on.
The time required for power-on clear is calculated as follows. No commands must be input during this time.
Time required for power-on clear = tPCLLNote
+ {Time required for clearing video RAM}
= 10(µs) + {10(µs) + 12/fOSC(MHz) × 288}
fOSC(MHz) : LC oscillation frequency or external clock frequency
Note Refer to POWER-ON CLEAR SPECIFICATIONS in 6. ELECTRICAL CHARACTERISTICS.
A dot clock input (to the OSCIN pin) is necessary to clear video RAM. Input a dot clock when an external clock input is
selected.
Data Sheet S13320EJ2V0DS
21
µPD6461, 6462
3. COMMAND DETAILS
3.1 VIDEO RAM BATCH CLEAR COMMAND
This command clears the entire video RAM by means of a single operation (the bit configuration is the same as for MSB-
first and LSB-first transfer).
(MSB)
D7
(LSB)
D0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
0
0
The video RAM batch clear command places the system in the following state:
•
All character data in video RAM (12 rows × 24 columns) is cleared (to display-off data (FEH: µPD6461/7EH:
µPD6462)) and blinking is turned off.
•
•
•
•
The video RAM write address is (row 0, column 0).
The character size is single (minimum) for all rows.
The output distribution format is set to the default (the VC1 and VC2 bits are set to 0).
Display is turned off and LC oscillation is turned on.
The time required for clearing video RAM is calculated as follows. No command must be input while the video RAM is
being cleared.
Time required to clear video RAM = 10(µs) + 12/fOSC(MHz) × 288
fOSC(MHz) : LC oscillation frequency or external clock frequency
A dot clock input (to the OSCIN pin) is necessary to clear the video RAM. Input a dot clock when external clock input
is selected.
Remark Power-on clear using the PCL pin is hardware reset, initializing the IC, including clearing the video RAM and
releasing test mode. The video RAM batch clear command, in contrast, performs software reset by initializing
the IC without first releasing test mode.
22
Data Sheet S13320EJ2V0DS
µPD6461, 6462
3.2 CHARACTER DISPLAY CONTROL COMMAND
This command turns on/off character display, LC oscillation, and the blinking of characters.
(1) For MSB-first transfer (Command bits are input starting from the MSB (D7).)
(MSB)
D7
(LSB)
D0
D6
0
D5
0
D4
1
D3
D2
LC
D1
0
DO
BL1
BL0
Blinking control bits
BL0 Function
BL1
0
0
1
1
0
1
0
1
Turns off blinking.
Turns on 2 Hz blinking.
Turns on 1 Hz blinking.
Turns on 0.5 Hz blinking.
LC oscillation control bit
Function
LC
0
1
Turns off LC oscillator.
Turns on LC oscillator.
Character display on/off control bit
Function
DO
0
1
Turns off character display.
Turns on character display.
(2) For LSB-first transfer (Command bits are input starting from the LSB (D0). The function of each bit is the same as
that for MSB-first transfer.)
(LSB)
D0
(MSB)
D7
D1
D2
LC
D3
D4
1
D5
0
D6
0
BL0
BL1
DO
0
•
•
Blinking control bits
These bits are used to turn on or off the blinking of characters for which blinking has been enabled with the displayed
character control command. The blinking ratio is 1:1, one of three blinking frequencies being selectable for the entire
screen.
LC oscillation control bit
This bit is used to turn the oscillator on or off. You can stop the oscillator when no character is being displayed,
thus reducing the power consumption.
While the oscillator is stopped, it is not possible to write to video RAM. Turn on the oscillator before attempting
to write to video RAM.
Cautions 1. When using LC oscillation (LC oscillation control bit = 1): When character display is turned on, the
oscillation is synchronized with Hsync, stopping when Hsync goes low. When character display
is turned off, oscillation continues regardless of the state of Hsync.
2. When using an external clock (LC oscillation control bit = 1): While the oscillator is turned on, clock
pulses are supplied to the IC internal circuit. While the oscillator is turned off, no clock pulses are
supplied.
•
Character display on/off control bit
This bit is used to turn character display on or off. Character display is turned on or off upon the detection of a
falling edge of Hsync.
23
Data Sheet S13320EJ2V0DS
µPD6461, 6462
3.3 BACKGROUND/RIM COLOR CONTROL COMMAND
This command specifies the color of the background or rim when overall background, minimum background, or rimming
is specified.
(1) For MSB-first transfer (Command bits are input starting from the MSB (D7).)
(MSB)
(LSB)
D7
D6
0
D5
1
D4
0
D3
R
D2
G
D1
B
D0
0
BFC
Rim color specification bit
BFC
0
1
Color
Black
White
Background color specification bits
R
0
0
0
0
1
1
1
1
G
0
0
1
1
0
0
1
1
B
0
1
0
1
0
1
0
1
Color
Black
Blue
Green
Cyan
Red
Magenta
Yellow
White
(2) For LSB-first transfer (Command bits are input starting from the LSB (D0). The function of each bit is the same as
that for MSB-first transfer.)
(LSB)
D0
(MSB)
D7
D1
B
D2
G
D3
R
D4
0
D5
1
D6
0
BFC
0
•
•
Rim color specification bit
This bit is used to specify the color (white or black) of the rim added to all characters displayed on the screen (only
for the RGB channel). When rimming is specified for the VC1 or VC2 channel, the rim color is always black.
Background color specification bits
These bits are used to specify one of eight colors to be used for the background of the entire screen (only for the
RGB channel). When background (overall/minimum) is specified for the VC1 or VC2 channel, the background color
is always black.
24
Data Sheet S13320EJ2V0DS
µPD6461, 6462
3.4 3-CHANNEL INDEPENDENT DISPLAY ON/OFF COMMAND
This command turns character display on or off independently for each of the three channels.
(1) For MSB-first transfer (Command bits are input starting from the MSB (D7).)
(MSB)
D7
(LSB)
D0
D6
1
D5
1
D4
1
D3
0
D2
D1
0
DOA
DOB DOC
Control bits
Function
When RGB+VC1+VC2 mode is selected
0
Turns off display for RGB channel.
Turns on display for RGB channel.
Turns off display for VC1 channel.
Turns on display for VC1 channel.
Turns off display for VC2 channel.
Turns on display for VC2 channel.
DOA
1
0
DOB
1
0
DOC
1
Control bits
Function
Turns off character display (for all channels).
Turns on character display (for all channels).
Don't care
When RGB+3BLK mode is selected
0
DOA
1
DOB
DOC
–
–
Don't care
(2) For LSB-first transfer (Command bits are input starting from the LSB (D0). The function of each bit is the same as
that for MSB-first transfer.)
(LSB)
D0
(MSB)
D7
D1
D2
D3
0
D4
1
D5
1
D6
1
DOC DOB DOA
0
25
Data Sheet S13320EJ2V0DS
µPD6461, 6462
3.5 CHARACTER REVERSE ON/OFF COMMAND
This command specifies whether all characters displayed on the screen are reversed.
(1) For MSB-first transfer (Command bits are input starting from the MSB (D7).)
(MSB)
D7
(LSB)
D0
D6
0
D5
1
D4
1
D3
1
D2
0
D1
0
0
BCRE
Control bit
0
Function
Does not reverse characters.
Reverses characters.
BCRE
1
(2) For LSB-first transfer (Command bits are input starting from the LSB (D0). The function of each bit is the same as
that for MSB-first transfer.)
(LSB)
D0
(MSB)
D7
D1
0
D2
0
D3
1
D4
1
D5
1
D6
0
BCRE
0
Each character is reversed only when reversing of the character is enabled with the displayed character control
command.
•
Example of reversed character (uppercase letter “I”)
When not reversed
When reversed
Background color or image (where dots
are not filled in the character pattern)
Character color
when not reversed
Character color (where dots are filled
in the character pattern)
Black
Remark When the character is not reversed, one of eight colors can be selected for the background color for the RGB
channel. For the VC1 and VC2 channels, which can display only white or black, the background is always black
(characters are white).
When characters are rseversed for the VC1 or VC2 channel, the display is as follows:
• Example of reversed character for VC1 or VC2 channel (uppercase letter “I”)
When not reversed
When reversed
Background color (black) or image (where
dots are not filled in the character pattern)
Character color when
not reversed: White
Character color: White (where dots
are filled in the character pattern)
Black
26
Data Sheet S13320EJ2V0DS
µPD6461, 6462
•
Rimming of reversed character
For an ordinary character
When not reversed
When reversed
Image
Rim
Black
No rim
Character color
Character color when not reversed
For a solid character (character pattern 18H (µPD6461)/1FH (µPD6462): Refer to 5. CHARACTER PATTERNS)
When not reversed When reversed
Rim
Black
No rim
Character color
Display-off data does not change when reversed. When blank data is reversed, it becomes a solid character for which
the character color is initially set. The character color can be set only for the RGB channel. It is always white (black when
reversed) for the VC1 and VC2 channels.
27
Data Sheet S13320EJ2V0DS
µPD6461, 6462
3.6 CHARACTER DISPLAY POSITION CONTROL COMMAND
This command specifies the character display start position with one of 32 steps in 12-dot units for the horizontal direction,
and one of 32 steps in three-line units for the vertical direction (this command is a 2-byte command, requiring 16 bits for
each command even when continuously input).
(1) For MSB-first transfer (Command bits are input starting from the MSB (D15).)
(MSB)
D15
1
(LSB)
D0
D14
0
D13
0
D12
0
D11
0
D10
0
D9
V4
D8
V3
D7
V2
D6
V1
D5
V0
D4
H4
D3
H3
D2
H2
D1
H1
H0
Control bits for horizontal display start position
H4 H3 H2 H1 H0 Start position
(4 + 12 × 1)/fOSC (MHz) from rising
edge of Hsync (µs)
(4 + 12 × 2)/fOSC (MHz) from rising
0
0
0
0
0
0
0
0
0
1
edge of Hsync ( s)
µ
(4 + 12 × 32 )/fOSC (MHz) from rising
edge of Hsync (µs)
1
1
1
1
1
Remarks fOSC: LC oscillation frequency or external input clock
Control bits for vertical display start position
V4 V3 V2 V1 V0
Start position
3H × 0 + 1H (9H × 0 + 1H) from
rising edge of Vsync
0
0
0
0
0
0
0
0
0
1
3H × 1 + 1H (9H × 1 + 1H) from
rising edge of Vsync
3H × 31 + 1H (9H × 31 + 1H) from
rising edge of Vsync
1
1
1
1
1
Remarks 1. H: Line
2. ( ) shows when units of nine lines are selected by
specifying a mask option.
(2) For LSB-first transfer (Command bits are input starting from the LSB (D0). The function of each bit is the same as
that for MSB-first transfer.)
(LSB)
(MSB)
D15
V2
D0
V3
D1
V4
D2
0
D3
0
D4
0
D5
0
D6
0
D7
1
D8
H0
D9
H1
D10
H2
D11
H3
D12
H4
D13
V0
D14
V1
28
Data Sheet S13320EJ2V0DS
µPD6461, 6462
•
•
Control bits for the horizontal display start position
These bits are used to specify the horizontal display start position (timing) as one of 32 steps in units of 12 dots
(12/fOSC (MHz)). Settable positions are based on the rising edge of the horizontal synchronizing signal input to the
Hsync pin. The 32 positions are calculated by adding 12 dots, one to 32 times, to the position equivalent to 16 clock
pulses (16/fOSC (MHz)) from the rising edge (fOSC (MHz): LC oscillation frequency or external input clock frequency).
Control bits for the vertical display start position
These bits are used to specify the vertical display start position as one of 32 steps in units of three lines (or 32
steps in units of nine lines when specified with a mask option). The minimum settable position is three lines from a
rising edge of the vertical synchronizing signal input to the Vsync pin.
Horizontal synchronizing signal (Hsync)
A
B
Display area of 12 rows x 24 columns
Vertical synchronizing signal (Vsync)
4
3
2
1
0
A : 3H×(2 V4+2 V3+2 V2+2 V1+2 V0)+1H
9H when units of nine lines are selected by specifying a mask option
12
4
4
3
2
1
0
B : ×(2 H4+2 H3+2 H2+2 H1+2 H0+1) +
fOSC(MHz)
fOSC(MHz)
fOSC : LC oscillation frequency or external input clock frequency H : Line
29
Data Sheet S13320EJ2V0DS
µPD6461, 6462
3.7 WRITE ADDRESS CONTROL COMMAND
This command specifies the address at which a character is written in the display area (video RAM) of 12 rows × 24 columns
(this command is a 2-byte command, requiring 16 bits for each command, even when continuously input).
(1) For MSB-first transfer (Command bits are input starting from the MSB (D15).)
(MSB)
D15
1
(LSB)
D0
D14
0
D13
0
D12
0
D11
1
D10
0
D9
0
D8
D7
D6
D5
D4
D3
D2
D1
AR3
AR2
AR1
AR0
AC4
AC3
AC2
AC1
AC0
Column address specification bits
AC4 AC3 AC2 AC1 AC0
Column
Column 0
Column 1
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
Column 23
Any other value is invalid.
Column address specification bits
AR3 AR2 AR1 AR0 Row address specification bits
Row
0
0
0
0
0
0
0
1
Row 0
Row 1
Row 11
1
0
1
1
Any other value is invalid.
(2) For LSB-first transfer (Command bits are input starting from the LSB (D0). The function of each bit is the same as
that for MSB-first transfer.)
(LSB)
D0
(MSB)
D15
D1
0
D2
0
D3
1
D4
0
D5
0
D6
0
D7
1
D8
D9
D10
AC2
D11
AC3
D12
AR4
D13
AR0
D14
AR1
AR3
AC0
AC1
AR2
•
•
Column write address specification bits
The display area has 24 columns. These bits are used to specify the column in which a character is to be written.
Row write address specification bits
The display area has 12 rows. These bits are used to specify the row in which a character is to be written.
30
Data Sheet S13320EJ2V0DS
µPD6461, 6462
3.8 OUTPUT PIN CONTROL COMMAND
This command distributes character signals to the VC1 and VC2 channels (this command is a 2-byte command, requiring
16 bits for each command, even when continuously input). The µPD6461, 6462 support a mask option for selecting one
of three formats for the output distribution format for the VC1 and VC2 channels.
(1) For MSB-first transfer (Command bits are input starting from the MSB (D15).)
(MSB)
D15
1
(LSB)
D0
D14
0
D13
0
D12
1
D11
1
D10
1
D9
0
D8
0
D7
D6
D5
0
D4
0
D3
D2
D1
VC2
VC1
AR3
AR2
AR1
AR0
Row specification bits
AR0
AR3 AR2
AR1
0
Function
0
0
0
0
0
1
Specifies row 0.
Specifies row 1.
0
1
0
1
1
Specifies row 11.
Other values are invalid.
Option A
Option B
Option C
Output pin control bits
Output from each pin
V
C2
V
C1
0
0
0
1
V
C1: Outputs a specified row. VC2: Fixed to low level.
C1: Fixed to low level. VC2: Outputs a specified row.
V
Output pin control bits
Output from each pin
VC2
V
C1
0
0
0
1
V
C1: Outputs all rows. VC2: Fixed to low level.
C1: Outputs all rows. VC2: Outputs a specified row.
V
Output pin control bits
Output from each pin
VC2
V
C1
0
0
1
1
0
1
0
1
VC1: Outputs columns 0 to 23. VC2: Fixed to low level.
V
V
C1: Outputs columns 0 to 11. VC2: Outputs columns 12 to 23.
C1: Outputs columns 12 to 23. VC2: Outputs columns 0 to 11.
VC1: Fixed to low level. VC2: Outputs columns 0 to 23.
(2) For LSB-first transfer (Command bits are input starting from the LSB (D0). The function of each bit is the same as
that for MSB-first transfer.)
(LSB)
D0
(MSB)
D15
D1
0
D2
1
D3
1
D4
1
D5
0
D6
0
D7
1
D8
D9
D10
AR2
D11
AR3
D12
0
D13
0
D14
0
AR0
AR1
VC1
VC2
•
•
Row specification bits
Output distribution to the VC1 and VC2 pins is specified for each row (or for 12 columns). These bits are used to
specify the row.
Output pin control bits
These bits are used to distribute character output signals to the VC1 and VC2 pins depending on whether option
A, B, or C has been selected by specifying a mask option (the corresponding blanking signals are output likewise).
31
Data Sheet S13320EJ2V0DS
µPD6461, 6462
3.9 CHARACTER SIZE CONTROL COMMAND
This command specifies the character size (height and width at one time) for each row (this command is a 2-byte
command, requiring 16 bits for each command, even when continuously input).
(1) For MSB-first transfer (Command bits are input starting from the MSB (D15).)
(MSB)
D15
1
(LSB)
D0
D14
0
D13
0
D12
1
D11
1
D10
0
D9
0
D8
0
D7
0
D6
S
D5
0
D4
0
D3
D2
D1
AR3
AR2
AR1
AR0
Row specification bits
AR3 AR2 AR1 AR0
Row
0
0
0
0
0
0
0
1
Row 0
Row 1
1
0
1
1
Row 11
Any other value is invalid.
Character size specification bit
Size
Height: One dot per line. Width: One dot per 1t (minimum dot).
Height: One dot per two lines. Width: One dot per 2t.
1
1t (µµs) =
S
0
1
f
OSC(MHz)
(fOSC : LC oscillation frequency
(2) For LSB-first transfer (Command bits are input starting from the LSB (D0). The function of each bit is the same as
that for MSB-first transfer.)
(LSB)
D0
(MSB)
D15
0
D1
0
D2
0
D3
1
D4
1
D5
0
D6
0
D7
1
D8
D9
D10
AR2
D11
AR3
D12
0
D13
0
D14
S
0
AR0
AR1
•
•
Row specification bits
The character size is specified for each row. These bits are used to specify the row.
Character size specification bit
This bit is used to select either of two supported sizes.
32
Data Sheet S13320EJ2V0DS
µPD6461, 6462
3.10 3-CHANNEL INDEPENDENT BACKGROUND CONTROL COMMAND
This command specifies the background for each of the three output channels (this command is a 2-byte command,
requiring 16 bits for each command, even when continuously input).
(1) For MSB-first transfer (Command bits are input starting from the MSB (D15).)
(MSB)
D15
(LSB)
D0
D14
0
D13
1
D12
1
D11
0
D10
0
D9
1
D8
D7
D6
D5
D4
D3
D2
D1
1
BA1
BA0
BFA
BB1
BB0
BFB
BC1
BC0
BFC
Background control bits for VC2 channel
V
C2 output
BC1
BC0
Background
No background
0
0
1
1
0
1
0
1
Minimum background
Not to be set
Overall background
Rimming control bit for VC2 channel
BFC
Function
0
1
Does not rim characters.
Rims characters.
Background control bits for VC1 channel
V
C1 output
BB1
0
BB0
0
Background
No background
0
1
Minimum background
Not to be set
1
0
1
1
Overall background
Rimming control bit for VC1 channel
BFB
0
Function
Does not rim characters.
Rims characters.
1
Background control bits for RGB channel
RGB output
BA1
0
BA0
0
Background
No background
0
1
Minimum background
Not to be set
1
0
1
1
Overall background
Rimming control bit for RGB channel
BFA
0
Function
Does not rim characters.
Rims characters.
1
(2) For LSB-first transfer (Command bits are input starting from the LSB (D0). The function of each bit is the same as
that for MSB-first transfer.)
(LSB)
D0
(MSB)
D15
D1
1
D2
0
D3
0
D4
1
D5
1
D6
0
D7
1
D8
D9
D10
BC1
D11
BFB
D12
BB0
D13
BB1
D14
BFA
BA1
BFC
BC0
BA0
33
Data Sheet S13320EJ2V0DS
µPD6461, 6462
•
Rimming control bit
This bit is used to specify whether all characters displayed on the screen are rimmed.
Rimming: Whenever there is a dot at the right or left edge of the display area for a character, rimming of the dot will
encroach into the adjacent character display area. For dots at the top or bottom edge, however, no rim is
added either above the top edge or below the bottom edge, that is, rimming does not encroach into the
character display area above or below. Other dots are rimmed as shown below.
Example
Character dots
Rim
The width of a rim is always 1t (minimum dot) regardless of the character size.
•
Background control bits
These bits are used to select no background, minimum background, or overall background as the background type.
The background color is specified with the background/rim color control command.
No background:
Outputs only character data.
Minimum background: Adds a background of an area that is wider than the character display area by a minimum
of one dot at each side.
Overall background: Adds a background over the entire screen.
•
Background and rimming in RGB+VC1+VC2 mode
Characters for which the VC2 channel is specified with the displayed character control command are not output to
the RGB or VC1 channel. When background (minimum/overall) is specified for the RGB or VC1 channel, no background
is added to the areas for the VC2-specified characters. By contrast for the VC2 channel, a background is added only
to those areas for VC2-specified characters. (Refer to 1.4 DISPLAY IN RGB+VC1+VC2 MODE and 1.4.4 Display of
VC2-Specified Characters for details of the display of VC2-specified character areas for the RGB or VC1 channel.)
When RGB+3BLK (RGB compatible blanking) mode is selected, only the background control bits for the RGB
channel are valid. Those for the VC1 and VC2 channels are invalid (In RGB+3BLK mode, no pin outputs a signal for
the VC2 channel. The VC1 pin is used to output the logical OR of the R, G, and B outputs.).
34
Data Sheet S13320EJ2V0DS
µPD6461, 6462
3.11 TEST MODE COMMAND
This command is used only to test the IC. Usually, do not input this command. The system cannot enter test mode while
the TEST pin (pin 9) is connected to ground.
(1) For MSB-first transfer (Command bits are input starting from the MSB (D15).)
(MSB)
D15
1
(LSB)
D0
D14
0
D13
1
D12
1
D11
0
D10
0
D9
0
D8
T8
D7
T7
D6
T6
D5
T5
D4
T4
D3
T3
D2
T2
D1
T1
T0
(2) For LSB-first transfer (Command bits are input starting from the LSB (D0). The function of each bit is the same as
that for MSB-first transfer.)
(LSB)
D0
(MSB)
D15
T7
D1
0
D2
0
D3
0
D4
1
D5
1
D6
0
D7
1
D8
T0
D9
T1
D10
T2
D11
T3
D12
T4
D13
T5
D14
T6
T8
3.12 DISPLAYED CHARACTER CONTROL COMMAND
This command specifies the attributes of each character, including the character pattern, color, and whether it is blinked.
When inputting this command, ensure that LC oscillator is turned on (if the LC oscillator is turned off, it is not possible to
write to video RAM).
This command is a 2-byte continuous command. When continuously writing characters with the same attributes (except
for a pattern), you need input only the eight low-order bits (D0 to D7) of the command for the second and subsequent
characters. In this case, the write column address is automatically incremented (After a character has been written into
column 23, the next character is automatically written into left-most column 0 of the next row. When a character is written
into column 23 of row 11, the next character is automatically written into column 0 of row 0.).
→
Column address (
)
→
→
→
→
→
→
→
→
→
22 23
0
1
2
• • • • • • • • • • • •
21
Row n
Row address
Row n+1
( )
Row address incremented
→
→
→
22 23
0
1
2
• • • • • • • • • • • •
21
35
Data Sheet S13320EJ2V0DS
µPD6461, 6462
(1) For MSB-first transfer (Command bits are input starting from the MSB (D15).)
(MSB)
(LSB)
D15
1
D14
1
D13
RV
D12
R
D11
G
D10
B
D9
BL
D8
D7
D6
C6
D5
C5
D4
C4
D3
C3
D2
C2
D1
C1
D0
C0
VC2
C7Note
Character pattern specification bits
C7Note
C6
0
C5
0
C4
0
C3
0
C2
0
C1
0
C0
0
Function
0
0
Outputs pattern at address 00H.
Outputs pattern at address 01H.
0
0
0
0
0
0
1
µ
µ
FEH ( PD6461)/7EH ( PD6462)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
(display-off data).
FFH (µPD6461)/7FH (µPD6462)
(Indicates the end of second-byte
continuous input.)
VC2 channel specification bit
VC2
Function
Does not specify output to
0
V
C2 channel.
1
Specifies output to VC2 channel.
Blinking control bit
Function
BL
0
Disables blinking.
Enables blinking.
1
Character color specification bits
R
0
0
0
0
1
1
1
1
G
0
0
1
1
0
0
1
1
B
0
1
0
1
0
1
0
1
Color
Black
Blue
Green
Cyan
Red
Magenta
Yellow
White
Reversing control bit
Function
RV
0
Disables reversing.
Enables reversing.
1
Note C7 bit is “don’t care” at the µPD6462. However, this data sheet explains the µPD6462 with “0” in the C7 bit.
36
Data Sheet S13320EJ2V0DS
µPD6461, 6462
(2) For LSB-first transfer (Command bits are input starting from the LSB (D0). The function of each bit is the same as
that for MSB-first transfer.)
(LSB)
D0
(MSB)
D15
C7
D1
BL
D2
B
D3
G
D4
R
D5
RV
D6
1
D7
1
D8
C0
D9
C1
D10
C2
D11
C3
D12
C4
D13
C5
D14
C6
VC2
•
Character pattern specification bits
These bits are used to specify the address of the character pattern to be used. Address FEH (µPD6461)/7EH
(µPD6462) indicates display-off data and address FFH (µPD6461)/7FH (µPD6462) indicates the end code for second-
byte continuous input. The design of each character pattern can be modified by specifying a mask code option (except
for addresses FEH and FFH (µPD6461)/7EH and 7FH (µPD6462)).
•
•
•
•
VC2 channel specification bit
This bit is used to specify whether each character is output to the VC2 channel. Characters for which the VC2 channel
is specified are not output to the RGB or VC1 channel (This bit is invalid in RGB+3BLK mode).
Blinking control bit
This bit is used to enable or disable blinking for each character. Blinking of characters is turned on/off for the entire
screen with the character display control command (refer to 3.2 CHARACTER DISPLAY CONTROL COMMAND).
Character color specification bits
These bits are used to specify the color of each character (These bits are valid only for the RGB channel. Only
a single color can be used for the VC1 and VC2 channels).
Reversing control bit
This bit is used to enable or disable reversing for each character. The characters of the entire screen are reversed
with the character reverse on/off command (refer to 3.5 CHARACTER REVERSE ON/OFF COMMAND).
37
Data Sheet S13320EJ2V0DS
µPD6461, 6462
4. COMMAND TRANSFER
4.1 1-BYTE COMMANDS
MSB first: Input starting from bit D7
LSB first: Input starting from bit D0
DATA
D7 - D0
D0 - D7
DATA
CLK
CS
4.2 2-BYTE COMMANDS
First byte
Second byte
D7 - D0
MSB first
First byte: D15 to D8
Second byte: D7 to D0
DATA
DATA
D15 - D8
First byte
D0 - D7
Second byte
D8 - D15
LSB first
First byte: D0 to D7
Second byte: D8 to D15
CLK
CS
When inputting a 2-byte command, keep the CS signal low between the first and second bytes of the command.
4.3 2-BYTE CONTINUOUS COMMAND
First byte
D15 - D8
Second byte
D7 - D0
Second byte
D7 - D0
DATA
DATA
MSB first
LSB first
First byte
D0 - D7
Second byte
D8 - D15
Second byte
D8 - D15
CLK
CS
The 2-byte continuous command is used to write characters to video RAM. When continuously writing characters for
which the specifications for the color, blinking, reversing, and VC2 channel are the same, transfer the first byte of the first
command then continuously transfer only the second bytes (character pattern addresses) of the commands.
When changing any part of the first byte, end continuous input (by setting the CS signal to high or transferring the end
code for second-byte continuous input) then transfer the newly modified first byte.
38
Data Sheet S13320EJ2V0DS
µPD6461, 6462
4.4 CONTINUOUS INPUT OF COMMAND
Transfer each of the 1-byte, 2-byte, and 2-byte successive commands from a microcontroller to the µPD6461, 6462
as follows.
To transfer a 1-byte or 2-byte command, or a 2-byte successive command with blinking data changed after a 2-
byte successive command has been transferred, either make CS high once, or transfer 2-byte successive command
end code (FFH: µPD6461/7FH: µPD6462) at the end of the 2-byte successive command. In the latter case, it is not
necessary to make CS high.
4.4.1 When End Code is Not Used
Example 1-byte command → 2-byte successive command → 1-byte command
1-byte command 2-byte successive
command
1-byte command
1st byte
2nd byte
D7-D0
2nd byte
D7-D0
DATA
D7-D0
D15-D8
(D0-D7)
D7-D0
MSB first (LSB first)
(D0-D7)
(D8-D15)
(D8-D15)
(D0-D7)
00H-FEH (
µ
PD6461)
00H-FEH ( PD6461)
µ
µ
00H-7EH ( PD6462)
00H-7EH (
µ
PD6462)
(normal character)
(normal character)
CLK
CS
Make CS low once and then back high again.
4.4.2 When End Code is Used
Example 1-byte command → 2-byte successive command → 1-byte command
1-byte command 2-byte successive
1-byte command
command
1st byte
2nd byte
D7-D0
2nd byte
D7-D0
D7-D0
D15-D8
(D0-D7)
D7-D0
DATA
MSB first (LSB first)
(D0-D7)
(D8-D15)
(D8-D15)
(D0-D7)
µ
00H-FEH ( PD6461)
FFH ( PD6461)/
µ
00H-7EH (
µ
PD6462)
7FH ( PD6462)
µ
(normal character)
(2-byte successive
command end code)
CLK
CS
It is not necessary to make CS low and then back high again.
Remark By using the 2-byte successive command end code, the CS pin may remain low. However, it is
recommended to make CS pin high to improve the noise immunity.
39
Data Sheet S13320EJ2V0DS
µPD6461, 6462
5. CHARACTER PATTERNS
The µPD6461, 6462 can display 256 (µPD6461)/128 (µPD6462) character patterns, including alphanumerics, Kanji
characters, and symbols, which are stored in the character generator ROM. Each pattern in the character generator ROM
can be modified by specifying a mask code option. However, the display-off data at character address FEH (µPD6461)/
7EH (µPD6462) and end code for second-byte continuous input at FFH (µPD6461)/7FH (µPD6462) cannot be modified.
No character pattern can be stored at these addresses.
When none of the 12 × 18 dots are filled for a character pattern at addresses 00H to FDH (µPD6461)/00H to 7DH
(µPD6462), the character pattern is called blank data. Character address FEH (µPD6461)/7EH (µPD6462) contains display-
off data. Blank data and display-off data are represented in the same way (with no dots filled) in character patterns shown
on the following pages, but they are different as follows:
Table 5-1 The Differences between Blank Data and Display-off Data
Display of character area in each background mode
Character data
No background
Displays image.
Displays image.
Minimum background
Overall background
Blank data
Displays background.
Displays background.
Display-off data
Displays image only
(without background).
Displays image only
(without background).
You cannot specify display-off data for addresses other than FEH (µPD6461)/7EH (µPD6462) when using a mask code
option. Blank data, however, can be specified at any address from 00H to FDH (µPD6461)/00H to 7DH (µPD6462) (address
FFH (µPD6461)/7FH (µPD6462) cannot be used because it contains the end code for second-byte continuous input).
The character patterns of the µPD6461GS-101/102, µPD6462GS-001 (NEC’s standard model) are shown on the
following pages.
40
Data Sheet S13320EJ2V0DS
µPD6461, 6462
µPD6461GS-101/102 Character Patterns
00H
08H
10H
18H
20H
28H
01H
09H
11H
19H
21H
29H
02H
0AH
12H
1AH
22H
2AH
03H
0BH
13H
1BH
23H
2BH
04H
0CH
14H
1CH
24H
2CH
05H
0DH
15H
1DH
25H
2DH
06H
07H
0FH
17H
1FH
27H
2FH
0EH
16H
1EH
26H
2EH
Data Sheet S13320EJ2V0DS
41
µPD6461, 6462
30H
38H
40H
48H
50H
58H
31H
39H
41H
49H
51H
59H
32H
3AH
42H
4AH
52H
5AH
33H
3BH
43H
4BH
53H
5BH
34H
3CH
44H
4CH
54H
5CH
35H
3DH
45H
4DH
55H
5DH
36H
37H
3FH
47H
4FH
57H
5FH
3EH
46H
4EH
56H
5EH
42
Data Sheet S13320EJ2V0DS
µPD6461, 6462
60H
68H
70H
78H
80H
88H
61H
69H
71H
79H
81H
89H
62H
6AH
72H
7AH
82H
8AH
63H
6BH
73H
7BH
83H
8BH
64H
6CH
74H
7CH
84H
8CH
65H
6DH
75H
7DH
85H
8DH
66H
67H
6FH
77H
7FH
87H
8FH
6EH
76H
7EH
86H
8EH
Data Sheet S13320EJ2V0DS
43
µPD6461, 6462
90H
98H
A0H
A8H
B0H
B8H
91H
99H
A1H
A9H
B1H
B9H
92H
9AH
A2H
AAH
B2H
BAH
93H
9BH
A3H
ABH
B3H
BBH
94H
9CH
A4H
ACH
B4H
BCH
95H
9DH
A5H
ADH
B5H
BDH
96H
97H
9FH
A7H
AFH
B7H
BFH
9EH
A6H
AEH
B6H
BEH
44
Data Sheet S13320EJ2V0DS
µPD6461, 6462
C0H
C8H
D0H
D8H
E0H
E8H
C1H
C9H
D1H
D9H
E1H
E9H
C2H
CAH
D2H
DAH
E2H
EAH
C3H
CBH
D3H
DBH
E3H
EBH
C4H
CCH
D4H
DCH
E4H
ECH
C5H
CDH
D5H
DDH
E5H
EDH
C6H
C7H
CFH
D7H
DFH
E7H
EFH
CEH
D6H
DEH
E6H
EEH
Data Sheet S13320EJ2V0DS
45
µPD6461, 6462
F0H
F1H
F2H
F3H
F4H
F5H
F6H
F7H
F8H
F9H
FAH
FBHNote 1
FCH
FDH
FEHNote 2
FFHNote 3
Notes 1. Blank data
2. Display-off data (fixed at this address)
3. End code for second-byte continuous input (fixed at this address)
46
Data Sheet S13320EJ2V0DS
µPD6461, 6462
µPD6462GS-001 Character Patterns
00H
01H
02H
03H
04H
05H
06H
07H
08H
10HNote 1
18H
09H
11H
19H
21H
29H
0AH
12H
1AH
22H
2AH
0BH
13H
1BH
23H
2BH
0CH
14H
1CH
24H
2CH
0DH
15H
1DH
25H
2DH
0EH
16H
1EH
26H
2EH
0FH
17H
1FH
27H
2FH
20H
28H
Data Sheet S13320EJ2V0DS
47
µPD6461, 6462
30H
38H
40H
48H
50H
58H
31H
39H
41H
49H
51H
59H
32H
3AH
42H
4AH
52H
5AH
33H
3BH
43H
4BH
53H
5BH
34H
3CH
44H
4CH
54H
5CH
35H
3DH
45H
4DH
55H
5DH
36H
37H
3FH
47H
4FH
57H
5FH
3EH
46H
4EH
56H
5EH
48
Data Sheet S13320EJ2V0DS
µPD6461, 6462
60H
68H
70H
78H
61H
69H
71H
79H
62H
6AH
72H
7AH
63H
6BH
73H
7BH
64H
6CH
74H
7CH
65H
6DH
75H
7DH
66H
67H
6EH
6FH
76H
77H
7EHNote 2
7FHNote 3
Notes 1. Blank data
2. Display-off data (fixed at this address)
3. End code for second-byte continuous input (fixed at this address)
Data Sheet S13320EJ2V0DS
49
µPD6461, 6462
6. ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Unit
V
Parameter
Supply voltage
Symbol µPD6461GS, 6462GS
µPD6461GT
VDD
VIN
VOUT
TA
7
V
Input pin voltage
–0.3 to VDD + 0.3
V
Output pin voltage
–0.3 to VDD + 0.3
–20 to +75
°C
°C
mW
mA
Operating ambient temperature
Storage temperature
Tstg
PD
–40 to +125
Permissible package power dissipation (TA = 75 °C)
Output current
180
320
IO
5
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure
that the absolute maximum rating are not exceeded.
RECOMMENDED OPERATING RANGES
Parameter
Symbol
VDD
Conditions
Min.
2.7
Typ.
Max.
5.5
Unit
V
Supply voltage
Oscillation frequency (LC oscillation)
Oscillation frequency (external clock)
Operating temperature
fOSC
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
6.0
8.0
MHz
MHz
˚C
fOSC
4.0
8.0
TA
–20
+75
ELECTRICAL CHARACTERISTICS (TA = –20 to +75°C)
Parameter
Symbol
VDD
Conditions
Min.
2.7
Typ.
5.0
Max.
5.5
Unit
V
Supply voltage
Supply current 1
Supply current 2
IDD
fOSC = 8.0 MHz, VDD = 5.0 V
fOSC = 8.0 MHz, VDD = 3.0 V
DATA, CLK, CS, PCL
5.0
10.0
6.0
mA
mA
V
IDD
3.0
Control input high level voltage
VCIH
VCIL
VISH
VISL
0.7VDD
Control input low level voltage
0.3VDD
V
Synchronizing signal input high level voltage
Synchronizing signal input low level voltage
Signal output high level voltage
Hsync, Vsync
0.48VDD
V
0.16VDD
V
VOSH
I
OSL = –1 mA (VDD = 5 V) / –0.5 mA 0.9VDD
V
(VDD = 3 V)
Signal output low level voltage
VOSL
VOST
IOSL = 1 mA (VDD = 5 V) / 0.5 mA
(VDD = 3 V)
0.1VDD
0.1VDD
V
V
Oscillation output low level voltage
CKOUT
IOST = –0.5 mA (VDD = 5 V)
Remark Signal input : DATA, CLK, CS, PCL, Hsync, Vsync
Signal output: CKOUT, VR, VG, VB, VC1, VC2, VBLK, BLK1, BLK2 (RBLK, GBLK, BBLK
)
(
)
: Set by a mask option
50
Data Sheet S13320EJ2V0DS
µPD6461, 6462
RECOMMENDED OPERATING TIMINGS (TA = –20 to +75°C, VDD = 2.7 to 5.5 V)
Parameter
Symbol
tSET
Conditions
Min.
200
200
400
400
1.0
Typ.
Max.
Unit
ns
ns
ns
ns
µs
ns
ns
ns
Setup time
Hold time
tHOLD
tCKL
Minimum low level width of clock
Minimum high level width of clock
Clock cycle
tCKH
tTCK
CS setup time
tCSS
400
400
400
CS hold time
tCSH
<1> In case of 1-byte or 2-byte
command
Delay time from CLK↑ → CS↑
tDCKCS
<2> In case of 2-byte continuous
commandNote
3
µs
4
8
µs
µs
Minimum low level width of Hsync
Minimum low level width of Vsync
tHWL
tVWL
Note When 2-byte continuous command end code is used, condition <1> can be applied.
DATA
10 %
t
SET
tHOLD
90 %
90 %
90 %
10 %
CLK
tCSS
t
CKL
tCKH
tDCKCS
tTCK
90 %
CS
10 %
10 %
t
CSH
Hsync
10 %
tHWL
Vsync
10 %
tVWL
Data Sheet S13320EJ2V0DS
51
µPD6461, 6462
POWER-ON CLEAR SPECIFICATIONS
Parameter
Symbol
tPCLL
Conditions
Min.
10
Typ.
Max.
Unit
PCL pin low level hold time
µs
VDD
0.8 VDD
VDD
0 V
t
PCLL
VDD
PCL
0.16 VDD
0 V
EXTERNAL CLOCK INPUT
Timing for external clock input (valid when selected with mask option)
50 %
Hsync
t
S
t
C-H
t
H-C
90 %
External
clock
50 %
10 %
Parameter
Symbol
tC-H
Conditions
Min.
30
Typ.
Max.
Unit
ns
Time from external clock fall to synchro-
nizing signal rise
Time from synchronizing signal rise to
external clock fall
tH-C
tS
30
ns
ns
tS (rising slew rate)
Note
Note 10% of the external clock cycle
Example: When the external clock frequency is 8 MHz
Clock cycle = 125 ns
The maximum slew rate is 10% of 125 ns, giving 12.5 ns.
Remarks 1. Keep the external clock in phase with the rising edges of Hsync.
2. Design the input of Hsync so that noise of more than 100 ns is suppressed.
3. When using an external clock, leave the OSCOUT pin open.
52
Data Sheet S13320EJ2V0DS
µPD6461, 6462
CHARACTER AND BLK SIGNAL OUTPUT
Character and BLK signals are output in synchronization with the falling edges of the dot clock.
50 %
Dot clock
CUS
CDS
CDL
DTW
90 %
Character signal
BLK signal
50 %
10 %
OUTPUT TIMINGS (TA = –20 to +75˚C, pins: VR, VG, VB, VBLK, VC1, BLK1, VC2, BLK2, (RBLK, GBLK, BBLK))
Pins in parentheses are selected by specifying a mask option.
Symbol
CDL
Parameter
Conditions
Min. Typ. Max. Unit
Output delay time of character/BLK signal
Output delay time of character/BLK signal
Rise time of character/BLK signal
Rise time of character/BLK signal
Fall time of character/BLK signal
Fall time of character/BLK signal
Time equivalent to minimum dot
VDD = 4.5 to 5.5 V, output load capacity = 10 pF
VDD = 2.7 to 3.3 V, output load capacity = 10 pF
VDD = 4.5 to 5.5 V, output load capacity = 10 pF
VDD = 2.7 to 3.3 V, output load capacity = 10 pF
VDD = 4.5 to 5.5 V, output load capacity = 10 pF
VDD = 2.7 to 3.3 V, output load capacity = 10 pF
VDD = 4.5 to 5.5 V, output load capacity = 10 pF
10
15
2
18
35
30
80
10
25
10
25
ns
ns
ns
ns
ns
ns
ns
CDL
CUS
CUS
CDS
CDS
DTW
4
2
4
(1 /Oscillation
Note
Note
frequency)
VDD = 2.7 to 3.3 V, output load capacity = 10 pF (1 /Oscillation
frequency)
5
DTW
Time equivalent to minimum dot
ns
5
Note Min.: (1/fOSC) – 5 ns, Max.: (1/fOSC) + 5 ns
fOSC: Frequency of LC oscillation or external input clock.
TIMING FOR CONTINUOUS COMMAND INPUT
When inputting commands continuously, the following timing requirements must be observed:
(TA = –20 to +75˚C, VDD = 2.7 to 5.5 V)
Unit
µs
Parameter
Symbol
T1
Conditions
For all commands
Min.
2.0
Typ. Max.
Continuous command input timing 1
Continuous command input timing 2
µs
Whendisplayis
turned on
T2
For VRAM write
commands
2 µs + (21/fOSC)
× S +tHWL
µs
Whendisplayis 2 µs + (12/fOSC)
turned off
× S
fOSC: Frequency of LC oscillation or external input clock (MHz), S: Character size (single (minimum) or double), tHWL: Hsync width.
Commands other than VRAM write commands may not comply with T2 provided the control clock cycle satisfies the specifications.
Hi-Z
Hi-Z
T1
Hi-Z
DATA
CLK
T2
Data Sheet S13320EJ2V0DS
53
µPD6461, 6462
7. APPLICATION CIRCUIT EXAMPLE
µ
PD6461GS/GT, PD6462GS
µ
1 (1)
20 (24)
19 (23)
18 (21)
Hsync
Vsync
VB
CLK
CS
Connected to microcontroller
Inputs a negative Hsync,
Vsync signal
2 (2)
3 (4)
Note 1
µ
10 F
VDD
DATA
PCL
VDD
+
100 kΩ
4 (5)
5 (6)
17 (20)
16 (19)
VG
VR
10
µ
F +
0.01 F
µ
6 (7)
15 (18)
14 (17)
VBLK
CKOUT
Note 4(BBLK)
LC module
pin No. 1
Note 2
Output
7
(8)Note 3
VC2
OSCOUT
Note 4(GBLK)
LC module
pin No. 3
33 F
µ
8(9) Note 3
9(10)
13 (16)
12 (15)
BLK2
OSCIN
TEST
GND
Note 4(RBLK)
5 to 30 pF
30 pF
VC1
11 (14)
10(11)
BLK1
Notes 1. CR constant must be satisfied with Power-ON Clear Specification (refer to 6. ELECTRICAL
CHARACTERISTICS).
2. This circuit can reduce the number of external components and facilitates the adjustment of oscillation
frequency, using LC module (part number: Q285NCIS-11181, manufactured by Toko, Inc.)
3. Connect these pins as follows when inputting external clock:
OSCIN pin: external clock input, OSCOUT pin: open
4. Signals in ( ) are set by a mask option (RGB + RGB compatible blanking).
Remarks 1. The number in the parentheses indicates the pin number of the µPD6461GT-xxx.
2. With the µPD6461GT-xxx, influence by noise via lead frame can be surpressed by connecting the
N.C. pins (3, 12, 13, 22) to GND.
54
Data Sheet S13320EJ2V0DS
µPD6461, 6462
8. PACKAGE DRAWINGS
20-PIN PLASTIC SSOP (7.62 mm (300))
20
11
detail of lead end
P
1
10
A
H
I
F
J
G
S
L
N
S
K
C
B
D
M
M
E
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
A
B
C
6.7 0.3
0.575 MAX.
0.65 (T.P.)
+0.08
0.32
D
−0.07
E
F
G
H
I
0.125 0.075
2.0 MAX.
1.7 0.1
8.1 0.3
6.1 0.2
J
1.0 0.2
+0.10
0.15
K
−0.05
L
M
N
0.5 0.2
0.12
0.10
+7°
3°
P
−3°
P20GM-65-300B-4
Data Sheet S13320EJ2V0DS
55
µPD6461, 6462
24-PIN PLASTIC SOP (9.53 mm (375))
24
13
P
1
12
A
F
H
I
G
J
L
C
S
K
M
D
M
B
E
N
S
NOTE
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
+0.41
15.3
A
−0.2
B
C
1.87 MAX.
1.27 (T.P.)
+0.08
0.42
D
−0.07
E
F
G
H
I
0.125 0.075
2.9 MAX.
2.50 0.2
10.3 0.2
7.2 0.2
J
1.6 0.2
+0.08
0.17
K
−0.07
L
M
N
0.8 0.2
0.12
0.10
+7°
3°
P
−3°
P24GT-50-375B-4
56
Data Sheet S13320EJ2V0DS
µPD6461, 6462
9. RECOMMENDED SOLDERING CONDITIONS
When soldering these products, it is highly recommended to observe the conditions as shown below. If other soldering
processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales
offices.
For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL”
(C10535E).
Surface Mount Devices
µPD6461GS-xxx: 20-pin plastic SSOP (7.62 mm (300))
µPD6461GT-xxx: 24-pin plastic SOP (9.53 mm (375))
µPD6462GS-xxx: 20-pin plastic SSOP (7.62 mm (300))
Process
Conditions
Symbol
Infrared ray reflow
Peak temperature: 235°C or below (Package surface temperature),
Reflow time: 30 seconds or less (at 210°C or higher),
Maximum number of reflow processes: 2 times.
IR35-00-2
Vapor phase soldering
Wave soldering
Peak temperature: 215°C or below (Package surface temperature),
Reflow time: 40 seconds or less (at 200°C or higher),
Maximum number of reflow processes: 2 times.
VP15-00-2
WS60-00-1
–
Solder temperature: 260°C or below, Flow time: 10 seconds or less,
Maximum number of flow processes: 1 time,
Pre-heating temperature: 120°C or below (Package surface temperature).
Partial heating method
Pin temperature: 300°C or below,
Heat time: 3 seconds or less (Per each side of the device).
Caution Apply only one kind of soldering condition to a device, except for “partial heating method”, or the
device will be damaged by heat stress.
Data Sheet S13320EJ2V0DS
57
µPD6461, 6462
[MEMO]
58
Data Sheet S13320EJ2V0DS
µPD6461, 6462
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S13320EJ2V0DS
59
µPD6461, 6462
•
The information in this document is current as of March, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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