UPD444016G5-8-7JF-A [RENESAS]
256X16 STANDARD SRAM, 8ns, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44;
| 型号： | UPD444016G5-8-7JF-A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 256X16 STANDARD SRAM, 8ns, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44 ISM频段 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总22页 (文件大小：312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DATA SHEET
MOS INTEGRATED CIRCUIT
μPD444016
4M-BIT CMOS FAST SRAM
256K-WORD BY 16-BIT
Description
The μPD444016 is a high speed, low power, 4,194,304 bits (262,144 words by 16 bits) CMOS static RAM.
Operating supply voltage is 5.0 V 0.5 V.
The μPD444016 is packaged in 44-pin plastic SOJ and 44-pin plastic TSOP (II).
Features
• 262,144 words by 16 bits organization
• Fast access time : 8, 10, 12 ns (MAX.)
• Byte data control : /LB (I/O1 - I/O8), /UB (I/O9 - I/O16)
• Output Enable input for easy application
• Single +5.0 V power supply
Ordering Information
Part number
Package
Access time
Supply current mA (MAX.)
ns (MAX.)
At operating
At standby
10
μPD444016LE-8
44-pin plastic SOJ
(10.16 mm (400))
8
220
200
190
220
200
190
220
200
190
220
200
190
μPD444016LE-10
10
12
8
μPD444016LE-12
μPD444016G5-8-7JF
μPD444016G5-10-7JF
μPD444016G5-12-7JF
μPD444016LE-8-A
44-pin plastic TSOP (II)
(10.16 mm (400))
(Normal bent)
10
12
8
44-pin plastic SOJ
(10.16 mm (400))
μPD444016LE-10-A
μPD444016LE-12-A
μPD444016G5-8-7JF-A
μPD444016G5-10-7JF-A
μPD444016G5-12-7JF-A
10
12
8
44-pin plastic TSOP (II)
(10.16 mm (400))
(Normal bent)
10
12
Remark Products with -A at the end of the part number are lead-free products.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M14430EJ6V0DS00 (6th edition)
Date Published September 2006 NS CP(K)
Printed in Japan
1999
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
μPD444016
Pin Configuration (Marking Side)
/××× indicates active low signal.
44-pin plastic SOJ (10.16 mm (400))
[ μPD444016LE ]
[ μPD444016LE-A ]
44-pin plastic TSOP (II) (10.16 mm (400)) (Normal bent)
[ μPD444016G5-××-7JF ]
[ μPD444016G5-××-7JF-A ]
A0
A1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
1
A16
2
A2
A15
3
A3
/OE
4
A4
/UB
5
/CS
I/O1
I/O2
I/O3
I/O4
/LB
6
I/O16
I/O15
I/O14
I/O13
GND
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
V
CC
GND
I/O5
I/O6
I/O7
I/O8
/WE
A5
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
A6
A7
A8
A9
A0 - A17
:
Address Inputs
Data Inputs / Outputs
Chip Select
/LB, /UB
VCC
:
:
:
:
Byte data select
Power supply
Ground
I/O1 - I/O16 :
/CS
/WE
/OE
:
:
:
GND
NC
Write Enable
No connection
Output Enable
Remark Refer to Package Drawings for the 1-pin index mark.
2
Data Sheet M14430EJ6V0DS
μPD444016
Block Diagram
A0
|
A17
Memory cell array
4,194,304 bits
I/O1 - I/O8
Input data
controller
Sense amplifier /
Switching circuit
Output data
controller
I/O9 - I/O16
Column decoder
/WE
/CS
/LB
Address buffer
/UB
/OE
VCC
GND
Truth Table
/CS
/OE
/WE
/LB
/UB
Mode
I/O
Supply current
I/O1 - I/O8
High impedance
DOUT
I/O9 - I/O16
High impedance
DOUT
×
×
×
L
×
L
H
L
Not selected
Read
ISB
ICC
L
H
L
H
L
DOUT
High impedance
DOUT
H
L
High impedance
DIN
×
L
L
L
Write
DIN
L
H
L
DIN
High impedance
DIN
H
×
High impedance
High impedance
High impedance
×
L
L
H
H
Output disable
High impedance
High impedance
×
×
H
H
Remark × : Don’t care
Data Sheet M14430EJ6V0DS
3
μPD444016
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
VCC
VT
Condition
Rating
Unit
V
Supply voltage
–0.5 Note to +7.0
Input / Output voltage
Operating ambient temperature
Storage temperature
–0.5 Note to VCC+0.5
0 to 70
V
TA
°C
°C
Tstg
–55 to +125
Note –2.0 V (MIN.) (pulse width : 2 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply voltage
Symbol
VCC
VIH
Condition
MIN.
4.5
TYP.
5.0
MAX.
5.5
Unit
V
V
High level input voltage
2.2
VCC+0.5
+0.8
Low level input voltage
VIL
–0.5 Note
0
V
°C
Operating ambient temperature
TA
70
Note –2.0 V (MIN.) (pulse width : 2 ns)
4
Data Sheet M14430EJ6V0DS
μPD444016
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Input leakage current
Output leakage current
Symbol
ILI
Test condition
MIN.
–2
TYP.
MAX.
+2
Unit
μA
VIN = 0 V to VCC
μA
ILO
VI/O = 0 V to VCC, /CS = VIH or /OE = VIH
or /WE = VIL or /LB = VIH or /UB = VIH
–2
+2
Operating supply current
Standby supply current
ICC
/CS = VIL,
Cycle time : 8 ns
Cycle time : 10 ns
220
200
190
40
mA
mA
II/O = 0 mA,
Minimum cycle time Cycle time : 12 ns
/CS = VIH, VIN = VIH or VIL
ISB
/CS ≥ VCC – 0.2 V,
ISB1
10
VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V
High level output voltage
Low level output voltage
VOH
VOL
IOH = –4.0 mA
IOL = +8.0 mA
2.4
V
V
0.4
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These DC characteristics are in common regardless of package types.
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter Symbol
Test condition
MIN.
TYP.
MAX.
Unit
pF
Input capacitance
CIN
CI/O
VIN = 0 V
VI/O = 0 V
6
8
Input / Output capacitance
pF
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These parameters are periodically sampled and not 100% tested.
Data Sheet M14430EJ6V0DS
5
μPD444016
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
Input Waveform (Rise and Fall Time ≤ 3 ns)
3.0 V
1.5 V
Test Points
1.5 V
GND
Output Waveform
1.5 V
Test Points
1.5 V
Output Load
AC characteristics directed with the note should be measured with the output load shown in Figure 1 or Figure
2.
Figure 1
Figure 2
(tAA, tACS, tOE, tABD, tOH)
(tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW)
VTT = +1.5 V
+5.0 V
50 Ω
480 Ω
Z = 50 Ω
O
I/O (Output)
I/O (Output)
255 Ω
30 pF
5 pF
CL
C
L
Remark CL includes capacitances of the probe and jig, and stray capacitances.
6
Data Sheet M14430EJ6V0DS
μPD444016
Read Cycle
μPD444016-8
μPD444016-10
μPD444016-12
Parameter
Symbol
Unit
Notes
MIN.
8
MAX.
MIN.
10
MAX.
MIN.
12
MAX.
Read cycle time
tRC
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
8
8
4
4
10
10
5
12
12
6
1
/CS access time
tACS
tOE
/OE access time
/LB, /UB access time
tABD
tOH
5
6
Output hold from address change
/CS to output in low impedance
/OE to output in low impedance
/LB, /UB to output in low impedance
/CS to output in high impedance
/OE to output hold in high impedance
/LB, /UB to output hold in high impedance
3
3
0
0
3
3
0
0
3
3
0
0
tCLZ
tOLZ
tBLZ
tCHZ
tOHZ
tBHZ
2, 3
4
4
4
5
5
5
6
6
6
Notes 1. See the output load shown in Figure 1.
2. Transition is measured at 200 mV from steady-state voltage with the output load shown in Figure 2.
3. These parameters are periodically sampled and not 100% tested.
Remark These AC characteristics are in common regardless of package types.
Read Cycle Timing Chart 1 (Address Access)
t
RC
Address (Input)
I/O (Output)
t
AA
t
OH
Previous data out
Data out
Remarks 1. In read cycle, /WE should be fixed to high level.
2. /CS = /OE = /LB (or /UB) = VIL
Data Sheet M14430EJ6V0DS
7
μPD444016
Read Cycle Timing Chart 2 (/CS Access)
tRC
Address (Input)
/CS (Input)
t
AA
tACS
t
CLZ
t
CHZ
/OE (Input)
/LB, /UB (Input)
I/O (Output)
t
t
OE
t
OHZ
BHZ
t
t
OLZ
BLZ
ABD
t
High impedance
High impedance
Data out
Caution Address valid prior to or coincident with /CS low level input.
Remark In read cycle, /WE should be fixed to high level.
8
Data Sheet M14430EJ6V0DS
μPD444016
Write Cycle
μPD444016-8
μPD444016-10
μPD444016-12
Parameter
Symbol
Unit
Notes
MIN.
MAX.
MIN.
10
7
MAX.
MIN.
12
8
MAX.
Write cycle time
tWC
tCW
tAW
tWP
tBW
tDW
tDH
8
6
6
6
6
4
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/CS to end of write
Address valid to end of write
Write pulse width
7
8
7
8
/LB, /UB to end of write
Data valid to end of write
Data hold time
7
8
5
6
0
0
Address setup time
tAS
0
0
Write recovery time
tWR
tWHZ
tOW
0
0
/WE to output in high impedance
Output active from end of write
4
5
6
1, 2
3
3
3
Notes 1. Transition is measured at 200 mV from steady-state voltage with the output load shown in Figure 2.
2. These parameters are periodically sampled and not 100% tested.
Remark These AC characteristics are in common regardless of package types.
Write Cycle Timing Chart 1 (/WE Controlled)
tWC
Address (Input)
/CS (Input)
tCW
tAW
tAS
tWP
tWR
/WE (Input)
tBW
/LB, /UB (Input)
tOW
t
WHZ
tDW
tDH
High
impe-
dance
High
impe-
dance
I/O (Input / Output)
Indefinite data out
Data in
Indefinite data out
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. Do not input data to the I/O pins while they are in the output state.
Remarks 1. Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB
(or low level /UB).
2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read
operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance.
Data Sheet M14430EJ6V0DS
9
μPD444016
Write Cycle Timing Chart 2 (/CS Controlled)
tWC
Address (Input)
tAS
tCW
/CS (Input)
/WE (Input)
t
AW
tWP
tWR
tBW
/LB, /UB (Input)
I/O (Input)
t
DW
tDH
High impedance
High impedance
Data in
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB
(or low level /UB).
10
Data Sheet M14430EJ6V0DS
μPD444016
Write Cycle Timing Chart 3 (/LB, /UB Controlled)
tWC
Address (Input)
tAW
tCW
tWR
/CS (Input)
/WE (Input)
tWP
tAS
tBW
/LB, /UB (Input)
I/O (Input)
t
DW
tDH
High impedance
High impedance
Data in
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB
(or low level /UB).
Data Sheet M14430EJ6V0DS
11
μPD444016
Package Drawings
44-PIN PLASTIC SOJ (10.16 mm (400))
B
44
23
C
D
1
22
G
J
E
F
S
U
T
P
M
M
N
Q
S
K
I
H
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
+0.20
B
28.73
−0.35
C
10.16
D
E
F
G
H
I
11.18 0.20
1.03 0.15
0.74
3.5 0.2
2.3 0.2
0.8 MIN.
2.6
J
K
M
N
P
Q
T
1.27 (T.P.)
0.40 0.10
0.12
9.4 0.20
0.10
R 0.85
+0.10
0.20
U
−0.05
P44LE-400A-1
12
Data Sheet M14430EJ6V0DS
μPD444016
44-PIN PLASTIC TSOP (II) (10.16 mm (400))
44
23
detail of lead end
F
P
E
1
22
A
H
G
I
J
S
C
N
S
L
M
D
M
K
B
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
A
B
C
18.63 MAX.
0.93 MAX.
0.8 (T.P.)
+0.08
0.32
D
−0.07
E
F
G
H
I
0.1 0.05
1.2 MAX.
0.97
11.76 0.2
10.16 0.1
0.8 0.2
J
+0.025
0.145
K
−0.015
L
M
N
0.5 0.1
0.13
0.10
+7°
3°
P
−3°
S44G5-80-7JF5-1
Data Sheet M14430EJ6V0DS
13
μPD444016
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the μPD444016.
Types of Surface Mount Device
μPD444016LE
μPD444016G5-7JF : 44-pin plastic TSOP (II) (10.16 mm (400)) (Normal bent)
μPD444016LE-A : 44-pin plastic SOJ (10.16 mm (400))
: 44-pin plastic SOJ (10.16 mm (400))
μPD444016G5-7JF-A : 44-pin plastic TSOP (II) (1016 mm (400)) (Normal bent)
<R>
Quality Grade
• A quality grade of the products is “Standard”.
• Anti-radioactive design is not implemented in the products.
• Semiconductor devices have the possibility of unexpected defects by affection of cosmic ray that reach to the
ground and so forth.
14
Data Sheet M14430EJ6V0DS
μPD444016
Revision History
Edition/
Date
Page
Type of
revision
Location
Description
(Previous edition → This edition)
This
Previous
edition
edition
6th edition/
Sep. 2006
p.14
p.14
Addition
Quality Grade
Section of Quality Grade has been added.
Data Sheet M14430EJ6V0DS
15
μPD444016
[ MEMO ]
16
Data Sheet M14430EJ6V0DS
μPD444016
[ MEMO ]
Data Sheet M14430EJ6V0DS
17
μPD444016
[ MEMO ]
18
Data Sheet M14430EJ6V0DS
μPD444016
NOTES FOR CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
1
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
Data Sheet M14430EJ6V0DS
19
μPD444016
•
The information in this document is current as of September, 2006. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
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•
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•
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M8E 02. 11-1
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