UPD17244UC-XXX-5A4 [RENESAS]
4-BIT, MROM, 4.5MHz, MICROCONTROLLER, PDSO30, 0.300 INCH, PLASTIC, SSOP-30;
| 型号： | UPD17244UC-XXX-5A4 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 4-BIT, MROM, 4.5MHz, MICROCONTROLLER, PDSO30, 0.300 INCH, PLASTIC, SSOP-30 光电二极管 |
| 文件： | 总104页 (文件大小：677K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD17240,17241,17242,17243,17244,17245,17246
4-BIT SINGLE-CHIP MICROCONTROLLERS
FOR SMALL GENERAL-PURPOSE INFRARED
REMOTE CONTROL TRANSMITTERS
DESCRIPTION
The µPD17240, 17241, 17242, 17243, 17244, 17245, 17246 (hereafter called the µPD17246 Subseries) are 4-
bit single-chip microcontrollers for small general-purpose infrared remote control transmitters.
This subseries employs 17K general-purpose register system architecture for the CPU, and can directly execute
operations between data memories instead of the conventional method of executing operations through an
accumulator. Moreover, all the instructions are 16-bit/1-word instructions, enabling efficient programming.
In addition, a one-time PROM model, the µPD17P246, to which data can be written only once, is also available.
This product is convenient either for evaluating the µPD17246 Subseries programs or for small-scale production of
application systems.
Detailed function descriptions are provided in the following user's manual. Be sure to read them before
designing.
µPD172×× Subseries User's Manual: U12795E
FEATURES
•
•
•
Infrared remote controller carrier generator (REM output)
17K architecture: General-purpose register system
Program memory (ROM), data memory (RAM)
µPD17240
4 KB
µPD17241
8 KB
µPD17242
µPD17243
µPD17244
µPD17245
µPD17246
Program
12 KB
16 KB
20 KB
24 KB
32 KB
memory (ROM) (2,048 × 16) (4,096 × 16) (6,144 × 16) (8,192 × 16) (10,240 × 16) (12,288 × 16) (16,384 × 16)
Data memory
(RAM)
447 × 4 bits
•
•
•
8-bit timer:
1 channel
Basic interval timer/watchdog timer: 1 channel
Instruction execution time (can be changed in two steps)
@ fX = 4 MHz:
External interrupt pin (INT/P1B0):
I/O pins:
4 µs (high-speed mode)/8 µs (normal mode)
1
•
•
•
•
•
24
Supply voltage:
VDD = 2.0 to 3.6 V
On-chip RAM retention detector
Low-voltage detector (mask option)
Unless otherwise specified, the µPD17246 is treated as the representative model throughout this document.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. U15002EJ1V1DS00 (1st edition)
Date Published August 2005 N CP (K)
Printed in Japan
2000
The mark shows major revised points.
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
APPLICATIONS
Preset remote controllers, toys, portable systems, etc.
ORDERING INFORMATION
Part Number
Package
µPD17240MC-×××-5A4
µPD17241MC-×××-5A4
µPD17242MC-×××-5A4
µPD17243MC-×××-5A4
µPD17244MC-×××-5A4
µPD17245MC-×××-5A4
µPD17246MC-×××-5A4
µPD17240MC-×××-5A4-A
µPD17241MC-×××-5A4-A
µPD17242MC-×××-5A4-A
µPD17243MC-×××-5A4-A
µPD17244MC-×××-5A4-A
µPD17245MC-×××-5A4-A
µPD17246MC-×××-5A4-A
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
Remarks 1. ××× indicates ROM code suffix.
2. Products that have the part numbers suffixed by “-A” are lead-free products.
Data Sheet U15002EJ1V1DS
2
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
DIFFERENCES BETWEEN µPD17246 SUBSERIES, µPD17236 SUBSERIES, AND µPD17255
SUBSERIES (1/2)
Item
µPD17246 Subseries
µPD17236 Subseries
µPD17225 Subseries
ROM
µPD17240: 2,048 × 16 bits
µPD17241: 4,096 × 16 bits
µPD17242: 6,144 × 16 bits
µPD17243: 8,192 × 16 bits
µPD17244: 10,240 × 16 bits
µPD17245: 12,288 × 16 bits
µPD17246: 16,384 × 16 bits
µPD17230: 2,048 × 16 bits
µPD17231: 4,096 × 16 bits
µPD17232: 6,144 × 16 bits
µPD17233: 8,192 × 16 bits
µPD17234: 10,240 × 16 bits
µPD17235: 12,288 × 16 bits
µPD17236: 16,384 × 16 bits
µPD17225: 2,048 × 16 bits
µPD17226: 4,096 × 16 bits
µPD17227: 6,144 × 16 bits
µPD17228: 8,192 × 16 bits
RAM
Ports
447 × 4 bits
223 × 4 bits
111 × 4 bits
(µPD17225, 17226)
223 × 4 bits
(µPD17227, 17228)
P0B0 to P0B3: I/O (bit I/O)
P0C0 to P0C3: I/O (group I/O)
P0D0 to P0D3: I/O (group I/O)
P1A0 to P1A2: I/O (bit I/O)
P1B0: I/O, functions
P0B0 to P0B3: I/O (bit I/O)
P0B0 to P0B3: Input
P0C0 to P0C3: I/O (group I/O) P0C0 to P0C3: Output
P0D0 to P0D3: I/O (group I/O) P0D0 to P0D3: Output
P1A0: Input or output
selectable by mask
alternately as INT pin
option
Reset
The RESET pin is internally pulled down by the occurrence of
the internal reset signals on the left, causing a reset (usually,
the RESET pin is pulled up).
A low level is output from the
WDOUT pin by the
• Reset by watchdog
timer
occurrence of the internal
reset signals on the left, and
a reset takes place if the
WDOUT pin is externally
connected to the RESET pin.
• Reset by stack pointer
• Low-voltage detector
(mask option)
Capacitor for oscillation
Vector address
Selected by mask option
(15 pF)
Not provided
Basic interval timer: 0002H
Rising and falling
Basic interval timer:
0001H
Rising and falling edges of INT pin: 0002H
edges of INT pin:
8-bit timer:
0003H
0004H
8-bit timer:
0003H
RAM retention flag
Provided
Not provided
Data Sheet U15002EJ1V1DS
3
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
DIFFERENCES BETWEEN µPD17246 SUBSERIES, µPD17236 SUBSERIES, AND µPD17255
SUBSERIES (2/2)
Item
µPD17246 Subseries
µPD17236 Subseries
µPD17225 Subseries
STOP mode release
condition
<1> When any of pins P0A0
to P0A3 goes low
<1> When any of pins P0A0
to P0A3 goes low
When any of pins P0A0 to
P0A3 and P0B0 to P0B3 goes
<2> When pins P0B0 to P0B3, <2> When pins P0B0 to P0B3, low
P0C0 to P0C3, and P0D0
to P0D3 are used as input
pins and when any of
them goes low
P0C0 to P0C3, and P0D0
to P0D3 are used as
input pins and when any
of them goes low
<3> When an interrupt
request (IRQ) of the
<3> When an interrupt
request (IRQ) of the
interrupt for which the IP
flag is set is generated
at the rising edge or
falling edge of the INT
pin
interrupt for which the IP
flag is set is generated at
the rising edge or falling
edge of the INT pin
<4> When P0E0 to P0E3 are
used as input pins when
a key matrix is used and
when any of these pins
goes low
<5> When P1A0 to P1A2 and
P1B0 are used as input
pins when a key matrix is
used and when the level
of any of these pins
equals the set clear level
Carrier frequency
(fX = 4 MHz)
Selected by register file
(after reset: fX/2)
Selected by mask option
<1> If carrier generation
clock is fX/2: 7.8 kHz to
1 MHz
7.8 kHz to 1 MHz
<1> If carrier generation clock
is fX/2: 3.9 kHz to 1 MHz
<2> If carrier generation clock <2> If carrier generation
is fX: 7.8 kHz to 2 MHz
<3> If carrier generation clock
is 2fX: 15.6 kHz to 4 MHz
clock is fX: 15.6 kHz to
2 MHz
NRZ low-level period
setting modulo register
(NRZLTMM) and NRZ
high-level period setting
modulo register
• NRZLTMM: 8 bits
• NRZLTMM: 7 bits (bit 7 is REM output control bit)
(REM output control bit is bit • NRZHTMM: 7 bits (bit 7 is fixed to 0)
1 of register file at address
12H)
• NRZHTMM: 8 bits
(NRZHTMM)
Data Sheet U15002EJ1V1DS
4
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
PIN CONFIGURATION (TOP VIEW)
•
30-pin plastic SSOP (7.62 mm (300))
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P1A
2
1
P0D
P0D
2
3
P0D
P0D
P0C
P0C
P0C
P0C
1
0
3
2
1
0
2
3
P1B
0/INT
4
P0E
P0E
P0E
P0E
0
1
2
3
5
6
7
P0B
P0B
P0B
P0B
P0A
P0A
P0A
P0A
3
2
1
0
3
2
1
0
8
REM
9
V
DD
10
11
12
13
14
15
X
OUT
X
IN
GND
RESET
P1A
P1A
0
1
GND:
INT:
Ground
External interrupt request signal input
P0A0 to P0A3: Input port (CMOS input with pull-up resistor)
P0B0 to P0B3: I/O port (CMOS input with pull-up resistor/N-ch open-drain output)
P0C0 to P0C3: I/O port (CMOS input with pull-up resistor/N-ch open-drain output)
P0D0 to P0D3: I/O port (CMOS input with pull-up resistor/N-ch open-drain output)
P0E0 to P0E3: I/O port (when key matrix is used: CMOS input with pull-up resistor/N-ch open-
drain output, when key matrix is not used: CMOS input/push-pull output)
P1A0/P1A2:
Input port (when key matrix is used: CMOS input/N-ch open-drain output, when
key matrix is not used: CMOS input/push-pull output)
Input port (CMOS input)
P1B0:
REM:
Remote controller output (CMOS push-pull output)
Reset input
RESET:
VDD:
Power supply
XIN, XOUT:
Resonator connection
Data Sheet U15002EJ1V1DS
5
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
BLOCK DIAGRAM
Remote
control
divider
P0A
P0A
P0A
P0A
0
1
2
3
REM
P0A
P0B
P0C
P0D
P0E
P1A
P1B
RF
RAM
447 × 4 bits
8-bit
timer
P0B
P0B
P0B
P0B
0
1
2
3
System registers
Interrupt
controller
INT/P1B
0
ALU
Reset
controller
P0C
P0C
P0C
P0C
0
1
2
3
RESET
ROM
µ
PD17240: 2,048 × 16 bits
Instruction
decoder
µ
PD17241: 4,096 × 16 bits
µ
PD17242: 6,144 × 16 bits
µ
PD17243: 8,192 × 16 bits
µ
PD17244: 10,240 × 16 bits
P0D
P0D
P0D
P0D
0
1
2
3
µ
PD17245: 12,288 × 16 bits
µ
PD17246: 16,384 × 16 bits
Program counter
V
DD
Power
supply
circuit
P0E
P0E
P0E
P0E
0
1
2
3
GND
CPU clock
Stack (5 levels)
X
X
IN
Basic interval/
watchdog timer
OSC
P1A
P1A
P1A
0
1
2
OUT
P1B
0
Data Sheet U15002EJ1V1DS
6
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
CONTENTS
1. PIN FUNCTIONS ..........................................................................................................................
1.1 Pin Function List...............................................................................................................
9
9
1.2 I/O Circuits ......................................................................................................................... 12
1.3 Handling of Unused Pins ................................................................................................. 14
2. MEMORY SPACE ......................................................................................................................... 15
2.1 Program Counter (PC) ...................................................................................................... 15
2.2 Program Memory (ROM) .................................................................................................. 18
2.3 Stack ................................................................................................................................... 20
2.4 Data Memory (RAM).......................................................................................................... 22
2.5 Register File (RF) .............................................................................................................. 31
3. PORTS .......................................................................................................................................... 34
3.1 Port 0A (P0A0 to P0A3) ..................................................................................................... 34
3.2 Port 0B (P0B0 to P0B3) ..................................................................................................... 34
3.3 Port 0C (P0C0 to P0C3) ..................................................................................................... 34
3.4 Port 0D (P0D0 to P0D3) ..................................................................................................... 34
3.5 Port 0E (P0E0 to P0E3)...................................................................................................... 35
3.6 Port 1A (P1A0 to P1A2) ..................................................................................................... 35
3.7 Port 1B (P1B0).................................................................................................................... 36
3.8 INT Pin ................................................................................................................................ 37
3.9 Switching Bit I/O (Port 0B, 0E, 1A) ................................................................................. 38
3.10 Selecting I/O Mode of Group I/O (Port 0C, 0D) ............................................................. 40
3.11 Selecting Whether Key Matrix Is Used or Not (Port 0E, 1A) ....................................... 41
3.12 Specifying Resistor Connection (Port 0E, 1A) ............................................................. 42
3.13 Selecting Standby Mode Release Condition and Whether Pull-Up or Pull-Down
Resistor Is Connected (Port 1A) ..................................................................................... 44
3.14 Selecting Whether Key Matrix Is Used, Standby Mode Release Condition, and
Whether Pull-Up or Pull-Down Resistor Is Connected (Port 1B) ............................... 46
4. CLOCK GENERATOR ................................................................................................................. 47
4.1 Instruction Execution Time (CPU Clock) Selection...................................................... 47
5. 8-BIT TIMER AND REMOTE CONTROLLER CARRIER GENERATOR ................................... 48
5.1 Configuration of 8-Bit Timer (with Modulo Function) .................................................. 48
5.2 Function of 8-Bit Timer (with Modulo Function) .......................................................... 50
5.3 Carrier Generator for Remote Controller....................................................................... 51
6. BASIC INTERVAL TIMER/WATCHDOG TIMER ......................................................................... 57
6.1 Source Clock for Basic Interval Timer ........................................................................... 57
6.2 Controlling Basic Interval Timer ..................................................................................... 57
6.3 Operation Timing for Watchdog Timer ........................................................................... 59
7. RAM RETENTION DETECTOR................................................................................................... 60
7.1 RAM Retention Flag.......................................................................................................... 60
Data Sheet U15002EJ1V1DS
7
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
8. INTERRUPT FUNCTIONS ........................................................................................................... 62
8.1 Interrupt Sources .............................................................................................................. 62
8.2 Hardware of Interrupt Controller .................................................................................... 63
8.3 Interrupt Sequence ........................................................................................................... 66
9. STANDBY FUNCTIONS............................................................................................................... 68
9.1 HALT Mode......................................................................................................................... 68
9.2 HALT Instruction Execution Conditions ........................................................................ 69
9.3 STOP Mode ........................................................................................................................ 70
9.4 STOP Instruction Execution Conditions........................................................................ 71
9.5 Releasing Standby Mode ................................................................................................. 72
10. RESET .......................................................................................................................................... 73
10.1 Reset by Reset Signal Input ............................................................................................ 73
10.2 Reset by Watchdog Timer (with RESET Pin Internally Pulled Down) ........................
73
10.3 Reset by Stack Pointer (with RESET Pin Internally Pulled Down)............................. 74
11. LOW-VOLTAGE DETECTOR (WITH RESET PIN INTERNALLY PULLED DOWN) .................
75
12. ASSEMBLER RESERVED WORDS............................................................................................ 76
12.1 Mask Option Directives .................................................................................................... 76
12.2 Reserved Symbols ............................................................................................................ 77
13. INSTRUCTION SET ..................................................................................................................... 83
13.1 Instruction Set Outline ..................................................................................................... 83
13.2 Legend ................................................................................................................................ 84
13.3 List of Instructions ........................................................................................................... 85
13.4 Assembler (RA17K) Embedded Macro Instructions .................................................... 87
14. ELECTRICAL SPECIFICATIONS................................................................................................ 88
15. APPLICATION CIRCUIT EXAMPLE ........................................................................................... 94
16. PACKAGE DRAWING ................................................................................................................. 95
17. RECOMMENDED SOLDERING CONDITIONS ........................................................................ 96
APPENDIX A DIFFERENCES BETWEEN µPD17246 AND µPD17P246 ....................................... 97
APPENDIX B DEVELOPMENT TOOLS ............................................................................................ 98
Data Sheet U15002EJ1V1DS
8
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
1. PIN FUNCTIONS
1.1 Pin Function List (1/3)
Pin No.
Pin Name
Function
Output Format After Reset
28
29
1
P0D0
P0D1
P0D2
P0D3
These pins constitute a 4-bit I/O port which can be set to the input N-ch
Low-level
output
or output mode in 4-bit units (group I/O).
open drain
In the input mode, these pins serve as CMOS input pins with a
pull-up resistor, and can be used to input the key return signals of
a key matrix. The standby status must be released when at least
one of the input lines goes low. In the output mode, these pins are
used as N-ch open-drain output pins and can be used to output
the signals of a key matrix.
2
3
P1B0/INT
This is an input port pin. Whether this pin functions as the P1B0
pin or the INT pin can be selected by the register file.
• P1B0
–
P1B0 input
(when key
matrix not
used and no
resistor
This is a 1-bit CMOS input port.
This port can be used to input key return signals when a key
matrix is used. At this time, whether a pull-up/down resistor is
connected to this port and the standby mode release condition
(whether it is released when this pin is high or low) can be
selected.
connected)
1. If connection of a resistor is specified and if it is specified that
the standby mode is released when this pin goes low
... A pull-up resistor is connected. If a low level is input to the
P1B0 pin, the standby mode is released.
2. If connection of a resistor is specified and if it is specified that
the standby mode is released when this pin goes high
... A pull-down resistor is connected. If a high level is input to
the P1B0 pin, the standby mode is released.
3. If connection of a resistor is not specified and if it is specified
that the standby mode is released when this pin goes low
(or high)
... No resistor is connected. If a low (or high) level is input to
the P1B0 pin, the standby mode is released.
If a key matrix is not used, whether a resistor is connected and
whether the resistor is pull-up or pull-down can be
selected.
• INT
This is an external interrupt request signal. It can also be used
to release the standby mode if an external interrupt request
signal is input to this pin while the INT pin interrupt enable flag
(IP) is set.
Data Sheet U15002EJ1V1DS
9
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
1.1 Pin Function List (2/3)
Pin No.
Pin Name
Function
Output Format After Reset
4
5
6
7
P0E0
P0E1
P0E2
P0E3
These pins constitute a 4-bit I/O port that can be set to the input or When key
CMOS input
(when key
matrix is not
used and no
resistor
output mode in 1-bit units.
matrix is
If this port is set to the input mode when a key matrix is used, it
functions as a CMOS input port with a pull-up resistor and can be
used to input key return signals. If one of the pins of this port
goes low, the standby mode is released.
used: N-ch
open-drain,
when key
matrix is not connected)
used: CMOS
If this port is set to the output mode when a key matrix is used, it
functions as an N-ch open-drain output port and can be used to
output key matrix signals.
push-pull
If this port is set to the input mode when a key matrix is not used,
it functions as a CMOS input port to/from which a resistor can be
connected/disconnected in 1-bit units. If this port is set in the
output mode when a key matrix is not used, it functions as a high-
current CMOS output port.
8
9
REM
Outputs transfer signal for infrared remote controller.
Active-high output.
CMOS
Low-level
output
push-pull
VDD
Power supply
–
–
–
10
11
XOUT
XIN
Connects ceramic resonator for system clock oscillation.
A capacitor (15 pF) for oscillation can be connected by using a
mask option.
(Oscillation
stops)
12
13
GND
Ground
–
–
–
RESET
System reset input. Turns ON pull down resistor if the POC or
watchdog timer overflows and if the stack pointer overflows or
underflows, and resets the system. Usually, the pull-down resistor
is ON.
Input
Data Sheet U15002EJ1V1DS
10
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
1.1 Pin Function List (3/3)
Pin No.
Pin Name
Function
These pins constitute a 3-bit I/O port that can be set to the input or When key
output mode in 1-bit units. matrix is
If this port is set to the input mode when a key matrix is used, it used: N-ch
Output Format After Reset
14
15
30
P1A0
P1A1
P1A2
CMOS input
(when key
matrix is not
used and
functions as a CMOS input port and can be used to input key
return signals. At this time, whether a pull-up/down resistor is
connected to this port and the standby mode release condition
(whether it is released when this pin is high or low) can be
selected in 1-bit units
open-drain,
when key
no resistor
matrix is not connected)
used: CMOS
push-pull.
1. If connection of a resistor is specified and if it is specified that
the standby mode is released when this port goes low
... A pull-up resistor is connected. If a low level is input to
the set key, the standby mode is released.
2. If connection of a resistor is specified and if it is specified that
the standby mode is released when this port goes high
... A pull-down resistor is connected. If a high level is input
to the set key, the standby mode is released.
3. If connection of a resistor is not specified and if it is specified
that the standby mode is released when this port goes low
(or high)
... No resistor is connected. If a low (or high) level is input to
the set key, the standby mode is released.
If this port is set to the output mode when a key matrix is used, it
functions as an N-ch open-drain output port and can be used to
output key matrix signals.
If this port is set to the input mode when a key matrix is used, it
functions as a CMOS input port.
Connection of a resistor to this port and whether the resistor is
pull-up or pull-down can be selected in 1-bit units.
If this port is set in the output mode when a key matrix is not used,
it functions as a high-current CMOS output port.
16
17
18
19
P0A0
P0A1
P0A2
P0A3
These pins are CMOS input pins with a 4-bit pull-up resistor.
They can be used to input the key return signals of a key matrix.
If any one of these pins goes low, the standby status is released.
–
CMOS input
with pull-up
resistor
20
21
22
23
P0B0
P0B1
P0B2
P0B3
These pins constitute a 4-bit I/O port that can be set to the input or N-ch
CMOS input
with pull-up
resistor
output mode in 1-bit units.
open drain
In the input mode, these pins are CMOS input pins with a pull-up
resistor, and can be used to input the key return signals of a key
matrix. The standby status is released when at least one of these
pins goes low.
In the output mode, they serve as N-ch open-drain output pins and
can be used to output the key return signals of a key matrix.
24
25
26
27
P0C0
P0C1
P0C2
P0C3
These pins constitute a 4-bit I/O port that can be set to the input or N-ch
Low-level
output
output mode in 4-bit units (group I/O).
open drain
In the input mode, these pins are CMOS input pins with a pull-up
resistor, and can be used to input the key return signals of a key
matrix. The standby status is released when at least one of these
pins goes low.
In the output mode, they serve as N-ch open-drain output pins and
can be used to output the key return signals of a key matrix.
Data Sheet U15002EJ1V1DS
11
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
1.2 I/O Circuits
The equivalent I/O circuit for each µPD17246 pin is shown below.
Figure 1-1. I/O Circuits (1/2)
(1) P0A
(4) P1A
V
DD
STOP
clear level
Data
V
DD
Pull-up/
pull-down
resistor
P-ch
Input buffer
Data
Data
Data
V
DD
Output
latch
P-ch
(2) P0B, P0C, P0D
Key matrix
use/non-
use resistor
N-ch
Output
V
DD
disable
Selector
N-ch
Input buffer
P-ch
Output
Data
(5) P1B
latch
V
DD
N-ch
Output
disable
Pull-up/
pull-down
resistor
Data
Data
P-ch
N-ch
Selector
Input buffer
STOP
clear level
(3) P0E
VDD
Input buffer
Key matrix
Data
Data
Data
use/non-
use resistor
P-ch
VDD
Pull-up
resistor
P-ch
N-ch
Output
latch
Output
disable
Selector
Input buffer
Data Sheet U15002EJ1V1DS
12
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
Figure 1-1. I/O Circuits (2/2)
(8) REM
(6) RESET
VDD
V
DD
Data
P-ch
Reset input
P-ch
N-ch
Output
disable
Input buffer
Schmitt trigger input with
hysteresis characteristics
N-ch
(7) INT
Input buffer
Schmitt trigger input with hysteresis
characteristics
Data Sheet U15002EJ1V1DS
13
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
1.3 Handling of Unused Pins
Handle the unused pins as follows.
Table 1-1. Handling of Unused Pins
Pin Name
P0A0 to P0A3
P0B0 to P0B3
P0C0 to P0C3
P0D0 to P0D3
P0E0 to P0E3
P1A0 to P1A2
P1B0/INT
Recommended Connection
Leave open.
Connect to GND (When input).
Connect to GND.
Leave open.
REM
Data Sheet U15002EJ1V1DS
14
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
2. MEMORY SPACE
2.1 Program Counter (PC)
The program counter (PC) specifies an address of the program memory (ROM).
The program counter consists of an 11/12/13-bit binary counter and a 1-bit segment register (SGR) as shown
in Figure 2-1.
Its contents are initialized to address 0000H at reset.
Figure 2-1. Configuration of Program Counter
Page
MSB
SGR
LSB
PC
PC12
PC11
PC10
PC
9
PC8
PC7
PC6
PC
5
PC
4
PC3
PC
2
PC
1
0
PC (
PC ( PD17241)
PD17242, 17243)
µPD17244, 17245, 17246)
µPD17240)
µ
PC (µ
PC (
2.1.1
The segment register specifies a segment of the program memory.
Table 2-1 shows the relationship between the segment register and program memory.
Segment register (SGR)
Table 2-1. Relationship Between Segment Register and Program Memory
Value of Segment Register
Segment of Program Memory
Segment 0
0
1
Segment 1
The segment register is set when the following instructions are executed.
•
•
•
BR @AR
CALL @AR
SYSCAL entry
Data Sheet U15002EJ1V1DS
15
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
The first address of the subroutine that can be called by the system call instruction (“SYSCAL entry”) is the first
16 steps of each block (blocks 0 to 7) in page 0 of segment 1 (system segment).
Figure 2-2. Outline of System Call Instruction
Segment 1
Segment 0
(system segment)
Block 0 of segment 1
0 0 0 0 0 H
0 2 0 0 0 H
0 2 0 0 0 H
0 2 0 0 F H
Entry address of
SYSCAL instruction
Block 0
0 2 0 F F H
0 2 1 0 0 H
Block 1
Block 2
0 2 1 F F H
0 2 2 0 0 H
Page 0
(16 bits × 2K steps)
0 2 2 F F H
Area in which
entry address of
system segment
can be specified
.
.
.
.
0 2 7 0 0 H
Block 7
0 0 7 F F H
0 0 8 0 0 H
0 2 7 F F H
0 2 8 0 0 H
Page 1
Page 2
Page 1
Page 2
Page 3
0 0 F F F H
0 1 0 0 0 H
0 2 F F F H
0 3 0 0 0 H
0 1 7 F F H
0 1 8 0 0 H
0 3 7 F F H
0 3 8 0 0 H
Page 3
0 1 F F F H
0 3 F F F H
(16 bits × 8K steps)
(16 bits × 8K steps)
Data Sheet U15002EJ1V1DS
16
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
Figure 2-3. Value of Program Counter on Execution of Each Instruction
Program Counter
Contents of Program Counter (PC)Note
Instruction
BR addr
SGR b12
0
b11
0
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Page 0
Page 1
Page 2
Page 3
0
1
1
1
Re-
tained
0
Operand of instruction (addr)
Operand of instruction (addr)
1
CALL addr
Re-
tained
0
0
0
0
SYSCAL entry
1
0
0
0
0
entryH
entryL
BR @AR
CALL @AR
Contents of address register
MOVT DBF, @AR
RET
RETSK
Contents (return address) of address stack register (ASR)
specified by stack pointer (SP)
RETI
Other instructions
(including skip instruction)
On acknowledging interrupt
Re-
tained
Increment
0
0
Vector address of each interrupt
Watchdog timer reset,
RESET pin,
0
0
0
0
0
0
0
0
0
0
0
0
0
reset by stack pointer
Note µPD17240:
µPD17241:
b0 to b10
b0 to b11
b0 to b12
µPD17242, 17243:
µPD17244, 17245, 17246: b0 to b12, SGR
Remark entryH: Higher 3 bits of entry
entryL: Lower 4 bits of entry
Table 2-2. Interrupt Vector Address
Priority
Internal/External
Internal
Interrupt Source
Vector Address
1
2
3
8-bit timer
0004H
0003H
0002H
External
Rising and falling edges of INT pin
Basic interval timer
Internal
Data Sheet U15002EJ1V1DS
17
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
2.2 Program Memory (ROM)
The configuration of the program memory is as follows.
Part Number
µPD17240
Program Memory Capacity
2,048 × 16 bits
Program Memory Address
0000H to 07FFH
µPD17241
µPD17242
µPD17243
µPD17244
µPD17245
µPD17246
4,096 × 16 bits
0000H to 0FFFH
0000H to 17FFH
6,144 × 16 bits
8,192 × 16 bits
0000H to 1FFFH
0000H to 27FFH
10,240 × 16 bits
12,288 × 16 bits
16,384 × 16 bits
0000H to 2FFFH
0000H to 3FFFH
The program memory stores the program, interrupt vector table, and fixed data table.
The program memory is addressed by the program counter.
Figure 2-4 shows the program memory map. The entire range of the program memory can be addressed by the
BD addr, BR @AR, CALL @AR, MOVT DBF, and @AR instructions. Note, however, that the subroutine entry
addresses that can be specified by the CALL addr instruction are from 0000H to 07FFH.
Data Sheet U15002EJ1V1DS
18
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
Figure 2-4. Program Memory Map
Address
0 0 0 0
H
Reset start address
0 0 0 1 H Normal address
0 0 0 2
0 0 0 3
0 0 0 4
H
H
H
Basic interval timer interrupt vector
Page 0 Subroutine entry Branch addresses for
address for CALL BR@AR instruction
INT pin rising/falling edge interrupt vector
8-bit timer interrupt vector
addr instruction
Subroutine entry
addresses for CALL@AR
instruction
Segment 0 Branch
addresses
(
(
(
(
µ
µ
µ
µ
PD17240)
PD17241)
PD17242)
PD17243)
0 7 F F
0 F F F
1 7 F F
H
H
H
Table reference
addresses for MOVT DBF,
@AR instruction
for BR addr Page 1
instruction
Page 2
Page 3
Page 0
1 F F F
2 0 0 0
H
H
Subroutine entry
address for CALL
addr instruction
(
(
µ
µ
PD17244)
PD17245)
2 7 F F H
Page 1
Segment 1 Branch
(system addresses
segment) for BR addr
instruction
2 F F F
H
H
Page 2
Page 3
(
µ
PD17246)
16 bits
3 F F F
Data Sheet U15002EJ1V1DS
19
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
2.3 Stack
A stack is a register used to save a program return address and the contents of system registers (to be described
later) when a subroutine is called or when an interrupt is acknowledged.
2.3.1
Stack configuration
Figure 2-5 shows the stack configuration.
A stack consists of a stack pointer (a 4-bit binary counter, the highest bit fixed to 0), five 11-bit (µPD17240)/12-
bit (µPD17241)/13-bit (µPD17242, 17243)/14-bit (µPD17244, 17245, 17246) address stack registers, and three 6-
bit interrupt stack registers.
Figure 2-5. Stack Configuration
Stack pointer
Address stack registers
(SP)
(ASR)
b
3
b
2
b
1
b0
b
12
b
11
b
10
b
9
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b0
b
13
0
SPb2 SPb1 SPb0
0H
1H
2H
3H
4H
5H
6H
7H
Address stack register 0
Address stack register 1
Address stack register 2
Address stack register 3
Address stack register 4
Undefined
The RESET pin is
internally pulled down
and reset is effected.
Undefined
Undefined
µ
PD17240
PD17241
PD17242, 17243
PD17244, 17245, 17246
µ
µ
µ
Interrupt stack registers
(INTSK)
b
5
b
4
b
3
b
2
b
1
b0
0H BANKSK0
1H BANKSK1
BCDSK0
BCDSK1
BCDSK2
CMPSK0
CMPSK1
CMPSK2
CYSK0
CYSK1
CYSK2
ZSK0
ZSK1
ZSK2
IXESK0
IXESK1
IXESK2
BANKSK2
2H
Data Sheet U15002EJ1V1DS
20
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
2.3.2
Function of stack
The address stack register stores a return address when the subroutine call instruction or table reference
instruction (first instruction cycle) is executed or when an interrupt is acknowledged. It also stores the contents of
the address registers (ARs) when a stack manipulation instruction (PUSH AR) is executed.
If subroutines or interrupts are nested to more than 5 levels, the RESET pin is internally pulled down and
a reset is effected.
The interrupt stack register (INTSK) saves the contents of the bank register (BANK) and program status word
(PSWORD) when an interrupt is acknowledged. The saved contents are restored when an interrupt return (RETI)
instruction is executed.
INTSK saves data each time an interrupt is acknowledged, but the data stored first is lost if more than 3 levels
of interrupts occur.
2.3.3
Stack pointer (SP) and interrupt stack pointer
Table 2-3 shows the operations of the stack pointer (SP).
The stack pointer can take eight values, 0H to 7H. Because there are only five stack registers available, however,
the RESET pin is internally pulled down and reset is effected if the value of SP is 6 or greater.
Table 2-3. Operations of Stack Pointer
Instruction
Value of Stack Pointer (SP)
Counter of Interrupt Stack Register
0
CALL addr
CALL @AR
−1
MOVT DBF, @AR
(1st instruction cycle)
PUSH AR
SYSCAL entry
When interrupt is acknowledged
–1
+1
–1
0
RET
RETSK
MOVT DBF, @AR
(2nd instruction cycle)
POP AR
RETI
+1
+1
Data Sheet U15002EJ1V1DS
21
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
2.4 Data Memory (RAM)
The data memory (RAM) stores data for operations and control. It can always be read/written by instructions.
2.4.1
Memory configuration
Figure 2-6 shows the configuration of the data memory (RAM).
The data memory consists of four “banks”: BANK0, BANK1, BANK2, and BANK3.
In each bank, every 4 bits of data are assigned an address. The higher 3 bits of the address indicate a “row address”
and the lower 4 bits of the address indicate a “column address”. For example, a data memory location indicated by
row address 1H and column address 0AH is termed a data memory location at address 1AH. Each address stores
data of 4 bits (= 1 nibble).
In addition, the data memory is divided into the following six functional blocks.
(1) System register (SYSREG)
A system register (SYSREG) is resident on addresses 74H to 7FH (12 nibbles) of each bank. In other words,
each bank has the same system register at its addresses 74H to 7FH.
(2) Data buffer (DBF)
A data buffer is resident on addresses 0CH to 0FH (4 nibbles) of bank 0 of the data memory.
The reset value is 0320H.
(3) General register (GR)
A general register is resident on any row (16 nibbles) of any bank of the data memory.
The row address of the general register is pointed to by the general register pointer (RP) in the system register
(SYSREG).
(4) Port register
A port data register is resident on addresses 6FH, and 70H to 73H of BANK0 and addresses 70H and 71H
of BANK1 (7 nibbles) of the data memory.
No data can be written to or read from addresses 72H and 73H of BANK1 and addresses 70H to 73H of BANK2
or BANK3.
Data Sheet U15002EJ1V1DS
22
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
(5) General-purpose data memory
The general-purpose data memory area is an area of the data memory excluding the system register area,
and the port register area. This memory area has a total of 447 nibbles (111 nibbles in BANK0 and 336 nibbles
(112 nibbles × 3) in BANK1 to BANK3).
Figure 2-6. Configuration of Data Memory (1/2)
BANK 0
8
Column address
0
1
2
3
4
5
6
7
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
Data buffer (DBF)
Example
Address 1AH
in BANK 0
P0E
P0A P0B P0C P0D
System register (SYSREG)
BANK 1
Column address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
Note 1
Note 2
Note 3
P1A
P1B
System register (SYSREG)
Notes 1. Address 6FH of BANK1 can be used as a general-purpose data memory area.
2. Bits 0 to 2 of address 70H of BANK1 are used. Bit 3 is fixed to 0.
3. Only bit 0 of address 71H of BANK1 is used. Bits 1 to 3 are fixed to 0.
Caution No data can be written to or read from addresses 72H and 73H of BANK1.
Data Sheet U15002EJ1V1DS
23
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
Figure 2-6. Configuration of Data Memory (2/2)
Column address
BANK2
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
Note
System register (SYSREG)
Column address
BANK3
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
Note
System register (SYSREG)
Note Address 6FH of BANK2, BANK3 can be used as a general-purpose data memory area.
Caution No data can be written to or read from addresses 70H to 73H of BANK2 and BANK3.
Data Sheet U15002EJ1V1DS
24
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
2.4.2
System registers (SYSREG)
The system registers are registers that are directly related to control of the CPU. These registers are mapped to
addresses 74H to 7FH on the data memory and can be referenced regardless of bank specification.
The system registers include the following registers.
•
•
•
•
•
•
•
•
Address registers (AR0 to AR3)
Window register (WR)
Bank register (BANK)
Memory pointer enable flag (MPE)
Memory pointers (MPH, MPL)
Index registers (IXH, IXM, IXL)
General register pointers (RPH, RPL)
Program status word (PSWORD)
Figure 2-7. Configuration of System Registers
Address
Name
74H
75H
76H
77H
78H
79H
7AH
7BH
7CH
7DH
General
register
pointer
(RP)
7EH
RPL
7FH
Index register
(IX)
Program
status
word
Window Bank
register register
(WR)
Address register
(AR)
Data memory
row address
pointer (MP)
(BANK)
(PSWORD)
IXH
IXM
Symbol
Bit
AR 3
AR 2
AR 1
AR 0
WR
BANK
IXL
RPH
PSW
MPH
MPL
b3b2b1b0b3b2b1b0b3b2b1b0b3b2b1b0b3b2b1b0b3b2b1b0b3b2b1b0b3b2b1b0b3b2b1b0b3b2b1b0b3b2b1b0b3b2b1b0
(WR)
(AR) (µPD17244,17245,17246)
0 0
(IX)
(BANK)
0 0
µ
(AR) ( PD17242,17243)
M
P
E
B C C
C M Y Z X
D P
I
0 0 0
(RP)
Data
0 0
0 0
µ
(AR) ( PD17241)
0 0 0 0
0 0 0 0 0
(MP)
E
µ
(AR) ( PD17240)
Initial
value
at
Undefined
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
reset
Data Sheet U15002EJ1V1DS
25
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
2.4.3
General register (GR)
A general register is a register on the data memory and used for arithmetic operations and transfer of data to and
from the data memory.
(1) Configuration of general register
Figure 2-8 shows the configuration of the general registers.
A general register occupies 16 nibbles (16 × 4 bits) on a selected row address of the data memory as shown
in Figure 2-8.
The row address is selected by the general register pointer (RP) of the system register. Five bits of RP are
valid. Of these, the lower 3 bits (bits 1 to 3 of RPL) are used to set a row address, and the higher 2 bits (bits
0 and 1 of RPH) are used to set a bank. The data memory that can be used as general registers is at row
addresses 0H to 7H in BANK0 to 4.
(2) Functions of general registers
A general register enables an arithmetic operation and data transfer between the data memory and a selected
general register by a single instruction. As a general register is a part of the data memory, you can say that
the general registers enable arithmetic operations and data transfer between two locations of the data memory.
Similarly, the general registers can be accessed by a data memory manipulation instruction as they are a part
of the data memory.
Data Sheet U15002EJ1V1DS
26
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
Figure 2-8. Configuration of General Registers
General register pointer
(RP)
RPH
RPL
BANK0
Column address
b
3
b2
b
1
b0
b3
b2
b
1
b0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
0
0
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Example
General registers
when
General register (16 nibbles)
RP = 0000010B
Port
register
Port register
BANK1
System register
RP
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
Port
register
System register
System register
System register
BANK2
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
General register
settable range
Same system
registers exist
BANK3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
Setting Setting
of BANK of row
address
Data Sheet U15002EJ1V1DS
27
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
2.4.4
Data buffer (DBF)
The data buffer on addresses 0CH to 0FH of the data memory is used for data transfer to and from peripheral
hardware and for storage of data during table referencing.
(1) Functions of the data buffer
The data buffer has two major functions: a function to transfer data to and from hardware and a function to
read constant data from the program memory (for table referencing). Figure 2-9 shows the relationship
between the data buffer and peripheral hardware.
Figure 2-9. Data Buffer and Peripheral Hardware
Data buffer
(DBF)
Peripheral
address
Peripheral hardware
8-bit timer
(TMC, TMM)
Internal bus
05H, 06H
Carrier generator for
remote controller
03H, 04H
40H
(NRZLTMM, NRZHTMM)
Address register (AR)
Program memory
(ROM)
Constant data
Data Sheet U15002EJ1V1DS
28
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
Table 2-4. Relationship Between Peripheral Hardware and Data Buffer
Peripheral
Hardware
Peripheral Register Transferring Data with Data Buffer
Name
Symbol
TMC
Peripheral address Data buffer used
PUT/GET
GET only
8-bit timer
8-bit counter
05H
06H
DBF0, DBF1
DBF0, DBF1
8-bit modulo
register
TMM
PUT only
Remote controller
carrier generator
NRZ low-level
timer modulo
register
NRZLTMM
03H
04H
40H
DBF0, DBF1
DBF0, DBF1
DBF0 to DBF3
PUT
GET
NRZ high-level
timer modulo
register
NRZHTMM
PUT
GET
Note 1
Address register
Address register AR
PUT
Note 2
GET
Notes 1. In the µPD17240: Bits 0 to 3 of AR3 and bit 3 of AR2 are arbitrary values
In the µPD17241: Bits 0 to 3 of AR3 are arbitrary values
In the µPD17242, 17243: Bits 1 to 3 of AR3 are arbitrary values
In the µPD17244, 17245, 17246: Bits 2 to 3 of AR3 are arbitrary values
2. In the µPD17240: Bits 0 to 3 of AR3 and bit 3 of AR2 are always 0
In the µPD17241: Bits 0 to 3 of AR3 are always 0
In the µPD17242, 17243: Bits 1 to 3 of AR3 are always 0
In the µPD17244, 17245, 17246: Bits 2 to 3 of AR3 are always 0
(2) Table referencing
An MOVT instruction reads constant data from a specified location of the program memory (ROM) and sets
it in the data buffer.
The function of the MOVT instruction is explained below.
MOVT DBF, @AR: Reads data from a program memory location pointed to by the address register (AR) and
sets it in the data buffer (DBF).
Data buffer
DBF 3
DBF 2
DBF 1
DBF 0
Program memory (ROM)
16 bits
MOVT DBF, @ AR
b
15
b0
Data Sheet U15002EJ1V1DS
29
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
(3) Notes on using data buffer
When transferring data to/from the peripheral hardware via the data buffer, the unused peripheral addresses,
write-only peripheral registers (only when executing PUT), and read-only peripheral registers (only when
executing GET) must be handled as follows.
•
•
•
When device operates
Nothing changes even if data is written to a read-only register.
If an unused address is read, an undefined value is read. Nothing changes even if data is written to that
address.
Using assembler
An error occurs if an instruction is executed to read a write-only register.
Again, an error occurs if an instruction is executed to write data to a read-only register.
An error also occurs if an instruction is executed to read or write an unused address.
If an in-circuit emulator (IE-17K or IE-17K-ET) is used (when an instruction is executed for patch
processing)
An undefined value is read if an attempt is made to read the data of a write-only register, but an error does
not occur.
Nothing changes even if data is written to a read-only register, and an error does not occur.
An undefined value is read if an unused address is read; nothing changes even if data is written to this
address. An error does not occur.
Data Sheet U15002EJ1V1DS
30
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
2.5 Register File (RF)
The register file mainly consists of registers that set the conditions of the peripheral hardware.
These registers can be controlled by the dedicated instructions PEEK and POKE, and the embedded macro
instructions of RA17K, SETn, CLRn, and INITFLG.
2.5.1
Figure 2-10 shows the configuration of the register file and how the register file is accessed by the PEEK and POKE
instructions.
Configuration of register file
The control registers are controlled by using dedicated instructions PEEK and POKE. Since the control registers
are assigned to addresses 00H to 3FH regardless of the bank, the addresses 00H to 3FH of the general-purpose data
memory cannot be accessed when the PEEK or POKE instruction is used.
The addresses that can be accessed by the PEEK and POKE instructions are addresses 00H to 3FH of the control
registers and 40H to 7FH of the general-purpose data memory. The register file consists of these addresses.
The control registers are assigned to addresses 80H to BFH on the IE-17K to facilitate debugging.
Figure 2-10. Register File Configuration and Register File Access with PEEK or POKE Instructions
Column address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
Data memory
POKE M063, WR
7
System register
0
1
2
3
PEEK WR, SP
POKE LCDMD, WR
Control register
Register file
Data Sheet U15002EJ1V1DS
31
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
2.5.2
Control registers
The control registers consist of a total of 64 nibbles (64 × 4 bits) of addresses 00H to 3FH of the register file.
Of these, however, only 24 nibbles are actually used. The remaining 40 nibbles are unused registers that are
prohibited from being read or written.
When the “PEEK WR, rf” instruction is executed, the contents of the register file addressed by “rf” are read to the
window register.
When the “POKE rf, WR” instruction is executed, the contents of the window register are written to the register
file addressed by “rf”.
When using the assembler (RA17K), the macro instructions listed below, which are embedded as flag type symbol
manipulation instructions, can be used. The macro instructions allow the contents of the register file to be manipulated
in bit units.
For the configuration of the control register, refer to Figure 12-1 Register File List.
SETn:
CLRn:
SKTn:
SKFn:
NOTn:
Sets flag to “1”
Sets flag to “0”
Skips if all flags are “1”
Skips if all flags are “0”
Inverts flag
INITFLG: Initializes flag
INITFLGX: Initializes flag
2.5.3
Notes on using register files
When using the register files, bear in mind the points described below. For details, refer to the µPD172xx
Subseries User’s Manual (U12795E).
(1) When manipulating control registers (read-only and unused registers)
When manipulating the write-only (W), the read-only (R), and unused control registers by using an assembler
or in-circuit emulator, keep in mind the following points.
•
•
•
When device operates
Nothing changes even if data is written to a read-only register.
If an unused register is read, an undefined value is read; nothing is changed even if data is written to this
register.
Using assembler
An error occurs if an instruction is executed to read data from a write-only register.
An error occurs if an instruction is executed to write data to a read-only register.
An error also occurs if an instruction is executed to read or write an unused address.
When an in-circuit emulator (IE-17K or IE-17K-ET) is used (when an instruction is executed for patch
processing)
An undefined value is read if a write-only register is read, and an error does not occur.
Nothing changes even if data is written to a read-only register, and an error does not occur.
An undefined value is read if an unused address is read; nothing changes even if data is written to this
address. An error does not occur.
Data Sheet U15002EJ1V1DS
32
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
(2) Symbol definition of register file
An error occurs if a register file address is directly specified as a numeral by the operand “rf” of the “PEEK
WR, rf” or “POKE rf, WR” instruction if the 17K Series Assembler (RA17K) is being used.
Therefore, the addresses of the register file must be defined in advance as symbols.
To define the addresses of the control registers as symbols, define them as addresses 80H to BFH of BANK0.
The portion of the register file overlapping the data memory (40H to 7FH), however, can be defined as symbols
as is.
Data Sheet U15002EJ1V1DS
33
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
3. PORTS
3.1 Port 0A (P0A0 to P0A3)
This is a 4-bit input port. Data is read using port register P0A (address 70H of BANK0). This port is a CMOS input
port with a pull-up resistor, and can be used as the key return input lines of a key matrix.
In the standby mode, the standby status is released when a low level is input to at least one of these pins.
3.2 Port 0B (P0B0 to P0B3)
This is a 4-bit I/O port which can be set to the input or output mode in 1-bit units by using P0BBIO (address 26H)
of the register file.
In the input mode, each bit of this port serves as a CMOS input pin with a pull-up resistor and can be used as a
key return input line of a key matrix. In the standby mode, the standby status is released when a low level is input
to at least one of these pins.
In the output mode, these pins serve as N-ch open-drain output pins and can be used as the key source lines of
a key matrix.
The data input to this port can be read or the data output from this port can be set by using the P0B register (address
71H of BANK0). When this port is read in the output mode, the contents of the output latch are read.
In the input mode, a pull-up resistor of 200 kΩ is connected to each bit of this port. In the output mode, the pull-
up resistor is disconnected.
After reset, this port is set to the input mode.
3.3 Port 0C (P0C0 to P0C3)
This is a 4-bit I/O port which can be set to the input or output mode in 4-bit units (group I/O) by using P0CDGIO
(bit 2 of address 37H) of the register file.
In the input mode, each bit of this port serves as a CMOS input pin with a pull-up resistor and can be used as a
key return input line of a key matrix. In the standby mode, the standby status is released when a low level is input
to at least one of these pins.
In the output mode, these pins serve as N-ch open-drain output pins and can be used as the key source lines of
a key matrix.
The data input to this port can be read or the data output from this port can be set by using the P0C register (address
72H of BANK0). When this port is read in the output mode, the contents of the output latch are read.
In the input mode, a pull-up resistor of 200 kΩ is connected to each bit of this port. In the output mode, the pull-
up resistor is disconnected.
After reset, this port is set to the output mode and outputs a low level.
3.4 Port 0D (P0D0 to P0D3)
This is a 4-bit I/O port which can be set to the input or output mode in 4-bit units (group I/O) by using P0CDGIO
(bit 3 of address 37H) of the register file.
In the input mode, each bit of this port serves as a CMOS input pin with a pull-up resistor and can be used as a
key return input line of a key matrix. In the standby mode, the standby status is released when a low level is input
to at least one of these pins.
In the output mode, these pins serve as N-ch open-drain output pins and can be used as the key source lines of
a key matrix.
The data input to this port can be read or the data output from this port can be set by using the P0D register (address
73H of BANK0). When this port is read in the output mode, the contents of the output latch are read.
In the input mode, a pull-up resistor of 200 kΩ is connected to each bit of this port. In the output mode, the pull-
up resistor is disconnected.
After reset, this port is set to the output mode and outputs a low level.
Data Sheet U15002EJ1V1DS
34
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
3.5 Port 0E (P0E0 to P0E3)
This is a 4-bit I/O port. The input mode or output mode and whether a key matrix is used or not can be set for this
port in 1-bit units.
The input and output modes of this port are selected by using P0EBIO (address 27H) of the register file.
Whether a key matrix is used or not is specified by P0EKEY (address 16H) of the register file.
If this port is set to the input mode when a key matrix is used, it functions as a CMOS input port with a pull-up resistor
and can be used to input key return signals. If one of the pins of this port goes low, the standby mode is released.
If this port is set to the output mode when a key matrix is used, it functions as an N-ch open-drain output port and
can be used to output key matrix signals.
If this port is set to the input mode when a key matrix is not used, it functions as a CMOS input port to/from which
a pull-up resistor can be connected/disconnected in 1-bit units, by using P0EBPU (address 17H) of the register file
(if a pull-up resistor is connected, it is not disconnected even if the output mode is set). At this time, the standby mode
is not released.
If this port is set to the output mode when a key matrix is not used, it functions as a high-current CMOS output port.
To read the input data from this port or set output data to it, use the P0E register (address 6FH of BANK0). When
this port is read in the output mode, the contents of the output latch are read.
After reset, this port is set to the input mode (a key matrix is not used and a resistor is not connected).
3.6 Port 1A (P1A0 to P1A2)
These pins constitute a 3-bit I/O port that can be set in the input or output mode in 1-bit units.
If this port is set to the input mode when a key matrix is used, it functions as a CMOS input port and can be used
to input key return signals. At this time, whether a resistor is connected to this port and the standby mode release
condition (whether it is released when this port is high or low) can be selected.
1. If connection of a resistor is specified and if it is specified that the standby mode is released when this port
goes low
... A pull-up resistor is connected. If a low level is input to the set key, the standby mode is released.
2. If connection of a resistor is specified and if it is specified that the standby mode is released when this port
goes high
... A pull-down resistor is connected. If a high level is input to the set key, the standby mode is released.
3. If connection of a resistor is not specified and if it is specified that the standby mode is released when this port
goes low (or high)
... No resistor is connected. If a low (or high) level is input to the set key, the standby mode is released.
If this port is set to the output mode when a key matrix is used, it functions as an N-ch open-drain output port and
can be used to output key matrix signals.
If this port is set to the input mode when a key matrix is not used, it functions as a CMOS input port. Connection
of a resistor to this port and whether a pull-up or pull-down resistor is connected to the port can be selected in 1-bit
units. At this time, the standby mode is not released.
If this port is set to the output mode when a key matrix is not used, it functions as a high-current CMOS output port.
To set this port to the input mode or output mode, use P1ABIO (address 25H) of the register file. To specify whether
a key matrix is used or not, use P1AKEY (address 06H) of the register file. To specify whether a resistor is connected,
use P1ABPU (address 07H) of the register file. To specify the standby mode release condition (to specify whether
a pull-down or pull-up resistor is connected when a key matrix is not used), use P1AHL (address 05H) of the register
file.
Use the P1A register (address 70H of BANK1) to read the input data from this port or set output data to it. When
this port is read in the output mode, the contents of the output latch are read.
After reset, this port is set to the input mode (a key matrix is not used and a resistor is not connected).
Data Sheet U15002EJ1V1DS
35
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
3.7 Port 1B (P1B0)
The P1B0 pin functions alternately as the INT pin. To use the P1B0 pin, set INTSEL (bit 1 of address 1FH) of the
register file to 0.
The P1B0 pin functions as a 1-bit CMOS input port.
This port can be used to input a key return signal when a key matrix is used. At this time, whether a resistor is
connected to this port and the standby mode release condition (whether it is released when this pin is high or low)
can be selected.
1. If connection of a resistor is specified and if it is specified that the standby mode is released when this pin goes
low
... A pull-up resistor is connected. If a low level is input to P1B0, the standby mode is released.
2. If connection of a resistor is specified and if it is specified that the standby mode is released when this pin goes
high
... A pull-down resistor is connected. If a high level is input to P1B0, the standby mode is released.
3. If connection of a resistor is not specified and if it is specified that the standby mode is released when this pin
goes low (or high)
... No resistor is connected. If a low (or high) level is input to P1B0, the standby mode is released.
If a key matrix is not used, whether a resistor is connected and whether a pull-up or pull-down resistor is connected
can be selected. At this time, the standby mode is not released.
To specify whether a resistor is connected, use P1BPU0 (bit 0 of address 05H) of the register file. To specify
whether a key matrix is used or not, use P1BKEY0 (bit 1 of address 05H) of the register file. To specify a standby
condition (to specify whether a pull-down or pull-up resistor is connected when a key matrix is not used), use P1BHL0
(bit 2 of address 05H) of the register file.
Use the P1B register (address 71H of BANK1) to read the input data.
After reset, the P1B0 pin is selected and functions as an input port (a key matrix is not used and a resistor is not
connected).
Data Sheet U15002EJ1V1DS
36
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
3.8 INT Pin
The INT pin functions alternately as the P1B0 pin. To use the INT pin, set INTSEL (bit 1 of address 1FH) of the
register file to 1.
This pin inputs an external interrupt request signal. The IRQ flag (RF: bit 0 of address 3EH) is set at either the
rising or falling edge of the signal input to this pin.
The status of this pin can be read by using the INT flag (RF: bit 0 of address 0FH). When a high level is input to
the pin, the INT flag is set to “1”; when a low level is input, the flag is reset to “0” (refer to 8.2.1 INT).
Table 3-1. Relationship Between Port Register and Each Pin
Bank Address
Target Port
Port 0A
Bit
Output
Format
Read Contents
Input mode Output mode Input mode Output mode
Pin status
Written Contents
After Reset
0
70H
71H
72H
73H
6FH
b3 P0A3 Input
b2 P0A2
–
–
–
Input mode
(with pull-up
resistor)
b1 P0A1
b0 P0A0
Port 0B
Port 0C
Port 0D
Port 0E
b3 P0B3 N-ch
Output latch Output latch Output latch
open drain
b2 P0B2
b1 P0B1
b0 P0B0
b3 P0C3
b2 P0C2
b1 P0C1
b0 P0C0
b3 P0D3
b2 P0D2
b1 P0D1
b0 P0D0
b3 P0E3 CMOS
Output mode
(low-level
output)
Input mode
(when key
push-pull
b2 P0E2
b1 P0E1
b0 P0E0
matrix not
or N-ch
used and no
pull-up resistor
connected)
open drain
1
70H
71H
Port 1A
b2 P1A2 CMOS
Input mode
(when key
matrix not
used and no
resistor
push-pull
b1 P1A1
b0 P1A0
or N-ch
open drain
connected)
Port 1B
b0 P1B0 Input
–
–
–
Input mode
(when key
matrix not
used and no
resistor
connected)
Data Sheet U15002EJ1V1DS
37
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
3.9 Switching Bit I/O (Port 0B, 0E, 1A)
An I/O that can be set to the input or output mode in bit units is called a bit I/O. P0B, P0E, and P1A are bit I/O
ports, which can be set in the input or output mode in bit units by the register file shown below. When the mode is
changed from input to output, the P0B, P0E, and P1A output latch contents are output to the port lines as soon as
the mode has been changed.
3
2
1
0
Address After reset
R/W
R/W
P0BBIO3
P0BBIO2
P0BBIO1
P0BBIO0
RF: 26H
0H
P0BBIO0
Sets P0B input/output mode
0
0
1
Sets P0B
Sets P0B
0
0
in input mode
in output mode
P0BBIO1
Sets P0B
1
input/output mode
in input mode
in output mode
0
1
Sets P0B
Sets P0B
1
1
P0BBIO2
Sets P0B
2
input/output mode
in input mode
in output mode
0
1
Sets P0B
Sets P0B
2
2
P0BBIO3
Sets P0B
3
input/output mode
in input mode
in output mode
0
1
Sets P0B
Sets P0B
3
3
Data Sheet U15002EJ1V1DS
38
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
3
2
1
0
Address
RF: 27H
After reset
0H
R/W
R/W
P0EBIO3 P0EBIO2 P0EBIO1 P0EBIO0
P0EBIO0
Sets P0E input/output mode
0
0
1
Sets P0E
0
0
in input mode
in output mode
Sets P0E
P0EBIO1
Sets P0E input/output mode
1
0
1
Sets P0E
1
1
in input mode
in output mode
Sets P0E
P0EBIO2
Sets P0E input/output mode
2
0
1
Sets P0E
2
2
in input mode
in output mode
Sets P0E
P0EBIO3
Sets P0E input/output mode
3
0
1
Sets P0E
3
3
in input mode
in output mode
Sets P0E
3
0
2
1
0
Address
RF: 25H
After reset
0H
R/W
R/W
P1ABIO2 P1ABIO1 P1ABIO0
P1ABIO0
Sets P1A
0
input/output mode
input/output mode
input/output mode
0
1
Sets P1A
0
0
in input mode
Sets P1A
in output mode
P1ABIO1
Sets P1A
1
0
1
Sets P1A
1
1
in input mode
Sets P1A
in output mode
P1ABIO2
Sets P1A
2
0
1
Sets P1A
2
2
in input mode
Sets P1A
in output mode
Data Sheet U15002EJ1V1DS
39
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
3.10 Selecting I/O Mode of Group I/O (Port 0C, 0D)
An I/O that is set to the input or output mode in 4-bit units is called a group I/O. P0C and P0D can be used as
group I/O ports. The input and output modes of these ports are selected by using the following register file. If the
mode is changed from input to output, the contents of the port register are output to the respective ports as soon as
the mode has been changed.
3
2
1
0
0
0
Address After reset
R/W
R/W
P0DGIO
P0CGIO
RF: 37H
CH
P0CGIO
I/O mode of P0C
0
to P0C
3
0
1
Sets P0C
Sets P0C
0
0
to P0C
to P0C
3
3
in input mode
in output mode
P0DGIO
I/O mode of P0D
0
to P0D
3
0
1
Sets P0D
Sets P0D
0
0
to P0D
to P0D
3
3
in input mode
in output mode
Data Sheet U15002EJ1V1DS
40
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
3.11 Selecting Whether Key Matrix Is Used or Not (Port 0E, 1A)
By using the following register file, whether P0E and P1A are used for a key matrix can be selected in bit units.
3
0
2
1
0
Address
RF: 06H
After reset
0H
R/W
R/W
P1AKEY2 P1AKEY1 P1AKEY0
P1AKEY0
Selects whether P1A
0
is used for key matrix or not
not used for key matrix
used for key matrix
0
1
P1A
0
0
P1A
P1AKEY1
Selects whether P1A
1
is used for key matrix or not
not used for key matrix
used for key matrix
0
1
P1A
1
1
P1A
P1AKEY2
Selects whether P1A
2
is used for key matrix or not
not used for key matrix
used for key matrix
0
1
P1A
2
2
P1A
3
2
1
0
Address
After reset
0H
R/W
R/W
P0EKEY3 P0EKEY2 P0EKEY1 P0EKEY0
RF: 16H
P0EKEY0
Selects whether P0E
0
is used for key matrix or not
not used for key matrix
used for key matrix
0
1
P0E
0
0
P0E
P0EKEY1
Selects whether P0E
1
is used for key matrix or not
not used for key matrix
used for key matrix
0
1
P0E
1
1
P0E
P0EKEY2
Selects whether P0E
2
is used for key matrix or not
not used for key matrix
used for key matrix
0
1
P0E
2
2
P0E
P0EKEY3
Selects whether P0E
3
is used for key matrix or not
not used for key matrix
used for key matrix
0
1
P0E
3
3
P0E
Data Sheet U15002EJ1V1DS
41
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
3.12 Specifying Resistor Connection (Port 0E, 1A)
(1) Port 0E
If a key matrix is not used, whether or not a pull-up resistor is connected to port P0E can be specified in 1-
bit units by using the following registers of the register fileNote
.
3
2
1
0
Address
RF: 17H
After reset
0H
R/W
R/W
P0EBPU3 P0EBPU2 P0EBPU1 P0EBPU0
P0EBPU0
Connects pull-up resistor to P0E
0
1
2
3
0
1
Not connected
Connected
P0EBPU1
Connects pull-up resistor to P0E
Not connected
Connected
0
1
Connects pull-up resistor to P0E
P0EBPU2
Not connected
Connected
0
1
Connects pull-up resistor to P0E
P0EBPU3
Not connected
Connected
0
1
Note To disconnect the pull-up resistor in the output mode, clear the corresponding bit of the P0EBPU register.
Data Sheet U15002EJ1V1DS
42
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
(2) Port 1A
Whether a resistor is connected to each bit of port P1A when a key matrix is not used can be specified in 1-
bit units by using the following register fileNote
.
To connect a resistor, select whether a pull-down or pull-up resistor is to be connected, by using P1AHL
(address 05H) of the register file.
3
0
2
1
0
Address
RF: 07H
After reset
0H
R/W
R/W
P1ABPU2 P1ABPU1 P1ABPU0
P1ABPU0
Connects resistor to P1A0
Connects resistor to P1A1
Connects resistor to P1A2
Not connected
Connected
0
1
P1ABPU1
Not connected
Connected
0
1
P1ABPU2
0
1
Not connected
Connected
Note To disconnect the resistor in the output mode, clear the corresponding bit of the P1ABPU register.
Data Sheet U15002EJ1V1DS
43
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
3.13 Selecting Standby Mode Release Condition and Whether Pull-Up or Pull-Down Resistor
Is Connected (Port 1A)
The standby mode release condition and whether a pull-up or pull-down resistorNote is connected to P1A can be
specified in 1-bit units by using the following register file.
Note Specify whether a resistor is connected or not by using P1ABPU (address 07H) of the register file.
(1) When key matrix is used (P1AKEYn = 1)
3
0
2
1
0
Address
RF: 05H
After reset
0H
R/W
R/W
P1AHL2
P1AHL1
P1AHL0
P1AHL0
Connects pull-down/pull-up resistor to P1A
0
and
selects standby mode release condition
Resistor is connected (P1ABPU0 = 1) Resistor is not connected (P1ABPU0 = 0)
Pull-up resistor
Standby mode is released when a low level is input to P1A.
Pull-down resistor No resistor
Standby mode is released when a high level is input to P1A.
No resistor
0
1
P1AHL1
Connects pull-down/pull-up resistor to P1A
1
and
selects standby mode release condition
Resistor is connected (P1ABPU1 = 1) Resistor is not connected (P1ABPU1 = 0)
Pull-up resistor
Standby mode is released when a low level is input to P1A.
Pull-down resistor No resistor
Standby mode is released when a high level is input to P1A.
No resistor
0
1
P1AHL2
Connects pull-down/pull-up resistor to P1A
2
and
selects standby mode release condition
Resistor is connected (P1ABPU2 = 1) Resistor is not connected (P1ABPU2 = 0)
Pull-up resistor
Standby mode is released when a low level is input to P1A.
Pull-down resistor No resistor
Standby mode is released when a high level is input to P1A.
No resistor
0
1
Remark P1AKEY: Address 06H of register file
P1ABPU: Address 07H of register file
n = 0 to 2
Data Sheet U15002EJ1V1DS
44
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
(2) When key matrix is not used (P1AKEYn = 0)
3
0
2
1
0
Address
RF: 05H
After reset
0H
R/W
R/W
P1AHL2
P1AHL1
P1AHL0
P1AHL0
Connects pull-down/pull-up resistor to P1A
0
Resistor is connected (P1ABPU0 = 1) Resistor is not connected (P1ABPU0 = 0)
0
1
Pull-up resistor
No resistor
Pull-down resistor
P1AHL1
Connects pull-down/pull-up resistor to P1A
1
Resistor is connected (P1ABPU1 = 1) Resistor is not connected (P1ABPU1 = 0)
0
1
Pull-up resistor
No resistor
Pull-down resistor
P1AHL2
Connects pull-down/pull-up resistor to P1A
2
Resistor is connected (P1ABPU2 = 1) Resistor is not connected (P1ABPU2 = 0)
0
1
Pull-up resistor
No resistor
Pull-down resistor
Caution The standby mode is not released by P1A when a key matrix is not used.
Remark P1AKEY: Address 06H of register file
P1ABPU: Address 07H of register file
n = 0 to 2
Data Sheet U15002EJ1V1DS
45
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
3.14 Selecting Whether Key Matrix Is Used, Standby Mode Release Condition, and Whether
Pull-Up or Pull-Down Resistor Is Connected (Port 1B)
Whether a key matrix is used or not, whether a resistor is connected to P1B or not, whether a pull-up or pull-down
resistor is connected, and the standby mode release condition can be specified by using the following register file.
3
0
2
1
0
Address
RF: 15H
After reset
0H
R/W
R/W
P1BHL0 P1BKEY0 P1BPU0
P1BPU0
Connects resistor to P1B
0
Not connected
Connected
0
1
P1BKEY0
Selects whether P1B
0
is used for key matrix or not
0
1
P1B
P1B
0
not used for key matrix
used for key matrix
0
• When key matrix is used (P1BKEY0 = 1)
P1BHL0
Connects pull-down/pull-up resistor to P1B
0
and
selects standby mode release condition
Resistor is connected (P1BPU0 = 1) Resistor is not connected (P1BPU0 = 0)
0
1
Pull-up resistor
Standby mode is released when a low level is input to P1B.
Pull-down resistor No resistor
Standby mode is released when a high level is input to P1B.
No resistor
• When key matrix is not used (P1BKEY0 = 0)
P1BHL0
Connects pull-down/pull-up resistor to P1B
0
Resistor is connected (P1BPU0 = 1) Resistor is not connected (P1BPU0 = 0)
0
1
Pull-up resistor
No resistor
Pull-down resistor
Caution The standby mode is not released by P1B when a key matrix is not used.
Data Sheet U15002EJ1V1DS
46
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
4. CLOCK GENERATOR
4.1 Instruction Execution Time (CPU Clock) Selection
The µPD17246 is equipped with a clock oscillator that supplies clocks to the CPU and peripheral hardware.
Instruction execution time can be changed in two steps (normal mode and high-speed mode) without changing the
oscillation frequency.
To change the instruction execution time, change the mode of SYSCK (RF: address 02H) of the register file by
using the POKE instruction.
Note, that the mode is actually only changed when the instruction next to the POKE instruction has been executed.
Whenusingthehigh-speedmode,payattentiontothesupplyvoltage.(Referto14. ELECTRICALSPECIFICATIONS.)
After reset, the normal mode is set.
3
0
2
0
1
0
0
Address
RF: 02H
After reset
0H
R/W
R/W
SYSCK
SYSCK
Selects instruction execution time
0
1
Normal mode 32/f
X
(8
µ
s)
(4
High-speed mode 16/f
X
µs)
Values in parentheses apply to operation when the system clock f = 4 MHz.
X
Data Sheet U15002EJ1V1DS
47
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
5. 8-BIT TIMER AND REMOTE CONTROLLER CARRIER GENERATOR
The µPD17246 is equipped with an 8-bit timer, which is mainly used to generate the leader pulse of the remote
controller signal and to output codes.
5.1 Configuration of 8-Bit Timer (with Modulo Function)
Figure 5-1 shows the configuration of the 8-bit timer.
As shown in this figure, the 8-bit timer consists of an 8-bit counter (TMC), an 8-bit modulo register (TMM), a
comparator that compares the value of the timer with the value of the modulo register, and a selector that selects the
operation clock of the 8-bit timer.
To start/stop the 8-bit timer, and to reset the 8-bit counter, TMEN (address 33H, bit 3) and TMRES (address 33H,
bit 2) of the register file are used. To select the operation clock of the 8-bit timer, use TMCK1 (address 33H, bit 1)
and TMCK0 (address 33H, bit 0) of the register file.
The value of the 8-bit counter is read by using the GET instruction through the DBF (data buffer). No value can
be set to the 8-bit counter. A value is set to the modulo register by using the PUT instruction through DBF. The value
of the modulo register cannot be read.
When the value of the counter matches with that of the modulo register, an interrupt flag (IRQTM: address 3FH,
bit 0) of the register file is set.
TMC
Address
After reset
00H
R/W
R
7
7
6
6
5
4
3
2
1
1
0
0
8-bit counter
Peripheral register: 05H
TMM
Address
After reset
FFH
R/W
W
5
4
3
2
Peripheral register: 06H
8-bit modulo register
Caution Do not clear TMM to 0 (IRQTM is not set).
Data Sheet U15002EJ1V1DS
48
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
Figure 5-1. Configuration of 8-Bit Timer and Remote Controller Carrier Generator
Data buffer
Internal bus
8-bit timer
RF: 33H
TMEN TMRES TMCK1 TMCK0
8-bit modulo register
f
f
X
/32
/64
TMM
X
fX
/256
IRQTM
Comparator
R
S
Q
8-bit counter
TMC
Remote controller carrier generator
f
X
/2
8-bit counter
Comparator
f
X
SW
2f
X
RF: 11H
NRZBF
RF: 12H
NRZ
8-bit modulo register
NRZLTMM
RF: 12H
REMEN
8-bit counter
Comparator
REM
8-bit modulo register
NRZHTMM
Remark TMM, TMC, NRZLTMM, and NRZHTMM are peripheral registers.
Data Sheet U15002EJ1V1DS
49
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
5.2 Function of 8-Bit Timer (with Modulo Function)
3
2
1
0
Address
RF: 33H
After reset
8HNote 1
R/W
TMEN
TMRES
TMCK1
TMCK0
R/WNote 2
TMCK1
0
TMCK0
8-bit timer clock source selection
Count clock: f /32
(measurable time range: 8 s to 2.048 ms,
X
0
1
µ
µ
X
resolution: 8 s (error: +8
Count clock: f /64
(measurable time range: 16
µs))
µ
s to 4.096 ms,
0
resolution: 16
µ
s (error: +16
µ
s))
Count clock: f
X/256
(measurable time range: 64
resolution: 64 s (error: +64
µ
s to 16.384 ms,
s))
1
1
0
1
µ
µ
Remote controller carrier generator output
Values in parentheses apply to operation when system clock f
X
= 4 MHz.
TMRES
8-bit timer reset flag
Data read out is always "0"
Resets 8-bit counter and IRQTM
0
1
TMEN
8-bit timer count enable flag
0
1
Stops 8-bit timer count operation
Enables 8-bit timer count operation (falling edge)
Notes 1. When the STOP mode is released, bit 3 must be set.
2. Bit 2 is a write-only bit.
Caution If the system clock is changed while the timer is counting, an error occurs in the timer as follows
(when system clock fX = 4 MHz):
•
•
High-speed mode 16/fX → Normal mode 32/fX ... (Error due to resolution of set timer) +1.5 µs
Normal mode 32/fX → High-speed mode 16/fX ... (Error due to resolution of set timer) –1.5 µs
Data Sheet U15002EJ1V1DS
50
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
5.3 Carrier Generator for Remote Controller
µPD17246 is provided with a carrier generator for the remote controller.
The remote controller carrier generator consists of an 8-bit counter, NRZ high-level timer modulo register
(NRZHTMM), and NRZ low-level timer modulo register (NRZLTMM). The high-level and low-level periods are set in
the corresponding modulo registers through the DBF to determine the carrier duty factor and carrier frequency.
As a clock input to the 8-bit counter, fX/2, fX, or 2fX can be selected by using REMCK0 and REMCK1 (address 13H,
bits 0 and 1) of the register file (this clock for carrier generation is RfX). When RfX is oscillated by a 4 MHz resonator,
therefore, the input clock is 2 MHz (fX/2), 4 MHz (fX), or 8 MHz (2fX).
The NRZ high-level output timer modulo register is called NRZHTMM, and the NRZ low-level timer modulo register
is called NRZLTMM. Data is written to these registers by the PUT instruction. The contents in these register are read
by the GET instruction.
Whether the REM pin outputs a carrier or a high level is selected by REMEN (address 12H, bit 1) of the register
file. Be sure to clear this bit to 0 to output a carrier.
NRZLTMM
7
6
5
4
3
2
1
1
0
0
Address
After reset
Undefined
R/W
R/W
8-bit modulo register
Peripheral register: 03H
NRZHTMM
7
6
5
4
3
2
Address
After reset
Undefined
R/W
R/W
8-bit modulo register
Peripheral register: 03H
3
0
2
1
0
Address
RF: 13H
After reset
0H
R/W
R/W
0
REMCK1 REMCK0
Clock for carrier generation (Rf )
X
REMCK1 REMCK0
0
0
1
1
0
1
0
1
RfX
RfX
RfX
= f
= f
X
X
/2 (when f
(when f = 4 MHz, Rfx = 4 MHz)
Note (when f
= 4 MHz, Rf = 8 MHz)
X
= 4 MHz, Rf
X
= 2 MHz)
X
= 2f
X
X
X
Note Rf
X
= 2f
X
can be selected only when f = 3.5 to 4.5 MHz.
X
Data Sheet U15002EJ1V1DS
51
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
5.3.1
Remote controller signal output control
The REM pin, which outputs the carrier, is controlled by bits NRZ and NRZBF of the register file and timer 0. While
the NRZ contents are “1”, the clock generated by the remote controller carrier generator is output to the REM pin;
while the NRZ contents are “0”, the REM pin outputs a low level. The NRZBF contents are automatically transferred
to NRZ by the interrupt signal generated by timer 0. If data is set in NRZBF in advance, the REM pin status changes
in synchronization with the timer 0 counting operation.
If the interrupt signal is generated from timer 0 with the REM pin at the high level (i.e. NRZ is “1”) and the carrier
clock at the high level, the REM pin output does not accord with the updated contents of NRZ until the carrier clock
goes low. This processing is useful for holding the high level pulse width from the output carrier constant (refer to
the figure below).
When the contents of NRZ are “0”, the remote controller carrier generator stops. However, if the clock for timer
0 is output from the remote controller carrier generator, the clock continues to operate, even when the NRZ contents
become “0”.
An actual example showing a remote controller signal output to the REM pin is given below.
When REMEN (address 12H, bit 1) of register file is 0 (carrier output)
NRZ
REM
MAX. 500 ns (delay)Note
(f = 4 MHz, Rf = f /2)
REM pin does not go low
until carrier goes low
even if NRZ becomes 0
X
X
X
Note Value when (TMCK1, TMCK0) ≠ (1, 1).
When (TMCK1, TMCK0) = (1, 1), the value differs depending on how NRZ is manipulated. If NRZ is set
by an instruction, the width of the first high-level pulse may be shortened. If NRZ is set by data transferred
from NRZBF, the high-level pulse is delayed by the low-level pulse of the carrier clock.
Data Sheet U15002EJ1V1DS
52
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
When REMEN (address 12H, bit 1) of register file is 1 (carrier not output)
NRZ
REM
3
0
2
0
1
0
Address
RF: 12H
After reset
0H
R/W
R/W
REMEN
NRZ
REMEN
NRZ
NRZ data
Outputs low level to REM pin
Outputs a carrier to REM pin
Outputs low level to REM pin
Outputs high level to REM pin
0
0
1
1
0
1
0
1
3
0
2
0
1
0
0
Address
RF: 11H
After reset
0H
R/W
R/W
NRZBF
NRZBF
NRZ data output next
0
1
NRZ buffer bit. Transferred to NRZ by interrupt
signal of timer 0.
Data Sheet U15002EJ1V1DS
53
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
Setting carrier frequency and duty factor
Where the system clock frequency is fX, carrier frequency is fC, and carrier generation clock is RfX:
•
•
•
When RfX = fX/2:
When RfX = fX:
When RfX = 2fX:
(division ratio) = fX/(2 × fC)
(division ratio) = fX/fC
(division ratio) = 2fX/fC
is divided into m:n and is set in the modulo registers as follows:
High-level period set value= { × m/(m + n)} – 1
Low-level period set value = { × n/(m + n)} – 1
Example Where f
C
= 38 kHz, duty factor (high-level period) = 1/3, f
X
= 4 MHz, and Rf
X
= 2f :
X
= 2 × 4 MHz/38 kHz = 210.5
m:n = 1:2
From the above, the value of the modulo register is:
.
High-level period = 69
.
.
Low-level period = 139
.
Therefore, the carrier frequency is 38.10 kHz.
Table 5-1. Carrier Frequency List
(1) Where f
X
= 4 MHz and Rf
X
= f /2
X
Set Value
NRZHTMM
tH (µs)
tL (µs)
1/fC (µs)
fC (kHz)
Duty
NRZLTMM
00H
00H
01H
04H
09H
0FH
0FH
11H
11H
19H
3FH
7FH
FFH
0.5
1.0
0.5
1.5
1.0
2.5
1000
400
200
100
60.6
40.0
38.5
37.7
25.0
15.6
7.8
1/2
2/5
1/2
1/2
1/2
1/3
1/3
1/3
1/3
1/2
1/2
1/2
02H
04H
2.5
2.5
5.0
09H
5.0
5.0
10.0
16.5
25.0
26.0
26.5
40.0
64.0
128.0
256.0
10H
8.0
8.5
21H
8.0
17.0
17.0
17.5
27.0
32.0
64.0
128.0
21H
9.0
22H
9.0
35H
13.0
32.0
64.0
128.0
3FH
7FH
FFH
3.9
Data Sheet U15002EJ1V1DS
54
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
(2) Where fX = 4 MHz, RfX = fX (original oscillation)
Set Value
NRZHTMM
tH (µs)
tL (µs)
1/fC (µs)
fC (kHz)
Duty
NRZLTMM
00H
00H
01H
04H
09H
0FH
0FH
11H
11H
19H
3FH
7FH
FFH
0.25
0.5
0.25
0.75
1.25
2.5
0.5
1.25
2.5
2000
800
400
200
121
80
1/2
2/5
1/2
1/2
1/2
1/3
1/3
1/3
1/3
1/2
1/2
1/2
02H
04H
1.25
2.5
09H
5.0
10H
4.0
4.25
8.5
8.25
12.5
13.0
13.25
20.0
32.0
64.0
128.0
21H
4.0
21H
4.5
8.5
76.9
75.47
50
22H
4.5
8.75
13.5
16.0
32.0
64.0
35H
6.5
3FH
16.0
32.0
64.0
31.25
15.6
7.8
7FH
FFH
(3) Where fX = 4 MHz, RfX = 2fX
Set Value
NRZHTMM
tH (µs)
tL (µs)
1/fC (µs)
fC (kHz)
Duty
NRZLTMM
00H
00H
07H
13H
27H
41H
41H
45H
45H
69H
C7H
FFH
0.125
1.0
0.125
1.5
0.25
2.5
4,000
400
200
100
60.6
40
1/2
2/5
1/2
1/2
1/2
1/3
1/3
1/3
1/3
1/2
1/2
0BH
13H
2.5
2.5
5.0
27H
5.0
5.0
10
41H
8.25
8.25
8.75
8.75
13.25
25.0
32.0
8.25
16.75
17.25
17.5
26.75
25.0
32.0
16.5
25
85H
89H
26.0
26.25
40.0
50.0
64.0
38.5
38.10
25
8BH
D5H
C7H
FFH
20
15.6
tH
tL
REM
(fC)
1/fC
Data Sheet U15002EJ1V1DS
55
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
5.3.2
Countermeasures against noise during transmission (carrier output)
When a signal is transmitted from the transmitter of a remote controller, a peak current of 0.5 to 1 A may flow through
the infrared LED. Since two batteries are usually used as the power source of the transmitter, several Ω of equivalent
resistance (r) exists in the power source as shown in Figure 5-2. This resistance increases to 10 to 20 Ω if the supply
voltage drops to 2 V. While the carrier is being output from the REM pin (while the infrared LED lights), therefore,
a high-frequency noise may be generated on the power lines due to the voltage fluctuation that may take place
especially during switching.
To minimize the influence on the microcontroller of this high-frequency noise, take the following measures.
<1> Separate the power lines of the microcontroller from the power lines of the infrared LED with the terminals
of the batteries at the center. Use thick power lines and keep the wiring short.
<2> Locate the resonator as close as possible to the microcontroller and shield it with GND lines (as indicated
by the shaded portion in the figure below).
<3> Locate the capacitor for stabilization of the power supply closely to the power lines of the microcontroller.
Also, use a capacitor to eliminate high-frequency noise.
<4> To prevent data from changing, do not execute data read/write processing such as key scan, an interrupt
that requires a stack, or the CALL/RET instruction, while the carrier is being output.
<5> To improve the reliability in case of program hang-up, use the watchdog timer.
Figure 5-2. Example of Countermeasures Against Noise
0.5 to 1 A
Infrared LED
REM
VDD
Microcontroller
r
+
–
Batteries
VSS
Data Sheet U15002EJ1V1DS
56
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
6. BASIC INTERVAL TIMER/WATCHDOG TIMER
The basic interval timer has a function to generate the interval timer interrupt signal and watchdog timer reset signal.
6.1 Source Clock for Basic Interval Timer
The system clock (fX) is divided to generate the source clock for the basic interval timer. The input clock frequency
for the basic interval timer is fX/27. When the CPU is set in the STOP mode, the basic interval timer also stops.
6.2 Controlling Basic Interval Timer
The basic interval timer is controlled by the bits in the register file. That is, the basic interval timer is reset by
BTMRES. The frequency for the interrupt signal, output by the basic interval timer, is selected by BTMMD, and the
watchdog timer is reset by WDTRES.
Figure 6-1. Basic Interval Timer Configuration
f
X
X
/218
/220
f
1/27
divider
1/211
divider
1/2
divider
1/2
divider
1/2
divider
System
clock f
X
Reset signal output
BTMRES
WDTRES
BTMCK
IRQBTM
Data Sheet U15002EJ1V1DS
57
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
3
2
1
0
0
Address
RF: 03H
After reset
0H
R/W
WDTRES BTMCK
BTMRES
R/WNote
BTMRES
Basic interval timer reset
0
1
Data read out is always "0"
Writing "1" resets basic interval timer
BTMCK
Basic interval timer mode selection
0
1
Generates interrupt signal IRQBTM every f
Generates interrupt signal IRQBTM every f
X
X
/220
/218
WDTRES
Watchdog timer reset
0
1
Data read out is always "0"
Writing "1" resets watchdog timer (f
/221 counter)
X
Note Bits 1 and 3 are write-only bits.
Data Sheet U15002EJ1V1DS
58
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
6.3 Operation Timing for Watchdog Timer
The basic interval timer can be used as a watchdog timer.
Unless the watchdog timer is reset within a fixed timeNote, it is judged that “the program has hung up”, and the
µPD17246 is reset. It is therefore necessary to reset the watchdog timer via programming within the fixed time.
The watchdog timer can be reset by setting WDTRES to 1.
Note Fixed time: Approx. 340 ms (at 4 MHz)
Caution The watchdog timer cannot be reset in the shaded range in Figure 6-2. Therefore, set WDTRES
before both the fX/221 and fX/220 signals go high.
Figure 6-2. Watchdog Timer Operation Timing
fX
/218
fX
fX
fX
/219
/220
/221
INTBTM (f
INTBTM (f
X
X
/220)
/218)
Reset signal
Reset signal goes low
if WDTRES is not set
Watchdog timer
reset signal
WDTRES
Setting WDTRES at
this timing is invalid
Data Sheet U15002EJ1V1DS
59
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
7. RAM RETENTION DETECTOR
7.1 RAM Retention Flag
The RAM retention flag (bit 0 of the register file at address 21H) indicates whether the supply voltage has dropped
below the level at which the contents of the RAM are lost while the battery is being exchanged or when the battery
voltage has dropped.
This flag is at bit 3 of control register 0 (P3).
It is cleared to 0 if the supply voltage drops below the RAM retention detection voltage (approx. 1.4 V TYP.). If
this flag is 0, it can be judged that the RAM contents have been lost or that power has just been applied. This flag
can be used to initialize the RAM via software. After initializing the RAM and writing the necessary data to it, set this
RAM retention flag to “1” by software. At this time, 1 means that data has been set to the RAM.
Figure 7-1. Supply Voltage Transition and Detection Voltage
VDD
VPOC
VID
POC detection voltage
VPOC = 1.85 V (TYP.)
(A)
(3)
RAM retention detection voltage
VID = 1.4 V (TYP.)
(B)
0 V
t
(1)
(2)
(4)
(5)
(6)
RAM retention flag
Set to 1
Flag content is read.
Flag content is read.
(1) If the supply voltage rises after the battery has been set, and exceeds VPOC (POC detection voltage), reset
is cleared. Because the supply voltage rises from 0 V, which is lower than VID (RAM retention detection
voltage), the RAM retention flag remains in the initial status 0.
(2) The supply voltage has now risen to the level at which the device can operate. Write the necessary data to
the RAM and set the RAM retention flag to 1.
(3) The device is reset if the supply voltage drops below VPOC. At point (A) in the above figure, the RAM retention
flag remains 1 because the supply voltage is higher than VID at this point.
(4) If the RAM retention flag is checked by software after reset has been cleared, it is 1. This means that the
contents of the RAM have not been lost. It is therefore not necessary to initialize the RAM by software.
(5) The device is reset if the supply voltage drops below VPOC. At point (B) in the figure, the voltage is lower than
VID. Consequently, the RAM retention flag is cleared to 0.
(6) If the RAM retention flag is checked by software after reset has been cleared, it is 0. This means that the
contents of the RAM may have been lost. If this happens, initialize the RAM by software.
Data Sheet U15002EJ1V1DS
60
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
3
0
2
0
1
0
0
Address
RF: 21H
After reset
R/W
RAMFLAG
UndefinedNote R/W
RAMFLAG
RAM retention flag
RAM data may be undefined.
RAM data are retained.
0
1
Note RAMFLAG is “0” when VDD is about 1.4 V or less, and “undefined” when VDD is about 1.4 V or more.
Data Sheet U15002EJ1V1DS
61
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
8. INTERRUPT FUNCTIONS
8.1 Interrupt Sources
µPD17246 is provided with three interrupt sources.
When an interrupt has been acknowledged, the program execution automatically branches to a predetermined
address, which is called a vector address. A vector address is assigned to each interrupt source, as shown in Table
8-1.
Table 8-1. Vector Address
Priority
Interrupt Source
Ext/Int
Internal
External
Internal
Vector Address
0004H
1
2
3
8-bit timer
INT pin rising and falling edges
Basic interval timer
0003H
0002H
Remark 0001H is normal address
When more than one interrupt request is issued at the same time, the interrupts are acknowledged in sequence,
starting from the one with the highest priority.
Whether an interrupt is enabled or disabled is specified by the EI or DI instruction. The basic condition under which
an interrupt is acknowledged is that the interrupt is enabled by the EI instruction. While the DI instruction is executed,
or while an interrupt is acknowledged, the interrupt is disabled.
To enable acknowledgement of an interrupt after the interrupt has been processed, the EI instruction must be
executed before the RETI instruction. Acknowledging the interrupt is enabled by the EI instruction after the instruction
next to the EI instruction has been executed. Therefore, no interrupt can be acknowledged between the EI and RETI
instructions.
Caution In interrupt processing, only the BCD, CMP, CY, Z, IXE flags are automatically saved to the stack
by the hardware, to a maximum of three levels. Also, within the interrupt processing contents,
when peripheral hardware (timer, A/D converter, etc. ) is accessed, the DBF and WR contents
are not saved by the hardware. Accordingly, it is recommended that at the beginning of interrupt
processing, DBF and WR be saved by software to RAM, and immediately before finishing
interrupt processing, the saved contents be returned to their original location.
Data Sheet U15002EJ1V1DS
62
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
8.2 Hardware of Interrupt Controller
This section describes the flags of the interrupt controller.
(1) Interrupt request flag and interrupt enable flag
The interrupt request flag (IRQ×××) is set to 1 when an interrupt request is generated, and is automatically
cleared to 0 when the interrupt processing is executed.
An interrupt enable flag (IP×××) is provided for each interrupt request flag. When the IP××× flag is 1, the
interrupt is enabled; when it is 0, the interrupt is disabled.
(2) EI/DI instruction
Whether an acknowledged interrupt is executed or not is specified by the EI or DI instruction.
When the EI instruction is executed, INTE (interrupt enable flag), which enables the interrupt, is set to 1. The
INTE flag is not registered on the register file. Consequently, the status of this flag cannot be checked by
an instruction.
The DI flag clears the INTE flag to 0 to disable all the interrupts.
The INTE flag is also cleared to 0 at reset, disabling all the interrupts.
Table 8-2. Interrupt Request Flags and Interrupt Enable Flag
Interrupt
Signal Setting Interrupt Request Flag
Interrupt
Request Flag
Enable Flag
IRQTM
IRQ
Reset by 8-bit timer.
IPTM
Set when edge of INT pin input signal is detected
Reset by basic interval timer.
IP
IRQBTM
IPBTM
8.2.1
This flag reads the INT pin status.
When a high level is input to the INT pin, this flag is set to 1; when a low level is input, the flag is reset to 0.
INT
3
0
2
0
1
0
0
Address
RF: 0FH
After reset
Undefined
R/W
R
INT
INT
0
INT pin level detection
INT pin: Low level
INT pin: High level
1
Data Sheet U15002EJ1V1DS
63
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
8.2.2
IEG
This pin selects the interrupt edge to be detected on the INT pin.
When this flag is 0, the interrupt is detected at the rising edge; when it is 1, the interrupt is detected at the falling
edge.
8.2.3
INTSEL
This flag selects whether pin 3 is used as the INT pin or P1B0 pin. When INTSEL is cleared to 0, pin 3 functions
as the P1B0 pin; when it is set to 1, the pin functions as the INT pin.
After reset, the P1B0 pin is selected.
3
0
2
0
1
0
Address
RF: 1FH
After reset
0H
R/W
R/W
INTSEL
IEG
IEG
INT pin interrupt detection edge selection
Rising edge of INT pin
Falling edge of INT pin
0
1
INTSEL
Selection of pin 3 function
0
1
As P1B
0
pin
As INT pin
8.2.4
Interrupt enable flag
This flag enables each interrupt source. When this flag is 1, the corresponding interrupt is enabled; when it is 0,
the interrupt is disabled.
3
0
2
1
0
Address
RF: 2FH
After reset
0H
R/W
R/W
IPBTM
IP
IPTM
IPTM
8-bit timer interrupt enable flag
0
1
Disables interrupt acknowledgement by 8-bit timer
Enables interrupt acknowledgement by 8-bit timer
IP
0
INT pin interrupt enable flag
Disables interrupt acknowledgement by INT pin input
Enables interrupt acknowledgement by INT pin input
1
IPBTM
Basic interval timer interrupt enable flag
0
1
Disables interrupt acknowledgement by basic interval timer
Enables interrupt acknowledgement by basic interval timer
Data Sheet U15002EJ1V1DS
64
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
8.2.5
IRQ
This is an interrupt request flag that indicates the interrupt request status.
When an interrupt request is generated, this flag is set to 1. When the interrupt has been acknowledged, the
interrupt request flag is reset to 0.
The interrupt request flag can be read or written by the program. Therefore, when it is set to 1, an interrupt can
be generated by the software. By writing 0 to the flag, the interrupt pending status can be canceled.
3
0
2
0
1
0
0
Address
RF: 3DH
After reset
0H
R/W
R/W
IRQBTM
IRQBTM
Basic interval timer interrupt request flag
Interrupt request has not been made.
0
1
Basic interval timer interrupt request has been made.
3
0
2
0
1
0
0
Address
RF: 3EH
After reset
0H
R/W
R/W
IRQ
IRQ
0
INT pin interrupt request flag
Interrupt request has not been made.
1
Interrupt request has been made at rising edge or falling
edge of INT input.
3
0
2
0
1
0
0
Address
RF: 3FH
After reset
1HNote
R/W
R/W
IRQTM
IRQTM
8-bit timer interrupt request flag
Interrupt request has not been made.
0
1
8-bit timer interrupt request has been made.
Note It is also set to 1H after the STOP mode is released.
Data Sheet U15002EJ1V1DS
65
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
8.3 Interrupt Sequence
If the IRQ×× flag is set to 1 when the IP×× flag is “1”, interrupt processing is started after the instruction cycle of
the instruction executed when the IRQ×× flag was set has ended. Since the MOVT instruction, EI instruction, and
the instruction that matches the condition to skip use two instruction cycles, the interrupt enabled while this instruction
is executed is processed after the second instruction cycle is over.
If the IP×× flag is “0”, the interrupt processing is not performed even if the IRQ×× flag is set, until the IP×× flag is
set.
If two or more interrupts are enabled simultaneously, the interrupts are processed starting from the one with the
highest priority. The interrupt with the lower priority is held pending until the processing of the interrupt with the higher
priority is finished.
8.3.1
Operations when interrupt is acknowledged
When an interrupt has been acknowledged, the CPU performs processing in the following sequence:
Clears IRQ××× corresponding to
INTE flag and acknowledged interrupt
Decrements value of stack pointer by 1
(SP − 1)
Saves contents of program counter to
stack addressed by stack pointer
Loads vector address to program counter
Save contents of PSWORD to interrupt stack register
One instruction cycle is required to perform the above processing.
Data Sheet U15002EJ1V1DS
66
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
8.3.2
Returning from interrupt processing routine
To return from an interrupt processing routine, use the RETI instruction.
The following processing is then executed within an instruction cycle.
Loads contents of stack addressed by
stack pointer to program counter
Loads contents of interrupt
stack register to PSWORD
Increments value of stack pointer by 1
To enable an interrupt after the processing of an interrupt has finished, the EI instruction must be executed
immediately before the RETI instruction.
Interrupt acknowledgement is enabled by the EI instruction after the instruction next to the EI instruction
has been executed. Therefore, the interrupt is not acknowledged between the EI and RETI instructions.
Data Sheet U15002EJ1V1DS
67
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
9. STANDBY FUNCTIONS
The µPD17246 is provided with HALT and STOP modes as standby functions.
By using the standby function, current consumption can be reduced.
In the HALT mode, the program is not executed, but the system clock fX is not stopped. This mode is maintained,
until the HALT mode release condition is satisfied.
In the STOP mode, the system clock is stopped and program execution is stopped. This mode is maintained, until
the STOP mode release condition is satisfied.
The HALT mode is set, when the HALT instruction has been executed. The STOP mode is set, when the STOP
instruction has been executed.
9.1 HALT Mode
In this mode, program execution is temporarily stopped, with the main clock continuing oscillation, to reduce current
consumption.
Use the HALT instruction to set the HALT mode.
The HALT mode release condition can be specified by the operand for the HALT instruction, as shown in Table
9-1.
After the HALT mode has been released, the operation is performed as shown in Table 9-2 and Figure 9-1.
Caution Do not execute an instruction that clears the interrupt request flag (IRQ×××) for which the
interrupt enable flag (IP×××) is set immediately before the HALT 8H instruction; otherwise, the
HALT mode may not be set.
Table 9-1. HALT Mode Releasing Conditions
Operand Value
0010B (02H)
1000B (08H)
Release Conditions
When interrupt request (IRQTM) occurs for 8-bit timer
<1> When interrupt request (IRQTM, IRQBTM, or IRQ), whose interrupt enable flag (IPTM,
IPBTM, or IP) is set, occurs
<2> When any of P0A0 to P0A3 pins goes low
<3> When P0B0 to P0B3, P0C0 to P0C3, and P0D0 to P0D3 are used as input pins and any of these
goes low
<4> If P0E0 to P0E3 are used as input pins when a key matrix is used and if any of these pins goes
low
<5> If P1A0 to P1A2 and P1B0 are used as input pins when a key matrix is used and if the level of any
Note
of these pins is the set clear level
Other than above
Setting prohibited
Note Set the clear level by using bits 0 to 2 (P1AHL0 to P1AHL2) of the register file at address 05H, and bit 2
(P1BHL0) at address 15H.
Data Sheet U15002EJ1V1DS
68
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
Table 9-2. Operations After HALT Mode Release
(a) HALT 08H
HALT Mode Released by:
Interrupt Status
Don’t care
Interrupt Enable Flag
Don’t care
Operations After HALT Mode Release
Instruction next to HALT is executed
When release condition of P0A0
to P0A3, P0B
P0C , P0D to P0D
P1A to P1A , P1B
0
to P0B
, P0E
is satisfied
3
, P0C
0
to
3
0
3
0
to P0E ,
3
0
2
0
When release condition is
satisfied by interrupt request
DI
EI
Disabled
Enabled
Disabled
Enabled
Standby mode is not released
Instruction next to HALT is executed
Standby mode is not released
Branches to interrupt vector address
(b) HALT 02H
HALT Mode Released by:
8-bit timer
Interrupt Status
DI
Interrupt Enable Flag
Disabled
Operations After HALT Mode Release
Instructions are executed from the
instruction next to the HALT instruction.
Enabled
EI
Disabled
Enabled
Branches to interrupt vector address
9.2 HALT Instruction Execution Conditions
The HALT instruction can be executed under special conditions, as shown in Table 9-3, to prevent the program
from hanging up.
If the conditions in Table 9-3 are not satisfied, the HALT instruction is treated as a NOP instruction.
Table 9-3. HALT Instruction Execution Conditions
Operand Value
0010B (02H)
1000B (08H)
Execution Conditions
When all interrupt request flags (IRQTM) of 8-bit timer are reset
<1> When interrupt request flag (IRQTH, IRQBTM, or IRQ) is reset, corresponding to interrupt whose
interrupt enable flag (IPTM, IPBTM, or IP) is set
<2> When high level is input to all P0A0 to P0A3 pins
<3> When P0B0 to P0B3, P0C0 to P0C3, and P0D0 to P0D3 are used as input pins, a high level must
be input to all the pins.
<4> A high level must be input to all the pins if P0E0 to P0E3 are used as input pins when a key
matrix is used.
Note
<5> A level reverse to the set clear level
must be input to all the pins if P1A0 to P1A2 and P1B0
are used as input pins when a key matrix is used (for example, if the clear level is high, the
execution condition is low-level input).
Other than above
Setting prohibited
Note Set the clear level by using bits 0 to 2 (P1AHL0 to P1AHL2) of the register file at address 05H, and bit 2
(P1BHL0) at address 15H.
Data Sheet U15002EJ1V1DS
69
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
9.3 STOP Mode
In the STOP mode, the system clock (fX) oscillation is stopped and the program execution is stopped to minimize
current consumption.
To set the STOP mode, use the STOP instruction.
The STOP mode release condition can be specified by the STOP instruction operand, as shown in Table 9-4.
After the STOP mode has released, the µPD17246 performs the following.
<1> Resets IRQTM.
<2> Starts the basic interval timer and watchdog timer (does not reset).
<3> Resets and starts the 8-bit timer.
<4> Executes the instruction next to [STOP 8H] when the current value of the 8-bit counter matches the value
of the modulo register (IRQTM is set).
The µPD17246 oscillator is stopped when the STOP instruction has been executed (i.e., in the STOP mode).
Oscillation is not resumed until the STOP mode is released. After the STOP mode has been released, the HALT mode
is set. Set the time required to release the HALT mode by using the timer with modulo function.
The time that elapses from when the STOP mode has been released by occurrence of an interrupt until an operation
mode is set is shown in the following table.
Caution Do not execute an instruction that clears the interrupt request flag (IRQ×××) for which the
interrupt enable flag (IP×××) is set immediately before the STOP 8H instruction; otherwise, the
STOP mode may not be set.
8-Bit Modulo Register Set Value
(TMM)
Time Required to Set Operation Mode
After STOP Mode Release
At 4 MHz
40H
FFH
4.160 ms (64 µs × 65)
16.384 ms (64 µs × 256)
Caution To set the time required for an operation mode to be set after the STOP mode has been released,
make sure that sufficient time is allowed for oscillation to stabilize.
Remark Set the 8-bit modulo timer before executing STOP instruction.
Table 9-4. STOP Mode Release Conditions
Operand Value
1000B (08H)
Release Conditions
<1> When any of P0A0 to P0A3 pins goes low
<2> When P0B0 to P0B3, P0C0 to P0C3, and P0D0 to P0D3 are used as input pins and any of these
goes low
<3> If the interrupt request (IRQ) of an interrupt for which the INT pin interrupt enable flag (IP) is set
is generated at the rising or falling edge of the INT pin
<4> If P0E0 to P0E3 are used as input pins when a key matrix is used and if any of these pins goes
low
<5> If P1A0 to P1A2 and P1B0 are used as input pins when a key matrix is used and if the level of any
Note
of these pins is the set clear level
Other than above
Setting prohibited
Note Set the clear level by using bits 0 to 2 (P1AHL0 to P1AHL2) of the register file at address 05H, and bit 2
(P1BHL0) at address 15H.
Data Sheet U15002EJ1V1DS
70
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
9.4 STOP Instruction Execution Conditions
The STOP instruction can be executed under special conditions, as shown in Table 9-5, to prevent the program
from hanging up.
If the conditions in Table 9-5 are not satisfied, the STOP instruction is treated as an NOP instruction.
Table 9-5. STOP Instruction Execution Conditions
Operand Value
1000B (08H)
Execution Conditions
<1> High level input for all P0A0 to P0A3 pins
<2> When P0B0 to P0B3, P0C0 to P0C3, and P0D0 to P0D3 are used as input pins and all pins
are high
<3> If the INT pin interrupt request flag (IRQ) for an interrupt for which the INT pin interrupt
enable flag (IP) is set is reset
<4> A high level must be input to all the pins if P0E0 to P0E3 are used as input pins when a
key matrix is used.
Note
<5> A level reverse to the set clear level
must be input to all the pins if P1A0 to P1A2 and
P1B0 are used as input pins when a key matrix is used (for example, if the clear level is
high, the execution condition is low-level input).
Other than above
Setting prohibited
Note Set the clear level by using bits 0 to 2 (P1AHL0 to P1AHL2) of the register file at address 05H, and bit 2
(P1BHL0) at address 15H.
Data Sheet U15002EJ1V1DS
71
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
9.5 Releasing Standby Mode
The operations for releasing the STOP and HALT modes are as shown in Figure 9-1.
Figure 9-1. Operations After Standby Mode Release
(a) Releasing STOP mode by interrupt
Wait
(time set by TMM)
STOP
instruction
Standby
release signal
Operation
mode
Operation
mode
STOP mode
HALT mode
Oscillation
Oscillation stops
Oscillation
Clock
(b) Releasing HALT mode by interrupt
HALT
instruction
Standby
release signal
Operation
mode
Operation
mode
HALT mode
Oscillation
Clock
Remark The dotted line indicates the operation to be performed when the interrupt request releasing the standby
mode has been acknowledged.
Data Sheet U15002EJ1V1DS
72
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
10. RESET
10.1 Reset by Reset Signal Input
When a low-level signal of more than 10 µs is input to the RESET pin, the µPD17246 is reset.
When the system is reset, the oscillator remains in the HALT mode and then enters an operation mode, in the same
way as when the STOP mode is released. The wait time after the reset signal has been canceled is 16.384 ms (fX
= 4 MHz).
On power application, input the reset signal at least once because the internal circuitry operations are not stable.
When µPD17246 is reset, the following initialization takes place.
(1) Program counter is reset to 0.
(2) Flags in the register file are initialized to their default values (for the default values, refer to Figure 12-1
Register Files).
(3) The default value (0320H) is written to the data buffer (DBF).
(4) The hardware peripherals are initialized.
(5) The system clock (fX) stops oscillation.
When the RESET pin is made high, the system clock starts oscillating, and the program execution starts from
address 0 about 16 ms (at 4 MHz) later.
Figure 10-1. Reset Operation by RESET Input
Wait
(about 16 ms at 4 MHz)
Starts from address 0H
RESET
Operation mode
or standby mode
HALT mode
Operation mode
Oscillation stops
10.2 Reset by Watchdog Timer (with RESET Pin Internally Pulled Down)
When the watchdog timer operates during program execution, the RESET pin is internally pulled down, and the
program counter is reset to 0 (normally, the RESET pin is pulled up).
If the watchdog timer is not reset for a fixed period of time, the program can be restarted from address 0H.
Program so that the watchdog timer is reset at intervals of within 340 ms (at fX = 4 MHz) (set the WDTRES flag).
Data Sheet U15002EJ1V1DS
73
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
10.3 Reset by Stack Pointer (with RESET Pin Internally Pulled Down)
When the value of the stack pointer reaches 6H or 7H during program execution, the RESET pin is internally pulled
down, and the program counter is reset to 0 (normally, the RESET pin is pulled up).
Therefore, if an interrupt or CALL instruction is executed when the value of the stack pointer is 0 (stack underflow)
or if the stack level exceeds 6 as a result of execution of the RET instruction because the correspondence between
the CALL and RET instructions is not established (stack overflow), the program can be restarted from address 0H.
Table 10-1. Status of Each Hardware After Reset
Hardware
RESET Input in
Standby Mode
RESET Input
During Operation
Program counter (PC)
Ports
0000H
0000H
Input
Input/output
Input
0
Output latch
0
Data memory (RAM)
General-purpose data memory
(Except DBF, port register)
Retains previous
status
Undefined
DBF
0320H
0
0320H
0
System register (SYSREG)
WR
Retains previous
status
Undefined
Control registers
8-bit timer
Refer to Figure 12-1 Register Files
Counter (TMC)
00H
FFH
00H
Modulo register (TMM)
FFH
Remote controller carrier
generator
NRZ high-level timer modulo register (NRZHTMM) Retains previous
Undefined
status
NRZ low-level timer modulo register (NRZLTMM)
Basic interval timer/watchdog timer counter
00H
00H
Data Sheet U15002EJ1V1DS
74
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
11. LOW-VOLTAGE DETECTOR (WITH RESET PIN INTERNALLY PULLED DOWN)
The RESET pin is internally pulled down for initialization (reset) to prevent program hang-up that may take place
when the batteries are replaced, if the low-voltage detector detects a low voltage.
A drop in the supply voltage is detected if the status in which VDD is about 1.7 to 2.0 V lasts for 1 ms or longer.
Note, however, that 1 ms is the guaranteed value and that the microcontroller may be reset even if the above low-
voltage condition lasts for less than 1 ms.
Although the voltage at which the reset function is effected ranges from about 1.7 to 2.0 V, the program counter
is prevented from hanging up even if the supply voltage drops until the reset function is effected. Note that a
resonator may stop oscillating before the reset function is effected if normal operation under the low voltage is not
guaranteed.
The low-voltage detector can be set arbitrarily by a mask option.
Data Sheet U15002EJ1V1DS
75
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
12. ASSEMBLER RESERVED WORDS
12.1 Mask Option Directives
When developing the µ PD17246 program, mask options must be specified by using mask option directives in the
program.
To select the low-voltage detector and capacitor for oscillation of the µPD17246, a mask option must be specified.
12.1.1
OPTION and ENDOP directives
The portion of the program enclosed by the OPTION and ENDOP directives is called a mask option definition block.
This block is described in the following format.
Description format:
Symbol
Mnemonic
OPTION
Operand
Comment
[Label: ]
[;Comment]
:
:
:
ENDOP
12.1.2
Mask option definition directives
Table 12-1 lists the directives that can be used in the mask option definition block.
Here is an example of mask option definition.
Description example:
Symbol
Mnemonic
Operand
Comment
OPTION
OPTPOC
OPTCAP
ENDOP
USEPOC
USECAP
; Internal low-voltage detector
; Internal capacitor for oscillation
Data Sheet U15002EJ1V1DS
76
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
Table 12-1. Mask Option Definition Directives
Name
CAP
Directive
OPTCAP
Operands
1
1st Operand
USECAP
2nd Operand
3rd Operand
4th Operand
(capacitor for
oscillation provided)
NOUSECAP
(capacitor for
oscillation not
provided)
POC
OPTPOC
1
USEPOC
(low-voltage detector
provided)
NOUSEPOC
(low-voltage detector
not provided)
12.2 Reserved Symbols
The symbols defined by the µPD17246 device file are listed in Table 12-2.
The defined symbols are the following register file names, port names, and peripheral hardware names.
12.2.1
Register file
The names of the symbols assigned to the register file are defined. These registers are accessed by the PEEK
and POKE instructions via the window register (WR). Figure 12-1 shows the register file.
12.2.2
Registers and ports on data memory
The names of the registers assigned to addresses 00H to 7FH on the data memory and the names of ports assigned
to address 70H and those that follow, and system register names are defined. Figure 12-2 shows the data memory
configuration.
12.2.3
Peripheral hardware
The names of peripheral hardware accessed by the GET and PUT instructions are defined. Table 12-3 shows
the peripheral hardware.
Data Sheet U15002EJ1V1DS
77
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
Table 12-2. Reserved Symbols (1/3)
Symbol Name
DBF3
DBF2
DBF1
DBF0
AR3
Attribute
MEM
MEM
MEM
MEM
MEM
MEM
MEM
MEM
MEM
MEM
MEM
MEM
FLG
Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Bits 15 to 12 of data buffer
0.0CH
0.0DH
Bits 11 to 8 of data buffer
Bits 7 to 4 of data buffer
Bits 3 to 0 of data buffer
Bits 15 to 12 of address register
Bits 11 to 8 of address register
Bits 7 to 4 of address register
Bits 3 to 0 of address register
Window register
0.0EH
0.0FH
0.74H
AR2
0.75H
AR1
0.76H
AR0
0.77H
WR
0.78H
BANK
IXH
0.79H
Bank register
0.7AH
Index register, high
Data memory row address pointer, high
Memory pointer enable flag
Index register, middle
Data memory row address pointer, low
Index register, low
General register pointer, high
General register pointer, low
Program status word
BCD flag
MPH
MPE
IXM
0.7AH
0.7AH.3
0.7BH
MEM
MEM
MEM
MEM
MEM
MEM
FLG
MPL
0.7BH
IXL
0.7CH
RPH
RPL
0.7DH
0.7EH
PSW
BCD
CMP
CY
0.7FH
0.7EH.0
0.7FH.3
0.7FH.2
0.7FH.1
0.7FH.0
0.70H.0
0.70H.1
0.70H.2
0.70H.3
0.71H.0
0.71H.1
0.71H.2
0.71H.3
0.72H.0
0.72H.1
0.72H.2
0.72H.3
0.73H.0
0.73H.1
0.73H.2
0.73H.3
FLG
Compare flag
FLG
Carry flag
Z
FLG
Zero flag
IXE
FLG
Index enable flag
P0A0
P0A1
P0A2
P0A3
P0B0
P0B1
P0B2
P0B3
P0C0
P0C1
P0C2
P0C3
P0D0
P0D1
P0D2
P0D3
FLG
Bit 0 of port 0A
FLG
Bit 1 of port 0A
FLG
Bit 2 of port 0A
FLG
Bit 3 of port 0A
FLG
Bit 0 of port 0B
FLG
Bit 1 of port 0B
FLG
Bit 2 of port 0B
FLG
Bit 3 of port 0B
FLG
Bit 0 of port 0C
FLG
Bit 1 of port 0C
FLG
Bit 2 of port 0C
FLG
Bit 3 of port 0C
FLG
Bit 0 of port 0D
FLG
Bit 1 of port 0D
FLG
Bit 2 of port 0D
FLG
Bit 3 of port 0D
Data Sheet U15002EJ1V1DS
78
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
Table 12-2. Reserved Symbols (2/3)
Symbol Name
P0E0
Attribute
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
MEM
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
0.6FH.0
0.6FH.1
0.6FH.2
0.6FH.3
1.70H.0
1.70H.1
1.70H.2
1.71H.0
0.81H
Bit 0 of port 0E
Bit 1 of port 0E
Bit 2 of port 0E
Bit 3 of port 0E
Bit 0 of port 1A
Bit 1 of port 1A
Bit 2 of port 1A
Bit 0 of port 1B
Stack pointer
P0E1
P0E2
P0E3
P1A0
P1A1
P1A2
P1B0
SP
SYSCK
WDTRES
BTMCK
BTMRES
P1AHL0
P1AHL1
P1AHL2
P1AKEY0
P1AKEY1
P1AKEY2
P1ABPU0
P1ABPU1
P1ABPU2
INT
0.82H.0
0.83H.3
0.83H.2
0.83H.1
0.85H.0
0.85H.1
0.85H.2
0.86H.0
0.86H.1
0.86H.2
0.87H.0
0.87H.1
0.87H.2
0.8FH.0
0.91H.0
0.92H.0
0.92H.1
0.93H.1
0.93H.0
0.95H.2
0.95H.1
0.95H.0
0.96H.0
0.96H.1
0.96H.2
0.96H.3
0.97H.0
0.97H.1
0.97H.2
0.97H.3
0.9FH.1
System clock select flag
Watchdog timer reset flag
Basic interval timer mode select flag
Basic interval timer mode reset flag
P1A0 port standby clear level select flag
P1A1 port standby clear level select flag
P1A2 port standby clear level select flag
P1A0 port key matrix select flag
P1A1 port key matrix select flag
P1A2 port key matrix select flag
P1A0 port pull-up resistor select flag
P1A1 port pull-up resistor select flag
P1A2 port pull-up resistor select flag
INT pin status flag
NRZBF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NRZ buffer data flag
NRZ
NRZ data flag
REMEN
REMCK1
REMCK0
P1BHL0
P1BKEY0
P1BBPU0
P0EKEY0
P0EKEY1
P0EKEY2
P0EKEY3
P0EBPU0
P0EBPU1
P0EBPU2
P0EBPU3
INTSEL
Carrier output select flag
Carrier generation clock select flag
Carrier generation clock select flag
P1B0 port standby clear level select flag
P1B0 port key matrix select flag
P1B0 port pull-up resistor select flag
P1E0 port key matrix select flag
P1E1 port key matrix select flag
P1E2 port key matrix select flag
P1E3 port key matrix select flag
P0E0 pull-up setting flag
P0E1 pull-up setting flag
P0E2 pull-up setting flag
P0E3 pull-up setting flag
INT select flag
Data Sheet U15002EJ1V1DS
79
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
Table 12-2. Reserved Symbols (3/3)
Symbol Name
IEG
Attribute
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
FLG
DAT
DAT
DAT
DAT
DAT
DAT
DAT
DAT
DAT
DAT
DAT
DAT
Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
INT pin interrupt edge flag
0.9FH.0
0.0A1H.0
0.0A5H.0
0.0A5H.1
0.0A5H.2
0.0A6H.0
0.0A6H.1
0.0A6H.2
0.0A6H.3
0.0A7H.0
0.0A7H.1
0.0A7H.2
0.0A7H.3
0.0AFH.2
0.0AFH.1
0.0AFH.0
0.0B3H.3
0.0B3H.2
0.0B3H.1
0.0B3H.0
0.0B7H.2
0.0B7H.3
0.0BDH.0
0.0BEH.0
0.0BFH.0
05H
RAMFLAG
P1ABIO0
P1ABIO1
P1ABIO2
P0BBIO0
P0BBIO1
P0BBIO2
P0BBIO3
P0EBIO0
P0EBIO1
P0EBIO2
P0EBIO3
IPBTM
RAM retention flag
P1A0 I/O select flag
P1A1 I/O select flag
P1A2 I/O select flag
P0B0 I/O select flag
P0B1 I/O select flag
P0B2 I/O select flag
P0B3 I/O select flag
P0E0 I/O setting flag
P0E1 I/O setting flag
P0E2 I/O setting flag
P0E3 I/O setting flag
Basic interval timer interrupt enable flag
INT pin interrupt enable flag
Timer interrupt enable flag
Timer enable flag
IP
IPTM
TMEN
TMRES
TMCK1
TMCK0
P0CGIO
P0DGIO
IRQBTM
IRQ
Timer reset flag
Timer clock flag
Timer clock flag
P0C3 to P0C0 I/O select flag
P0D3 to P0D0 I/O select flag
Basic interval timer interrupt request flag
INT pin interrupt request flag
Timer interrupt request flag
Timer count register
IRQTM
TMC
TMM
06H
W
Timer modulo register
NRZLTMM
NRZHTMM
AR
03H
R/W
R/W
R/W
—
NRZ low-level timer modulo register
NRZ high-level timer modulo register
Address register
04H
40H
USECAP
NOUSECAP
USEPOC
NOUSEPOC
DBF
0FF11H
0FF22H
0FF33H
0FF44H
0FH
Capacitor with oscillator is used.
Capacitor with oscillator is not used.
POC circuit is used.
—
—
—
POC circuit is not used.
Fixed operand value for PUT, GET, MOVT instruction
Fixed operand value for INC instruction
Indicates that the EPA bit of AR is ON.
—
IX
01H
—
AR_EPA1
8040H
—
Data Sheet U15002EJ1V1DS
80
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
Figure 12-1. Register Files (1/2)
Column
Address
0
1
2
3
4
5
6
7
Row
Address
Bit 3
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
WDTRES
BTMCK
BTMRES
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P1AHL2 0 P1AKEY2 0 P1ABPU2 0
P1AHL1 0 P1AKEY1 0 P1ABPU1 0
P1AHL0 0 P1AKEY0 0 P1ABPU0 0
Bit 2
Bit 1
Bit 0
Bit 3
Bit 2
Bit 1
Bit 0
Bit 3
Bit 2
0
1
2
3
SP
SYSCK
0
0
0 P0EKEY3 0 P0EBPU3
0
0
0
0
0
0
0
P1BHL0 0 P0EKEY2 0
P1BKEY0 0 P0EKEY1 0
P1BPU0 0 P0EKEY0 0
P0EBPU2
0
REMEN
NRZ
REMCK1
REMCK0
P0EBPU1 0
NRZBF
0
P0EBPU0
0
0
0
0
0
0
0
0
P0BBIO3 0 P0EBIO3
0
0
0
0
P1ABIO2
P1ABIO1
P1ABIO0
0
P0EBIO2
P0BBIO2
P0BBIO1 0 P0EBIO1
Bit 1
Bit 0
Bit 3
Bit 2
0
P0BBIO0
P0EBIO0
P0DGIO
P0CGIO
0
RAMFLAG 0
1
1
0
0
TMEN
TMRES
TMCK1
TMCK0
1
0
0
0
Bit 1
Bit 0
0
Note After reset
Figure 12-2. Data Memory Configuration
Column address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
DBF3 DBF2 DBF1 DBF0
DBF
P0E
0
to P0E
3
AR3 AR2 AR1 AR0 WR BANK IXH IXM IXL RPH RPL PSW
System register
P0D
P0C
0
to P0D
3
0
to P0C
3
P1B
P0B
P1A
P0A
0
0
0
0
to P0B
3
to P0A
3
Data Sheet U15002EJ1V1DS
81
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
Figure 12-1. Register Files (2/2)
Column
Address
8
9
A
B
C
D
E
F
Row
Address
Bit 3
0
0
0
0
P
0
0
Bit 2
Bit 1
Bit 0
Bit 3
Bit 2
Bit 1
Bit 0
Bit 3
Bit 2
Bit 1
Bit 0
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
2
3
INT
0
0
INTSEL 0
IEG
0
0
0
0
0
0
0
0
0
IPBTM
IP
IPTM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IRQBTM 0
IRQ
IRQTM 1
Note After reset
P: When INT pin is high level, 1; when INT pin is low level, 0.
Table 12-3. Peripheral Hardware
Name
TMC
Address
05H
Valid Bit
Description
8
8
Timer count register
Timer modulo register
TMM
06H
NRZLTMM
NRZHTMM
AR
03H
8
Low-level timer modulo register for NRZ
High-level timer modulo register for NRZ
Address register
04H
8
40H
16
Data Sheet U15002EJ1V1DS
82
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
13. INSTRUCTION SET
13.1 Instruction Set Outline
b15
0
1
b14 to b11
BIN.
HEX.
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
0
1
2
3
4
5
6
7
ADD
SUB
ADDC
SUBC
AND
XOR
OR
r, m
r, m
r, m
r, m
r, m
r, m
r, m
ADD
SUB
ADDC
SUBC
AND
XOR
OR
m, #n4
m, #n4
m, #n4
m, #n4
m, #n4
m, #n4
m, #n4
INC
AR
INC
IX
MOVT
BR
DBF, @AR
@AR
@AR
CALL
RET
Note
SYSCAL
RETSK
EI
entry
DI
RETI
PUSH
POP
GET
AR
AR
DBF, p
p, DBF
WR, rf
rf, WR
r
PUT
PEEK
POKE
RORC
STOP
HALT
NOP
s
h
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
8
9
LD
r, m
ST
m, r
SKE
MOV
SKNE
BR
m, #n4
SKGE
MOV
SKLT
CALL
MOV
SKT
m, #n4
m, @r
m, #n4
addr
A
B
C
D
E
F
@r, m
m, #n4
addr (Page 0)
addr (Page 1)
addr (Page 2)
addr (Page 3)
BR
m, #n4
m, #n
m, #n
BR
BR
SKF
Note µPD17244, 17245, 17246 only
Data Sheet U15002EJ1V1DS
83
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
13.2 Legend
AR:
ASR:
addr:
BANK:
CMP:
CY:
DBF:
entry:
h:
Address register
Address stack register specified by stack pointer
Program memory address (lower 11 bits)
Bank register
Compare flag
Carry flag
Data buffer
Entry address of system segment
Halt releasing condition
INTEF:
INTR:
INTSK:
IX:
Interrupt enable flag
Register automatically saved to stack in case of interrupt
Interrupt stack register
Index register
MP:
MPE:
m:
Data memory row address pointer
Memory pointer enable flag
Data memory address specified by mR, mC
Data memory row address (high)
Data memory column address (low)
Bit position (4 bits)
mR:
mC:
n:
n4:
Immediate data (4 bits)
PAGE:
PC:
p:
Page (bits 11 and 12 of program counter)
Program counter
Peripheral address
pH:
Peripheral address (higher 3 bits)
Peripheral address (lower 4 bits)
General register column address
Register file address
pL:
r:
rf:
rfR:
Register file row address (higher 3 bits)
Register file column address (lower 4 bits)
Stack pointer
rfC:
SP:
s:
Stop releasing condition
WR:
(×):
Window register
Contents addressed by ×
Data Sheet U15002EJ1V1DS
84
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
13.3 List of Instructions
Group
Mnemonic
ADD
Operand
Operation
Instruction Code
Operand
Opcode
00000
10000
00010
10010
00111
00111
00001
10001
00011
10011
00110
10110
00100
10100
00101
10101
11110
11111
01001
01011
11001
11011
00111
Add
r, m
(r) ← (r) + (m)
(m) ← (m) + n4
mR
mR
mR
mR
000
000
mR
mR
mR
mR
mR
mR
mR
mR
mR
mR
mR
mR
mR
mR
mR
mR
000
mC
mC
r
n4
r
m, #n4
r, m
ADDC
INC
(r) ← (r) + (m) + CY
(m) ← (m) + n4 + CY
AR ← AR + 1
mC
m, #n4
AR
mC
n4
0000
0000
r
1001
1000
mC
IX
IX ← IX + 1
Subtract
Logical
SUB
r, m
(r) ← (r) – (m)
m, #n4
r, m
(m) ← (m) – n4
mC
n4
r
SUBC
OR
(r) ← (r) – (m) – CY
(m) ← (m) – n4 – CY
(r) ← (r) ∨ (m)
mC
m, #n4
r, m
mC
n4
r
mC
m, #n4
r, m
(m) ← (m) ∨ n4
(r) ← (r) ∧ (m)
(m) ← (m) ∧ n4
(r) ← (r) ∀ (m)
mC
n4
r
AND
mC
m, #n4
r, m
mC
n4
r
XOR
mC
m, #n4
m, #n
m, #n
m, #n4
m, #n4
m, #n4
m, #n4
r
(m) ← (m) ∀ n4
mC
n4
n
Judge
SKT
CMP ← 0, if (m) ∧ n = n, then skip
CMP ← 0, if (m) ∧ n = 0, then skip
(m) – n4, skip if zero
(m) – n4, skip if not zero
(m) – n4, skip if not borrow
(m) – n4, skip if borrow
mC
SKF
mC
n
Compare
SKE
mC
n4
n4
n4
n4
r
SKNE
SKGE
SKLT
RORC
mC
mC
mC
Rotate
0111
CY → (r)b3 → (r)b2 → (r)b1 → (r)b0
Transfer
LD
r, m
(r) ← (m)
(m) ← (r)
01000
11000
01010
mR
mR
mR
mC
mC
mC
r
r
r
ST
m, r
MOV
@r, m
if MPE = 1 : (MP, (r)) ← (m)
if MPE = 0 : (BANK, mR, (r)) ← (m)
m, @r
if MPE = 1 : (m) ← (MP, (r))
11010
mR
mC
r
if MPE = 0 : (m) ← (BANK, mR, (r))
m, #n4
(m) ← n4
11101
00111
mR
mC
n4
MOVT
DBF,
@AR
SP ← SP – 1, ASR ← PC, PC ← AR
DBF ← (PC), PC ← ASR, SP ← SP + 1
000
0001
0000
Data Sheet U15002EJ1V1DS
85
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
Group
Mnemonic
Operand
Operation
Instruction Code
Operand
Opcode
00111
00111
00111
00111
00111
00111
Note 1
00111
11100
Transfer
PUSH
POP
PEEK
POKE
GET
PUT
AR
SP ← SP – 1, ASR ← AR
AR ← ASR, SP ← SP + 1
WR ← (rf)
000
000
rfR
1101
1100
0011
0010
1011
1010
addr
0100
addr
0000
0000
rfC
AR
WR, rf
rf, WR
DBF, p
p, DBF
addr
(rf) ← WR
rfR
rfC
(DBF) ← (p)
pH
pL
(p) ← (DBF)
pH
pL
Branch
BR
Note 1
@AR
addr
PC ← AR
000
0000
Subroutine CALL
SP ← SP – 1, ASR ← PC,
PC10–0 ← addr, PAGE ← 0
@AR
SP ← SP – 1, ASR ← PC,
PC ← AR
00111
00111
000
0101
0000
0000
SYSCALNote 2 entry
SP ← SP – 1, ASR ← PC, SGR ← 1,
PC12,11 ← 0, PC10–8 ← entryH, PC7–4 ← 0,
PC3–0 ← entryL
entryH
entryL
RET
RETSK
RETI
EI
PC ← ASR, SP ← SP + 1
00111
00111
00111
00111
00111
00111
00111
00111
000
001
100
000
001
010
011
100
1110
1110
1110
1111
1111
1111
1111
1111
0000
0000
0000
0000
0000
s
PC ← ASR, SP ← SP + 1 and skip
PC ← ASR, INTR ← INTSK, SP ← SP + 1
Interrupt
Other
INTEF ← 1
INTEF ← 0
STOP
DI
STOP
HALT
NOP
s
h
HALT
h
No operation
0000
Notes 1. The operation and operation codes “BR addr” of the µPD17240, 17241, 17242, 17243, 17244, 17245, and
17246 are as follows.
(a) µPD17240
Operand
addr
Operation
PC10–0 ← addr
Opcode
01100
(b) µPD17241
Operand
addr
Operation
PC10–0 ← addr, Page ← 0
PC10–0 ← addr, Page ← 1
Opcode
01100
01101
(c) µPD17242
Operand
addr
Operation
PC10–0 ← addr, Page ← 0
PC10–0 ← addr, Page ← 1
PC10–0 ← addr, Page ← 2
Opcode
01100
01101
01110
Data Sheet U15002EJ1V1DS
86
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
(d) µPD17243, 17244, 17245, 17246
Operand
addr
Operation
PC10–0 ← addr, Page ← 0
PC10–0 ← addr, Page ← 1
PC10–0 ← addr, Page ← 2
PC10–0 ← addr, Page ← 3
Opcode
01100
01101
01110
01111
2. µPD17244, 17245, and 17246 only
13.4 Assembler (RA17K) Embedded Macro Instructions
Legend
flag n: FLG type symbol
n:
<
Bit number
>: Contents in < > can be omitted
Mnemonic
Embedded SKTn
Operand
flag 1, ...flag n
flag 1, ...flag n
flag 1, ...flag n
flag 1, ...flag n
flag 1, ...flag n
Operation
n
if (flag 1) to (flag n) = all “1”, then skip
if (flag 1) to (flag n) = all “0”, then skip
(flag 1) to (flag n) ← 1
1 ≤ n ≤ 4
1 ≤ n ≤ 4
1 ≤ n ≤ 4
1 ≤ n ≤ 4
1 ≤ n ≤ 4
macro
SKFn
SETn
CLRn
NOTn
(flag 1) to (flag n) ← 0
if (flag n) = “0”, then (flag n) ← 1
if (flag n) = “1”, then (flag n) ← 0
INITFLG
BANKn
<NOT> flag 1,
if description = NOT flag n, then (flag n) ← 0
if description = flag n, then (flag n) ← 1
1 ≤ n ≤ 4
···<<NOT> flag n>
(BANK) ← n
n = 0, 1
—
Expansion BRX
instruction
Label
Jump Label
CALLX
function-name
CALL sub-routine
—
INITFLGX
<NOT/INV> flag 1,
...<NOT/INV> flag n
if description = NOT (or INV)
flag, (flag) ← 0
n ≤ 4
if description = flag, (flag) ← 1
Data Sheet U15002EJ1V1DS
87
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
14. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Item
Supply voltage
Symbol
VDD
VI
Conditions
Ratings
–0.3 to +3.8
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–36.0
Unit
V
Input voltage
V
Output voltage
Output current, high
VO
V
Note
IOH
REM pin
Peak value
rms value
Peak value
rms value
Peak value
rms value
Peak value
rms value
Peak value
rms value
Peak value
rms value
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
°C
–24.0
1 pin (P0E, P1A pins)
Total of P0E, P1A pins
–7.5
–5.0
–22.5
–15.0
Note
Output current, low
IOL
1 pin (P0B, P0C, P0D,
P0E, P1A, REM pins)
7.5
5.0
Total of P0B, P0C, P0D,
REM pins
22.5
15.0
Total of P0E, P1A pins
30.0
20.0
Operating temperature
Storage temperature
Power dissipation
TA
Tstg
Pd
–40 to +85
–65 to +150
180
°C
TA = 85°C
mW
Note Calculate rms value by this expression: [rms value] = [Peak value] ×
Duty
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Data Sheet U15002EJ1V1DS
88
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
Recommended Operating Ranges (TA = –40 to +85°C, VDD = 2.0 to 3.6 V)
Item
Supply Voltage
Symbol
VDD1
Conditions
MIN.
2.0
TYP. MAX.
3.6
Unit
V
fX = 1 MHz High-speed mode
(Instruction execution time: 16 µs)
fX = 4 MHz High-speed mode
(Instruction execution time: 4 µs)
fX = 8 MHz Normal mode
(Instruction execution time: 4 µs)
VDD2
VDD3
VDD4
fX
High-speed mode
2.2
3.6
V
(Instruction execution time: 2 µs)
Oscillation frequency
Operating temperature
RfX = fX/2 or fX
RfX = 2fX
1.0
3.5
–40
3.5
4.0
4.0
8.0
4.5
+85
32
MHz
MHz
°C
TA
+25
Note
Low-voltage detector
(Mask option)
tCY
µs
Note Reset if the status of VDD = 1.7 to 2.0 V lasts for 1 ms or longer. Program hang-up does not occur even
if the voltage drops, until the reset function is effected. A resonator may stop oscillating before the reset
function is effected if normal operation under the low voltage is not guaranteed.
Caution Design the application circuit so that the RESET pin goes low when the supply voltage is less
than 2.2 V.
fX vs VDD
(MH )
Z
10
9
8
7
6
5
4
3
2
Operation
guaranteed area
1
0.4
0
2 2.2
3
3.6
4
Supply voltage VDD (V)
Remark The region indicated by the broken lines in the above figure is the guaranteed operating range in the
high-speed mode.
Data Sheet U15002EJ1V1DS
89
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 2.0 to 3.6 V)
Resonator
Recommended
Constants
Item
Conditions
MIN.
1.0
TYP. MAX.
Unit
Ceramic
Oscillation frequency
4.0
8.0
4
MHz
Note 1
resonator
(fX)
X
IN
X
OUT
Oscillation
After VDD reached MIN.
in oscillation voltage
range
ms
Note 2
stabilization time
Notes 1. The oscillation frequency only indicates the oscillator characteristics.
2. The oscillation stabilization time is necessary for oscillation to be stabilized after VDD application or
STOP mode release.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the dotted lines
in the above figure, to avoid an adverse effect from wiring capacitance.
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with other signal lines. Do not route the wiring near a signal line
through which a large current flows.
•
•
Always make the ground point of the oscillator capacitor the same potential as GND. Do not
ground the capacitor to a ground pattern through which a large current flows.
Do not fetch signals from the oscillator.
Data Sheet U15002EJ1V1DS
90
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
Recommended Oscillator Constant
Ceramic resonator (TA = –40 to +85°C)
Recommended
Oscillation
Frequency
(MHz)
Circuit Constant (pF) Voltage Range (VDD)
Remarks
Manufacturer
Part Number
C1
C2
MIN.
1.8
MAX.
3.6
Murata Mfg. Co., Ltd. CSBLA1M00J58-B0Note
CSBFB1M00J58-R1Note
CSTLS2M00G56-B0Note
CSTCC2M00G56-R0Note
CSTLS3M00G56-B0Note
CSTCC3M00G56-R0Note
CSTLS4M00G56-B0
1.0
2.0
3.0
4.0
6.0
8.0
100
100
Rd = 3.3 kΩ
–
–
Rd = 1.0 kΩ
On-chip capacitor
Rd = 470 Ω
On-chip capacitor
On-chip capacitor
CSTCR4M00G55-R0
CSTLS6M00G56-B0
CSTCR6M00G55-R0
CSTLS8M00G56-B0
CSTCC8M00G56-R0
TDK
FCR3.52MC5
FCR4.0MC5
FCR4.0MSC5
FCR6.0MC5
FCR8.0MC5
KBR-2.0MS
KBR-3.0MS
KBR-4.0MKE
KBR-4.0MSE
KBR-6.0MKC
KBR-6.0MSB
KBR-8.0MKC
KBR-8.0MSB
3.52
4.0
4.0
6.0
8.0
2.0
3.0
4.0
–
–
1.8
1.8
3.6
3.6
On-chip capacitor
Kyocera Corp.
68
47
–
68
47
–
–
On-chip capacitor
33
–
33
–
–
6.0
8.0
On-chip capacitor
33
–
33
–
–
On-chip capacitor
–
33
33
Note A limiting resistor is required when these ceramic resonators are used (refer to the following figure). When
other recommended resonators are used, the limiting resistor is not necessary.
X
IN
XOUT
Rd
C2
C1
Caution The oscillator constant is a reference value based on evaluation in specific environments by the
resonator manufacturer. If the oscillator characteristics need to be optimized in the actual
application, request the resonator manufacturer for evaluation on the implementation circuit.
Note that the oscillation voltage and oscillation frequency merely indicate the characteristics of
the oscillator. The internal operation conditions of the µPD17240, 17241, 17242, 17243, 17244,
17245, and 17246 must be within the specifications of the DC and AC characteristics.
Data Sheet U15002EJ1V1DS
91
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
DC Characteristics (TA = –40 to +85°C, VDD = 2.0 to 3.6 V)
Item
Symbol
VIHI1
VIH2
VIH3
VIL1
Conditions
MIN.
TYP.
MAX.
VDD
Unit
V
Input voltage, high
RESET, INT
0.80VDD
P0A, P0B, P0C, P0D
P0E, P1A, P1B
0.70VDD
VDD
V
0.70VDD
VDD
V
Input voltage, low
RESET, INT
0
0
0
0.2VDD
0.3VDD
0.3VDD
3.0
V
VIL2
P0A, P0B, P0C, P0D
P0E, P1A, P1B
V
VIL3
V
Input leakage current, high
Input leakage current, low
Internal pull-up resistor
ILIH
P0A, P0B, P0C, P0D, P0E, VIH = VDD
µA
P1A, P1B0/INT, RESET
w/o pull-down resistor
ILIL
P0E, P1A, P1B0/INT
VIL = 0 V
–3.0
µA
w/o pull-up resistor
R1
R2
P0E, P1A, P1B, RESET (pulled up)
25
100
25
50
200
50
100
400
100
–24
kΩ
kΩ
kΩ
mA
P0A, P0B, P0C, P0D
P1A, P1B
Internal pull-down resistor
Output current, high
R3
IOH
REM
VOH = 1.0 V,
VDD = 3 V
–6
–13
Output voltage, high
Output voltage, low
VOH
VOL1
VOL2
P0E, P1A, REM
P0B, P0C, P0D, REM
P0E, P1A
IOH = –0.5 mA VDD–0.3
VDD
0.3
0.3
3.6
2.0
V
V
V
V
V
IOL = 0.5 mA
IOL = 1.5 mA
0
0
Data retention characteristics VDDDR RESET = Low level or STOP mode
1.3
Low-voltage detection
voltage (mask option)
VDT
RESET pin pulled down, VDT = VDD
1.85
1.40
RAM retention detection
voltage
VID
VID = VDD, RAMFLAG = 0 (RF21H.0)
1.50
V
Supply current
IDD1
Operating mode
(high-speed)
VDD = 3 V 10% fX = 1 MHz
fX = 4 MHz
0.6
0.75
0.9
1.1
1.3
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
fX = 8 MHz
1.6
IDD2
IDD3
IDD4
Operating mode
(low-speed)
VDD = 3 V 10% fX = 1 MHz
fX = 4 MHz
0.48
0.6
0.9
1.1
fX = 8 MHz
0.8
1.4
HALT mode
STOP mode
VDD = 3 V 10% fX = 1 MHz
fX = 4 MHz
0.4
0.75
0.85
0.95
20.0
5.0
0.45
0.5
fX = 8 MHz
VDD = 3 V 10%
2.0
built-in POC
TA = 25°C
2.0
µA
Note This does not include the current that flows through the internal pull-up resistors.
Data Sheet U15002EJ1V1DS
92
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
AC Characteristics (TA = –40 to +85°C, VDD = 2.0 to 3.6 V)
Item
Symbol
tCY1
Conditions
MIN.
3.4
1.9
20
TYP.
MAX.
33
Unit
µs
Note
CPU clock cycle time
VDD = 2.0 to 3.6 V
VDD = 2.2 to 3.6 V
(Instruction execution time)
INT high-/low-level width
tCY2
33
µs
tINTH,
tINTL
µs
RESET low-level width
tRSL
10
µs
Note The CPU clock cycle time (instruction execution time) is determined by the oscillation frequency of the
resonator connected and SYSCK (RF: address 02H) of the register file. The figure below shows the CPU
clock cycle time tCY vs. supply voltage VDD characteristics (refer to 4. CLOCK GENERATOR).
tCY vs VDD
40
33
10
9
8
µ
7
6
5
Operation
guaranteed
area
4
3
3.4
1.9
2
1
2.2
3.6
0
1
2
3
4
Supply voltage VDD (V)
Data Sheet U15002EJ1V1DS
93
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
15. APPLICATION CIRCUIT EXAMPLE
P0D
2
P1A
2
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P0D
3
P0D
P0D
P0C
P0C
P0C
P0C
1
0
3
2
1
0
2
P1B0/INT
3
P0E
P0E
P0E
P0E
0
1
2
3
+
4
5
6
7
REM
P0B
P0B
P0B
P0B
P0A
P0A
P0A
P0A
3
2
1
0
3
2
1
0
8
VDD
9
XOUT
10
11
12
13
14
15
3 V
XIN
4 MHz
GND
RESET
P1A
0
Jog
shuttle
P1A
1
=
Key matrix
8 × 9 = 72 keys
Data Sheet U15002EJ1V1DS
94
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
16. PACKAGE DRAWING
30-PIN PLASTIC SSOP (7.62 mm (300))
30
16
detail of lead end
F
G
T
P
L
1
15
U
E
A
H
I
J
S
B
C
N
S
M
D
M
K
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
A
B
C
9.85 0.15
0.45 MAX.
0.65 (T.P.)
+0.08
0.24
D
−0.07
E
F
G
H
I
0.1 0.05
1.3 0.1
1.2
8.1 0.2
6.1 0.2
1.0 0.2
0.17 0.03
0.5
J
K
L
M
N
0.13
0.10
+5°
3°
P
−3°
T
0.25
U
0.6 0.15
S30MC-65-5A4-2
Data Sheet U15002EJ1V1DS
95
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
17. RECOMMENDED SOLDERING CONDITIONS
The µPD17240, 17241, 17242, 17243, 17244, 17245, and 17246 should be soldered and mounted under the
following recommended conditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 17-1. Surface Mounting Type Soldering Conditions
(1) µPD17240MC-×××-5A4: 30-pin plastic SSOP (7.62 mm (300))
µPD17241MC-×××-5A4: 30-pin plastic SSOP (7.62 mm (300))
µPD17242MC-×××-5A4: 30-pin plastic SSOP (7.62 mm (300))
µPD17243MC-×××-5A4: 30-pin plastic SSOP (7.62 mm (300))
µPD17244MC-×××-5A4: 30-pin plastic SSOP (7.62 mm (300))
µPD17245MC-×××-5A4: 30-pin plastic SSOP (7.62 mm (300))
µPD17246MC-×××-5A4: 30-pin plastic SSOP (7.62 mm (300))
Recommended Condition
Soldering Method
Infrared reflow
Soldering Conditions
Symbol
Package peak temperature: 235°C, Time: 30 seconds max.
(at 210°C or higher), Count: Three times or less
IR35-00-3
VPS
Package peak temperature: 215°C, Time: 40 seconds max.
(at 200°C or higher), Count: Three times or less
VP15-00-3
Wave soldering
Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once, WS60-00-1
Preheating temperature: 120°C max. (package surface temperature)
Partial heating
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
–
(2) µPD17240MC-×××-5A4-A: 30-pin plastic SSOP (7.62 mm (300))
µPD17241MC-×××-5A4-A: 30-pin plastic SSOP (7.62 mm (300))
µPD17242MC-×××-5A4-A: 30-pin plastic SSOP (7.62 mm (300))
µPD17243MC-×××-5A4-A: 30-pin plastic SSOP (7.62 mm (300))
µPD17244MC-×××-5A4-A: 30-pin plastic SSOP (7.62 mm (300))
µPD17245MC-×××-5A4-A: 30-pin plastic SSOP (7.62 mm (300))
µPD17246MC-×××-5A4-A: 30-pin plastic SSOP (7.62 mm (300))
Recommended Condition
Symbol
Soldering Method
Infrared reflow
Soldering Conditions
Package peak temperature: 260°C, Time: 60 seconds max.
(at 220°C or higher), Count: Three times or less, Exposure limit: 3 days
IR60-103-3
Note
(after that, prebake at 125°C for 10 to 72 hours)
Wave soldering
Partial heating
For details, contact an NEC Electronics sales representative.
–
–
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Remark Products that have the part numbers suffixed by “-A” are lead-free products.
Data Sheet U15002EJ1V1DS
96
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
APPENDIX A DIFFERENCES BETWEEN µPD17246 AND µPD17P246
The µPD17P246 is equipped with PROM to which data can be written by the user instead of the internal mask ROM
(program memory) of the µPD17246.
Table A-1 shows the differences between the µPD17246 and µPD17P246.
The CPU functions and internal hardware of the µPD17P246, 17240, 17241, 17242, 17243, 17244, 17245, and
17246 are identical. Therefore, the µPD17P246 can be used to evaluate the program developed for the µPD17240,
17241, 17242, 17243, 17244, 17245, and 17246 system. Note, however, that some of the electrical specifications
such as supply current and low-voltage detection voltage of the µPD17P246 differ from those of the µPD17240, 17241,
17242, 17243, 17244, 17245, and 17246.
Table A-1. Differences Between µPD17246 and µPD17P246
Product Name
µPD17P246
µPD17246
Item
(µPD17P246M1, 17P246M2)
Program memory
One-time PROM
Mask ROM
32 KB (16,384 × 16)
(0000H to 3FFFH)
Data memory
447 × 4 bits
Capacitor for oscillator
• Not provided (µPD17P246M1)
• Provided (µPD17P246M2)
Any (mask option)
Note 1
Low-voltage detector
Provided
Any (mask option)
Not provided
VPP pin, operation mode select pin
Provided
Note 2
Instruction execution time
4 µs (VDD = 2.2 to 3.6 V)
VDD = 2.2 to 3.6 V
30-pin plastic SSOP (7.62 mm (300))
4 µs (VDD = 2.0 to 3.6 V)
VDD = 2.0 to 3.6 V
Note 2
Supply voltage
Package
Notes 1. Although the circuit configuration is identical, the electrical characteristics differ depending on the product.
2. When fx = 4 MHz and high-speed mode operation is set.
Data Sheet U15002EJ1V1DS
97
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
APPENDIX B DEVELOPMENT TOOLS
The following development tools are available to develop the programs for the µPD17246 Subseries.
Hardware
Name
Remarks
The IE-17K and IE-17K-ET are in-circuit emulators used in common with the 17K Series
microcontrollers.
In-circuit emulator
IE-17K,
IE-17K-ETNote 1
TM
The IE-17K and IE-17K-ET are connected to the PC-9800 series or IBM PC/AT compatible
machines as the host machine via RS-232C.
By using these in-circuit emulators with a system evaluation board corresponding to the
microcomputer, the emulators can emulate the microcomputer. A higher level debugging
TM
environment can be provided by using the human interface SIMPLEHOST
.
EM board
This is an EM board for the µPD17246 Subseries. It can be used alone to evaluate a system
or in combination with an in-circuit emulator for debugging.
Note 2
(EM-17246
)
Emulation probe
(EP-17K30GS)
The EP-17K30GS is an emulation probe for a 17K Series 30-pin shrink SOP (MC-5A4). When
Note 3
used with the EV-9500GT-30
, it connects an EM board to the target system.
Conversion adapter
The EV-9500GT-30 is a conversion adapter for a 30-pin shrink SOP (MC-5A4). It is used
to connect the EP-17K30GS and target system.
Note 3
(EV-9500GT-30
)
PROM programmer
TheAF-9706,AF-9708,andAF-9709arePROMprogrammerscorrespondingtotheµPD17P246.
By connecting the program adapter PA-17P236 to this PROM programmer, the µPD17P246 can
be programmed.
Note 4
Note 4
(AF-9706
, AF-9708
,
Note 4
AF-9709
)
Program adapter
(PA-17P236)
The PA-17P236 is an adapter used to program the µPD17P236, and is used in combination
with the AF-9706, AF-9708, or AF-9709.
Notes 1. Low-cost model: External power supply type
2. This is a product of Naito Densei Machida Mfg., Co., Ltd. (TEL +81-45-475-4191)
3. Two EV-9500GT-30 units are supplied with the EP-17K30GS. Five EV-9500GT-30 units are optionally
available as a set.
4. These are products of Ando Electric Co., Ltd. (TEL: +81-53-576-1560).
Data Sheet U15002EJ1V1DS
98
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
Software
Name
Outline
Host Machine
OS
Supply
Order Code
TM
17K assembler
(RA17K)
PC-9800
series
Japanese Windows
3.5" 2HD µSAA13RA17K
3.5" 2HC µSAB13RA17K
µSBB13RA17K
The RA17K is an assembler
common to 17K Series products.
When developing the programs of
devices, RA17K is used in
combination with a device file
(AS17225).
IBM PC/AT
compatible
machine
Japanese Windows
English Windows
Japanese Windows
Japanese Windows
English Windows
Japanese Windows
Japanese Windows
English Windows
Device file
(AS17246)
PC-9800
series
3.5" 2HD µSAA13AS17246
3.5" 2HC µSAB13AS17246
µSBB13AS17246
The AS17246 is a device file for
the µPD17240, 17241, 17242,
17243, 17244, 17245, and 17246,
and is used in combination with an
assembler for the 17K Series
(RA17K).
IBM PC/AT
compatible
machine
Support
PC-9800
series
3.5" 2HD µSAA13ID17K
3.5" 2HC µSAB13ID17K
µSBB13ID17K
SIMPLEHOST is a software
package that enables a human
interface on Windows when a
program is developed by using an
in-circuit emulator and a personal
computer.
software
(SIMPLEHOST)
IBM PC/AT
compatible
machine
Data Sheet U15002EJ1V1DS
99
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is
fixed, and also in the transition period when the input level passes through the area between VIL (MAX)
and VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or
GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins
must be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
Data Sheet U15002EJ1V1DS
100
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65030
800-366-9782
•
•
•
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Seoul Branch
Seoul, Korea
Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
Tel: 02-558-3737
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Tel: 01-30-67 58 00
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Shanghai, P.R. China
Tel: 021-5888-5400
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Milano, Italy
Tel: 02-66 75 41
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Taipei, Taiwan
Tel: 02-2719-2377
•
Branch The Netherlands
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Tel: 040-2654010
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•
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Taeby, Sweden
Tel: 08-63 87 200
United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
J05.6
Data Sheet U15002EJ1V1DS
101
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
SIMPLEHOST is a trademark of NEC Electronics Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States
and/or other countries.
PC/AT is a trademark of IBM Corporation.
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
•
The information in this document is current as of August, 2005. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
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or any other liability arising from the use of such products. No license, express, implied or otherwise, is
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Descriptions of circuits, software and other related information in this document are provided for illustrative
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M8E 02. 11-1
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