SH7101 [RENESAS]
32-Bit RISC Microcomputer; 32位RISC微计算机
| 型号： | SH7101 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 32-Bit RISC Microcomputer |
| 文件： | 总486页 (文件大小：2763K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
REJ09B0394-0200
The revision list can be viewed directly by clicking the title page.
The revision list summarizes the locations of revisions and
additions. Details should always be checked by referring to the
relevant text.
SH7101
Hardware Manual
32
Renesas 32-Bit RISC Microcomputer
SuperHTM RISC engine Family/SH7100 Series
SH7101 HD6437101
Rev.2.00
Revision date: Sep. 27, 2007
www.renesas.com
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
Rev.2.00 Sep. 27, 2007 Page ii of xxxiv
REJ09B0394-0200
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in
the manual.
⎯ The input pins of CMOS products are generally in the high-impedance state. In
operation with an unused pin in the open-circuit state, extra electromagnetic noise is
induced in the vicinity of LSI, an associated shoot-through current flows internally, and
malfunctions may occur due to the false recognition of the pin state as an input signal.
Unused pins should be handled as described under Handling of Unused Pins in the
manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
⎯ The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the
states of pins are not guaranteed from the moment when power is supplied until the
reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on
reset function are not guaranteed from the moment when power is supplied until the
power reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
⎯ The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has
become stable. When switching the clock signal during program execution, wait until the
target clock signal has stabilized.
⎯ When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization
of the clock signal. Moreover, when switching to a clock signal produced with an
external resonator (or by an external oscillator) while program execution is in progress,
wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number,
confirm that the change will not lead to problems.
⎯ The characteristics of MPU/MCU in the same group but having different type numbers
may differ because of the differences in internal memory capacity and layout pattern.
When changing to products of different type numbers, implement a system-evaluation
test for each of the products.
Rev.2.00 Sep. 27, 2007 Page iii of xxxiv
REJ09B0394-0200
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
•
•
CPU and System-Control Modules
On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each
section includes notes in relation to the descriptions given, and usage notes are given, as required,
as the final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Index
Rev.2.00 Sep. 27, 2007 Page iv of xxxiv
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Preface
The SH7101 single-chip RISC (Reduced Instruction Set Computer) microcomputer includes a
Renesas Technology-original RISC CPU as its core, and the peripheral functions required to
configure a system.
Target Users: This manual was written for users who will be using this LSI in the design of
application systems. Users of this manual are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of this LSI to the above users.
Refer to the SH-1/SH-2/SH-DSP Software Manual for a detailed description of the
instruction set.
Notes on reading this manual:
•
Product names
The following products are covered in this manual.
Product Classifications and Abbreviations
Basic Classification
On-Chip ROM Classification
Mask ROM version (ROM: 32 kbytes)
Part No.
SH7101 (80-pin version)
HD6437101
In this manual, the product abbreviations are used to distinguish products. For example,
products are collectively referred to as the SH7101.
•
In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
•
•
In order to understand the details of the CPU's functions
Read the SH-1/SH-2/SH-DSP Software Manual.
In order to understand the details of a register when the user knows its name
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bit names, and initial values of the registers are summarized in section
18, List of Registers.
Rev.2.00 Sep. 27, 2007 Page v of xxxiv
REJ09B0394-0200
Rules:
Register name:
Bit order:
The following notation is used for cases when the same or a
similar function, e.g. serial communication, is implemented
on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
The MSB (most significant bit) is on the left and the LSB
(least significant bit) is on the right.
Related Manuals: The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/
SH7101 manuals:
Document Title
Document No.
This manual
SH7101 Hardware Manual
SH-1/SH-2/SH-DSP Software Manual
REJ09B0171-0500
Users manuals for development tools:
Document Title
Document No.
SuperH C/C++ Compiler, Assembler, Optimizing Linkage Editor User's
Manual
REJ10B0047-0100
SuperH RISC engine Simulator/Debugger (for Windows) User's Manual
High-performance Embedded Workshop User's Manual
REJ10B0210-0300
REJ10J1554-0100
Application Notes:
Document Title
Document No.
SuperH RISC engine C/C++ Compiler Package Application Note
REJ05B0463-0400
Rev.2.00 Sep. 27, 2007 Page vi of xxxiv
REJ09B0394-0200
Main Revisions for This Edition
Item
Page
Revision (See Manual for Details)
All
⎯
•
Company name and brand names amended
(Before) Hitachi, Ltd. → (After) Renesas Technology Corp.
6.5 Interrupt Exception 79
Processing Vectors
Table
Table amended
Interrupt
Source
Name
Table 6.2 Interrupt
Exception Processing
Vectors and Priorities
MTU channel 3 TGIA_3
TGIB_3
TGIC_3
TGID_3
TCIV_3
7.5.1 Bus Control
Register 1 (BCR1)
89
94
Bit table amended
Initial
Value
Bit
Bit Name
R/W
Description
14
⎯
1
R
Reserved
These bits are always read as 1 and should always be
written to 1.
8.1 Features
Title and figure amended
Figure 8.1 Block
Diagram of MTU
Interrupt request signals
Channel 3: TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
Channel 4: TGI4A
TGI4B
TGI4C
TGI4D
TCI4V
8.3.3 Timer I/O Control 109
Register (TIOR)
Table amended
Description
Bit 3
Bit 2
Bit 1
Bit 0
TGRC_0
Table 8.13 TIORL_0
(channel 0)
IOC3 IOC2 IOC1 IOC0 Function
TIOC0C Pin Function
0
0
0
0
1
Output
compare
register*
Output disable
Initial output is 0
0 output at compare match
8.4.4 Cascaded
Operation
149
Note amended
Note: When phase counting mode is set for channel 1 or 2, the
counter clock setting is invalid and the counters operates
independently in phase counting mode.
Table 8.30 Cascaded
Combinations
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Item
Page
Revision (See Manual for Details)
8.4.4 Cascaded
Operation
149
Figure amended
[1] Set bits TPSC2 to TPSC0 in the channel 1
TCR to B'111 to select TCNT_2 overflow/ underflow
counting.
Figure 8.18 Cascaded
Operation Setting
Procedure
8.4.8 Complementary
PWM Mode
170
Description amended
10. Set enabling/disabling of PWM waveform output pin output
in the timer output master enable register (TOER).
Example of
Complementary PWM
Mode Setting
Procedure:
11. Set bits CST3 and CST4 in TSTR to 1 simultaneously to
start the count operation.
Complementary PWM 192
Mode Output Protection
Function:
Description amended
• Register and counter miswrite prevention function
With the exception of the buffer registers, which can be
rewritten at any time, access by the CPU can be enabled or
disabled for the mode registers, control registers, compare
registers, and counters used in complementary PWM mode by
means of bit 13 in the bus controller's bus control register 1
(BCR1). Some registers in channels 3 and 4 concerned are
listed below: total 21 registers of TCR_3 and TCR_4; TMDR_3
and TMDR_4; TIORH_3 and TIORH_4; TIORL_3 and
TIORL_4; TIER_3 and TIER_4; TCNT_3 and TCNT_4;
TGRA_3 and TGRA_4; TGRB_3 and TGRB_4; TOER; TOCR;
TGCR; TCDR; and TDDR. This function enables the CPU to
prevent miswriting due to the CPU runaway by disabling CPU
access to the mode registers, control registers, and counters. In
access disabled state, an undefined value is read from the
registers concerned, and cannot be modified.
8.5.1 Interrupts and
Priorities
194
Description amended
An interrupt is requested if the TCIEU bit in TIER is set to 1
when the TCFU flag in TSR is set to 1 by the occurrence of
TCNT underflow on a channel. The interrupt request is cleared
by clearing the TCFU flag to 0. The MTU has two underflow
interrupts, one each for channels 1 and 2.
Underflow Interrupt:
Rev.2.00 Sep. 27, 2007 Page viii of xxxiv
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Item
Page
Revision (See Manual for Details)
8.7.15 Overflow Flags in 216
Reset Sync PWM Mode
Figure amended
Counter cleared by compare match 3A
TGRA_3
(H'FFFF)
Figure 8.81 Reset Sync
PWM Mode Overflow
Flag
TCNT_3 = TCNT_4
H'0000
Not set
Not set
TCFV_3
TCFV_4
8.7.21 Simultaneous
Input Capture of
TCNT_1 and TCNT_2 in
Cascade Connection
219
Description amended
When timer counters 1 and 2 (TCNT_1 and TCNT_2) are
operated as a 32-bit counter in cascade connection, the
cascade counter value cannot be captured successfully even if
input-capture input is simultaneously done to TIOC1A and
TIOC2A or to TIOC1B and TIOC2B. This is because the input
timing of TIOC1A and TIOC2A or of TIOC1B and TIOC2B may
not be the same when external input-capture signals to be input
into TCNT_1 and TCNT_2 are taken in synchronization with the
internal clock. For example, TCNT_1 (the counter for upper 16
bits) does not capture the count-up value by overflow from
TCNT_2 (the counter for lower 16 bits) but captures the count
value before the count-up. In this case, the values of TCNT_1 =
H'FFF1 and TCNT_2 = H'0000 should be transferred to
TGRA_1 and TGRA_2 or to TGRB_1 and TGRB_2, but the
values of TCNT_1 = H'FFF0 and TCNT_2 = H'0000 are
erroneously transferred.
Rev.2.00 Sep. 27, 2007 Page ix of xxxiv
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Item
Page
Revision (See Manual for Details)
8.9.5 Usage Note
262
Description added
(1) Symptom
(a) Regarding the POEnF*1 bits
If setting of the POEnF bits in the input level control/status
registers (ICSR1 and ICSR2) by the hardware*2 and reading
from these bits occur simultaneously, “0” will be read, where “1”
should be read.
Furthermore, if clearing of these bits is attempted subsequent
to the above condition, the clearing should be ignored*3 but it
will be carried out.
Notes: *1 For the SH7046-Series and SH7047-Series, n = 0 to
6; for the SH7144-Series, n = 0 to 3.
*2 The POEnF bits are set when the signals input to the
respective POEn pins satisfy the conditions that are
specified by the POEnM1 and POEnM0 of the
ICSR1 and ICSR2.
*3 The correct operation is that clearing of the POEnF
bits is only possible after “1” is read from them in
order to prevent accidental clearing.
(b) Regarding the OSF bit
The same symptom applies to the OSF bits of the output level
control/status register (OCSR).
(2) To Avoid This Problem
Please clear the POEnF bits or the OSF bit in these steps: first
execute a read for ICSR1, ICSR2, or OCSR, then write “0” to
the bits that had a read value of “1” to clear them while writing
“1” to other bits. If this procedure is not followed, the POEnF
bits and the OSF bit may be cleared unexpectedly if their
setting by hardware and reading occur simultaneously.
10.3.2 Receive Data
Register (RDR)
280
280
Description added
... RDR cannot be written to by the CPU. The initial value of
RDR is H'00.
10.3.4 Transmit Data
Register (TDR)
Description added
... Although TDR can be read or written to by the CPU at all
times, to achieve reliable serial transmission, write transmit
data to TDR for only once after confirming that the TDRE bit in
SSR is set to 1. The initial value of TDR is H'FF.
Rev.2.00 Sep. 27, 2007 Page x of xxxiv
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Item
Page
Revision (See Manual for Details)
11.1 Features
325
Description added
• Conversion time: 6.7 μs per channel (at Pφ = 20-MHz
operation)
5.4 μs per channel (at Pφ = 25-MHz
operation)
11.7.2 Permissible
Signal Source
Impedance
340
Description amended
This LSI's analog input is designed such that conversion
accuracy is guaranteed for an input signal for which the signal
source impedance is 1 kΩ or less, or 3 kΩ or less. This
specification is provided to enable the A/D converter's sample-
and-hold circuit input capacitance to be charged within the
sampling time; if the sensor output impedance exceeds 1 kΩ or
3 kΩ, charging may be insufficient and it may not be possible to
guarantee A/D conversion accuracy. ...
17.3.1 Sleep Mode
395
Description added
Notes on Using Sleep
Mode
• There are 4 conditions to clear sleep mode.
(1) Clearing by an interrupt
(2) Clearing by DTC address error
(3) Clearing by the power-on reset
(4) Clearing by the manual reset
When clearing sleep mode by (1) or (2), CPU may run out of
control. Please clear sleep mode by (3) or (4), don't use (1) or
(2).
• Do not use DTC module or AUD module during sleep mode.
Rev.2.00 Sep. 27, 2007 Page xi of xxxiv
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All trademarks and registered trademarks are the property of their respective owners.
Rev.2.00 Sep. 27, 2007 Page xii of xxxiv
REJ09B0394-0200
Contents
Section 1 Overview............................................................................................... 1
1.1 Features..................................................................................................................................1
1.2 Internal Block Diagram..........................................................................................................3
1.3 Pin Arrangement ....................................................................................................................4
1.4 Pin Functions .........................................................................................................................5
1.5 Differences from SH7046 Group...........................................................................................9
Section 2 CPU..................................................................................................... 11
2.1 Features................................................................................................................................11
2.2 Register Configuration......................................................................................................... 11
2.2.1 General Registers (Rn)............................................................................................13
2.2.2 Control Registers ....................................................................................................13
2.2.3 System Registers.....................................................................................................14
2.2.4 Initial Values of Registers.......................................................................................15
2.3 Data Formats........................................................................................................................15
2.3.1 Data Format in Registers.........................................................................................15
2.3.2 Data Formats in Memory........................................................................................16
2.3.3 Immediate Data Format ..........................................................................................16
2.4 Instruction Features..............................................................................................................17
2.4.1 RISC-Type Instruction Set......................................................................................17
2.4.2 Addressing Modes ..................................................................................................20
2.4.3 Instruction Format...................................................................................................24
2.5 Instruction Set ......................................................................................................................26
2.5.1 Instruction Set by Classification .............................................................................26
2.6 Processing States..................................................................................................................41
2.6.1 State Transitions......................................................................................................41
Section 3 MCU Operating Modes....................................................................... 43
3.1 Selection of Operating Modes..............................................................................................43
3.2 Input/Output Pins.................................................................................................................44
3.3 Explanation of Operating Modes .........................................................................................44
3.3.1 Mode 3 (Single chip mode).....................................................................................44
3.3.2 Clock Mode.............................................................................................................44
3.4 Address Map ........................................................................................................................45
3.5 Initial State of This LSI........................................................................................................46
Section 4 Clock Pulse Generator ........................................................................ 47
4.1 Oscillator..............................................................................................................................47
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4.1.1 Connecting Crystal Resonator ................................................................................ 47
4.1.2 External Clock Input Method.................................................................................. 49
4.2 Function for Detecting Oscillator Halt................................................................................. 49
4.3 Usage Notes ......................................................................................................................... 50
4.3.1 Note on Crystal Resonator...................................................................................... 50
4.3.2 Notes on Board Design........................................................................................... 50
Section 5 Exception Processing...........................................................................53
5.1 Overview.............................................................................................................................. 53
5.1.1 Types of Exception Processing and Priority ........................................................... 53
5.1.2 Exception Processing Operations............................................................................ 54
5.1.3 Exception Processing Vector Table ........................................................................ 55
5.2 Resets ................................................................................................................................ 57
5.2.1 Types of Reset ........................................................................................................ 57
5.2.2 Power-On Reset ...................................................................................................... 57
5.2.3 Manual Reset .......................................................................................................... 58
5.3 Address Errors ..................................................................................................................... 59
5.3.1 Cause of Address Error Exception.......................................................................... 59
5.3.2 Address Error Exception Processing....................................................................... 60
5.4 Interrupts.............................................................................................................................. 60
5.4.1 Interrupt Sources..................................................................................................... 60
5.4.2 Interrupt Priority Level ........................................................................................... 61
5.4.3 Interrupt Exception Processing............................................................................... 61
5.5 Exceptions Triggered by Instructions .................................................................................. 62
5.5.1 Types of Exceptions Triggered by Instructions ...................................................... 62
5.5.2 Trap Instructions..................................................................................................... 62
5.5.3 Illegal Slot Instructions........................................................................................... 63
5.5.4 General Illegal Instructions..................................................................................... 63
5.6 Cases when Exception Sources are Not Accepted............................................................... 64
5.6.1 Immediately after Delayed Branch Instruction....................................................... 64
5.6.2 Immediately after Interrupt-Disabled Instruction ................................................... 64
5.7 Stack Status after Exception Processing Ends ..................................................................... 65
5.8 Usage Notes ......................................................................................................................... 66
5.8.1 Value of Stack Pointer (SP) .................................................................................... 66
5.8.2 Value of Vector Base Register (VBR).................................................................... 66
5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing......... 66
Section 6 Interrupt Controller (INTC).................................................................67
6.1 Features................................................................................................................................ 67
6.2 Input/Output Pins................................................................................................................. 68
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6.3 Register Descriptions ...........................................................................................................68
6.3.1 Interrupt Control Register 1 (ICR1)........................................................................69
6.3.2 Interrupt Control Register 2 (ICR2)........................................................................70
6.3.3 IRQ Status Register (ISR).......................................................................................72
6.3.4 Interrupt Priority Registers A, D to I (IPRA, IPRD to IPRI) ..................................73
6.4 Interrupt Sources..................................................................................................................75
6.4.1 External Interrupts ..................................................................................................75
6.4.2 On-Chip Peripheral Module Interrupts ...................................................................77
6.5 Interrupt Exception Processing Vectors Table.....................................................................77
6.6 Operation..............................................................................................................................81
6.6.1 Interrupt Sequence ..................................................................................................81
6.6.2 Stack after Interrupt Exception Processing .............................................................83
6.7 Interrupt Response Time......................................................................................................84
Section 7 Bus State Controller (BSC)................................................................. 87
7.1 Features................................................................................................................................87
7.2 Input/output Pin....................................................................................................................87
7.3 Register ................................................................................................................................87
7.4 Address Map ........................................................................................................................88
7.5 Register Description.............................................................................................................89
7.5.1 Bus Control Register 1 (BCR1) ..............................................................................89
7.6 On-chip Peripheral I/O Register Access ..............................................................................90
Section 8 Multi-Function Timer Pulse Unit (MTU)........................................... 91
8.1 Features................................................................................................................................91
8.2 Input/Output Pins.................................................................................................................95
8.3 Register Descriptions ...........................................................................................................96
8.3.1 Timer Control Register (TCR)................................................................................98
8.3.2 Timer Mode Register (TMDR).............................................................................102
8.3.3 Timer I/O Control Register (TIOR) ......................................................................104
8.3.4 Timer Interrupt Enable Register (TIER)...............................................................122
8.3.5 Timer Status Register (TSR).................................................................................124
8.3.6 Timer Counter (TCNT).........................................................................................126
8.3.7 Timer General Register (TGR) .............................................................................127
8.3.8 Timer Start Register (TSTR).................................................................................127
8.3.9 Timer Synchro Register (TSYR) ..........................................................................128
8.3.10 Timer Output Master Enable Register (TOER) ....................................................130
8.3.11 Timer Output Control Register (TOCR)...............................................................131
8.3.12 Timer Gate Control Register (TGCR)...................................................................133
8.3.13 Timer Subcounter (TCNTS) .................................................................................135
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8.3.14 Timer Dead Time Data Register (TDDR)............................................................. 135
8.3.15 Timer Period Data Register (TCDR) .................................................................... 135
8.3.16 Timer Period Buffer Register (TCBR).................................................................. 135
8.3.17 Bus Master Interface............................................................................................. 136
8.4 Operation ........................................................................................................................... 137
8.4.1 Basic Functions..................................................................................................... 137
8.4.2 Synchronous Operation......................................................................................... 142
8.4.3 Buffer Operation................................................................................................... 145
8.4.4 Cascaded Operation .............................................................................................. 149
8.4.5 PWM Modes......................................................................................................... 150
8.4.6 Phase Counting Mode........................................................................................... 156
8.4.7 Reset-Synchronized PWM Mode.......................................................................... 163
8.4.8 Complementary PWM Mode................................................................................ 167
8.5 Interrupt Sources................................................................................................................ 192
8.5.1 Interrupts and Priorities......................................................................................... 192
8.5.2 A/D Converter Activation..................................................................................... 194
8.6 Operation Timing............................................................................................................... 195
8.6.1 Input/Output Timing............................................................................................. 195
8.6.2 Interrupt Signal Timing......................................................................................... 200
8.7 Usage Notes ....................................................................................................................... 204
8.7.1 Module Standby Mode Setting ............................................................................. 204
8.7.2 Input Clock Restrictions ....................................................................................... 204
8.7.3 Caution on Period Setting..................................................................................... 205
8.7.4 Contention between TCNT Write and Clear Operations...................................... 205
8.7.5 Contention between TCNT Write and Increment Operations............................... 206
8.7.6 Contention between TGR Write and Compare Match.......................................... 207
8.7.7 Contention between Buffer Register Write and Compare Match ......................... 208
8.7.8 Contention between TGR Read and Input Capture............................................... 210
8.7.9 Contention between TGR Write and Input Capture.............................................. 211
8.7.10 Contention between Buffer Register Write and Input Capture............................. 212
8.7.11 TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection .... 212
8.7.12 Counter Value during Complementary PWM Mode Stop.................................... 214
8.7.13 Buffer Operation Setting in Complementary PWM Mode ................................... 214
8.7.14 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .................. 215
8.7.15 Overflow Flags in Reset Sync PWM Mode.......................................................... 216
8.7.16 Contention between Overflow/Underflow and Counter Clearing......................... 217
8.7.17 Contention between TCNT Write and Overflow/Underflow................................ 218
8.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to
Reset-Synchronous PWM Mode........................................................................... 218
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8.7.19 Output Level in Complementary PWM Mode and
Reset-Synchronous PWM Mode...........................................................................219
8.7.20 Interrupts in Module Standby Mode .....................................................................219
8.7.21 Simultaneous Input Capture of TCNT_1 and TCNT_2 in Cascade Connection...219
8.8 MTU Output Pin Initialization...........................................................................................220
8.8.1 Operating Modes...................................................................................................220
8.8.2 Reset Start Operation ............................................................................................220
8.8.3 Operation in Case of Re-Setting Due to Error During Operation, Etc..................221
8.8.4 Overview of Initialization Procedures and Mode Transitions
in Case of Error during Operation, Etc. ................................................................222
8.9 Port Output Enable (POE)..................................................................................................252
8.9.1 Features.................................................................................................................252
8.9.2 Pin Configuration..................................................................................................254
8.9.3 Register Configuration..........................................................................................254
8.9.4 Operation ..............................................................................................................259
8.9.5 Usage Note............................................................................................................262
Section 9 Watchdog Timer ............................................................................... 263
9.1 Features..............................................................................................................................263
9.2 Input/Output Pin.................................................................................................................264
9.3 Register Descriptions .........................................................................................................265
9.3.1 Timer Counter (TCNT).........................................................................................265
9.3.2 Timer Control/Status Register (TCSR).................................................................266
9.3.3 Reset Control/Status Register (RSTCSR).............................................................268
9.4 Operation............................................................................................................................269
9.4.1 Watchdog Timer Mode.........................................................................................269
9.4.2 Interval Timer Mode.............................................................................................271
9.4.3 Clearing Software Standby Mode.........................................................................271
9.4.4 Timing of Setting the Overflow Flag (OVF) ........................................................272
9.4.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF).........................272
9.5 Interrupt Source..................................................................................................................273
9.6 Usage Notes .......................................................................................................................273
9.6.1 Notes on Register Access......................................................................................273
9.6.2 TCNT Write and Increment Contention................................................................275
9.6.3 Changing CKS2 to CKS0 Bit Values....................................................................275
9.6.4 Changing between Watchdog Timer/Interval Timer Modes.................................275
9.6.5 System Reset by WDTOVF Signal.......................................................................276
9.6.6 Internal Reset in Watchdog Timer Mode..............................................................276
9.6.7 Manual Reset in Watchdog Timer Mode..............................................................276
9.6.8 Notes on Using WDTOVF pin..............................................................................276
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Section 10 Serial Communication Interface (SCI)............................................277
10.1 Features.............................................................................................................................. 277
10.2 Input/Output Pins............................................................................................................... 279
10.3 Register Descriptions......................................................................................................... 279
10.3.1 Receive Shift Register (RSR) ............................................................................... 280
10.3.2 Receive Data Register (RDR)............................................................................... 280
10.3.3 Transmit Shift Register (TSR).............................................................................. 280
10.3.4 Transmit Data Register (TDR).............................................................................. 280
10.3.5 Serial Mode Register (SMR) ................................................................................ 281
10.3.6 Serial Control Register (SCR)............................................................................... 283
10.3.7 Serial Status Register (SSR) ................................................................................. 285
10.3.8 Serial Direction Control Register (SDCR)............................................................ 287
10.3.9 Bit Rate Register (BRR) ....................................................................................... 287
10.4 Operation in Asynchronous Mode ..................................................................................... 296
10.4.1 Data Transfer Format............................................................................................ 296
10.4.2 Receive Data Sampling Timing and Reception Margin
in Asynchronous Mode......................................................................................... 298
10.4.3 Clock..................................................................................................................... 299
10.4.4 SCI Initialization (Asynchronous Mode).............................................................. 300
10.4.5 Data Transmission (Asynchronous Mode)............................................................ 301
10.4.6 Serial Data Reception (Asynchronous Mode)....................................................... 303
10.5 Multiprocessor Communication Function.......................................................................... 307
10.5.1 Multiprocessor Serial Data Transmission............................................................. 309
10.5.2 Multiprocessor Serial Data Reception .................................................................. 310
10.6 Operation in Clocked Synchronous Mode ......................................................................... 313
10.6.1 Clock..................................................................................................................... 313
10.6.2 SCI Initialization (Clocked Synchronous Mode).................................................. 314
10.6.3 Serial Data Transmission (Clocked Synchronous Mode) ..................................... 315
10.6.4 Serial Data Reception (Clocked Synchronous Mode)........................................... 318
10.6.5 Simultaneous Serial Data Transmission and Reception
(Clocked Synchronous Mode) .............................................................................. 320
10.7 Interrupts Sources .............................................................................................................. 322
10.7.1 Interrupts in Normal Serial Communication Interface Mode ............................... 322
10.8 Usage Notes ....................................................................................................................... 323
10.8.1 TDR Write and TDRE Flag .................................................................................. 323
10.8.2 Module Standby Mode Setting ............................................................................. 323
10.8.3 Break Detection and Processing (Asynchronous Mode Only).............................. 323
10.8.4 Sending a Break Signal (Asynchronous Mode Only)........................................... 323
10.8.5 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only) ..................................................................... 324
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10.8.6 Cautions on Clocked Synchronous External Clock Mode....................................324
10.8.7 Caution on Clocked Synchronous Internal Clock Mode.......................................324
Section 11 A/D Converter................................................................................. 325
11.1 Features..............................................................................................................................325
11.2 Input/Output Pins...............................................................................................................327
11.3 Register Descriptions .........................................................................................................328
11.3.1 A/D Data Registers 8 to 15 (ADDR8 to ADDR15)..............................................328
11.3.2 A/D Control/Status Registers_0 and _1 (ADCSR_0 and ADCSR_1) ..................329
11.3.3 A/D Control Registers_0 and _1 (ADCR_0 and ADCR_1)..................................330
11.3.4 A/D Trigger Select Register (ADTSR).................................................................332
11.4 Operation............................................................................................................................333
11.4.1 Single Mode..........................................................................................................333
11.4.2 Continuous Scan Mode.........................................................................................333
11.4.3 Single-Cycle Scan Mode.......................................................................................335
11.4.4 Input Sampling and A/D Conversion Time...........................................................335
11.4.5 A/D Converter Activation by MTU ......................................................................337
11.4.6 External Trigger Input Timing..............................................................................337
11.5 Interrupt Sources................................................................................................................338
11.6 Definitions of A/D Conversion Accuracy..........................................................................338
11.7 Usage Notes .......................................................................................................................340
11.7.1 Module Standby Mode Setting .............................................................................340
11.7.2 Permissible Signal Source Impedance ..................................................................340
11.7.3 Influences on Absolute Accuracy .........................................................................340
11.7.4 Range of Analog Power Supply and Other Pin Settings.......................................341
11.7.5 Notes on Board Design .........................................................................................341
11.7.6 Notes on Noise Countermeasures .........................................................................341
Section 12 Compare Match Timer (CMT)........................................................ 343
12.1 Features..............................................................................................................................343
12.2 Register Descriptions .........................................................................................................344
12.2.1 Compare Match Timer Start Register (CMSTR) ..................................................344
12.2.2 Compare Match Timer Control/Status Register_0 and _1
(CMCSR_0, CMCSR_1) ......................................................................................345
12.2.3 Compare Match Timer Counter_0 and _1 (CMCNT_0, CMCNT_1)...................346
12.2.4 Compare Match Timer Constant Register_0 and _1 (CMCOR_0, CMCOR_1)...346
12.3 Operation............................................................................................................................346
12.3.1 Cyclic Count Operation ........................................................................................346
12.3.2 CMCNT Count Timing.........................................................................................347
12.4 Interrupts............................................................................................................................347
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12.4.1 Interrupt Sources................................................................................................... 347
12.4.2 Compare Match Flag Set Timing.......................................................................... 347
12.4.3 Compare Match Flag Clear Timing ...................................................................... 348
12.5 Usage Notes ....................................................................................................................... 349
12.5.1 Contention between CMCNT Write and Compare Match.................................... 349
12.5.2 Contention between CMCNT Word Write and Incrementation ........................... 350
12.5.3 Contention between CMCNT Byte Write and Incrementation............................. 351
Section 13 Pin Function Controller (PFC) ........................................................353
13.1 Register Descriptions......................................................................................................... 360
13.1.1 Port A I/O Register L (PAIORL).......................................................................... 360
13.1.2 Port A Control Registers L3 to L1 (PACRL3 to PACRL1).................................. 361
13.1.3 Port B I/O Register (PBIOR) ................................................................................ 364
13.1.4 Port B Control Registers 1 and 2 (PBCR1 and PBCR2)....................................... 365
13.1.5 Port E I/O Registers L and H (PEIORL and PEIORH)......................................... 366
13.1.6 Port E Control Registers L1, L2, and H (PECRL1, PECRL2, and PECRH) ........ 366
13.2 Usage Notes ....................................................................................................................... 370
13.2.1 Note on PFC Setting ............................................................................................. 370
13.2.2 Note on PFC Setting Order................................................................................... 370
Section 14 I/O Ports...........................................................................................371
14.1 Port A .............................................................................................................................. 371
14.1.1 Register Description.............................................................................................. 372
14.1.2 Port A Data Register L (PADRL)......................................................................... 372
14.2 Port B .............................................................................................................................. 374
14.2.1 Register Description.............................................................................................. 374
14.2.2 Port B Data Register (PBDR) ............................................................................... 374
14.3 Port E .............................................................................................................................. 376
14.3.1 Register Descriptions............................................................................................ 377
14.3.2 Port E Data Registers H and L (PEDRH and PEDRL)......................................... 377
14.4 Port F .............................................................................................................................. 379
14.4.1 Register Description.............................................................................................. 379
14.4.2 Port F Data Register (PFDR) ................................................................................ 379
14.5 Port G .............................................................................................................................. 381
14.5.1 Register Description.............................................................................................. 381
14.5.2 Port G Data Register (PGDR)............................................................................... 381
Section 15 Mask ROM ......................................................................................383
15.1 Usage Note......................................................................................................................... 383
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Section 16 RAM ............................................................................................... 385
16.1 Usage Note.........................................................................................................................385
Section 17 Power-Down Modes ....................................................................... 387
17.1 Input/Output Pins...............................................................................................................389
17.2 Register Descriptions .........................................................................................................390
17.2.1 Standby Control Register (SBYCR) .....................................................................390
17.2.2 System Control Register (SYSCR) .......................................................................392
17.2.3 Module Standby Control Register 1 and 2 (MSTCR1 and MSTCR2)..................393
17.3 Operation............................................................................................................................395
17.3.1 Sleep Mode ...........................................................................................................395
17.3.2 Software Standby Mode........................................................................................396
17.3.3 Module Standby Mode..........................................................................................398
17.4 Usage Notes .......................................................................................................................399
17.4.1 I/O Port Status.......................................................................................................399
17.4.2 Current Consumption during Oscillation Stabilization Wait Period.....................399
17.4.3 On-Chip Peripheral Module Interrupt...................................................................399
17.4.4 Writing to MSTCR1 and MSTCR2 ......................................................................399
Section 18 List of Registers .............................................................................. 401
18.1 Register Addresses (Order of Address)..............................................................................401
18.2 Register Bits.......................................................................................................................408
18.3 Register States in Each Operating Mode............................................................................415
Section 19 Electrical Characteristics ................................................................ 421
19.1 Absolute Maximum Ratings ..............................................................................................421
19.2 DC Characteristics .............................................................................................................422
19.3 AC Characteristics .............................................................................................................425
19.3.1 Test Conditions for the AC Characteristics...........................................................425
19.3.2 Clock Timing ........................................................................................................426
19.3.3 Control Signal Timing ..........................................................................................428
19.3.4 Multi-Function Timer Pulse Unit (MPU) Timing.................................................431
19.3.5 I/O Port Timing.....................................................................................................432
19.3.6 Watchdog Timer (WDT) Timing..........................................................................433
19.3.7 Serial Communication Interface (SCI) Timing.....................................................434
19.3.8 Output Enable (POE) Timing ...............................................................................436
19.3.9 A/D Converter Timing..........................................................................................436
19.4 A/D Converter Characteristics ...........................................................................................438
Appendix A Pin States...................................................................................... 439
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Appendix B Product Lineup..............................................................................441
Appendix C Package Dimensions .....................................................................443
Index
.........................................................................................................445
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Figures
Section 1 Overview
Figure 1.1
Figure 1.2
Internal Block Diagram of SH7101............................................................................3
SH7101 Pin Arrangement ..........................................................................................4
Section 2 CPU
Figure 2.1
Figure 2.2
Figure 2.3
Figure 2.4
CPU Internal Registers.............................................................................................12
Data Format in Registers..........................................................................................15
Data Formats in Memory .........................................................................................16
Transitions between Processing States.....................................................................41
Section 3 MCU Operating Modes
Figure 3.1
Address Map for SH7101 Mask ROM Version .......................................................45
Section 4 Clock Pulse Generator
Figure 4.1
Figure 4.2
Figure 4.3
Figure 4.4
Figure 4.5
Figure 4.6
Block Diagram of Clock Pulse Generator................................................................47
Connection of Crystal Resonator (Example)............................................................48
Crystal Resonator Equivalent Circuit.......................................................................48
Example of External Clock Connection...................................................................49
Cautions for Oscillator Circuit System Board Design..............................................50
Recommended External Circuitry around PLL........................................................51
Section 6 Interrupt Controller (INTC)
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4
Figure 6.5
INTC Block Diagram...............................................................................................67
Block Diagram of IRQ3 to IRQ0 Interrupts Control................................................76
Interrupt Sequence Flowchart ..................................................................................82
Stack after Interrupt Exception Processing ..............................................................83
Example of the Pipeline Operation when an IRQ Interrupt is Accepted..................85
Section 8 Multi-Function Timer Pulse Unit (MTU)
Figure 8.1
Figure 8.2
Figure 8.3
Figure 8.4
Figure 8.5
Figure 8.6
Figure 8.7
Figure 8.8
Figure 8.9
Block Diagram of MTU ...........................................................................................94
Complementary PWM Mode Output Level Example ............................................132
Example of Counter Operation Setting Procedure .................................................137
Free-Running Counter Operation...........................................................................138
Periodic Counter Operation....................................................................................139
Example of Setting Procedure for Waveform Output by Compare Match.............139
Example of 0 Output/1 Output Operation ..............................................................140
Example of Toggle Output Operation ....................................................................140
Example of Input Capture Operation Setting Procedure........................................141
Figure 8.10 Example of Input Capture Operation .....................................................................142
Figure 8.11 Example of Synchronous Operation Setting Procedure .........................................143
Figure 8.12 Example of Synchronous Operation.......................................................................144
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Figure 8.13 Compare Match Buffer Operation.......................................................................... 145
Figure 8.14 Input Capture Buffer Operation ............................................................................. 146
Figure 8.15 Example of Buffer Operation Setting Procedure.................................................... 146
Figure 8.16 Example of Buffer Operation (1) ........................................................................... 147
Figure 8.17 Example of Buffer Operation (2) ........................................................................... 148
Figure 8.18 Cascaded Operation Setting Procedure.................................................................. 149
Figure 8.19 Example of Cascaded Operation ............................................................................ 150
Figure 8.20 Example of PWM Mode Setting Procedure........................................................... 152
Figure 8.21 Example of PWM Mode Operation (1).................................................................. 153
Figure 8.22 Example of PWM Mode Operation (2).................................................................. 154
Figure 8.23 Example of PWM Mode Operation (3).................................................................. 155
Figure 8.24 Example of Phase Counting Mode Setting Procedure............................................ 157
Figure 8.25 Example of Phase Counting Mode 1 Operation..................................................... 157
Figure 8.26 Example of Phase Counting Mode 2 Operation..................................................... 158
Figure 8.27 Example of Phase Counting Mode 3 Operation..................................................... 159
Figure 8.28 Example of Phase Counting Mode 4 Operation..................................................... 160
Figure 8.29 Phase Counting Mode Application Example ......................................................... 162
Figure 8.30 Procedure for Selecting the Reset-Synchronized PWM Mode............................... 165
Figure 8.31 Reset-Synchronized PWM Mode Operation Example
(When the TOCR's OLSN = 1 and OLSP = 1)....................................................... 166
Figure 8.32 Block Diagram of Channels 3 and 4 in Complementary PWM Mode................... 169
Figure 8.33 Example of Complementary PWM Mode Setting Procedure................................. 171
Figure 8.34 Complementary PWM Mode Counter Operation................................................... 173
Figure 8.35 Example of Complementary PWM Mode Operation............................................. 175
Figure 8.36 Example of PWM Cycle Updating......................................................................... 178
Figure 8.37 Example of Data Update in Complementary PWM Mode..................................... 179
Figure 8.38 Example of Initial Output in Complementary PWM Mode (1).............................. 180
Figure 8.39 Example of Initial Output in Complementary PWM Mode (2).............................. 181
Figure 8.40 Example of Complementary PWM Mode Waveform Output (1) .......................... 183
Figure 8.41 Example of Complementary PWM Mode Waveform Output (2) .......................... 183
Figure 8.42 Example of Complementary PWM Mode Waveform Output (3) .......................... 184
Figure 8.43 Example of Complementary PWM Mode 0% and 100% Waveform Output (1)... 184
Figure 8.44 Example of Complementary PWM Mode 0% and 100% Waveform Output (2)... 185
Figure 8.45 Example of Complementary PWM Mode 0% and 100% Waveform Output (3)... 185
Figure 8.46 Example of Complementary PWM Mode 0% and 100% Waveform Output (4)... 186
Figure 8.47 Example of Complementary PWM Mode 0% and 100% Waveform Output (5)... 186
Figure 8.48 Example of Toggle Output Waveform Synchronized with PWM Output.............. 187
Figure 8.49 Counter Clearing Synchronized with Another Channel......................................... 188
Figure 8.50 Example of Output Phase Switching by External Input (1) ................................... 189
Figure 8.51 Example of Output Phase Switching by External Input (2) ................................... 190
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Figure 8.52 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1)...190
Figure 8.53 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2)...191
Figure 8.54 Count Timing in Internal Clock Operation.............................................................195
Figure 8.55 Count Timing in External Clock Operation ...........................................................195
Figure 8.56 Count Timing in External Clock Operation (Phase Counting Mode).....................196
Figure 8.57 Output Compare Output Timing (Normal Mode/PWM Mode)..............................196
Figure 8.58 Output Compare Output Timing
(Complementary PWM Mode/Reset Synchronous PWM Mode) ..........................197
Figure 8.59 Input Capture Input Signal Timing.........................................................................197
Figure 8.60 Counter Clear Timing (Compare Match) ...............................................................198
Figure 8.61 Counter Clear Timing (Input Capture)...................................................................198
Figure 8.62 Buffer Operation Timing (Compare Match) ..........................................................199
Figure 8.63 Buffer Operation Timing (Input Capture) ..............................................................199
Figure 8.64 TGI Interrupt Timing (Compare Match) ................................................................200
Figure 8.65 TGI Interrupt Timing (Input Capture)....................................................................201
Figure 8.66 TCIV Interrupt Setting Timing...............................................................................202
Figure 8.67 TCIU Interrupt Setting Timing...............................................................................202
Figure 8.68 Timing for Status Flag Clearing by the CPU .........................................................203
Figure 8.69 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode.................204
Figure 8.70 Contention between TCNT Write and Clear Operations........................................205
Figure 8.71 Contention between TCNT Write and Increment Operations ................................206
Figure 8.72 Contention between TGR Write and Compare Match ...........................................207
Figure 8.73 Contention between Buffer Register Write and Compare Match (Channel 0).......208
Figure 8.74 Contention between Buffer Register Write and Compare Match
(Channels 3 and 4)..................................................................................................209
Figure 8.75 Contention between TGR Read and Input Capture................................................210
Figure 8.76 Contention between TGR Write and Input Capture ...............................................211
Figure 8.77 Contention between Buffer Register Write and Input Capture...............................212
Figure 8.78 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection..213
Figure 8.79 Counter Value during Complementary PWM Mode Stop .....................................214
Figure 8.80 Buffer Operation and Compare-Match Flags in Reset Sync PWM Mode..............215
Figure 8.81 Reset Sync PWM Mode Overflow Flag.................................................................216
Figure 8.82 Contention between Overflow and Counter Clearing ............................................217
Figure 8.83 Contention between TCNT Write and Overflow....................................................218
Figure 8.84 Error Occurrence in Normal Mode, Recovery in Normal Mode............................223
Figure 8.85 Error Occurrence in Normal Mode, Recovery in PWM Mode 1............................224
Figure 8.86 Error Occurrence in Normal Mode, Recovery in PWM Mode 2............................225
Figure 8.87 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode...............226
Figure 8.88 Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode....227
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Figure 8.89 Error Occurrence in Normal Mode,
Recovery in Reset-Synchronous PWM Mode........................................................ 228
Figure 8.90 Error Occurrence in PWM Mode 1, Recovery in Normal Mode ........................... 229
Figure 8.91 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 ........................... 230
Figure 8.92 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2 ........................... 231
Figure 8.93 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode............... 232
Figure 8.94 Error Occurrence in PWM Mode 1, Recovery in Complementary PWM Mode.... 233
Figure 8.95 Error Occurrence in PWM Mode 1,
Recovery in Reset-Synchronous PWM Mode........................................................ 234
Figure 8.96 Error Occurrence in PWM Mode 2, Recovery in Normal Mode ........................... 235
Figure 8.97 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1 ........................... 236
Figure 8.98 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2 ........................... 237
Figure 8.99 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode............... 238
Figure 8.100 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode............... 239
Figure 8.101 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1............... 240
Figure 8.102 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2............... 241
Figure 8.103 Error Occurrence in Phase Counting Mode,
Recovery in Phase Counting Mode........................................................................ 242
Figure 8.104 Error Occurrence in Complementary PWM Mode, Recovery in Normal Mode.... 243
Figure 8.105 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1.... 244
Figure 8.106 Error Occurrence in Complementary PWM Mode,
Recovery in Complementary PWM Mode............................................................. 245
Figure 8.107 Error Occurrence in Complementary PWM Mode,
Recovery in Complementary PWM Mode............................................................. 246
Figure 8.108 Error Occurrence in Complementary PWM Mode,
Recovery in Reset-Synchronous PWM Mode........................................................ 247
Figure 8.109 Error Occurrence in Reset-Synchronous PWM Mode,
Recovery in Normal Mode..................................................................................... 248
Figure 8.110 Error Occurrence in Reset-Synchronous PWM Mode,
Recovery in PWM Mode 1..................................................................................... 249
Figure 8.111 Error Occurrence in Reset-Synchronous PWM Mode,
Recovery in Complementary PWM Mode............................................................. 250
Figure 8.112 Error Occurrence in Reset-Synchronous PWM Mode,
Recovery in Reset-Synchronous PWM Mode........................................................ 251
Figure 8.113 POE Block Diagram............................................................................................... 253
Figure 8.114 Low-Level Detection Operation............................................................................. 259
Figure 8.115 Output-Level Detection Operation......................................................................... 260
Figure 8.116 Falling Edge Detection Operation.......................................................................... 261
Section 9 Watchdog Timer
Figure 9.1
Block Diagram of WDT......................................................................................... 264
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Figure 9.2
Figure 9.3
Figure 9.4
Figure 9.5
Figure 9.6
Figure 9.7
Figure 9.8
Figure 9.9
Operation in Watchdog Timer Mode .....................................................................270
Operation in Interval Timer Mode .........................................................................271
Timing of Setting OVF...........................................................................................272
Timing of Setting WOVF.......................................................................................272
Writing to TCNT and TCSR ..................................................................................273
Writing to RSTCSR ...............................................................................................274
Contention between TCNT Write and Increment...................................................275
Example of System Reset Circuit Using WDTOVF Signal ...................................276
Section 10 Serial Communication Interface (SCI)
Figure 10.1 Block Diagram of SCI............................................................................................278
Figure 10.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits).................................................296
Figure 10.3 Receive Data Sampling Timing in Asynchronous Mode .......................................298
Figure 10.4 Relation between Output Clock and Transmit Data Phase
(Asynchronous Mode)............................................................................................299
Figure 10.5 Sample SCI Initialization Flowchart ......................................................................300
Figure 10.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)...................................................301
Figure 10.7 Sample Serial Transmission Flowchart..................................................................302
Figure 10.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit)..................................................303
Figure 10.9 Sample Serial Reception Data Flowchart (1) .........................................................305
Figure 10.9 Sample Serial Reception Data Flowchart (2) .........................................................306
Figure 10.10 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) ...........................................308
Figure 10.11 Sample Multiprocessor Serial Transmission Flowchart.........................................309
Figure 10.12 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)...............................310
Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (1).........................................311
Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (2).........................................312
Figure 10.14 Data Format in Clocked Synchronous Communication (For LSB-First) ...............313
Figure 10.15 Sample SCI Initialization Flowchart ......................................................................314
Figure 10.16 Sample SCI Transmission Operation in Clocked Synchronous Mode...................316
Figure 10.17 Sample Serial Transmission Flowchart..................................................................317
Figure 10.18 Example of SCI Operation in Reception................................................................318
Figure 10.19 Sample Serial Reception Flowchart .......................................................................319
Figure 10.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations .......321
Section 11 A/D Converter
Figure 11.1 Block Diagram of A/D Converter (For One Module) ............................................326
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Figure 11.2 Operation Example in Continuous Scan Mode
(Three Channels Selected) (AN8 to AN10) ........................................................... 334
Figure 11.3 A/D Conversion Timing......................................................................................... 336
Figure 11.4 External Trigger Input Timing ............................................................................... 337
Figure 11.5 Definitions of A/D Conversion Accuracy.............................................................. 339
Figure 11.6 Definitions of A/D Conversion Accuracy.............................................................. 339
Figure 11.7 Example of Analog Input Circuit........................................................................... 340
Figure 11.8 Example of Analog Input Protection Circuit.......................................................... 342
Figure 11.9 Analog Input Pin Equivalent Circuit...................................................................... 342
Section 12 Compare Match Timer (CMT)
Figure 12.1 CMT Block Diagram.............................................................................................. 343
Figure 12.2 Counter Operation.................................................................................................. 346
Figure 12.3 Count Timing ......................................................................................................... 347
Figure 12.4 CMF Set Timing .................................................................................................... 348
Figure 12.5 Timing of CMF Clear by CPU............................................................................... 348
Figure 12.6 CMCNT Write and Compare Match Contention ................................................... 349
Figure 12.7 CMCNT Word Write and Increment Contention................................................... 350
Figure 12.8 CMCNT Byte Write and Increment Contention..................................................... 351
Section 14 I/O Ports
Figure 14.1 Port A..................................................................................................................... 371
Figure 14.2 Port B ..................................................................................................................... 374
Figure 14.3 Port E...................................................................................................................... 376
Figure 14.4 Port F...................................................................................................................... 379
Figure 14.5 Port G..................................................................................................................... 381
Section 15 Mask ROM
Figure 15.1 Mask ROM Block Diagram ................................................................................... 383
Section 17 Power-Down Modes
Figure 17.1 Mode Transition Diagram...................................................................................... 389
Figure 17.2 NMI Timing in Software Standby Mode................................................................ 398
Section 19 Electrical Characteristics
Figure 19.1 Output Load Circuit ............................................................................................... 425
Figure 19.2 System Clock Timing............................................................................................. 427
Figure 19.3 EXTAL Clock Input Timing.................................................................................. 427
Figure 19.4 Oscillation Settling Time ....................................................................................... 427
Figure 19.5 Reset Input Timing................................................................................................. 429
Figure 19.6 Reset Input Timing................................................................................................. 429
Figure 19.7 Interrupt Signal Input Timing................................................................................. 430
Figure 19.8 Interrupt Signal Output Timing.............................................................................. 430
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Figure 19.9 MTU Input/Output Timing.....................................................................................431
Figure 19.10 MTU Clock Input Timing ......................................................................................432
Figure 19.11 I/O Port Input/Output Timing.................................................................................433
Figure 19.12 WDT Timing..........................................................................................................433
Figure 19.13 Input Clock Timing ................................................................................................434
Figure 19.14 SCI Input/Output Timing .......................................................................................435
Figure 19.15 POE Input/Output Timing......................................................................................436
Figure 19.16 External Trigger Input Timing ...............................................................................437
Appendix C Package Dimensions
Figure C.1 FP-80Q...................................................................................................................443
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Tables
Section 1 Overview
Table 1.1 Pin Functions ...............................................................................................................5
Table 1.2 Differences from SH7046 Group.................................................................................9
Section 2 CPU
Table 2.1 Initial Values of Registers..........................................................................................15
Table 2.2 Sign Extension of Word Data ....................................................................................17
Table 2.3 Delayed Branch Instructions......................................................................................17
Table 2.4 T Bit...........................................................................................................................18
Table 2.5 Immediate Data Accessing.........................................................................................18
Table 2.6 Absolute Address Accessing......................................................................................19
Table 2.7 Displacement Accessing ............................................................................................19
Table 2.8 Addressing Modes and Effective Addresses..............................................................20
Table 2.9 Instruction Formats....................................................................................................24
Table 2.10 Classification of Instructions .....................................................................................27
Table 2.11 Symbols Used in Instruction Code, Operation, and Execution States Tables............30
Table 2.12 Data Transfer Instructions..........................................................................................31
Table 2.13 Arithmetic Operation Instructions .............................................................................33
Table 2.14 Logic Operation Instructions .....................................................................................36
Table 2.15 Shift Instructions........................................................................................................37
Table 2.16 Branch Instructions....................................................................................................38
Table 2.17 System Control Instructions.......................................................................................39
Section 3 MCU Operating Modes
Table 3.1 Selection of Operating Modes....................................................................................43
Table 3.2 Maximum Operating Clock Frequency for Each Clock Mode ..................................43
Table 3.3 Operating Mode Pin Configuration............................................................................44
Section 4 Clock Pulse Generator
Table 4.1 Damping Resistance Values.......................................................................................48
Table 4.2 Crystal Resonator Characteristics ..............................................................................48
Section 5 Exception Processing
Table 5.1 Types of Exception Processing and Priority ..............................................................53
Table 5.2 Timing for Exception Source Detection and Start of Exception Processing..............54
Table 5.3 Exception Processing Vector Table ...........................................................................55
Table 5.4 Calculating Exception Processing Vector Table Addresses.......................................56
Table 5.5 Reset Status................................................................................................................57
Table 5.6 Bus Cycles and Address Errors..................................................................................59
Table 5.7 Interrupt Sources........................................................................................................60
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Table 5.8 Interrupt Priority ........................................................................................................ 61
Table 5.9 Types of Exceptions Triggered by Instructions ......................................................... 62
Table 5.10 Generation of Exception Sources Immediately after Delayed Branch Instruction
or Interrupt-Disabled Instruction ............................................................................... 64
Table 5.11 Stack Status after Exception Processing Ends ........................................................... 65
Section 6 Interrupt Controller (INTC)
Table 6.1 Pin Configuration....................................................................................................... 68
Table 6.2 Interrupt Exception Processing Vectors and Priorities .............................................. 78
Table 6.3 Interrupt Response Time............................................................................................ 84
Section 7 Bus State Controller (BSC)
Table 7.1 Address Map.............................................................................................................. 88
Table 7.2 On-chip Peripheral I/O Register Access .................................................................... 90
Section 8 Multi-Function Timer Pulse Unit (MTU)
Table 8.1 MTU Functions.......................................................................................................... 92
Table 8.2 Pin configuration........................................................................................................ 95
Table 8.3 CCLR0 to CCLR2 (channels 0, 3, and 4) .................................................................. 99
Table 8.4 CCLR0 to CCLR2 (channels 1 and 2) ....................................................................... 99
Table 8.5 TPSC0 to TPSC2 (channel 0) .................................................................................. 100
Table 8.6 TPSC0 to TPSC2 (channel 1) .................................................................................. 100
Table 8.7 TPSC0 to TPSC2 (channel 2) .................................................................................. 101
Table 8.8 TPSC0 to TPSC2 (channels 3 and 4)....................................................................... 101
Table 8.9 MD0 to MD3 ........................................................................................................... 103
Table 8.10 TIORH_0 (channel 0).............................................................................................. 106
Table 8.11 TIORH_0 (channel 0).............................................................................................. 107
Table 8.12 TIORL_0 (channel 0)............................................................................................... 108
Table 8.13 TIORL_0 (channel 0)............................................................................................... 109
Table 8.14 TIOR_1 (channel 1)................................................................................................. 110
Table 8.15 TIOR_1 (channel 1)................................................................................................. 111
Table 8.16 TIOR_2 (channel 2)................................................................................................. 112
Table 8.17 TIOR_2 (channel 2)................................................................................................. 113
Table 8.18 TIORH_3 (channel 3).............................................................................................. 114
Table 8.19 TIORH_3 (channel 3).............................................................................................. 115
Table 8.20 TIORL_3 (channel 3)............................................................................................... 116
Table 8.21 TIORL_3 (channel 3)............................................................................................... 117
Table 8.22 TIORH_4 (channel 4).............................................................................................. 118
Table 8.23 TIORH_4 (channel 4).............................................................................................. 119
Table 8.24 TIORL_4 (channel 4)............................................................................................... 120
Table 8.25 TIORL_4 (channel 4)............................................................................................... 121
Table 8.26 Output Level Select Function .................................................................................. 131
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Table 8.27 Output Level Select Function ..................................................................................132
Table 8.28 Output level Select Function....................................................................................134
Table 8.29 Register Combinations in Buffer Operation ............................................................145
Table 8.30 Cascaded Combinations...........................................................................................149
Table 8.31 PWM Output Registers and Output Pins .................................................................151
Table 8.32 Phase Counting Mode Clock Input Pins ..................................................................156
Table 8.33 Up/Down-Count Conditions in Phase Counting Mode 1.........................................158
Table 8.34 Up/Down-Count Conditions in Phase Counting Mode 2.........................................159
Table 8.35 Up/Down-Count Conditions in Phase Counting Mode 3.........................................160
Table 8.36 Up/Down-Count Conditions in Phase Counting Mode 4.........................................161
Table 8.37 Output Pins for Reset-Synchronized PWM Mode...................................................163
Table 8.38 Register Settings for Reset-Synchronized PWM Mode...........................................163
Table 8.39 Output Pins for Complementary PWM Mode..........................................................167
Table 8.40 Register Settings for Complementary PWM Mode .................................................168
Table 8.41 Registers and Counters Requiring Initialization ......................................................176
Table 8.42 MTU Interrupts........................................................................................................193
Table 8.43 Mode Transition Combinations ...............................................................................221
Table 8.44 Pin Configuration.....................................................................................................254
Table 8.45 Pin Combinations.....................................................................................................254
Section 9 Watchdog Timer
Table 9.1 Pin Configuration.....................................................................................................264
Table 9.2 WDT Interrupt Source (in Interval Timer Mode) ....................................................273
Section 10 Serial Communication Interface (SCI)
Table 10.1 Pin Configuration.....................................................................................................279
Table 10.2 Relationships between N Setting in BRR and Effective Bit Rate B0 .......................288
Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode)....................................289
Table 10.4 Maximum Bit Rate for Each Frequency when Using Baud Rate Generator
(Asynchronous Mode) .............................................................................................291
Table 10.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)....................292
Table 10.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)........................293
Table 10.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) .......295
Table 10.8 Serial Transfer Formats (Asynchronous Mode).......................................................297
Table 10.9 SSR Status Flags and Receive Data Handling .........................................................304
Table 10.10 SCI Interrupt Sources...............................................................................................322
Section 11 A/D Converter
Table 11.1 Pin Configuration.....................................................................................................327
Table 11.2 Channel Select List ..................................................................................................330
Table 11.3 A/D Conversion Time (Single Mode)......................................................................336
Table 11.4 A/D Conversion Time (Scan Mode) ........................................................................337
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Table 11.5 A/D Converter Interrupt Source............................................................................... 338
Table 11.6 Analog Pin Specifications........................................................................................ 342
Section 13 Pin Function Controller (PFC)
Table 13.1 Multiplexed Pins (Port A)........................................................................................ 353
Table 13.2 Multiplexed Pins (Port B)........................................................................................ 354
Table 13.3 Multiplexed Pins (Port E) ........................................................................................ 355
Table 13.4 Multiplexed Pins (Port F)......................................................................................... 356
Table 13.5 Multiplexed Pins (Port G)........................................................................................ 356
Table 13.6 Pin Functions in Each Operating Mode................................................................... 357
Section 14 I/O Ports
Table 14.1 Port A Data Register L (PADRL) Read/Write Operations ...................................... 373
Table 14.2 Port B Data Register (PBDR) Read/Write Operations............................................. 375
Table 14.3 Port E Data Registers H and L (PEDRH and PEDRL) Read/Write Operations ...... 378
Table 14.4 Port F Data Register (PFDR) Read/Write Operations ............................................. 380
Table 14.5 Port G Data Register (PGDR) Read/Write Operations ............................................ 382
Section 17 Power-Down Modes
Table 17.1 Internal Operation States in Each Mode .................................................................. 388
Table 17.2 Pin Configuration..................................................................................................... 389
Section 19 Electrical Characteristics
Table 19.1 Absolute Maximum Ratings .................................................................................... 421
Table 19.2 DC Characteristics ................................................................................................... 422
Table 19.3 Permitted Output Current Values............................................................................. 424
Table 19.4 Clock Timing........................................................................................................... 426
Table 19.5 Control Signal Timing ............................................................................................. 428
Table 19.6 Multi-Function Timer Pulse Unit Timing................................................................ 431
Table 19.7 I/O Port Timing........................................................................................................ 432
Table 19.8 Watchdog Timer Timing.......................................................................................... 433
Table 19.9 Serial Communication Interface Timing.................................................................. 434
Table 19.10 Output Enable Timing ............................................................................................. 436
Table 19.11 A/D Converter Timing............................................................................................. 436
Table 19.12 A/D Converter Characteristics................................................................................. 438
Appendix A Pin States
Table A.1 Pin States ................................................................................................................. 439
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1. Overview
Section 1 Overview
The SH7101 single-chip RISC (Reduced Instruction Set Computer) microcomputer integrates a
Renesas Technology-original RISC CPU core with peripheral functions required for system
configuration.
The SH7101 CPU has a RISC-type instruction set. Most instructions can be executed in one state
(one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-
bit internal-bus architecture enhances data processing power. With this CPU, it has become
possible to assemble low cost, high performance/high-functioning systems, even for applications
that were previously impossible with microcomputers, such as real-time control, which demands
high speeds.
In addition, the SH7101 includes on-chip peripheral functions necessary for system configuration,
such as ROM and RAM, timers, a serial communication interface (SCI), an A/D converter, an
interrupt controller (INTC), and I/O ports.
As the on-chip ROM, only mask ROM version is available. However, when F-ZTATTM (Flexible
Zero Turn Around Time) version is required, the SH7046F can be used.
1.1
Features
•
Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer)
architecture
⎯ Instruction length: 16-bit fixed length for improved code efficiency
⎯ Load-store architecture (basic operations are executed between registers)
⎯ Sixteen 32-bit general registers
⎯ Five-stage pipeline
⎯ On-chip multiplier: multiplication operations (32 bits × 32 bits → 64 bits) executed in two
to four cycles
⎯ C language-oriented 62 basic instructions
Various peripheral functions
•
⎯ Multifunction timer/pulse unit (MTU)
⎯ Compare match timer (CMT)
⎯ Watchdog timer (WDT)
⎯ Asynchronous or clocked synchronous serial communication interface (SCI)
⎯ 10-bit A/D converter
⎯ Clock pulse generator
Rev.2.00 Sep. 27, 2007 Page 1 of 448
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1. Overview
•
On-chip memory
ROM
Model
ROM
RAM
Remarks
Mask ROM
Version
HD6437101
32 kbytes
2 kbytes
⎯
•
Maximum operating frequency and operating temperature range
Maximum operating frequency (MHz)
Operating temperature
Model
(system clock (φ) and peripheral clock (Pφ))
range (°C)
HD6437101F40
(40, 40)
–20 to +75
–40 to +85
HD6437101FW40 (40, 40)
•
I/O ports
Model
No. of I/O Pins
No. of Input-only Pins
12
HD6437101
42
•
•
Supports various power-down states
Compact package
Package
(Code)
Model
Package
Body Size
Pin Pitch
HD6437101
QFP-80
FP-80Q
14.0 × 14.0 mm
0.65 mm
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1. Overview
1.2
Internal Block Diagram
RES
WDTOVF
MD3
MD2
MD1
MD0
Mask ROM
32 kbytes
RAM
2 kbytes
NMI
EXTAL
XTAL
PLLVcL
PLLCAP
PLLVss
FWP
PLL
CPU
VcL
VcL
Vcc
Vcc
Interrupt
controller
Bus state controller
Vcc
Vss
Vss
Serial communication
interface
(×2 channels)
Vss
Multifunction timer
pulse unit
Vss
AVcc
AVcc
AVss
AVss
Compare match
timer
(×2 channels)
A/D
converter
Watchdog
timer
: Peripheral address bus (12 bits)
: Peripheral data bus (16 bits)
: Internal address bus (32 bits)
: Internal upper data bus (16 bits)
: Internal lower data bus (16 bits)
Figure 1.1 Internal Block Diagram of SH7101
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1. Overview
1.3
Pin Arrangement
PA1/POE1/TXD2
VcL
PA0/POE0/RXD2
Vss
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
AVss
PF8/AN8
AVcc
PF9/AN9
PF10/AN10
PF11/AN11
PG0
PG1
PG2
PG3
PF12/AN12
PF13/AN13
PF14/AN14
AVcc
PF15/AN15
AVss
Vss
PE21*
VcL
PE20*
FWP
Vcc
RES
NMI
MD3
MD2
MD1
MD0
EXTAL
XTAL
QFP-80
(Top view)
PLLVcL
PLLCAP
PLLVss
WDTOVF
PE0/TIOC0A
PE1/TIOC0B
Note: * This pin has a pull-up MOS.
Figure 1.2 SH7101 Pin Arrangement
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1. Overview
1.4
Pin Functions
Table 1.1 Pin Functions
Type
Symbol
I/O
Name
Function
Power
Supply
VCC
Input
Power supply Power supply pins. Connect all these pins
to the system power supply. The chip does
not operate normally when some of these
pins are open.
VSS
Input
Ground
Ground pins. Connect all these pins to the
system power supply (0 V). The chip does
not operate normally when some of these
pins are open.
VCL
Output Power supply External capacitance pins for internal
for internal
power-down
power-down power supply. Connect these
pins to VSS via a 0.47 μF (–10%/+100%)
capacitor (placed close to the pins).
Clock
PLLVCL
Output Power supply External capacitance pin for internal
for PLL
power-down power supply for an on-chip
PLL oscillator. Connect this pin to PLLVSS
via a 0.47 μF (–10%/+100%) capacitor
(placed close to the pin).
PLLVSS
PLLCAP
EXTAL
Input
Input
Input
Ground for
PLL
On-chip PLL oscillator ground pin.
Capacitance
for PLL
External capacitance pin for an on-chip
PLL oscillator.
External clock For connection to a crystal resonator. (An
external clock can be supplied from the
EXTAL pin.) For examples of crystal
resonator connection and external clock
input, see section 4, Clock Pulse
Generator.
XTAL
Input
Crystal
For connection to a crystal resonator. For
examples of crystal resonator connection
and external clock input, see section 4,
Clock Pulse Generator.
Operating
mode control
MD3 to MD0 Input
Set the mode Set the operating mode. Inputs at these
pins should not be changed during
operation.
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1. Overview
Type
Symbol
I/O
Name
Function
Operating
mode control
FWP
Input
Protection
against write
Pin for the flash memory. This pin is only
used in the flash memory version. Writing
operation into or erasing of flash memory can be
Flash memory protected. This pin becomes the Vcc pin
for the mask ROM version.
System
control
RES
Input
Input
Power on
reset
When this pin is driven low, the chip
becomes to power on reset state.
MRES
WDTOVF
Manual reset When this pin is driven low, the chip
becomes to manual reset state.
Output Watchdog
Output signal for the watchdog timer
timer overflow overflow. This pin should be pulled down
with at least 1 MΩ resistor value.
Interrupts
NMI
Input
Non-maskable Non-maskable interrupt pin. If this pin is
interrupt
not used, it should be fixed high or low.
IRQ3 to IRQ0 Input
Interrupt
These pins request a maskable interrupt.
request 3 to 0 One of the level input or edge input can be
selected. In case of the edge input, one of
the rising edge, falling edge, or both can
be selected.
IRQOUT
Multi function TCLKA
Output Interrupt
Shows that an interrupt cause has
request output occurred.
Input
External clock These pins input an external clock.
timer-pulse
unit (MTU)
TCLKB
TCLKC
TCLKD
input for MTU
timer
TIOC0A
TIOC0B
TIOC0C
TIOC0D
Input/
MTU input
The TGRA_0 to TGRD_0 input capture
Output capture/output input/output compare output/PWM output
compare
(channel 0)
pins.
TIOC1A
TIOC1B
Input/
MTU input
The TGRA_1 to TGRB_1 input capture
Output capture/output input/output compare output/PWM output
compare
pins.
(channel 1)
TIOC2A
TIOC2B
Input/
MTU input
The TGRA_2 to TGRB_2 input capture
Output capture/output input/output compare output/PWM output
compare
pins.
(channel 2)
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1. Overview
Type
Symbol
I/O
Name
Function
The TGRA_3 to TGRD_3 input capture
Multi function TIOC3A
Input/
MTU input
timer-pulse
unit (MTU)
TIOC3B
TIOC3C
TIOC3D
Output capture/output input/output compare output/PWM output
compare
pins.
(channel 3)
TIOC4A
TIOC4B
TIOC4C
TIOC4D
Input/
MTU input
The TGRA_4 to TGRB_4 input capture
Output capture/output input/output compare output/PWM output
compare
(channel 4)
pins.
Serial com- TxD2
Output Transmitted
data
Data output pins.
munication
Interface
(SCI)
TxD3
RxD2
RxD3
Input
Received data Data input pins.
SCK2
SCK3
Input/
Output
Serial clock
Clock input/output pins.
MTU output POE3 to
Input
Port output
control
Input pins for the signal to request the
output pins of MTU waveform to become
high impedance state.
control
POE0
A/D
converter
AN15 to AN8 Input
Analog input
pins
Analog input pins.
8 channels: AN15 to AN8
ADTRG
Input
Input
Input of trigger Pin for input of an external trigger to start
for A/D
A/D conversion
conversion
AVCC
Analog power Power supply pin for the A/D converter.
supply
When the A/D converter is not used,
connect this pin to the system power
supply (+5 V). Connect all AVCC pins to
the power supply. The chip does not
operate normally when some of these pins
are open.
AVSS
Input
Analog ground The ground pin for the A/D converter.
Connect this pin to the system power
supply (0 V). Connect all AVSS pins to the
system power supply. The chip does not
operate normally when some of these pins
are open.
Rev.2.00 Sep. 27, 2007 Page 7 of 448
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1. Overview
Type
Symbol
I/O
Name
Function
I/O ports
PA15 to PA0 Input/
General
16-bit general purpose input/output port
pins. PA15 to PA12 have a pull-up MOS.
Output purpose port
PB5 to PB2 Input/
General
4-bit general purpose input/output port
pins
Output purpose port
PE21 to PE0 Input/
General
22-bit general purpose input/output port
pins. PE21 to PE16 have a pull-up MOS.
Output purpose port
PF15 to PF8 Input
PG3 to PG0 Input
General
purpose port
8-bit general purpose input port pins
General
4-bit general purpose input port pins
purpose port
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1. Overview
1.5
Differences from SH7046 Group
Table 1.2 Differences from SH7046 Group
Item
SH7046F
SH7101
DTC, MMT, UBC
INT
Incorporated
Not incorporated
Registers IPRA and IPRD to IPRK
available.
Registers IPRJ and IPRK deleted.
BSC
Registers BCR1, BCR2, WCR1, and Registers BCR2, WCR1, and
RAMER
RAMER deleted.
POE
POE6 to POE0
POE6 to POE4 for MMT deleted.
A/D Converter
4ch × 3 modules
4ch × 2 modules
AN19 to AN8
AN15 to AN8
I/O port
PFC
PA2/IRQ0/PCIO/SCK2
PA3/POE4/RXD3
PA2/IRQ0/SCK2
PA3/RXD3
PA4/POE5/TXD3
PA4/TXD3
PA5/IRQ1/POE6/SCK3
PA8/TCLKC/IRQ2/RXD3
PA9/TCLKD/IRQ3/TXD3
PA12/UBCTRG
PA5/IRQ1/SCK3
PA8/TCLKC/RXD3
PA9/TCLKD/TXD3
PA12 (pulled up when used as
general purpose input)
PA13/POE4
PA14/POE5
PA15/POE6
PA13 (pulled up when used as
general purpose input)
PA14 (pulled up when used as
general purpose input)
PA15 (pulled up when used as
general purpose input)
PE7/TIOC2B/RXD2
PE8/TIOC3A/SCK2
PE10/TIOC3C/TXD2
PE16/PUOA/UBCTRG
PE7/TIOC2B
PE8/TIOC3A
PE10/TIOC3C
PE16 (pulled up when used as
general purpose input)*
PE17/PVOA
PE18/PWOA
PE17 (pulled up when used as
general purpose input)*
PE18 (pulled up when used as
general purpose input)*
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1. Overview
Item
SH7046F
SH7101
I/O port
PFC
PE19/PUOB
PE19 (pulled up when used as
general purpose input)*
PE20/PVOB
PE21/PWOB
PE20 (pulled up when used as
general purpose input)*
PE21 (pulled up when used as
general purpose input)*
PG0/AN16
PG1/AN17
PG2/AN18
PG3/AN19
Flash 256 kbytes
12 kbytes
PG0
PG1
PG2
PG3
ROM
Mask ROM 32 kbytes
2 kbytes
RAM
Operating clock
4 to 50 MHz
10 to 40 MHz
Note:
*
Pins PE21 to PE16 also functioned as high-current function pins. Howwever, in the
SH7101, pins PE21 to PE16 are exclusively for general input/output.
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2. CPU
Section 2 CPU
2.1
Features
•
General-register architecture
⎯ Sixteen 32-bit general registers
•
•
Sixty-two basic instructions
Eleven addressing modes
⎯ Register direct [Rn]
⎯ Register indirect [@Rn]
⎯ Register indirect with post-increment [@Rn+]
⎯ Register indirect with pre-decrement [@-Rn]
⎯ Register indirect with displacement [@disp:4,Rn]
⎯ Register indirect with index [@R0, Rn]
⎯ GBR indirect with displacement [@disp:8,GBR]
⎯ GBR indirect with index [@R0,GBR]
⎯ Program-counter relative with displacement [@disp:8,PC]
⎯ Program-counter relative [disp:8/disp:12/Rn]
⎯ Immediate [#imm:8]
2.2
Register Configuration
The register set consists of sixteen 32-bit general registers, three 32-bit control registers, and four
32-bit system registers.
CPUS200A_010020030200
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General registers (Rn)
31
0
*1
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
*2
R15, SP (hardware stack pointer)
Status register (SR)
31
9
8 7 6 5 4 3 2 1 0
M Q I3 I2 I1 I0
S T
Global base register (GBR)
31
0
GBR
Vector base register (VBR)
31
0
0
VBR
Multiply-accumulate register (MAC)
31
MACH
MACL
Procedure register (PR)
31
0
0
PR
Program counter (PC)
31
PC
Notes: 1. R0 functions as an index register in the indirect indexed register addressing mode and indirect indexed GBR
addressing mode. In some instructions, R0 functions as a fixed source register or destination register.
2. R15 functions as a hardware stack pointer (SP) during exception processing.
Figure 2.1 CPU Internal Registers
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2. CPU
2.2.1
General Registers (Rn)
The sixteen 32-bit general registers (Rn) are numbered R0 to R15. General registers are used for
data processing and address calculation. R0 is also used as an index register. Several instructions
have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving
and recovering the status register (SR) and program counter (PC) in exception processing is
accomplished by referencing the stack using R15.
2.2.2
Control Registers
The control registers consist of three 32-bit registers: status register (SR), global base register
(GBR), and vector base register (VBR). The status register indicates processing states. The global
base register functions as a base address for the indirect GBR addressing mode to transfer data to
the registers of on-chip peripheral modules. The vector base register functions as the base address
of the exception processing vector area (including interrupts).
Status Register (SR):
Initial
Bit
Bit Name Value
R/W
Description
31 to 10 ⎯
All 0
R/W
Reserved
This bit is always read as 0. The write value should
always be 0.
9
8
M
Q
Undefined R/W
Undefined R/W
Used by the DIV0U, DIV0S, and DIV1 instructions.
Used by the DIV0U, DIV0S, and DIV1 instructions.
Interrupt mask bits.
7
6
5
4
I3
I2
I1
I0
1
1
1
1
R/W
R/W
R/W
R/W
3, 2
⎯
All 0
R/W
Reserved
This bit is always read as 0. The write value should
always be 0.
1
S
Undefined R/W
S bit
Used by the MAC instruction.
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Initial
Bit
Bit Name Value
R/W
Description
0
T
Undefined R/W
T bit
The MOVT, CMP/cond, TAS, TST, BT (BT/S), BF
(BF/S), SETT, and CLRT instructions use the T bit to
indicate true (1) or false (0).
The ADDV, ADDC, SUBV, SUBC, DIV0U, DIV0S,
DIV1, NEGC, SHAR, SHAL, SHLR, SHLL, ROTR,
ROTL, ROTCR, and ROTCL instructions also use the
T bit to indicate carry/borrow or overflow/underflow.
Global Base Register (GBR): Indicates the base address of the indirect GBR addressing mode.
The indirect GBR addressing mode is used in data transfer for on-chip peripheral modules register
areas and in logic operations.
Vector Base Register (VBR): Indicates the base address of the exception processing vector area.
2.2.3
System Registers
System registers consist of four 32-bit registers: high and low multiply and accumulate registers
(MACH and MACL), the procedure register (PR), and the program counter (PC).
Multiply-and-Accumulate Registers (MAC): Registers to store the results of multiply-and-
accumulate operations.
Procedure Register (PR): Registers to store the return address from a subroutine procedure.
Program Counter (PC): Registers to indicate the sum of current instruction addresses and four,
that is, the address of the second instruction after the current instruction.
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2.2.4
Initial Values of Registers
Table 2.1 lists the values of the registers after reset.
Table 2.1 Initial Values of Registers
Classification
Register
R0 to R14
R15 (SP)
Initial Value
General registers
Undefined
Value of the stack pointer in the vector
address table
Control registers
System registers
SR
Bits I3 to I0 are 1111 (H'F), reserved bits
are 0, and other bits are undefined
GBR
Undefined
H'00000000
Undefined
VBR
MACH, MACL, PR
PC
Value of the program counter in the vector
address table
2.3
Data Formats
2.3.1
Data Format in Registers
Register operands are always longwords (32 bits). If the size of memory operand is a byte (8 bits)
or a word (16 bits), it is changed into a longword by expanding the sign-part when loaded into a
register.
31
0
Longword
Figure 2.2 Data Format in Registers
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2.3.2
Data Formats in Memory
Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed
from any address. Locate, however, word data at an address 2n, longword data at 4n. Otherwise,
an address error will occur if an attempt is made to access word data starting from an address other
than 2n or longword data starting from an address other than 4n. In such cases, the data accessed
cannot be guaranteed. The hardware stack area, pointed by the hardware stack pointer (SP, R15),
uses only longword data starting from address 4n because this area holds the program counter and
status register.
Address m + 1
Address m + 3
Address m Address m + 2
23
Byte
7
31
Byte
15
Byte
0
Byte
Address 2n
Address 4n
Word
Word
Longword
Figure 2.3 Data Formats in Memory
Immediate Data Format
2.3.3
Byte (8 bit) immediate data resides in an instruction code. Immediate data accessed by the MOV,
ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data.
Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and
handled as longword data. Consequently, AND instructions with immediate data always clear the
upper 24 bits of the destination register.
Word or longword immediate data is not located in the instruction code, but instead is stored in a
memory table. An immediate data transfer instruction (MOV) accesses the memory table using the
PC relative addressing mode with displacement.
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2.4
Instruction Features
2.4.1
RISC-Type Instruction Set
All instructions are RISC type. This section details their functions.
16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency.
One Instruction per State: The microprocessor can execute basic instructions in one state using
the pipeline system. One state is 25 ns at 40 MHz.
Data Length: Longword is the standard data length for all operations. Memory can be accessed in
bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and
handled as longword data. Immediate data is sign-extended for arithmetic operations or zero-
extended for logic operations. It also is handled as longword data.
Table 2.2 Sign Extension of Word Data
CPU of This LSI
Description
Example of Conventional CPU
MOV.W
ADD
@(disp,PC),R1 Data is sign-extended to 32
ADD.W #H'1234,R0
bits, and R1 becomes
H'00001234. It is next
operated upon by an ADD
R1,R0
.........
.DATA.W H'1234
instruction.
Note: @(disp, PC) accesses the immediate data.
Load-Store Architecture: Basic operations are executed between registers. For operations that
involve memory access, data is loaded to the registers and executed (load-store architecture).
Instructions such as AND that manipulate bits, however, are executed directly in memory.
Delayed Branch Instructions: Unconditional branch instructions are delayed branch instructions.
With a delayed branch instruction, the branch is taken after execution of the instruction following
the delayed branch instruction. This reduces the disturbance of the pipeline control in case of
branch instructions. There are two types of conditional branch instructions: delayed branch
instructions and ordinary branch instructions.
Table 2.3 Delayed Branch Instructions
CPU of This LSI
Description
Example of Conventional CPU
BRA
ADD
TRGET
R1,R0
Executes the ADD before
branching to TRGET.
ADD.W
BRA
R1,R0
TRGET
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Multiply/Multiply-and-Accumulate Operations: 16-bit × 16-bit → 32-bit multiply operations
are executed in one to two states. 16-bit × 16-bit + 64-bit → 4-bit multiply-and-accumulate
operations are executed in two to three states. 32-bit × 32-bit → 64-bit multiply and 32-bit × 32-bit
+ 64-bit → 64-bit multiply-and-accumulate operations are executed in two to four states.
T Bit: The T bit in the status register changes according to the result of the comparison. Whether a
conditional branch is taken or not taken depends upon the T bit condition (true/false). The number
of instructions that change the T bit is kept to a minimum to improve the processing speed.
Table 2.4 T Bit
CPU of This LSI
Description
Example of Conventional CPU
CMP/GE
BT
R1,R0
T bit is set when R0 ≥ R1. The
program branches to TRGET0
when R0 ≥ R1 and to TRGET1
when R0 < R1.
CMP.W R1,R0
TRGET0
TRGET1
BGE
BLT
TRGET0
TRGET1
BF
ADD
#−1,R0
#0,R0
TRGET
T bit is not changed by ADD. T bit is SUB.W #1,R0
set when R0 = 0. The program
CMP/EQ
BT
BEQ
TRGET
branches if R0 = 0.
Immediate Data: Byte (8-bit) immediate data is located in an instruction code. Word or longword
immediate data is not located in instruction codes but in a memory table. An immediate data
transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with
displacement.
Table 2.5 Immediate Data Accessing
Classification
8-bit immediate
16-bit immediate
CPU of This LSI
Example of Conventional CPU
MOV.B #H'12,R0
MOV
#H'12,R0
MOV.W
@(disp,PC),R0
.................
H'1234
MOV.W #H'1234,R0
.DATA.W
MOV.L
32-bit immediate
@(disp,PC),R0
.................
H'12345678
MOV.L #H'12345678,R0
.DATA.L
Note: @(disp, PC) accesses the immediate data.
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Absolute Address: When data is accessed by absolute address, the value in the absolute address is
placed in the memory table in advance. That value is transferred to the register by loading the
immediate data during the execution of the instruction, and the data is accessed in the indirect
register addressing mode.
Table 2.6 Absolute Address Accessing
Classification
CPU of This LSI
Example of Conventional CPU
Absolute address
MOV.L
MOV.B
@(disp,PC),R1
MOV.B @H'12345678,R0
@R1,R0
..................
H'12345678
.DATA.L
Note: @(disp, PC) accesses the immediate data.
16-Bit/32-Bit Displacement: When data is accessed by 16-bit or 32-bit displacement, the
displacement value is placed in the memory table in advance. That value is transferred to the
register by loading the immediate data during the execution of the instruction, and the data is
accessed in the indirect indexed register addressing mode.
Table 2.7 Displacement Accessing
Classification
CPU of This LSI
Example of Conventional CPU
16-bit displacement MOV.W
@(disp,PC),R0
@(R0,R1),R2
..................
H'1234
MOV.W @(H'1234,R1),R2
MOV.W
.DATA.W
Note: @(disp, PC) accesses the immediate data.
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2.4.2
Addressing Modes
Table 2.8 describes addressing modes and effective address calculation.
Table 2.8 Addressing Modes and Effective Addresses
Addressing
Mode
Instruction
Format
Effective Address Calculation
Equation
Direct register
addressing
Rn
The effective address is register Rn. (The operand ⎯
is the contents of register Rn.)
Indirect register @Rn
addressing
The effective address is the contents of register
Rn.
Rn
Rn
Rn
Post-increment
indirect register
addressing
@Rn+
The effective address is the contents of register
Rn.
A constant is added to the content of Rn after the
instruction is executed. 1 is added for a byte
operation, 2 for a word operation, and 4 for a
longword operation.
Rn
(After the
instruction
executes)
Byte:
Rn + 1 → Rn
Rn
Rn
Word:
Rn + 2 → Rn
Rn + 1/2/4
+
Longword:
Rn + 4 → Rn
1/2/4
The effective address is the value obtained by
Pre-decrement
indirect register
addressing
@-Rn
Byte:
subtracting a constant from Rn. 1 is subtracted for Rn – 1 → Rn
a byte operation, 2 for a word operation, and 4 for
a longword operation.
Word:
Rn – 2 → Rn
Longword:
Rn
Rn – 4 → Rn
(Instruction is
executed with
Rn after this
calculation)
Rn – 1/2/4
–
Rn – 1/2/4
1/2/4
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Addressing
Mode
Instruction
Format
Effective Address Calculation
Equation
Indirect register @(disp:4, The effective address is the sum of Rn and a 4-bit Byte:
addressing with Rn)
displacement
displacement (disp). The value of disp is zero-
extended, and remains unchanged for a byte
operation, is doubled for a word operation, and is
quadrupled for a longword operation.
Rn + disp
Word:
Rn + disp × 2
Longword:
Rn + disp × 4
Rn
disp
(zero-extended)
+
Rn + disp × 1/2/4
×
1/2/4
Indirect indexed @(R0, Rn) The effective address is the sum of Rn and R0.
Rn + R0
register
addressing
Rn
+
Rn + R0
R0
@(disp:8, The effective address is the sum of GBR value and Byte:
Indirect GBR
addressing with GBR)
displacement
an 8-bit displacement (disp). The value of disp is
zero-extended, and remains unchanged for a byte
operation, is doubled for a word operation, and is
quadrupled for a longword operation.
GBR + disp
Word:
GBR + disp ×
2
GBR
Longword:
GBR + disp ×
4
GBR
+ disp × 1/2/4
disp
(zero-extended)
+
×
1/2/4
Indirect indexed @(R0,
GBR addressing GBR)
The effective address is the sum of GBR value and GBR + R0
R0.
GBR
+
GBR + R0
R0
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2. CPU
Addressing
Mode
Instruction
Format
Effective Address Calculation
Equation
Indirect PC
@(disp:8, The effective address is the sum of PC value and Word:
addressing with PC)
displacement
an 8-bit displacement (disp). The value of disp is
zero-extended, and is doubled for a word
operation, and quadrupled for a longword
operation. For a longword operation, the lowest
two bits of the PC value are masked.
PC + disp × 2
Longword:
PC &
H'FFFFFFFC
+ disp × 4
PC
(for longword)
&
PC + disp × 2
H'FFFFFFFC
or
+
PC & H'FFFFFFFC
+ disp × 4
disp
(zero-extended)
×
2/4
PC relative
addressing
disp:8
The effective address is the sum of PC value and PC + disp × 2
the value that is obtained by doubling the sign-
extended 8-bit displacement (disp).
PC
disp
(sign-extended)
+
PC + disp × 2
×
2
disp:12
The effective address is the sum of PC value and PC + disp × 2
the value that is obtained by doubling the sign-
extended 12-bit displacement (disp).
PC
disp
(sign-extended)
+
PC + disp × 2
×
2
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2. CPU
Addressing
Mode
Instruction
Format
Effective Address Calculation
Equation
PC relative
addressing
Rn
The effective address is the sum of the register PC PC + Rn
and Rn.
PC
+
PC + Rn
Rn
Immediate
addressing
#imm:8
#imm:8
#imm:8
The 8-bit immediate data (imm) for the TST, AND,
OR, and XOR instructions is zero-extended.
⎯
The 8-bit immediate data (imm) for the MOV, ADD, ⎯
and CMP/EQ instructions is sign-extended.
The 8-bit immediate data (imm) for the TRAPA
instruction is zero-extended and then quadrupled.
⎯
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2.4.3
Instruction Format
The instruction formats and the meaning of source and destination operand are described below.
The meaning of the operand depends on the instruction code. The symbols used are as follows:
•
•
•
•
•
xxxx: Instruction code
mmmm: Source register
nnnn: Destination register
iiii: Immediate data
dddd: Displacement
Table 2.9 Instruction Formats
Source
Operand
Destination
Operand
Instruction Formats
Example
0 format
⎯
⎯
NOP
15
0
0
xxxx xxxx
xxxx xxxx
xxxx xxxx
n format
15
⎯
nnnn: Direct
register
MOVT Rn
xxxx nnnn
Control register or nnnn: Direct
system register register
STS
MACH,Rn
Control register or nnnn: Indirect pre- STC.L SR,@-Rn
system register
decrement register
m format
15
mmmm: Direct
register
Control register or LDC
system register
Rm,SR
0
mmmm: Indirect
post-increment
register
Control register or LDC.L @Rm+,SR
system register
xxxx mmmm xxxx xxxx
mmmm: Indirect
register
⎯
⎯
JMP
@Rm
mmmm: PC
BRAF Rm
relative using Rm
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Source
Operand
Destination
Operand
Instruction Formats
Example
ADD Rm,Rn
nm format
15
mmmm: Direct
register
nnnn: Direct
register
0
mmmm: Direct
register
nnnn: Indirect
register
MOV.L Rm,@Rn
xxxx nnnn
xxxx
mmmm
mmmm: Indirect
post-increment
register (multiply-
and-accumulate)
MACH, MACL
MAC.W
@Rm+,@Rn+
nnnn*: Indirect
post-increment
register (multiply-
and-accumulate)
mmmm: Indirect
post-increment
register
nnnn: Direct
register
MOV.L @Rm+,Rn
mmmm: Direct
register
nnnn: Indirect pre- MOV.L Rm,@-Rn
decrement
register
mmmm: Direct
register
nnnn: Indirect
indexed register
MOV.L
Rm,@(R0,Rn)
md format
15
mmmmdddd:
Indirect register
with displacement
R0 (Direct
register)
MOV.B
@(disp,Rn),R0
0
0
0
xxxx xxxx
dddd
mmmm
nd4 format
15
R0 (Direct register) nnnndddd:
Indirect register
with displacement
MOV.B
R0,@(disp,Rn)
xxxx xxxx
nnnn dddd
nmd format
15
mmmm: Direct
register
nnnndddd: Indirect MOV.L
register with
displacement
Rm,@(disp,Rn)
xxxx nnnn
dddd
mmmm
mmmmdddd:
Indirect register
with displacement
nnnn: Direct
register
MOV.L
@(disp,Rm),Rn
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Source
Operand
Destination
Operand
Instruction Formats
Example
d format
dddddddd: Indirect R0 (Direct register) MOV.L
GBR with
displacement
@(disp,GBR),R0
15
0
xxxx xxxx dddd dddd
R0 (Direct register) dddddddd: Indirect MOV.L
GBR with
R0,@(disp,GBR)
displacement
dddddddd: PC
relative with
R0 (Direct register) MOVA
@(disp,PC),R0
displacement
⎯
dddddddd: PC
relative
BF
label
label
d12 format
15
⎯
dddddddddddd:
PC relative
BRA
0
0
0
(label = disp
+ PC)
xxxx
dddd dddd dddd
nd8 format
15
dddddddd: PC
relative with
nnnn: Direct
register
MOV.L
@(disp,PC),Rn
displacement
xxxx nnnn
dddd dddd
i format
15
iiiiiiii: Immediate
Indirect indexed
GBR
AND.B
#imm,@(R0,GBR)
xxxx xxxx
i i i i
i i i i
iiiiiiii: Immediate
iiiiiiii: Immediate
iiiiiiii: Immediate
R0 (Direct register) AND
#imm,R0
⎯
TRAPA #imm
ni format
15
nnnn: Direct
register
ADD
#imm,Rn
0
xxxx nnnn
i i i i
i i i i
Note:
*
In multiply-and-accumulate instructions, nnnn is the source register.
2.5
Instruction Set
2.5.1
Instruction Set by Classification
Table 2.10 lists the instructions according to their classification.
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Table 2.10 Classification of Instructions
Operation
No. of
Classification Types Code
Function
Instructions
Data transfer
5
MOV
Data transfer, immediate data transfer,
peripheral module data transfer, structure data
transfer
39
MOVA
MOVT
SWAP
XTRCT
ADD
Effective address transfer
T bit transfer
Swap of upper and lower bytes
Extraction of the middle of registers connected
Binary addition
Arithmetic
operations
21
33
ADDC
ADDV
Binary addition with carry
Binary addition with overflow check
CMP/cond Comparison
DIV1
Division
DIV0S
DIV0U
DMULS
DMULU
DT
Initialization of signed division
Initialization of unsigned division
Signed double-length multiplication
Unsigned double-length multiplication
Decrement and test
EXTS
EXTU
MAC
Sign extension
Zero extension
Multiply-and-accumulate, double-length
multiply-and-accumulate operation
MUL
Double-length multiply operation
Signed multiplication
MULS
MULU
NEG
Unsigned multiplication
Negation
NEGC
SUB
Negation with borrow
Binary subtraction
SUBC
SUBV
Binary subtraction with borrow
Binary subtraction with underflow
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Operation
Classification Types Code
No. of
Instructions
Function
Logic
6
AND
Logical AND
14
operations
NOT
Bit inversion
OR
Logical OR
TAS
Memory test and bit set
Logical AND and T bit set
Exclusive OR
TST
XOR
Shift
10
ROTL
ROTR
ROTCL
ROTCR
SHAL
SHAR
SHLL
SHLLn
SHLR
SHLRn
BF
One-bit left rotation
One-bit right rotation
One-bit left rotation with T bit
One-bit right rotation with T bit
One-bit arithmetic left shift
One-bit arithmetic right shift
One-bit logical left shift
n-bit logical left shift
One-bit logical right shift
n-bit logical right shift
14
Branch
9
Conditional branch, conditional branch with
delay (Branch when T = 0)
11
BT
Conditional branch, conditional branch with
delay (Branch when T = 1)
BRA
BRAF
BSR
BSRF
JMP
JSR
Unconditional branch
Unconditional branch
Branch to subroutine procedure
Branch to subroutine procedure
Unconditional branch
Branch to subroutine procedure
Return from subroutine procedure
RTS
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No. of
Operation
Classification Types Code
Function
Instructions
System
control
11
CLRT
T bit clear
31
CLRMAC MAC register clear
LDC
Load to control register
Load to system register
No operation
LDS
NOP
RTE
Return from exception processing
T bit set
SETT
SLEEP
STC
Transition to power-down mode
Store control register data
Store system register data
Trap exception handling
STS
TRAPA
Total:
62
142
The table below shows the format of instruction codes, operation, and execution states. They are
described by using this format according to their classification.
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Table 2.11 Symbols Used in Instruction Code, Operation, and Execution States Tables
Item
Format
Explanation
Instruction
Described in
mnemonic.
OP: Operation code
Sz: Size
OP.Sz SRC,DEST
SRC: Source
DEST: Destination
Rm: Source register
Rn: Destination register
imm: Immediate data
disp: Displacement*2
Instruction
code
Described in MSB ↔ mmmm: Source register
LSB order
nnnn: Destination register
0000: R0
0001: R1
⋅
⋅
⋅
1111: R15
iiii: Immediate data
dddd: Displacement
Outline of the →, ←
Direction of transfer
Operation
(xx)
Memory operand
M/Q/T
Flag bits in the SR
&
Logical AND of each bit
Logical OR of each bit
Exclusive OR of each bit
Logical NOT of each bit
n-bit left shift
|
^
~
<<n
>>n
n-bit right shift
Execution
states
⎯
Value when no wait states are inserted*1
T bit
⎯
Value of T bit after instruction is executed. An em-dash (⎯)
in the column means no change.
Notes: 1. Instruction execution states: The execution states shown in the table are minimums.
The actual number of states may be increased when (1) contention occurs between
instruction fetches and data access, or (2) when the destination register of the load
instruction (memory → register) equals to the register used by the next instruction.
2. Depending on the operand size, displacement is scaled by ×1, ×2, or ×4. For details,
refer the SH-1/SH-2/SH-DSP Software Manual.
Rev.2.00 Sep. 27, 2007 Page 30 of 448
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2. CPU
Data Transfer Instructions
Table 2.12 Data Transfer Instructions
Execu-
tion
T
Instruction
MOV #imm,Rn
Instruction Code
1110nnnniiiiiiii
Operation
States
Bit
#imm → Sign extension →
1
⎯
Rn
MOV.W @(disp,PC),Rn 1001nnnndddddddd
(disp × 2 + PC) → Sign
extension → Rn
1
⎯
MOV.L @(disp,PC),Rn 1101nnnndddddddd
(disp × 4 + PC) → Rn
Rm → Rn
1
1
1
1
1
1
⎯
⎯
⎯
⎯
⎯
⎯
MOV
Rm,Rn
0110nnnnmmmm0011
0010nnnnmmmm0000
0010nnnnmmmm0001
0010nnnnmmmm0010
0110nnnnmmmm0000
MOV.B Rm,@Rn
MOV.W Rm,@Rn
MOV.L Rm,@Rn
MOV.B @Rm,Rn
Rm → (Rn)
Rm → (Rn)
Rm → (Rn)
(Rm) → Sign extension →
Rn
MOV.W @Rm,Rn
0110nnnnmmmm0001
(Rm) → Sign extension →
1
⎯
Rn
MOV.L @Rm,Rn
MOV.B Rm,@–Rn
MOV.W Rm,@–Rn
MOV.L Rm,@–Rn
MOV.B @Rm+,Rn
0110nnnnmmmm0010
0010nnnnmmmm0100
0010nnnnmmmm0101
0010nnnnmmmm0110
0110nnnnmmmm0100
(Rm) → Rn
1
1
1
1
1
⎯
⎯
⎯
⎯
⎯
Rn–1 → Rn, Rm → (Rn)
Rn–2 → Rn, Rm → (Rn)
Rn–4 → Rn, Rm → (Rn)
(Rm) → Sign extension →
Rn, Rm + 1 → Rm
MOV.W @Rm+,Rn
MOV.L @Rm+,Rn
0110nnnnmmmm0101
0110nnnnmmmm0110
(Rm) → Sign extension →
Rn, Rm + 2 → Rm
1
⎯
(Rm) → Rn, Rm + 4 → Rm
R0 → (disp + Rn)
1
1
1
1
1
⎯
⎯
⎯
⎯
⎯
MOV.B R0,@(disp,Rn) 10000000nnnndddd
MOV.W R0,@(disp,Rn) 10000001nnnndddd
MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
MOV.B @(disp,Rm),R0 10000100mmmmdddd
R0 → (disp × 2 + Rn)
Rm → (disp × 4 + Rn)
(disp + Rm) → Sign
extension → R0
MOV.W @(disp,Rm),R0 10000101mmmmdddd
(disp × 2 + Rm) → Sign
extension → R0
1
⎯
Rev.2.00 Sep. 27, 2007 Page 31 of 448
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2. CPU
Execu-
tion
T
Instruction
Instruction Code
Operation
States
Bit
MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
(disp × 4 + Rm) → Rn
Rm → (R0 + Rn)
Rm → (R0 + Rn)
Rm → (R0 + Rn)
1
1
1
1
1
⎯
⎯
⎯
⎯
⎯
MOV.B Rm,@(R0,Rn)
MOV.W Rm,@(R0,Rn)
MOV.L Rm,@(R0,Rn)
MOV.B @(R0,Rm),Rn
0000nnnnmmmm0100
0000nnnnmmmm0101
0000nnnnmmmm0110
0000nnnnmmmm1100
(R0 + Rm) → Sign
extension → Rn
MOV.W @(R0,Rm),Rn
0000nnnnmmmm1101
(R0 + Rm) → Sign
extension → Rn
1
⎯
MOV.L @(R0,Rm),Rn
0000nnnnmmmm1110
(R0 + Rm) → Rn
1
1
1
1
1
⎯
⎯
⎯
⎯
⎯
MOV.B R0,@(disp,GBR) 11000000dddddddd
MOV.W R0,@(disp,GBR) 11000001dddddddd
MOV.L R0,@(disp,GBR) 11000010dddddddd
MOV.B @(disp,GBR),R0 11000100dddddddd
R0 → (disp + GBR)
R0 → (disp × 2 + GBR)
R0 → (disp × 4 + GBR)
(disp + GBR) → Sign
extension → R0
MOV.W @(disp,GBR),R0 11000101dddddddd
(disp × 2 + GBR) → Sign
extension → R0
1
⎯
MOV.L @(disp,GBR),R0 11000110dddddddd
(disp × 4 + GBR) → R0
disp × 4 + PC → R0
T → Rn
1
1
1
1
⎯
⎯
⎯
⎯
MOVA
MOVT
@(disp,PC),R0 11000111dddddddd
Rn
0000nnnn00101001
0110nnnnmmmm1000
SWAP.B Rm,Rn
SWAP.W Rm,Rn
XTRCT Rm,Rn
Rm → Swap bottom two
bytes → Rn
0110nnnnmmmm1001
0010nnnnmmmm1101
Rm → Swap two
consecutive words → Rn
1
1
⎯
⎯
Rm: Middle 32 bits of
Rn → Rn
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2. CPU
Arithmetic Operation Instructions
Table 2.13 Arithmetic Operation Instructions
Execu-
tion
Instruction
Instruction Code
Operation
States
T Bit
⎯
ADD
Rm,Rn
0011nnnnmmmm1100 Rn + Rm → Rn
0111nnnniiiiiiii Rn + imm → Rn
1
1
1
ADD
#imm,Rn
Rm,Rn
⎯
ADDC
0011nnnnmmmm1110 Rn + Rm + T → Rn,
Carry → T
Carry
ADDV
Rm,Rn
0011nnnnmmmm1111 Rn + Rm → Rn,
Overflow → T
1
1
1
Overflow
CMP/EQ #imm,R0
CMP/EQ Rm,Rn
CMP/HS Rm,Rn
CMP/GE Rm,Rn
CMP/HI Rm,Rn
CMP/GT Rm,Rn
CMP/PL Rn
10001000iiiiiiii If R0 = imm, 1 → T
Comparison
result
0011nnnnmmmm0000 If Rn = Rm, 1 → T
Comparison
result
0011nnnnmmmm0010 If Rn ≥ Rm with unsigned 1
data, 1 → T
Comparison
result
0011nnnnmmmm0011 If Rn ≥ Rm with signed
data, 1 → T
1
Comparison
result
0011nnnnmmmm0110 If Rn > Rm with unsigned 1
data, 1 → T
Comparison
result
0011nnnnmmmm0111 If Rn > Rm with signed
data, 1 → T
1
1
1
1
Comparison
result
0100nnnn00010101 If Rn > 0, 1 → T
Comparison
result
CMP/PZ Rn
0100nnnn00010001 If Rn ≥ 0, 1 → T
Comparison
result
CMP/STR Rm,Rn
0010nnnnmmmm1100 If Rn and Rm have
Comparison
result
an equivalent byte,
1 → T
DIV1
Rm,Rn
Rm,Rn
0011nnnnmmmm0100 Single-step division (Rn
1
1
Calculation
result
÷ Rm)
DIV0S
0010nnnnmmmm0111 MSB of Rn → Q, MSB
of Rm → M, M ^ Q → T
Calculation
result
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2. CPU
Execu-
tion
Instruction
DIV0U
Instruction Code
Operation
States
T Bit
0
0000000000011001 0 → M/Q/T
1
DMULS.L Rm,Rn
0011nnnnmmmm1101 Signed operation of
Rn × Rm → MACH,
2 to 4*
⎯
MACL 32 × 32 → 64 bits
DMULU.L Rm,Rn
0011nnnnmmmm0101 Unsigned operation of
Rn × Rm → MACH,
2 to 4*
⎯
MACL 32 × 32 → 64 bits
DT
Rn
0100nnnn00010000 Rn – 1 → Rn, when Rn
is 0, 1 → T. When Rn is
1
Comparison
result
nonzero, 0 → T
EXTS.B Rm,Rn
EXTS.W Rm,Rn
EXTU.B Rm,Rn
EXTU.W Rm,Rn
0110nnnnmmmm1110 Byte in Rm is sign-
extended → Rn
1
1
1
1
⎯
⎯
⎯
⎯
⎯
0110nnnnmmmm1111 Word in Rm is sign-
extended → Rn
0110nnnnmmmm1100 Byte in Rm is zero-
extended → Rn
0110nnnnmmmm1101 Word in Rm is zero-
extended → Rn
MAC.L
MAC.W
MUL.L
@Rm+,@Rn+ 0000nnnnmmmm1111 Signed operation of
3/
(Rn) × (Rm) + MAC →
MAC 32 × 32 + 64 →
64 bits
(2 to 4)*
@Rm+,@Rn+ 0100nnnnmmmm1111 Signed operation of
3/(2)*
⎯
(Rn) × (Rm) + MAC →
MAC 16 × 16 + 64 →
64 bits
Rm,Rn
0000nnnnmmmm0111 Rn × Rm → MACL,
32 × 32 → 32 bits
2 to 4*
1 to 3*
⎯
⎯
MULS.W Rm,Rn
MULU.W Rm,Rn
0010nnnnmmmm1111 Signed operation of
Rn × Rm → MACL 16 ×
16 → 32 bits
0010nnnnmmmm1110 Unsigned operation of
Rn × Rm → MACL 16 ×
1 to 3*
⎯
16 → 32 bits
NEG
Rm,Rn
Rm,Rn
0110nnnnmmmm1011 0 – Rm → Rn
1
1
⎯
NEGC
0110nnnnmmmm1010 0 – Rm – T → Rn,
Borrow → T
Borrow
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2. CPU
Execu-
tion
States
Instruction
Instruction Code
Operation
T Bit
SUB
Rm,Rn
0011nnnnmmmm1000 Rn – Rm → Rn
1
1
⎯
SUBC
Rm,Rn
0011nnnnmmmm1010 Rn – Rm – T → Rn,
Borrow → T
Borrow
SUBV
Rm,Rn
0011nnnnmmmm1011 Rn – Rm → Rn,
Underflow → T
1
Overflow
Note:
*
The normal number of execution states is shown. (The number in parentheses is the
number of states when there is contention with the preceding or following instructions.)
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2. CPU
Logic Operation Instructions
Table 2.14 Logic Operation Instructions
Execu-
tion
Instruction
Instruction Code
Operation
States T Bit
AND
AND
Rm,Rn
#imm,R0
0010nnnnmmmm1001
11001001iiiiiiii
Rn & Rm → Rn
R0 & imm → R0
1
1
3
⎯
⎯
⎯
AND.B #imm,@(R0,GBR) 11001101iiiiiiii
(R0 + GBR) & imm →
(R0 + GBR)
NOT
OR
Rm,Rn
0110nnnnmmmm0111
0010nnnnmmmm1011
11001011iiiiiiii
~Rm → Rn
1
1
1
3
⎯
⎯
⎯
⎯
Rm,Rn
Rn | Rm → Rn
R0 | imm → R0
OR
#imm,R0
OR.B
#imm,@(R0,GBR) 11001111iiiiiiii
(R0 + GBR) | imm →
(R0 + GBR)
TAS.B @Rn
0100nnnn00011011
0010nnnnmmmm1000
11001000iiiiiiii
If (Rn) is 0, 1 → T; 1 →
MSB of (Rn)
4
1
1
Test
result
TST
TST
Rm,Rn
#imm,R0
Rn & Rm; if the result is
0, 1 → T
Test
result
R0 & imm; if the result is
Test
0, 1 → T
result
TST.B #imm,@(R0,GBR) 11001100iiiiiiii
(R0 + GBR) & imm; if the 3
Test
result is 0, 1 → T
result
XOR
XOR
Rm,Rn
0010nnnnmmmm1010
11001010iiiiiiii
Rn ^ Rm → Rn
R0 ^ imm → R0
1
1
⎯
⎯
⎯
#imm,R0
XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
(R0 + GBR) ^ imm → (R0 3
+ GBR)
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2. CPU
Shift Instructions
Table 2.15 Shift Instructions
Execu-
tion
Instruction
Instruction Code
Operation
States
T Bit
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
⎯
ROTL
ROTR
Rn
Rn
0100nnnn00000100
0100nnnn00000101
0100nnnn00100100
0100nnnn00100101
0100nnnn00100000
0100nnnn00100001
0100nnnn00000000
0100nnnn00000001
0100nnnn00001000
0100nnnn00001001
0100nnnn00011000
0100nnnn00011001
0100nnnn00101000
0100nnnn00101001
T ← Rn ← MSB
LSB → Rn → T
T ← Rn ← T
T → Rn → T
T ← Rn ← 0
MSB → Rn → T
T ← Rn ← 0
0 → Rn → T
Rn<<2 → Rn
Rn>>2 → Rn
Rn<<8 → Rn
Rn>>8 → Rn
Rn<<16 → Rn
Rn>>16 → Rn
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ROTCL Rn
ROTCR Rn
SHAL
SHAR
SHLL
SHLR
Rn
Rn
Rn
Rn
SHLL2 Rn
SHLR2 Rn
SHLL8 Rn
SHLR8 Rn
SHLL16 Rn
SHLR16 Rn
⎯
⎯
⎯
⎯
⎯
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2. CPU
Branch Instructions
Table 2.16 Branch Instructions
Execu-
tion
Instruction
Instruction Code
Operation
States
T Bit
BF
label
10001011dddddddd If T = 0, disp × 2 + PC → PC; if T =
3/1*
3/1*
3/1*
2/1*
2
⎯
1, nop
BF/S label
10001111dddddddd Delayed branch, if T = 0, disp × 2 +
PC → PC; if T = 1, nop
⎯
⎯
⎯
⎯
BT
BT/S label
BRA label
BRAF Rm
label
10001001dddddddd If T = 1, disp × 2 + PC → PC; if T =
0, nop
10001101dddddddd Delayed branch, if T = 1, disp × 2 +
PC → PC; if T = 0, nop
1010dddddddddddd Delayed branch, disp × 2 + PC →
PC
0000mmmm00100011 Delayed branch, Rm + PC → PC
2
2
⎯
⎯
BSR
label
1011dddddddddddd Delayed branch, PC → PR, disp × 2
+ PC → PC
BSRF Rm
0000mmmm00000011 Delayed branch, PC → PR,
Rm + PC → PC
2
⎯
JMP
JSR
@Rm
0100mmmm00101011 Delayed branch, Rm → PC
2
2
⎯
⎯
@Rm
0100mmmm00001011 Delayed branch, PC → PR,
Rm → PC
RTS
0000000000001011 Delayed branch, PR → PC
2
⎯
Note:
*
One state when the program does not branch.
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2. CPU
System Control Instructions
Table 2.17 System Control Instructions
Execu-
tion
Instruction
CLRT
Instruction Code
Operation
States T Bit
0000000000001000
0000000000101000
0100mmmm00001110
0100mmmm00011110
0100mmmm00101110
0100mmmm00000111
0100mmmm00010111
0100mmmm00100111
0100mmmm00001010
0100mmmm00011010
0100mmmm00101010
0100mmmm00000110
0100mmmm00010110
0100mmmm00100110
0000000000001001
0000000000101011
0 → T
1
1
1
1
1
3
3
3
1
1
1
1
1
1
1
4
0
CLRMAC
0 → MACH, MACL
Rm → SR
⎯
LSB
⎯
⎯
LSB
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
LDC
LDC
LDC
Rm,SR
Rm,GBR
Rm,VBR
Rm → GBR
Rm → VBR
LDC.L @Rm+,SR
LDC.L @Rm+,GBR
LDC.L @Rm+,VBR
(Rm) → SR, Rm + 4 → Rm
(Rm) → GBR, Rm + 4 → Rm
(Rm) → VBR, Rm + 4 → Rm
Rm → MACH
LDS
LDS
LDS
Rm,MACH
Rm,MACL
Rm,PR
Rm → MACL
Rm → PR
LDS.L @Rm+,MACH
LDS.L @Rm+,MACL
LDS.L @Rm+,PR
NOP
(Rm) → MACH, Rm + 4 → Rm
(Rm) → MACL, Rm + 4 → Rm
(Rm) → PR, Rm + 4 → Rm
No operation
RTE
Delayed branch, stack area
→ PC/SR
SETT
0000000000011000
0000000000011011
0000nnnn00000010
0000nnnn00010010
0000nnnn00100010
0100nnnn00000011
0100nnnn00010011
0100nnnn00100011
1 → T
1
1
SLEEP
Sleep
3*
1
⎯
⎯
⎯
⎯
⎯
⎯
⎯
STC
STC
STC
SR,Rn
SR → Rn
GBR,Rn
VBR,Rn
GBR → Rn
1
VBR → Rn
1
STC.L SR,@–Rn
STC.L GBR,@–Rn
STC.L VBR,@–Rn
Rn – 4 → Rn, SR → (Rn)
Rn – 4 → Rn, GBR → (Rn)
Rn – 4 → Rn, VBR → (Rn)
2
2
2
Rev.2.00 Sep. 27, 2007 Page 39 of 448
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2. CPU
Execu-
tion
Instruction
Instruction Code
Operation
States T Bit
STS
STS
STS
MACH,Rn
0000nnnn00001010
0000nnnn00011010
0000nnnn00101010
0100nnnn00000010
0100nnnn00010010
0100nnnn00100010
11000011iiiiiiii
MACH → Rn
1
1
1
1
1
1
8
⎯
⎯
⎯
⎯
⎯
⎯
⎯
MACL,Rn
PR,Rn
MACL → Rn
PR → Rn
STS.L MACH,@–Rn
STS.L MACL,@–Rn
STS.L PR,@–Rn
TRAPA #imm
Rn – 4 → Rn, MACH → (Rn)
Rn – 4 → Rn, MACL → (Rn)
Rn – 4 → Rn, PR → (Rn)
PC/SR → stack area, (imm × 4
+ VBR) → PC
Note:
*
The number of execution states before the chip enters sleep mode: The execution
states shown in the table are minimums. The actual number of states may be increased
when (1) contention occurs between instruction fetches and data access, or (2) when
the destination register of the load instruction (memory → register) equals to the
register used by the next instruction.
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2. CPU
2.6
Processing States
2.6.1
State Transitions
The CPU has four processing states: reset, exception processing, program execution and power-
down. Figure 2.4 shows the transitions between the states.
From any state
From any state
when RES = 1
when RES = 0
and MRES = 0
Power-on reset state
Manual reset state
RES = 0
Reset state
RES = 1,
RES = 1
MRES = 1
Exception
processing state
When a power-on reset
or manual reset
occurred by WDT
NMI or IRQ
interrupt occurs
Exception
processing
source
Exception
processing
ends
occurs
Program execution state
SSBY bit cleared
for SLEEP
instruction
SSBY bit set
for SLEEP
instruction
Sleep mode
Software standby mode
Power-down state
Figure 2.4 Transitions between Processing States
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2. CPU
Reset State: The CPU resets in the reset state. When the RES pin level goes low, the power-on
reset state is entered. When the RES pin is high and the MRES pin is low, the manual reset state is
entered.
Exception Processing State: The exception processing state is a transient state that occurs when
exception processing sources such as resets or interrupts alter the CPU's processing state flow.
For a reset, the initial values of the program counter (PC) (execution start address) and stack
pointer (SP) are fetched from the exception processing vector table and stored; the CPU then
branches to the execution start address and execution of the program begins.
For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status
register (SR) are saved to the stack area. The exception service routine start address is fetched
from the exception processing vector table; the CPU then branches to that address and the program
starts executing, thereby entering the program execution state.
Program Execution State: In the program execution state, the CPU sequentially executes the
program.
Power-Down State: In the power-down state, the CPU operation halts and power consumption
declines. The SLEEP instruction places the CPU in the sleep mode or the software standby mode.
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3. MCU Operating Modes
Section 3 MCU Operating Modes
3.1
Selection of Operating Modes
This LSI has one operating mode and four clock modes. The operating mode is determined by the
setting of MD3 to MD0, and FWP pins. Do not change these pins during LSI operation (while
power is on). Do not set these pins in the other way than the combination shown in table 3.1. This
LSI supports only mode 3.
Table 3.1 Selection of Operating Modes
Pin Setting
Mode
No.
FWP MD3
MD2
MD1 MD0 Mode Name
On-Chip ROM
Mode 3
1
x
x
1
1
Single chip mode
Active
Note: The symbol x means “Don't care.”
The clock mode is selected by the input of MD2 and MD3 pins.
Table 3.2 Maximum Operating Clock Frequency for Each Clock Mode
Pin Setting
MD3
MD2
Maximum Operating Clock Frequency
0
0
1
1
0
1
0
1
10 MHz (Input clock × 1, maximum of input clock: 10 MHz)
20 MHz (Input clock × 2, maximum of input clock: 10 MHz)
40 MHz (Input clock × 4*, maximum of input clock: 10 MHz)
40 MHz (Input clock × 4 for system clock, Input clock × 2 for
peripheral clock, maximum of input clock: 10 MHz)
Note:
*
The maximum of input clock is 10 MHz so that Pφ is lower or equal to 40 MHz.
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3. MCU Operating Modes
3.2
Input/Output Pins
Table 3.3 describes the configuration of operating mode related pins.
Table 3.3 Operating Mode Pin Configuration
Pin Name
MD0
Input/Output Function
Input
Input
Input
Input
Input
Designates operating mode through the level applied to this pin
MD1
Designates operating mode through the level applied to this pin
Designates clock mode through the level applied to this pin
Designates clock mode through the level applied to this pin
MD2
MD3
FWP
Pin for the hardware protection against writing/erasing the on-chip
flash memory. In this LSI, conncet this pin to VCC.
3.3
Explanation of Operating Modes
This LSI does not support modes 0 to 2 (MCU extension mode 0 to 2).
3.3.1 Mode 3 (Single chip mode)
All ports can be used in this mode, however the external address cannot be used. The SH7101
supports only this mode.
3.3.2
Clock Mode
The input waveform frequency can be used as is, doubled or quadrupled as system clock
frequency.
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3. MCU Operating Modes
3.4
Address Map
Figure 3.1 shows the address map.
ROM: 32 kbytes, RAM: 2 kbytes
Mode 3
H'00000000
On-chip ROM
H'00007FFF
H'FFFF8000
On-chip peripheral
I/O registers
H'FFFFBFFF
H'FFFFF800
On-chip RAM
H'FFFFFFFF
Figure 3.1 Address Map for SH7101 Mask ROM Version
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3. MCU Operating Modes
3.5
Initial State of This LSI
To reduce power consumption, some modules are set to the module standby states in the initial
state in this LSI. Therefore, the module standby states should be cancelled to activate these
modules. For details, see section 17, Power-Down Modes.
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4. Clock Pulse Generator
Section 4 Clock Pulse Generator
This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (φ), internal
clock (φ/2 to φ/8192, Pφ/2 to Pφ/1024), and peripheral clock (Pφ). The CPG consists of an
oscillator, PLL circuit, and prescaler. A block diagram of the clock pulse generator is shown in
figure 4.1. The frequency from the oscillator can be modified by the PLL circuit.
PLLCAP
EXTAL
Clock divider
PLL circuit
Oscillator
(× 1/2)
XTAL
Prescaler
Prescaler
MD2
MD3
Clock mode
control circuitry
φ
φ/2 to
φ/8192
Pφ/2 to
Pφ/1024
Pφ
Within the LSI
Figure 4.1 Block Diagram of Clock Pulse Generator
4.1
Oscillator
Clock pulses can be supplied from a connected crystal resonator or an external clock.
4.1.1 Connecting Crystal Resonator
Circuit Configuration: A crystal resonator can be connected as shown in figure 4.2. Use the
damping resistance (Rd) listed in table 4.1. Use an AT-cut parallel-resonance type crystal
resonator that has a resonance frequency of 4 to 10 MHz. It is recommended to consult crystal
dealer concerning the compatibility of the crystal resonator and the LSI.
CPG0100A_010020030200
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4. Clock Pulse Generator
CL1
EXTAL
XTAL
Rd
CL2
CL1 = CL2 = 18–22 pF (Recommended value)
Figure 4.2 Connection of Crystal Resonator (Example)
Table 4.1 Damping Resistance Values
Frequency (MHz)
4
8
10
0
Rd (Ω)
500
200
Crystal Resonator: Figure 4.3 shows an equivalent circuit of the crystal resonator. Use a crystal
resonator with the characteristics listed in table 4.2.
CL
L
R
s
XTAL
EXTAL
AT-cut parallel-resonance type
C0
Figure 4.3 Crystal Resonator Equivalent Circuit
Table 4.2 Crystal Resonator Characteristics
Frequency (MHz)
Rs max (Ω)
4
8
10
60
7
120
7
80
7
C0 max (pF)
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4. Clock Pulse Generator
4.1.2
External Clock Input Method
Figure 4.4 shows an example of an external clock input connection. In this case, make the external
clock high level to stop it in standby mode. During operation, make the external input clock
frequency 4 to 10 MHz.
When leaving the XTAL pin open, make sure the parasitic capacitance is less than 10 pF.
Even when inputting an external clock, be sure to wait at least the oscillation stabilization time in
power-on sequence or in releasing standby mode, in order to ensure the PLL stabilization time.
EXTAL
XTAL
External clock input
Open state
Figure 4.4 Example of External Clock Connection
4.2
Function for Detecting Oscillator Halt
This CPG can detect a clock halt and automatically cause the timer pins to become high-
impedance when any system abnormality causes the oscillator to halt. That is, when a change of
EXTAL has not been detected, the high-current six pins (PE9/TIOC3B, PE11/TIOC3D,
PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C, and PE15/TIOC4D/IRQOUT) are set to
high-impedance regardless of PFC setting.
Even in standby mode, these six pins become high-impedance regardless of PFC setting. These
pins enter the normal state after standby mode is released. When abnormalities that halt the
oscillator occur except in standby mode, other LSI operations become undefined. In this case, LSI
operations, including these six pins, become undefined even when the oscillator operation starts
again.
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4. Clock Pulse Generator
4.3
Usage Notes
4.3.1
Note on Crystal Resonator
A sufficient evaluation at the user's site is necessary to use the LSI, by referring the resonator
connection examples shown in this section, because various characteristics related to the crystal
resonator are closely linked to the user's board design. As the resonator circuit ratings will depend
on the resonator and the floating capacitance of the mounting circuit, the ratings should be
determined in consultation with the resonator manufacturer. Ensure that a voltage exceeding the
maximum rating is not applied to the oscillator pin.
4.3.2
Notes on Board Design
Measures against radiation noise are taken in this LSI. If radiation noise needs to be further
reduced, usage of a multi-layer printed circuit board with ground planes is recommended.
When using a crystal resonator, place the crystal resonator and its load capacitors as close as
possible to the XTAL and EXTAL pins. Do not route any signal lines near the oscillator circuitry
as shown in figure 4.5. Otherwise, correct oscillation can be interfered by induction.
Avoid
Signal A Signal B
This LSI
XTAL
CL2
EXTAL
CL1
Figure 4.5 Cautions for Oscillator Circuit System Board Design
A circuitry shown in figure 4.6 is recommended as an external circuitry around the PLL. Place
oscillation stabilization capacitor C1 close to the PLLCAP pin, and ensure that no other signal
lines cross this line. Separate PLLVCL, PLLVSS, VCC, and VSS from the board power supply source,
and be sure to insert bypass capacitors CB close to the pins.
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4. Clock Pulse Generator
R1: 3 kΩ
C1: 470 pF
PLLCAP
PLLVCL
*
CPB = 0.47 μF
PLLVSS
VCC
VSS
*
CB = 0.47 μF
(Values are recommended values.)
Note: * CB and CPB are laminated ceramic type.
Figure 4.6 Recommended External Circuitry around PLL
Electromagnetic waves are radiated from an LSI in operation. This LSI has an electromagnetic
peak in the harmonics band whose primary frequency is determined by the lower frequency
between the system clock (φ) and peripheral clock (Pφ). For example, when φ = 40 MHz and Pφ =
40 MHz, the primary frequency is 40 MHz. If this LSI is used adjacent to a device sensitive to
electromagnetic interference, e.g. FM/VHF band receiver, a printed circuit board of more than
four layers with planes exclusively for system ground is recommended.
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4. Clock Pulse Generator
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5. Exception Processing
Section 5 Exception Processing
5.1
Overview
5.1.1
Types of Exception Processing and Priority
Exception processing is started by four sources: resets, address errors, interrupts and instructions
and have the priority, as shown in table 5.1. When several exception processing sources occur at
once, they are processed according to the priority.
Table 5.1 Types of Exception Processing and Priority
Exception
Source
Priority
Reset
Power-on reset
Manual reset
High
Address error CPU address error
Interrupt
NMI
IRQ
On-chip peripheral
modules:
•
•
•
•
•
•
Multifunction timer unit (MTU)
A/D converter 0 and 1 (A/D0, A/D1)
Compare match timer 0 and 1 (CMT0, CMT1)
Watchdog timer (WDT)
Input/output port (I/O) (MTU)
Serial communication interface 2 and 3 (SCI2,
SCI3)
Instructions
Trap instruction (TRAPA instruction)
General illegal instructions (undefined code)
Illegal slot instructions (undefined code placed directly after a delayed
branch instruction*1 or instructions that rewrite the PC*2)
Low
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and
BRAF.
2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, and BRAF.
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5. Exception Processing
5.1.2
Exception Processing Operations
The exception processing sources are detected and the processing starts according to the timing
shown in table 5.2.
Table 5.2 Timing for Exception Source Detection and Start of Exception Processing
Exception
Source
Timing of Source Detection and Start of Processing
Reset
Power-on reset
Starts when the RES pin changes from low to high or when
WDT overflows.
Manual reset
Starts when the MRES pin changes from low to high.
Address error
Interrupts
Detected when instruction is decoded and starts when the
execution of the previous instruction is completed.
Instructions Trap instruction
Starts from the execution of a TRAPA instruction.
General illegal
instructions
Starts from the decoding of undefined code anytime except
after a delayed branch instruction (delay slot).
Illegal slot
instructions
Starts from the decoding of undefined code placed in a delayed
branch instruction (delay slot) or of instructions that rewrite the
PC.
When exception processing starts, the CPU operates as follows:
1. Exception processing triggered by reset:
The initial values of the program counter (PC) and stack pointer (SP) are fetched from the
exception processing vector table (PC and SP are respectively the H'00000000 and
H'00000004 addresses for power-on resets and the H'00000008 and H'0000000C addresses for
manual resets). See section 5.1.3, Exception Processing Vector Table, for more information.
H'00000000 is then written to the vector base register (VBR), and H'F (B'1111) is written to
the interrupt mask bits (I3 to I0) of the status register (SR). The program begins running from
the PC address fetched from the exception processing vector table.
2. Exception processing triggered by address errors, interrupts and instructions:
SR and PC are saved to the stack indicated by R15. For interrupt exception processing, the
interrupt priority level is written to the SR's interrupt mask bits (I3 to I0). For address error and
instruction exception processing, the I3 to I0 bits are not affected. The start address is then
fetched from the exception processing vector table and the program begins running from that
address.
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5. Exception Processing
5.1.3
Exception Processing Vector Table
Before exception processing begins running, the exception processing vector table must be set in
memory. The exception processing vector table stores the start addresses of exception service
routines. (The reset exception processing table holds the initial values of PC and SP.)
All exception sources are given different vector numbers and vector table address offsets. The
vector table addresses are calculated from these vector numbers and vector table address offsets.
During exception processing, the start addresses of the exception service routines are fetched from
the exception processing vector table that is indicated by this vector table address.
Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector
table addresses are calculated.
Table 5.3 Exception Processing Vector Table
Exception Sources
Vector Numbers
Vector Table Address Offset
H'00000000 to H'00000003
H'00000004 to H'00000007
H'00000008 to H'0000000B
H'0000000C to H'0000000F
H'00000010 to H'00000013
H'00000014 to H'00000017
H'00000018 to H'0000001B
H'0000001C to H'0000001F
H'00000020 to H'00000023
H'00000024 to H'00000027
H'00000028 to H'0000002B
H'0000002C to H'0000002F
H'00000030 to H'00000033
Power-on reset
PC
SP
PC
SP
0
1
Manual reset
2
3
General illegal instruction
(Reserved by system)
Slot illegal instruction
(Reserved by system)
4
5
6
7
8
CPU address error
9
(Reserved by system)
10
11
12
Interrupts
NMI
(Reserved by
system)
(Reserved by system)
(Reserved by system)
(Reserved by system)
13
14
H'00000034 to H'00000037
H'00000038 to H'0000003B
15
:
H'0000003C to H'0000003F
:
31
H'0000007C to H'0000007F
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5. Exception Processing
Exception Sources
Vector Numbers
Vector Table Address Offset
Trap instruction (user vector)
32
:
H'00000080 to H'00000083
:
63
H'000000FC to H'000000FF
Interrupts
IRQ0
64
65
66
67
68
69
70
71
H'00000100 to H'00000103
H'00000104 to H'00000107
H'00000108 to H'0000010B
H'0000010C to H'0000010F
H'00000110 to H'00000113
H'00000114 to H'00000117
H'00000118 to H'0000011B
H'0000011C to H'0000011F
IRQ1
IRQ2
IRQ3
Reserved by system
Reserved by system
Reserved by system
Reserved by system
On-chip peripheral module *
72
:
H'00000120 to H'00000124
:
255
H'000003FC to H'000003FF
Note:
*
The vector numbers and vector table address offsets for each on-chip peripheral
module interrupt are given in section 6, Interrupt Controller (INTC), and table 6.2,
Interrupt Exception Processing Vectors and Priorities.
Table 5.4 Calculating Exception Processing Vector Table Addresses
Exception Source
Vector Table Address Calculation
Resets
Vector table address = (vector table address offset)
= (vector number) × 4
Address errors, interrupts,
instructions
Vector table address = VBR + (vector table address offset)
= VBR + (vector number) × 4
Notes: 1. VBR: Vector base register
2. Vector table address offset: See table 5.3.
3. Vector number: See table 5.3.
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5. Exception Processing
5.2
Resets
5.2.1
Types of Reset
Resets have the highest priority of any exception source. There are two types of resets: manual
resets and power-on resets. As table 5.5 shows, both types of resets initialize the internal status of
the CPU. In power-on resets, all registers of the on-chip peripheral modules are initialized; in
manual resets, they are not.
Table 5.5 Reset Status
Conditions for Transition
to Reset Status
Internal Status
On-Chip
Peripheral
Module
WDT
Overflow MRES
Type
RES
Low
High
High
CPU/INTC
Initialized
Initialized
Initialized
PFC, IO Port
Initialized
Power-on reset
⎯
⎯
Initialized
Initialized
Overflow High
Low
Not initialized
Manual reset
⎯
Not initialized Not initialized
5.2.2
Power-On Reset
Power-On Reset by RES Pin: When the RES pin is driven low, the LSI becomes to be a power-
on reset state. To reliably reset the LSI, the RES pin should be kept at low for at least the duration
of the oscillation settling time when applying power or when in standby mode (when the clock
circuit is halted) or at least 25 tcyc when the clock circuit is running. During power-on reset, CPU
internal status and all registers of on-chip peripheral modules are initialized. See appendix A, Pin
States, for the status of individual pins during the power-on reset status.
In the power-on reset status, power-on reset exception processing starts when the RES pin is first
driven low for a set period of time and then returned to high. The CPU will then operate as
follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the
exception processing vector table.
2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table.
3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0)
of the status register (SR) are set to H'F (B'1111).
4. The values fetched from the exception processing vector table are set in PC and SP, then the
program begins executing.
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5. Exception Processing
Be certain to always perform power-on reset processing when turning the system power on.
Power-On Reset by WDT: When a setting is made for a power-on reset to be generated in the
WDT's watchdog timer mode, and the WDT's TCNT overflows, the LSI becomes to be a power-
on reset state.
The pin function controller (PFC) registers and I/O port registers are not initialized by the reset
signal generated by the WDT (these registers are initialized only by a power-on reset from outside
of the chip).
If reset caused by the input signal at the RES pin and a reset caused by WDT overflow occur
simultaneously, the RES pin reset has priority, and the WOVF bit in RSTCSR is cleared to 0.
When WDT-initiated power-on reset processing is started, the CPU operates as follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the
exception processing vector table.
2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table.
3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3-I0) of
the status register (SR) are set to H'F (B'1111).
4. The values fetched from the exception processing vector table are set in the PC and SP, then
the program begins executing.
5.2.3
Manual Reset
When the RES pin is high and the MRES pin is driven low, the LSI enters a manual reset state. To
reliably reset the LSI, the MRES pin should be kept at low for at least the duration of the
oscillation settling time that is set in WDT in standby mode (when the clock is halted) or at least
25 tcyc when the clock is operating. During manual reset, the CPU internal status is initialized.
Registers of on-chip peripheral modules are not initialized. When the LSI enters manual reset
status in the middle of a bus cycle, manual reset exception processing does not start until the bus
cycle has ended. Thus, manual resets do not abort bus cycles. However, once MRES is driven low,
hold the low level until the CPU becomes to be a manual reset mode after the bus cycle ends.
(Keep at low level for at least the longest bus cycle). See appendix A, Pin States, for the status of
individual pins during manual reset mode.
In the manual reset status, manual reset exception processing starts when the MRES pin is first
kept low for a set period of time and then returned to high. The CPU will then operate in the same
procedures as described for power-on resets.
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5. Exception Processing
5.3
Address Errors
5.3.1
Cause of Address Error Exception
Address errors occur when instructions are fetched or data is read or written, as shown in table 5.6.
Table 5.6 Bus Cycles and Address Errors
Bus Cycle
Type
Bus Master Bus Cycle Description
Address Errors
None (normal)
Instruction CPU
fetch
Instruction fetched from even address
Instruction fetched from odd address
Address error occurs
None (normal)
Instruction fetched from other than on-chip
peripheral module space*
Instruction fetched from on-chip peripheral
module space*
Address error occurs
Address error occurs
Instruction fetched from external memory
space when in single chip mode
Data
read/write
CPU
Word data accessed from even address
Word data accessed from odd address
None (normal)
Address error occurs
None (normal)
Longword data accessed from a longword
boundary
Longword data accessed from other than a
long-word boundary
Address error occurs
None (normal)
Byte or word data accessed in on-chip
peripheral module space*
Longword data accessed in 16-bit on-chip
None (normal)
peripheral module space*
Longword data accessed in 8-bit on-chip
peripheral module space*
Address error occurs
Address error occurs
External memory space accessed when in
single chip mode
Note:
*
See section 7, Bus State Controller (BSC) for more information on the on-chip
peripheral module space.
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5. Exception Processing
5.3.2
Address Error Exception Processing
When an address error occurs, the bus cycle in which the address error occurred ends, the current
instruction finishes, and then address error exception processing starts. The CPU operates as
follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the last executed instruction.
3. The start address of the exception service routine is fetched from the exception processing
vector table that corresponds to the occurred address error, and the program starts executing
from that address. The jump in this case is not a delayed branch.
5.4
Interrupts
5.4.1
Interrupt Sources
Table 5.7 shows the sources that start the interrupt exception processing. They are NMI, IRQ and
on-chip peripheral modules.
Table 5.7 Interrupt Sources
Type
Request Source
Number of Sources
NMI
NMI pin (external input)
IRQ0 to IRQ3 pins (external input)
Multifunction timer unit
Compare match timer
A/D converter (A/D0 and A/D1)
Serial communication interface
Watchdog timer
1
IRQ
4
On-chip peripheral module
23
2
2
8
1
Input/output port
1
Each interrupt source is allocated a different vector number and vector table offset. See section 6,
Interrupt Controller (INTC), and table 6.2, Interrupt Exception Processing Vectors and Priorities,
for more information on vector numbers and vector table address offsets.
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5. Exception Processing
5.4.2
Interrupt Priority Level
The interrupt priority is predetermined. When multiple interrupts occur simultaneously
(overlapped interruptions), the interrupt controller (INTC) determines their relative priorities and
starts the exception processing according to the results.
The priority of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and
priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always
accepted. IRQ interrupts and on-chip peripheral module interrupt priority levels can be set freely
using the INTC's interrupt priority registers A, D to I (IPRA, IPRD to IPRI) as shown in table 5.8.
The priority levels that can be set are 0 to 15. Level 16 cannot be set. See section 6.3.4, Interrupt
Priority Registers A, D to I (IPRA, IPRD to IPRI), for more information on IPRA, IPRD to IPRI.
Table 5.8 Interrupt Priority
Type
Priority Level
16
Comment
NMI
Fixed priority level. Cannot be masked.
IRQ
0 to 15
Set with interrupt priority registers A, D to I
(IPRA, IPRD to IPRI).
On-chip peripheral module
5.4.3
Interrupt Exception Processing
When an interrupt occurs, the interrupt controller (INTC) ascertains its priority level. NMI is
always accepted, but other interrupts are only accepted if they have a priority level higher than the
priority level set in the interrupt mask bits (I3 to I0) of the status register (SR).
When an interrupt is accepted, exception processing begins. In interrupt exception processing, the
CPU saves SR and the program counter (PC) to the stack. The priority level value of the accepted
interrupt is written to SR bits I3 to I0. For NMI, however, the priority level is 16, but the value set
in I3 to I0 is H'F (level 15). Next, the start address of the exception service routine is fetched from
the exception processing vector table for the accepted interrupt, that address is jumped to and
execution begins. See section 6.6, Operation, for more information on the interrupt exception
processing.
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5. Exception Processing
5.5
Exceptions Triggered by Instructions
5.5.1
Types of Exceptions Triggered by Instructions
Exception processing can be triggered by trap instruction, illegal slot instructions, and general
illegal instructions, as shown in table 5.9.
Table 5.9 Types of Exceptions Triggered by Instructions
Type
Source Instruction
Comment
Trap instruction
TRAPA
⎯
Illegal slot
instructions
Undefined code placed
immediately after a delayed
Delayed branch instructions: JMP, JSR,
BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
branch instruction (delay slot) or BRAF
instructions that rewrite the PC
Instructions that rewrite the PC: JMP, JSR,
BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF
General illegal
instructions
Undefined code anywhere
besides in a delay slot
⎯
5.5.2
Trap Instructions
When a TRAPA instruction is executed, trap instruction exception processing starts. The CPU
operates as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the TRAPA instruction.
3. The CPU reads the start address of the exception service routine from the exception processing
vector table that corresponds to the vector number specified in the TRAPA instruction, jumps
to that address and starts executing the program. This jump is not a delayed branch.
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5. Exception Processing
5.5.3
Illegal Slot Instructions
An instruction placed immediately after a delayed branch instruction is called “instruction placed
in a delay slot”. When the instruction placed in the delay slot is an undefined code, illegal slot
exception processing starts after the undefined code is decoded. Illegal slot exception processing
also starts when an instruction that rewrites the program counter (PC) is placed in a delay slot and
the instruction is decoded. The CPU handles an illegal slot instruction as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the target address of the
delayed branch instruction immediately before the undefined code or the instruction that
rewrites the PC.
3. The start address of the exception service routine is fetched from the exception processing
vector table that corresponds to the exception that occurred. That address is jumped to and the
program starts executing. The jump in this case is not a delayed branch.
5.5.4
General Illegal Instructions
When undefined code placed anywhere other than immediately after a delayed branch instruction
(i.e., in a delay slot) is decoded, general illegal instruction exception processing starts. The CPU
handles the general illegal instructions in the same procedures as in the illegal slot instructions.
Unlike processing of illegal slot instructions, however, the program counter value that is stacked is
the start address of the undefined code.
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5. Exception Processing
5.6
Cases when Exception Sources are Not Accepted
When an address error or interrupt is generated directly after a delayed branch instruction or
interrupt-disabled instruction, it is sometimes not accepted immediately but stored instead, as
shown in table 5.10. In this case, it will be accepted when an instruction that can accept the
exception is decoded.
Table 5.10 Generation of Exception Sources Immediately after Delayed Branch Instruction
or Interrupt-Disabled Instruction
Exception Source
Point of Occurrence
Address Error
Not accepted
Accepted
Interrupt
Immediately after a delayed branch instruction*1
Immediately after an interrupt-disabled instruction*2
Not accepted
Not accepted
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and
BRAF
2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, and STS.L
5.6.1
Immediately after Delayed Branch Instruction
When an instruction placed immediately after a delayed branch instruction (delay slot) is decoded,
neither address errors nor interrupts are accepted. The delayed branch instruction and the
instruction placed immediately after it (delay slot) are always executed consecutively, so no
exception processing occurs during this period.
5.6.2
Immediately after Interrupt-Disabled Instruction
When an instruction placed immediately after an interrupt-disabled instruction is decoded,
interrupts are not accepted. Address errors can be accepted.
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5. Exception Processing
5.7
Stack Status after Exception Processing Ends
The status of the stack after exception processing ends is shown in table 5.11.
Table 5.11 Stack Status after Exception Processing Ends
Types
Stack Status
Address error
Address of instruction
32 bits
32 bits
SP
SP
SP
SP
SP
after executed instruction
SR
Trap instruction
Address of instruction
after TRAPA instruction
32 bits
32 bits
SR
General illegal instruction
Address of instruction after
general illegal instruction
32 bits
32 bits
SR
Interrupt
Address of instruction
after executed instruction
32 bits
32 bits
SR
Illegal slot instruction
Jump destination address
of delay branch instruction
32 bits
32 bits
SR
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5. Exception Processing
5.8
Usage Notes
5.8.1
Value of Stack Pointer (SP)
The value of the stack pointer must always be a multiple of four. If it is not, an address error will
occur when the stack is accessed during exception processing.
5.8.2
Value of Vector Base Register (VBR)
The value of the vector base register must always be a multiple of four. If it is not, an address error
will occur when the stack is accessed during exception processing.
5.8.3
Address Errors Caused by Stacking of Address Error Exception Processing
When the value of the stack pointer is not a multiple of four, an address error will occur during
stacking of the exception processing (interrupts, etc.) and address error exception processing will
start after the first exception processing is ended. Address errors will also occur in the stacking for
this address error exception processing. To ensure that address error exception processing does not
go into an endless loop, no address errors are accepted at that point. This allows program control
to be shifted to the service routine for address error exception and enables error processing.
When an address error occurs during exception processing stacking, the stacking bus cycle (write)
is executed. During stacking of the status register (SR) and program counter (PC), the value of SP
is reduced by 4 for both of SR and PC, therefore the value of SP is still not a multiple of four after
the stacking. The address value output during stacking is the SP value, so the address itself where
the error occurred is output. This means that the write data stacked is undefined.
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6. Interrupt Controller (INTC)
Section 6 Interrupt Controller (INTC)
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt
requests to the CPU.
6.1
Features
•
•
•
16 levels of interrupt priority
NMI noise canceler function
Occurrence of interrupt can be reported externally (IRQOUT pin)
Figure 6.1 shows a block diagram of the INTC.
IRQOUT
NMI
IRQ0
Input
control
Com-
parator
IRQ1
Interrupt
request
IRQ2
IRQ3
SR
(Interrupt request)
MTU
I3 I2 I1 I0
(Interrupt request)
CMT
(Interrupt request)
A/D
CPU
(Interrupt request)
SCI
(Interrupt request)
WDT
(Interrupt request)
I/O
ICR1
ICR2
ISR
IPR
IPRA to IPRI
Bus
interface
Module bus
INTC
Legend:
MTU : Multifunction timer unit
CMT : Compare match timer
A/D : A/D converter
I/O
ICR1, ICR2
ISR
: I/O port (Port output controller)
: Interrupt control register
: IRQ status register
SCI : Serial communications interface IPRA, IPRD to IPRI: Interrupt priority registers A, D to I
WDT : Watchdog timer SR : Status register
Figure 6.1 INTC Block Diagram
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6. Interrupt Controller (INTC)
6.2
Input/Output Pins
Table 6.1 shows the INTC pin configuration.
Table 6.1 Pin Configuration
Name
Abbreviation I/O
Function
Non-maskable interrupt input pin
NMI
I
Input of non-maskable interrupt
request signal
Interrupt request input pins
Interrupt request output pin
IRQ0 to IRQ3
IRQOUT
I
Input of maskable interrupt request
signals
O
Output of notification signal when an
interrupt has occurred
6.3
Register Descriptions
The interrupt controller has the following registers. For details on register addresses and register
states during each processing, refer to section 18, List of Registers.
•
•
•
•
•
•
•
•
•
•
Interrupt control register 1 (ICR1)
Interrupt control register 2 (ICR2)
IRQ status register (ISR)
Interrupt priority register A (IPRA)
Interrupt priority register D (IPRD)
Interrupt priority register E (IPRE)
Interrupt priority register F (IPRF)
Interrupt priority register G (IPRG)
Interrupt priority register H (IPRH)
Interrupt priority register I (IPRI)
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6. Interrupt Controller (INTC)
6.3.1
Interrupt Control Register 1 (ICR1)
ICR1 is a 16-bit register that sets the input signal detection mode of the external interrupt input
pins NMI and IRQ0 to IRQ3 and indicates the input signal level at the NMI pin.
Initial
Bit
Bit Name Value
R/W
Description
15
NMIL
1/0
R
NMI Input Level
Sets the level of the signal input to the NMI pin. This bit
can be read to determine the NMI pin level. This bit
cannot be modified.
0: NMI input level is low
1: NMI input level is high
14 to 9 ⎯
All 0
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
8
7
NMIE
R/W
NMI Edge Select
0: Interrupt request is detected on falling edge of NMI
input (Initial value)
1: Interrupt request is detected on rising edge of NMI
input
IRQ0S
IRQ1S
IRQ2S
0
0
0
R/W
R/W
R/W
IRQ0 Sense Select
This bit sets the IRQ0 interrupt request detection mode.
0: Interrupt request is detected on low level of IRQ0 input
1: Interrupt request is detected on edge of IRQ0 input
(edge direction is selected by ICR2)
6
5
IRQ1 Sense Select
This bit sets the IRQ1 interrupt request detection mode.
0: Interrupt request is detected on low level of IRQ1 input
1: Interrupt request is detected on edge of IRQ1 input
(edge direction is selected by ICR2)
IRQ2 Sense Select
This bit sets the IRQ2 interrupt request detection mode.
0: Interrupt request is detected on low level of IRQ2 input
1: Interrupt request is detected on edge of IRQ2 input
(edge direction is selected by ICR2)
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6. Interrupt Controller (INTC)
Initial
Bit
Bit Name Value
R/W
Description
4
IRQ3S
0
R/W
IRQ3 Sense Select
This bit sets the IRQ3 interrupt request detection mode.
0: Interrupt request is detected on low level of IRQ3 input
1: Interrupt request is detected on edge of IRQ3 input
(edge direction is selected by ICR2)
3 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
6.3.2
Interrupt Control Register 2 (ICR2)
ICR2 is a 16-bit register that sets the edge detection mode of the external interrupt input pins IRQ0
to IRQ3. ICR2 is, however, valid only when IRQ interrupt request detection mode is set to the
edge detection mode by the sense select bits of IRQ0 to IRQ 3 in Interrupt control register 1
(ICR1). If the IRQ interrupt request detection mode has been set to low level detection mode, the
setting of ICR2 is ignored.
Initial
Bit
Bit Name Value
R/W
Description
15
14
IRQ0ES1
IRQ0ES0
0
0
R/W
R/W
This bit sets the IRQ0 interrupt request edge detection
mode.
00: Interrupt request is detected on falling edge of IRQ0
input
01: Interrupt request is detected on rising edge of IRQ0
input
10: Interrupt request is detected on both of falling and
rising edge of IRQ0 input
11: Cannot be set
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6. Interrupt Controller (INTC)
Initial
Bit
Bit Name Value
R/W
Description
13
12
IRQ1ES1
IRQ1ES0
0
0
R/W
R/W
This bit sets the IRQ1 interrupt request edge detection
mode.
00: Interrupt request is detected on falling edge of IRQ1
input
01: Interrupt request is detected on rising edge of IRQ1
input
10: Interrupt request is detected on both of falling and
rising edge of IRQ1 input
11: Cannot be set
11
10
IRQ2ES1
IRQ2ES0
0
0
R/W
R/W
This bit sets the IRQ2 interrupt request edge detection
mode.
00: Interrupt request is detected on falling edge of IRQ2
input
01: Interrupt request is detected on rising edge of IRQ2
input
10: Interrupt request is detected on both of falling and
rising edge of IRQ2 input
11: Cannot be set
9
8
IRQ3ES1
IRQ3ES0
0
0
R/W
R/W
This bit sets the IRQ3 interrupt request edge detection
mode.
00: Interrupt request is detected on falling edge of IRQ3
input
01: Interrupt request is detected on rising edge of IRQ3
input
10: Interrupt request is detected on both of falling and
rising edge of IRQ3 input
11: Cannot be set
7 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
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6. Interrupt Controller (INTC)
6.3.3
IRQ Status Register (ISR)
ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input pins
IRQ0 to IRQ3. When IRQ interrupts are set to edge detection, held interrupt requests can be
withdrawn by writing 0 to IRQnF after reading IRQnF = 1.
Initial
Bit
Bit Name Value
R/W
Description
15 to 8
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
7
6
5
4
IRQ0F
IRQ1F
IRQ2F
IRQ3F
0
0
0
0
R/W
R/W
R/W
R/W
IRQ0 to IRQ3 Flags
These bits display the IRQ0 to IRQ3 interrupt request
status.
[Setting condition]
•
When interrupt source that is selected by ICR1 and
ICR2 has occurred.
[Clearing conditions]
•
•
When 0 is written after reading IRQnF = 1
When interrupt exception processing has been
executed at high level of IRQn input under the low
level detection mode.
•
When IRQn interrupt exception processing has
been executed under the edge detection mode of
falling edge, rising edge or both of falling and rising
edge.
3 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
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6. Interrupt Controller (INTC)
Interrupt Priority Registers A, D to I (IPRA, IPRD to IPRI)
6.3.4
Interrupt priority registers are seven 16-bit readable/writable registers that set priority levels from
0 to 15 for interrupts except NMI. For the correspondence between interrupt request sources and
IPR, refer to table 6.2 Interrupt Exception Processing Vectors and Priorities. Each of the
corresponding interrupt priority ranks are established by setting a value from H'0 to H'F in each of
the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0. Reserved bits that are not assigned should
be set H'0 (B'0000.)
Initial
Bit
Bit Name Value
R/W
Description
15
14
13
12
IPR15
IPR14
IPR13
IPR12
0
0
0
0
R/W
R/W
R/W
R/W
These bits set priority levels for the corresponding
interrupt source.
0000: Priority level 0 (lowest)
0001: Priority level 1
0010: Priority level 2
0011: Priority level 3
0100: Priority level 4
0101: Priority level 5
0110: Priority level 6
0111: Priority level 7
1000: Priority level 8
1001: Priority level 9
1010: Priority level 10
1011: Priority level 11
1100: Priority level 12
1101: Priority level 13
1110: Priority level 14
1111: Priority level 15 (highest)
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6. Interrupt Controller (INTC)
Initial
Bit
Bit Name Value
R/W
Description
11
10
9
IPR11
IPR10
IPR9
0
0
0
0
R/W
R/W
R/W
R/W
These bits set priority levels for the corresponding
interrupt source.
0000: Priority level 0 (lowest)
0001: Priority level 1
0010: Priority level 2
0011: Priority level 3
0100: Priority level 4
0101: Priority level 5
0110: Priority level 6
0111: Priority level 7
1000: Priority level 8
1001: Priority level 9
1010: Priority level 10
1011: Priority level 11
1100: Priority level 12
1101: Priority level 13
1110: Priority level 14
1111: Priority level 15 (highest)
8
IPR8
7
6
5
4
IPR7
IPR6
IPR5
IPR4
0
0
0
0
R/W
R/W
R/W
R/W
These bits set priority levels for the corresponding
interrupt source.
0000: Priority level 0 (lowest)
0001: Priority level 1
0010: Priority level 2
0011: Priority level 3
0100: Priority level 4
0101: Priority level 5
0110: Priority level 6
0111: Priority level 7
1000: Priority level 8
1001: Priority level 9
1010: Priority level 10
1011: Priority level 11
1100: Priority level 12
1101: Priority level 13
1110: Priority level 14
1111: Priority level 15 (highest)
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6. Interrupt Controller (INTC)
Initial
Bit
Bit Name Value
R/W
Description
3
2
1
0
IPR3
IPR2
IPR1
IPR0
0
0
0
0
R/W
R/W
R/W
R/W
These bits set priority levels for the corresponding
interrupt source.
0000: Priority level 0 (lowest)
0001: Priority level 1
0010: Priority level 2
0011: Priority level 3
0100: Priority level 4
0101: Priority level 5
0110: Priority level 6
0111: Priority level 7
1000: Priority level 8
1001: Priority level 9
1010: Priority level 10
1011: Priority level 11
1100: Priority level 12
1101: Priority level 13
1110: Priority level 14
1111: Priority level 15 (highest)
Note: Name in the tables above is represented by a general name. Name in the list of register is,
on the other hand, represented by a module name.
6.4
Interrupt Sources
6.4.1
External Interrupts
There are three types of interrupt sources: NMI, IRQ, and on-chip peripheral modules. Each
interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the highest).
Giving an interrupt a priority level of 0 masks it.
NMI Interrupts: The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin
is detected by edge. Use the NMI edge select bit (NMIE) in the interrupt control register 1 (ICR1)
to select either the rising or falling edge. NMI interrupt exception processing sets the interrupt
mask level bits (I3 to I0) in the status register (SR) to level 15.
IRQ3 to IRQ0 Interrupts: IRQ interrupts are requested by input from pins IRQ0 to IRQ3. Set
the IRQ sense select bits (IRQ0S to IRQ3S) of the interrupt control register 1 (ICR1) and IRQ
edge select bit (IRQ0ES[1:0] to IRQ3ES[1:0]) of the interrupt control register 2 (ICR2) to select
low level detection, falling edge detection, or rising edge detection for each pin. The priority level
can be set from 0 to 15 for each pin using the interrupt priority register A (IPRA).
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6. Interrupt Controller (INTC)
When IRQ interrupts are set to low level detection, an interrupt request signal is sent to the INTC
during the period the IRQ pin is low level. Interrupt request signals are not sent to the INTC when
the IRQ pin becomes high level. Interrupt request levels can be confirmed by reading the IRQ
flags (IRQ0F to IRQ3F) of the IRQ status register (ISR).
When IRQ interrupts are set to falling edge detection, interrupt request signals are sent to the
INTC upon detecting a change on the IRQ pin from high to low level. The results of detection for
IRQ interrupt request are maintained until the interrupt request is accepted. It is possible to
confirm that IRQ interrupt requests have been detected by reading the IRQ flags (IRQ0F to
IRQ3F) of the IRQ status register (ISR), and by writing a 0 after reading a 1, IRQ interrupt request
detection results can be withdrawn.
In IRQ interrupt exception processing, the interrupt mask bits (I3 to I0) of the status register (SR)
are set to the priority level value of the accepted IRQ interrupt. Figure 6.2 shows the block
diagram of this IRQ3 to IRQ0 interrupts.
IRQnS
IRQnES
ISR.IRQnF
Level
detection
IRQ pins
CPU interrupt
request
Edge
detection
S
R
Q
RESIRQn
(Acceptance of IRQn interrupt/writing 0 after reading IRQnF = 1)
Figure 6.2 Block Diagram of IRQ3 to IRQ0 Interrupts Control
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6. Interrupt Controller (INTC)
6.4.2
On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral
modules.
As a different interrupt vector is assigned to each interrupt source, the exception service routine
does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be
assigned to individual on-chip peripheral modules in interrupt priority registers A, D to I (IPRA,
IPRD to IPRI). On-chip peripheral module interrupt exception processing sets the interrupt mask
level bits (I3 to I0) in the status register (SR) to the priority level value of the on-chip peripheral
module interrupt that was accepted.
6.5
Interrupt Exception Processing Vectors Table
Table 6.2 lists interrupt sources and their vector numbers, vector table address offsets and interrupt
priorities.
Each interrupt source is allocated a different vector number and vector table address offset. Vector
table addresses are calculated from the vector numbers and address offsets. In interrupt exception
processing, the exception service routine start address is fetched from the vector table indicated by
the vector table address. For the details of calculation of vector table address, see table 5.4,
Calculating Exception Processing Vector Table Addresses in the section 5 Exception Processing.
IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and
15 for each pin or module by setting interrupt priority registers A, D to I (IPRA, IPRD to IPRI).
However, the smaller vector number has interrupt source, the higher priority ranking is assigned
among two or more interrupt sources specified by the same IPR, and the priority ranking cannot be
changed. A power-on reset assigns priority level 0 to IRQ interrupts and on-chip peripheral
module interrupts. If the same priority level is assigned to two or more interrupt sources and
interrupts from those sources occur simultaneously, they are processed by the default priority
order indicated in table 6.2.
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6. Interrupt Controller (INTC)
Table 6.2 Interrupt Exception Processing Vectors and Priorities
Interrupt
Source
Vector
No.
Vector Table
Starting Address IPR
Default
Priority
Name
External pin
NMI
11
H'0000002C
H'00000030
H'00000038
H'0000003C
H'00000100
⎯
⎯
⎯
⎯
High
⎯
Reserved by system 12
Reserved by system 14
Reserved by system 15
⎯
⎯
Interrupts
IRQ0
64
IPRA15 to
IPRA12
IRQ1
IRQ2
IRQ3
65
66
67
H'00000104
H'00000108
H'0000010C
H'00000110
H'00000114
H'00000118
H'0000011C
H'00000120
H'00000130
H'00000140
H'00000150
H'00000160
H'00000164
H'00000168
H'0000016C
H'00000170
H'00000180
H'00000184
H'00000190
H'00000194
IPRA11 to IPRA8
IPRA7 to IPRA4
IPRA3 to IPRA0
Reserved by system 68
Reserved by system 69
Reserved by system 70
Reserved by system 71
Reserved by system 72
Reserved by system 76
Reserved by system 80
Reserved by system 84
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
MTU channel 0 TGIA_0
TGIB_0
88
IPRD15 to
IPRD12
89
TGIC_0
90
TGID_0
91
TCIV_0
92
IPRD11 to IPRD8
IPRD7 to IPRD4
MTU channel 1 TGIA_1
TGIB_1
96
97
TCIV_1
100
101
IPRD3 to IPRD0
TCIU_1
Low
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6. Interrupt Controller (INTC)
Interrupt
Source
Vector
No.
Vector Table
Starting Address IPR
Default
Priority
Name
MTU channel 2 TGIA_2
TGIB_2
104
105
108
109
112
113
114
115
116
120
121
122
123
124
H'000001A0
H'000001A4
H'000001B0
H'000001B4
H'000001C0
H'000001C4
H'000001C8
H'000001CC
H'000001D0
H'000001E0
H'000001E4
H'000001E8
H'000001EC
H'000001F0
IPRE15 to
IPRE12
High
TCIV_2
IPRE11 to IPRE8
TCIU_2
MTU channel 3 TGIA_3
TGIB_3
IPRE7 to IPRE4
TGIC_3
TGID_3
TCIV_3
IPRE3 to IPRE0
MTU channel 4 TGIA_4
TGIB_4
IPRF15 to
IPRF12
TGIC_4
TGID_4
TCIV_4
IPRF11 to IPRF8
⎯
Reserved by system 128 to
135
H'00000200 to
H'0000021C
⎯
A/D
ADI0
ADI1
136
137
H'00000220
H'00000224
H'00000230
H'00000240
H'00000250
H'00000260
IPRG15 to
IPRG12
⎯
Reserved by system 140
⎯
CMT
CMI0
CMI1
ITI
144
148
152
IPRG7 to IPRG4
IPRG3 to IPRG0
Watchdog
timer
IPRH15 to
IPRH12
⎯
Reserved by system 153
MTUPOE 156
H'00000264
H'00000270
⎯
I/O (MTU)
IPRH11 to IPRH8
⎯
Reserved by system 160 to
167
H'00000290 to
H'0000029C
⎯
SCI channel 2 ERI_2
168
169
170
171
H'000002A0
H'000002A4
H'000002A8
H'000002AC
IPRI15 to IPRI12
RXI_2
TXI_2
TEI_2
Low
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6. Interrupt Controller (INTC)
Interrupt
Source
Vector
No.
Vector Table
Starting Address IPR
Default
Priority
Name
SCI channel 3 ERI_3
172
173
174
175
H'000002B0
H'000002B4
H'000002B8
H'000002BC
H'000002C0
H'000002C4
H'000002C8
H'000002CC
H'000002D0
H'000002D4
H'000002E0
IPRI11 to IPRI8 High
RXI_3
TXI_3
TEI_3
⎯
⎯
Reserved by system 176
Reserved by system 177
⎯
⎯
Reserved by system 178
Reserved by system 179
Reserved by system 180
Reserved by system 181
Reserved by system 184
⎯
⎯
⎯
⎯
Reserved by system 188 to
196
H'000002F0 to
H'00000310
⎯
⎯
⎯
Reserved by system 200
Reserved by system 204
Reserved by system 208
Reserved by system 209
Reserved by system 210
Reserved by system 211
Reserved by system 212
H'00000320
H'00000330
H'00000340
H'00000344
H'00000348
H'0000034C
⎯
⎯
⎯
⎯
H'00000350 to
H'000003DC
⎯
Low
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6. Interrupt Controller (INTC)
6.6
Operation
6.6.1
Interrupt Sequence
The sequence of interrupt operations is explained below.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest priority interrupt in the interrupt requests sent,
according to the priority levels set in interrupt priority registers A, D to I (IPRA, IPRD to
IPRI). Interrupts that have lower-priority than that of the selected interrupt are ignored.* If
interrupts that have the same priority level or interrupts within a same module occur
simultaneously, the interrupt with the highest priority is selected according to the default
priority order indicated in table 6.2.
3. The interrupt controller compares the priority level of the selected interrupt request with the
interrupt mask bits (I3 to I0) in the CPU's status register (SR). If the request priority level is
equal to or less than the level set in I3 to I0, the request is ignored. If the request priority level
is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends
an interrupt request signal to the CPU.
4. When the interrupt controller accepts an interrupt, a low level is output from the IRQOUT pin.
5. The CPU detects the interrupt request sent from the interrupt controller when CPU decodes the
instruction to be executed. Instead of executing the decoded instruction, the CPU starts
interrupt exception processing (figure 6.5).
6. SR and PC are saved onto the stack.
7. The priority level of the accepted interrupt is copied to the interrupt mask level bits (I3 to I0) in
the status register (SR).
8. When the accepted interrupt is sensed by level or is from an on-chip peripheral module, a high
level is output from the IRQOUT pin. When the accepted interrupt is sensed by edge, a high
level is output from the IRQOUT pin at the moment when the CPU starts interrupt exception
processing instead of instruction execution as noted in (5) above. However, if the interrupt
controller accepts an interrupt with a higher priority than the interrupt just to be accepting, the
IRQOUT pin holds low level.
9. The CPU reads the start address of the exception service routine from the exception vector
table for the accepted interrupt, jumps to that address, and starts executing the program. This
jump is not a delay branch.
Note: * Interrupt requests that are designated as edge-detect type are held pending until the
interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing
the IRQ status register (ISR). Interrupts held pending due to edge detection are cleared
by a power-on reset or a manual reset.
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6. Interrupt Controller (INTC)
Program
execution state
No
Interrupt?
Yes
No
NMI?
Yes
No
Level 15
interrupt?
Yes
No
Level 14
interrupt?
Yes
I3 to I0 ≤
level 14?
Yes
No
Level 1
No
interrupt?
Yes
I3 to I0 ≤
level 13?
Yes
No
Yes
I3 to I0 =
level 0?
*1
No
IRQOUT = low
Save SR to stack
Save PC to stack
Copy accept-interrupt
level to I3 to I0
*2
IRQOUT = high
Read exception
vector table
Branch to exception
service routine
Notes: I3 to I0 are Interrupt mask bits of status register (SR) in the CPU
1. IRQOUT is the same signal as interrupt request signal to the CPU (see figure 6.1).
Therefore, IRQOUT is output when the request priority level is higher than the level in bits I3–I0 of SR.
2. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when
the CPU starts interrupt exception processing instead of instruction execution (namely, before saving SR to stack).
However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepted
and has output an interrupt request to the CPU, the IRQOUT pin holds low level.
Figure 6.3 Interrupt Sequence Flowchart
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6. Interrupt Controller (INTC)
6.6.2
Stack after Interrupt Exception Processing
Figure 6.4 shows the stack after interrupt exception processing.
Address
PC*1
SR
SP*2
32 bits
32 bits
4n–8
4n–4
4n
Notes: 1. PC: Start address of the next instruction (return destination instruction) after the executing
instruction
2. Always make sure that SP is a multiple of 4
Figure 6.4 Stack after Interrupt Exception Processing
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6. Interrupt Controller (INTC)
6.7
Interrupt Response Time
Table 6.3 lists the interrupt response time, which is the time from the occurrence of an interrupt
request until the interrupt exception processing starts and fetching of the first instruction of the
interrupt service routine begins. Figure 6.5 shows an example of the pipeline operation when an
IRQ interrupt is accepted.
Table 6.3 Interrupt Response Time
Number of States
NMI, Peripheral
Item
Module
0 or 1
2
IRQ
Remarks
Idle cycle
1
Interrupt priority judgment
and comparison with SR
mask bits
3
Wait for completion of
sequence currently being
executed by CPU
X (≥ 0)
X (≥ 0)
The longest sequence is for
interrupt or address-error
exception processing (X = 4
+ m1 + m2 + m3 + m4). If an
interrupt-masking instruction
follows, however, the time
may be even longer.
Time from start of interrupt 5 + m1 + m2 + m3 5 + m1 + m2 + m3 Performs the saving PC and
exception processing until
fetch of first instruction of
exception service routine
starts
SR, and vector address
fetch.
Interrupt
response
time
Total: (7 or 8) + m1 +
m2 + m3 + X
9 + m1 + m2 +
m3 + X
Minimum: 10
12
0.25 to 0.28 μs
0.48 μs*
Maximum: 12 + 2 (m1 + m2
+ m3) + m4
13 + 2 (m1 + m2
+ m3) + m4
Note:
*
0.48 μs at 40 MHz is the value in the case that m1 = m2 = m3 = m4 = 1.
m1 to m4 are the number of states needed for the following memory accesses.
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch first instruction of interrupt service routine
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6. Interrupt Controller (INTC)
Interrupt acceptance
5 + m1 + m2 + m3
3
m1 m2
1
m3
1
1
3
IRQ
Instruction (instruction
replaced by interrupt
exception processing)
F
D
F
E
E
M
M
E
M
E
E
F
Overrun fetch
Interrupt service routine
start instruction
D
E
Legend:
F: Instruction fetch (instruction fetched from memory where program is stored).
D: Instruction decoding (fetched instruction is decoded).
E: Instruction execution (data operation and address calculation is performed according to the results
of decoding).
M: Memory access (data in memory is accessed).
Figure 6.5 Example of the Pipeline Operation when an IRQ Interrupt is Accepted
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6. Interrupt Controller (INTC)
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7. Bus State Controller (BSC)
Section 7 Bus State Controller (BSC)
The bus state controller (BSC) controls accesses to the on-chip ROM, RAM, and peripheral
module registers.
7.1
Features
The BSC has the following features:
•
On-chip ROM and RAM interfaces
⎯ On-chip ROM and RAM access of 32 bits in 1 state
Accesses to on-chip peripheral module registers
•
7.2
Input/output Pin
There are no pins corresponding to this function.
7.3
Register
The BSC has the following register. For details on these register addresses and register states in
each processing states, refer to section 18, List of Registers.
•
Bus control register 1 (BCR1)
BSC1000A_010020030200
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7. Bus State Controller (BSC)
7.4
Address Map
Table 7.1 shows the address map.
Table 7.1 Address Map
On-chip ROM enabled mode
Address
Space
Memory
Size
Bus Width
32 bits
H'0000 0000 to H'0000 7FFF
H'0000 8000 to H'0001 FFFF
H'0002 0000 to H'0003 FFFF
On-chip ROM
On-chip ROM
32 kbytes
Reserved
Reserved
Reserved
16 kbytes
32 bits
32 bits
H'0004 0000 to H'FFFF 7FFF Reserved
Reserved
H'FFFF 8000 to H'FFFF BFFF On-chip peripheral On-chip peripheral
8, 16 bits
module
H'FFFF C000 to H'FFFF CFFF Reserved
H'FFFF D000 to H'FFFF DFFF On-chip RAM
H'FFFF E000 to H'FFFF F7FF
module
Reserved
On-chip RAM
Reserved
Reserved
2 kbytes
32 bits
32 bits
32 bits
H'FFFF F800 to H'FFFF FFFF
Note: Reserved area should not be accessed, or operation cannot be guaranteed.
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7. Bus State Controller (BSC)
7.5
Register Description
7.5.1
Bus Control Register 1 (BCR1)
BCR1 is a 16-bit readable/writable register that enables access to the MTU control registers.
Initial
Bit
Bit Name
Value
R/W
Description
15
⎯
0
R
Reserved
These bits are always read as 0 and should always be
written to 0.
14
13
⎯
1
1
R
Reserved
These bits are always read as 1 and should always be
written to 1.
MTURWE
R/W
MTU Read/Write Enable
This bit enables MTU control register access. For
details, refer to MTU section.
0: MTU control register access is disabled
1: MTU control register access is enabled
12 to 8 ⎯
All 0
All 0
All 1
R
R
R
Reserved
These bits are always read as 0 and the write value
should always be 0.
7 to 4
3 to 0
⎯
⎯
Reserved
These bits are always read as 0 and the write value
should always be 0.
Reserved
These bits are always read as 1 and the write value
should always be 1.
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7. Bus State Controller (BSC)
7.6
On-chip Peripheral I/O Register Access
On-chip peripheral I/O registers are accessed from the bus state controller, as shown in table 7.2.
Table 7.2 On-chip Peripheral I/O Register Access
On-chip Peripheral
Module
SCI
MTU,
POE
INTC
PFC,
PORT
CMT
A/D
WDT
Connected bus width 8 bits
Access cycle
16 bits
16 bits
16 bits
16 bits
8 bits
16 bits
2 cycles*1 2 cycles*1 2 cycles*2 2 cycles*2 2 cycles*1 3 cycles*1 3 cycles*2
Notes: 1. In terms of the peripheral clock value
2. In terms of the system clock value
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8. Multi-Function Timer Pulse Unit (MTU)
Section 8 Multi-Function Timer Pulse Unit (MTU)
This LSI has an on-chip multi-function timer pulse unit (MTU) that comprises five 16-bit timer
channels.
The block diagram is shown in figure 8.1.
8.1
Features
•
•
•
Maximum 16-pulse input/output
Selection of 8 counter input clocks for each channel
The following operations can be set for each channel:
⎯ Waveform output at compare match
⎯ Input capture function
⎯ Counter clear operation
Multiple timer counters (TCNT) can be written to simultaneously
Simultaneous clearing by compare match and input capture is possible
Register simultaneous input/output is possible by synchronous counter operation
⎯ A maximum 12-phase PWM output is possible in combination with synchronous operation
Buffer operation settable for channels 0, 3, and 4
Phase counting mode settable independently for each of channels 1 and 2
Cascade connection operation
•
•
•
•
•
•
•
•
•
Fast access via internal 16-bit bus
23 interrupt sources
Automatic transfer of register data
A/D converter conversion start trigger can be generated
Module standby mode can be set
Positive and negative 3-phase waveforms (6-phase waveforms in total) can be output in
complementary or reset synchronous PWM mode by combining channels 3 and 4.
•
AC synchronous motor (brushless DC motor) can be driven in complementary or reset
synchronous PWM mode by combining channels 0, 3, and 4. Chopping or level output can be
selected as drive waveform output.
TIMMTU0A_010020030200
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.1 MTU Functions
Item
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Count clock
Pφ/1
Pφ/1
Pφ/1
Pφ/1
Pφ/1
Pφ/4
Pφ/4
Pφ/4
Pφ/4
Pφ/4
Pφ/16
Pφ/64
TCLKA
TCLKB
TCLKC
TCLKD
Pφ/16
Pφ/64
Pφ/256
TCLKA
TCLKB
Pφ/16
Pφ/64
Pφ/1024
TCLKA
TCLKB
TCLKC
Pφ/16
Pφ/64
Pφ/256
Pφ/1024
TCLKA
TCLKB
Pφ/16
Pφ/64
Pφ/256
Pφ/1024
TCLKA
TCLKB
General registers
TGRA_0
TGRB_0
TGRA_1
TGRB_1
TGRA_2
TGRB_2
TGRA_3
TGRB_3
TGRA_4
TGRB_4
General registers/
buffer registers
TGRC_0
TGRD_0
⎯
⎯
TGRC_3
TGRD_3
TGRC_4
TGRD_4
I/O pins
TIOC0A
TIOC0B
TIOC0C
TIOC0D
TIOC1A
TIOC1B
TIOC2A
TIOC2B
TIOC3A
TIOC3B
TIOC3C
TIOC3D
TIOC4A
TIOC4B
TIOC4C
TIOC4D
Counter clear
function
TGR
compare
match or
TGR
compare
match or
TGR
compare
match or
TGR
compare
match or
TGR
compare
match or
input capture input capture input capture input capture input capture
Compare 0 output
match
output
1 output
Toggle
output
Input capture
function
Synchronous
operation
PWM mode 1
PWM mode 2
⎯
⎯
Complementary PWM
mode
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Reset synchronous
PWM mode
AC synchronous motor
drive mode
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8. Multi-Function Timer Pulse Unit (MTU)
Item
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Phase counting
mode
⎯
⎯
⎯
Buffer operation
⎯
⎯
A/D converter start
trigger
TGRA_0
compare
match or
input
TGRA_1
compare
match or
input
TGRA_2
compare
match or
input
TGRA_3
compare
match or
input
TGRA_4
compare
match or
input
capture
capture
capture
capture
capture
Interrupt sources
5 sources
4 sources
4 sources
5 sources
5 sources
• Compare
match or
input
• Compare
match or
input
• Compare
match or
input
• Compare
match or
input
• Compare
match or
input
capture 0A
• Compare
match or
input
capture 1A
• Compare
match or
input
capture 2A
• Compare
match or
input
capture 3A
• Compare
match or
input
capture 4A
• Compare
match or
input
capture 0B
• Compare
match or
input
capture 1B
• Overflow
• Underflow • Underflow
capture 2B
• Overflow
capture 3B
• Compare
match or
input
capture 4B
• Compare
match or
input
capture 0C
• Compare
match or
input
capture 3C
• Compare
match or
input
capture 4C
• Compare
match or
input
capture 0D
• Overflow
capture 3D
• Overflow
capture 4D
• Underflow/
Overflow
Legend:
: Possible
⎯ : Not possible
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8. Multi-Function Timer Pulse Unit (MTU)
Interrupt request signals
Channel 3: TGI3A
TGI3B
Input/output pins
TGI3C
TGI3D
TCI3V
Channel 3: TIOC3A
TIOC3B
TIOC3C
TIOC3D
Channel 4: TIOC4A
TIOC4B
Channel 4: TGI4A
TGI4B
TGI4C
TGI4D
TCI4V
TIOC4C
TIOC4D
Clock input
Internal clock:
Pφ/1
Pφ/4
Internal data bus
Pφ/16
Pφ/64
Pφ/256
Pφ/1024
External clock: TCLKA
A/D converter conversion
start signal
TCLKB
TCLKC
TCLKD
Interrupt request signals
Channel 0: TGI0A
TGI0B
Input/output pins
Channel 0: TIOC0A
TIOC0B
TIOC0C
TIOC0D
Channel 1: TIOC1A
TIOC1B
TGI0C
TGI0D
TCI0V
Channel 1: TGI1A
TGI1B
TCI1V
Channel 2: TIOC2A
TIOC2B
TCI1U
Channel 2: TGI2A
TGI2B
TCI2V
TCI2U
Legend:
TSTR:
TSYR:
TCR:
Timer start register
Timer synchro register
Timer control register
Timer mode register
TIER:
TSR:
TCNT:
Timer interrupt enable register
Timer status register
Timer counter
TMDR:
TGR (A, B, C, D): Timer general registers (A, B, C, D)
TIOR (H, L): Timer I/O control registers (H, L)
Figure 8.1 Block Diagram of MTU
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8. Multi-Function Timer Pulse Unit (MTU)
8.2
Input/Output Pins
Table 8.2 Pin configuration
Channel Symbol I/O Function
Input External clock A input pin
All
TCLKA
TCLKB
TCLKC
TCLKD
(Channel 1 phase counting mode A phase input)
Input External clock B input pin
(Channel 1 phase counting mode B phase input)
Input External clock C input pin
(Channel 2 phase counting mode A phase input)
Input External clock D input pin
(Channel 2 phase counting mode B phase input)
0
TIOC0A I/O
TIOC0B I/O
TIOC0C I/O
TIOC0D I/O
TIOC1A I/O
TIOC1B I/O
TIOC2A I/O
TIOC2B I/O
TIOC3A I/O
TIOC3B I/O
TIOC3C I/O
TIOC3D I/O
TIOC4A I/O
TIOC4B I/O
TIOC4C I/O
TIOC4D I/O
TGRA_0 input capture input/output compare output/PWM output pin
TGRB_0 input capture input/output compare output/PWM output pin
TGRC_0 input capture input/output compare output/PWM output pin
TGRD_0 input capture input/output compare output/PWM output pin
TGRA_1 input capture input/output compare output/PWM output pin
TGRB_1 input capture input/output compare output/PWM output pin
TGRA_2 input capture input/output compare output/PWM output pin
TGRB_2 input capture input/output compare output/PWM output pin
TGRA_3 input capture input/output compare output/PWM output pin
TGRB_3 input capture input/output compare output/PWM output pin
TGRC_3 input capture input/output compare output/PWM output pin
TGRD_3 input capture input/output compare output/PWM output pin
TGRA_4 input capture input/output compare output/PWM output pin
TGRB_4 input capture input/output compare output/PWM output pin
TGRC_4 input capture input/output compare output/PWM output pin
TGRD_4 input capture input/output compare output/PWM output pin
1
2
3
4
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8. Multi-Function Timer Pulse Unit (MTU)
8.3
Register Descriptions
The MTU has the following registers. For details on register addresses and register states during
each process, refer to section 18, List of Registers. To distinguish registers in each channel, an
underscore and the channel number are added as a suffix to the register name; TCR for channel 0
is expressed as TCR_0.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Timer control register_0 (TCR_0)
Timer mode register_0 (TMDR_0)
Timer I/O control register H_0 (TIORH_0)
Timer I/O control register L_0 (TIORL_0)
Timer interrupt enable register_0 (TIER_0)
Timer status register_0 (TSR_0)
Timer counter_0 (TCNT_0)
Timer general register A_0 (TGRA_0)
Timer general register B_0 (TGRB_0)
Timer general register C_0 (TGRC_0)
Timer general register D_0 (TGRD_0)
Timer control register_1 (TCR_1)
Timer mode register_1 (TMDR_1)
Timer I/O control register _1 (TIOR_1)
Timer interrupt enable register_1 (TIER_1)
Timer status register_1 (TSR_1)
Timer counter_1 (TCNT_1)
Timer general register A_1 (TGRA_1)
Timer general register B_1 (TGRB_1)
Timer control register_2 (TCR_2)
Timer mode register_2 (TMDR_2)
Timer I/O control register_2 (TIOR_2)
Timer interrupt enable register_2 (TIER_2)
Timer status register_2 (TSR_2)
Timer counter_2 (TCNT_2)
Timer general register A_2 (TGRA_2)
Timer general register B_2 (TGRB_2)
Timer control register_3 (TCR_3)
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8. Multi-Function Timer Pulse Unit (MTU)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Timer mode register_3 (TMDR_3)
Timer I/O control register H_3 (TIORH_3)
Timer I/O control register L_3 (TIORL_3)
Timer interrupt enable register_3 (TIER_3)
Timer status register_3 (TSR_3)
Timer counter_3 (TCNT_3)
Timer general register A_3 (TGRA_3)
Timer general register B_3 (TGRB_3)
Timer general register C_3 (TGRC_3)
Timer general register D_3 (TGRD_3)
Timer control register_4 (TCR_4)
Timer mode register_4 (TMDR_4)
Timer I/O control register H_4 (TIORH_4)
Timer I/O control register L_4 (TIORL_4)
Timer interrupt enable register_4 (TIER_4)
Timer status register_4 (TSR_4)
Timer counter_4 (TCNT_4)
Timer general register A_4 (TGRA_4)
Timer general register B_4 (TGRB_4)
Timer general register C_4 (TGRC_4)
Timer general register D_4 (TGRD_4)
Common Registers
•
•
Timer start register (TSTR)
Timer synchro register (TSYR)
Common Registers for timers 3 and 4
•
•
•
•
•
•
•
Timer output master enable register (TOER)
Timer output control enable register (TOCR)
Timer gate control register (TGCR)
Timer cycle data register (TCDR)
Timer dead time data register (TDDR)
Timer subcounter (TCNTS)
Timer cycle buffer register (TCBR)
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8. Multi-Function Timer Pulse Unit (MTU)
8.3.1 Timer Control Register (TCR)
The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each
channel. The MTU has a total of five TCR registers, one for each channel (channel 0 to 4). TCR
register settings should be conducted only when TCNT operation is stopped.
Initial
Bit
Bit Name value
R/W
Description
7
6
5
CCLR2
CCLR1
CCLR0
0
0
0
R/W
R/W
R/W
Counter Clear 0 to 2
These bits select the TCNT counter clearing source. See
tables 8.3 and 8.4 for details.
4
3
CKEG1
CKEG0
0
0
R/W
R/W
Clock Edge 0 and 1
These bits select the input clock edge. When the input clock
is counted using both edges, the input clock period is
halved (e.g. Pφ /4 both edges = φ /2 rising edge). If phase
counting mode is used on channels 1 and 2, this setting is
ignored and the phase counting mode setting has priority.
Internal clock edge selection is valid when the input clock is
Pφ /4 or slower. When Pφ /1, or the overflow/underflow of
another channel is selected for the input clock, although
values can be written, counter operation compiles with the
initial value.
00: Count at rising edge
01: Count at falling edge
1X: Count at both edges
Legend:
X: Don't care
2
1
0
TPSC2
TPSC1
TPSC0
0
0
0
R/W
R/W
R/W
Time Prescaler 0 to 2
These bits select the TCNT counter clock. The clock source
can be selected independently for each channel. See tables
8.5 to 8.8 for details.
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.3 CCLR0 to CCLR2 (channels 0, 3, and 4)
Bit 7
Bit 6
Bit 5
Channel CCLR2
CCLR1
CCLR0
Description
0, 3, 4
0
0
0
1
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
1
0
1
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*1
1
0
1
0
1
TCNT clearing disabled
TCNT cleared by TGRC compare match/input
capture*2
0
1
TCNT cleared by TGRD compare match/input
capture*2
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*1
Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.
Table 8.4 CCLR0 to CCLR2 (channels 1 and 2)
Bit 7
Bit 6
Bit 5
CCLR0
Channel Reserved*2 CCLR1
Description
1, 2
0
0
1
0
1
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
0
1
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*1
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
2. Bit 7 is reserved in channels 1 and 2. It is always read as 0.
Writing is ignored.
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.5 TPSC0 to TPSC2 (channel 0)
Bit 2
Bit 1
Bit 0
Channel TPSC2
TPSC1
TPSC0
Description
0
0
0
1
0
1
0
1
0
1
0
1
0
1
Internal clock: counts on Pφ/1
Internal clock: counts on Pφ/4
Internal clock: counts on Pφ/16
Internal clock: counts on Pφ/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
External clock: counts on TCLKC pin input
External clock: counts on TCLKD pin input
1
Table 8.6 TPSC0 to TPSC2 (channel 1)
Bit 2
Bit 1
Bit 0
Channel TPSC2
TPSC1
TPSC0
Description
1
0
0
1
0
1
0
1
0
1
0
1
0
1
Internal clock: counts on Pφ/1
Internal clock: counts on Pφ/4
Internal clock: counts on Pφ/16
Internal clock: counts on Pφ/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
Internal clock: counts on Pφ/256
Counts on TCNT_2 overflow/underflow
1
Note: This setting is ignored when channel 1 is in phase counting mode.
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.7 TPSC0 to TPSC2 (channel 2)
Bit 2
Bit 1
Bit 0
Channel TPSC2
TPSC1
TPSC0
Description
2
0
0
1
0
1
0
1
0
1
0
1
0
1
Internal clock: counts on Pφ/1
Internal clock: counts on Pφ/4
Internal clock: counts on Pφ/16
Internal clock: counts on Pφ/64
1
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
External clock: counts on TCLKC pin input
Internal clock: counts on Pφ/1024
Note: This setting is ignored when channel 2 is in phase counting mode.
Table 8.8 TPSC0 to TPSC2 (channels 3 and 4)
Bit 2
Bit 1
Bit 0
Channel TPSC2
TPSC1
TPSC0
Description
3, 4
0
0
1
0
1
0
1
0
1
0
1
0
1
Internal clock: counts on Pφ/1
Internal clock: counts on Pφ/4
Internal clock: counts on Pφ/16
Internal clock: counts on Pφ/64
Internal clock: counts on Pφ/256
Internal clock: counts on Pφ/1024
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
1
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8. Multi-Function Timer Pulse Unit (MTU)
8.3.2 Timer Mode Register (TMDR)
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of
each channel. The MTU has five TMDR registers, one for each channel. TMDR register settings
should be changed only when TCNT operation is stopped.
Initial
Bit
Bit Name value
R/W
Description
7, 6
⎯
All 1
⎯
Reserved
These bits are always read as 1, and should only be
written with 1.
5
BFB
0
R/W
Buffer Operation B
Specifies whether TGRB is to operate in the normal
way, or TGRB and TGRD are to be used together for
buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare is not
generated.
In channels 1 and 2, which have no TGRD, bit 5 is
reserved. It is always read as 0, and the write value
should always be 0.
0: TGRB and TGRD operate normally
1: TGRB and TGRD used together for buffer operation
4
BFA
0
R/W
Buffer Operation A
Specifies whether TGRA is to operate in the normal
way, or TGRA and TGRC are to be used together for
buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not
generated.
In channels 1 and 2, which have no TGRC, bit 4 is
reserved. It is always read as 0, and the write value
should always be 0.
0: TGRA and TGRD operate normally
1: TGRA and TGRC used together for buffer operation
3
2
1
0
MD3
MD2
MD1
MD0
0
0
0
0
R/W
R/W
R/W
R/W
Modes 0 to 3
These bits are used to set the timer operating mode.
See table 8.9 for details.
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.9 MD0 to MD3
Bit 3
MD3
Bit 2
MD2
Bit 1
MD1
Bit 0
MD0
Description
0
0
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
X
0
1
0
1
Normal operation
Reserved (do not set)
PWM mode 1
PWM mode 2*1
Phase counting mode 1*2
Phase counting mode 2*2
Phase counting mode 3*2
Phase counting mode 4*2
Reset synchronous PWM mode*3
1
1
0
1
Reserved (do not set)
1
0
Reserved (do not set)
Reserved (do not set)
Complementary PWM mode 1 (transmit at peak)*3
Complementary PWM mode 2 (transmit at valley)*3
Complementary PWM mode 2 (transmit at peak and valley)*3
1
Legend:
X: Don't care
Notes: 1. PWM mode 2 can not be set for channels 3, 4.
2. Phase counting mode can not be set for channels 0, 3, and 4.
3. Reset synchronous PWM mode, complementary PWM mode can only be set for
channel 3. When channel 3 is set to reset synchronous PWM mode or complementary
PWM mode, the channel 4 settings become ineffective and automatically conform to the
channel 3 settings. However, do not set channel 4 to reset synchronous PWM mode or
complementary PWM mode. Reset synchronous PWM mode and complementary PWM
mode can not be set for channels 0, 1, and 2.
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8. Multi-Function Timer Pulse Unit (MTU)
8.3.3
Timer I/O Control Register (TIOR)
The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU
has eight TIOR registers, two each for channels 0, 3, and 4, and one each for channels 1 and 2.
Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is
valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM
mode 2, the output at the point at which the counter is cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4
Bit
Bit Name Initial value R/W
Description
7
6
5
4
IOB3
IOB2
IOB1
IOB0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control B0 to B3
Specify the function of TGRB.
See the following tables.
TIORH_0: Table 8.10
TIOR_1: Table 8.14
TIOR_2: Table 8.16
TIORH_3: Table 8.18
TIORH_4: Table 8.22
3
2
1
0
IOA3
IOA2
IOA1
IOA0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control A0 to A3
Specify the function of TGRA.
See the following tables.
TIORH_0: Table 8.11
TIOR_1: Table 8.15
TIOR_2: Table 8.17
TIORH_3: Table 8.19
TIORH_4: Table 8.23
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8. Multi-Function Timer Pulse Unit (MTU)
TIORL_0, TIORL_3, TIORL_4
Bit
Bit Name Initial value R/W
Description
7
6
5
4
IOD3
IOD2
IOD1
IOD0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control D0 to D3
Specify the function of TGRD.
When the TGRD is used as a buffer register of the
TGRB, this setting is invalid and input capture/output
compare is not generated.
See the following tables.
TIORL_0: Table 8.12
TIORL_3: Table 8.20
TIORL_4: Table 8.24
3
2
1
0
IOC3
IOC2
IOC1
IOC0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control C0 to C3
Specify the function of TGRC.
When the TGRC is used as a buffer register of the
TGRA, this setting is invalid and input capture/output
compare is not generated.
See the following tables.
TIORL_0: Table 8.13
TIORL_3: Table 8.21
TIORL_4: Table 8.25
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.10 TIORH_0 (channel 0)
Description
Bit 7
Bit 6
Bit 5
Bit 4
TGRB_0
IOB3 IOB2 IOB1 IOB0 Function
TIOC0B Pin Function
0
0
0
0
1
Output
compare
register
Output disabled
Initial output is 0
0 output at compare match
1
0
1
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
1
0
1
0
1
Output disabled
Initial output is 1
0 output at compare match
0
1
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
1
0
1
0
0
1
Input
capture
register
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1
X
X
X
Capture input source is channel 1/count clock
Input capture at TCNT_1 count- up/count-down
Legend:
X: Don't care
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.11 TIORH_0 (channel 0)
Description
Bit 3
Bit 2
Bit 1
Bit 0
TGRA_0
IOA3 IOA2 IOA1 IOA0 Function
TIOC0A Pin Function
0
0
0
0
1
Output
compare
register
Output disabled
Initial output is 0
0 output at compare match
1
0
1
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
1
0
1
0
1
Output disabled
Initial output is 1
0 output at compare match
0
1
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
1
0
1
0
0
1
Input
capture
register
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1
X
X
X
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
Legend:
X: Don't care
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.12 TIORL_0 (channel 0)
Description
Bit 7
Bit 6
Bit 5
Bit 4
TGRD_0
IOD3 IOD2 IOD1 IOD0 Function
TIOC0D Pin Function
0
0
0
0
1
Output
compare
register*
Output disabled
Initial output is 0
0 output at compare match
1
0
1
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
1
0
1
0
1
Output disabled
Initial output is 1
0 output at compare match
0
1
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
1
0
1
0
0
1
Input
capture
register*
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1
X
X
X
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
Legend:
X: Don't care
Note:
*
When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.13 TIORL_0 (channel 0)
Description
Bit 3
Bit 2
Bit 1
Bit 0
TGRC_0
IOC3 IOC2 IOC1 IOC0 Function
TIOC0C Pin Function
0
0
0
0
1
Output
compare
register*
Output disable
Initial output is 0
0 output at compare match
1
0
1
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
1
0
1
0
1
Output disabled
Initial output is 1
0 output at compare match
0
1
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
1
0
1
0
0
1
Input
capture
register*
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1
X
X
X
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
Legend:
X: Don't care
Note:
*
When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.14 TIOR_1 (channel 1)
Description
Bit 7
IOB3 IOB2
Bit 6
Bit 5
IOB1
Bit 4
IOB0
TGRB_1
Function
TIOC1B Pin Function
0
0
0
0
1
Output
compare
register
Output disabled
Initial output is 0
0 output at compare match
1
0
1
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
1
0
1
0
1
Output disabled
Initial output is 1
0 output at compare match
0
1
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
1
0
1
0
0
1
X
X
Input
capture
register
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1
X
Input capture at generation of TGRC_0 compare
match/input capture
Legend:
X: Don't care
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.15 TIOR_1 (channel 1)
Description
Bit 3
IOA3 IOA2
Bit 2
Bit 1
IOA1
Bit 0
IOA0
TGRA_1
Function
TIOC1A Pin Function
0
0
0
0
1
Output
compare
register
Output disabled
Initial output is 0
0 output at compare match
1
0
1
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
1
0
1
0
1
Output disabled
Initial output is 1
0 output at compare match
0
1
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
1
0
1
0
0
1
X
X
Input
capture
register
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1
X
Input capture at generation of channel 0/TGRA_0
compare match/input capture
Legend:
X: Don't care
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.16 TIOR_2 (channel 2)
Description
Bit 7
Bit 6
Bit 5
Bit 4
TGRB_2
IOB3 IOB2 IOB1 IOB0 Function
TIOC2B Pin Function
0
0
1
X
0
0
1
Output
compare
register
Output disabled
Initial output is 0
0 output at compare match
1
0
1
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
0
1
0
1
Output disabled
Initial output is 1
0 output at compare match
0
1
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
1
0
1
0
1
X
Input
capture
register
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Legend:
X: Don't care
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.17 TIOR_2 (channel 2)
Description
Bit 3
Bit 2
Bit 1
Bit 0
TGRA_2
IOA3 IOA2 IOA1 IOA0 Function
TIOC2A Pin Function
0
0
1
X
0
0
1
Output
compare
register
Output disabled
Initial output is 0
0 output at compare match
1
0
1
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
0
1
0
1
Output disabled
Initial output is 1
0 output at compare match
0
1
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
1
0
1
0
1
X
Input
capture
register
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Legend:
X: Don't care
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.18 TIORH_3 (channel 3)
Description
Bit 7
Bit 6
Bit 5
Bit 4
TGRB_3
IOB3 IOB2 IOB1 IOB0 Function
TIOC3B Pin Function
0
0
1
X
0
0
1
Output
compare
register
Output disabled
Initial output is 0
0 output at compare match
1
0
1
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
0
1
0
1
Output disabled
Initial output is 1
0 output at compare match
0
1
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
1
0
1
0
1
X
Input
capture
register
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Legend:
X: Don't care
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.19 TIORH_3 (channel 3)
Description
Bit 3
Bit 2
Bit 1
Bit 0
TGRA_3
IOA3 IOA2 IOA1 IOA0 Function
TIOC3A Pin Function
0
0
1
X
0
0
1
Output
compare
register
Output disabled
Initial output is 0
0 output at compare match
1
0
1
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
0
1
0
1
Output disabled
Initial output is 1
0 output at compare match
0
1
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
1
0
1
0
1
X
Input
capture
register
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Legend:
X: Don't care
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.20 TIORL_3 (channel 3)
Description
Bit 7
Bit 6
Bit 5
Bit 4
TGRD_3
IOD3 IOD2 IOD1 IOD0 Function
TIOC3D Pin Function
0
0
1
X
0
0
1
Output
compare
register*
Output disabled
Initial output is 0
0 output at compare match
1
0
1
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
0
1
0
1
Output disabled
Initial output is 1
0 output at compare match
0
1
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
1
0
1
0
1
X
Input
capture
register*
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Legend:
X: Don't care
Note:
*
When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.21 TIORL_3 (channel 3)
Description
Bit 3
Bit 2
Bit 1
Bit 0
TGRC_3
IOC3 IOC2 IOC1 IOC0 Function
TIOC3C Pin Function
0
0
1
X
0
0
1
Output
compare
register*
Output disabled
Initial output is 0
0 output at compare match
1
0
1
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
0
1
0
1
Output disabled
Initial output is 1
0 output at compare match
0
1
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
1
0
1
0
1
X
Input
capture
register*
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Legend:
X: Don't care
Note:
*
When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.22 TIORH_4 (channel 4)
Description
Bit 7
Bit 6
Bit 5
Bit 4
TGRB_4
IOB3 IOB2 IOB1 IOB0 Function
TIOC4B Pin Function
0
0
1
X
0
0
1
Output
compare
register
Output disabled
Initial output is 0
0 output at compare match
1
0
1
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
0
1
0
1
Output disabled
Initial output is 1
0 output at compare match
0
1
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
1
0
1
0
1
X
Input
capture
register
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Legend:
X: Don't care
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.23 TIORH_4 (channel 4)
Description
Bit 3
Bit 2
Bit 1
Bit 0
TGRA_4
IOA3 IOA2 IOA1 IOA0 Function
TIOC4A Pin Function
0
0
1
X
0
0
1
Output
compare
register
Output disabled
Initial output is 0
0 output at compare match
1
0
1
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
0
1
0
1
Output disabled
Initial output is 1
0 output at compare match
0
1
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
1
0
1
0
1
X
Input
capture
register
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Legend:
X: Don't care
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.24 TIORL_4 (channel 4)
Description
Bit 7
Bit 6
Bit 5
Bit 4
TGRD_4
IOD3 IOD2 IOD1 IOD0 Function
TIOC4B Pin Function
0
0
1
X
0
0
1
Output
compare
register*
Output disabled
Initial output is 0
0 output at compare match
1
0
1
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
0
1
0
1
Output disabled
Initial output is 1
0 output at compare match
0
1
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
1
0
1
0
1
X
Input
capture
register
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Legend:
X: Don't care
Note:
*
When the BFB bit in TMDR_4 is set to 1 and TGRD_4 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.25 TIORL_4 (channel 4)
Description
Bit 3
Bit 2
Bit 1
Bit 0
TGRC_4
IOC3 IOC2 IOC1 IOC0 Function
TIOC4C Pin Function
0
0
1
X
0
0
1
Output
compare
register*
Output disabled
Initial output is 0
0 output at compare match
1
0
1
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
0
1
0
1
Output disabled
Initial output is 1
0 output at compare match
0
1
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
1
0
1
0
1
X
Input
capture
register
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Legend:
X: Don't care
Note:
*
When the BFA bit in TMDR_4 is set to 1 and TGRC_4 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
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8. Multi-Function Timer Pulse Unit (MTU)
8.3.4 Timer Interrupt Enable Register (TIER)
The TIER registers are 8-bit readable/writable registers that control enabling or disabling of
interrupt requests for each channel. The MTU has five TIER registers, one for each channel.
Initial
Bit
Bit Name value
R/W
Description
7
TTGE
0
R/W
A/D Conversion Start Request Enable
Enables or disables generation of A/D conversion start
requests by TGRA input capture/compare match.
0: A/D conversion start request generation disabled
1: A/D conversion start request generation enabled
6
5
⎯
1
0
R
Reserved
This bit is always read as 1, and should only be written
with 1.
TCIEU
R/W
Underflow Interrupt Enable
Enables or disables interrupt requests (TCIU) by the
TCFU flag when the TCFU flag in TSR is set to 1 in
channels 1 and 2.
In channels 0, 3, and 4, bit 5 is reserved. It is always
read as 0, and the write value should always be 0.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
4
3
TCIEV
TGIED
0
0
R/W
R/W
Overflow Interrupt Enable
Enables or disables interrupt requests (TCIV) by the
TCFV flag when the TCFV flag in TSR is set to 1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled
TGR Interrupt Enable D
Enables or disables interrupt requests (TGID) by the
TGFD bit when the TGFD bit in TSR is set to 1 in
channels 0, 3, and 4.
In channels 1 and 2, bit 3 is reserved. It is always read as
0, and the write value should always be 0.
0: Interrupt requests (TGID) by TGFD bit disabled
1: Interrupt requests (TGID) by TGFD bit enabled
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8. Multi-Function Timer Pulse Unit (MTU)
Initial
Bit
Bit Name value
R/W
Description
2
TGIEC
0
R/W
TGR Interrupt Enable C
Enables or disables interrupt requests (TGIC) by the
TGFC bit when the TGFC bit in TSR is set to 1 in
channels 0, 3, and 4.
In channels 1 and 2, bit 2 is reserved. It is always read as
0, and the write value should always be 0.
0: Interrupt requests (TGIC) by TGFC bit disabled
1: Interrupt requests (TGIC) by TGFC bit enabled
1
0
TGIEB
TGIEA
0
0
R/W
R/W
TGR Interrupt Enable B
Enables or disables interrupt requests (TGIB) by the
TGFB bit when the TGFB bit in TSR is set to 1.
0: Interrupt requests (TGIB) by TGFB bit disabled
1: Interrupt requests (TGIB) by TGFB bit enabled
TGR Interrupt Enable A
Enables or disables interrupt requests (TGIA) by the
TGFA bit when the TGFA bit in TSR is set to 1.
0: Interrupt requests (TGIA) by TGFA bit disabled
1: Interrupt requests (TGIA) by TGFA bit enabled
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8. Multi-Function Timer Pulse Unit (MTU)
8.3.5 Timer Status Register (TSR)
The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The
MTU has five TSR registers, one for each channel.
Initial
Bit
Bit Name value
R/W
Description
7
TCFD
1
R
Count Direction Flag
Status flag that shows the direction in which TCNT
counts in channels 1, 2, 3, and 4.
In channel 0, bit 7 is reserved. It is always read as 1, and
should only be written with 1.
0: TCNT counts down
1: TCNT counts up
6
5
⎯
1
0
R
Reserved
This bit is always read as 1, and should only be written
with 1.
TCFU
R/(W)
Underflow Flag
Status flag that indicates that TCNT underflow has
occurred when channels 1 and 2 are set to phase
counting mode. Only 0 can be written, for flag clearing.
In channels 0, 3, and 4, bit 5 is reserved. It is always
read as 0, and the write value should always be 0.
[Setting condition]
•
When the TCNT value underflows (changes from
H'0000 to H'FFFF)
[Clearing condition]
When 0 is written to TCFU after reading TCFU = 1
•
4
TCFV
0
R/(W)
Overflow Flag
Status flag that indicates that TCNT overflow has
occurred. Only 0 can be written, for flag clearing.
[Setting condition]
•
When the TCNT value overflows (changes from
H'FFFF to H'0000)
In channel 4, when TCNT_4 is underflowed (changes
from H'0000 to H'0001) in complementary PWM
mode.
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
•
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8. Multi-Function Timer Pulse Unit (MTU)
Initial
Bit
Bit Name value
R/W
Description
3
TGFD
0
R/(W)
Input Capture/Output Compare Flag D
Status flag that indicates the occurrence of TGRD input
capture or compare match in channels 0, 3, and 4. Only
0 can be written, for flag clearing. In channels 1 and 2, bit
3 is reserved. It is always read as 0, and the write value
should always be 0.
[Setting conditions]
•
When TCNT = TGRD and TGRD is functioning as
output compare register
•
When TCNT value is transferred to TGRD by input
capture signal and TGRD is functioning as input
capture register
[Clearing condition]
When 0 is written to TGFD after reading TGFD = 1
•
2
TGFC
0
R/(W)
Input Capture/Output Compare Flag C
Status flag that indicates the occurrence of TGRC input
capture or compare match in channels 0, 3, and 4. Only
0 can be written, for flag clearing. In channels 1 and 2, bit
2 is reserved. It is always read as 0, and the write value
should always be 0.
[Setting conditions]
•
When TCNT = TGRC and TGRC is functioning as
output compare register
•
When TCNT value is transferred to TGRC by input
capture signal and TGRC is functioning as input
capture register
[Clearing condition]
•
When 0 is written to TGFC after reading TGFC = 1
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8. Multi-Function Timer Pulse Unit (MTU)
Initial
Bit
Bit Name value
R/W
Description
1
TGFB 0
R/(W)
Input Capture/Output Compare Flag B
Status flag that indicates the occurrence of TGRB input
capture or compare match. Only 0 can be written, for flag
clearing.
[Setting conditions]
•
When TCNT = TGRB and TGRB is functioning as
output compare register
•
When TCNT value is transferred to TGRB by input
capture signal and TGRB is functioning as input
capture register
[Clearing condition]
When 0 is written to TGFB after reading TGFB = 1
•
0
TGFA
0
R/(W)
Input Capture/Output Compare Flag A
Status flag that indicates the occurrence of TGRA input
capture or compare match. Only 0 can be written, for flag
clearing.
[Setting conditions]
•
When TCNT = TGRA and TGRA is functioning as
output compare register
•
When TCNT value is transferred to TGRA by input
capture signal and TGRA is functioning as input
capture register
[Clearing condition]
When 0 is written to TGFA after reading TGFA = 1
•
8.3.6
Timer Counter (TCNT)
The TCNT registers are 16-bit readable/writable counters. The MTU has five TCNT counters, one
for each channel. The initial value is H'0000.
The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit
unit.
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8. Multi-Function Timer Pulse Unit (MTU)
8.3.7
Timer General Register (TGR)
The TGR registers are dual function 16-bit readable/writable registers, functioning as either output
compare or input capture registers. The MTU has 16 TGR registers, four each for channels 0, 3,
and 4 and two each for channels 1 and 2. TGRC and TGRD for channels 0, 3, and 4 can also be
designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units;
they must always be accessed as a 16-bit unit. TGR buffer register combinations are TGRA-
TGRC and TGRB-TGRD. The initial value is H'FFFF.
8.3.8
Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 4.
When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT
counter.
Initial
Bit
Bit Name value
R/W
Description
7
6
CST4
CST3
0
0
R/W
R/W
Counter Start 4 and 3
These bits select operation or stoppage for TCNT.
If 0 is written to the CST bit during operation with the
TIOC pin designated for output, the counter stops but the
TIOC pin output compare output level is retained. If TIOR
is written to when the CST bit is cleared to 0, the pin
output level will be changed to the set initial output value.
0: TCNT_4 and TCNT_3 count operation is stopped
1: TCNT_4 and TCNT_3 performs count operation
5 to 3 ⎯
All 0
R
Reserved
These bits are always read as 0. Only 0 should be written
to these bits.
2
1
0
CST2
0
0
0
R/W
R/W
R/W
Counter Start 2 to 0
CST1
CST0
These bits select operation or stoppage for TCNT.
If 0 is written to the CST bit during operation with the
TIOC pin designated for output, the counter stops but the
TIOC pin output compare output level is retained. If TIOR
is written to when the CST bit is cleared to 0, the pin
output level will be changed to the set initial output value.
0: TCNT_2 and TCNT_0 count operation is stopped
1: TCNT_2 and TCNT_0 performs count operation
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8. Multi-Function Timer Pulse Unit (MTU)
8.3.9 Timer Synchro Register (TSYR)
TSYR is an 8-bit readable/writable register that selects independent operation or synchronous
operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when
the corresponding bit in TSYR is set to 1.
Initial
Bit
Bit Name value
R/W
Description
7
6
SYNC4
SYNC3
0
0
R/W
R/W
Timer Synchro 4 and 3
These bits are used to select whether operation is
independent of or synchronized with other channels.
When synchronous operation is selected, the TCNT
synchronous presetting of multiple channels, and
synchronous clearing by counter clearing on another
channel, are possible.
To set synchronous operation, the SYNC bits for at least
two channels must be set to 1. To set synchronous
clearing, in addition to the SYNC bit, the TCNT clearing
source must also be set by means of bits CCLR0 to
CCLR2 in TCR.
0: TCNT_4 and TCNT_3 operate independently (TCNT
presetting/clearing is unrelated to other channels)
1: TCNT_4 and TCNT_3 performs synchronous
operation
TCNT synchronous presetting/synchronous clearing is
possible
5 to 3 ⎯
All 0
R
Reserved
These bits are always read as 0. Only 0 should be written
to these bits.
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8. Multi-Function Timer Pulse Unit (MTU)
Initial
Bit
Bit Name value
R/W
Description
2
1
0
SYNC2
SYNC1
SYNC0
0
0
0
R/W
R/W
R/W
Timer Synchro 2 to 0
These bits are used to select whether operation is
independent of or synchronized with other channels.
When synchronous operation is selected, the TCNT
synchronous presetting of multiple channels, and
synchronous clearing by counter clearing on another
channel, are possible.
To set synchronous operation, the SYNC bits for at least
two channels must be set to 1. To set synchronous
clearing, in addition to the SYNC bit, the TCNT clearing
source must also be set by means of bits CCLR0 to
CCLR2 in TCR.
0: TCNT_2 to TCNT_0 operates independently (TCNT
presetting /clearing is unrelated to other channels)
1: TCNT_2 to TCNT_0 performs synchronous operation
TCNT synchronous presetting/synchronous clearing is
possible
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8. Multi-Function Timer Pulse Unit (MTU)
8.3.10 Timer Output Master Enable Register (TOER)
TOER is an 8-bit readable/writable register that enables/disables output settings for output pins
TIOC4D, TIOC4C, TIOC3D, TIOC4B, TIOC4A, and TIOC3B. These pins do not output
correctly if the TOER bits have not been set. Set TOER of CH3 and CH4 prior to setting TIOR of
CH3 and CH4.
Initial
Bit Name value
Bit
R/W
Description
7, 6
⎯
All 1
R
Reserved
These bits are always read as 1. Only 1 should be written
to these bits.
5
4
3
2
1
0
OE4D
0
R/W
R/W
R/W
R/W
R/W
R/W
Master Enable TIOC4D
This bit enables/disables the TIOC4D pin MTU output.
0: MTU output is disabled
1: MTU output is enabled
OE4C
OE3D
OE4B
OE4A
OE3B
0
0
0
0
0
Master Enable TIOC4C
This bit enables/disables the TIOC4C pin MTU output.
0: MTU output is disabled
1: MTU output is enabled
Master Enable TIOC3D
This bit enables/disables the TIOC3D pin MTU output.
0: MTU output is disabled
1: MTU output is enabled
Master Enable TIOC4B
This bit enables/disables the TIOC4B pin MTU output.
0: MTU output is disabled
1: MTU output is enabled
Master Enable TIOC4A
This bit enables/disables the TIOC4A pin MTU output.
0: MTU output is disabled
1: MTU output is enabled
Master Enable TIOC3B
This bit enables/disables the TIOC3B pin MTU output.
0: MTU output is disabled
1: MTU output is enabled
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8. Multi-Function Timer Pulse Unit (MTU)
8.3.11
Timer Output Control Register (TOCR)
TOCR is an 8-bit readable/writable register that enables/disables PWM synchronized toggle
output in complementary PWM mode/reset synchronized PWM mode, and controls output level
inversion of PWM output.
Initial
Bit
Bit Name value
R/W
Description
7
⎯
0
R
Reserved
These bits are always read as 0. Only 0 should be written
to this bit.
6
PSYE
0
R/W
PWM Synchronous Output Enable
This bit selects the enable/disable of toggle output
synchronized with the PWM period.
0: Toggle output is disabled
1: Toggle output is enabled
5 to 2 ⎯
All 0
0
R
Reserved
These bits are always read as 0. Only 0 should be written
to this bit.
1
0
OLSN
R/W
Output Level Select N
This bit selects the reverse phase output level in reset-
synchronized PWM mode/complementary PWM mode.
See table 8.26
OLSP
0
R/W
Output Level Select P
This bit selects the positive phase output level in reset-
synchronized PWM mode/complementary PWM mode.
See table 8.27
Table 8.26 Output Level Select Function
Bit 1
Function
Compare Match Output
OLSN Initial Output
Active Level
Low level
Increment Count
High level
Decrement Count
Low level
0
1
High level
Low level
High level
Low level
High level
Note: The reverse phase waveform initial output value changes to active level after elapse of the
dead time after count start.
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.27 Output Level Select Function
Bit 1
Function
Compare Match Output
OLSP Initial Output
Active Level
Low level
Increment Count
Low level
Decrement Count
High level
0
1
High level
Low level
High level
High level
Low level
Figure 8.2 shows an example of complementary PWM mode output (1 phase) when OLSN = 1,
OLSP = 1.
TCNT_3, and
TCNT_4 values
TGRA_3
TCNT_3
TCNT_4
TGRA_4
TDDR
H'0000
Time
Compare match
output (up count)
Initial
output
Compare match
output (down count)
Positive
phase output
Active level
Initial
output
Compare match
output (down count)
Compare match
output (up count)
Reverse
phase output
Active
level
Active level
Figure 8.2 Complementary PWM Mode Output Level Example
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8. Multi-Function Timer Pulse Unit (MTU)
8.3.12
Timer Gate Control Register (TGCR)
TGCR is an 8-bit readable/writable register that controls the waveform output necessary for
brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode.
These register settings are ineffective for anything other than complementary PWM mode/reset-
synchronized PWM mode.
Initial
Bit
Bit Name value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 1. Only 1 should be written to
this bit.
6
5
BDC
0
R/W
R/W
Brushless DC Motor
This bit selects whether to make the functions of this
register (TGCR) effective or ineffective.
0: Ordinary output
1: Functions of this register are made effective
N
0
Reverse Phase Output (N) Control
This bit selects whether the level output or the reset-
synchronized PWM/complementary PWM output while
the reverse pins (TIOC3D, TIOC4C, and TIOC4D) are
on-output.
0: Level output
1: Reset synchronized PWM/complementary PWM
output
4
P
0
R/W
Positive Phase Output (P) Control
This bit selects whether the level output or the reset-
synchronized PWM/complementary PWM output while
the positive pin (TIOC3B, TIOC4A, and TIOC4B) are on-
output.
0: Level output
1: Reset synchronized PWM/complementary PWM
output
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8. Multi-Function Timer Pulse Unit (MTU)
Initial
Bit
Bit Name value
R/W
Description
3
FB
0
R/W
External Feedback Signal Enable
This bit selects whether the switching of the output of the
positive/reverse phase is carried out automatically with
the MTU/channel 0 TGRA, TGRB, TGRC input capture
signals or by writing 0 or 1 to bits 2 to 0 in TGCR.
0: Output switching is carried out by external input (Input
sources are channel 0 TGRA, TGRB, TGRC input
capture signal)
1: Output switching is carried out by software (TGCR's
UF, VF, WF settings).
2
1
0
WF
VF
UF
0
0
0
R/W
R/W
R/W
Output Phase Switch 2 to 0
These bits set the positive phase/negative phase output
phase on or off state. The setting of these bits is valid
only when the FB bit in this register is set to 1. In this
case, the setting of bits 2 to 0 is a substitute for external
input. See table 8.28.
Table 8.28 Output level Select Function
Function
Bit 2
WF
0
Bit 1
VF
0
Bit 0
UF
0
TIOC3B TIOC4A TIOC4B TIOC3D TIOC4C TIOC4D
U Phase V Phase W Phase U Phase V Phase W Phase
OFF
ON
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
OFF
ON
1
1
0
1
0
OFF
OFF
OFF
ON
OFF
ON
1
ON
OFF
OFF
OFF
ON
1
0
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
1
OFF
ON
ON
0
OFF
OFF
OFF
OFF
1
OFF
OFF
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8. Multi-Function Timer Pulse Unit (MTU)
8.3.13
Timer Subcounter (TCNTS)
TCNTS is a 16-bit read-only counter that is used only in complementary PWM mode. The initial
value is H'0000.
Note: Accessing the TCNTS in 8-bit units is prohibited. Always access in 16-bit units.
8.3.14
Timer Dead Time Data Register (TDDR)
TDDR is a 16-bit register, used only in complementary PWM mode, that specifies the TCNT_3
and TCNT_4 counter offset values. In complementary PWM mode, when the TCNT_3 and
TCNT_4 counters are cleared and then restarted, the TDDR register value is loaded into the
TCNT_3 counter and the count operation starts. The initial value is H'FFFF.
Note: Accessing the TDDR in 8-bit units is prohibited. Always access in 16-bit units.
8.3.15
Timer Period Data Register (TCDR)
TCDR is a 16-bit register used only in complementary PWM mode. Set half the PWM carrier
sync value as the TCDR register value. This register is constantly compared with the TCNTS
counter in complementary PWM mode, and when a match occurs, the TCNTS counter switches
direction (decrement to increment). The initial value is H'FFFF.
Note: Accessing the TCDR in 8-bit units is prohibited. Always access in 16-bit units.
8.3.16
Timer Period Buffer Register (TCBR)
The timer period buffer register (TCBR) is a 16-bit register used only in complementary PWM
mode. It functions as a buffer register for the TCDR register. The TCBR register values are
transferred to the TCDR register with the transfer timing set in the TMDR register. The initial
value is H'FFFF.
Note: Accessing the TCBR in 8-bit units is prohibited. Always access in 16-bit units.
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8. Multi-Function Timer Pulse Unit (MTU)
8.3.17 Bus Master Interface
The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer period
buffer register (TCBR), and timer dead time data register (TDDR), and timer period data register
(TCDR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8-bit
read/write is not possible. Always access in 16-bit units.
All registers other than the above registers are 8-bit registers. These are connected to the CPU by
a 16-bit data bus, so 16-bit read/writes and 8-bit read/writes are both possible.
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8. Multi-Function Timer Pulse Unit (MTU)
8.4
Operation
8.4.1
Basic Functions
Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of
free-running operation, synchronous counting, and external event counting.
Each TGR can be used as an input capture register or output compare register.
Always set the MTU external pins function using the pin function controller (PFC).
Counter Operation
When one of bits CST0 to CST4 is set to 1 in TSTR, the TCNT counter for the corresponding
channel begins counting. TCNT can operate as a free-running counter, periodic counter, for
example.
Example of Count Operation Setting Procedure: Figure 8.3 shows an example of the count
operation setting procedure.
[1] Select the counter clock
Operation selection
with bits TPSC2 to TPSC0
in TCR. At the same time,
select the input clock edge
with bits CKEG1 and
CKEG0 in TCR.
[1]
Select counter clock
Periodic counter
[2] For periodic counter
operation, select the TGR
to be used as the TCNT
clearing source with bits
CCLR2 to CCLR0 in TCR.
Free-running counter
Select counter clearing
source
[2]
[3]
[3] Designate the TGR
selected in [2] as an output
compare register by means
of TIOR.
Select output compare
register
[4] Set the periodic counter
cycle in the TGR selected
in [2].
Set period
[4]
[5]
[5] Set the CST bit in TSTR to
1 to start the counter
operation.
Start count operation
[5]
Start count operation
<Periodic counter>
<Free-running counter>
Figure 8.3 Example of Counter Operation Setting Procedure
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8. Multi-Function Timer Pulse Unit (MTU)
Free-Running Count Operation and Periodic Count Operation: Immediately after a reset, the
MTU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR
is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter.
When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of
the corresponding TCIEV bit in TIER is 1 at this point, the MTU requests an interrupt. After
overflow, TCNT starts counting up again from H'0000.
Figure 8.4 illustrates free-running counter operation.
TCNT value
H'FFFF
H'0000
CST bit
Time
TCFV
Figure 8.4 Free-Running Counter Operation
When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant
channel performs periodic count operation. The TGR register for setting the period is designated
as an output compare register, and counter clearing by compare match is selected by means of bits
CCLR0 to CCLR2 in TCR. After the settings have been made, TCNT starts up-count operation as
a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches
the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000.
If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt.
After a compare match, TCNT starts counting up again from H'0000.
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8. Multi-Function Timer Pulse Unit (MTU)
Figure 8.5 illustrates periodic counter operation.
Counter cleared by TGR
compare match
TCNT value
TGR
H'0000
CST bit
Time
Flag cleared by software
TGF
Figure 8.5 Periodic Counter Operation
Waveform Output by Compare Match
The MTU can perform 0, 1, or toggle output from the corresponding output pin using compare
match.
Example of Setting Procedure for Waveform Output by Compare Match: Figure 8.6 shows
an example of the setting procedure for waveform output by compare match.
[1] Select initial value 0 output or 1 output,
and compare match output value 0
output, 1 output, or toggle output, by
means of TIOR. The set initial value is
output at the TIOC pin until the first
compare match occurs.
Output selection
Select waveform output
mode
[1]
[2] Set the timing for compare match
generation in TGR.
[3] Set the CST bit in TSTR to 1 to start the
count operation.
[2]
[3]
Set output timing
Start count operation
<Waveform output>
Figure 8.6 Example of Setting Procedure for Waveform Output by Compare Match
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8. Multi-Function Timer Pulse Unit (MTU)
Examples of Waveform Output Operation: Figure 8.7 shows an example of 0 output/1 output.
In this example TCNT has been designated as a free-running counter, and settings have been made
such that 1 is output by compare match A, and 0 is output by compare match B. When the set level
and the pin level coincide, the pin level does not change.
TCNT value
H'FFFF
TGRA
TGRB
Time
H'0000
No change
No change
1 output
TIOCA
TIOCB
0 output
No change
No change
Figure 8.7 Example of 0 Output/1 Output Operation
Figure 8.8 shows an example of toggle output.
In this example, TCNT has been designated as a periodic counter (with counter clearing on
compare match B), and settings have been made such that the output is toggled by both compare
match A and compare match B.
TCNT value
Counter cleared by TGRB compare match
H'FFFF
TGRB
TGRA
Time
H'0000
Toggle output
Toggle output
TIOCB
TIOCA
Figure 8.8 Example of Toggle Output Operation
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8. Multi-Function Timer Pulse Unit (MTU)
Input Capture Function
The TCNT value can be transferred to TGR on detection of the TIOC pin input edge.
Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0 and 1,
it is also possible to specify another channel's counter input clock or compare match signal as the
input capture source.
Note: When another channel's counter input clock is used as the input capture input for channels
0 and 1, φ /1 should not be selected as the counter input clock used for input capture input.
Input capture will not be generated if φ /1 is selected.
Example of Input Capture Operation Setting Procedure: Figure 8.9 shows an example of the
input capture operation setting procedure.
[1] Designate TGR as an input capture
Input selection
register by means of TIOR, and select
rising edge, falling edge, or both edges
as the input capture source and input
signal edge.
[1]
[2]
Select input capture input
[2] Set the CST bit in TSTR to 1 to start
the count operation.
Start count
<Input capture operation>
Figure 8.9 Example of Input Capture Operation Setting Procedure
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8. Multi-Function Timer Pulse Unit (MTU)
Example of Input Capture Operation: Figure 8.10 shows an example of input capture operation.
In this example both rising and falling edges have been selected as the TIOCA pin input capture
input edge, the falling edge has been selected as the TIOCB pin input capture input edge, and
counter clearing by TGRB input capture has been designated for TCNT.
Counter cleared by TIOCB
input (falling edge)
TCNT value
H'0180
H'0160
H'0010
H'0005
Time
H'0000
TIOCA
TGRA
H'0005
H'0160
H'0010
TIOCB
TGRB
H'0180
Figure 8.10 Example of Input Capture Operation
Synchronous Operation
In synchronous operation, the values in a number of TCNT counters can be rewritten
8.4.2
simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared
simultaneously by making the appropriate setting in TCR (synchronous clearing).
Synchronous operation enables TGR to be incremented with respect to a single time base.
Channels 0 to 4 can all be designated for synchronous operation.
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8. Multi-Function Timer Pulse Unit (MTU)
Example of Synchronous Operation Setting Procedure: Figure 8.11 shows an example of the
synchronous operation setting procedure.
Synchronous operation
selection
Set synchronous
[1]
operation
Synchronous presetting
Set TCNT
Synchronous clearing
[2]
Clearing
source generation
channel?
No
Yes
Select counter
clearing source
Set synchronous
counter clearing
[3]
[5]
[4]
[5]
Start count
Start count
<Synchronous presetting>
<Counter clearing>
<Synchronous clearing>
[1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous
operation.
[2] When the TCNT counter of any of the channels designated for synchronous operation is written to,
the same value is simultaneously written to the other TCNT counters.
[3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc.
[4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source.
[5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.
Figure 8.11 Example of Synchronous Operation Setting Procedure
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8. Multi-Function Timer Pulse Unit (MTU)
Example of Synchronous Operation: Figure 8.12 shows an example of synchronous operation.
In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to
2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and
synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time,
synchronous presetting, and synchronous clearing by TGRB_0 compare match, are performed for
channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle.
For details of PWM modes, see section 8.4.5, PWM Modes.
Synchronous clearing by TGRB_0 compare match
TCNT_0 to TCNT_2
values
TGRB_0
TGRB_1
TGRA_0
TGRB_2
TGRA_1
TGRA_2
Time
H'0000
TIOCA_0
TIOCA_1
TIOCA_2
Figure 8.12 Example of Synchronous Operation
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8. Multi-Function Timer Pulse Unit (MTU)
8.4.3
Buffer Operation
Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer
registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or as a compare match register.
Table 8.29 shows the register combinations used in buffer operation.
Table 8.29 Register Combinations in Buffer Operation
Channel
Timer General Register
TGRA_0
Buffer Register
TGRC_0
0
TGRB_0
TGRD_0
3
4
TGRA_3
TGRC_3
TGRB_3
TGRD_3
TGRA_4
TGRC_4
TGRB_4
TGRD_4
•
When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 8.13.
Compare match signal
Buffer
register
Timer general
register
Comparator
TCNT
Figure 8.13 Compare Match Buffer Operation
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8. Multi-Function Timer Pulse Unit (MTU)
•
When TGR is an input capture register
When input capture occurs, the value in TCNT is transferred to TGR and the value previously
held in the timer general register is transferred to the buffer register.
This operation is illustrated in figure 8.14.
Input capture
signal
Buffer
register
Timer general
register
TCNT
Figure 8.14 Input Capture Buffer Operation
Example of Buffer Operation Setting Procedure: Figure 8.15 shows an example of the buffer
operation setting procedure.
[1] Designate TGR as an input capture register or
Buffer operation
output compare register by means of TIOR.
[2] Designate TGR for buffer operation with bits
BFA and BFB in TMDR.
[1]
[2]
Select TGR function
Set buffer operation
[3] Set the CST bit in TSTR to 1 start the count
operation.
Start count
[3]
<Buffer operation>
Figure 8.15 Example of Buffer Operation Setting Procedure
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8. Multi-Function Timer Pulse Unit (MTU)
Examples of Buffer Operation:
When TGR is an output compare register
•
Figure 8.16 shows an operation example in which PWM mode 1 has been designated for
channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used
in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0
output at compare match B.
As buffer operation has been set, when compare match A occurs the output changes and the
value in buffer register TGRC is simultaneously transferred to timer general register TGRA.
This operation is repeated each time that compare match A occurs.
For details of PWM modes, see section 8.4.5, PWM Modes.
TCNT value
TGRB_0
H'0520
H'0450
H'0200
TGRA_0
Time
H'0000
TGRC_0
H'0200
H'0450
H'0520
Transfer
TGRA_0
TIOCA
H'0200
H'0450
Figure 8.16 Example of Buffer Operation (1)
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8. Multi-Function Timer Pulse Unit (MTU)
•
When TGR is an input capture register
Figure 8.17 shows an operation example in which TGRA has been designated as an input
capture register, and buffer operation has been designated for TGRA and TGRC.
Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling
edges have been selected as the TIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in TGRA upon the
occurrence of input capture A, the value previously stored in TGRA is simultaneously
transferred to TGRC.
TCNT value
H'0F07
H'09FB
H'0532
H'0000
TIOCA
Time
H'0532
H'0F07
H'0532
H'09FB
H'0F07
TGRA
TGRC
Figure 8.17 Example of Buffer Operation (2)
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8. Multi-Function Timer Pulse Unit (MTU)
8.4.4
Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 counter clock upon overflow/underflow of
TCNT_2 as set in bits TPSC0 to TPSC2 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 8.30 shows the register combinations used in cascaded operation.
Table 8.30 Cascaded Combinations
Combination
Upper 16 Bits
Lower 16 Bits
Channels 1 and 2
TCNT_1
TCNT_2
Note: When phase counting mode is set for channel 1 or 2, the counter clock setting is invalid and
the counters operates independently in phase counting mode.
Example of Cascaded Operation Setting Procedure: Figure 8.18 shows an example of the
setting procedure for cascaded operation.
[1] Set bits TPSC2 to TPSC0 in the channel 1
Cascaded operation
TCR to B'111 to select TCNT_2 overflow/
underflow counting.
[2] Set the CST bit in TSTR for the upper and
lower channel to 1 to start the count
operation.
Set cascading
[1]
[2]
Start count
<Cascaded operation>
Figure 8.18 Cascaded Operation Setting Procedure
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8. Multi-Function Timer Pulse Unit (MTU)
Examples of Cascaded Operation: Figure 8.19 illustrates the operation when TCNT_2
overflow/underflow counting has been set for TCNT_1 and phase counting mode has been
designated for channel 2.
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
TCLKC
TCLKD
FFFD FFFE FFFF 0000
0000
0001
0002
0001
0001 0000 FFFF
TCNT_2
TCNT_1
0000
Figure 8.19 Example of Cascaded Operation
8.4.5
PWM Modes
In PWM mode, PWM waveforms are output from the output pins. The output level can be selected
as 0, 1, or toggle output in response to a compare match of each TGR.
TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty
cycle.
Designating TGR compare match as the counter clearing source enables the period to be set in that
register. All channels can be designated for PWM mode independently. Synchronous operation is
also possible.
There are two PWM modes, as described below.
•
PWM mode 1
PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and
TGRC with TGRD. The output specified by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is
output from the TIOCA and TIOCC pins at compare matches A and C, and the output
specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B
and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired
TGRs are identical, the output value does not change when a compare match occurs.
In PWM mode 1, a maximum 8-phase PWM output is possible.
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8. Multi-Function Timer Pulse Unit (MTU)
•
PWM mode 2
PWM output is generated using one TGR as the cycle register and the others as duty cycle
registers. The output specified in TIOR is performed by means of compare matches. Upon
counter clearing by a synchronization register compare match, the output value of each pin is
the initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical,
the output value does not change when a compare match occurs.
In PWM mode 2, a maximum 8-phase PWM output is possible in combination use with
synchronous operation.
The correspondence between PWM output pins and registers is shown in table 8.31.
Table 8.31 PWM Output Registers and Output Pins
Output Pins
Channel
Registers
TGRA_0
TGRB_0
TGRC_0
TGRD_0
TGRA_1
TGRB_1
TGRA_2
TGRB_2
TGRA_3
TGRB_3
TGRC_3
TGRD_3
TGRA_4
TGRB_4
TGRC_4
TGRD_4
PWM Mode 1
PWM Mode 2
TIOC0A
0
TIOC0A
TIOC0B
TIOC0C
TIOC1A
TIOC2A
TIOC3A
TIOC3C
TIOC4A
TIOC4C
TIOC0C
TIOC0D
1
2
3
TIOC1A
TIOC1B
TIOC2A
TIOC2B
Cannot be set
Cannot be set
Cannot be set
Cannot be set
Cannot be set
Cannot be set
Cannot be set
Cannot be set
4
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.
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8. Multi-Function Timer Pulse Unit (MTU)
Example of PWM Mode Setting Procedure: Figure 8.20 shows an example of the PWM mode
setting procedure.
[1] Select the counter clock with bits TPSC2 to
PWM mode
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and
CKEG0 in TCR.
[1]
[2]
Select counter clock
[2] Use bits CCLR2 to CCLR0 in TCR to select
the TGR to be used as the TCNT clearing
source.
Select counter clearing
source
[3] Use TIOR to designate the TGR as an output
compare register, and select the initial value
and output value.
[3]
Select waveform
output level
[4] Set the cycle in the TGR selected in [2], and
set the duty in the other TGR.
[5] Select the PWM mode with bits MD3 to MD0
in TMDR.
Set TGR
[4]
[5]
[6]
[6] Set the CST bit in TSTR to 1 to start the
count operation.
Set PWM mode
Start count
<PWM mode>
Figure 8.20 Example of PWM Mode Setting Procedure
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8. Multi-Function Timer Pulse Unit (MTU)
Examples of PWM Mode Operation: Figure 8.21 shows an example of PWM mode 1 operation.
In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA
initial output value and output value, and 1 is set as the TGRB output value.
In this case, the value set in TGRA is used as the period, and the values set in the TGRB registers
are used as the duty cycle.
Counter cleared by
TGRA compare match
TCNT value
TGRA
TGRB
H'0000
TIOCA
Time
Figure 8.21 Example of PWM Mode Operation (1)
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8. Multi-Function Timer Pulse Unit (MTU)
Figure 8.22 shows an example of PWM mode 2 operation.
In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare
match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the
output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase
PWM waveform.
In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs are
used as the duty cycle levels.
Counter cleared by
TGRB_1 compare match
TCNT value
TGRB_1
TGRA_1
TGRD_0
TGRC_0
TGRB_0
TGRA_0
H'0000
Time
TIOC0A
TIOC0B
TIOC0C
TIOC0D
TIOC1A
Figure 8.22 Example of PWM Mode Operation (2)
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8. Multi-Function Timer Pulse Unit (MTU)
Figure 8.23 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle
in PWM mode.
TCNT value
TGRB rewritten
TGRA
TGRB
rewritten
TGRB
TGRB rewritten
H'0000
Time
0% duty cycle
TIOCA
Output does not change when cycle register and duty register
compare matches occur simultaneously
TCNT value
TGRB rewritten
TGRA
TGRB rewritten
TGRB rewritten
TGRB
H'0000
Time
100% duty cycle
TIOCA
Output does not change when cycle register and duty
register compare matches occur simultaneously
TCNT value
TGRB rewritten
TGRA
TGRB rewritten
TGRB
TGRB rewritten
Time
H'0000
100% duty cycle
0% duty cycle
TIOCA
Figure 8.23 Example of PWM Mode Operation (3)
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8. Multi-Function Timer Pulse Unit (MTU)
8.4.6 Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT counts up or down accordingly. This mode can be set for channels 1 and 2.
When phase counting mode is set, an external clock is selected as the counter input clock and
TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits
CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of
TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be
used.
This can be used for two-phase encoder pulse input.
If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs
when TCNT is counting down, the TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is
counting up or down.
Table 8.32 shows the correspondence between external clock pins and channels.
Table 8.32 Phase Counting Mode Clock Input Pins
External Clock Pins
Channels
A-Phase
TCLKA
TCLKC
B-Phase
TCLKB
TCLKD
When channel 1 is set to phase counting mode
When channel 2 is set to phase counting mode
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8. Multi-Function Timer Pulse Unit (MTU)
Example of Phase Counting Mode Setting Procedure: Figure 8.24 shows an example of the
phase counting mode setting procedure.
[1] Select phase counting mode with bits
Phase counting mode
MD3 to MD0 in TMDR.
[2] Set the CST bit in TSTR to 1 to start
the count operation.
Select phase counting
mode
[1]
[2]
Start count
<Phase counting mode>
Figure 8.24 Example of Phase Counting Mode Setting Procedure
Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or
down according to the phase difference between two external clocks. There are four modes,
according to the count conditions.
•
Phase counting mode 1
Figure 8.25 shows an example of phase counting mode 1 operation, and table 8.33 summarizes
the TCNT up/down-count conditions.
TCLKA (channel 1)
TCLKC (channel 2)
TCLKB (channel 1)
TCLKD (channel 2)
TCNT value
Down-count
Up-count
Time
Figure 8.25 Example of Phase Counting Mode 1 Operation
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.33 Up/Down-Count Conditions in Phase Counting Mode 1
TCLKA (Channel 1)
TCLKC (Channel 2)
TCLKB (Channel 1)
TCLKD (Channel 2)
Operation
High level
Low level
Up-count
Low level
High level
High level
Low level
Down-count
High level
Low level
Legend:
: Rising edge
: Falling edge
•
Phase counting mode 2
Figure 8.26 shows an example of phase counting mode 2 operation, and table 8.34 summarizes
the TCNT up/down-count conditions.
TCLKA (channel 1)
TCLKC (channel 2)
TCLKB (channel 1)
TCLKD (channel 2)
TCNT value
Up-count
Down-count
Time
Figure 8.26 Example of Phase Counting Mode 2 Operation
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.34 Up/Down-Count Conditions in Phase Counting Mode 2
TCLKA (Channel 1)
TCLKC (Channel 2)
TCLKB (Channel 1)
TCLKD (Channel 2)
Operation
High level
Low level
Don't care
Low level
High level
Up-count
High level
Low level
Don't care
High level
Low level
Down-count
Legend:
: Rising edge
: Falling edge
•
Phase counting mode 3
Figure 8.27 shows an example of phase counting mode 3 operation, and table 8.35 summarizes
the TCNT up/down-count conditions.
TCLKA (channel 1)
TCLKC (channel 2)
TCLKB (channel 1)
TCLKD (channel 2)
TCNT value
Down-count
Up-count
Time
Figure 8.27 Example of Phase Counting Mode 3 Operation
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.35 Up/Down-Count Conditions in Phase Counting Mode 3
TCLKA (Channel 1)
TCLKC (Channel 2)
TCLKB (Channel 1)
TCLKD (Channel 2)
Operation
High level
Low level
Don't care
Low level
High level
Up-count
High level
Low level
Down-count
Don't care
High level
Low level
Legend:
: Rising edge
: Falling edge
•
Phase counting mode 4
Figure 8.28 shows an example of phase counting mode 4 operation, and table 8.36 summarizes
the TCNT up/down-count conditions.
TCLKA (channel 1)
TCLKC (channel 2)
TCLKB (channel 1)
TCLKD (channel 2)
TCNT value
Down-count
Up-count
Time
Figure 8.28 Example of Phase Counting Mode 4 Operation
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.36 Up/Down-Count Conditions in Phase Counting Mode 4
TCLKA (Channel 1)
TCLKC (Channel 2)
TCLKB (Channel 1)
TCLKD (Channel 2)
Operation
High level
Low level
Up-count
Low level
High level
Don't care
Down-count
Don't care
High level
Low level
High level
Low level
Legend:
: Rising edge
: Falling edge
Phase Counting Mode Application Example: Figure 8.29 shows an example in which channel 1
is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase
encoder pulses in order to detect position or speed.
Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input
to TCLKA and TCLKB.
Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and
TGRC_0 are used for the compare match function and are set with the speed control period and
position control period. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating
in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture
source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected.
TGRA_1 and TGRB_1 for channel 1 are designated for input capture, and channel 0 TGRA_0 and
TGRC_0 compare matches are selected as the input capture source and store the up/down-counter
values for the control periods.
This procedure enables the accurate detection of position and speed.
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8. Multi-Function Timer Pulse Unit (MTU)
Channel 1
Edge
detection
circuit
TCLKA
TCLKB
TCNT_1
TGRA_1
(speed period capture)
TGRB_1
(position period capture)
TCNT_0
+
-
TGRA_0
(speed control period)
+
-
TGRC_0
(position control period)
TGRB_0 (pulse width capture)
TGRD_0 (buffer operation)
Channel 0
Figure 8.29 Phase Counting Mode Application Example
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8. Multi-Function Timer Pulse Unit (MTU)
8.4.7
Reset-Synchronized PWM Mode
In the reset-synchronized PWM mode, three-phase output of positive and negative PWM
waveforms that share a common wave transition point can be obtained by combining channels 3
and 4.
When set for reset-synchronized PWM mode, the TIOC3B, TIOC3D, TIOC4A, TIOC4C,
TIOC4B, and TIOC4D pins function as PWM output pins and TCNT3 functions as an upcounter.
Table 8.37 shows the PWM output pins used. Table 8.38 shows the settings of the registers.
Table 8.37 Output Pins for Reset-Synchronized PWM Mode
Channel
Output Pin
TIOC3B
TIOC3D
TIOC4A
TIOC4C
TIOC4B
TIOC4D
Description
3
PWM output pin 1
PWM output pin 1' (negative-phase waveform of PWM output 1)
PWM output pin 2
4
PWM output pin 2' (negative-phase waveform of PWM output 2)
PWM output pin 3
PWM output pin 3' (negative-phase waveform of PWM output 3)
Table 8.38 Register Settings for Reset-Synchronized PWM Mode
Register
TCNT_3
TCNT_4
TGRA_3
TGRB_3
TGRA_4
TGRB_4
Description of Setting
Initial setting of H'0000
Initial setting of H'0000
Set count cycle for TCNT_3
Sets the turning point for PWM waveform output by the TIOC3B and TIOC3D pins
Sets the turning point for PWM waveform output by the TIOC4A and TIOC4C pins
Sets the turning point for PWM waveform output by the TIOC4B and TIOC4D pins
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8. Multi-Function Timer Pulse Unit (MTU)
Procedure for Selecting the Reset-Synchronized PWM Mode: Figure 8.30 shows an example
of procedure for selecting the reset synchronized PWM mode.
1. Clear the CST3 and CST4 bits in the TSTR to 0 to halt the counting of TCNT. The reset-
synchronized PWM mode must be set up while TCNT_3 and TCNT_4 are halted.
2. Set bits TPSC2 to TPSC0 and CKEG1 and CKEG0 in the TCR_3 to select the counter clock
and clock edge for channel 3. Set bits CCLR2 to CCLR0 in the TCR_3 to select TGRA
compare-match as a counter clear source.
3. When performing brushless DC motor control, set bit BDC in the timer gate control register
(TGCR) and set the feedback signal input source and output chopping or gate signal direct
output.
4. Reset TCNT_3 and TCNT_4 to H'0000.
5. TGRA_3 is the period register. Set the waveform period value in TGRA_3. Set the transition
timing of the PWM output waveforms in TGRB_3, TGRA_4, and TGRB_4. Set times within
the compare-match range of TCNT_3.
X ≤ TGRA_3 (X: set value).
6. Select enabling/disabling of toggle output synchronized with the PMW cycle using bit PSYE
in the timer output control register (TOCR), and set the PWM output level with bits OLSP and
OLSN.
7. Set bits MD3 to MD0 in TMDR_3 to B'1000 to select the reset-synchronized PWM mode.
TIOC3A, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C and TIOC4D function as PWM
output pins*. Do not set to TMDR_4.
8. Set the enabling/disabling of the PWM waveform output pin in TOER.
9. Set the CST3 bit in the TSTR to 1 to start the count operation.
Notes: The output waveform starts to toggle operation at the point of TCNT_3 = TGRA_3 = X by
setting X = TGRA, i.e., cycle = duty cycle.
* PFC registers should be specified before this procedure.
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8. Multi-Function Timer Pulse Unit (MTU)
Reset-synchronized
PWM mode
Stop counting
1
Select counter clock and
counter clear source
2
3
Brushless DC motor
control setting
4
5
6
Set TCNT
Set TGR
PWM cycle output enabling,
PWM output level setting
7
Set reset-synchronized
PWM mode
8
9
Enable waveform output
Start count operation
Reset-synchronized PWM mode
Figure 8.30 Procedure for Selecting the Reset-Synchronized PWM Mode
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8. Multi-Function Timer Pulse Unit (MTU)
Reset-Synchronized PWM Mode Operation: Figure 8.31 shows an example of operation in the
reset-synchronized PWM mode. TCNT_3 and TCNT_4 operate as upcounters. The counter is
cleared when a TCNT_3 and TGRA_3 compare-match occurs, and then begins counting up from
H'0000. The PWM output pin output toggles with each occurrence of a TGRB_3, TGRA_4,
TGRB_4 compare-match, and upon counter clears.
TCNT_3 and TCNT_4
values
TGRA_3
TGRB_3
TGRA_4
TGRB_4
H'0000
Time
TIOC3B
TIOC3D
TIOC4A
TIOC4C
TIOC4B
TIOC4D
Figure 8.31 Reset-Synchronized PWM Mode Operation Example
(When the TOCR's OLSN = 1 and OLSP = 1)
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8. Multi-Function Timer Pulse Unit (MTU)
8.4.8
Complementary PWM Mode
In the complementary PWM mode, three-phase output of non-overlapping positive and negative
PWM waveforms can be obtained by combining channels 3 and 4.
In complementary PWM mode, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D
pins function as PWM output pins, the TIOC3A pin can be set for toggle output synchronized with
the PWM period. TCNT_3 and TCNT_4 function as increment/decrement counters.
Table 8.39 shows the PWM output pins used. Table 8.40 shows the settings of the registers used.
A function to directly cut off the PWM output by using an external signal is supported as a port
function.
Table 8.39 Output Pins for Complementary PWM Mode
Channel
Output Pin
TIOC3A
TIOC3B
TIOC3C
TIOC3D
Description
3
Toggle output synchronized with PWM period (or I/O port)
PWM output pin 1
I/O port*
PWM output pin 1' (non-overlapping negative-phase waveform
of PWM output 1)
4
TIOC4A
TIOC4C
PWM output pin 2
PWM output pin 2' (non-overlapping negative-phase waveform
of PWM output 2)
TIOC4B
TIOC4D
PWM output pin 3
PWM output pin 3' (non-overlapping negative-phase waveform
of PWM output 3)
Note:
*
Avoid setting the TIOC3C pin as a timer I/O pin in the complementary PWM mode.
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8. Multi-Function Timer Pulse Unit (MTU)
Table 8.40 Register Settings for Complementary PWM Mode
Channel
Counter/Register
Description
Read/Write from CPU
3
TCNT_3
Start of up-count from value set
in dead time register
Maskable by BSC/BCR1
setting*
TGRA_3
TGRB_3
Set TCNT_3 upper limit value
(1/2 carrier cycle + dead time)
Maskable by BSC/BCR1
setting*
PWM output 1 compare register
Maskable by BSC/BCR1
setting*
TGRC_3
TGRD_3
TGRA_3 buffer register
Always readable/writable
Always readable/writable
PWM output 1/TGRB_3 buffer
register
4
TCNT_4
TGRA_4
TGRB_4
TGRC_4
TGRD_4
Up-count start, initialized to
H'0000
Maskable by BSC/BCR1
setting*
PWM output 2 compare register
Maskable by BSC/BCR1
setting*
PWM output 3 compare register
Maskable by BSC/BCR1
setting*
PWM output 2/TGRA_4 buffer
register
Always readable/writable
PWM output 3/TGRB_4 buffer
register
Always readable/writable
Timer dead time data register
(TDDR)
Set TCNT_4 and TCNT_3 offset
value (dead time value)
Maskable by BSC/BCR1
setting*
Timer cycle data register
(TCDR)
Set TCNT_4 upper limit value
(1/2 carrier cycle)
Maskable by BSC/BCR1
setting*
Timer cycle buffer register
(TCBR)
TCDR buffer register
Always readable/writable
Subcounter (TCNTS)
Subcounter for dead time
generation
Read-only
Temporary register 1 (TEMP1)
Temporary register 2 (TEMP2)
Temporary register 3 (TEMP3)
PWM output 1/TGRB_3
temporary register
Not readable/writable
Not readable/writable
Not readable/writable
PWM output 2/TGRA_4
temporary register
PWM output 3/TGRB_4
temporary register
Note:
*
Access can be enabled or disabled according to the setting of bit 13 (MTURWE) in
BSC/BCR1 (bus controller/bus control register 1).
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8. Multi-Function Timer Pulse Unit (MTU)
TGRC_3
TGRA_3
TCBR
TCDR
TDDR
PWM cycle
output
Comparator
Match
signal
PWM output 1
PWM output 2
PWM output 3
PWM output 4
PWM output 5
PWM output 6
TCNT_3
TCNTS
TCNT_4
Comparator
Match
signal
External cutoff
input
POE0
POE1
POE2
POE3
TGRD_3
TGRC_4
TGRD_4
External cutoff
interrupt
: Registers that can always be read or written from the CPU
: Registers that can be read or written from the CPU
(but for which access disabling can be set by the bus controller)
: Registers that cannot be read or written from the CPU
(except for TCNTS, which can only be read)
Figure 8.32 Block Diagram of Channels 3 and 4 in Complementary PWM Mode
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8. Multi-Function Timer Pulse Unit (MTU)
Example of Complementary PWM Mode Setting Procedure: An example of the
complementary PWM mode setting procedure is shown in figure 8.33.
1. Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter
(TCNT) operation. Perform complementary PWM mode setting when TCNT_3 and TCNT_4
are stopped.
2. Set the same counter clock and clock edge for channels 3 and 4 with bits TPSC2 to TPSC0 and
bits CKEG1 and CKEG0 in the timer control register (TCR). Use bits CCLR2 to CCLR0 to set
synchronous clearing only when restarting by a synchronous clear from another channel during
complementary PWM mode operation.
3. When performing brushless DC motor control, set bit BDC in the timer gate control register
(TGCR) and set the feedback signal input source and output chopping or gate signal direct
output.
4. Set the dead time in TCNT_3. Set TCNT_4 to H'0000.
5. Set only when restarting by a synchronous clear from another channel during complementary
PWM mode operation. In this case, synchronize the channel generating the synchronous clear
with channels 3 and 4 using the timer synchro register (TSYR).
6. Set the output PWM duty cycle in the duty cycle registers (TGRB_3, TGRA_4, TGRB_4) and
buffer registers (TGRD_3, TGRC_4, TGRD_4). Set the same initial value in each
corresponding TGR.
7. Set the dead time in the dead time register (TDDR), 1/2 the carrier cycle in the carrier cycle
data register (TCDR) and carrier cycle buffer register (TCBR), and 1/2 the carrier cycle plus
the dead time in TGRA_3 and TGRC_3.
8. Select enabling/disabling of toggle output synchronized with the PWM cycle using bit PSYE
in the timer output control register (TOCR), and set the PWM output level with bits OLSP and
OLSN.
9. Select complementary PWM mode in timer mode register 3 (TMDR_3). Pins TIOC3A,
TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D function as output pins*. Do
not set in TMDR_4.
10. Set enabling/disabling of PWM waveform output pin output in the timer output master enable
register (TOER).
11. Set bits CST3 and CST4 in TSTR to 1 simultaneously to start the count operation.
Note: * PFC registers should be specified before this procedure.
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8. Multi-Function Timer Pulse Unit (MTU)
Complementary PWM mode
Stop count operation
1
Counter clock, counter clear
source selection
2
3
Brushless DC motor control
setting
TCNT setting
4
5
6
Inter-channel synchronization
setting
TGR setting
Dead time, carrier cycle
setting
7
8
PWM cycle output enabling,
PWM output level setting
Complementary PWM mode
setting
9
Enable waveform output
Start count operation
10
11
<Complementary PWM mode>
Figure 8.33 Example of Complementary PWM Mode Setting Procedure
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8. Multi-Function Timer Pulse Unit (MTU)
Outline of Complementary PWM Mode Operation
In complementary PWM mode, 6-phase PWM output is possible. Figure 8.34 illustrates counter
operation in complementary PWM mode, and figure 8.35 shows an example of complementary
PWM mode operation.
Counter Operation: In complementary PWM mode, three counters⎯TCNT_3, TCNT_4, and
TCNTS⎯perform up/down-count operations.
TCNT_3 is automatically initialized to the value set in TDDR when complementary PWM mode
is selected and the CST bit in TSTR is 0.
When the CST bit is set to 1, TCNT_3 counts up to the value set in TGRA_3, then switches to
down-counting when it matches TGRA_3. When the TCNT_3 value matches TDDR, the counter
switches to up-counting, and the operation is repeated in this way.
TCNT_4 is initialized to H'0000.
When the CST bit is set to 1, TCNT_4 counts up in synchronization with TCNT_3, and switches
to down-counting when it matches TCDR. On reaching H'0000, TCNT_4 switches to up-counting,
and the operation is repeated in this way.
TCNTS is a read-only counter. It need not be initialized.
When TCNT_3 matches TCDR during TCNT_3 and TCNT_4 up/down-counting, down-counting
is started, and when TCNTS matches TCDR, the operation switches to up-counting. When
TCNTS matches TGRA_3, it is cleared to H'0000.
When TCNT_4 matches TDDR during TCNT_3 and TCNT_4 down-counting, up-counting is
started, and when TCNTS matches TDDR, the operation switches to down-counting. When
TCNTS reaches H'0000, it is set with the value in TGRA_3.
TCNTS is compared with the compare register and temporary register in which the PWM duty
cycle is set during the count operation only.
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8. Multi-Function Timer Pulse Unit (MTU)
TCNT_3
TCNT_4
TCNTS
Counter value
TGRA_3
TCDR
TCNT_3
TCNT_4
TCNTS
TDDR
H'0000
Time
Figure 8.34 Complementary PWM Mode Counter Operation
Register Operation: In complementary PWM mode, nine registers are used, comprising compare
registers, buffer registers, and temporary registers. Figure 8.35 shows an example of
complementary PWM mode operation.
The registers which are constantly compared with the counters to perform PWM output are
TGRB_3, TGRA_4, and TGRB_4. When these registers match the counter, the value set in bits
OLSN and OLSP in the timer output control register (TOCR) is output.
The buffer registers for these compare registers are TGRD_3, TGRC_4, and TGRD_4.
Between a buffer register and compare register there is a temporary register. The temporary
registers cannot be accessed by the CPU.
Data in a compare register is changed by writing the new data to the corresponding buffer register.
The buffer registers can be read or written at any time.
The data written to a buffer register is constantly transferred to the temporary register in the Ta
interval. Data is not transferred to the temporary register in the Tb interval. Data written to a
buffer register in this interval is transferred to the temporary register at the end of the Tb interval.
The value transferred to a temporary register is transferred to the compare register when TCNTS
for which the Tb interval ends matches TGRA_3 when counting up, or H'0000 when counting
down. The timing for transfer from the temporary register to the compare register can be selected
with bits MD3 to MD0 in the timer mode register (TMDR). Figure 8.35 shows an example in
which the mode is selected in which the change is made in the trough.
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8. Multi-Function Timer Pulse Unit (MTU)
In the Tb interval (Tb1 in figure 8.35) in which data transfer to the temporary register is not
performed, the temporary register has the same function as the compare register, and is compared
with the counter. In this interval, therefore, there are two compare match registers for one-phase
output, with the compare register containing the pre-change data, and the temporary register
containing the new data. In this interval, the three counters⎯TCNT_3, TCNT_4, and
TCNTS⎯and two registers⎯compare register and temporary register⎯are compared, and PWM
output controlled accordingly.
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8. Multi-Function Timer Pulse Unit (MTU)
Transfer from temporary
Transfer from temporary
register to compare register
register to compare register
Tb2
Ta
Tb1
Ta
Tb2
Ta
TGRA_3
TCDR
TCNTS
TCNT_3
TCNT_4
TGRA_4
TGRC_4
TDDR
H'0000
Buffer register
TGRC_4
H'6400
H'6400
H'0080
Temporary register
TEMP2
H'0080
Compare register
TGRA_4
H'6400
H'0080
Output waveform
Output waveform
(Output waveform is active-low)
Figure 8.35 Example of Complementary PWM Mode Operation
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8. Multi-Function Timer Pulse Unit (MTU)
Initialization: In complementary PWM mode, there are six registers that must be initialized.
Before setting complementary PWM mode with bits MD3 to MD0 in the timer mode register
(TMDR), the following initial register values must be set.
TGRC_3 operates as the buffer register for TGRA_3, and should be set with 1/2 the PWM carrier
cycle + dead time Td. The timer cycle buffer register (TCBR) operates as the buffer register for
the timer cycle data register (TCDR), and should be set with 1/2 the PWM carrier cycle. Set dead
time Td in the timer dead time data register (TDDR).
Set the respective initial PWM duty cycle values in buffer registers TGRD_3, TGRC_4, and
TGRD_4.
The values set in the five buffer registers excluding TDDR are transferred simultaneously to the
corresponding compare registers when complementary PWM mode is set.
Set TCNT_4 to H'0000 before setting complementary PWM mode.
Table 8.41 Registers and Counters Requiring Initialization
Register/Counter
TGRC_3
Set Value
1/2 PWM carrier cycle + dead time Td
Dead time Td
TDDR
TCBR
1/2 PWM carrier cycle
Initial PWM duty cycle value for each phase
H'0000
TGRD_3, TGRC_4, TGRD_4
TCNT_4
Note: The TGRC_3 set value must be the sum of 1/2 the PWM carrier cycle set in TCBR and
dead time Td set in TDDR.
PWM Output Level Setting: In complementary PWM mode, the PWM pulse output level is set
with bits OLSN and OLSP in the timer output control register (TOCR).
The output level can be set for each of the three positive phases and three negative phases of 6-
phase output.
Complementary PWM mode should be cleared before setting or changing output levels.
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8. Multi-Function Timer Pulse Unit (MTU)
Dead Time Setting: In complementary PWM mode, PWM pulses are output with a non-
overlapping relationship between the positive and negative phases. This non-overlap time is called
the dead time.
The non-overlap time is set in the timer dead time data register (TDDR). The value set in TDDR is
used as the TCNT_3 counter start value, and creates non-overlap between TCNT_3 and TCNT_4.
Complementary PWM mode should be cleared before changing the contents of TDDR.
PWM Cycle Setting: In complementary PWM mode, the PWM pulse cycle is set in two
registers⎯TGRA_3, in which the TCNT_3 upper limit value is set, and TCDR, in which the
TCNT_4 upper limit value is set. The settings should be made so as to achieve the following
relationship between these two registers:
TGRA_3 set value = TCDR set value + TDDR set value
The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3 and
TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3 and
TCDR in accordance with the transfer timing selected with bits MD3 to MD0 in the timer mode
register (TMDR).
The updated PWM cycle is reflected from the next cycle when the data update is performed at the
crest, and from the current cycle when performed in the trough. Figure 8.36 illustrates the
operation when the PWM cycle is updated at the crest.
See the following section, Register data updating, for the method of updating the data in each
buffer register.
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8. Multi-Function Timer Pulse Unit (MTU)
TGRC_3
update
TGRA_3
update
Counter value
TCNT_3
TCNT_4
TGRA_3
Time
Figure 8.36 Example of PWM Cycle Updating
Register Data Updating: In complementary PWM mode, the buffer register is used to update the
data in a compare register. The update data can be written to the buffer register at any time. There
are five PWM duty cycle and carrier cycle registers that have buffer registers and can be updated
during operation.
There is a temporary register between each of these registers and its buffer register. When
subcounter TCNTS is not counting, if buffer register data is updated, the temporary register value
is also rewritten. Transfer is not performed from buffer registers to temporary registers when
TCNTS is counting; in this case, the value written to a buffer register is transferred after TCNTS
halts.
The temporary register value is transferred to the compare register at the data update timing set
with bits MD3 to MD0 in the timer mode register (TMDR). Figure 8.37 shows an example of data
updating in complementary PWM mode. This example shows the mode in which data updating is
performed at both the counter crest and trough.
When rewriting buffer register data, a write to TGRD_4 must be performed at the end of the
update. Data transfer from the buffer registers to the temporary registers is performed
simultaneously for all five registers after the write to TGRD_4.
A write to TGRD_4 must be performed after writing data to the registers to be updated, even when
not updating all five registers, or when updating the TGRD_4 data. In this case, the data written to
TGRD_4 should be the same as the data prior to the write operation.
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8. Multi-Function Timer Pulse Unit (MTU)
Figure 8.37 Example of Data Update in Complementary PWM Mode
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8. Multi-Function Timer Pulse Unit (MTU)
Initial Output in Complementary PWM Mode: In complementary PWM mode, the initial
output is determined by the setting of bits OLSN and OLSP in the timer output control register
(TOCR).
This initial output is the PWM pulse non-active level, and is output from when complementary
PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set in
the dead time register (TDDR). Figure 8.38 shows an example of the initial output in
complementary PWM mode.
An example of the waveform when the initial PWM duty cycle value is smaller than the TDDR
value is shown in figure 8.39.
Timer output control register settings
OLSN bit: 0 (initial output: high; active level: low)
OLSP bit: 0 (initial output: high; active level: low)
TCNT_3, 4 value
TCNT_3
TCNT_4
TGR4_A
TDDR
Time
Initial output
Dead time
Positive phase
output
Active level
Negative phase
output
Active level
Complementary
PWM mode
TCNT_3, 4 count start
(TSTR setting)
(TMDR setting)
Figure 8.38 Example of Initial Output in Complementary PWM Mode (1)
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8. Multi-Function Timer Pulse Unit (MTU)
Timer output control register settings
OLSN bit: 0 (initial output: high; active level: low)
OLSP bit: 0 (initial output: high; active level: low)
TCNT_3, 4 value
TCNT_3
TCNT_4
TDDR
TGR_4
Time
Initial output
Positive phase
Active level
output
Negative phase
output
Complementary
PWM mode
TCNT_3, 4 count start
(TSTR setting)
(TMDR setting)
Figure 8.39 Example of Initial Output in Complementary PWM Mode (2)
Complementary PWM Mode PWM Output Generation Method: In complementary PWM
mode, 3-phase output is performed of PWM waveforms with a non-overlap time between the
positive and negative phases. This non-overlap time is called the dead time.
A PWM waveform is generated by output of the output level selected in the timer output control
register in the event of a compare-match between a counter and data register. While TCNTS is
counting, data register and temporary register values are simultaneously compared to create
consecutive PWM pulses from 0 to 100%. The relative timing of on and off compare-match
occurrence may vary, but the compare-match that turns off each phase takes precedence to secure
the dead time and ensure that the positive phase and negative phase on times do not overlap.
Figures 8.40 to 8.42 show examples of waveform generation in complementary PWM mode.
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8. Multi-Function Timer Pulse Unit (MTU)
The positive phase/negative phase off timing is generated by a compare-match with the solid-line
counter, and the on timing by a compare-match with the dotted-line counter operating with a delay
of the dead time behind the solid-line counter. In the T1 period, compare-match a that turns off the
negative phase has the highest priority, and compare-matches occurring prior to a are ignored. In
the T2 period, compare-match c that turns off the positive phase has the highest priority, and
compare-matches occurring prior to c are ignored.
In normal cases, compare-matches occur in the order a → b → c → d (or c → d → a' → b'), as
shown in figure 8.40.
If compare-matches deviate from the a → b → c → d order, since the time for which the negative
phase is off is less than twice the dead time, the figure shows the positive phase is not being turned
on. If compare-matches deviate from the c → d → a' → b' order, since the time for which the
positive phase is off is less than twice the dead time, the figure shows the negative phase is not
being turned on.
If compare-match c occurs first following compare-match a, as shown in figure 8.41, compare-
match b is ignored, and the negative phase is turned off by compare-match d. This is because
turning off of the positive phase has priority due to the occurrence of compare-match c (positive
phase off timing) before compare-match b (positive phase on timing) (consequently, the waveform
does not change since the positive phase goes from off to off).
Similarly, in the example in figure 8.42, compare-match a' with the new data in the temporary
register occurs before compare-match c, but other compare-matches occurring up to c, which turns
off the positive phase, are ignored. As a result, the positive phase is not turned on.
Thus, in complementary PWM mode, compare-matches at turn-off timings take precedence, and
turn-on timing compare-matches that occur before a turn-off timing compare-match are ignored.
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8. Multi-Function Timer Pulse Unit (MTU)
T2 period
T1 period
T1 period
TGR3A_3
TCDR
c
d
a
b
a'
b'
TDDR
H'0000
Positive phase
Negative phase
Figure 8.40 Example of Complementary PWM Mode Waveform Output (1)
T2 period
T1 period
T1 period
TGRA_3
TCDR
c
d
a
b
a
b
TDDR
H'0000
Positive phase
Negative phase
Figure 8.41 Example of Complementary PWM Mode Waveform Output (2)
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8. Multi-Function Timer Pulse Unit (MTU)
T1 period
TGRA_3
T2 period
T1 period
TCDR
a
b
TDDR
c
d
a'
b'
H'0000
Positive phase
Negative phase
Figure 8.42 Example of Complementary PWM Mode Waveform Output (3)
T1 period
T2 period
T1 period
c
d
TGRA_3
TCDR
a
b
a'
b'
TDDR
H'0000
Positive phase
Negative phase
Figure 8.43 Example of Complementary PWM Mode 0% and 100% Waveform Output (1)
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8. Multi-Function Timer Pulse Unit (MTU)
T1 period
T2 period
T1 period
TGRA_3
TCDR
a
b
a
b
TDDR
H'0000
c
d
Positive phase
Negative phase
Figure 8.44 Example of Complementary PWM Mode 0% and 100% Waveform Output (2)
T1 period
T2 period
T1 period
c
d
TGRA_3
TCDR
a
b
TDDR
H'0000
Positive phase
Negative phase
Figure 8.45 Example of Complementary PWM Mode 0% and 100% Waveform Output (3)
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8. Multi-Function Timer Pulse Unit (MTU)
T1 period
T2 period
T1 period
TGRA_3
TCDR
a
b
TDDR
H'0000
c b'
d a'
Positive phase
Negative phase
Figure 8.46 Example of Complementary PWM Mode 0% and 100% Waveform Output (4)
T1 period
T2 period
T1 period
c
a d
b
TGRA_3
TCDR
TDDR
H'0000
Positive phase
Negative phase
Figure 8.47 Example of Complementary PWM Mode 0% and 100% Waveform Output (5)
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8. Multi-Function Timer Pulse Unit (MTU)
Complementary PWM Mode 0% and 100% Duty Cycle Output: In complementary PWM
mode, 0% and 100% duty cycles can be output as required. Figures 8.43 to 8.47 show output
examples.
100% duty cycle output is performed when the data register value is set to H'0000. The waveform
in this case has a positive phase with a 100% on-state. 0% duty cycle output is performed when
the data register value is set to the same value as TGRA_3. The waveform in this case has a
positive phase with a 100% off-state.
On and off compare-matches occur simultaneously, but if a turn-on compare-match and turn-off
compare-match for the same phase occur simultaneously, both compare-matches are ignored and
the waveform does not change.
Toggle Output Synchronized with PWM Cycle: In complementary PWM mode, toggle output
can be performed in synchronization with the PWM carrier cycle by setting the PSYE bit to 1 in
the timer output control register (TOCR). An example of a toggle output waveform is shown in
figure 8.48.
This output is toggled by a compare-match between TCNT_3 and TGRA_3 and a compare-match
between TCNT4 and H'0000.
The output pin for this toggle output is the TIOC3A pin. The initial output is 1.
TGRA_3
TCNT_3
TCNT_4
H'0000
Toggle output
TIOC3A pin
Figure 8.48 Example of Toggle Output Waveform Synchronized with PWM Output
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Counter Clearing by another Channel: In complementary PWM mode, by setting a mode for
synchronization with another channel by means of the timer synchro register (TSYR), and
selecting synchronous clearing with bits CCLR2 to CCLR0 in the timer control register (TCR), it
is possible to have TCNT_3, TCNT_4, and TCNTS cleared by another channel.
Figure 8.49 illustrates the operation.
Use of this function enables counter clearing and restarting to be performed by means of an
external signal.
TCNTS
TGRA_3
TCDR
TCNT_3
TCNT_4
TDDR
H'0000
Channel 1
Input capture A
TCNT_1
Synchronous counter clearing by channel 1 input capture A
Figure 8.49 Counter Clearing Synchronized with Another Channel
Example of AC Synchronous Motor (Brushless DC Motor) Drive Waveform Output: In
complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate
control register (TGCR). Figures 8.50 to 8.53 show examples of brushless DC motor drive
waveforms created using TGCR.
When output phase switching for a 3-phase brushless DC motor is performed by means of external
signals detected with a Hall element, etc., clear the FB bit in TGCR to 0. In this case, the external
signals indicating the polarity position are input to channel 0 timer input pins TIOC0A, TIOC0B,
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and TIOC0C (set with PFC). When an edge is detected at pin TIOC0A, TIOC0B, or TIOC0C, the
output on/off state is switched automatically.
When the FB bit is 1, the output on/off state is switched when the UF, VF, or WF bit in TGCR is
cleared to 0 or set to 1.
The drive waveforms are output from the complementary PWM mode 6-phase output pins. With
this 6-phase output, in the case of on output, it is possible to use complementary PWM mode
output and perform chopping output by setting the N bit or P bit to 1. When the N bit or P bit is 0,
level output is selected.
The 6-phase output active level (on output level) can be set with the OLSN and OLSP bits in the
timer output control register (TOCR) regardless of the setting of the N and P bits.
External input
TIOC0A pin
TIOC0B pin
TIOC0C pin
TIOC3B pin
TIOC3D pin
6-phase output
TIOC4A pin
TIOC4C pin
TIOC4B pin
TIOC4D pin
When BDC = 1, N = 0, P = 0, FB = 0, output active level = high
Figure 8.50 Example of Output Phase Switching by External Input (1)
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8. Multi-Function Timer Pulse Unit (MTU)
External input
TIOC0A pin
TIOC0B pin
TIOC0C pin
6-phase output TIOC3B pin
TIOC3D pin
TIOC4A pin
TIOC4C pin
TIOC4B pin
TIOC4D pin
When BDC = 1, N = 1, P = 1, FB = 0, output active level = high
Figure 8.51 Example of Output Phase Switching by External Input (2)
TGCR
UF bit
VF bit
WF bit
6-phase output
TIOC3B pin
TIOC3D pin
TIOC4A pin
TIOC4C pin
TIOC4B pin
TIOC4D pin
When BDC = 1, N = 0, P = 0, FB = 1, output active level = high
Figure 8.52 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1)
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8. Multi-Function Timer Pulse Unit (MTU)
TGCR
UF bit
VF bit
WF bit
6-phase output TIOC3B pin
TIOC3D pin
TIOC4A pin
TIOC4C pin
TIOC4B pin
TIOC4D pin
When BDC = 1, N = 1, P = 1, FB = 1, output active level = high
Figure 8.53 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2)
A/D Conversion Start Request Setting: In complementary PWM mode, an A/D conversion start
request can be set using a TGRA_3 compare-match or a compare-match on a channel other than
channels 3 and 4.
When start requests using a TGRA_3 compare-match are set, A/D conversion can be started at the
center of the PWM pulse.
A/D conversion start requests can be set by setting the TTGE bit to 1 in the timer interrupt enable
register (TIER).
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8. Multi-Function Timer Pulse Unit (MTU)
Complementary PWM Mode Output Protection Function
Complementary PWM mode output has the following protection functions.
•
Register and counter miswrite prevention function
With the exception of the buffer registers, which can be rewritten at any time, access by the
CPU can be enabled or disabled for the mode registers, control registers, compare registers,
and counters used in complementary PWM mode by means of bit 13 in the bus controller's bus
control register 1 (BCR1). Some registers in channels 3 and 4 concerned are listed below: total
21 registers of TCR_3 and TCR_4; TMDR_3 and TMDR_4; TIORH_3 and TIORH_4;
TIORL_3 and TIORL_4; TIER_3 and TIER_4; TCNT_3 and TCNT_4; TGRA_3 and
TGRA_4; TGRB_3 and TGRB_4; TOER; TOCR; TGCR; TCDR; and TDDR. This function
enables the CPU to prevent miswriting due to the CPU runaway by disabling CPU access to
the mode registers, control registers, and counters. In access disabled state, an undefined value
is read from the registers concerned, and cannot be modified.
•
•
Halting of PWM output by external signal
The 6-phase PWM output pins can be set automatically to the high-impedance state by
inputting specified external signals. There are four external signal input pins.
See section 8.9, Port Output Enable (POE), for details.
Halting of PWM output when oscillator is stopped
If it is detected that the clock input to this LSI has stopped, the 6-phase PWM output pins
automatically go to the high-impedance state. The pin states are not guaranteed when the clock
is restarted.
For details, see section 4.2, Function for Detecting Oscillator Halt.
8.5
Interrupt Sources
8.5.1
Interrupts and Priorities
There are three kinds of MTU interrupt source; TGR input capture/compare match, TCNT
overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled
bit, allowing the generation of interrupt request signals to be enabled or disabled individually.
When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the
corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Relative channel priorities can be changed by the interrupt controller, however the priority order
within a channel is fixed. For details, see section 6, Interrupt Controller (INTC).
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Table 8.42 lists the MTU interrupt sources.
Table 8.42 MTU Interrupts
Channel Name
Interrupt Source
Interrupt Flag
TGFA_0
TGFB_0
TGFC_0
TGFD_0
TCFV_0
TGFA_1
TGFB_1
TCFV_1
TCFU_1
TGFA_2
TGFB_2
TCFV_2
TCFU_2
TGFA_3
TGFB_3
TGFC_3
TGFD_3
TCFV_3
TGFA_4
TGFB_4
TGFC_4
TGFD_4
TCFV_4
Priority
0
TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
TGI1A
TGI1B
TCI1V
TCI1U
TGI2A
TGI2B
TCI2V
TCI2U
TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
TGI4A
TGI4B
TGI4C
TGI4D
TCI4V
TGRA_0 input capture/compare match
TGRB_0 input capture/compare match
TGRC_0 input capture/compare match
TGRD_0 input capture/compare match
TCNT_0 overflow
High
1
2
3
TGRA_1 input capture/compare match
TGRB_1 input capture/compare match
TCNT_1 overflow
TCNT_1 underflow
TGRA_2 input capture/compare match
TGRB_2 input capture/compare match
TCNT_2 overflow
TCNT_2 underflow
TGRA_3 input capture/compare match
TGRB_3 input capture/compare match
TGRC_3 input capture/compare match
TGRD_3 input capture/compare match
TCNT_3 overflow
4
TGRA_4 input capture/compare match
TGRB_4 input capture/compare match
TGRC_4 input capture/compare match
TGRD_4 input capture/compare match
TCNT_4 overflow
Low
Note: This table shows the initial state immediately after a reset. The relative channel priorities
can be changed by the interrupt controller.
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8. Multi-Function Timer Pulse Unit (MTU)
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is
set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare
match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The
MTU has 16 input capture/compare match interrupts, four each for channels 0, 3, and 4, and two
each for channels 1 and 2.
Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the
TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt
request is cleared by clearing the TCFV flag to 0. The MTU has five overflow interrupts, one for
each channel.
Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the
TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt
request is cleared by clearing the TCFU flag to 0. The MTU has two underflow interrupts, one
each for channels 1 and 2.
8.5.2
A/D Converter Activation
The A/D converter can be activated by the TGRA input capture/compare match in each channel.
If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a
TGRA input capture/compare match on a particular channel, a request to start A/D conversion is
sent to the A/D converter. If the MTU conversion start trigger has been selected on the A/D
converter at this time, A/D conversion starts.
In the MTU, a total of five TGRA input capture/compare match interrupts can be used as A/D
converter conversion start sources, one for each channel.
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8. Multi-Function Timer Pulse Unit (MTU)
8.6
Operation Timing
8.6.1
Input/Output Timing
TCNT Count Timing: Figure 8.54 shows TCNT count timing in internal clock operation, and
figure 8.55 shows TCNT count timing in external clock operation (normal mode), and figure 8.56
shows TCNT count timing in external clock operation (phase counting mode).
Pφ
Falling edge
Rising edge
Internal clock
TCNT input
clock
N-1
N
N+1
N+2
TCNT
Figure 8.54 Count Timing in Internal Clock Operation
Pφ
Falling edge
Rising edge
Falling edge
External clock
TCNT input
clock
TCNT
N-1
N
N+1
N+2
Figure 8.55 Count Timing in External Clock Operation
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8. Multi-Function Timer Pulse Unit (MTU)
Pφ
External
clock
Falling edge
Rising edge
Falling edge
TCNT input
clock
N
TCNT
N+1
N-1
Figure 8.56 Count Timing in External Clock Operation (Phase Counting Mode)
Output Compare Output Timing: A compare match signal is generated in the final state in
which TCNT and TGR match (the point at which the count value matched by TCNT is updated).
When a compare match signal is generated, the output value set in TIOR is output at the output
compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match
signal is not generated until the TCNT input clock is generated.
Figure 8.57 shows output compare output timing (normal mode and PWM mode) and figure 8.58
shows output compare output timing (complementary PWM mode and reset synchronous PWM
mode).
Pφ
TCNT input
clock
N
N
N+1
TCNT
TGR
Compare
match signal
TIOC pin
Figure 8.57 Output Compare Output Timing (Normal Mode/PWM Mode)
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8. Multi-Function Timer Pulse Unit (MTU)
Pφ
TCNT input
clock
N+1
N
N
TCNT
TGR
Compare
match signal
TIOC pin
Figure 8.58 Output Compare Output Timing
(Complementary PWM Mode/Reset Synchronous PWM Mode)
Input Capture Signal Timing: Figure 8.59 shows input capture signal timing.
Pφ
Input capture
input
Input capture
signal
N
N+1
N+2
TCNT
TGR
N
N+2
Figure 8.59 Input Capture Input Signal Timing
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8. Multi-Function Timer Pulse Unit (MTU)
Timing for Counter Clearing by Compare Match/Input Capture: Figure 8.60 shows the
timing when counter clearing on compare match is specified, and figure 8.61 shows the timing
when counter clearing on input capture is specified.
Pφ
Compare
match signal
Counter
clear signal
N
N
H'0000
TCNT
TGR
Figure 8.60 Counter Clear Timing (Compare Match)
Pφ
Input capture
signal
Counter clear
signal
N
H'0000
N
TCNT
TGR
Figure 8.61 Counter Clear Timing (Input Capture)
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8. Multi-Function Timer Pulse Unit (MTU)
Buffer Operation Timing: Figures 8.62 and 8.63 show the timing in buffer operation.
Pφ
TCNT
n
n+1
Compare
match signal
TGRA,
TGRB
n
N
TGRC,
TGRD
N
Figure 8.62 Buffer Operation Timing (Compare Match)
Pφ
Input capture
signal
N
n
N+1
TCNT
TGRA,
TGRB
N
n
N+1
N
TGRC,
TGRD
Figure 8.63 Buffer Operation Timing (Input Capture)
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8. Multi-Function Timer Pulse Unit (MTU)
8.6.2 Interrupt Signal Timing
TGF Flag Setting Timing in Case of Compare Match: Figure 8.64 shows the timing for setting
of the TGF flag in TSR on compare match, and TGI interrupt request signal timing.
Pφ
TCNT input
clock
TCNT
TGR
N
N
N+1
Compare
match signal
TGF flag
TGI interrupt
Figure 8.64 TGI Interrupt Timing (Compare Match)
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8. Multi-Function Timer Pulse Unit (MTU)
TGF Flag Setting Timing in Case of Input Capture: Figure 8.65 shows the timing for setting of
the TGF flag in TSR on input capture, and TGI interrupt request signal timing.
Pφ
Input capture
signal
TCNT
N
TGR
N
TGF flag
TGI interrupt
Figure 8.65 TGI Interrupt Timing (Input Capture)
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8. Multi-Function Timer Pulse Unit (MTU)
TCFV Flag/TCFU Flag Setting Timing: Figure 8.66 shows the timing for setting of the TCFV
flag in TSR on overflow, and TCIV interrupt request signal timing.
Figure 8.67 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU
interrupt request signal timing.
Pφ
TCNT input
clock
TCNT
(overflow)
H'FFFF
H'0000
Overflow
signal
TCFV flag
TCIV interrupt
Figure 8.66 TCIV Interrupt Setting Timing
Pφ
TCNT
input clock
TCNT
(underflow)
H'0000
H'FFFF
Underflow
signal
TCFU flag
TCIU interrupt
Figure 8.67 TCIU Interrupt Setting Timing
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8. Multi-Function Timer Pulse Unit (MTU)
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC is activated, the flag is cleared automatically. Figure 8.68 shows the timing
for status flag clearing by the CPU.
TSR write cycle
T1
T2
Pφ
TSR address
Address
Write signal
Status flag
Interrupt
request signal
Figure 8.68 Timing for Status Flag Clearing by the CPU
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8. Multi-Function Timer Pulse Unit (MTU)
8.7
Usage Notes
8.7.1
Module Standby Mode Setting
MTU operation can be disabled or enabled using the module standby register. The initial setting is
for MTU operation to be halted. Register access is enabled by clearing module standby mode. For
details, refer to section 17, Power-Down Modes.
8.7.2
Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower
pulse widths.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 8.69 shows the input clock
conditions in phase counting mode.
Phase
differ-
ence
Phase
differ-
ence
Pulse width
Pulse width
Overlap
Overlap
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Pulse width
Pulse width
Notes: Phase difference and overlap : 1.5 states or more
Pulse width : 2.5 states or more
Figure 8.69 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
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8. Multi-Function Timer Pulse Unit (MTU)
8.7.3
Caution on Period Setting
When counter clearing on compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
Pφ
f =
(N + 1)
Where
f
: Counter frequency
Pφ : Peripheral clock operating frequency
: TGR set value
N
8.7.4
Contention between TCNT Write and Clear Operations
If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing
takes precedence and the TCNT write is not performed.
Figure 8.70 shows the timing in this case.
TCNT write cycle
T1
T2
Pφ
TCNT address
Address
Write signal
Counter clear
signal
N
H'0000
TCNT
Figure 8.70 Contention between TCNT Write and Clear Operations
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8. Multi-Function Timer Pulse Unit (MTU)
8.7.5 Contention between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented.
Figure 8.71 shows the timing in this case.
TCNT write cycle
T1
T2
Pφ
TCNT address
Address
Write signal
TCNT input
clock
N
M
TCNT
TCNT write data
Figure 8.71 Contention between TCNT Write and Increment Operations
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8. Multi-Function Timer Pulse Unit (MTU)
Contention between TGR Write and Compare Match
8.7.6
When a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed
and the compare match signal is generated.
Figure 8.72 shows the timing in this case.
TGR write cycle
T1
T2
Pφ
TGR address
Address
Write signal
Compare
match signal
TCNT
TGR
N
N
N + 1
M
TGR write data
Figure 8.72 Contention between TGR Write and Compare Match
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8. Multi-Function Timer Pulse Unit (MTU)
8.7.7 Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR
by the buffer operation differs depending on channel 0 and channels 3 and 4: data on channel 0 is
that after write, and on channels 3 and 4, before write.
Figures 8.73 and 8.74 show the timing in this case.
TGR write cycle
T1
T2
Pφ
Buffer register
address
Address
Write signal
Compare
match signal
Compare
match buffer
signal
Buffer register write data
N
M
M
Buffer register
TGR
Figure 8.73 Contention between Buffer Register Write and Compare Match (Channel 0)
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8. Multi-Function Timer Pulse Unit (MTU)
TGR write cycle
T1
T2
Pφ
Buffer register
address
Address
Write signal
Compare match
signal
Compare match
buffer signal
Buffer register write data
N
M
N
Buffer register
TGR
Figure 8.74 Contention between Buffer Register Write and Compare Match
(Channels 3 and 4)
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8. Multi-Function Timer Pulse Unit (MTU)
8.7.8 Contention between TGR Read and Input Capture
If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be that in the buffer after input capture transfer.
Figure 8.75 shows the timing in this case.
TGR read cycle
T1
T2
Pφ
Address
TGR address
Read signal
Input capture
signal
X
M
TGR
M
Internal data bus
Figure 8.75 Contention between TGR Read and Input Capture
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8. Multi-Function Timer Pulse Unit (MTU)
Contention between TGR Write and Input Capture
8.7.9
If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 8.76 shows the timing in this case.
TGR write cycle
T1
T2
Pφ
TGR address
Address
Write signal
Input capture
signal
TCNT
TGR
M
M
Figure 8.76 Contention between TGR Write and Input Capture
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8. Multi-Function Timer Pulse Unit (MTU)
8.7.10 Contention between Buffer Register Write and Input Capture
If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 8.77 shows the timing in this case.
Buffer register write cycle
T1
T2
Pφ
Buffer register
address
Address
Write signal
Input capture
signal
TCNT
N
M
N
TGR
Buffer register
M
Figure 8.77 Contention between Buffer Register Write and Input Capture
TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection
8.7.11
With timer counters TCNT_1 and TCNT_2 in a cascade connection, when a contention occurs
during TCNT_1 count (during a TCNT_2 overflow/underflow) in the T2 state of the TCNT_2
write cycle, the write to TCNT_2 is conducted, and the TCNT_1 count signal is disabled. At this
point, if there is match with TGRA_1 and the TCNT_1 value, a compare signal is issued.
Furthermore, when the TCNT_1 count clock is selected as the input capture source of channel 0,
TGRA_0 to D_0 carry out the input capture operation. In addition, when the compare match/input
capture is selected as the input capture source of TGRB_1, TGRB_1 carries out input capture
operation. The timing is shown in figure 8.78.
For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT
clearing.
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8. Multi-Function Timer Pulse Unit (MTU)
TCNT write cycle
T1 T2
Pφ
Address
TCNT_2 address
Write signal
TCNT_2
H'FFFE
H'FFFF
N
N + 1
TCNT_2 write data
TGR2A_2 to
TGR2B_2
H'FFFF
Ch2 compare-
match signal A/B
Disabled
TCNT_1 input
clock
TCNT_1
TGRA_1
M
M
Ch1 compare-
match signal A
TGRB_1
N
M
Ch1 input capture
signal B
TCNT_0
P
TGRA_0 to
TGRD_0
Q
P
Ch0 input capture
signal A to D
Figure 8.78 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection
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8. Multi-Function Timer Pulse Unit (MTU)
8.7.12 Counter Value during Complementary PWM Mode Stop
When counting operation is stopped with TCNT_3 and TCNT_4 in complementary PWM mode,
TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is set to H'0000.
When restarting complementary PWM mode, counting begins automatically from the initialized
state. This explanatory diagram is shown in figure 8.79.
When counting begins in another operating mode, be sure that TCNT_3 and TCNT_4 are set to
the initial values.
TGRA_3
TCDR
TCNT_3
TCNT_4
TDDR
H'0000
Complementary PWM
mode operation
Complementary PWM
mode operation
Complementary
PMW restart
Counter
operation stop
Figure 8.79 Counter Value during Complementary PWM Mode Stop
Buffer Operation Setting in Complementary PWM Mode
8.7.13
In complementary PWM mode, conduct rewrites by buffer operation for the PWM cycle setting
register (TGRA_3), timer cycle data register (TCDR), and duty cycle setting registers (TGRB_3,
TRGA_4, and TGRB_4).
In complementary PWM mode, channel 3 and channel 4 buffers operate in accordance with bit
settings BFA and BFB of TMDR_3. When TMDR_3's BFA bit is set to 1, TGRC_3 functions as a
buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for
TRGA_4, while the TCBR functions as the TCDR's buffer register.
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8. Multi-Function Timer Pulse Unit (MTU)
Reset Sync PWM Mode Buffer Operation and Compare Match Flag
8.7.14
When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits of TMDR_4
to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit of TMDR_4 is
set to 1.
In reset sync PWM mode, the channel 3 and channel 4 buffers operate in accordance with the BFA
and BFB bit settings of TMDR_3. For example, if the BFA bit of TMDR_3 is set to 1, TGRC_3
functions as the buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer
register for TRGA_4.
The TGFC bit and TGFD bit of TSR_3 and TSR_4 are not set when TGRC_3 and TGRD_3 are
operating as buffer registers.
Figure 8.80 shows an example of operations for TGR_3, TGR_4, TIOC3, and TIOC4, with
TMDR_3's BFA and BFB bits set to 1, and TMDR_4's BFA and BFB bits set to 0.
TGRA_3
TGRC_3
Buffer transfer with
compare match A3
TCNT3
Point a
TGRA_3,
TGRC_3
TGRB_3, TGRA_4,
TGRB_4
Point b
TGRD_3, TGRC_4,
TGRD_4
TGRB_3, TGRD_3,
TGRA_4, TGRC_4,
TGRB_4, TGRD_4
H'0000
TIOC3A
TIOC3B
TIOC3D
TIOC4A
TIOC4C
TIOC4B
TIOC4D
TGFC
Not set
TGFD
Not set
Figure 8.80 Buffer Operation and Compare-Match Flags in Reset Sync PWM Mode
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8. Multi-Function Timer Pulse Unit (MTU)
8.7.15 Overflow Flags in Reset Sync PWM Mode
When set to reset sync PWM mode, TCNT_3 and TCNT_4 start counting when the CST3 bit of
TSTR is set to 1. At this point, TCNT_4's count clock source and count edge obey the TCR_3
setting.
In reset sync PWM mode, with cycle register TGRA_3's set value at H'FFFF, when specifying
TGR3A compare-match for the counter clear source, TCNT_3 and TCNT_4 count up to H'FFFF,
then a compare-match occurs with TGRA_3, and TCNT_3 and TCNT_4 are both cleared. At this
point, TSR's overflow flag TCFV bit is not set.
Figure 8.81 shows a TCFV bit operation example in reset sync PWM mode with a set value for
cycle register TGRA_3 of H'FFFF, when a TGRA_3 compare-match has been specified without
synchronous setting for the counter clear source.
Counter cleared by compare match 3A
TGRA_3
(H'FFFF)
TCNT_3 = TCNT_4
H'0000
Not set
Not set
TCFV_3
TCFV_4
Figure 8.81 Reset Sync PWM Mode Overflow Flag
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8. Multi-Function Timer Pulse Unit (MTU)
Contention between Overflow/Underflow and Counter Clearing
8.7.16
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 8.82 shows the operation timing when a TGR compare match is specified as the clearing
source, and when H'FFFF is set in TGR.
Pφ
TCNT input
clock
TCNT
H'FFFF
H'0000
Counter clear
signal
TGF
Disabled
TCFV
Figure 8.82 Contention between Overflow and Counter Clearing
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8. Multi-Function Timer Pulse Unit (MTU)
8.7.17 Contention between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T2 state of a TCNT write cycle, and
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 8.83 shows the operation timing when there is contention between TCNT write and
overflow.
TCNT write cycle
T1
T2
Pφ
TCNT address
Address
Write signal
TCNT
TCNT write data
H'FFFF
M
TCFV flag
Figure 8.83 Contention between TCNT Write and Overflow
8.7.18
Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-
Synchronous PWM Mode
When making a transition from channel 3 or 4 normal operation or PWM mode 1 to reset-
synchronous PWM mode, if the counter is halted with the output pins (TIOC3B, TIOC3D,
TIOC4A, TIOC4C, TIOC4B, TIOC4D) in the high-impedance state, followed by the transition to
reset-synchronous PWM mode and operation in that mode, the initial pin output will not be correct.
When making a transition from normal operation to reset-synchronous PWM mode, write H'11 to
registers TIOR3_H, TIOR3_L, TIOR4_H, and TIOR4_L to initialize the output pins to low level
output, then set an initial register value of H'00 before making the mode transition.
When making a transition from PWM mode 1 to reset-synchronous PWM mode, first switch to
normal operation, then initialize the output pins to low level output and set an initial register value
of H'00 before making the transition to reset-synchronous PWM mode.
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8. Multi-Function Timer Pulse Unit (MTU)
8.7.19 Output Level in Complementary PWM Mode and Reset-Synchronous PWM Mode
When channels 3 and 4 are in complementary PWM mode or reset-synchronous PWM mode, the
PWM waveform output level is set with the OLSP and OLSN bits in the timer output control
register (TOCR). In the case of complementary PWM mode or reset-synchronous PWM mode,
TIOR should be set to H'00.
8.7.20 Interrupts in Module Standby Mode
If module standby mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source. Interrupts should therefore be disabled before entering module
standby mode.
8.7.21 Simultaneous Input Capture of TCNT_1 and TCNT_2 in Cascade Connection
When timer counters 1 and 2 (TCNT_1 and TCNT_2) are operated as a 32-bit counter in cascade
connection, the cascade counter value cannot be captured successfully even if input-capture input
is simultaneously done to TIOC1A and TIOC2A or to TIOC1B and TIOC2B. This is because the
input timing of TIOC1A and TIOC2A or of TIOC1B and TIOC2B may not be the same when
external input-capture signals to be input into TCNT_1 and TCNT_2 are taken in synchronization
with the internal clock. For example, TCNT_1 (the counter for upper 16 bits) does not capture the
count-up value by overflow from TCNT_2 (the counter for lower 16 bits) but captures the count
value before the count-up. In this case, the values of TCNT_1 = H'FFF1 and TCNT_2 = H'0000
should be transferred to TGRA_1 and TGRA_2 or to TGRB_1 and TGRB_2, but the values of
TCNT_1 = H'FFF0 and TCNT_2 = H'0000 are erroneously transferred.
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8. Multi-Function Timer Pulse Unit (MTU)
8.8
MTU Output Pin Initialization
8.8.1
Operating Modes
The MTU has the following six operating modes. Waveform output is possible in all of these
modes.
•
•
•
•
•
•
Normal mode (channels 0 to 4)
PWM mode 1 (channels 0 to 4)
PWM mode 2 (channels 0 to 2)
Phase counting modes 1 to 4 (channels 1 and 2)
Complementary PWM mode (channels 3 and 4)
Reset-synchronous PWM mode (channels 3 and 4)
The MTU output pin initialization method for each of these modes is described in this section.
8.8.2 Reset Start Operation
The MTU output pins (TIOC*) are initialized low by a reset or in standby mode. Since MTU pin
function selection is performed by the pin function controller (PFC), when the PFC is set, the
MTU pin states at that point are output to the ports. When MTU output is selected by the PFC
immediately after a reset, the MTU output initial level, low, is output directly at the port. When
the active level is low, the system will operate at this point, and therefore the PFC setting should
be made after initialization of the MTU output pins is completed.
Note: Channel number and port notation are substituted for *.
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8. Multi-Function Timer Pulse Unit (MTU)
Operation in Case of Re-Setting Due to Error During Operation, Etc.
8.8.3
If an error occurs during MTU operation, MTU output should be cut by the system. Cutoff is
performed by switching the pin output to port output with the PFC and outputting the inverse of
the active level. For large-current pins, output can also be cut by hardware, using port output
enable (POE). The pin initialization procedures for re-setting due to an error during operation, etc.,
and the procedures for restarting in a different mode after re-setting, are shown below.
The MTU has six operating modes, as stated above. There are thus 36 mode transition
combinations, but some transitions are not available with certain channel and mode combinations.
Possible mode transition combinations are shown in table 8.43.
Table 8.43 Mode Transition Combinations
After
Before
Normal
PWM1
PWM2
PCM
Normal
(1)
PWM1
(2)
PWM2
(3)
PCM
(4)
CPWM
(5)
RPWM
(6)
(7)
(8)
(9)
(10)
(16)
(20)
None
None
(11)
(12)
(13)
(17)
(21)
(26)
(14)
(18)
(22)
(27)
(15)
None
None
(23) (24)
(28)
None
None
(25)
(19)
CPWM
RPWM
Legend:
None
None
(29)
Normal: Normal mode
PWM1: PWM mode 1
PWM2: PWM mode 2
PCM: Phase counting modes 1 to 4
CPWM: Complementary PWM mode
RPWM: Reset-synchronous PWM mode
The above abbreviations are used in some places in following descriptions.
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8. Multi-Function Timer Pulse Unit (MTU)
8.8.4
Overview of Initialization Procedures and Mode Transitions in Case of Error
during Operation, Etc.
•
•
•
•
•
•
When making a transition to a mode (Normal, PWM1, PWM2, PCM) in which the pin output
level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of
a TIOR setting.
In PWM mode 1, since a waveform is not output to the TIOC*B (TIOC *D) pin, setting TIOR
will not initialize the pins. If initialization is required, carry it out in normal mode, then switch
to PWM mode 1.
In PWM mode 2, since a waveform is not output to the cycle register pin, setting TIOR will
not initialize the pins. If initialization is required, carry it out in normal mode, then switch to
PWM mode 2.
In normal mode or PWM mode 2, if TGRC and TGRD operate as buffer registers, setting
TIOR will not initialize the buffer register pins. If initialization is required, clear buffer mode,
carry out initialization, and then set buffer mode again.
In PWM mode 1, if either TGRC or TGRD operates as a buffer register, setting TIOR will not
initialize the TGRC pin. To initialize the TGRC pin, clear buffer mode, carry out initialization,
then set buffer mode again.
When making a transition to a mode (CPWM, RPWM) in which the pin output level is
selected by the timer output control register (TOCR) setting, switch to normal mode and
perform initialization with TIOR, then restore TIOR to its initial value, and temporarily disable
channel 3 and 4 output with the timer output master enable register (TOER). Then operate the
unit in accordance with the mode setting procedure (TOCR setting, TMDR setting, TOER
setting).
Note: Channel number is substituted for * indicated in this article.
Pin initialization procedures are described below for the numbered combinations in table 8.43. The
active level is assumed to be low.
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8. Multi-Function Timer Pulse Unit (MTU)
(1) Operation when Error Occurs during Normal Mode Operation, and Operation is
Restarted in Normal Mode: Figure 8.84 shows an explanatory diagram of the case where an
error occurs in normal mode and operation is restarted in normal mode after re-setting.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RESET TMDR TOER TIOR PFC TSTR Match Error
PFC TSTR TMDR TIOR PFC TSTR
(normal) (1)
(1 init (MTU)
0 out)
(1)
occurs (PORT) (0) (normal) (1 init (MTU)
0 out)
(1)
MTU module
output
TIOC*A
TIOC*B
Port output
PEn
Hi-Z
Hi-Z
PEn
Note: n = 0 to 15
Figure 8.84 Error Occurrence in Normal Mode, Recovery in Normal Mode
1. After a reset, MTU output is low and ports are in the high-impedance state.
2. After a reset, the TMDR setting is for normal mode.
3. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR.
4. Initialize the pins with TIOR. (The example shows initial high output, with low output on
compare-match occurrence.)
5. Set MTU output with the PFC.
6. The count operation is started by TSTR.
7. Output goes low on compare-match occurrence.
8. An error occurs.
9. Set port output with the PFC and output the inverse of the active level.
10. The count operation is stopped by TSTR.
11. Not necessary when restarting in normal mode.
12. Initialize the pins with TIOR.
13. Set MTU output with the PFC.
14. Operation is restarted by TSTR.
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8. Multi-Function Timer Pulse Unit (MTU)
(2) Operation when Error Occurs during Normal Mode Operation, and Operation is
Restarted in PWM Mode 1: Figure 8.85 shows an explanatory diagram of the case where an
error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RESET TMDR TOER TIOR PFC TSTR Match Error
PFC TSTR TMDR TIOR PFC TSTR
(normal) (1)
(1 init (MTU)
0 out)
(1)
occurs (PORT) (0) (PWM1) (1 init (MTU)
0 out)
(1)
MTU module
output
TIOC*A
TIOC*B
• Not initialized (TIOC*B)
Port output
PEn
Hi-Z
Hi-Z
PEn
Note: n = 0 to 15
Figure 8.85 Error Occurrence in Normal Mode, Recovery in PWM Mode 1
1 to 10 are the same as in figure 8.84.
11. Set PWM mode 1.
12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized. If
initialization is required, initialize in normal mode, then switch to PWM mode 1.)
13. Set MTU output with the PFC.
14. Operation is restarted by TSTR.
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8. Multi-Function Timer Pulse Unit (MTU)
(3) Operation when Error Occurs during Normal Mode Operation, and Operation is
Restarted in PWM Mode 2: Figure 8.86 shows an explanatory diagram of the case where an
error occurs in normal mode and operation is restarted in PWM mode 2 after re-setting.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RESET TMDR TOER TIOR PFC TSTR Match Error
PFC TSTR TMDR TIOR PFC TSTR
(normal) (1)
(1 init (MTU)
0 out)
(1)
occurs (PORT) (0) (PWM2) (1 init (MTU)
0 out)
(1)
MTU module
output
• Not initialized (cycle register)
TIOC*A
TIOC*B
Port output
PEn
Hi-Z
Hi-Z
PEn
Note: n = 0 to 15
Figure 8.86 Error Occurrence in Normal Mode, Recovery in PWM Mode 2
1 to 10 are the same as in figure 8.84.
11. Set PWM mode 2.
12. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized. If
initialization is required, initialize in normal mode, then switch to PWM mode 2.)
13. Set MTU output with the PFC.
14. Operation is restarted by TSTR.
Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not
necessary.
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8. Multi-Function Timer Pulse Unit (MTU)
(4) Operation when Error Occurs during Normal Mode Operation, and Operation is
Restarted in Phase Counting Mode: Figure 8.87 shows an explanatory diagram of the case
where an error occurs in normal mode and operation is restarted in phase counting mode after re-
setting.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RESET TMDR TOER TIOR PFC TSTR Match Error
PFC TSTR TMDR TIOR PFC TSTR
(normal) (1)
(1 init (MTU)
0 out)
(1)
occurs (PORT) (0)
(PCM) (1 init (MTU)
0 out)
(1)
MTU module
output
TIOC*A
TIOC*B
Port output
PEn
Hi-Z
Hi-Z
PEn
Note: n = 0 to 15
Figure 8.87 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode
1 to 10 are the same as in figure 8.84.
11. Set phase counting mode.
12. Initialize the pins with TIOR.
13. Set MTU output with the PFC.
14. Operation is restarted by TSTR.
Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is
not necessary.
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8. Multi-Function Timer Pulse Unit (MTU)
(5) Operation when Error Occurs during Normal Mode Operation, and Operation is
Restarted in Complementary PWM Mode: Figure 8.88 shows an explanatory diagram of the
case where an error occurs in normal mode and operation is restarted in complementary PWM
mode after re-setting.
1
2
3
4
5
6
7
8
9
10
11
12
13
(0)
14
15
(16)
(17)
(18)
(1)
RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR
(normal) (1) (1 init (MTU) (1)
0 out)
occurs (PORT) (0)
(0 init (disabled
0 out)
)
(CPWM) (1) (MTU)
MTU module
output
TIOC3A
TIOC3B
TIOC3D
Port output
PE8
Hi-Z
Hi-Z
Hi-Z
PE9
PE11
Figure 8.88 Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode
1 to 10 are the same as in figure 8.84.
11. Initialize the normal mode waveform generation section with TIOR.
12. Disable operation of the normal mode waveform generation section with TIOR.
13. Disable channel 3 and 4 output with TOER.
14. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR.
15. Set complementary PWM.
16. Enable channel 3 and 4 output with TOER.
17. Set MTU output with the PFC.
18. Operation is restarted by TSTR.
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8. Multi-Function Timer Pulse Unit (MTU)
(6) Operation when Error Occurs during Normal Mode Operation, and Operation is
Restarted in Reset-Synchronous PWM Mode: Figure 8.89 shows an explanatory diagram of the
case where an error occurs in normal mode and operation is restarted in reset-synchronous PWM
mode after re-setting.
1
2
3
4
5
6
7
8
9
10
11
12
13
(0)
14
15
16
17
18
(1)
RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR
(normal) (1) (1 init (MTU) (1)
0 out)
occurs (PORT) (0)
(0 init (disabled
0 out)
)
(CPWM) (1) (MTU)
MTU module
output
TIOC3A
TIOC3B
TIOC3D
Port output
PE8
Hi-Z
Hi-Z
Hi-Z
PE9
PE11
Figure 8.89 Error Occurrence in Normal Mode, Recovery in Reset-Synchronous
PWM Mode
1 to 13 are the same as in figure 8.88.
14. Select the reset-synchronous PWM output level and cyclic output enabling/disabling with
TOCR.
15. Set reset-synchronous PWM.
16. Enable channel 3 and 4 output with TOER.
17. Set MTU output with the PFC.
18. Operation is restarted by TSTR.
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8. Multi-Function Timer Pulse Unit (MTU)
(7) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is
Restarted in Normal Mode: Figure 8.90 shows an explanatory diagram of the case where an
error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RESET TMDR TOER TIOR PFC TSTR Match Error
PFC TSTR TMDR TIOR PFC TSTR
(PWM1) (1)
(1 init (MTU)
0 out)
(1)
occurs (PORT) (0) (normal) (1 init (MTU)
0 out)
(1)
MTU module
output
TIOC*A
• Not initialized (TIOC*B)
TIOC*B
Port output
PEn
Hi-Z
Hi-Z
PEn
Note: n = 0 to 15
Figure 8.90 Error Occurrence in PWM Mode 1, Recovery in Normal Mode
1. After a reset, MTU output is low and ports are in the high-impedance state.
2. Set PWM mode 1.
3. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR.
4. Initialize the pins with TIOR. (The example shows initial high output, with low output on
compare-match occurrence. In PWM mode 1, the TIOC*B side is not initialized.)
5. Set MTU output with the PFC.
6. The count operation is started by TSTR.
7. Output goes low on compare-match occurrence.
8. An error occurs.
9. Set port output with the PFC and output the inverse of the active level.
10. The count operation is stopped by TSTR.
11. Set normal mode.
12. Initialize the pins with TIOR.
13. Set MTU output with the PFC.
14. Operation is restarted by TSTR.
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8. Multi-Function Timer Pulse Unit (MTU)
(8) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is
Restarted in PWM Mode 1: Figure 8.91 shows an explanatory diagram of the case where an
error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RESET TMDR TOER TIOR PFC TSTR Match Error
PFC TSTR TMDR TIOR PFC TSTR
(PWM1) (1)
(1 init (MTU)
0 out)
(1)
occurs (PORT) (0) (PWM1) (1 init (MTU)
0 out)
(1)
MTU module
output
TIOC*A
• Not initialized (TIOC*B)
• Not initialized (TIOC*B)
TIOC*B
Port output
PEn
Hi-Z
Hi-Z
PEn
Note: n = 0 to 15
Figure 8.91 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1
1 to 10 are the same as in figure 8.90.
11. Not necessary when restarting in PWM mode 1.
12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.)
13. Set MTU output with the PFC.
14. Operation is restarted by TSTR.
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8. Multi-Function Timer Pulse Unit (MTU)
(9) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is
Restarted in PWM Mode 2: Figure 8.92 shows an explanatory diagram of the case where an
error occurs in PWM mode 1 and operation is restarted in PWM mode 2 after re-setting.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RESET TMDR TOER TIOR PFC TSTR Match Error
PFC TSTR TMDR TIOR PFC TSTR
(PWM1) (1)
(1 init (MTU)
0 out)
(1)
occurs (PORT) (0) (PWM2) (1 init (MTU)
0 out)
(1)
MTU module
output
• Not initialized (cycle register)
TIOC*A
• Not initialized (TIOC*B)
TIOC*B
Port output
PEn
Hi-Z
Hi-Z
PEn
Note: n = 0 to 15
Figure 8.92 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2
1 to 10 are the same as in figure 8.90.
11. Set PWM mode 2.
12. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.)
13. Set MTU output with the PFC.
14. Operation is restarted by TSTR.
Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not
necessary.
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8. Multi-Function Timer Pulse Unit (MTU)
(10) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is
Restarted in Phase Counting Mode: Figure 8.93 shows an explanatory diagram of the case
where an error occurs in PWM mode 1 and operation is restarted in phase counting mode after re-
setting.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RESET TMDR TOER TIOR PFC TSTR Match Error
PFC TSTR TMDR TIOR PFC TSTR
(PWM1) (1)
(1 init (MTU)
0 out)
(1)
occurs (PORT) (0)
(PCM) (1 init (MTU)
0 out)
(1)
MTU module
output
TIOC*A
• Not initialized (TIOC*B)
TIOC*B
Port output
PEn
Hi-Z
Hi-Z
PEn
Note: n = 0 to 15
Figure 8.93 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode
1 to 10 are the same as in figure 8.90.
11. Set phase counting mode.
12. Initialize the pins with TIOR.
13. Set MTU output with the PFC.
14. Operation is restarted by TSTR.
Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is
not necessary.
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8. Multi-Function Timer Pulse Unit (MTU)
(11) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is
Restarted in Complementary PWM Mode: Figure 8.94 shows an explanatory diagram of the
case where an error occurs in PWM mode 1 and operation is restarted in complementary PWM
mode after re-setting.
1
2
3
4
5
6
7
8
9
10
PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR
occurs (PORT) (0) (normal) (0 init (disabled (0) (CPWM) (1) (MTU) (1)
0 out)
11
12
13
14
15
16
17
18
19
RESET TMDR TOER TIOR
(PWM1) (1) (1 init (MTU)
0 out)
PFC TSTR Match Error
(1)
)
MTU module
output
TIOC3A
TIOC3B
TIOC3D
• Not initialized (TIOC3B)
• Not initialized (TIOC3D)
Port output
PE8
Hi-Z
Hi-Z
Hi-Z
PE9
PE11
Figure 8.94 Error Occurrence in PWM Mode 1, Recovery in Complementary PWM Mode
1 to 10 are the same as in figure 8.90.
11. Set normal mode for initialization of the normal mode waveform generation section.
12. Initialize the PWM mode 1 waveform generation section with TIOR.
13. Disable operation of the PWM mode 1 waveform generation section with TIOR.
14. Disable channel 3 and 4 output with TOER.
15. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR.
16. Set complementary PWM.
17. Enable channel 3 and 4 output with TOER.
18. Set MTU output with the PFC.
19. Operation is restarted by TSTR.
Rev.2.00 Sep. 27, 2007 Page 233 of 448
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8. Multi-Function Timer Pulse Unit (MTU)
(12) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is
Restarted in Reset-Synchronous PWM Mode: Figure 8.95 shows an explanatory diagram of the
case where an error occurs in PWM mode 1 and operation is restarted in reset-synchronous PWM
mode after re-setting.
1
2
3
4
5
6
7
8
9
10
PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR
occurs (PORT) (0) (normal) (0 init (disabled (0) (RPWM) (1) (MTU) (1)
0 out)
11
12
13
14
15
16
17
18
19
RESET TMDR TOER TIOR
(PWM1) (1) (1 init (MTU)
0 out)
PFC TSTR Match Error
(1)
)
MTU module
output
TIOC3A
TIOC3B
TIOC3D
• Not initialized (TIOC3B)
• Not initialized (TIOC3D)
Port output
PE8
Hi-Z
Hi-Z
Hi-Z
PE9
PE11
Figure 8.95 Error Occurrence in PWM Mode 1,
Recovery in Reset-Synchronous PWM Mode
1 to 14 are the same as in figure 8.90.
15. Select the reset-synchronous PWM output level and cyclic output enabling/disabling with
TOCR.
16. Set reset-synchronous PWM.
17. Enable channel 3 and 4 output with TOER.
18. Set MTU output with the PFC.
19. Operation is restarted by TSTR.
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8. Multi-Function Timer Pulse Unit (MTU)
(13) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is
Restarted in Normal Mode: Figure 8.96 shows an explanatory diagram of the case where an
error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting.
1
2
3
4
5
6
7
8
9
10
PFC TSTR TMDR TIOR PFC TSTR
occurs (PORT) (0) (normal) (1 init (MTU) (1)
0 out)
11
12
13
RESET TMDR TIOR
PFC TSTR Match Error
(1)
(PWM2) (1 init (MTU)
0 out)
MTU module
output
• Not initialized (cycle register)
TIOC*A
TIOC*B
Port output
PEn
Hi-Z
Hi-Z
PEn
Note: n = 0 to 15
Figure 8.96 Error Occurrence in PWM Mode 2, Recovery in Normal Mode
1. After a reset, MTU output is low and ports are in the high-impedance state.
2. Set PWM mode 2.
3. Initialize the pins with TIOR. (The example shows initial high output, with low output on
compare-match occurrence. In PWM mode 2, the cycle register pins are not initialized. In the
example, TIOC *A is the cycle register.)
4. Set MTU output with the PFC.
5. The count operation is started by TSTR.
6. Output goes low on compare-match occurrence.
7. An error occurs.
8. Set port output with the PFC and output the inverse of the active level.
9. The count operation is stopped by TSTR.
10. Set normal mode.
11. Initialize the pins with TIOR.
12. Set MTU output with the PFC.
13. Operation is restarted by TSTR.
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8. Multi-Function Timer Pulse Unit (MTU)
(14) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is
Restarted in PWM Mode 1: Figure 8.97 shows an explanatory diagram of the case where an
error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting.
1
2
3
4
5
6
7
8
9
10
PFC TSTR TMDR TIOR PFC TSTR
occurs (PORT) (0) (PWM1) (1 init (MTU) (1)
0 out)
11
12
13
RESET TMDR TIOR
PFC TSTR Match Error
(1)
(PWM2) (1 init (MTU)
0 out)
MTU module
output
• Not initialized (cycle register)
TIOC*A
TIOC*B
• Not initialized (TIOC*B)
Port output
PEn
Hi-Z
Hi-Z
PEn
Note: n = 0 to 15
Figure 8.97 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1
1 to 9 are the same as in figure 8.96.
10. Set PWM mode 1.
11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.)
12. Set MTU output with the PFC.
13. Operation is restarted by TSTR.
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8. Multi-Function Timer Pulse Unit (MTU)
(15) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is
Restarted in PWM Mode 2: Figure 8.98 shows an explanatory diagram of the case where an
error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting.
1
2
3
4
5
6
7
8
9
10
PFC TSTR TMDR TIOR PFC TSTR
occurs (PORT) (0) (PWM2) (1 init (MTU) (1)
0 out)
11
12
13
RESET TMDR TIOR
PFC TSTR Match Error
(1)
(PWM2) (1 init (MTU)
0 out)
MTU module
output
• Not initialized (cycle register)
• Not initialized (cycle register)
TIOC*A
TIOC*B
Port output
PEn
Hi-Z
Hi-Z
PEn
Note: n = 0 to 15
Figure 8.98 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2
1 to 9 are the same as in figure 8.96.
10. Not necessary when restarting in PWM mode 2.
11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.)
12. Set MTU output with the PFC.
13. Operation is restarted by TSTR.
Rev.2.00 Sep. 27, 2007 Page 237 of 448
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8. Multi-Function Timer Pulse Unit (MTU)
(16) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is
Restarted in Phase Counting Mode: Figure 8.99 shows an explanatory diagram of the case
where an error occurs in PWM mode 2 and operation is restarted in phase counting mode after re-
setting.
1
2
3
4
5
6
7
8
9
10
11
12
13
RESET TMDR TIOR
PFC TSTR Match Error
(1) occurs (PORT) (0)
PFC TSTR TMDR TIOR PFC TSTR
(PWM2) (1 init (MTU)
(PCM) (1 init (MTU)
0 out)
(1)
0 out)
MTU module
output
• Not initialized (cycle register)
TIOC*A
TIOC*B
Port output
PEn
Hi-Z
Hi-Z
PEn
Note: n = 0 to 15
Figure 8.99 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode
1 to 9 are the same as in figure 8.96.
10. Set phase counting mode.
11. Initialize the pins with TIOR.
12. Set MTU output with the PFC.
13. Operation is restarted by TSTR.
Rev.2.00 Sep. 27, 2007 Page 238 of 448
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8. Multi-Function Timer Pulse Unit (MTU)
(17) Operation when Error Occurs during Phase Counting Mode Operation, and Operation
is Restarted in Normal Mode: Figure 8.100 shows an explanatory diagram of the case where an
error occurs in phase counting mode and operation is restarted in normal mode after re-setting.
1
2
3
4
5
6
7
8
9
10
PFC TSTR TMDR TIOR PFC TSTR
occurs (PORT) (0) (normal) (1 init (MTU) (1)
0 out)
11
12
13
RESET TMDR TIOR
PFC TSTR Match Error
(1)
(PCM) (1 init (MTU)
0 out)
MTU module
output
TIOC*A
TIOC*B
Port output
PEn
Hi-Z
Hi-Z
PEn
Note: n = 0 to 15
Figure 8.100 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode
1. After a reset, MTU output is low and ports are in the high-impedance state.
2. Set phase counting mode.
3. Initialize the pins with TIOR. (The example shows initial high output, with low output on
compare-match occurrence.)
4. Set MTU output with the PFC.
5. The count operation is started by TSTR.
6. Output goes low on compare-match occurrence.
7. An error occurs.
8. Set port output with the PFC and output the inverse of the active level.
9. The count operation is stopped by TSTR.
10. Set in normal mode.
11. Initialize the pins with TIOR.
12. Set MTU output with the PFC.
13. Operation is restarted by TSTR.
Rev.2.00 Sep. 27, 2007 Page 239 of 448
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8. Multi-Function Timer Pulse Unit (MTU)
(18) Operation when Error Occurs during Phase Counting Mode Operation, and Operation
is Restarted in PWM Mode 1: Figure 8.101 shows an explanatory diagram of the case where an
error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting.
1
2
3
4
5
6
7
8
9
10
PFC TSTR TMDR TIOR PFC TSTR
occurs (PORT) (0) (PWM1) (1 init (MTU) (1)
0 out)
11
12
13
RESET TMDR TIOR
PFC TSTR Match Error
(1)
(PCM) (1 init (MTU)
0 out)
MTU module
output
TIOC*A
TIOC*B
• Not initialized (TIOC*B)
Port output
PEn
Hi-Z
Hi-Z
PEn
Note: n = 0 to 15
Figure 8.101 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1
1 to 9 are the same as in figure 8.100.
10. Set PWM mode 1.
11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.)
12. Set MTU output with the PFC.
13. Operation is restarted by TSTR.
Rev.2.00 Sep. 27, 2007 Page 240 of 448
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8. Multi-Function Timer Pulse Unit (MTU)
(19) Operation when Error Occurs during Phase Counting Mode Operation, and Operation
is Restarted in PWM Mode 2: Figure 8.102 shows an explanatory diagram of the case where an
error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting.
1
2
3
4
5
6
7
8
9
10
PFC TSTR TMDR TIOR PFC TSTR
occurs (PORT) (0) (PWM2) (1 init (MTU) (1)
0 out)
11
12
13
RESET TMDR TIOR
PFC TSTR Match Error
(1)
(PCM) (1 init (MTU)
0 out)
MTU module
output
• Not initialized (cycle register)
TIOC*A
TIOC*B
Port output
PEn
Hi-Z
Hi-Z
PEn
Note: n = 0 to 15
Figure 8.102 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2
1 to 9 are the same as in figure 8.100.
10. Set PWM mode 2.
11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.)
12. Set MTU output with the PFC.
13. Operation is restarted by TSTR.
Rev.2.00 Sep. 27, 2007 Page 241 of 448
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8. Multi-Function Timer Pulse Unit (MTU)
(20) Operation when Error Occurs during Phase Counting Mode Operation, and Operation
is Restarted in Phase Counting Mode: Figure 8.103 shows an explanatory diagram of the case
where an error occurs in phase counting mode and operation is restarted in phase counting mode
after re-setting.
1
2
3
4
5
6
7
8
9
10
11
12
13
RESET TMDR TIOR
PFC TSTR Match Error
(1) occurs (PORT) (0)
PFC TSTR TMDR TIOR PFC TSTR
(PCM) (1 init (MTU)
(PCM) (1 init (MTU)
0 out)
(1)
0 out)
MTU module
output
TIOC*A
TIOC*B
Port output
PEn
Hi-Z
Hi-Z
PEn
Note: n = 0 to 15
Figure 8.103 Error Occurrence in Phase Counting Mode,
Recovery in Phase Counting Mode
1 to 9 are the same as in figure 8.100.
10. Not necessary when restarting in phase counting mode.
11. Initialize the pins with TIOR.
12. Set MTU output with the PFC.
13. Operation is restarted by TSTR.
Rev.2.00 Sep. 27, 2007 Page 242 of 448
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8. Multi-Function Timer Pulse Unit (MTU)
(21) Operation when Error Occurs during Complementary PWM Mode Operation, and
Operation is Restarted in Normal Mode: Figure 8.104 shows an explanatory diagram of the
case where an error occurs in complementary PWM mode and operation is restarted in normal
mode after re-setting.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RESET TOCR TMDR TOER PFC TSTR Match Error
PFC TSTR TMDR TIOR PFC TSTR
(CPWM) (1)
(MTU)
(1)
occurs (PORT) (0) (normal) (1 init (MTU)
0 out)
(1)
MTU module
output
TIOC3A
TIOC3B
TIOC3D
Port output
PE8
Hi-Z
Hi-Z
Hi-Z
PE9
PE11
Figure 8.104 Error Occurrence in Complementary PWM Mode, Recovery in Normal Mode
1. After a reset, MTU output is low and ports are in the high-impedance state.
2. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR.
3. Set complementary PWM.
4. Enable channel 3 and 4 output with TOER.
5. Set MTU output with the PFC.
6. The count operation is started by TSTR.
7. The complementary PWM waveform is output on compare-match occurrence.
8. An error occurs.
9. Set port output with the PFC and output the inverse of the active level.
10. The count operation is stopped by TSTR. (MTU output becomes the complementary PWM
output initial value.)
11. Set normal mode. (MTU output goes low.)
12. Initialize the pins with TIOR.
13. Set MTU output with the PFC.
14. Operation is restarted by TSTR.
Rev.2.00 Sep. 27, 2007 Page 243 of 448
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8. Multi-Function Timer Pulse Unit (MTU)
(22) Operation when Error Occurs during Complementary PWM Mode Operation, and
Operation is Restarted in PWM Mode 1: Figure 8.105 shows an explanatory diagram of the
case where an error occurs in complementary PWM mode and operation is restarted in PWM
mode 1 after re-setting.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RESET TOCR TMDR TOER PFC TSTR Match Error
PFC TSTR TMDR TIOR PFC TSTR
(CPWM) (1)
(MTU)
(1)
occurs (PORT) (0) (PWM1) (1 init (MTU)
0 out)
(1)
MTU module
output
TIOC3A
TIOC3B
TIOC3D
• Not initialized (TIOC3B)
• Not initialized (TIOC3D)
Port output
PE8
Hi-Z
Hi-Z
Hi-Z
PE9
PE11
Figure 8.105 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1
1 to 10 are the same as in figure 8.104.
11. Set PWM mode 1. (MTU output goes low.)
12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.)
13. Set MTU output with the PFC.
14. Operation is restarted by TSTR.
Rev.2.00 Sep. 27, 2007 Page 244 of 448
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8. Multi-Function Timer Pulse Unit (MTU)
(23) Operation when Error Occurs during Complementary PWM Mode Operation, and
Operation is Restarted in Complementary PWM Mode: Figure 8.106 shows an explanatory
diagram of the case where an error occurs in complementary PWM mode and operation is
restarted in complementary PWM mode after re-setting (when operation is restarted using the
cycle and duty cycle settings at the time the counter was stopped).
1
2
3
4
5
6
7
8
9
10
PFC TSTR PFC TSTR Match
occurs (PORT) (0) (MTU) (1)
11
12
13
RESET TOCR TMDR TOER PFC TSTR Match Error
(CPWM) (1)
(MTU)
(1)
MTU module
output
TIOC3A
TIOC3B
TIOC3D
Port output
PE8
Hi-Z
Hi-Z
Hi-Z
PE9
PE11
Figure 8.106 Error Occurrence in Complementary PWM Mode, Recovery in
Complementary PWM Mode
1 to 10 are the same as in figure 8.104.
11. Set MTU output with the PFC.
12. Operation is restarted by TSTR.
13. The complementary PWM waveform is output on compare-match occurrence.
Rev.2.00 Sep. 27, 2007 Page 245 of 448
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8. Multi-Function Timer Pulse Unit (MTU)
(24) Operation when Error Occurs during Complementary PWM Mode Operation, and
Operation is Restarted in Complementary PWM Mode: Figure 8.107 shows an explanatory
diagram of the case where an error occurs in complementary PWM mode and operation is
restarted in complementary PWM mode after re-setting (when operation is restarted using
completely new cycle and duty cycle settings).
1
2
3
4
5
6
7
8
9
10
PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR
occurs (PORT) (0) (normal) (0) (CPWM) (1) (MTU) (1)
11
12
13
14
15
16
17
RESET TOCR TMDR TOER PFC TSTR Match Error
(CPWM) (1)
(MTU)
(1)
MTU module
output
TIOC3A
TIOC3B
TIOC3D
Port output
PE8
Hi-Z
Hi-Z
Hi-Z
PE9
PE11
Figure 8.107 Error Occurrence in Complementary PWM Mode, Recovery in
Complementary PWM Mode
1 to 10 are the same as in figure 8.104.
11. Set normal mode and make new settings. (MTU output goes low.)
12. Disable channel 3 and 4 output with TOER.
13. Select the complementary PWM mode output level and cyclic output enabling/disabling with
TOCR.
14. Set complementary PWM.
15. Enable channel 3 and 4 output with TOER.
16. Set MTU output with the PFC.
17. Operation is restarted by TSTR.
Rev.2.00 Sep. 27, 2007 Page 246 of 448
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8. Multi-Function Timer Pulse Unit (MTU)
(25) Operation when Error Occurs during Complementary PWM Mode Operation, and
Operation is Restarted in Reset-Synchronous PWM Mode: Figure 8.108 shows an explanatory
diagram of the case where an error occurs in complementary PWM mode and operation is
restarted in reset-synchronous PWM mode.
1
2
3
4
5
6
7
8
9
10
PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR
occurs (PORT) (0) (normal) (0) (RPWM) (1) (MTU) (1)
11
12
13
14
15
16
17
RESET TOCR TMDR TOER PFC TSTR Match Error
(CPWM) (1)
(MTU)
(1)
MTU module
output
TIOC3A
TIOC3B
TIOC3D
Port output
PE8
Hi-Z
Hi-Z
Hi-Z
PE9
PE11
Figure 8.108 Error Occurrence in Complementary PWM Mode,
Recovery in Reset-Synchronous PWM Mode
1 to 10 are the same as in figure 8.104.
11. Set normal mode. (MTU output goes low.)
12. Disable channel 3 and 4 output with TOER.
13. Select the reset-synchronous PWM mode output level and cyclic output enabling/disabling
with TOCR.
14. Set reset-synchronous PWM.
15. Enable channel 3 and 4 output with TOER.
16. Set MTU output with the PFC.
17. Operation is restarted by TSTR.
Rev.2.00 Sep. 27, 2007 Page 247 of 448
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8. Multi-Function Timer Pulse Unit (MTU)
(26) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and
Operation is Restarted in Normal Mode: Figure 8.109 shows an explanatory diagram of the
case where an error occurs in reset-synchronous PWM mode and operation is restarted in normal
mode after re-setting.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RESET TOCR TMDR TOER PFC TSTR Match Error
PFC TSTR TMDR TIOR PFC TSTR
(CPWM) (1)
(MTU)
(1)
occurs (PORT) (0) (normal) (1 init (MTU)
0 out)
(1)
MTU module
output
TIOC3A
TIOC3B
TIOC3D
Port output
PE8
Hi-Z
Hi-Z
Hi-Z
PE9
PE11
Figure 8.109 Error Occurrence in Reset-Synchronous PWM Mode,
Recovery in Normal Mode
1. After a reset, MTU output is low and ports are in the high-impedance state.
2. Select the reset-synchronous PWM output level and cyclic output enabling/disabling with
TOCR.
3. Set reset-synchronous PWM.
4. Enable channel 3 and 4 output with TOER.
5. Set MTU output with the PFC.
6. The count operation is started by TSTR.
7. The reset-synchronous PWM waveform is output on compare-match occurrence.
8. An error occurs.
9. Set port output with the PFC and output the inverse of the active level.
10. The count operation is stopped by TSTR. (MTU output becomes the reset-synchronous PWM
output initial value.)
11. Set normal mode. (MTU positive phase output is low, and negative phase output is high.)
12. Initialize the pins with TIOR.
13. Set MTU output with the PFC.
14. Operation is restarted by TSTR.
Rev.2.00 Sep. 27, 2007 Page 248 of 448
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8. Multi-Function Timer Pulse Unit (MTU)
(27) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and
Operation is Restarted in PWM Mode 1: Figure 8.110 shows an explanatory diagram of the
case where an error occurs in reset-synchronous PWM mode and operation is restarted in PWM
mode 1 after re-setting.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RESET TOCR TMDR TOER PFC TSTR Match Error
PFC TSTR TMDR TIOR PFC TSTR
(RPWM) (1)
(MTU)
(1)
occurs (PORT) (0) (PWM1) (1 init (MTU)
0 out)
(1)
MTU module
output
TIOC3A
TIOC3B
TIOC3D
• Not initialized (TIOC3B)
• Not initialized (TIOC3D)
Port output
PE8
Hi-Z
Hi-Z
Hi-Z
PE9
PE11
Figure 8.110 Error Occurrence in Reset-Synchronous PWM Mode,
Recovery in PWM Mode 1
1 to 10 are the same as in figure 8.109.
11. Set PWM mode 1. (MTU positive phase output is low, and negative phase output is high.)
12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.)
13. Set MTU output with the PFC.
14. Operation is restarted by TSTR.
Rev.2.00 Sep. 27, 2007 Page 249 of 448
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8. Multi-Function Timer Pulse Unit (MTU)
(28) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and
Operation is Restarted in Complementary PWM Mode: Figure 8.111 shows an explanatory
diagram of the case where an error occurs in reset-synchronous PWM mode and operation is
restarted in complementary PWM mode after re-setting.
1
2
3
4
5
6
7
8
9
10
PFC TSTR TOER TOCR TMDR TOER PFC TSTR
occurs (PORT) (0) (0) (CPWM) (1) (MTU) (1)
11
12
13
14
15
16
RESET TOCR TMDR TOER PFC TSTR Match Error
(RPWM) (1)
(MTU)
(1)
MTU module
output
TIOC3A
TIOC3B
TIOC3D
Port output
PE8
Hi-Z
Hi-Z
Hi-Z
PE9
PE11
Figure 8.111 Error Occurrence in Reset-Synchronous PWM Mode,
Recovery in Complementary PWM Mode
1 to 10 are the same as in figure 8.109.
11. Disable channel 3 and 4 output with TOER.
12. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR.
13. Set complementary PWM. (The MTU cyclic output pin goes low.)
14. Enable channel 3 and 4 output with TOER.
15. Set MTU output with the PFC.
16. Operation is restarted by TSTR.
Rev.2.00 Sep. 27, 2007 Page 250 of 448
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8. Multi-Function Timer Pulse Unit (MTU)
(29) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and
Operation is Restarted in Reset-Synchronous PWM Mode: Figure 8.112 shows an explanatory
diagram of the case where an error occurs in reset-synchronous PWM mode and operation is
restarted in reset-synchronous PWM mode after re-setting.
1
2
3
4
5
6
7
8
9
10
PFC TSTR PFC TSTR Match
occurs (PORT) (0) (MTU) (1)
11
12
13
RESET TOCR TMDR TOER PFC TSTR Match Error
(RPWM) (1)
(MTU)
(1)
MTU module
output
TIOC3A
TIOC3B
TIOC3D
Port output
PE8
Hi-Z
Hi-Z
Hi-Z
PE9
PE11
Figure 8.112 Error Occurrence in Reset-Synchronous PWM Mode,
Recovery in Reset-Synchronous PWM Mode
1 to 10 are the same as in figure 8.109.
11. Set MTU output with the PFC.
12. Operation is restarted by TSTR.
13. The reset-synchronous PWM waveform is output on compare-match occurrence.
Rev.2.00 Sep. 27, 2007 Page 251 of 448
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8. Multi-Function Timer Pulse Unit (MTU)
8.9
Port Output Enable (POE)
The port output enable (POE) can be used to establish a high-impedance state for high-current pins,
by changing the POE0 to POE3 pin input, depending on the output status of the high-current pins
(PE9/TIOC3B, PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C,
PE15/TIOC4D/IRQOUT). It can also simultaneously generate interrupt requests.
The high-current pins also become high-impedance regardless of whether these pin functions are
selected in cases such as when the oscillator stops or in standby mode.
8.9.1
Features
•
•
•
•
Each of the POE0 to POE3 input pins can be set for falling edge, Pφ/8 × 16, Pφ/16 × 16, or
Pφ/128 × 16 low-level sampling.
High-current pins can be set to high-impedance state by POE0 to POE3 pin falling-edge or
low-level sampling.
High-current pins can be set to high-impedance state when the high-current pin output levels
are compared and simultaneous low-level output continues for one cycle or more.
Interrupts can be generated by input-level sampling or output-level comparison results.
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8. Multi-Function Timer Pulse Unit (MTU)
The POE has input-level detection circuitry and output-level detection circuitry, as shown in the
block diagram of figure 8.113.
TIOC3B
TIOC3D
TIOC4A
TIOC4C
TIOC4B
TIOC4D
Output level
detection circuit
Output level
detection circuit
Output level
detection circuit
High-
OCSR
ICSR1
impedance
request control
signal
Interrupt request
(MTUPOE)
Input level detection circuit
Falling-edge
detection circuit
POE3
POE2
POE1
POE0
Low-level
detection circuit
Pφ/8
Pφ/16
Pφ/128
Legend:
OCSR: Output level control/status register
ICSR1: Input level control/status register
Figure 8.113 POE Block Diagram
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8. Multi-Function Timer Pulse Unit (MTU)
8.9.2 Pin Configuration
Table 8.44 Pin Configuration
Name
Abbreviation
I/O
Description
Port output enable input pins POE0 to POE3
Input
Input request signals to make high-
current pins high-impedance state
Table 8.45 shows output-level comparisons with pin combinations.
Table 8.45 Pin Combinations
Pin Combination
I/O
Description
PE9/TIOC3B and PE11/TIOC3D
Output
All high-current pins are made high-impedance state
when the pins simultaneously output low-level for
longer than 1 cycle.
PE12/TIOC4A and PE14/TIOC4C Output
All high-current pins are made high-impedance state
when the pins simultaneously output low-level for
longer than 1 cycle.
PE13/TIOC4B/MRES and
PE15/TIOC4D/IRQOUT
Output
All high-current pins are made high-impedance state
when the pins simultaneously output low-level for
longer than 1 cycle.
8.9.3
Register Configuration
The POE has the two registers. The input level control/status register 1 (ICSR1) controls both
POE0 to POE3 pin input signal detection and interrupts. The output level control/status register
(OCSR) controls both the enable/disable of output comparison and interrupts.
Input Level Control/Status Register 1 (ICSR1): The input level control/status register (ICSR1)
is a 16-bit readable/writable register that selects the POE0 to POE3 pin input modes, controls the
enable/disable of interrupts, and indicates status.
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8. Multi-Function Timer Pulse Unit (MTU)
Initial
Bit
Bit Name value
R/W
Description
15
POE3F
POE2F
POE1F
POE0F
0
0
0
0
R/(W)*
POE3 Flag
This flag indicates that a high impedance request has
been input to the POE3 pin
[Clearing condition]
•
By writing 0 to POE3F after reading a POE3F = 1
[Setting condition]
•
When the input set by ICSR1 bits 7 and 6 occurs at
the POE3 pin
14
13
12
R/(W)*
R/(W)*
R/(W)*
POE2 Flag
This flag indicates that a high impedance request has
been input to the POE2 pin
[Clearing condition]
•
By writing 0 to POE2F after reading a POE2F = 1
[Setting condition]
•
When the input set by ICSR1 bits 5 and 4 occurs at
the POE2 pin
POE1 Flag
This flag indicates that a high impedance request has
been input to the POE1 pin
[Clearing condition]
•
By writing 0 to POE1F after reading a POE1F = 1
[Setting condition]
•
When the input set by ICSR1 bits 3 and 2 occurs at
the POE1 pin
POE0 Flag
This flag indicates that a high impedance request has
been input to the POE0 pin
[Clearing condition]
•
By writing 0 to POE0F after reading a POE0F = 1
[Setting condition]
•
When the input set by ICSR1 bits 1 and 0 occurs at
the POE0 pin
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8. Multi-Function Timer Pulse Unit (MTU)
Initial
Bit
Bit Name value
R/W
Description
11 to 9 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
8
PIE
0
R/W
Port Interrupt Enable
This bit enables/disables interrupt requests when any of
the POE0F to POE3F bits of the ICSR1 are set to 1
0: Interrupt requests disabled
1: Interrupt requests enabled
7
6
POE3M1
POE3M0
0
0
R/W
R/W
POE3 mode 1, 0
These bits select the input mode of the POE3 pin
00: Accept request on falling edge of POE3 input
01: Accept request when POE3 input has been sampled
for 16 Pφ/8 clock pulses, and all are low level.
10: Accept request when POE3 input has been sampled
for 16 Pφ/16 clock pulses, and all are low level.
11: Accept request when POE3 input has been sampled
for 16 Pφ/128 clock pulses, and all are low level.
5
4
POE2M1
POE2M0
0
0
R/W
R/W
POE2 mode 1, 0
These bits select the input mode of the POE2 pin
00: Accept request on falling edge of POE2 input
01: Accept request when POE2 input has been sampled
for 16 Pφ/8 clock pulses, and all are low level.
10: Accept request when POE2 input has been sampled
for 16 Pφ/16 clock pulses, and all are low level.
11: Accept request when POE2 input has been sampled
for 16 Pφ/128 clock pulses, and all are low level.
3
2
POE1M1
POE1M0
0
0
R/W
R/W
POE1 mode 1, 0
These bits select the input mode of the POE1 pin
00: Accept request on falling edge of POE1 input
01: Accept request when POE1 input has been sampled
for 16 Pφ/8 clock pulses, and all are low level.
10: Accept request when POE1 input has been sampled
for 16 Pφ/16 clock pulses, and all are low level.
11: Accept request when POE1 input has been sampled
for 16 Pφ/128 clock pulses, and all are low level.
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8. Multi-Function Timer Pulse Unit (MTU)
Initial
Bit
Bit Name value
R/W
Description
1
0
POE0M1
POE0M0
0
0
R/W
R/W
POE0 mode 1, 0
These bits select the input mode of the POE0 pin
00: Accept request on falling edge of POE0 input
01: Accept request when POE0 input has been sampled
for 16 Pφ/8 clock pulses, and all are low level.
10: Accept request when POE0 input has been sampled
for 16 Pφ/16 clock pulses, and all are low level.
11: Accept request when POE0 input has been sampled
for 16 Pφ/128 clock pulses, and all are low level.
Note:
*
The write value should always be 0.
Output Level Control/Status Register (OCSR): The output level control/status register (OCSR)
is a 16-bit readable/writable register that controls the enable/disable of both output level
comparison and interrupts, and indicates status. If the OSF bit is set to 1, the high current pins
become high impedance.
Initial
Bit
Bit Name value
R/W
R/(W)* Output Short Flag
This flag indicates that any one pair of the three pairs of
Description
15
OSF
0
2 phase outputs compared have simultaneously
become low level outputs.
[Clearing condition]
•
By writing 0 to OSF after reading an OSF = 1
[Setting condition]
•
When any one pair of the three 2-phase outputs
simultaneously become low level
14 to 10 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
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8. Multi-Function Timer Pulse Unit (MTU)
Initial
Bit
Bit Name value
R/W
Description
9
OCE
0
R/W
Output Level Compare Enable
This bit enables the start of output level comparisons.
When setting this bit to 1, pay attention to the output pin
combinations shown in table 8.43, Mode Transition
Combinations. When 0 is output, the OSF bit is set to 1
at the same time when this bit is set, and output goes to
high impedance. Accordingly, bits 15 to 11 and bit 9 of
the port E data register (PEDR) are set to 1. For the
MTU output comparison, set the bit to 1 after setting the
MTU's output pins with the PFC. Set this bit only when
using pins as outputs.
When the OCE bit is set to 1, if OIE = 0 a high-
impedance request will not be issued even if OSF is set
to 1. Therefore, in order to have a high-impedance
request issued according to the result of the output level
comparison, the OIE bit must be set to 1. When OCE =
1 and OIE = 1, an interrupt request will be generated at
the same time as the high-impedance request:
however, this interrupt can be masked by means of an
interrupt controller (INTC) setting.
0: Output level compare disabled
1: Output level compare enabled; makes an output high
impedance request when OSF = 1.
8
OIE
0
R/W
Output Short Interrupt Enable
This bit makes interrupt requests when the OSF bit of
the OCSR is set.
0: Interrupt requests disabled
1: Interrupt request enabled
7 to 0
Note:
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
*
The write value should always be 0.
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8. Multi-Function Timer Pulse Unit (MTU)
8.9.4
Operation
Input Level Detection Operation
If the input conditions set by the ICSR1 occur on any of the POE pins, all high-current pins
become high-impedance state. However, only when the general input/output function or MTU
function is selected, the large-current pin is in the high-impedance state.
Falling Edge Detection: When a change from high to low level is input to the POE pins.
Low-Level Detection: Figure 8.114 shows the low-level detection operation. Sixteen continuous
low levels are sampled with the sampling clock established by the ICSR1. If even one high level is
detected during this interval, the low level is not accepted.
Furthermore, the timing when the large-current pins enter the high-impedance state from the
sampling clock is the same in both falling-edge detection and in low-level detection.
8/16/128 clock
cycles
Pφ
Sampling
clock
POE input
PE9/
TIOC3B
High-impedance
state*
When low level is
sampled at all points
Flag set
(POE received)
1
1
2
2
3
16
13
When high level is
sampled at least once
Flag not set
Note: * Other large-current pins (PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C,
PE15/TIOC4D/IRQOUT) also go to the high-impedance state at the same timing.
Figure 8.114 Low-Level Detection Operation
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8. Multi-Function Timer Pulse Unit (MTU)
Output-Level Compare Operation
Figure 8.115 shows an example of the output-level compare operation for the combination of
PE9/TIOC3B and PE11/TIOC3D. The operation is the same for the other pin combinations.
Pφ
0 level overlapping detected
PE9/
TIOC3B
PE11/
TIOC3D
High impedance state
Figure 8.115 Output-Level Detection Operation
Release from High-Impedance State
High-current pins that have entered high-impedance state due to input-level detection can be
released either by returning them to their initial state with a power-on reset, or by clearing all of
the bit 12 to 15 (POE0F to POE3F) flags of the ICSR1. High-current pins that have become high-
impedance due to output-level detection can be released either by returning them to their initial
state with a power-on reset, or by first clearing bit 9 (OCE) of the OCSR to disable output-level
compares, then clearing the bit 15 (OSF) flag. However, when returning from high-impedance
state by clearing the OSF flag, always do so only after outputting a high level from the high-
current pins (TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D). High-level outputs
can be achieved by setting the MTU internal registers.
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8. Multi-Function Timer Pulse Unit (MTU)
POE Timing
Figure 8.116 shows an example of timing from POE input to high impedance of pin.
Pφ
CK falling
POE input
Falling edge detected
PE9/
TIOC3B
High impedance state
Note: Other large-current pins (PE11/TICO3D, PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C,
PE15/TIOC4D/IRQOUT) also go to the high impedance state at the same timing
Figure 8.116 Falling Edge Detection Operation
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8. Multi-Function Timer Pulse Unit (MTU)
8.9.5 Usage Note
To set the POE pin as a level detection pin, a high level signal must be firstly input to the POE pin.
(1) Symptom
(a) Regarding the POEnF*1 bits
If setting of the POEnF bits in the input level control/status registers (ICSR1 and ICSR2) by the
hardware*2 and reading from these bits occur simultaneously, “0” will be read, where “1” should
be read.
Furthermore, if clearing of these bits is attempted subsequent to the above condition, the clearing
should be ignored*3 but it will be carried out.
Notes: *1 For the SH7046-Series and SH7047-Series, n = 0 to 6; for the SH7144-Series, n = 0 to
3.
*2 The POEnF bits are set when the signals input to the respective POEn pins satisfy the
conditions that are specified by the POEnM1 and POEnM0 of the ICSR1 and ICSR2.
*3 The correct operation is that clearing of the POEnF bits is only possible after “1” is
read from them in order to prevent accidental clearing.
(b) Regarding the OSF bit
The same symptom applies to the OSF bits of the output level control/status register (OCSR).
(2) To Avoid This Problem
Please clear the POEnF bits or the OSF bit in these steps: first execute a read for ICSR1, ICSR2,
or OCSR, then write “0” to the bits that had a read value of “1” to clear them while writing “1” to
other bits. If this procedure is not followed, the POEnF bits and the OSF bit may be cleared
unexpectedly if their setting by hardware and reading occur simultaneously.
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9. Watchdog Timer
Section 9 Watchdog Timer
The watchdog timer (WDT) is an 8-bit timer that can reset this LSI internally if the counter
overflows without rewriting the counter value due to a system crash or the like.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows.
The block diagram of the WDT is shown in figure 9.1.
9.1
Features
•
•
•
Selectable from eight counter input clocks.
Switchable between watchdog timer mode and interval timer mode
Clears software standby mode
In watchdog timer mode
•
•
Output WDTOVF signal
If the counter overflows, it is possible to select whether this LSI is internally reset or not.
In interval timer mode
If the counter overflows, the WDT generates an interval timer interrupt (ITI).
•
WDT0400A_010020030200
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9. Watchdog Timer
Overflow
φ/2
φ/64
Interrupt
control
ITI (interrupt
request signal)
φ/128
φ/256
φ/512
φ/1024
φ/4096
φ/8192
Clock
select
Clock
WDTOVF
Reset
control
Internal reset
signal*
Internal clock
sources
RSTCSR
TCNT
TSCR
Bus
interface
Module bus
WDT
Legend:
TCSR:
TCNT:
Timer control/status register
Timer counter
RSTCSR: Reset control/status register
Note: * The internal reset signal can be generated by making a register setting.
Power-on reset or manual reset can be selected.
Figure 9.1 Block Diagram of WDT
9.2
Input/Output Pin
Table 9.1 shows the pin configuration of the watchdog timer.
Table 9.1 Pin Configuration
Pin
Abbreviation I/O
Function
Watchdog timer overflow WDTOVF
O
Outputs the counter overflow signal in
watchdog timer mode
Note: The WDTOVF pin should not be pulled down. However, if it is necessary to pull this pin
down, a resistance of 1 MΩ or higher should be used.
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9. Watchdog Timer
9.3
Register Descriptions
The WDT has the following three registers. For details, refer to section 18, List of Registers. To
prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method
different from normal registers. For details, refer to section 9.6.1, Notes on Register Access.
•
•
•
Timer control/status register (TCSR)
Timer counter (TCNT)
Reset control/status register (RSTCSR)
9.3.1
Timer Counter (TCNT)
TCNT is an 8-bit readable/writable upcounter. When the timer enable bit (TME) in the timer
control/status register (TCSR) is set to 1, TCNT starts counting pulses of an internal clock selected
by clock select bits 2 to 0 (CKS2 to CKS0) in TCSR. When the value of TCNT overflows
(changes from H'FF to H'00), a watchdog timer overflow signal (WDTOVF) or interval timer
interrupt (ITI) is generated, depending on the mode selected in the WT/IT bit of TCSR.
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9. Watchdog Timer
9.3.2
Timer Control/Status Register (TCSR)
TCSR is an 8-bit readable/writable register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
Bit
Bit Name
Initial Value R/W
0
R/(W)*1 Overflow Flag
Indicates that TCNT has overflowed in interval timer
Description
7
OVF
mode. Only a write of 0 is permitted, to clear the
flag. This flag is not set in watchdog timer mode.
[Setting condition]
•
When TCNT overflows in interval timer mode.
[Clearing conditions]
•
•
Cleared by reading OVF
When 0 is written to the TME bit in interval timer
mode
6
WT/IT
0
R/W
Timer Mode Select
Selects whether the WDT is used as a watchdog
timer or interval timer. When TCNT overflows, the
WDT either generates an interval timer interrupt (ITI)
or generates a WDTOVF signal, depending on the
mode selected.
0: Interval timer mode
Interval timer interrupt (ITI) request to the CPU
when TCNT overflows
1: Watchdog timer mode
WDTOVF signal output externally when TCNT
overflows*2.
5
TME
0
R/W
Timer Enable
Enables or disables the timer.
0: Timer disabled
TCNT is initialized to H'00 and count-up stops
1: Timer enabled
TCNT starts counting. A WDTOVF signal or
interrupt is generated when TCNT overflows.
4, 3
⎯
All 1
R
Reserved
This bit is always read as 1, and should only be
written with 1.
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9. Watchdog Timer
Bit
Bit Name
Initial Value R/W
Description
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Select 2 to 0
Select one of eight internal clock sources for input to
TCNT. The clock signals are obtained by dividing the
frequency of the system clock (φ). The overflow
frequency for φ = 40 MHz is enclosed in
parentheses*3.
000: Clock φ/2 (frequency: 12.8 μs)
001: Clock φ/64 (frequency: 409.6 μs)
010: Clock φ/128 (frequency: 0.8 ms)
011: Clock φ/256 (frequency: 1.6 ms)
100: Clock φ/512 (frequency: 3.3 ms)
101: Clock φ/1024 (frequency: 6.6 ms)
110: Clock φ/4096 (frequency: 26.2 ms)
111: Clock φ/8192 (frequency: 52.4 ms)
Notes: 1. Only a 0 can be written after reading 1.
2. Section 9.3.3, Reset Control/Status Register (RSTCSR), describes in detail what
happens when TCNT overflows in watchdog timer mode.
3. The overflow interval listed is the time from when the TCNT begins counting at H'00
until an overflow occurs.
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9. Watchdog Timer
9.3.3
Reset Control/Status Register (RSTCSR)
RSTCSR is an 8-bit readable/writable register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal.
Initial
Bit
Bit Name Value
R/W
R/(W)* Watchdog Overflow Flag
This bit is set when TCNT overflows in watchdog timer
Description
7
WOVF 0
mode. This bit cannot be set in interval timer mode.
[Setting condition]
•
Set when TCNT overflows in watchdog timer mode
[Clearing condition]
•
Cleared by reading WOVF, and then writing 0 to
WOVF
6
5
RSTE
0
R/W
Reset Enable
Specifies whether or not a reset signal is generated in
the chip if TCNT overflows in watchdog timer mode.
0: Reset signal is not generated even if TCNT overflows
(Though this LSI is not reset, TCNT and TCSR in
WDT are reset)
1: Reset signal is generated if TCNT overflows
Reset Select
RSTS
0
R/W
Selects the type of internal reset generated if TCNT
overflows in watchdog timer mode.
0: Power-on reset
1: Manual reset
4 to 0
Note:
⎯
All 1
R
Reserved
These bits are always read as 1, and should only be
written with 1.
*
Only 0 can be written, for flag clearing.
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9. Watchdog Timer
9.4
Operation
9.4.1
Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/IT and TME bits of TCSR to 1. Software must
prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow
occurs. No TCNT overflows will occur while the system is operating normally, but if TCNT fails
to be rewritten and overflows occur due to a system crash or the like, a WDTOVF signal is output
externally. The WDTOVF signal can be used to reset the system. The WDTOVF signal is output
for 128 φ clock cycles.
If the RSTE bit in RSTCSR is set to 1, a signal to reset the chip will be generated internally
simultaneous to the WDTOVF signal when TCNT overflows. Either a power-on reset or a manual
reset can be selected by the RSTS bit in RSTCSR. The internal reset signal is output for 512 φ
clock cycles.
When a WDT overflow reset is generated simultaneously with a reset input at the RES pin, the
RES reset takes priority, and the WOVF bit in RSTCSR is cleared to 0.
The following are not initialized by a WDT reset signal:
•
•
•
POE (port output enable) of MTU registers
PFC (pin function controller) registers
I/O port registers
These registers are initialized only by an external power-on reset.
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9. Watchdog Timer
TCNT value
Overflow
H'FF
H'00
Time
WT/IT = 1 H'00 written
TME = 1 in TCNT
WOVF = 1 WT/IT = 1 H'00 written
TME = 1 in TCNT
WDTOVF and internal
reset generated
WDTOVF
signal
128 φ clocks
512 φ clocks
Internal reset
signal*
Legend:
WT/IT: Timer mode select bit
TME: Timer enable bit
Note: * Internal reset signal occurs only when the RSTE bit is set to 1.
Figure 9.2 Operation in Watchdog Timer Mode
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9. Watchdog Timer
9.4.2
Interval Timer Mode
To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1 in TCSR. An interval
timer interrupt (ITI) is generated each time the timer counter (TCNT) overflows. This function can
be used to generate interval timer interrupts at regular intervals.
TCNT value
Overflow
Overflow
Overflow
Overflow
H'FF
Time
H'00
WT/IT = 0
ITI
ITI
ITI
ITI
TME = 1
Legend:
ITI: Interval timer interrupt request generation
Figure 9.3 Operation in Interval Timer Mode
Clearing Software Standby Mode
9.4.3
The watchdog timer has a special function to clear software standby mode with an NMI interrupt
or IRQ0 to IRQ3 interrupts. When using software standby mode, set the WDT as described below.
Before Transition to Software Standby Mode: The TME bit in TCSR must be cleared to 0 to
stop the watchdog timer counter before entering software standby mode. The chip cannot enter
software standby mode while the TME bit is set to 1. Set bits CKS2 to CKS0 in TCSR so that the
counter overflow interval is equal to or longer than the oscillation settling time. See section 19.3,
AC Characteristics, for the oscillation settling time.
Recovery from Software Standby Mode: When an NMI signal or IRQ0 to IRQ3 signals are
received in software standby mode, the clock oscillator starts running and TCNT starts
incrementing at the rate selected by bits CKS2 to CKS0 before software standby mode was
entered. When TCNT overflows (changes from H'FF to H'00), the clock is presumed to be stable
and usable; clock signals are supplied to the entire chip and software standby mode ends.
For details on software standby mode, see section 17, Power-Down Modes.
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9. Watchdog Timer
9.4.4
Timing of Setting the Overflow Flag (OVF)
In interval timer mode, when TCNT overflows, the OVF bit of TCSR is set to 1 and an interval
timer interrupt (ITI) is simultaneously requested. Figure 9.4 shows this timing.
φ
H'FF H'00
TCNT
Overflow signal
(internal signal)
OVF
Figure 9.4 Timing of Setting OVF
9.4.5
Timing of Setting the Watchdog Timer Overflow Flag (WOVF)
When TCNT overflows in watchdog timer mode, the WOVF bit of RSTCSR is set to 1 and a
WDTOVF signal is output. When the RSTE bit in RSTCSR is set to 1, TCNT overflow enables an
internal reset signal to be generated for the entire chip. Figure 9.5 shows this timing.
φ
H'FF H'00
TCNT
Overflow signal
(internal signal)
WOVF
Figure 9.5 Timing of Setting WOVF
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9. Watchdog Timer
9.5
Interrupt Source
During interval timer mode operation, an overflow generates an interval timer interrupt (ITI). The
interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
Table 9.2 WDT Interrupt Source (in Interval Timer Mode)
Name
Interrupt Source
Interrupt Flag
ITI
TCNT overflow
OVF
9.6
Usage Notes
9.6.1
Notes on Register Access
The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write to. The procedures for writing to and reading these registers are given
below.
Writing to TCNT and TCSR: These registers must be written by a word transfer instruction.
They cannot be written by byte transfer instructions.
TCNT and TCSR both have the same write address. The write data must be contained in the lower
byte of the written word. The upper byte must be H'5A (for TCNT) or H'A5 (for TCSR) (figure
9.6). This transfers the write data from the lower byte to TCNT or TCSR.
• Writing to TCNT
15
8
7
0
H'5A
Address: H'FFFF8610
Write data
Write data
• Writing to TCSR
15
8
7
0
Address: H'FFFF8610
H'A5
Figure 9.6 Writing to TCNT and TCSR
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9. Watchdog Timer
Writing to RSTCSR: RSTCSR must be written by a word access to address H'FFFF8612. It
cannot be written by byte transfer instructions.
Procedures for writing 0 to WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are
different, as shown in figure 9.7.
To write 0 to the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower
byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the
RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The
values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively.
The WOVF bit is not affected.
• Writing 0 to the WOVF bit
15
8
7
0
Address: H'FFFF8612
H'A5
H'00
• Writing to the RSTE and RSTS bits
15
8
7
0
H'5A
Write data
Address: H'FFFF8612
Figure 9.7 Writing to RSTCSR
Reading from TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like other
registers. Use byte transfer instructions. The read addresses are H'FFFF8610 for TCSR,
H'FFFF8611 for TCNT, and H'FFFF8613 for RSTCSR.
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9. Watchdog Timer
9.6.2
TCNT Write and Increment Contention
If a timer counter increment clock pulse is generated during the T3 state of a write cycle to TCNT,
the write takes priority and the timer counter is not incremented. Figure 9.8 shows this operation.
TCNT write cycle
T
T
T
3
1
2
φ
Address
TCNT address
Internal write
signal
TCNT input
clock
TCNT
N
M
Counter write data
Figure 9.8 Contention between TCNT Write and Increment
Changing CKS2 to CKS0 Bit Values
9.6.3
If the values of bits CKS2 to CKS0 in the timer control/status register (TCSR) are rewritten while
the WDT is running, the count may not increment correctly. Always stop the watchdog timer (by
clearing the TME bit to 0) before rewriting the values of bits CKS2 to CKS0.
9.6.4
Changing between Watchdog Timer/Interval Timer Modes
To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0)
before switching between interval timer mode and watchdog timer mode.
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9. Watchdog Timer
9.6.5
System Reset by WDTOVF Signal
If a WDTOVF output signal is input to the RES pin, the chip cannot initialize correctly.
Avoid logical input of the WDTOVF signal to the RES input pin. To reset the entire system with
the WDTOVF signal, use the circuit shown in figure 9.9.
SH7101
Reset input
RES
Reset signal to entire system
WDTOVF
Figure 9.9 Example of System Reset Circuit Using WDTOVF Signal
9.6.6
Internal Reset in Watchdog Timer Mode
If the RSTE bit is cleared to 0 in watchdog timer mode, the chip will not be reset internally when a
TCNT overflow occurs, but TCNT and TCSR in the WDT will be reset.
9.6.7
Manual Reset in Watchdog Timer Mode
When an internal reset is effected by TCNT overflow in watchdog timer mode, the processor waits
until the end of the bus cycle at the time of manual reset generation before making the transition to
manual reset exception processing.
9.6.8
Notes on Using WDTOVF pin
The WDTOVF pin should not be pulled down. However, if it is necessary to pull this pin down, a
resistance of 1 MΩ or higher should be used.
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10. Serial Communication Interface (SCI)
Section 10 Serial Communication Interface (SCI)
This LSI has two independent serial communication interface (SCI) channels. The SCI can handle
both asynchronous and clocked synchronous serial communication. In asynchronous serial
communication mode, serial data communication can be carried out with standard asynchronous
communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or
Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial
communication between processors (multiprocessor communication function).
10.1
Features
•
•
Choice of asynchronous or clocked synchronous serial communication mode
Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously.
Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data.
•
On-chip baud rate generator allows any bit rate to be selected
External clock can be selected as a transfer clock source.
•
•
Choice of LSB-first or MSB-first transfer* (except in the case of asynchronous mode 7-bit
data)
Four interrupt sources
Four interrupt sources ⎯ transmit-end, transmit-data-empty, receive-data-full, and receive
error ⎯ that can issue requests.
•
Module standby mode can be set
Asynchronous mode
•
•
•
•
•
•
Data length: 7 or 8 bits
Stop bit length: 1 or 2 bits
Parity: Even, odd, or none
Multiprocessor bit: 1 or 0
Receive error detection: Parity, overrun, and framing errors
Break detection: Break can be detected by reading the RxD pin level directly in case of a
framing error
SCIS200B_010020030200
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10. Serial Communication Interface (SCI)
Clocked Synchronous mode
•
•
Data length: 8 bits
Receive error detection: Overrun errors detected
Note: * The description in this section are based on LSB-first transfer.
Figure 10.1 shows a block diagram of the SCI.
Internal
data bus
Module data bus
RDR
RSR
TDR
TSR
SSR
SCR
BRR
Pφ
Pφ/8
Pφ/32
Pφ/128
SMR
SDCR
Baud rate
generator
RxD
TxD
Transmission/
reception
control
Parity generation
Parity check
Clock
External clock
SCK
TEI
TXI
RXI
ERI
Legend:
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
SCR: Serial control register
SSR: Serial status register
BRR: Bit rate register
SDCR: Serial direction control register
Figure 10.1 Block Diagram of SCI
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10. Serial Communication Interface (SCI)
10.2
Input/Output Pins
Table 10.1 shows the SCI pin configuration.
Table 10.1 Pin Configuration
Channel
Pin Name*
SCK2
RxD2
I/O
Function
2
I/O
SCI2 clock input/output
SCI2 receive data input
SCI2 transmit data output
SCI3 clock input/output
SCI3 receive data input
SCI3 transmit data output
Input
Output
I/O
TxD2
3
SCK3
RxD3
Input
Output
TxD3
Note:
*
Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the
channel designation.
10.3
Register Descriptions
The SCI has the following registers for each channel. For details on register addresses and register
states during each processing, refer to section 18, List of Registers.
Channel 2
•
•
•
•
•
•
•
Serial Mode Register_2 (SMR_2)
Bit Rate Register_2 (BRR_2)
Serial Control Register_2 (SCR_2)
Transmit Data Register_2 (TDR_2)
Serial Status Register_2 (SSR_2)
Receive Data Register_2 (RDR_2)
Serial Direction Control Register_2 (SDCR_2)
Channel 3
•
•
•
•
•
Serial Mode Register_3 (SMR_3)
Bit Rate Register_3 (BRR_3)
Serial Control Register_3 (SCR_3)
Transmit Data Register_3 (TDR_3)
Serial Status Register_3 (SSR_3)
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10. Serial Communication Interface (SCI)
•
•
Receive Data Register_3 (RDR_3)
Serial Direction Control Register_3 (SDCR_3)
10.3.1
Receive Shift Register (RSR)
RSR is a shift register used to receive serial data that is input to the RxD pin and convert it into
parallel data. When one byte of data has been received, it is transferred to RDR automatically.
RSR cannot be directly read or written to by the CPU.
10.3.2
Receive Data Register (RDR)
RDR is an 8-bit register that stores receive data. When the SCI has received one byte of serial
data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR is
receive-enabled. Since RSR and RDR function as a double buffer in this way, enables continuous
receive operations to be performed. After confirming that the RDRF bit in SSR is set to 1, read
RDR for only once. RDR cannot be written to by the CPU. The initial value of RDR is H'00.
10.3.3
Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first
transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be
directly accessed by the CPU.
10.3.4
Transmit Data Register (TDR)
TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it
transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered
structures of TDR and TSR enables continuous serial transmission. If the next transmit data has
already been written to TDR during serial transmission, the SCI transfers the written data to TSR
to continue transmission. Although TDR can be read or written to by the CPU at all times, to
achieve reliable serial transmission, write transmit data to TDR for only once after confirming that
the TDRE bit in SSR is set to 1. The initial value of TDR is H'FF.
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10. Serial Communication Interface (SCI)
10.3.5
Serial Mode Register (SMR)
SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source.
Initial
Bit
Bit Name Value
R/W
Description
7
C/A
0
R/W
Communication Mode
0: Asynchronous mode
1: Clocked synchronous mode
6
5
CHR
0
R/W
R/W
Character Length (enabled only in asynchronous mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length. LSB-first is fixed and
the MSB (bit 7) of TDR is not transmitted in
transmission.
In clocked synchronous mode, a fixed data length of 8
bits is used.
PE
0
Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to transmit
data before transmission, and the parity bit is checked in
reception. For a multiprocessor format, parity bit addition
and checking are not performed regardless of the PE bit
setting.
4
3
O/E
0
0
R/W
R/W
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
STOP
Stop Bit Length (enabled only in asynchronous mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
In reception, only the first stop bit is checked. If the
second stop bit is 0, it is treated as the start bit of the
next transmit character.
2
MP
0
R/W
Multiprocessor Mode (enabled only in asynchronous
mode)
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit and O/E
bit settings are invalid in multiprocessor mode.
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10. Serial Communication Interface (SCI)
Initial
Bit
Bit Name Value
R/W
Description
1
0
CKS1
CKS0
0
0
R/W
R/W
Clock Select 1 and 0
These bits select the clock source for the baud rate
generator.
00: Pφ clock (n = 0)
01: Pφ/8 clock (n = 1)
10: Pφ/32 clock (n = 2)
11: Pφ/128 clock (n = 3)
For the relation between the bit rate register setting and
the baud rate, see section 10.3.9, Bit Rate Register
(BRR). n is the decimal display of the value of n in BRR
(see section 10.3.9, Bit Rate Register (BRR)).
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10. Serial Communication Interface (SCI)
10.3.6
Serial Control Register (SCR)
SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt
requests, and selection of the transfer clock source. For details on interrupt requests, refer to
section 10.7, Interrupts Sources.
Initial
Bit
Bit Name Value
R/W
Description
7
TIE
0
0
R/W
Transmit Interrupt Enable
When this bit is set to 1, TXI interrupt request is enabled.
6
RIE
R/W
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
5
4
3
TE
0
0
0
R/W
R/W
R/W
Transmit Enable
When this bit is set to 1, transmission is enabled.
RE
Receive Enable
When this bit is set to 1, reception is enabled.
MPIE
Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and ORER status flags in SSR is prohibited.
On receiving data in which the multiprocessor bit is 1, this
bit is automatically cleared and normal reception is
resumed. For details, refer to section 10.5,
Multiprocessor Communication Function.
2
TEIE
0
R/W
Transmit End Interrupt Enable
This bit is set to 1, TEI interrupt request is enabled.
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10. Serial Communication Interface (SCI)
Initial
Bit
Bit Name Value
R/W
Description
1
0
CKE1
CKE0
0
0
R/W
R/W
Clock Enable 1 and 0
Selects the clock source and SCK pin function.
Asynchronous mode:
00: Internal clock, SCK pin used for input pin (input signal
is ignored) or output pin (output level is undefined)
01: Internal clock, SCK pin used for clock output (The
output clock frequency is the same as the bit rate)
10: External clock, SCK pin used for clock input (The
input clock frequency is 16 times the bit rate)
11: External clock, SCK pin used for clock input (The
input clock frequency is 16 times the bit rate)
Clocked synchronous mode:
00: Internal clock, SCK pin used for synchronous clock
output
01: Internal clock, SCK pin used for synchronous clock
output
10: External clock, SCK pin used for synchronous clock
input
11: External clock, SCK pin used for synchronous clock
input
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10. Serial Communication Interface (SCI)
10.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared.
Initial
Bit
Bit Name Value
R/W
Description
7
TDRE 1
R/(W)* Transmit Data Register Empty
Displays whether TDR contains transmit data.
[Setting conditions]
•
•
•
Power-on reset or software standby mode
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and data
can be written to TDR
[Clearing condition]
When 0 is written to TDRE after reading TDRE = 1
R/(W)* Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
•
6
RDRF
0
•
When serial reception ends normally and receive data
is transferred from RSR to RDR
[Clearing conditions]
•
•
Power-on reset or software standby mode
When 0 is written to RDRF after reading RDRF = 1
The RDRF flag is not affected and retains their previous
values when the RE bit in SCR is cleared to 0.
5
ORER
0
R/(W)* Overrun Error
[Setting condition]
•
When the next serial reception is completed while
RDRF = 1
[Clearing conditions]
•
•
Power-on reset or software standby mode
When 0 is written to ORER after reading ORER = 1
The ORER flag is not affected and retains their previous
values when the RE bit in SCR is cleared to 0.
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10. Serial Communication Interface (SCI)
Initial
Bit
Bit Name Value
R/W
Description
4
FER
0
R/(W)* Framing Error
[Setting condition]
•
When the stop bit is 0
[Clearing conditions]
•
•
Power-on reset or software standby mode
When 0 is written to FER after reading FER = 1
In 2-stop-bit mode, only the first stop bit is checked.
The FER flag is not affected and retains their previous
values when the RE bit in SCR is cleared to 0.
3
PER
0
R/(W)* Parity Error
[Setting condition]
When a parity error is detected during reception
[Clearing conditions]
•
•
•
Power-on reset or software standby mode
When 0 is written to PER after reading PER = 1
The PER flag is not affected and retains their previous
values when the RE bit in SCR is cleared to 0.
2
TEND
1
R
Transmit End
[Setting conditions]
•
•
•
Power-on reset or software standby mode
When the TE bit in SCR is 0
When TDRE = 1 at transmission of the last bit of a 1-
byte serial transmit character
[Clearing condition]
When 0 is written to TDRE after reading TDRE = 1
•
1
MPB
0
0
R
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive data.
When the RE bit in SCR is cleared to 0 its previous state
is retained.
0
MPBT
R/W
Multiprocessor Bit Transfer
MPBT sets the multiprocessor bit value to be added to
the transmit data.
Note:
*
Only 0 can be written, for flag clearing.
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10. Serial Communication Interface (SCI)
10.3.8
Serial Direction Control Register (SDCR)
The DIR bit in the serial direction control register (SDCR) selects LSB-first or MSB-first transfer.
With an 8-bit data length, LSB-first/MSB-first selection is available regardless of the
communication mode. With a 7-bit data length, LSB-first transfer must be selected. The
description in this section assumes LSB-first transfer.
Initial
Bit
Bit Name Value
R/W
Description
7 to 4
⎯
All 1
R
Reserved
The write value must always be 1. Operation cannot be
guaranteed if 0 is written.
3
DIR
0
R/W
Data Transfer Direction
Selects the serial/parallel conversion format. Valid for an
8-bit transmit/receive format.
0: TDR contents are transmitted in LSB-first order
Receive data is stored in RDR in LSB-first
1: TDR contents are transmitted in MSB-first order
Receive data is stored in RDR in MSB-first
2
⎯
0
R
Reserved
The write value must always be 0. Operation cannot be
guaranteed if 1 is written.
1
0
⎯
⎯
1
0
R
R
Reserved
This bit is always read as 1, and cannot be modified.
Reserved
The write value must always be 0. Operation cannot be
guaranteed if 1 is written.
10.3.9
Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 10.2 shows
the relationships between the N setting in BRR and the effective bit rate B0 for asynchronous and
clocked synchronous modes. The initial value of BRR is H'FF, and it can be read or written to by
the CPU at all times.
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10. Serial Communication Interface (SCI)
Table 10.2 Relationships between N Setting in BRR and Effective Bit Rate B0
Mode
Bit Rate
Error
Asynchronous mode
(n = 0)
Pφ × 106
32 × 22n × (N + 1)
B
0
⎞
⎠
⎞
B0 =
Error (%) =
– 1 × 100
⎠
B1
Asynchronous mode
(n = 1 to 3)
Pφ × 106
32 × 22n+1 × (N + 1)
B
⎞
⎠
⎞
0
Error (%) =
– 1 × 100
B0 =
B0 =
B0 =
⎠
B1
Clocked synchronous
mode (n = 0)
Pφ × 106
4 × 22n × (N + 1)
⎯
Clocked synchronous
mode (n = 1 to 3)
Pφ × 106
4 × 22n+1 × (N + 1)
⎯
Notes: B0: Effective bit rate (bit/s) Actual transfer speed according to the register settings
B1: Logical bit rate (bit/s) Specified transfer speed of the target system
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
Pφ: Peripheral clock operating frequency (MHz)
n : Determined by the SMR settings shown in the following tables.
SMR Setting
CKS1
CKS0
n
0
1
2
3
0
0
1
1
0
1
0
1
Table 10.3 shows sample N settings in BRR in normal asynchronous mode. Table 10.4 shows the
maximum bit rate for each frequency in normal asynchronous mode. Table 10.6 shows sample N
settings in BRR in clocked synchronous mode. For details, refer to section 10.4.2, Receive Data
Sampling Timing and Reception Margin in Asynchronous Mode. Tables 10.5 and 10.7 show the
maximum bit rates with external clock input.
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10. Serial Communication Interface (SCI)
Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode)
Operating Frequency Pφ (MHz)
4
6
8
10
12
Logical
Bit Rate
(bit/s)
Error
(%)
Error
(%)
Error
(%)
Error
(%)
Error
(%)
n
N
n
N
n
N
n
N
n
N
110
1
1
1
1
1
0
0
0
0
0
0
0
0
140 0.74
103 0.16
1
1
1
1
0
0
0
0
0
0
0
0
0
212 0.03
155 0.16
2
2
2
2
1
1
0
0
0
0
0
0
0
70
51
25
12
25
12
51
25
16
12
8
0.03
0.16
0.16
0.16
0.16
0.16
0.16
0.16
2.12
0.16
–3.55
0.00
–6.99
2
2
1
1
1
0
0
0
0
0
0
0
0
88
64
–0.25
0.16
2
2
2
1
1
0
0
0
0
0
0
0
0
106 –0.44
150
77
38
77
38
0.16
0.16
0.16
0.16
300
51
25
12
51
25
12
8
0.16
0.16
0.16
0.16
0.16
0.16
–3.55
–6.99
8.51
0.00
8.51
77
38
0.16
0.16
129 0.16
600
64
32
0.16
1200
2400
4800
9600
14400
19200
28800
31250
38400
155 0.16
–1.36
77
38
19
12
9
0.16
129 0.16
155 0.16
0.16
64
32
21
15
10
9
0.16
77
38
25
19
12
11
9
0.16
0.16
0.16
–2.34
0.16
0.00
–2.34
–2.34
0.16
–1.36
–1.36
1.73
6
–2.34
–6.99
0.00
3
6
–1.36
0.00
3
5
7
2
4
–2.34
6
7
1.73
Operating Frequency Pφ (MHz)
14
16
18
20
22
Logical
Bit Rate
(bit/s)
Error
(%)
Error
(%)
Error
(%)
Error
(%)
Error
(%)
n
N
n
N
n
N
n
N
n
N
110
2
2
2
2
1
1
0
0
0
0
0
0
0
123 0.23
2
2
2
1
1
0
0
0
0
0
0
0
0
141 0.03
103 0.16
2
2
2
1
1
0
0
0
0
0
0
0
0
159 –0.12
116 0.16
2
2
2
1
1
1
0
0
0
0
0
0
0
177 –0.25
129 0.16
2
2
2
1
1
1
0
0
0
0
0
0
0
194 0.16
142 0.16
150
90
45
22
45
22
90
45
29
22
14
13
10
0.16
300
–0.93
–0.93
–0.93
–0.93
0.16
51
103 0.16
51 0.16
0.16
58
116 0.16
58 –0.69
–0.69
64
0.16
71
–0.54
600
129 0.16
142 0.16
1200
2400
4800
9600
14400
19200
28800
31250
38400
64
32
0.16
71
35
–0.54
–0.54
207 0.16
103 0.16
233 0.16
116 0.16
–1.36
129 0.16
142 0.16
–0.93
1.27
51
34
25
16
15
12
0.16
–0.79
0.16
2.12
0.00
0.16
58
38
28
19
17
14
–0.69
0.16
64
42
32
21
19
15
0.16
0.94
–1.36
–1.36
0.00
1.73
71
47
35
23
21
17
–0.54
–0.54
–0.54
–0.54
0.00
–0.93
1.27
1.02
–2.34
0.00
0.00
3.57
–2.34
–0.54
Rev.2.00 Sep. 27, 2007 Page 289 of 448
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10. Serial Communication Interface (SCI)
Operating Frequency Pφ (MHz)
26
24
25
28
30
Logical
Bit Rate
(bit/s)
Error
(%)
Error
Error
Error
(%)
Error
(%)
n
N
n
N
(%)
n
N
(%)
n
N
n
N
110
2
2
2
1
1
1
0
0
0
0
0
0
0
212 0.03
155 0.16
2
2
2
1
1
1
0
0
0
0
0
0
0
221 –0.02
162 –0.15
2
2
2
1
1
1
0
0
0
0
0
0
0
230 –0.08
168 0.16
2
2
2
1
1
1
0
0
0
0
0
0
0
248 –0.17
181 0.16
3
2
2
2
1
1
0
0
0
0
0
0
0
66
–0.62
150
194 0.16
300
77
0.16
80
0.47
84
–0.43
90
0.16
97
48
97
48
–0.35
–0.35
–0.35
–0.35
600
155 0.16
162 –0.15
168 0.16
181 0.16
1200
2400
4800
9600
14400
19200
28800
31250
38400
77
38
0.16
0.16
80
40
0.47
84
41
–0.43
0.76
90
45
0.16
–0.76
–0.93
155 0.16
162 –0.15
168 0.16
181 0.16
194 0.16
77
51
38
25
23
19
0.16
0.16
0.16
0.16
0.00
–2.34
80
53
40
26
24
19
0.47
0.47
–0.76
0.47
0.00
1.73
84
55
41
27
25
20
–0.43
0.76
0.76
0.76
0.00
0.76
90
60
45
29
27
22
0.16
97
64
48
32
29
23
–0.35
0.16
–0.39
–0.93
1.27
–0.35
–1.36
0.00
0.00
–0.93
1.73
Operating Frequency Pφ (MHz)
32
34
36
38
40
Logical
Bit Rate
(bit/s)
Error
(%)
Error
(%)
Error
(%)
Error
(%)
Error
(%)
n
N
n
N
n
N
n
N
n
N
110
3
2
2
2
1
1
0
0
0
0
0
0
0
70
0.03
3
2
2
2
1
1
0
0
0
0
0
0
0
74
0.62
3
2
2
2
1
1
0
0
0
0
0
0
0
79
–0.12
3
2
2
2
1
1
0
0
0
0
0
0
0
83
0.40
3
3
2
2
1
1
1
0
0
0
0
0
0
88
64
–0.25
0.16
150
207 0.16
103 0.16
220 0.16
233 0.16
116 0.16
246 0.16
300
110 –0.29
123 –0.24
129 0.16
64 0.16
129 0.16
600
51
103 0.16
51 0.16
0.16
54
110 –0.29
51 6.42
0.62
58
116 0.16
58 –0.69
–0.69
61
123 –0.24
61 –0.24
–0.24
1200
2400
4800
9600
14400
19200
28800
31250
38400
64
32
0.16
207 0.16
103 0.16
220 0.16
234 –0.27
116 0.16
246 0.16
–1.36
110 –0.29
123 –0.24
129 0.16
68
51
34
31
25
0.64
0.16
–0.79
0.00
0.16
73
54
36
33
27
–0.29
0.62
77
58
38
35
28
0.16
–0.69
0.16
0.00
1.02
81
61
40
37
30
0.57
86
64
42
39
32
–0.22
0.16
–0.24
0.57
–0.29
0.00
0.94
0.00
0.00
–1.18
–0.24
–1.36
Rev.2.00 Sep. 27, 2007 Page 290 of 448
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10. Serial Communication Interface (SCI)
Table 10.4 Maximum Bit Rate for Each Frequency when Using Baud Rate Generator
(Asynchronous Mode)
Pφ (MHz)
4
n
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
N
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Maximum Bit Rate (bit/s)
125000
8
250000
10
12
14
16
18
20
22
24
25
26
28
30
32
34
36
38
40
312500
375000
437500
500000
562500
625000
687500
750000
781250
812500
875000
937500
1000000
1062500
1125000
1187500
1250000
Rev.2.00 Sep. 27, 2007 Page 291 of 448
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10. Serial Communication Interface (SCI)
Table 10.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
Pφ (MHz)
4
External Clock (MHz)
1.0000
Maximum Bit Rate (bit/s)
62500
6
1.5000
93750
8
2.0000
125000
10
12
14
16
18
20
22
24
25
26
28
30
32
34
36
38
40
2.5000
156250
3.0000
187500
3.5000
218750
4.0000
250000
4.5000
281250
5.0000
312500
5.5000
343750
6.0000
375000
6.2500
390625
6.5000
406250
7.0000
437500
7.5000
468750
8.0000
500000
8.5000
531250
9.0000
562500
9.5000
593750
10.0000
625000
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10. Serial Communication Interface (SCI)
Table 10.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
Operating Frequency Pφ (MHz)
4
6
8
10
N
12
N
Logical Bit
Rate (bit/s)
n
N
n
N
n
N
n
n
250
2
124
249
124
49
24
99
39
19
9
2
187
⎯
2
249
124
249
99
49
24
9
⎯
2
⎯
155
⎯
124
⎯
249
99
49
24
9
⎯
2
⎯
187
⎯
149
74
⎯
14
59
29
11
5
500
1
⎯
1
2
1000
1
187
74
⎯
1
⎯
1
⎯
1
2500
1
1
1
5000
1
⎯
0
1
⎯
0
1
10000
25000
50000
100000
250000
500000
1000000
2500000
5000000
0
149
59
29
14
5
1
⎯
1
0
0
1
0
0
0
1
4
0
0
0
0
0
19
7
0
0
0
3
0
0
0
0
0
1
0
2
0
3
0
4
0
0
0
⎯
⎯
⎯
⎯
0
1
⎯
0
⎯
0
0
2
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Operating Frequency Pφ (MHz)
14
N
16
N
18
20
N
22
N
Logical Bit
Rate (bit/s)
n
n
n
N
n
n
250
500
3
2
108
218
108
174
⎯
⎯
139
69
3
2
124
249
124
49
24
49
19
9
3
⎯
2
140
⎯
140
224
112
⎯
3
⎯
2
155
⎯
155
249
124
⎯
24
99
49
19
9
3
⎯
3
171
⎯
42
⎯
137
⎯
219
109
54
21
10
⎯
1000
2
2
2500
1
2
1
1
⎯
1
5000
⎯
⎯
0
2
1
1
10000
25000
50000
100000
250000
500000
1000000
2500000
5000000
1
⎯
0
⎯
1
⎯
0
1
179
89
0
1
0
0
0
0
34
1
4
0
44
0
0
0
13
1
1
0
17
0
0
0
6
1
0
0
8
0
0
⎯
⎯
⎯
⎯
⎯
⎯
0
3
⎯
⎯
⎯
⎯
⎯
⎯
0
4
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0
1
⎯
⎯
0
0
Rev.2.00 Sep. 27, 2007 Page 293 of 448
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10. Serial Communication Interface (SCI)
Operating Frequency Pφ (MHz)
24
N
25
N
26
28
N
30
N
Logical Bit
Rate (bit/s)
n
n
n
N
n
n
250
3
187
⎯
3
194
⎯
3
202
101
202
⎯
3
218
108
218
⎯
3
233
116
233
⎯
500
⎯
2
⎯
2
3
3
3
1000
187
74
149
74
29
14
59
23
11
5
194
⎯
2
2
2
2500
2
⎯
1
⎯
1
⎯
1
⎯
1
5000
1
155
⎯
162
⎯
174
⎯
187
⎯
10000
25000
50000
100000
250000
500000
1000000
2500000
5000000
1
⎯
0
⎯
⎯
0
⎯
1
⎯
⎯
0
1
249
124
⎯
⎯
34
⎯
1
0
129
64
0
139
69
149
74
0
⎯
0
0
0
0
0
24
0
25
0
27
0
29
0
⎯
⎯
⎯
⎯
⎯
0
12
0
13
0
14
0
⎯
⎯
⎯
⎯
⎯
0
6
⎯
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
2
⎯
⎯
⎯
⎯
⎯
⎯
Operating Frequency Pφ (MHz)
32
N
34
N
36
38
N
40
N
Logical Bit
Rate (bit/s)
n
n
n
N
n
n
250
3
249
124
249
99
49
24
9
⎯
3
⎯
⎯
3
⎯
⎯
3
⎯
⎯
3
⎯
500
3
132
⎯
140
⎯
147
⎯
155
⎯
1000
2
⎯
2
⎯
2
⎯
2
⎯
2
2500
2
105
212
105
⎯
112
224
112
44
118
237
118
⎯
124
249
124
49
24
99
39
19
9
5000
2
1
1
1
1
10000
25000
50000
100000
250000
500000
1000000
2500000
5000000
2
1
1
1
1
2
⎯
0
1
⎯
0
1
2
4
169
84
0
179
89
189
94
1
1
9
0
0
0
0
1
3
0
33
0
35
0
37
0
1
1
0
16
0
17
0
18
0
1
0
⎯
⎯
⎯
⎯
0
8
⎯
⎯
⎯
⎯
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0
3
⎯
⎯
⎯
0
1
Rev.2.00 Sep. 27, 2007 Page 294 of 448
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10. Serial Communication Interface (SCI)
Table 10.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)
Pφ (MHz)
External Clock (MHz)
0.6667
Maximum Bit Rate (bit/s)
666666.7
4
6
1.0000
1000000.0
1333333.3
1666666.7
2000000.0
2333333.3
2666666.7
3000000.0
3333333.3
3666666.7
4000000.0
4166666.7
4333333.3
4666666.7
5000000.0
5333333.3
5666666.7
6000000.0
6333333.3
6666666.7
8
1.3333
10
12
14
16
18
20
22
24
25
26
28
30
32
34
36
38
40
Legend:
1.6667
2.0000
2.3333
2.6667
3.0000
3.3333
3.6667
4.0000
4.1667
4.3333
4.6667
5.0000
5.3333
5.6667
6.0000
6.3333
6.6667
⎯ : Can be set, but there will be a degree of error.
* : Continuous transfer is not possible.
Note: Settings with an error of 1% or less are recommended.
Rev.2.00 Sep. 27, 2007 Page 295 of 448
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10. Serial Communication Interface (SCI)
10.4
Operation in Asynchronous Mode
Figure 10.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by data, a parity bit, and finally stop bits (high level). In
asynchronous serial communication, the transmission line is usually held in the mark state (high
level). The SCI monitors the communication line, and when it goes to the space state (low level),
recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver
are independent units, enabling full-duplex communication. Both the transmitter and the receiver
also have a double-buffered structure, so that data can be read or written during transmission or
reception, enabling continuous data transfer.
Idle state
(mark state)
1
LSB
D0
MSB
D7
1
Serial
data
0
D1
D2
D3
D4
D5
D6
0/1
1
1
Start
bit
Parity
bit
Stop bit
Transmit/receive data
7 or 8 bits
1 bit
1 bit 1 or 2 bits
or
none
One unit of transfer data (character or frame)
Figure 10.2 Data Format in Asynchronous Communication (Example with 8-Bit Data,
Parity, Two Stop Bits)
10.4.1
Data Transfer Format
Table 10.8 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected according to the SMR setting. For details on the multiprocessor
bit, refer to section 10.5, Multiprocessor Communication Function.
Rev.2.00 Sep. 27, 2007 Page 296 of 448
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10. Serial Communication Interface (SCI)
Table 10.8 Serial Transfer Formats (Asynchronous Mode)
SMR Settings
Serial Transfer Format and Frame Length
CHR
PE
MP
STOP
1
2
3
4
5
6
7
8
9
10 11 12
0
0
0
0
S
8-bit data
8-bit data
8-bit data
8-bit data
STOP
0
0
0
1
1
1
1
0
0
1
0
1
1
0
0
1
1
X
X
X
X
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
S
S
S
S
S
S
S
S
S
S
S
STOP STOP
P
P
STOP
STOP STOP
7-bit data
STOP
7-bit data
7-bit data
7-bit data
STOP STOP
P
P
STOP
STOP STOP
8-bit data
MPB STOP
8-bit data
MPB STOP STOP
7-bit data
MPB STOP
1
7-bit data
MPB STOP STOP
Legend:
S:
STOP: Stop bit
P: Parity bit
MPB: Multiprocessor bit
X: Don't care
Start bit
Rev.2.00 Sep. 27, 2007 Page 297 of 448
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10. Serial Communication Interface (SCI)
10.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of
the basic clock as shown in figure 10.3. Thus the reception margin in asynchronous mode is given
by formula (1) below.
1
2N
(D – 0.5)
N
× 100%
M = 0.5 –
–
– (L – 0.5) F
........................... Formula (1)
Where M: Reception margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin is given by formula
below.
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
16 clocks
8 clocks
0
7
15
0
7
15
0
Internal basic
clock
Receive data
(RxD)
D0
D1
Start bit
Synchronization
sampling timing
Data sampling
timing
Figure 10.3 Receive Data Sampling Timing in Asynchronous Mode
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10. Serial Communication Interface (SCI)
10.4.3
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in
SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the
clock frequency should be 16 times the bit rate used.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is in the middle of the transmit data, as shown in figure 10.4.
The clock must not be stopped during operation.
SCK
0
D0 D1 D2 D3 D4 D5 D6 D7 0/1
1 frame
1
1
TxD
Figure 10.4 Relation between Output Clock and Transmit Data Phase
(Asynchronous Mode)
Rev.2.00 Sep. 27, 2007 Page 299 of 448
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10. Serial Communication Interface (SCI)
10.4.4 SCI Initialization (Asynchronous Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as described below. When the operating mode, transfer format, etc., is changed,
the TE and RE bits must be cleared to 0 before making the change using the following procedure.
When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does
not initialize the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.
When the external clock is used in asynchronous mode, the clock must be supplied even during
initialization.
Start transmission
[1] Set the clock selection in SCR.
[2] Set the data transfer format in SMR
and SCMR.
[3] Write a value corresponding to the
bit rate to BRR. Not necessary if an
external colck is used.
Clear RIE, TIE, TEIE, MPIE,
TE and RE bits in SCR to 0*
[4] Set the RIE, TIE, TEIE, and MPIE
bits.
[5] Set PFC of the external pin used.
Set RxD input during receiving and
TxD output during transmitting. Set
SCK input/output according to
contents set by CKE1 and CKE0.
When CKE1 and CKE0 are 0 in
asynchronous mode, setting the
SCK pin is unnecessary.
Set CKE1 and CKE0 bits in SCR
(TE and RE bits are 0)
[1]
Set data transfer format in
SMR
[2]
[3]
Set value in BRR
Wait
Outputting clocks from the SCK pin
starts at synchronous clock output
setting.
No
[6] Wait at least one bit interval, then
set the TE bit or RE bit in SCR to
1.* At this time, the TxD, RxD, and
SCK pins can be used. The TxD
pin is in a mark state during
transmitting, and RxD pin is in an
idle state for waiting the start bit
during receiving.
1-bit interval elapsed?
Yes
Set the RIE, TIE, TEIE,
and MPIE bits in SCR
[4]
Set PFC of the external pin used
SCK, TxD, RxD
[5]
[6]
Set TE and RE bits of SCR to 1
< Initialization completion>
Note: * In simultaneous transmit/receive operation, the TE and RE bits must be cleared to 0 or set to 1
simultaneously.
Figure 10.5 Sample SCI Initialization Flowchart
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10. Serial Communication Interface (SCI)
10.4.5
Data Transmission (Asynchronous Mode)
Figure 10.6 shows an example of the operation for transmission in asynchronous mode. In
transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if is cleared to 0, recognizes that data has been
written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request
(TXI) is generated. Because the TXI interrupt routine writes the next transmit data to TDR
before transmission of the current transmit data has finished, continuous transmission can be
enabled.
3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or
multiprocessor bit (may be omitted depending on the format), and stop bit.
4. The SCI checks the TDRE flag at the timing for sending the stop bit.
5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
serial transmission of the next frame is started.
6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark
state” is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI
interrupt request is generated.
Figure 10.7 shows a sample flowchart for transmission in asynchronous mode.
Start
bit
Data
Parity Stop Start
Data
Parity Stop
1
1
bit
bit bit
bit
bit
Idle state
(mark state)
0
D0 D1
D7 0/1
1
0
D0 D1
D7 0/1
1
TxD
TDRE
TEND
TXI interrupt
request
generated
Data written to TDR
and TDRE flag cleared
to 0 in TXI interrupt
processing routine
TXI interrupt
request
generated
TEI interrupt
request
generated
1 frame
Figure 10.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)
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10. Serial Communication Interface (SCI)
[1] SCI initialization:
Initialization
[1]
[2]
Set the TxD pin using the PFC.
After the TE bit is set to 1, 1 is
output for one frame, and
transmission is enabled. However,
data is not transmitted.
Start transmission
Read TDRE flag in SSR
[2] SCI status check and transmit data
write:
No
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
TDRE = 1
Yes
Write transmit data to TDR
and clear TDRE flag in SSR to 0
[3] Serial transmission continuation
procedure:
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear
the TDRE flag to 0.
No
All data transmitted?
Yes
[3]
[4] Break output at the end of serial
transmission:
Read TEND flag in SSR
To output a break in serial
transmission, first clear the port
data register (DR) to 0, then clear
the TE bit to 0 in SCR and use the
PFC to select the TxD pin as an
output port.
No
No
TEND = 1
Yes
[4]
Break output?
Yes
Clear DR to 0
Clear TE bit in SCR to 0;
select the TxD pin
as an output port with the PFC
<End>
Figure 10.7 Sample Serial Transmission Flowchart
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10. Serial Communication Interface (SCI)
Serial Data Reception (Asynchronous Mode)
10.4.6
Figure 10.8 shows an example of the operation for reception in asynchronous mode. In serial
reception, the SCI operates as described below.
1. The SCI monitors the communication line, and if a start bit is detected, performs internal
synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
2. If an overrun error (when reception of the next data is completed while the RDRF flag is still
set to 1) occurs, the OER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an
ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated.
4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive
data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt
request is generated.
5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt processing routine reads the receive data transferred to
RDR before reception of the next receive data has finished, continuous reception can be
enabled.
Start
bit
Data
Parity Stop Start
Data
Parity Stop
1
1
bit
bit bit
bit
bit
Idle state
(mark state)
0
D0 D1
D7 0/1
1
0
D0 D1
D7 0/1
1
RxD
RDRF
FER
RXI interrupt
request
generated
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
processing routine
ERI interrupt
request generated
by framing error
1 frame
Figure 10.8 Example of SCI Operation in Reception (Example with 8-Bit Data,
Parity, One Stop Bit)
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10. Serial Communication Interface (SCI)
Table 10.9 shows the states of the SSR status flags and receive data handling when a receive error
is detected. If a receive error is detected, the RDRF flag retains its state before receiving data.
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 10.9 shows a sample flow chart
for serial data reception.
Table 10.9 SSR Status Flags and Receive Data Handling
SSR Status Flag
RDRF* OER
FER
PER
Receive Data
Lost
Receive Error Type
Overrun error
1
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
1
1
Transferred to RDR
Transferred to RDR
Lost
Framing error
Parity error
Overrun error + framing error
Overrun error + parity error
Framing error + parity error
Lost
Transferred to RDR
Lost
Overrun error + framing error +
parity error
Note:
*
The RDRF flag retains its state before data reception.
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10. Serial Communication Interface (SCI)
[1] SCI initialization:
Initialization
[1]
Set the RxD pin using the PFC.
[2] [3] Receive error processing and break
detection:
Start reception
If a receive error occurs, read the
ORER, PER, and FER flags in SSR to
identify the error. After performing the
appropriate error processing, ensure
that the ORER, PER, and FER flags are
all cleared to 0. Reception cannot be
resumed if any of these flags are set to
1. In the case of a framing error, a
break can be detected by reading the
value of the input port corresponding to
Read ORER, PER, and
FER flags in SSR
[2]
Yes
PER ∨ FER ∨ ORER = 1
[3]
Error processing
(Continued on next page)
No
the RxD pin.
[4]
Read RDRF flag in SSR
[4] SCI status check and receive data read:
Read SSR and check that RDRF = 1,
then read the receive data in RDR and
clear the RDRF flag to 0. Transition of
the RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
No
RDRF = 1
Yes
[5] Serial reception continuation procedure:
To continue serial reception, before the
stop bit for the current frame is
Read receive data in RDR, and
clear RDRF flag in SSR to 0
received, read the RDRF flag, read
RDR, and clear the RDRF flag to 0.
No
All data received?
Yes
[5]
Clear RE bit in SCR to 0
<End>
Figure 10.9 Sample Serial Reception Data Flowchart (1)
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10. Serial Communication Interface (SCI)
[3]
Error processing
No
ORER = 1
Yes
Overrun error processing
No
FER = 1
Yes
Yes
Break?
No
Framing error processing
Clear RE bit in SCR to 0
No
PER = 1
Yes
Parity error processing
Clear ORER, PER, and
FER flags in SSR to 0
<End>
Figure 10.9 Sample Serial Reception Data Flowchart (2)
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10. Serial Communication Interface (SCI)
10.5
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer to be performed among a
number of processors sharing communication lines by means of asynchronous serial
communication using the multiprocessor format, in which a multiprocessor bit is added to the
transfer data. When multiprocessor communication is carried out, each receiving station is
addressed by a unique ID code. The serial communication cycle consists of two component
cycles: an ID transmission cycle which specifies the receiving station, and a data transmission
cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the
data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if
the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 10.10 shows an example
of inter-processor communication using the multiprocessor format. The transmitting station first
sends the ID code of the receiving station with which it wants to perform serial communication as
data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor
bit added. The receiving station skips data until data with a 1 multiprocessor bit is sent. When data
with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID.
The station whose ID matches then receives the data sent next. Stations whose ID does not match
continue to skip data until data with a 1 multiprocessor bit is again received.
The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1,
transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags,
RDRF, FER, and OER to 1 are inhibited until data with a 1 multiprocessor bit is received. On
reception of receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and the
MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to
1 at this time, an RXI interrupt is generated.
When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings
are the same as those in normal asynchronous mode. The clock used for multiprocessor
communication is the same as that in normal asynchronous mode.
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10. Serial Communication Interface (SCI)
Transmitting
station
Serial transmission line
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
Serial
data
H'01
H'AA
(MPB = 1)
(MPB = 0)
ID transmission cycle =
receiving station
specification
Data transmission cycle =
Data transmission to
receiving station specified
by ID
Legend:
MPB: Multiprocessor bit
Figure 10.10 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)
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10. Serial Communication Interface (SCI)
10.5.1
Multiprocessor Serial Data Transmission
Figure 10.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same
as those in asynchronous mode.
[1] SCI initialization:
Initialization
[1]
Set the TxD pin using the PFC.
After the TE bit is set to 1, 1 is
output for one frame, and
transmission is enabled.
Start transmission
Read TDRE flag in SSR
[2]
However, data is not transmitted.
[2] SCI status check and transmit
data write:
No
TDRE = 1
Yes
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
Write transmit data to TDR and
set MPBT bit in SSR
[3] Serial transmission continuation
procedure:
Clear TDRE flag to 0
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
possible, then write data to TDR,
and then clear the TDRE flag to
0.
No
All data transmitted?
Yes
[3]
[4] Break output at the end of serial
transmission:
Read TEND flag in SSR
To output a break in serial
transmission, first clear the port
data register (DR) to 0, then
clear the TE bit to 0 in SCR and
use the PFC to select the TxD
pin as an output port.
No
No
TEND = 1
Yes
Break output?
[4]
Yes
Clear DR to 0
Clear TE bit in SCR to 0;
select the TxD pin
as an output port with the PFC
<End>
Figure 10.11 Sample Multiprocessor Serial Transmission Flowchart
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10. Serial Communication Interface (SCI)
10.5.2 Multiprocessor Serial Data Reception
Figure 10.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data
with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is
generated at this time. All other SCI operations are the same as in asynchronous mode. Figure
10.12 shows an example of SCI operation for multiprocessor format reception.
Start
bit
Data (ID1)
Stop Start
Data (Data1)
Stop
bit
bit
bit
1
MPB
1
MPB
0
1
RxD
0
D0
D1
D7
1
0
D0
D1
D7
1
Idle state
(mark state)
MPIE
RDRF
RDR
value
ID1
If not this station's ID, RXI interrupt request is
MPIE = 0
RXI interrupt
request
(multiprocessor
interrupt)
RDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
MPIE bit is set to 1
again
not generated, and RDR
retains its state
generated
processing routine
(a) Data does not match station's ID
Start
bit
Data (ID2)
D1 D7
Stop Start
Data (Data2)
D1 D7
Stop
bit
1
1
bit
bit
MPB
1
MPB
0
RxD
0
D0
1
0
D0
1
Idle state
(mark state)
MPIE
RDRF
RDR
value
ID1
MPIE = 0
ID2
Data2
RXI interrupt
request
(multiprocessor
interrupt)
RDR data read and Matches this station's ID,
RDRF flag cleared so reception continues,
to 0 in RXI interrupt and data is received in RXI
processing routine interrupt processing routine
MPIE bit is set to 1
again
generated
(b) Data matches station's ID
Figure 10.12 Example of SCI Operation in Reception (Example with 8-Bit Data,
Multiprocessor Bit, One Stop Bit)
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10. Serial Communication Interface (SCI)
[1] SCI initialization:
Initialization
[1]
[2]
Set the RxD pin using the PFC.
[2] ID reception cycle:
Start reception
Set the MPIE bit in SCR to 1.
[3] SCI status check, ID reception and
comparison:
Set MPIE bit in SCR to 1
Read ORER and FER flags
in SSR
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and compare it with this
station's ID.
If the data is not this station's ID, set the
MPIE bit to 1 again, and clear the RDRF
flag to 0.
Yes
[3]
FER ∨ ORER = 1
No
Read RDRF flag in SSR
If the data is this station's ID, clear the
RDRF flag to 0.
No
No
[4] SCI status check and data reception:
Read SSR and check that the RDRF
flag is set to 1, then read the data in
RDR.
RDRF = 1
Yes
Read receive data in RDR
[5] Receive error processing and break
detection:
If a receive error occurs, read the ORER
and FER flags in SSR to identify the
error. After performing the appropriate
error processing, ensure that the ORER
and FER flags are all cleared to 0.
Reception cannot be resumed if either
of these flags is set to 1.
This station's ID?
Yes
Read ORER and FER flags
in SSR
In the case of a framing error, a break
can be detected by reading the RxD pin
value.
Yes
FER ∨ ORER = 1
No
Read RDRF flag in SSR
[4]
No
RDRF = 1
Yes
Read receive data in RDR
No
[5]
All data received?
Error processing
Yes
(Continued on
next page)
Clear RE bit in SCR to 0
<End>
Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (1)
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10. Serial Communication Interface (SCI)
[5]
Error processing
No
ORER = 1
Yes
Overrun error processing
No
FER = 1
Yes
Yes
Break?
No
Framing error processing
Clear RE bit in SCR to 0
Clear ORER and FER flags
in SSR to 0
<End>
Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (2)
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10. Serial Communication Interface (SCI)
10.6
Operation in Clocked Synchronous Mode
Figure 10.14 shows the general format for clocked synchronous communication. In clocked
synchronous mode, data is transmitted or received in synchronization with clock pulses. Data is
transferred in 8-bit units. In clocked synchronous serial communication, data on the transmission
line is output from one falling edge of the serial clock to the next. In clocked synchronous mode,
the SCI receives data in synchronization with the rising edge of the serial clock. After 8-bit data is
output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or
multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units,
enabling full-duplex communication by use of a common clock. Both the transmitter and the
receiver also have a double-buffered structure, so that data can be read or written during
transmission or reception, enabling continuous data transfer.
One unit of transfer data (character or frame)
*
*
Synchronization
clock
LSB
Bit 0
MSB
Bit 7
Serial data
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Don't care
Note: * High except in continuous transfer
Don't care
Figure 10.14 Data Format in Clocked Synchronous Communication (For LSB-First)
10.6.1
Clock
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK pin can be selected, according to the setting of CKE1 and
CKE0 bits in SCR. When the SCI is operated on an internal clock, the serial clock is output from
the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no
transfer is performed, the clock is fixed high.
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10. Serial Communication Interface (SCI)
10.6.2 SCI Initialization (Clocked Synchronous Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as described in a sample flowchart in figure 10.15. When the operating mode,
transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the
change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1.
Note that clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags, or the
contents of RDR.
[1] Set the clock selection in SCR.
Start initialization
[2] Set the data transfer format in SMR.
[3] Write a value corresponding to the bit
rate to BRR. Not necessary if an
external clock is used.
Clear RIE, TIE, TEIE, MPIE,
TE and RE bits in SCR to 0*
[4] Set the RIE, TIE TEIE, and MPIE bits.
Set CKE1 and CKE0 bits in SCR
(TE and RE bits are 0)
[1]
[5] Set PFC of the external pin used. Set
RxD input during receiving and TxD
output during transmitting. Set SCK
input/output according to contents set
by CKE1 and CKE0.
Set data transfer format in
SMR
[2]
[3]
[6] Wait at least one bit interval, then set
the TE bit or RE bit in SCR to 1.* At this
time, the TxD, RxD, and SCK pins can
be used. The TxD pin is in a mark state
during transmitting. When synchronous
clock output (clock master) is set during
receiving in synchronous mode,
outputting clocks from the SCK pin
starts.
Set value in BRR
Wait
No
1-bit interval elapsed?
Yes
Set the RIE, TIE, TEIE, and
MPIE bits in SCR
[4]
[5]
[6]
Set PFC of the external pin used
SCK, TxD, RxD
Set TE and RE bits of SCR to 1
<Transfer start>
Note: * In simultaneous transmit and receive operations, the TE and RE bits should both be
cleared to 0 or set to 1 simultaneously.
Figure 10.15 Sample SCI Initialization Flowchart
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10. Serial Communication Interface (SCI)
Serial Data Transmission (Clocked Synchronous Mode)
10.6.3
Figure 10.16 shows an example of SCI operation for transmission in clocked synchronous mode.
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been
written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty (TXI)
interrupt request is generated. Because the TXI interrupt routine writes the next transmit data
to TDR before transmission of the current transmit data has finished, continuous transmission
can be enabled.
3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock
mode has been specified and synchronized with the input clock when use of an external clock
has been specified.
4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintains the
output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt
request is generated. The SCK pin is fixed high.
Figure 10.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1.
Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the
RE bit to 0 does not clear the receive error flags.
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10. Serial Communication Interface (SCI)
Transfer
direction
Synchroniza-
tion clock
Serial data
Bit 0
Bit 1
Bit 0
Bit 4
Bit 5
Bit 6
Bit 7
TDRE
TEND
TXI interrupt Data written to TDR
TXI interrupt
generated
TEI interrupt
request
generated
request
and TDRE flag cleared request
generated
to 0 in TXI interrupt
processing routine
1 frame
Figure 10.16 Sample SCI Transmission Operation in Clocked Synchronous Mode
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10. Serial Communication Interface (SCI)
[1] SCI initialization:
Initialization
[1]
[2]
Set the TxD pin using the PFC.
[2] SCI status check and transmit data
write:
Start transmission
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
Read TDRE flag in SSR
No
No
[3] Serial transmission continuation
procedure:
TDRE = 1
Yes
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0.
Write transmit data to TDR and
clear TDRE flag in SSR to 0
All data transmitted?
Yes
[3]
Read TEND flag in SSR
No
TEND = 1
Yes
Clear TE bit in SCR to 0
<End>
Figure 10.17 Sample Serial Transmission Flowchart
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10. Serial Communication Interface (SCI)
10.6.4 Serial Data Reception (Clocked Synchronous Mode)
Figure 10.18 shows an example of SCI operation for reception in clocked synchronous mode. In
serial reception, the SCI operates as described below.
1. The SCI performs internal initialization in synchronization with a synchronization clock input
or output, starts receiving data, and stores the received data in RSR.
2. If an overrun error (when reception of the next data is completed while the RDRF flag is still
set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time,
an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt processing routine reads the receive data transferred to
RDR before reception of the next receive data has finished, continuous reception can be
enabled.
Synchroniza-
tion clock
Serial data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RDRF
ORER
ERI interrupt
request generated
by overrun error
RXI interrupt
request
generated
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
processing routine
RXI interrupt
request
generated
1 frame
Figure 10.18 Example of SCI Operation in Reception
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10. Serial Communication Interface (SCI)
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 10.19 shows a sample
flowchart for serial data reception.
[1] SCI initialization:
Initialization
[1]
Set the RxD pin using the PFC.
[2] [3] Receive error processing:
If a receive error occurs, read the
ORER flag in SSR, and after
Start reception
performing the appropriate error
processing, clear the ORER flag to 0.
Transfer cannot be resumed if the
ORER flag is set to 1.
[2]
[3]
Read ORER flag in SSR
Yes
ORER = 1
No
[4] SCI status check and receive data
read:
Error processing
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and clear the RDRF flag
to 0.
(Continued below)
Read RDRF flag in SSR
[4]
Transition of the RDRF flag from 0 to 1
can also be identified by an RXI
interrupt.
No
RDRF = 1
Yes
[5] Serial reception continuation
procedure:
To continue serial reception, before
the MSB (bit 7) of the current frame is
received, reading the RDRF flag,
reading RDR, and clearing the RDRF
flag to 0 should be finished.
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
Yes
[5]
Clear RE bit in SCR to 0
<End>
[3]
Error processing
Overrun error processing
Clear ORER flag in SSR to 0
<End>
Figure 10.19 Sample Serial Reception Flowchart
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10. Serial Communication Interface (SCI)
10.6.5
Simultaneous Serial Data Transmission and Reception (Clocked Synchronous
Mode)
Figure 10.20 shows a sample flowchart for simultaneous serial transmit and receive operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations after the SCI initialization. To switch from transmit mode to simultaneous transmit and
receive mode, after checking that the SCI has finished transmission and the TDRE and TEND
flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction.
To switch from receive mode to simultaneous transmit and receive mode, after checking that the
SCI has finished reception, clear RE to 0. Then after checking that the RDRF and receive error
flags (ORER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single
instruction.
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10. Serial Communication Interface (SCI)
[1] SCI initialization:
Initialization
[1]
[2]
Set the TxD and RxD pins using the PFC.
Start transmission/reception
[2] SCI status check and transmit data write:
Read SSR and check that the TDRE flag
is set to 1, then write transmit data to
TDR and clear the TDRE flag to 0.
Read TDRE flag in SSR
Transition of the TDRE flag from 0 to 1
can also be identified by a TXI interrupt.
No
TDRE = 1
Yes
[3] Receive error processing:
If a receive error occurs, read the ORER
flag in SSR, and after performing the
appropriate error processing, clear the
ORER flag to 0. Transmission/reception
cannot be resumed if the ORER flag is
set to 1.
Write transmit data to TDR and
clear TDRE flag in SSR to 0
Read ORER flag in SSR
ORER = 1
[4] SCI status check and receive data read:
Read SSR and check that the RDRF flag
is set to 1, then read the receive data in
RDR and clear the RDRF flag to 0.
Yes
[3]
Transition of the RDRF flag from 0 to 1
can also be identified by an RXI interrupt.
Error processing
[4]
No
[5] Serial transmission/reception continuation
procedure:
Read RDRF flag in SSR
To continue serial transmission/
reception, before the MSB (bit 7) of the
current frame is received, finish reading
the RDRF flag, reading RDR, and
clearing the RDRF flag to 0. Also, before
the MSB (bit 7) of the current frame is
transmitted, read 1 from the TDRE flag to
confirm that writing is possible. Then
write data to TDR and clear the TDRE
flag to 0.
No
No
RDRF = 1
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
All data received?
[5]
Yes
Clear TE and RE bits in SCR to 0
<End>
Note: When switching from transmit or receive operation to simultaneous transmit and receive operations,
first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously.
Figure 10.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
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10. Serial Communication Interface (SCI)
10.7
Interrupts Sources
10.7.1
Interrupts in Normal Serial Communication Interface Mode
Table 10.10 shows the interrupt sources in normal serial communication interface mode. A
different interrupt vector is assigned to each interrupt source, and individual interrupt sources can
be enabled or disabled using the enable bits in SCR.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND
flag in SSR is set to 1, a TEI interrupt request is generated.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated.
A TEI interrupt is generated when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI
interrupt and a TXI interrupt are generated simultaneously, the TXI interrupt has priority for
acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the
TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later.
Table 10.10 SCI Interrupt Sources
Channel
Name
ERI_2
RXI_2
TXI_2
TEI_2
ERI_3
RXI_3
TXI_3
TEI_3
Interrupt Source
Receive Error
Interrupt Flag
ORER, FER, PER
RDRF
2
Receive Data Full
Transmit Data Empty
Transmission End
Receive Error
TDRE
TEND
3
ORER, FER, PER
RDRF
Receive Data Full
Transmit Data Empty
Transmission End
TDRE
TEND
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10. Serial Communication Interface (SCI)
10.8
Usage Notes
10.8.1
TDR Write and TDRE Flag
The TDRE bit in the serial status register (SSR) is a status flag indicating transferring of transmit
data from TDR into TSR. The SCI sets the TDRE bit to 1 when it transfers data from TDR to TSR.
Data can be written to TDR regardless of the TDRE bit status.
If new data is written in TDR when TDRE is 0, however, the old data stored in TDR will be lost
because the data has not yet been transferred to TSR. Before writing transmit data to TDR, be sure
to check that the TDRE bit is set to 1.
10.8.2
Module Standby Mode Setting
SCI operation can be disabled or enabled using the module standby control register. The initial
setting is for SCI operation to be halted. Register access is enabled by clearing module standby
mode. For details, refer to section 17, Power-Down Modes.
10.8.3
Break Detection and Processing (Asynchronous Mode Only)
When framing error detection is performed, a break can be detected by reading the RxD pin value
directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the
PER flag may also be set. Note that, since the SCI continues the receive operation after receiving
a break, even if the FER flag is cleared to 0, it will be set to 1 again.
10.8.4
Sending a Break Signal (Asynchronous Mode Only)
The TxD pin becomes of the I/O port general I/O pin with the I/O direction and level determined
by the port data register (DR) and the port I/O register (IOR) of the pin function controller (PFC).
These conditions allow break signals to be sent.
The DR value is substituted for the marking status until the PFC is set. Consequently, the output
port is set to initially output a 1.
To send a break in serial transmission, first clear the DR to 0, then establish the TxD pin as an
output port using the PFC.
When the TE bit is cleared to 0, the transmission section is initialized regardless of the present
transmission status.
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10. Serial Communication Interface (SCI)
10.8.5 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
10.8.6
Cautions on Clocked Synchronous External Clock Mode
1. Set TE = RE = 1 only when external clock SCK is 1.
2. Do not set TE = RE = 1 until at least four Pφ clocks after external clock SCK has changed
from 0 to 1.
3. When receiving, RDRF is 1 when RE is cleared to 0 after 2.5–3.5 Pφ clocks from the rising
edge of the RxD D7 bit SCK input, but copying to RDR is not possible.
10.8.7
Caution on Clocked Synchronous Internal Clock Mode
When receiving, RDRF is 1 when RE is cleared to 0 after 1.5 Pφ clocks from the rising edge of the
RxD D7 bit SCK output, but copying to RDR is not possible.
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11. A/D Converter
Section 11 A/D Converter
This LSI includes a successive approximation type 10-bit A/D converter. The block diagram of the
A/D converter is shown in figure 11.1.
11.1
Features
•
•
10-bit resolution
Input channels
⎯ 8 channels (two independent A/D conversion modules)
Conversion time: 6.7 μs per channel (at Pφ = 20-MHz operation)
5.4 µs per channel (at Pφ = 25-MHz operation)
Three operating modes
•
•
⎯ Single mode: Single-channel A/D conversion
⎯ Continuous scan mode: 1 to 4 channels
⎯ Single-cycle scan mode: 1 to 4 channels
Data registers
•
⎯ Conversion results are held in a 16-bit data register for each channel
Sample and hold function
•
•
Three methods for conversion start
⎯ Software
⎯ Conversion start trigger from multifunction timer pulse unit (MTU)
⎯ External trigger signal
•
•
Interrupt source
⎯ An A/D conversion end interrupt request (ADI) can be generated
Module standby mode can be set
ADCMS20B_010020030200
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11. A/D Converter
Module data bus
Internal data bus
AVCC
10-bit D/A
AVSS
Pφ/4
+
AN8
Pφ/8
•
Comparator
Control circuit
Pφ/16
Pφ/32
•
•
Sample-and-
hold circuit
•
•
•
ADI
interrupt signal
AN15
Conversion start
trigger from MTU
ADTRG
Legend:
ADCR: A/D control register
ADCSR: A/D control/status register
ADTSR: A/D trigger select register
ADDR8–ADDR15: A/D data register 8 to 15
Note: The register number corresponds to the channel number of the module.
Figure 11.1 Block Diagram of A/D Converter (For One Module)
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11. A/D Converter
11.2
Input/Output Pins
Table 11.1 summarizes the input pins used by the A/D converter. This LSI has two A/D
conversion modules, each of which can be operated independently. The input channels are divided
into four channel sets.
Table 11.1 Pin Configuration
Module Type
Pin Name
AVCC
I/O
Function
Common
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Analog block power supply and reference voltage
Analog block ground and reference voltage
A/D external trigger input pin
AVSS
ADTRG
AN8
A/D module 0
(A/D0)
Analog input pin 8
Analog input pin 9
Analog input pin 10
Analog input pin 11
Analog input pin 12
Analog input pin 13
Analog input pin 14
Analog input pin 15
Group 1
AN9
AN10
AN11
AN12
AN13
AN14
AN15
A/D module 1
(A/D1)
Group 1
Note: The connected A/D module differs for each pin. The control registers of each module must
be set.
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11. A/D Converter
11.3
Register Descriptions
The A/D converter has the following registers. For details on register addresses and register states
in each operating mode, refer to section 18, List of Registers.
•
•
•
•
•
•
•
•
•
•
•
•
•
A/D data register 8 (H/L) (ADDR8)
A/D data register 9 (H/L) (ADDR9)
A/D data register 10 (H/L) (ADDR10)
A/D data register 11 (H/L) (ADDR11)
A/D data register 12 (H/L) (ADDR12)
A/D data register 13 (H/L) (ADDR13)
A/D data register 14 (H/L) (ADDR14)
A/D data register 15 (H/L) (ADDR15)
A/D control/status register_0 (ADCSR_0)
A/D control/status register_1 (ADCSR_1)
A/D control register_0 (ADCR_0)
A/D control register_1 (ADCR_1)
A/D trigger select register (ADTSR)
11.3.1
A/D Data Registers 8 to 15 (ADDR8 to ADDR15)
ADDR are 16-bit read-only registers. The conversion result for each analog input channel is stored
in ADDR with the corresponding number. (For example, the conversion result of AN8 is stored in
ADDR8.)
The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0.
The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read
directly from the CPU, however the lower byte should be read via a temporary register. The
temporary register contents are transferred from the ADDR when the upper byte data is read.
When reading ADDR, read only the upper byte, or read in word unit. ADDR are initialized to
H'0000.
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11. A/D Converter
A/D Control/Status Registers_0 and _1 (ADCSR_0 and ADCSR_1)
11.3.2
ADCSR for each module controls A/D conversion operations.
Initial
Bit
Bit Name Value
R/W
Description
7
ADF
0
R/(W)* A/D End Flag
A status flag that indicates the end of A/D conversion.
[Setting conditions]
•
•
When A/D conversion ends in single mode
When A/D conversion ends on all specified channels
in scan mode
[Clearing condition]
When 0 is written after reading ADF = 1
•
6
ADIE
0
R/W
A/D Interrupt Enable
The A/D conversion end interrupt (ADI) request is
enabled when 1 is set.
When changing the operating mode, first clear the
ADST bit in the A/D control registers (ADCR) to 0.
5
4
ADM1
ADM0
0
0
R/W
R/W
A/D Mode 1 and 0
Select the A/D conversion mode.
00: Single mode
01: 4-channel scan mode
10: Setting prohibited
11: Setting prohibited
When changing the operating mode, first clear the
ADST bit in the A/D control registers (ADCR) to 0.
3
⎯
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
2
1
0
CH2
CH1
CH0
0
0
0
R/W
R/W
R/W
Channel Select 2 to 0
Select analog input channels. See table 11.2.
When changing the operating mode, first clear the
ADST bit in the A/D control registers (ADCR) to 0.
Note:
*
Only 0 can be written to clear the flag.
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11. A/D Converter
Table 11.2 Channel Select List
Analog Input Channels
4-Channel Scan Mode*
Bit 2 Bit 1 Bit 0
Single Mode
A/D1
CH2
CH1
CH0
A/D0
AN8
A/D0
A/D1
1
0
0
1
0
1
AN12
AN8
AN12
AN9
AN13
AN8, AN9
AN8 to AN10
AN8 to AN11
AN12, AN13
AN12 to AN14
AN12 to AN15
1
AN10
AN11
AN14
AN15
Note:
*
Continuous scan mode or single-cycle scan mode can be selected with the ADCS bit.
11.3.3
A/D Control Registers_0 and _1 (ADCR_0 and ADCR_1)
ADCR for each module controls A/D conversion started by an external trigger signal and selects
the operating clock.
Initial
Bit
Bit Name Value
R/W
Description
7
TRGE
0
R/W
Trigger Enable
Enables or disables triggering of A/D conversion by
ADTRG or an MTU trigger.
0: A/D conversion triggering is disabled
1: A/D conversion triggering is enabled
6
5
CKS1
CKS0
0
0
R/W
R/W
Clock Select 0 and 1
Select the A/D conversion time.
00: Pφ/32
01: Pφ/16
10: Pφ/8
11: Pφ/4
When changing the A/D conversion time, first clear the
ADST bit in the A/D control registers (ADCR) to 0.
CKS [1,0] = b'11 can be set while Pφ ≤ 25 MHz.
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11. A/D Converter
Initial
Bit
Bit Name Value
R/W
Description
4
ADST
0
R/W
A/D Start
Starts or stops A/D conversion. When this bit is set to 1,
A/D conversion is started. When this bit is cleared to 0,
A/D conversion is stopped and the A/D converter enters
the idle state. In single or single-cycle scan mode, this bit
is automatically cleared to 0 when A/D conversion ends
on the selected single channel. In continuous scan mode,
A/D conversion is continuously performed for the
selected channels in sequence until this bit is cleared by
a software, reset, or in software standby mode, or
module standby mode.
3
ADCS
0
R/W
A/D Continuous Scan
Selects either single-cycle scan or continuous scan in
scan mode. This bit is valid only when scan mode is
selected.
0: Single-cycle scan
1: Continuous scan
When changing the operating mode, first clear the ADST
bit in the A/D control registers (ADCR) to 0.
2 to 0
⎯
All 1
R
Reserved
These bits are always read as 1. The write value should
always be 1.
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11. A/D Converter
11.3.4
A/D Trigger Select Register (ADTSR)
ADTSR enables an A/D conversion started by an external trigger signal.
Initial
Bit
Bit Name Value
R/W
Description
7 to 4
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
3
2
TRG1S1
TRG1S0
0
0
R/W
R/W
AD Trigger 1 Select 1 and 0
Enable the start of A/D conversion by A/D1 with a trigger
signal.
00: A/D conversion start by external trigger pin (ADTRG)
or MTU trigger is enabled
01: A/D conversion start by external trigger pin (ADTRG)
is enabled
10: A/D conversion start by MTU trigger is enabled
11: Setting prohibited
When changing the operating mode, first clear the TRGE
and ADST bits in the A/D control registers (ADCR) to 0.
1
0
TRG0S1
TRG0S0
0
0
R/W
R/W
AD Trigger 0 Select 1 and 0
Enable the start of A/D conversion by A/D0 with a trigger
signal.
00: A/D conversion start by external trigger pin (ADTRG)
or MTU trigger is enabled
01: A/D conversion start by external trigger pin (ADTRG)
is enabled
10: A/D conversion start by MTU trigger is enabled
11: Setting prohibited
When changing the operating mode, first clear the TRGE
and ADST bits in the A/D control registers (ADCR) to 0.
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11. A/D Converter
11.4
Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes; single mode and scan mode. There are two kinds of scan mode: continuous
mode and single-cycle mode. When changing the operating mode or analog input channel, in order
to prevent incorrect operation, first clear the ADST bit to 0 in ADCR. The ADST bit can be set at
the same time when the operating mode or analog input channel is changed.
11.4.1
Single Mode
In single mode, A/D conversion is to be performed only once on the specified single channel. The
operations are as follows.
1. A/D conversion is started when the ADST bit in ADCR is set to 1, according to software,
MTU, or external trigger input.
2. When A/D conversion is completed, the result is transferred to the A/D data register
corresponding to the channel.
3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at
this time, an ADI interrupt request is generated.
4. The ADST bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADST
bit is automatically cleared to 0 and the A/D converter enters the idle state.
When the ADST bit is cleared to 0 during A/D conversion, A/D conversion stops and the A/D
converter enters the idle state.
11.4.2
Continuous Scan Mode
In continuous scan mode, A/D conversion is to be performed sequentially on the specified
channels (four channels maximum). The operations are as follows.
1. When the ADST bit in ADCR is set to 1 by software, MTU, or external trigger input, A/D
conversion starts on the channel with the lowest number in the group (AN8, AN9, ..., AN11).
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
the A/D data register corresponding to each channel.
3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1.
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends.
Conversion of the first channel in the group starts again.
4. Steps 2 to 3 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops and the A/D converter enters the idle state.
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11. A/D Converter
Figure 11.2 Operation Example in Continuous Scan Mode (Three Channels Selected)
(AN8 to AN10)
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11. A/D Converter
11.4.3
Single-Cycle Scan Mode
In single-cycle scan mode, A/D conversion is to be performed once on the specified channels (four
channels maximum). Operations are as follows.
1. When the ADST bit in ADCR is set to 1 by a software, MTU, or external trigger input, A/D
conversion starts on the channel with the lowest number in the group (AN8, AN9, ..., AN11).
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
the A/D data register corresponding to each channel.
3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1.
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends.
4. After A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter
enters the idle state. When the ADST bit is cleared to 0 during A/D conversion, A/D
conversion stops and the A/D converter enters the idle state.
11.4.4
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit for each module. The A/D converter
samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST
bit in ADCR is set to 1, then starts conversion. Figure 11.3 shows the A/D conversion timing.
Table 11.3 shows the A/D conversion time.
As indicated in figure 11.3, the A/D conversion time (tCONV) includes tD and the input sampling time
(tSPL). The length of tD varies depending on the timing of the write access to ADCR. The total
conversion time therefore varies within the ranges indicated in table 11.3.
In scan mode, the values given in table 11.3 apply to the first conversion time. The values given
in table 11.4 apply to the second and subsequent conversions.
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11. A/D Converter
A/D conversion time (tCONV
)
A/D conversion start
Analog input
delay time(tD)
sampling time(tSPL)
Write cycle
A/D synchronization time
(Up to
(3 states)
59 states)
Pφ
Address
Internal write
signal
ADST write timing
Analog input
sampling
signal
Idle state
Sample-and-hold A/D conversion
A/D converter
ADF
End of A/D conversion
Figure 11.3 A/D Conversion Timing
Table 11.3 A/D Conversion Time (Single Mode)
CKS1 = 0
CKS1 = 1
CKS0 = 0
CKS0 = 1
CKS0 = 0
CKS0 = 1
Item
Symbol Min Typ Max Min Typ Max
Min Typ Max Min Typ Max
A/D conversion
start delay time
tD
31
⎯
62
15
⎯
30
7
⎯
64
⎯
14
3
⎯
32
⎯
6
Input sampling
time
tSPL
tCONV
⎯
256
⎯
⎯
128
⎯
⎯
⎯
259
⎯
⎯
131
⎯
134
A/D conversion
time
1024 ⎯
1055 515
530
266
Note: All values represent the number of states for Pφ.
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11. A/D Converter
Table 11.4 A/D Conversion Time (Scan Mode)
CKS1
CKS0
Conversion Time (State)
0
0
1
0
1
1024 (Fixed)
512 (Fixed)
256 (Fixed)
128 (Fixed)
1
11.4.5
A/D Converter Activation by MTU
The A/D converter can be independently activated by an A/D conversion request from the interval
timer of the MTU.
To activate the A/D converter by the MTU, set the A/D trigger select register (ADTSR). When the
TRGS1 and TRGS0 bits in ADTSR are set to 00 or 01, if an A/D conversion request from the
interval timer of the MTU occurs, the ADST bit in ADCR is automatically set to 1. The timing
from setting of the ADST bit until the start of A/D conversion is the same as when 1 is written to
the ADST bit by software.
11.4.6
External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS0 and TRGS1 bits are set to 00 or 01
in ADTSR, external trigger input is enabled at the ADTRG pin. A falling edge of the ADTRG pin
sets the ADST bit to 1 in ADCR, starting A/D conversion. Other operations, in both single and
scan modes, are the same as when the ADST bit has been set to 1 by software. Figure 11.4 shows
the timing.
CK
ADTRG
External trigger
signal
ADST
A/D conversion
Figure 11.4 External Trigger Input Timing
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11. A/D Converter
11.5
Interrupt Sources
The A/D converter generates an A/D conversion end interrupt (ADI) upon the completion of A/D
conversion. ADI interrupt requests are enabled when the ADIE bit is set to 1 while the ADF bit in
ADCSR is set to 1 after A/D conversion is completed.
The A/D converter can generate an A/D conversion end interrupt request. The ADI interrupt can
be enabled by setting the ADIE bit in the A/D control/status register (ADCSR) to 1, or disabled by
clearing the ADIE bit to 0.
Table 11.5 A/D Converter Interrupt Source
Name
Interrupt Source
Interrupt Source Flag
ADI
A/D conversion completed
ADF
11.6
Definitions of A/D Conversion Accuracy
This LSI's A/D conversion accuracy definitions are given below.
•
•
•
Resolution
The number of A/D converter digital output codes
Quantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 11.5).
Offset error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from the minimum voltage value B'0000000000 (H'00) to
B'0000000001 (H'01) (see figure 11.6).
•
•
•
Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see
figure 11.6).
Nonlinearity error
The error with respect to the ideal A/D conversion characteristic between zero voltage and full-
scale voltage. Does not include offset error, full-scale error, or quantization error (see figure
11.6).
Absolute accuracy
The deviation between the digital value and the analog input value. Includes offset error, full-
scale error, quantization error, and nonlinearity error.
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11. A/D Converter
Digital output
Ideal A/D conversion
characteristic
111
110
101
100
011
010
001
Quantization error
000
1
2
1022 1023 FS
1024 1024
Analog
input voltage
1024 1024
Figure 11.5 Definitions of A/D Conversion Accuracy
Full-scale error
Digital output
Ideal A/D conversion
characteristic
Nonlinearity
error
Actual A/D conversion
characteristic
FS
Analog
input voltage
Offset error
Figure 11.6 Definitions of A/D Conversion Accuracy
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11. A/D Converter
11.7
Usage Notes
11.7.1
Module Standby Mode Setting
Operation of the A/D converter can be disabled or enabled using the module standby control
register. The initial setting is for operation of the A/D converter to be halted. Register access is
enabled by clearing module standby mode. For details, refer to section 17, Power-Down Modes.
11.7.2
Permissible Signal Source Impedance
This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal
for which the signal source impedance is 1 kΩ or less, or 3 kΩ or less. This specification is
provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged
within the sampling time; if the sensor output impedance exceeds 1 kΩ or 3 kΩ, charging may be
insufficient and it may not be possible to guarantee A/D conversion accuracy. However, for A/D
conversion in single mode with a large capacitance provided externally, the input load will
essentially comprise only the internal input resistance of 10 kΩ, and the signal source impedance
is ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to
follow an analog signal with a large differential coefficient (e.g., 5 mV/μs or greater) (see figure
11.7). When converting a high-speed analog signal or converting in scan mode, a low-impedance
buffer should be inserted.
11.7.3
Influences on Absolute Accuracy
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect absolute accuracy. Be sure to make the connection to an electrically stable GND such as
AVss.
Care is also required to insure that filter circuits do not communicate with digital signals on the
mounting board (i.e., acting as antennas).
This LSI
A/D converter
Sensor output
impedance of
equivalent circuit
up to 3 kΩ or up to 1 kΩ
10 kΩ
Sensor input
Cin
15 pF
=
Low-pass
filter
20 pF
C to 0.1 μF
Figure 11.7 Example of Analog Input Circuit
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11. A/D Converter
11.7.4
Range of Analog Power Supply and Other Pin Settings
If the conditions below are not met, the reliability of the device may be adversely affected.
•
•
Analog input voltage range
The voltage applied to analog input pin ANn during A/D conversion should be in the range
AVss ≤ VAN ≤ AVcc.
Relationship between AVcc, AVss and Vcc, Vss
Set AVss = Vss for the relationship between AVcc, AVss and Vcc, Vss. If the A/D converter
is not used, the AVcc and AVss pins must not be left open.
11.7.5
Notes on Board Design
In board design, digital circuitry and analog circuitry should be as mutually isolated as possible,
and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close
proximity should be avoided as far as possible. Failure to do so may result in incorrect operation
of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital
circuitry must be isolated from the analog input signals (AN8 to AN15), and analog power supply
(AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one
point to a stable ground (Vss) on the board.
11.7.6
Notes on Noise Countermeasures
A protection circuit should be connected in order to prevent damage due to abnormal voltage, such
as an excessive surge at the analog input pins (AN8 to AN15), between AVcc and AVss, as shown
in figure 11.8. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to
AN8 to AN15 must be connected to AVss.
If a filter capacitor is connected, the input currents at the analog input pins (AN8 to AN15) are
averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in
scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit
in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in
the analog input pin voltage. Careful consideration is therefore required when deciding circuit
constants.
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11. A/D Converter
AVCC
2
*
Rin
100 Ω
0.1 µF
1
AN8 to AN15
AVSS
*
Notes: Values are reference values.
1.
10 µF
0.01 µF
2. Rin: Input impedance
Figure 11.8 Example of Analog Input Protection Circuit
Table 11.6 Analog Pin Specifications
Measurement
Item
Min
⎯
Max
20
3
Unit
pF
Condition
Analog input capacitance
Permissible signal source impedance
⎯
kΩ
pφ ≤ 20 MHz
⎯
1
kΩ
20 MHz < Pφ ≤ 25 MHz
10 kΩ
AN8 to AN15
To A/D converter
20 pF
Note: Values are reference values.
Figure 11.9 Analog Input Pin Equivalent Circuit
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12. Compare Match Timer (CMT)
Section 12 Compare Match Timer (CMT)
This LSI has an on-chip compare match timer (CMT) comprising two 16-bit timer channels. The
CMT has 16-bit counters and can generate interrupts at set intervals.
12.1
Features
•
Four types of counter input clock can be selected
⎯ One of four internal clocks (Pφ/8, Pφ/32, Pφ/128, Pφ/512) can be selected independently
for each channel.
•
•
Interrupt sources
⎯ A compare match interrupt can be requested independently for each channel.
Module standby mode can be set
Figure 12.1 shows a block diagram of the CMT.
Pφ/32 Pφ/512
Pφ/8 Pφ/128
Pφ/32 Pφ/512
CMI0
CMI1
Pφ/8
Pφ/128
Control circuit
Clock selection
Control circuit
Clock selection
Bus
interface
Module bus
CMT
Internal bus
Legend:
CMSTR: Compare match timer start register
CMCSR: Compare match timer control/status register
CMCOR: Compare match timer constant register
CMCNT: Compare match timer counter
CMI:
Compare match interrupt
Figure 12.1 CMT Block Diagram
TIMCMT0A_010020030200
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12. Compare Match Timer (CMT)
12.2
Register Descriptions
The CMT has the following registers. For details on register addresses and register states during
each processing, refer to section 18, List of Registers.
•
•
•
•
•
•
•
Compare Match Timer Start Register (CMSTR)
Compare Match Timer Control/Status Register_0 (CMCSR_0)
Compare Match Timer Counter_0 (CMCNT_0)
Compare Match Timer Constant Register_0 (CMCOR_0)
Compare Match Timer Control/Status Register_1 (CMCSR_1)
Compare Match Timer Counter_1 (CMCNT_1)
Compare Match Timer Constant Register_1 (CMCOR_1)
12.2.1
Compare Match Timer Start Register (CMSTR)
CMSTR is a 16-bit register that selects whether to operate or halt the channel 0 and channel 1
counters (CMCNT).
Initial
Bit
Bit Name Value
R/W
Description
15 to 2
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
1
0
STR1
0
R/W
R/W
Count Start 1
This bit selects whether to operate or halt compare
match timer counter_1.
0: CMCNT_1 count operation halted
1: CMCNT_1 count operation
STR0
0
Count Start 0
This bit selects whether to operate or halt compare
match timer counter_0.
0: CMCNT_0 count operation halted
1: CMCNT_0 count operation
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12. Compare Match Timer (CMT)
12.2.2
Compare Match Timer Control/Status Register_0 and _1 (CMCSR_0, CMCSR_1)
CMCSR is a 16-bit register that indicates the occurrence of compare matches, sets the
enable/disable status of interrupts, and establishes the clock used for incrementation.
Initial
Bit
Bit Name Value
R/W
Description
15 to 8
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
7
CMF
0
R/(W)* Compare Match Flag
This flag indicates whether or not the CMCNT and
CMCOR values have matched.
0: CMCNT and CMCOR values have not matched
[Clearing condition]
•
Write 0 to CMF after reading 1 from it
1: CMCNT and CMCOR values have matched
Compare Match Interrupt Enable
6
CMIE
0
R/W
This bit selects whether to enable or disable a compare
match interrupt (CMI) when the CMCNT and CMCOR
values have matched (CMF = 1).
0: Compare match interrupt (CMI) disabled
1: Compare match interrupt (CMI) enabled
5 to 2
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
1
0
CKS1
CKS0
0
0
R/W
R/W
These bits select the clock input to CMCNT among the
four internal clocks obtained by dividing the peripheral
clock (Pφ). When the STR bit in CMSTR is set to 1,
CMCNT begins incrementing with the clock selected by
CKS1 and CKS0.
00: Pφ/8
01: Pφ/32
10: Pφ/128
11: Pφ/512
Note:
*
Only 0 can be written, for flag clearing.
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12. Compare Match Timer (CMT)
12.2.3
Compare Match Timer Counter_0 and _1 (CMCNT_0, CMCNT_1)
CMCNT is a 16-bit register used as an up-counter for generating interrupt requests. CMCNT is
initialized to H'0000.
12.2.4
Compare Match Timer Constant Register_0 and _1 (CMCOR_0, CMCOR_1)
CMCOR is a 16-bit register that sets the period for compare match with CMCNT. CMCOR is
initialized to H'FFFF.
12.3
Operation
12.3.1
Cyclic Count Operation
When an internal clock is selected with the CKS1, CKS0 bits in CMCSR and the STR bit in
CMSTR is set to 1, CMCNT begins incrementing with the selected clock. When the CMCNT
counter value matches that of the compare match constant register (CMCOR), the CMCNT
counter is cleared to H'0000 and the CMF flag in CMCSR is set to 1. If the CMIE bit in CMCSR
is set to 1 at this time, a compare match interrupt (CMI) is requested. The CMCNT counter begins
counting up again from H'0000.
Figure 12.2 shows the compare match counter operation.
CMCNT value
Counter cleared by CMCOR
compare match
CMCOR
H'0000
Time
Figure 12.2 Counter Operation
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12. Compare Match Timer (CMT)
12.3.2
CMCNT Count Timing
One of four internal clocks (Pφ/8, Pφ/32, Pφ/128, Pφ/512) obtained by dividing the peripheral
clock (Pφ) can be selected by the CKS1 and CKS0 bits in CMCSR. Figure 12.3 shows the timing.
Pφ
Internal
clock
CMCNT
input clock
CMCNT
N-1
N
N+1
Figure 12.3 Count Timing
12.4
Interrupts
12.4.1
Interrupt Sources
The CMT has a compare match interrupt for each channel, with independent vector addresses
allocated to each of them. The corresponding interrupt request is output when interrupt request
flag CMF is set to 1 and interrupt enable bit CMIE has also been set to 1.
When activating CPU interrupts by interrupt request, the priority between the channels can be
changed by means of interrupt controller settings. See section 6, Interrupt Controller (INTC), for
details.
12.4.2
Compare Match Flag Set Timing
The CMF bit in CMCSR is set to 1 by the compare match signal generated when the CMCOR
register and the CMCNT counter match. The compare match signal is generated upon the final
state of the match (timing at which the CMCNT counter matching count value is updated).
Consequently, after the CMCOR register and the CMCNT counter match, a compare match signal
will not be generated until a CMCNT counter input clock occurs. Figure 12.4 shows the CMF bit
set timing.
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12. Compare Match Timer (CMT)
Pφ
CMCNT
input clock
CMCNT
CMCOR
N
N
0
Compare
match signal
CMF
CMI
Figure 12.4 CMF Set Timing
Compare Match Flag Clear Timing
12.4.3
The CMF bit in CMCSR is cleared by writing 0 to it after reading 1. Figure 12.5 shows the timing
when the CMF bit is cleared by the CPU.
CMCSR write cycle
T1
T2
Pφ
CMF
Figure 12.5 Timing of CMF Clear by CPU
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12. Compare Match Timer (CMT)
12.5
Usage Notes
12.5.1
Contention between CMCNT Write and Compare Match
If a compare match signal is generated during the T2 state of the CMCNT counter write cycle, the
CMCNT counter clear has priority, so the write to the CMCNT counter is not performed. Figure
12.6 shows the timing.
CMCNT write cycle
T1
T2
Pφ
Address
CMCNT
Internal
write signal
Compare
match signal
CMCNT
N
H'0000
Figure 12.6 CMCNT Write and Compare Match Contention
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12. Compare Match Timer (CMT)
12.5.2
Contention between CMCNT Word Write and Incrementation
If an increment occurs during the T2 state of the CMCNT counter word write cycle, the counter
write has priority, so no increment occurs. Figure 12.7 shows the timing.
CMCNT write cycle
T1
T2
Pφ
Address
CMCNT
Internal write
signal
CMCNT
input clock
CMCNT
N
M
CMCNT write data
Figure 12.7 CMCNT Word Write and Increment Contention
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12. Compare Match Timer (CMT)
Contention between CMCNT Byte Write and Incrementation
12.5.3
If an increment occurs during the T2 state of the CMCNT byte write cycle, the counter write has
priority, so no increment of the write data results on the side on which the write was performed.
The byte data on the side on which writing was not performed is also not incremented, so the
contents are those before the write.
Figure 12.8 shows the timing when an increment occurs during the T2 state of the CMCNTH write
cycle.
CMCNT write cycle
T1
T2
Pφ
Address
CMCNTH
Internal write
signal
CMCNT input
clock
N
X
M
X
CMCNTH
CMCNTH write data
CMCNTL
Figure 12.8 CMCNT Byte Write and Increment Contention
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12. Compare Match Timer (CMT)
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13. Pin Function Controller (PFC)
Section 13 Pin Function Controller (PFC)
The pin function controller (PFC) is composed of those registers that are used to select
the functions of multiplexed pins and assign pins to be inputs or outputs. Tables 13.1 to
13.5 list the multiplexed pins of this LSI.
Tables 13.6 lists the pin functions in each operating mode.
Table 13.1 Multiplexed Pins (Port A)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8
(Related
Port Module)
(Related
Module)
(Related
Module)
(Related
Module)
(Related
Module)
(Related
Module)
(Related
Module)
(Related
Module)
A
PA0 I/O
(port)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
POE0 input RXD2 input
(port) (SCI)
⎯
PA1 I/O
(port)
POE1 input TXD2 output ⎯
(port)
(SCI)
PA2 I/O
(port)
IRQ0 input
(INTC)
⎯
SCK2 I/O
(SCI)
⎯
⎯
PA3 I/O
(port)
⎯
⎯
⎯
⎯
⎯
RXD3 input
(SCI)
PA4 I/O
(port)
TXD3 output ⎯
(SCI)
PA5 I/O
(port)
IRQ1 input
(INTC)
SCK3 I/O
(SCI)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PA6 I/O
(port)
TCLKA
input (MTU)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
RXD2 input
(SCI)
⎯
PA7 I/O
(port)
TCLKB
input (MTU)
TXD2 output ⎯
(SCI)
PA8 I/O
(port)
TCLKC
input (MTU)
RXD3 input
(SCI)
⎯
PA9 I/O
(port)
TCLKD
input (MTU)
TXD3 output ⎯
(SCI)
PA10 I/O
(port)
⎯
⎯
⎯
⎯
SCK2 I/O
(SCI)
⎯
⎯
⎯
⎯
PA11 I/O
(port)
ADTRG
input (A/D)
SCK3 I/O
(SCI)
PA12 I/O
(port)
⎯
⎯
⎯
PA13 I/O
(port)
⎯
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13. Pin Function Controller (PFC)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8
(Related
Port Module)
(Related
Module)
(Related
Module)
(Related
Module)
(Related
Module)
(Related
Module)
(Related
Module)
(Related
Module)
A
PA14 I/O
(port)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PA15 I/O
(port)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Table 13.2 Multiplexed Pins (Port B)
Function 1
(Related Module)
Function 2
Function 3
Function 4
(Related Module)
Port
(Related Module)
IRQ0 input (INTC)
IRQ1 input (INTC)
IRQ2 input (INTC)
IRQ3 input (INTC)
(Related Module)
POE0 input (port)
POE1 input (port)
POE2 input (port)
POE3 input (port)
B
PB2 I/O (port)
PB3 I/O (port)
PB4 I/O (port)
PB5 I/O (port)
⎯
⎯
⎯
⎯
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13. Pin Function Controller (PFC)
Table 13.3 Multiplexed Pins (Port E)
Function 1
Function 2
Function 3
Function 4
Port
(Related Module)
(Related Module)
(Related Module)
(Related Module)
E
PE0 I/O (port)
PE1 I/O (port)
PE2 I/O (port)
PE3 I/O (port)
PE4 I/O (port)
PE5 I/O (port)
PE6 I/O (port)
PE7 I/O (port)
PE8 I/O (port)
PE9 I/O (port)
PE10 I/O (port)
PE11 I/O (port)
PE12 I/O (port)
PE13 I/O (port)
PE14 I/O (port)
PE15 I/O (port)
PE16 I/O (port)
PE17 I/O (port)
PE18 I/O (port)
PE19 I/O (port)
PE20 I/O (port)
PE21 I/O (port)
TIOC0A I/O (MTU)
TIOC0B I/O (MTU)
TIOC0C I/O (MTU)
TIOC0D I/O (MTU)
TIOC1A I/O (MTU)
TIOC1B I/O (MTU)
TIOC2A I/O (MTU)
TIOC2B I/O (MTU)
TIOC3A I/O (MTU)
TIOC3B I/O (MTU)
TIOC3C I/O (MTU)
TIOC3D I/O (MTU)
TIOC4A I/O (MTU)
TIOC4B I/O (MTU)
TIOC4C I/O (MTU)
TIOC4D I/O (MTU)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
RXD3 input (SCI)
⎯
TXD3 output (SCI)
⎯
SCK3 I/O (SCI)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
MRES input (INTC)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
IRQOUT output (INTC)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
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13. Pin Function Controller (PFC)
Table 13.4 Multiplexed Pins (Port F)
Function 1
(Related Module)
Function 2
(Related Module)
Function 3
(Related Module)
Function 4
(Related Module)
Port
F
PF8 input (port)
PF9 input (port)
PF10 input (port)
PF11 input (port)
PF12 input (port)
PF13 input (port)
PF14 input (port)
PF15 input (port)
AN8 input (A/D0)
AN9 input (A/D0)
AN10 input (A/D0)
AN11 input (A/D0)
AN12 input (A/D1)
AN13 input (A/D1)
AN14 input (A/D1)
AN15 input (A/D1)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Table 13.5 Multiplexed Pins (Port G)
Function 1
Port
(Related Module)
PG0 input (port)
PG1 input (port)
PG2 input (port)
PG3 input (port)
G
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13. Pin Function Controller (PFC)
Table 13.6 Pin Functions in Each Operating Mode
Pin Name
Single Chip Mode
PFC Selected Function Possibilities
Vcc
Pin No.
Initial Function
Vcc
11, 43, 66
9, 24, 41, 64
Vss
Vss
22, 62
27, 38
25, 40
1
VCL
VCL
AVcc
AVcc
AVss
AVss
PE2
PE2/TIOC0C
PE3/TIOC0D
PE4/TIOC1A/RxD3
PE5/TIOC1B/TxD3
PE6/TIOC2A/SCK3
PE7/TIOC2B
PE8/TIOC3A
PE9/TIOC3B
PE10/TIOC3C
PE11/TIOC3D
PE12/TIOC4A
PE13/TIOC4B/MRES
PE14/TIOC4C
PE15/TIOC4D/IRQOUT
PE16
2
PE3
3
PE4
4
PE5
5
PE6
6
PE7
7
PE8
8
PE9
10
12
13
14
15
16
17
18
19
20
21
23
26
28
29
30
31
PE10
PE11
PE12
PE13
PE14
PE15
PE16
PE17
PE17
PE18
PE18
PE19
PE19
PE20
PE20
PE21
PE21
PF15/AN15
PF14/AN14
PF13/AN13
PF12/AN12
PG3
PF15/AN15
PF14/AN14
PF13/AN13
PF12/AN12
PG3
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13. Pin Function Controller (PFC)
Pin Name
Single Chip Mode
PFC Selected Function Possibilities
PG2
Pin No.
32
33
34
35
36
37
39
42
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
63
65
67
68
69
Initial Function
PG2
PG1
PG1
PG0
PG0
PF11/AN11
PF10/AN10
PF9/AN9
PF8/AN8
PB5
PF11/AN11
PF10/AN10
PF9/AN9
PF8/AN8
PB5/IRQ3/POE3
PB4/IRQ2/POE2
PB3/IRQ1/POE1
PB2/IRQ0/POE0
PA15
PB4
PB3
PB2
PA15
PA14
PA13
PA12
PA11
PA10
PA9
PA14
PA13
PA12
PA11/ADTRG/SCK3
PA10/SCK2
PA9/TCLKD/TXD3
PA8/TCLKC/RXD3
PA7/TCLKB/TXD2
PA6/TCLKA/RXD2
PA5/IRQ1/SCK3
PA4/TXD3
PA8
PA7
PA6
PA5
PA4
PA3
PA3/RXD3
PA2
PA2/IRQ0/SCK2
PA1/POE1/TXD2
PA0/POE0/RXD2
FWP
PA1
PA0
FWP
RES
RES
NMI
NMI
MD3
MD3
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13. Pin Function Controller (PFC)
Pin Name
Single Chip Mode
Pin No.
70
Initial Function
MD2
PFC Selected Function Possibilities
MD2
71
MD1
MD1
72
MD0
MD0
73
EXTAL
XTAL
EXTAL
74
XTAL
75
PLLVCL
PLLCAP
PLLVss
WDTOVF
PE0
PLLVCL
PLLCAP
PLLVss
WDTOVF
PE0/TIOC0A
PE1/TIOC0B
76
77
78
79
80
PE1
Note: In single chip mode, do not set functions other than those that can be set by PFC listed in
this table.
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13. Pin Function Controller (PFC)
13.1
Register Descriptions
The PFC has the following registers. For details on the addresses of the registers and their states
during each process, see section 18, List of Registers.
• Port A I/O register L (PAIORL)
• Port A control register L3 (PACRL3)
• Port A control register L2 (PACRL2)
• Port A control register L1 (PACRL1)
• Port B I/O register (PBIOR)
• Port B control register 1 (PBCR1)
• Port B control register 2 (PBCR2)
• Port E I/O register H (PEIORH)
• Port E I/O register L (PEIORL)
• Port E control register H (PECRH)
• Port E control register L1 (PECRL1)
• Port E control register L2 (PECRL2)
13.1.1
Port A I/O Register L (PAIORL)
PAIORL is a 16-bit readable/writable register that is used to set the pins on port A as inputs or
outputs. Bits PA15IOR to PA0IOR correspond to pins PA15 to PA0 (names of multiplexed pins
are here given as port names and pin numbers alone). PAIORL is enabled when the port A pins are
functioning as general-purpose inputs/outputs (PA15 to PA0), and SCK2 and SCK3 pins are
functioning as inputs/outputs of SCI. In other states, PAIORL is disabled.
A given pin on port A will be an output pin if the corresponding bit in PAIORL is set to 1, and an
input pin if the bit is cleared to 0.
PAIORL is initialized to H'0000.
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13. Pin Function Controller (PFC)
13.1.2 Port A Control Registers L3 to L1 (PACRL3 to PACRL1)
PACRL3 to PACRL1 are 16-bit readable/writable registers that are used to select the functions of
the multiplexed pins on port A.
Port A Control Registers L3 to L1 (PACRL3 to PACRL1)
Initial
Register
Bit
Bit Name
Value
R/W
Description
PACRL3
PACRL1
PACRL1
15
15
14
PA15MD2
PA15MD1
PA15MD0
0
0
0
R/W
R/W
R/W
PA15 Mode
Select the function of the PA15 pin.
000: PA15 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
1xx: Setting prohibited
PACRL3
PACRL1
PACRL1
14
13
12
PA14MD2
PA14MD1
PA14MD0
0
0
0
R/W
R/W
R/W
PA14 Mode
Select the function of the PA14 pin.
000: PA14 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
1xx: Setting prohibited
PACRL3
PACRL1
PACRL1
13
11
10
PA13MD2
PA13MD1
PA13MD0
0
0
0
R/W
R/W
R/W
PA13 Mode
Select the function of the PA13 pin.
000: PA13 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
1xx: Setting prohibited
PACRL3
PACRL1
PACRL1
12
9
PA12MD2
PA12MD1
PA12MD0
0
0
0
R/W
R/W
R/W
PA12 Mode
Select the function of the PA12 pin.
8
000: PA12 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
1xx: Setting prohibited
PACRL3
PACRL1
PACRL1
11
7
PA11MD2
PA11MD1
PA11MD0
0
0
0
R/W
R/W
R/W
PA11 Mode
Select the function of the PA11/ADTRG/SCK3 pin.
6
000: PA11 I/O (port)
100: Setting prohibited
101: SCK3 I/O (SCI)
110: Setting prohibited
111: Setting prohibited
001: Setting prohibited
010: ADTRG input (A/D)
011: Setting prohibited
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13. Pin Function Controller (PFC)
Initial
Register
Bit
Bit Name
Value
R/W
Description
PACRL3
PACRL1
PACRL1
10
5
PA10MD2
PA10MD1
PA10MD0
0
0
0
R/W
R/W
R/W
PA10 Mode
Select the function of the PA10/SCK2 pin.
4
000: PA10 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: SCK2 I/O (SCI)
110: Setting prohibited
111: Setting prohibited
PACRL3
PACRL1
PACRL1
9
3
2
PA9MD2
PA9MD1
PA9MD0
0
0
0
R/W
R/W
R/W
PA9 Mode
Select the function of the PA9/TCLKD/TXD3 pin.
000: PA9 I/O (port)
100: Setting prohibited
101: TXD3 output (SCI)
110: Setting prohibited
111: Setting prohibited
001: TCLKD input (MTU)
010: Setting prohibited
011: Setting prohibited
PACRL3
PACRL1
PACRL1
8
1
0
PA8MD2
PA8MD1
PA8MD0
0
0
0
R/W
R/W
R/W
PA8 Mode
Select the function of the PA8/TCLKC/RXD3 pin.
000: PA8 I/O (port)
100: Setting prohibited
101: RXD3 input (SCI)
110: Setting prohibited
111: Setting prohibited
001: TCLKC input (MTU)
010: Setting prohibited
011: Setting prohibited
PACRL3
PACRL2
PACRL2
7
PA7MD2
PA7MD1
PA7MD0
0
0
0
R/W
R/W
R/W
PA7 Mode
15
14
Select the function of the PA7/TCLKB/TXD2 pin.
000: PA7 I/O (port)
100: Setting prohibited
101: TXD2 output (SCI)
110: Setting prohibited
111: Setting prohibited
001: TCLKB input (MTU)
010: Setting prohibited
011: Setting prohibited
PACRL3
PACRL2
PACRL2
6
PA6MD2
PA6MD1
PA6MD0
0
0
0
R/W
R/W
R/W
PA6 Mode
13
12
Select the function of the PA6/TCLKA/RXD2 pin.
000: PA6 I/O (port)
100: Setting prohibited
101: RXD2 input (SCI)
110: Setting prohibited
111: Setting prohibited
001: TCLKA input (MTU)
010: Setting prohibited
011: Setting prohibited
PACRL3
PACRL2
PACRL2
5
PA5MD2
PA5MD1
PA5MD0
0
0
0
R/W
R/W
R/W
PA5 Mode
11
10
Select the function of the PA5/IRQ1/SCK3 pin.
000: PA5 I/O (port)
100: Setting prohibited
001: Setting prohibited
010: Setting prohibited
011: IRQ1 input (INTC)
101: Setting prohibited
110: SCK3 I/O (SCI)
111: Setting prohibited
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13. Pin Function Controller (PFC)
Initial
Value
Register
Bit
Bit Name
R/W
Description
PACRL3
PACRL2
PACRL2
4
9
8
PA4MD2
PA4MD1
PA4MD0
0
0
0
R/W
R/W
R/W
PA4 Mode
Select the function of the PA4/TXD3 pin.
000: PA4 I/O (port)
100: Setting prohibited
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
101: Setting prohibited
110: TXD3 output (SCI)
111: Setting prohibited
PACRL3
PACRL2
PACRL2
3
7
6
PA3MD2
PA3MD1
PA3MD0
0
0
0
R/W
R/W
R/W
PA3 Mode
Select the function of the PA3/RXD3 pin.
000: PA3 I/O (port)
100: Setting prohibited
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
101: Setting prohibited
110: RXD3 input (SCI)
111: Setting prohibited
PACRL3
PACRL2
PACRL2
2
5
4
PA2MD2
PA2MD1
PA2MD0
0
0
0
R/W
R/W
R/W
PA2 Mode
Select the function of the PA2/IRQ0/SCK2 pin.
000: PA2 I/O (port)
100: Setting prohibited
001: Setting prohibited
010: Setting prohibited
011: IRQ0 input (INTC)
101: Setting prohibited
110: SCK2 I/O (SCI)
111: Setting prohibited
PACRL3
PACRL2
PACRL2
1
3
2
PA1MD2
PA1MD1
PA1MD0
0
0
0
R/W
R/W
R/W
PA1 Mode
Select the function of the PA1/POE1/TXD2 pin.
000: PA1 I/O (port)
100: Setting prohibited
101: POE1 input (port)
110: TXD2 output (SCI)
111: Setting prohibited
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
PACRL3
PACRL2
PACRL2
0
1
0
PA0MD2
PA0MD1
PA0MD0
0
0
0
R/W
R/W
R/W
PA0 Mode
Select the function of the PA0/POE0/RXD2 pin.
000: PA0 I/O (port)
100: Setting prohibited
101: POE0 input (port)
110: RXD2 input (SCI)
111: Setting prohibited
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
Note: x means “don't care”.
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13. Pin Function Controller (PFC)
13.1.3
Port B I/O Register (PBIOR)
PBIOR is a 16-bit readable/writable register that is used to set the pins on port B as inputs or
outputs. Bits PB5IOR to PB2IOR correspond to pins PB5 to PB2 (names of multiplexed pins are
here given as port names and pin numbers alone). PBIOR is enabled when port B pins are
functioning as general-purpose inputs/outputs (PB5 to PB2). In other states, PBIOR is disabled.
A given pin on port B will be an output pin if the corresponding bit in PBIOR is set to 1, and an
input pin if the bit is cleared to 0.
Bits 15 to 6, 1, and 0 are reserved. These bits are always read as 0. The write value should always
be 0.
PBIOR is initialized to H'0000.
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13. Pin Function Controller (PFC)
Port B Control Registers 1 and 2 (PBCR1 and PBCR2)
13.1.4
PBCR1 and PBCR2 are 16-bit readable/writable registers that are used to select the multiplexed
pin function of the pins on port B.
Port B Control Registers 1 and 2 (PBCR1 and PBCR2)
Initial
Register
Bit
Bit Name
Value
R/W
Description
PBCR1
PBCR1
PBCR2
PBCR2
15, 14
9 to 0
⎯
⎯
⎯
⎯
All 0
All 0
All 0
All 0
R
R
R
R
Reserved
These bits are always read as 0. The write value
should always be 0.
15 to 12
3 to 0
PBCR1
PBCR2
PBCR2
13
11
10
PB5MD2
PB5MD1
PB5MD0
0
0
0
R/W
R/W
R/W
PB5 Mode
Select the function of the PB5/IRQ3/POE3 pin.
000: PB5 I/O (port)
011: Setting prohibited
001: IRQ3 input (INTC) 1xx: Setting prohibited
010: POE3 input (port)
PBCR1
PBCR2
PBCR2
12
9
PB4MD2
PB4MD1
PB4MD0
0
0
0
R/W
R/W
R/W
PB4 Mode
Select the function of the PB4/IRQ2/POE2 pin.
8
000: PB4 I/O (port)
011: Setting prohibited
001: IRQ2 input (INTC) 1xx: Setting prohibited
010: POE2 input (port)
PBCR1
PBCR2
PBCR2
11
7
PB3MD2
PB3MD1
PB3MD0
0
0
0
R/W
R/W
R/W
PB3 Mode
Select the function of the PB3/IRQ1/POE1 pin.
6
000: PB3 I/O (port)
011: Setting prohibited
001: IRQ1 input (INTC) 1xx: Setting prohibited
010: POE1 input (port)
PBCR1
PBCR2
PBCR2
10
5
PB2MD2
PB2MD1
PB2MD0
0
0
0
R/W
R/W
R/W
PB2 Mode
Select the function of the PB2/IRQ0/POE0 pin.
4
000: PB2 I/O (port)
011: Setting prohibited
001: IRQ0 input (INTC) 1xx: Setting prohibited
010: POE0 input (port)
Note: x means “don't care”.
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13. Pin Function Controller (PFC)
13.1.5
Port E I/O Registers L and H (PEIORL and PEIORH)
PEIORL and PEIORH are 16-bit readable/writable registers that are used to set the pins on port E
as inputs or outputs. Bits PE21IOR to PE0IOR correspond to pins PE21 to PE0 (names of
multiplexed pins are here given as port names and pin numbers alone). PEIORL is enabled when
the port E pins are functioning as general-purpose inputs/outputs (PE15 to PE0), TIOC pins are
functioning as inputs/outputs of MTU, and SCK3 pins are functioning as inputs/outputs of SCI. In
other states, PEIORL is disabled. PEIORH is enabled when the port E pins are functioning as
general-purpose inputs/outputs (PE21 to PE16). In other states, PEIORH is disabled.
A given pin on port E will be an output pin if the corresponding PEIORL or PEIORH bit is set to
1, and an input pin if the bit is cleared to 0.
Bits 15 to 6 in PEIORH are reserved. These bits are always read as 0. The write value should
always be 0.
PEIORL and PEIORH are initialized to H'0000.
13.1.6
Port E Control Registers L1, L2, and H (PECRL1, PECRL2, and PECRH)
PECRL1, PECRL2 and PECRH are 16-bit readable/writable registers that are used to select the
multiplexed pin function of the pins on port E.
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13. Pin Function Controller (PFC)
Port E Control Registers L1, L2, and H (PECRL1, PECRL2, and PECRH)
Initial
Value
Register
Bit
Bit Name
R/W
Description
PECRH
15 to 12
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
PECRH
PECRH
11
10
PE21MD1
PE21MD0
0
0
R/W
R/W
PE21 Mode
Select the function of the PE21 pin.
00: PE21 I/O (port)
10: Setting prohibited
11: Setting prohibited
01: Setting prohibited
PECRH
PECRH
9
8
PE20MD1
PE20MD0
0
0
R/W
R/W
PE20 Mode
Select the function of the PE20 pin.
00: PE20 I/O (port)
10: Setting prohibited
11: Setting prohibited
01: Setting prohibited
PECRH
PECRH
7
6
PE19MD1
PE19MD0
0
0
R/W
R/W
PE19 Mode
Select the function of the PE19 pin.
00: PE19 I/O (port)
10: Setting prohibited
11: Setting prohibited
01: Setting prohibited
PECRH
PECRH
5
4
PE18MD1
PE18MD0
0
0
R/W
R/W
PE18 Mode
Select the function of the PE18 pin.
00: PE18 I/O (port)
10: Setting prohibited
11: Setting prohibited
01: Setting prohibited
PECRH
PECRH
3
2
PE17MD1
PE17MD0
0
0
R/W
R/W
PE17 Mode
Select the function of the PE17 pin.
00: PE17 I/O (port)
10: Setting prohibited
11: Setting prohibited
01: Setting prohibited
PECRH
PECRH
1
0
PE16MD1
PE16MD0
0
0
R/W
R/W
PE16 Mode
Select the function of the PE16 pin.
00: PE16 I/O (port)
10: Setting prohibited
11: Setting prohibited
01: Setting prohibited
PECRL1
PECRL1
15
14
PE15MD1
PE15MD0
0
0
R/W
R/W
PE15 Mode
Select the function of the PE15/TIOC4D/IRQOUT pin.
00: PE15 I/O (port)
10: Setting prohibited
01: TIOC4D I/O (MTU)
11: IRQOUT output (INTC)
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13. Pin Function Controller (PFC)
Initial
Register
Bit
Bit Name
Value
R/W
Description
PECRL1
PECRL1
13
12
PE14MD1
PE14MD0
0
0
R/W
R/W
PE14 Mode
Select the function of the PE14/TIOC4C pin.
00: PE14 I/O (port)
10: Setting prohibited
11: Setting prohibited
01: TIOC4C I/O (MTU)
PECRL1
PECRL1
11
10
PE13MD1
PE13MD0
0
0
R/W
R/W
PE13 Mode
Select the function of the PE13/TIOC4B/MRES pin.
00: PE13 I/O (port)
10: MRES input (INTC)
01: TIOC4B I/O (MTU)
11: Setting prohibited
PECRL1
PECRL1
9
8
PE12MD1
PE12MD0
0
0
R/W
R/W
PE12 Mode
Select the function of the PE12/TIOC4A pin.
00: PE12 I/O (port)
10: Setting prohibited
11: Setting prohibited
01: TIOC4A I/O (MTU)
PECRL1
PECRL1
7
6
PE11MD1
PE11MD0
0
0
R/W
R/W
PE11 Mode
Select the function of the PE11/TIOC3D pin.
00: PE11 I/O (port)
10: Setting prohibited
11: Setting prohibited
01: TIOC3D I/O (MTU)
PECRL1
PECRL1
5
4
PE10MD1
PE10MD0
0
0
R/W
R/W
PE10 Mode
Select the function of the PE10/TIOC3C pin.
00: PE10 I/O (port)
10: Setting prohibited
11: Setting prohibited
01: TIOC3C I/O (MTU)
PECRL1
PECRL1
3
2
PE9MD1
PE9MD0
0
0
R/W
R/W
PE9 Mode
Select the function of the PE9/TIOC3B pin.
00: PE9 I/O (port)
10: Setting prohibited
11: Setting prohibited
01: TIOC3B I/O (MTU)
PECRL1
PECRL1
1
0
PE8MD1
PE8MD0
0
0
R/W
R/W
PE8 Mode
Select the function of the PE8/TIOC3A pin.
00: PE8 I/O (port)
10: Setting prohibited
11: Setting prohibited
01: TIOC3A I/O (MTU)
PECRL2
PECRL2
15
14
PE7MD1
PE7MD0
0
0
R/W
R/W
PE7 Mode
Select the function of the PE7/TIOC2B pin.
00: PE7 I/O (port)
10: Setting prohibited
11: Setting prohibited
01: TIOC2B I/O (MTU)
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13. Pin Function Controller (PFC)
Initial
Value
Register
Bit
Bit Name
R/W
Description
PECRL2
PECRL2
13
12
PE6MD1
PE6MD0
0
0
R/W
R/W
PE6 Mode
Select the function of the PE6/TIOC2A/SCK3 pin.
00: PE6 I/O (port)
10: SCK3 I/O (SCI)
01: TIOC2A I/O (MTU)
11: Setting prohibited
PECRL2
PECRL2
11
10
PE5MD1
PE5MD0
0
0
R/W
R/W
PE5 Mode
Select the function of the PE5/TIOC1B/TXD3 pin.
00: PE5 I/O (port)
10: TXD3 output (SCI)
11: Setting prohibited
01: TIOC1B I/O (MTU)
PECRL2
PECRL2
9
8
PE4MD1
PE4MD0
0
0
R/W
R/W
PE4 Mode
Select the function of the PE4/TIOC1A/RXD3 pin.
00: PE4 I/O (port)
10: RXD3 input (SCI)
11: Setting prohibited
01: TIOC1A I/O (MTU)
PECRL2
PECRL2
7
6
PE3MD1
PE3MD0
0
0
R/W
R/W
PE3 Mode
Select the function of the PE3/TIOC0D pin.
00: PE3 I/O (port)
10: Setting prohibited
11: Setting prohibited
01: TIOC0D I/O (MTU)
PECRL2
PECRL2
5
4
PE2MD1
PE2MD0
0
0
R/W
R/W
PE2 Mode
Select the function of the PE2/TIOC0C pin.
00: PE2 I/O (port)
10: Setting prohibited
11: Setting prohibited
01: TIOC0C I/O (MTU)
PECRL2
PECRL2
3
2
PE1MD1
PE1MD0
0
0
R/W
R/W
PE1 Mode
Select the function of the PE1/TIOC0B pin.
00: PE1 I/O (port)
10: Setting prohibited
11: Setting prohibited
01: TIOC0B I/O (MTU)
PECRL2
PECRL2
1
0
PE0MD1
PE0MD0
0
0
R/W
R/W
PE0 Mode
Select the function of the PE0/TIOC0A pin.
00: PE0 I/O (port)
10: Setting prohibited
11: Setting prohibited
01: TIOC0A I/O (MTU)
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13. Pin Function Controller (PFC)
13.2
Usage Notes
13.2.1
Note on PFC Setting
In this LSI, individual functions are available as multiplexed functions on multiple pins. This
approach is intended to increase the number of selectable pin functions and to allow the easier
design of boards.
When the pin function controller (PFC) is used to select a function, only a single pin can be
specified for each function. If one function is specified for two or more pins, the function will not
work properly.
13.2.2 Note on PFC Setting Order
When a pin function is selected, the port I/O registers (PAIORL and PBIORL) must be set after
setting the port control registers (PACRL3, PACRL2, PACRL1, PBCR2, and PBCR1.
When a pin function which is multiplexed with the port E is selected, do not care about the setting
order of the port control registers (PECRH, PECRL1, and PECRL2) and the port I/O registers
(PEIORH and PEIORL).
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14. I/O Ports
Section 14 I/O Ports
This LSI has five ports: A, B, E, F, and G. Port A is a 16-bit port, port B is a 4-bit port, and port E
is a 22-bit port, all supporting both input and output. Port F is an 8-bit port and port G is a 4-bit
port, both for input-only.
All the port pins are multiplexed as general input/output pins and special function pins. The
functions of the multiplex pins are selected by means of the pin function controller (PFC). Each
port is provided with a data register for storing the pin data.
14.1
Port A
Port A is an input/output port with the 16 pins shown in figure 14.1.
PA15 to PA12 have an input-pull up MOS.
PA15 (I/O)
PA14 (I/O)
PA13 (I/O)
PA12 (I/O)
PA11 (I/O) / ADTRG (input) / SCK3 (I/O)
PA10 (I/O) / SCK2 (I/O)
PA9 (I/O) / TCLKD (input) / TXD3 (output)
Port A
PA8 (I/O) / TCLKC (input) / RXD3 (input)
PA7 (I/O) / TCLKB (input) / TXD2 (output)
PA6 (I/O) / TCLKA (input) / RXD2 (input)
PA5 (I/O) / IRQ1 (input) / SCK3 (I/O)
PA4 (I/O) / TXD3 (output)
PA3 (I/O) / RXD3 (input)
PA2 (I/O) / IRQ0 (input) / SCK2 (I/O)
PA1 (I/O) / POE1 (input) / TXD2 (output)
PA0 (I/O) / POE0 (input) / RXD2 (input)
Figure 14.1 Port A
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14. I/O Ports
14.1.1
Register Description
Port A is a 16-bit input/output port. Port A has the following register. For details on register
addresses and register states during each processing, refer to section 18, List of Registers.
•
Port A data register L (PADRL)
14.1.2 Port A Data Register L (PADRL)
PADRL is a 16-bit readable/writable register that stores port A data. Bits PA15DR to PA0DR
correspond to pins PA15 to PA0 (multiplexed functions omitted here).
When a pin functions is a general output, if a value is written to PADRL, that value is output
directly from the pin, and if PADRL is read, the register value is returned directly regardless of the
pin state.
When a pin functions is a general input, if PADRL is read, the pin state, not the register value, is
returned directly. If a value is written to PADRL, although that value is written into PADRL, it
does not affect the pin state. Table 14.1 summarizes port A data register L read/write operations.
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14. I/O Ports
Bit
15
14
13
12
11
10
9
Bit Name
PA15DR
PA14DR
PA13DR
PA12DR
PA11DR
PA10DR
PA9DR
PA8DR
PA7DR
PA6DR
PA5DR
PA4DR
PA3DR
PA2DR
PA1DR
PA0DR
Initial Value R/W
Description
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
See table 14.1
8
7
6
5
4
3
2
1
0
Table 14.1 Port A Data Register L (PADRL) Read/Write Operations
Bits 15 to 0:
PAIORL
Pin Function
Read
Write
0
General input
Pin state
Can write to PADRL, but it has no effect on pin
state
Other than
general input
Pin state
Can write to PADRL, but it has no effect on pin
state
1
General output
PADRL value Value written is output from pin
Other than
general output
PADRL value Can write to PADRL, but it has no effect on pin
state
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14. I/O Ports
14.2
Port B
Port B is an input/output port with the four pins shown in figure 14.2.
PB5 (I/O) / IRQ3 (input) / POE3 (input)
PB4 (I/O) / IRQ2 (input) / POE2 (input)
Port B
PB3 (I/O) / IRQ1 (input) / POE1 (input)
PB2 (I/O) / IRQ0 (input) / POE0 (input)
Figure 14.2 Port B
14.2.1
Register Description
Port B is a 4-bit input/output port. Port B has the following register. For details on register
addresses and register states during each processing, refer to section 18, List of Registers.
•
Port B data register (PBDR)
14.2.2 Port B Data Register (PBDR)
PBDR is a 16-bit readable/writable register that stores port B data. Bits PB5DR to PB2DR
correspond to pins PB5 to PB2 (multiplexed functions omitted here).
When a pin functions is a general output, if a value is written to PBDR, that value is output
directly from the pin, and if PBDR is read, the register value is returned directly regardless of the
pin state.
When a pin functions is a general input, if PBDR is read, the pin state, not the register value, is
returned directly. If a value is written to PBDR, although that value is written into PBDR, it does
not affect the pin state. Table 14.2 summarizes port B data register read/write operations.
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14. I/O Ports
Initial
Bit
Bit Name Value
R/W
Description
15 to 6
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
5
4
3
2
PB5DR
PB4DR
PB3DR
PB2DR
0
0
0
0
R/W
R/W
R/W
R/W
See table 14.2
1, 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Table 14.2 Port B Data Register (PBDR) Read/Write Operations
Bits 5 to 2:
PBIOR
Pin Function
Read
Write
0
General input
Pin state
Pin state
Can write to PBDR, but it has no effect on pin state
Can write to PBDR, but it has no effect on pin state
Other than
general input
1
General output
PBDR value
PBDR value
Value written is output from pin
Other than
Can write to PBDR, but it has no effect on pin state
general output
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14. I/O Ports
14.3
Port E
Port E is an input/output port with the 22 pins shown in figure 14.3.
PE21 to PE16 have an input-pull up MOS.
PE21 (I/O)
PE20 (I/O)
PE19 (I/O)
PE18 (I/O)
PE17 (I/O)
PE16 (I/O)
PE15 (I/O) / TIOC4D (I/O) / IRQOUT (output)
PE14 (I/O) / TIOC4C (I/O)
PE13 (I/O) / TIOC4B (I/O) / MRES (input)
PE12 (I/O) / TIOC4A (I/O)
Port E
PE11 (I/O) / TIOC3D (I/O)
PE10 (I/O) / TIOC3C (I/O)
PE9 (I/O) / TIOC3B (I/O)
PE8 (I/O) / TIOC3A (I/O)
PE7 (I/O) / TIOC2B (I/O)
PE6 (I/O) / TIOC2A (I/O) / SCK3 (I/O)
PE5 (I/O) / TIOC1B (I/O) / TXD3 (output)
PE4 (I/O) / TIOC1A (I/O) / RXD3 (input)
PE3 (I/O) / TIOC0D (I/O)
PE2 (I/O) / TIOC0C (I/O)
PE1 (I/O) / TIOC0B (I/O)
PE0 (I/O) / TIOC0A (I/O)
Figure 14.3 Port E
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14. I/O Ports
14.3.1
Register Descriptions
Port E has the following registers. For details on register addresses and register states during each
processing, refer to section 18, List of Registers.
•
•
Port E data register H (PEDRH)
Port E data register L (PEDRL)
14.3.2
Port E Data Registers H and L (PEDRH and PEDRL)
PEDRH and PEDRL are 16-bit readable/writable registers that store port E data. Bits PE21DR to
PE0DR correspond to pins PE21 to PE0 (multiplexed functions omitted here).
When a pin functions is a general output, if a value is written to PEDRH or PEDRL, that value is
output directly from the pin, and if PEDRH or PEDRL is read, the register value is returned
directly regardless of the pin state.
When a pin functions is a general input, if PEDRH or PEDRL is read, the pin state, not the register
value, is returned directly. If a value is written to PEDRH or PEDRL, although that value is
written into PEDRH or PEDRL it does not affect the pin state. Table 14.3 summarizes port E data
register read/write operations.
PEDRH:
Initial
Bit
Bit Name Value
R/W
Description
15 to 6
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
5
4
3
2
1
0
PE21DR
PE20DR
PE19DR
PE18DR
PE17DR
PE16DR
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
See table 14.3.
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14. I/O Ports
PEDRL:
Bit
15
14
13
12
11
10
9
Bit Name
Initial Value R/W
Description
PE15DR
PE14DR
PE13DR
PE12DR
PE11DR
PE10DR
PE9DR
PE8DR
PE7DR
PE6DR
PE5DR
PE4DR
PE3DR
PE2DR
PE1DR
PE0DR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
See table 14.3.
8
7
6
5
4
3
2
1
0
Table 14.3 Port E Data Registers H and L (PEDRH and PEDRL) Read/Write Operations
Bits 5 to 0 in PEDRH and bits 15 to 0 in PEDRL:
PEIOR
Pin Function
Read
Write
0
General input
Pin state
Can write to PEDRH or PEDRL, but it has no
effect on pin state
Other than
general input
Pin state
Can write to PEDRH or PEDRL, but it has no
effect on pin state
1
General output
PEDRH or
PEDRL value
Value written is output from pin (POE pin = high)*
High impedance regardless of PEDRH or PEDRL
value (POE pin = low)*
Other than
general output
PEDRH or
PEDRL value
Can write to PEDRH or PEDRL, but it has no
effect on pin state
Note:
*
Control by the POE pin is only available for large current-output pins (PE9 and PE11 to
PE15).
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14. I/O Ports
14.4
Port F
Port F is an input-only port with the eight pins shown in figure 14.4.
PF15 (input) / AN15 (input)
PF14 (input) / AN14 (input)
PF13 (input) / AN13 (input)
PF12 (input) / AN12 (input)
Port F
PF11 (input) / AN11 (input)
PF10 (input) / AN10 (input)
PF9 (input) / AN9 (input)
PF8 (input) / AN8 (input)
Figure 14.4 Port F
14.4.1
Register Description
Port F is an 8-bit input-only port. Port F has the following register. For details on register
addresses and register states during each processing, refer to section 18, List of Registers.
•
Port F data register (PFDR)
14.4.2 Port F Data Register (PFDR)
PFDR is a 16-bit read-only register that stores port F data.
Bits PF15DR to PF8DR correspond to pins PF15 to PF8 (multiplexed functions omitted here).
Any value written into these bits is ignored, and there is no effect on the state of the pins. When
any of the bits are read, the pin state rather than the bit value is read directly. However, when an
A/D converter analog input is being sampled, values of 1 are read out. Table 14.4 summarizes port
F data register read operation.
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14. I/O Ports
Bit
15
14
13
12
11
10
9
Bit Name
Initial Value R/W
Description
PF15DR
PF14DR
PF13DR
PF12DR
PF11DR
PF10DR
PF9DR
PF8DR
⎯
0/1*
0/1*
0/1*
0/1*
0/1*
0/1*
0/1*
0/1*
All 0
R
R
R
R
R
R
R
R
R
See table 14.4.
8
7 to 0
Reserved
These bits are always read as 0.
Note:
*
Initial values are dependent on the state of the external pins.
Table 14.4 Port F Data Register (PFDR) Read/Write Operations
Bits 15 to 8:
Pin Function
General input
ANn input
Read
Pin state
1
Write
Ignored (no effect on pin state)
Ignored (no effect on pin state)
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14. I/O Ports
14.5
Port G
Port G is an input-only port with the four pins shown in figure 14.5.
PG3 (input)
PG2 (input)
Port G
PG1 (input)
PG0 (input)
Figure 14.5 Port G
14.5.1
Register Description
Port G is a 4-bit input-only port. Port G has the following register. For details on register addresses
and register states during each processing, refer to section 18, List of Registers.
•
Port G data register (PGDR)
14.5.2 Port G Data Register (PGDR)
PGDR is an 8-bit read-only register that stores port G data.
Bits PG3DR to PG0DR correspond to pins PG3 to PG0.
Any value written into these bits is ignored, and there is no effect on the state of the pins. When
any of the bits are read, the pin state rather than the bit value is read directly. Table 14.5
summarizes port G data register read operation.
Initial
Bit Name Value
Bit
R/W
Description
7 to 4
⎯
All 0
R
Reserved
These bits are always read as 0.
3
PG3DR
PG2DR
PG1DR
PG0DR
0/1*
0/1*
0/1*
0/1*
R
R
R
R
See table 14.5.
2
1
0
Note:
*
Initial values are dependent on the state of the external pins.
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14. I/O Ports
Table 14.5 Port G Data Register (PGDR) Read/Write Operations
Bits 3 to 0:
Pin Function
Read
Write
General input
Pin state
Ignored (no effect on pin state)
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15. Mask ROM
Section 15 Mask ROM
This LSI is available with 32 kbytes of on-chip mask ROM. The on-chip ROM is connected to the
CPU through a 32-bit data bus (figure 15.1). The CPU can access the on-chip ROM in 8, 16 and
32-bit widths. Data in the on-chip ROM can always be accessed in one cycle.
Internal data bus (32 bits)
H'00000001
H'00000005
H'00000002
H'00000006
H'00000003
H'00000007
H'00000000
H'00000004
On-chip ROM
H'00007FFC
H'00007FFD
H'00007FFE
H'00007FFF
Figure 15.1 Mask ROM Block Diagram
The on-chip ROM is allocated to addresses H'00000000 to H'00007FFF.
15.1
Usage Note
•
Setting module standby mode
For mask ROM, this module can be disabled/enabled by the module standby control register.
Mask ROM operation is enabled for the initial value. Accessing mask ROM is disabled by
setting module standby mode. For details, see section 17, Power-Down Modes.
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15. Mask ROM
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16. RAM
Section 16 RAM
This LSI has an on-chip high-speed static RAM. The on-chip RAM is connected to the CPU by a
32-bit data bus, enabling 8, 16, or 32-bit width access to data in the on-chip RAM. Data in the on-
chip RAM can always be accessed in one cycle, providing high-speed access that makes this RAM
ideal for use as a program area, stack area, or data area. The contents of the on-chip RAM are
retained in both sleep and standby modes.
The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control
register (SYSCR). For details on the system control register (SYSCR), refer to section 17.2.2,
System Control Register (SYSCR).
Product Type
Type of ROM
RAM Capacity
RAM Address
SH7101
Mask ROM
2 kbytes
H'FFFFF800 to
H'FFFFFFFF
16.1
Usage Note
•
Module Standby Mode Setting
RAM can be enabled/disabled by the module standby control register. The initial value enables
RAM operation. RAM access is disabled by setting the module standby mode. For details, see
section 17, Power-Down Modes.
RAM0200A_000020030200
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16. RAM
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17. Power-Down Modes
Section 17 Power-Down Modes
In addition to the normal program execution state, this LSI has three power-down modes in which
operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power
operation can be achieved by individually controlling the CPU, on-chip peripheral functions, and
so on.
This LSI's power-down modes are as follows:
(1) Sleep mode
(2) Software standby mode
(3) Module standby mode
Sleep mode indicates the state of the CPU, and module standby mode indicates the state of the on-
chip peripheral function. Some of these states can be combined.
After a reset, the LSI is in normal-operation mode.
Table 17.1 lists internal operation states in each mode.
LPWSH20A_010020030200
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17. Power-Down Modes
Table 17.1 Internal Operation States in Each Mode
Normal
Function
operation
Functioning
Functioning
Sleep
Module Standby Software Standby
Functioning
Functioning
System clock pulse generator
Halted
CPU
Halted (retained) Functioning
Instructions
Registers
NMI
Halted (retained)
External
Functioning
Functioning
Functioning
Functioning
interrupts
IRQ3 to IRQ0
Peripheral
functions
Functioning
Functioning
Functioning
Functioning
Functioning
Functioning
Functioning
Functioning
Halted (reset)
I/O port
WDT
SCI
Retained
Halted (retained)
Halted (reset)
A/D
MTU
CMT
ROM
RAM
Functioning
Functioning
Retained
Retained
Notes: 1. "Halted (retained)" means that the operation of the internal state is suspended, although
internal register values are retained.
2. "Halted (reset)" means that internal register values and internal state are initialized.
3. In module standby mode, only modules for which a stop setting has been made are
halted (reset or retained).
4. There are two types of on-chip peripheral module registers; ones which are initialized in
software standby mode and module standby mode, and those not initialized those
modes. For details, refer to section 18.3, Register States in Each Operating Mode.
5. The port high-impedance bit (HIZ) in SBYCR sets the state of the I/O port in software
standby mode. For details on the setting, refer to section 17.2.1, Standby Control
Register (SBYCR). For the state of pins, refer to appendix A, Pin States.
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17. Power-Down Modes
Reset state
Program-halted state
SSBY = 0
RES pin = High
Program execution state
Sleep mode
(main clock)
SLEEP instruction
Normal-operation
mode
(main clock)
SLEEP
instruction
SSBY = 1
Software
standby mode
External
interrupt *
: Transition after exception processing
: Power-down mode
Notes:
*
NMI and IRQ
•
When a transition is made between modes by means of an interrupt, the transition cannot be
made on interrupt source generation alone. Ensure that interrupt handling is performed after
accepting the interrupt request.
•
In any state, a transition to the reset state occurs when RES is driven low.
Figure 17.1 Mode Transition Diagram
17.1
Input/Output Pins
Table 17.2 lists the pins relating to power-down mode.
Table 17.2 Pin Configuration
Pin Name
RES
I/O
Function
Input
Input
Power-on reset input pin
Manual reset input pin
MRES
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17. Power-Down Modes
17.2
Register Descriptions
Registers related to power down modes are shown below. For details on register addresses and
register states during each process, refer to section 18, List of Registers.
•
•
•
•
Standby control register (SBYCR)
System control register (SYSCR)
Module standby control register 1 (MSTCR1)
Module standby control register 2 (MSTCR2)
17.2.1
Standby Control Register (SBYCR)
SBYCR is an 8-bit readable/writable register that performs software standby mode control.
Initial
Bit
Bit Name Value
R/W
Description
7
SSBY 0
R/W
Software Standby
This bit specifies the transition mode after executing the
SLEEP instruction.
0: Shifts to sleep mode after the SLEEP instruction has
been executed
1: Shifts to software standby mode after the SLEEP
instruction has been executed
This bit cannot be set to 1 when the watchdog timer (WDT)
is operating (when the TME bit in TCSR of the WDT is set
to 1). When transferring to software standby mode, clear
the TME bit to 0, stop the WDT, then set the SSBY bit to 1.
6
HIZ
0
R/W
Port High-Impedance
In software standby mode, this bit selects whether the pin
state of the I/O port is retained or changed to high-
impedance.
0: In software standby mode, the pin state is retained.
1: In software standby mode, the pin state is changed to
high-impedance.
The HIZ bit cannot be set to 1 when the TME bit in TCSR of
the WDT is set to 1.
When changing the pin state of the I/O port to high-
impedance, clear the TME bit to 0, then set the HIZ bit to 1.
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17. Power-Down Modes
Initial
Bit
Bit Name Value
R/W
Description
5
⎯
0
R
Reserved
This bit is always read as 0. The write value should always
be 0.
4 to 1
0
⎯
All 1
1
R
Reserved
These bits are always read as 1. The write value should
always be 1.
IRQEL
R/W
IRQ3 to IRQ0 Enable
IRQ interrupts are enabled to clear software standby mode.
0: Software standby mode is cleared.
1: Software standby mode is not cleared.
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17. Power-Down Modes
17.2.2
System Control Register (SYSCR)
SYSCR is an 8-bit readable/writable register that enables/disables the access to the on-chip RAM.
Initial
Bit
Bit Name Value
R/W
Description
7, 6
⎯
All 1
All 0
1
R
Reserved
These bits are always read as 1. The write value should
always be 1.
5 to 1
0
⎯
R
Reserved
These bits are always read as 0. The write value should
always be 0.
RAME
R/W
RAM Enable
This bit enables/disables the on-chip RAM.
0: On-chip RAM disabled
1: On-chip RAM enabled
When this bit is cleared to 0, the access to the on-chip RAM
is disabled. In this case, an undefined value is returned
when reading or fetching the data or instruction from the on-
chip RAM, and writing to the on-chip RAM is ignored.
When RAME is cleared to 0 to disable the on-chip RAM, an
instruction to access the on-chip RAM should not be set
next to the instruction to write to SYSCR. If such an
instruction is set, normal access is not guaranteed.
When RAME is set to 1 to enable the on-chip RAM, an
instruction to read SYSCR should be set next to the
instruction to write to SYSCR. If an instruction to access the
on-chip RAM is set next to the instruction to write to
SYSCR, normal access is not guaranteed.
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17. Power-Down Modes
17.2.3
Module Standby Control Register 1 and 2 (MSTCR1 and MSTCR2)
MSTCR, comprising two 16-bit readable/writable registers, performs module standby mode
control. Setting a bit to 1, the corresponding module enters module standby mode, while clearing
the bit to 0 clears the module standby mode.
MSTCR1
Initial
Bit
Bit Name Value
R/W
Description
15 to 12
⎯
All 1
R
Reserved
These bits are always read as 1. The write value should
always be 1.
11
MSTP27
MSTP26
⎯
0
R/W
R/W
R
On-chip RAM
On-chip ROM
Reserved
10
0
9, 8
All 0
These bits are always read as 0. The write value should
always be 0.
7, 6
5
⎯
⎯
⎯
All 0
1
R
R
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Reserved
This bit is always read as 1. The write value should
always be 1.
4
1
Reserved
This bit is always read as 1. The write value should
always be 1.
3
MSTP19
MSTP18
⎯
1
R/W
R/W
R
Serial communication interface 3 (SCI_3)
Serial communication interface 2 (SCI_2)
Reserved
2
1
1, 0
All 1
These bits are always read as 1. The write value should
always be 1.
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17. Power-Down Modes
MSTCR2
Initial
Bit
Bit Name Value
R/W
Description
15
⎯
1
R
Reserved
This bit is always read as 1. The write value should always
be 1.
14
⎯
1
R
Reserved
This bit is always read as 1. The write value should always
be 1.
13
12
MSTP13
MSTP12
1
R/W
R/W
R
Multi-function timer pulse unit (MTU)
Compare match timer (CMT)
Reserved
1
11, 10 ⎯
All 0
These bits are always read as 0. The write value should
always be 0.
9
8
7
6
⎯
⎯
⎯
⎯
0
0
1
1
R
R
R
R
Reserved
This bit is always read as 0. The write value should always
be 0.
Reserved
This bit is always read as 0. The write value should always
be 0.
Reserved
This bit is always read as 1. The write value should always
be 1.
Reserved
This bit is always read as 1. The write value should always
be 1.
5
MSTP5
MSTP4
⎯
1
R/W
R/W
R
A/D converter (A/D1)
A/D converter (A/D0)
Reserved
4
1
3 to 0
All 0
These bits are always read as 0. The write value should
always be 0.
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17. Power-Down Modes
17.3
Operation
17.3.1 Sleep Mode
Transition to Sleep Mode: If SLEEP instruction is executed while the SSBY bit in SBYCR = 0,
the CPU enters sleep mode. In sleep mode, CPU operation stops, however the contents of the
CPU's internal registers are retained. Peripheral functions except the CPU do not stop.
Clearing Sleep Mode: Sleep mode is cleared by the conditions below.
•
•
Clearing by the power on reset
When the RES pin is driven low, the CPU enters the reset state. When the RES pin is driven
high after the elapse of the specified reset input period, the CPU starts the reset exception
handling. Also, when the internal power on reset is occurred, sleep mode is cleared.
Clearing by the manual reset
When the MRES pin is driven low while the RES pin is high, the CPU shifts to the manual
reset state and thus sleep mode is cleared. Also, when the internal manual reset is occurred,
sleep mode is cleared.
Notes on Using Sleep Mode
•
There are 4 conditions to clear sleep mode.
(1) Clearing by an interrupt
(2) Clearing by DTC address error
(3) Clearing by the power-on reset
(4) Clearing by the manual reset
When clearing sleep mode by (1) or (2), CPU may run out of control. Please clear sleep mode
by (3) or (4), don't use (1) or (2).
•
Do not use DTC module or AUD module during sleep mode.
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17. Power-Down Modes
17.3.2
Software Standby Mode
Transition to Software Standby Mode: A transition is made to software standby mode if the
SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1. In this mode, the CPU,
on-chip peripheral functions, and the oscillator, all stop.
However, the contents of the CPU's internal registers and on-chip RAM data (when the RAME bit
in SYSCR is 0) are retained as long as the specified voltage is supplied. There are two types of on-
chip peripheral module registers; ones which are initialized by software standby mode, and those
not initialized by that mode. For details, refer to section 18.3, Register States in Each Operating
Mode. The port high-impedance bit (HIZ) in SBYCR sets the state of the I/O port either to
"retained" or "high-impedance". For the state of pins, refer to appendix A, Pin States. In software
standby mode, the oscillator stops and thus power consumption is significantly reduced.
Clearing Software Standby Mode: Software standby mode is cleared by the condition below.
•
Clearing by the NMI interrupt input
When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit
(NMIE) in ICR1 of the interrupt controller (INTC)) is detected, clock oscillation is started.
This clock pulse is supplied only to the watchdog timer (WDT).
After the elapse of the time set in the clock select bits (CKS2 to CKS0) in TCSR of the WDT
before the transition to software standby mode, the WDT overflow occurs. Since this overflow
indicates that the clock has been stabilized, clock pulse will be supplied to the entire chip after
this overflow. Software standby mode is thus cleared and the NMI exception handling is
started.
When clearing software standby mode by the NMI interrupt, set CKS2 to CKS0 bits so that the
WDT overflow period will be longer than the oscillation stabilization time.
When software standby mode is cleared by the falling edge of the NMI pin, the NMI pin
should be high when the CPU enters software standby mode (when the clock pulse stops) and
should be low when the CPU returns from standby mode (when the clock is initiated after the
oscillation stabilization). When software standby mode is cleared by the rising edge of the
NMI pin, the NMI pin should be low when the CPU enters software standby mode (when the
clock pulse stops) and should be high when the CPU returns from software standby mode
(when the clock is initiated after the oscillation stabilization).
•
Clearing by the RES pin
When the RES pin is driven low, clock oscillation is started. At the same time as clock
oscillation is started, clock pulse is supplied to the entire chip. Ensure that the RES pin is held
low until clock oscillation stabilizes. When the RES pin is driven high, the CPU starts the reset
exception handling.
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17. Power-Down Modes
•
Clearing by the IRQ interrupt input
When the IRQEL bit in the standby control register (SBYCR) is set to 1 and when the falling
edge or rising edge of the IRQ pin (selected by the IRQ3S to IRQ0S bits in ICR1 of the
interrupt controller (INTC) and the IRQ3ES [1:0] to IRQ0ES [1:0] bits in ICR2) is detected,
clock oscillation is started.* This clock pulse is supplied only to the watchdog timer (WDT).
The IRQ interrupt priority level should be higher than the interrupt mask level set in the status
register (SR) of the CPU before the transition to software standby mode.
After the elapse of the time set in the clock select bits (CKS2 to CKS0) in TCSR of the WDT
before the transition to software standby mode, the WDT overflow occurs. Since this overflow
indicates that the clock has been stabilized, clock pulse will be supplied to the entire chip after
this overflow. Software standby mode is thus cleared and the IRQ exception handling is started.
When clearing software standby mode by the IRQ interrupt, set CKS2 to CKS0 bits so that the
WDT overflow period will be longer than the oscillation stabilization time.
When software standby mode is cleared by the falling edge or both edges of the IRQ pin, the
IRQ pin should be high when the CPU enters software standby mode (when the clock pulse
stops) and should be low when the CPU returns from software standby mode (when the clock
is initiated after the oscillation stabilization). When software standby mode is cleared by the
rising edge of the IRQ pin, the IRQ pin should be low when the CPU enters software standby
mode (when the clock pulse stops) and should be high when the CPU returns from software
standby mode (when the clock is initiated after the oscillation stabilization).
Note: * When the IRQ pin is set to falling-edge detection or both-edge detection, clock
oscillation starts at falling-edge detection. When the IRQ pin is set to rising-edge
detection, clock oscillation starts at rising-edge detection. Do not set the IRQ pin to
low-level detection.
Software Standby Mode Application Example: Figure 17.2 shows an example in which a
transition is made to software standby mode at the falling edge of the NMI pin, and software
standby mode is cleared at a rising edge of the NMI pin.
In this example, when the NMI pin is driven low while the NMI edge select bit (NMIE) in ICR1 is
0 (falling edge detection), an NMI interrupt is accepted. Then, the NMIE bit is set to 1 (rising edge
detection) in the NMI exception service routine, the SSBY bit in SBYCR is set to 1, and a SLEEP
instruction is executed to transfer to software standby mode.
Software standby mode is cleared by driving the NMI pin from low to high.
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17. Power-Down Modes
Oscillator
CK
NMI input
NMIE bit
SSBY bit
NMI
Program
execution state
Exception
service routine
Software
standby mode
Oscillation
WDT
NMI exception
handling
LSI state
exception
handling
start time setting time
Oscillation stabilization
time
Figure 17.2 NMI Timing in Software Standby Mode
Module Standby Mode
17.3.3
Module standby mode can be set for individual on-chip peripheral functions.
When the corresponding MSTP bit in MSTCR is set to 1, module operation stops at the end of the
bus cycle and a transition is made to module standby mode. The CPU continues operating
independently.
When the corresponding MSTP bit is cleared to 0, module standby mode is cleared and the
module starts operating at the end of the bus cycle. In module standby mode, the internal states of
modules are initialized.
After reset clearing, the SCI, MTU, CMT, and A/D converter are in module standby mode.
When an on-chip peripheral module is in module standby mode, read/write access to its registers is
disabled.
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17. Power-Down Modes
17.4
Usage Notes
17.4.1
I/O Port Status
When a transition is mode to software standby mode while the port high-impedance bit (HIZ) in
SBYCR is 0, I/O port states are retained. Therefore, there is no reduction in current consumption
for the output current when a high-level signal is output.
17.4.2
Current consumption increases during the oscillation stabilization wait period.
17.4.3 On-Chip Peripheral Module Interrupt
Current Consumption during Oscillation Stabilization Wait Period
Relevant interrupt operations cannot be performed in module standby mode. Consequently, if the
CPU enters module standby mode while an interrupt has been requested, it will not be possible to
clear the CPU interrupt source.
Interrupts should therefore be disabled before entering module standby mode.
17.4.4
Writing to MSTCR1 and MSTCR2
MSTCR1 and MSTCR2 should only be written to by the CPU.
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17. Power-Down Modes
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18. List of Registers
Section 18 List of Registers
The column “Access Size” shows the number of bits.
The column “Access States” shows the number of access states, in units of cycles, of the specified
reference clock. B, W, and L in the column represent 8-bit, 16-bit, and 32-bit access, respectively.
18.1
Register Addresses (Order of Address)
Access Access
Register Name
Abbreviation Bits Address
Module
Size
States
⎯
⎯
⎯
H'FFFF8000 to
H'FFFF81BF
⎯
⎯
⎯
Serial mode register_2
Bit rate register_2
SMR_2
BRR_2
SCR_2
TDR_2
SSR_2
RDR_2
8
8
H'FFFF81C0
H'FFFF81C1
H'FFFF81C2
H'FFFF81C3
H'FFFF81C4
H'FFFF81C5
H'FFFF81C6
SCI
(channel 2)
8, 16
In Pφ cycles
B: 2
W: 4
8
Serial control register_2
Transmit data register_2
Serial status register_2
Receive data register_2
8
8, 16
8
8
8
8, 16
8
8
8
Serial direction control register_2 SDCR_2
8
⎯
⎯
⎯
H'FFFF81C7 to
H'FFFF81CF
⎯
Serial mode register_3
Bit rate register_3
SMR_3
BRR_3
SCR_3
TDR_3
SSR_3
RDR_3
8
8
H'FFFF81D0
H'FFFF81D1
H'FFFF81D2
H'FFFF81D3
H'FFFF81D4
H'FFFF81D5
H'FFFF81D6
SCI
(channel 3)
8, 16
8
Serial control register_3
Transmit data register_3
Serial status register_3
Receive data register_3
8
8, 16
8
8
8
8, 16
8
8
8
Serial direction control register_3 SDCR_3
8
⎯
⎯
⎯
H'FFFF81D7 to
H'FFFF81FF
⎯
Timer control register_3
Timer control register_4
Timer mode register_3
TCR_3
8
8
8
8
8
8
H'FFFF8200
H'FFFF8201
H'FFFF8202
H'FFFF8203
H'FFFF8204
H'FFFF8205
MTU
(channels 3
and 4)
8, 16, 32 In Pφ cycles
B: 2
W: 2
TCR_4
8
TMDR_3
TMDR_4
TIORH_3
TIORL_3
8, 16
L: 4
Timer mode register_4
8
Timer I/O control register H_3
Timer I/O control register L_3
8, 16, 32
8
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18. List of Registers
Access Access
Register Name
Abbreviation Bits Address
Module
Size
8, 16
8
States
Timer I/O control register H_4
Timer I/O control register L_4
TIORH_4
TIORL_4
8
8
8
8
8
H'FFFF8206
H'FFFF8207
H'FFFF8208
H'FFFF8209
H'FFFF820A
MTU
(channels 3
and 4)
In Pφ cycles
B: 2
W: 2
Timer interrupt enable register_3 TIER_3
Timer interrupt enable register_4 TIER_4
8, 16, 32
8
L: 4
Timer output master enable
register
TOER
8, 16
Timer output control register
⎯
TOCR
⎯
8
H'FFFF820B
H'FFFF820C
H'FFFF820D
H'FFFF820E
H'FFFF820F
8
8
⎯
8
Timer gate control register
⎯
TGCR
⎯
⎯
⎯
⎯
⎯
Timer counter_3
TCNT_3
TCNT_4
TCDR
TDDR
TGRA_3
TGRB_3
TGRA_4
TGRB_4
TCNTS
TCBR
16 H'FFFF8210
16 H'FFFF8212
16 H'FFFF8214
16 H'FFFF8216
16 H'FFFF8218
16 H'FFFF821A
16 H'FFFF821C
16 H'FFFF821E
16 H'FFFF8220
16 H'FFFF8222
16 H'FFFF8224
16 H'FFFF8226
16 H'FFFF8228
16 H'FFFF822A
16, 32
16
Timer counter_4
Timer period data register
Timer dead time data register
Timer general register A_3
Timer general register B_3
Timer general register A_4
Timer general register B_4
Timer sub-counter
16, 32
16
16, 32
16
16, 32
16
16, 32
16
Timer period buffer register
Timer general register C_3
Timer general register D_3
Timer general register C_4
Timer general register D_4
Timer status register_3
Timer status register_4
⎯
TGRC_3
TGRD_3
TGRC_4
TGRD_4
TSR_3
TSR_4
⎯
16, 32
16
16, 32
16
8
8
H'FFFF822C
H'FFFF822D
8, 16
8
⎯
H'FFFF822E to
H'FFFF823F
Timer start register
Timer synchro register
⎯
TSTR
TSYR
⎯
8
8
H'FFFF8240
H'FFFF8241
MTU
(common)
8, 16
8
In Pφ cycles
B: 2
W: 2
⎯
H'FFFF8242 to
H'FFFF825F
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18. List of Registers
Access Access
Register Name
Abbreviation Bits Address
Module
Size
States
Timer control register_0
Timer mode register_0
Timer I/O control register H_0
Timer I/O control register L_0
TCR_0
8
8
8
8
8
8
H'FFFF8260
H'FFFF8261
H'FFFF8262
H'FFFF8263
H'FFFF8264
H'FFFF8265
MTU
(channel 0)
8, 16, 32 In Pφ cycles
B: 2
W: 2
TMDR_0
TIORH_0
TIORL_0
8
8, 16
8
L: 4
Timer interrupt enable register_0 TIER_0
8, 16, 32
8
Timer status register_0
Timer counter_0
TSR_0
TCNT_0
TGRA_0
TGRB_0
TGRC_0
TGRD_0
⎯
16 H'FFFF8266
16 H'FFFF8268
16 H'FFFF826A
16 H'FFFF826C
16 H'FFFF826E
16
Timer general register A_0
Timer general register B_0
Timer general register C_0
Timer general register D_0
⎯
16, 32
16
16, 32
16
⎯
H'FFFF8270 to
H'FFFF827F
⎯
Timer control register_1
Timer mode register_1
Timer I/O control register_1
⎯
TCR_1
TMDR_1
TIOR_1
⎯
8
8
H'FFFF8280
H'FFFF8281
H'FFFF8282
H'FFFF8283
H'FFFF8284
H'FFFF8285
MTU
(channel 1)
8, 16
8
8
8
⎯
8
⎯
Timer interrupt enable register_1 TIER_1
8, 16, 32
Timer status register_1
Timer counter_1
TSR_1
TCNT_1
TGRA_1
TGRB_1
⎯
8
8
16 H'FFFF8286
16 H'FFFF8288
16 H'FFFF828A
16
Timer general register A_1
Timer general register B_1
⎯
16, 32
16
⎯
H'FFFF828C to
H'FFFF829F
⎯
Timer control register_2
Timer mode register_2
Timer I/O control register_2
⎯
TCR_2
TMDR_2
TIOR_2
⎯
8
8
H'FFFF82A0
H'FFFF82A1
H'FFFF82A2
H'FFFF82A3
H'FFFF82A4
H'FFFF82A5
MTU
(channel 2)
8, 16
8
8
8
⎯
8
⎯
Timer interrupt enable register_2 TIER_2
8, 16, 32
Timer status register_2
Timer counter_2
TSR_2
8
8
TCNT_2
16 H'FFFF82A6
16
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18. List of Registers
Access Access
Register Name
Abbreviation Bits Address
Module
Size
16, 32
16
States
Timer general register A_2
Timer general register B_2
⎯
TGRA_2
TGRB_2
⎯
16 H'FFFF82A8
16 H'FFFF82AA
MTU
(channel 2)
In Pφ cycles
B: 2
W: 2
⎯
H'FFFF82AC to
H'FFFF833F
⎯
L: 4
⎯
⎯
⎯
H'FFFF8340 to INTC
H'FFFF8347
⎯
In φ cycles
B: 2
W: 2
L: 4
Interrupt priority register A
IPRA
16 H'FFFF8348
8, 16
⎯
⎯
⎯
H'FFFF834A to
H'FFFF834D
⎯
Interrupt priority register D
Interrupt priority register E
Interrupt priority register F
Interrupt priority register G
Interrupt priority register H
Interrupt control register 1
IRQ status register
IPRD
IPRE
IPRF
IPRG
IPRH
ICR1
ISR
16 H'FFFF834E
16 H'FFFF8350
16 H'FFFF8352
16 H'FFFF8354
16 H'FFFF8356
16 H'FFFF8358
16 H'FFFF835A
16 H'FFFF835C
8, 16
8, 16, 32
8, 16
8, 16, 32
8, 16
8, 16, 32
8, 16
Interrupt priority register I
⎯
IPRI
⎯
8, 16, 32
⎯
⎯
H'FFFF835E to
H'FFFF8365
Interrupt control register 2
ICR2
8
H'FFFF8366
8, 16
⎯
⎯
⎯
H'FFFF8368 to
H'FFFF837F
⎯
⎯
⎯
⎯
H'FFFF8380 to
H'FFFF8381
⎯
⎯
⎯
Port A data register L
PADRL
16 H'FFFF8382
I/O
8, 16
In φ cycles
B: 2
W: 2
⎯
⎯
⎯
H'FFFF8384 to
H'FFFF8385
⎯
⎯
L: 4
Port A I/O register L
PAIORL
16 H'FFFF8386
PFC
8, 16
⎯
⎯
⎯
H'FFFF8388 to
H'FFFF8389
⎯
⎯
Port A control register L3
Port A control register L1
Port A control register L2
Port B data register
⎯
PACRL3
PACRL1
PACRL2
PBDR
16 H'FFFF838A
16 H'FFFF838C
16 H'FFFF838E
16 H'FFFF8390
PFC
8, 16
8, 16, 32
8, 16
8, 16
⎯
I/O
⎯
⎯
H'FFFF8392 to
H'FFFF8393
⎯
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18. List of Registers
Access Access
Register Name
Port B I/O register
⎯
Abbreviation Bits Address
Module
PFC
⎯
Size
States
PBIOR
16 H'FFFF8394
8, 16, 32 In φ cycles
B: 2
W: 2
L: 4
⎯
⎯
H'FFFF8396 to
H'FFFF8397
⎯
Port B control register 1
Port B control register 2
⎯
PBCR1
PBCR2
⎯
16 H'FFFF8398
16 H'FFFF839A
PFC
8, 16, 32
8, 16
⎯
H'FFFF839C to
H'FFFF83AE
⎯
⎯
Port E data register L
Port F data register
PEDRL
PFDR
16 H'FFFF83B0
16 H'FFFF83B2
16 H'FFFF83B4
16 H'FFFF83B6
16 H'FFFF83B8
16 H'FFFF83BA
16 H'FFFF83BC
16 H'FFFF83BE
16 H'FFFF83C0
16 H'FFFF83C2
I/O
8, 16, 32
8, 16
Port E I/O register L
PEIORL
PEIORH
PECRL1
PECRL2
PECRH
PEDRH
ICSR1
PFC
8, 16, 32
8, 16
Port E I/O register H
Port E control register L1
Port E control register L2
Port E control register H
Port E data register H
Input control/status register 1
Output control/status register
8, 16, 32
8, 16
8, 16, 32
8, 16
I/O
MTU
8, 16, 32 In φ cycles
B: 2
W: 2
OCSR
8, 16
L: 4
⎯
⎯
⎯
H'FFFF83C4 to
H'FFFF83CC
⎯
⎯
Port G data register
PGDR
8
H'FFFF83CD
I/O
8
In Pφ cycles
B: 2
W: 2
L: 4
⎯
⎯
⎯
H'FFFF83CE to
H'FFFF83CF
⎯
⎯
⎯
Compare match timer start
register
CMSTR
CMCSR_0
16 H'FFFF83D0
16 H'FFFF83D2
CMT
8, 16, 32 In φ cycles
B: 2
W: 2
L: 4
Compare match timer
control/status register_0
8, 16
Compare match timer counter_0 CMCNT_0
16 H'FFFF83D4
16 H'FFFF83D6
8, 16, 32
8, 16
Compare match timer constant
register_0
CMCOR_0
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18. List of Registers
Access Access
Size States
Register Name
Abbreviation Bits Address
Module
CMCSR_1
16 H'FFFF83D8
CMT
8, 16, 32 In φ cycles
Compare match timer
B: 2
control/status register_1
W: 2
CMCNT_1
CMCOR_1
16 H'FFFF83DA
16 H'FFFF83DC
8, 16
L: 4
Compare match timer counter_1
8, 16
Compare match timer constant
register_1
⎯
⎯
⎯
⎯
⎯
⎯
H'FFFF83DE
H'FFFF83E0 to
H'FFFF842E
⎯
⎯
⎯
A/D data register 8
ADDR8
16 H'FFFF8430
A/D
(channel 0)
8, 16
In Pφ cycles
B: 3
W: 6
A/D data register 9
A/D data register 10
A/D data register 11
A/D data register 12
A/D data register 13
A/D data register 14
A/D data register 15
⎯
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
⎯
16 H'FFFF8432
16 H'FFFF8434
16 H'FFFF8436
16 H'FFFF8438
16 H'FFFF843A
16 H'FFFF843C
16 H'FFFF843E
8, 16
8, 16
8, 16
8, 16
8, 16
8, 16
8, 16
⎯
A/D
(channel 1)
⎯
H'FFFF8440 to
H'FFFF847F
⎯
A/D control/status register_0
A/D control/status register_1
⎯
ADCSR_0
ADCSR_1
⎯
8
8
H'FFFF8480
H'FFFF8481
A/D
8, 16
8
⎯
H'FFFF8482 to
H'FFFF8487
⎯
A/D control register_0
A/D control register_1
⎯
ADCR_0
ADCR_1
⎯
8
8
H'FFFF8488
H'FFFF8489
8, 16
8
⎯
H'FFFF848A to
H'FFFF860F
⎯
⎯
Timer control/status register
Timer counter
TCSR
TCNT*1
TCNT*2
RSTCSR*1
RSTCSR*2
SBYCR
8
8
8
8
8
8
H'FFFF8610
H'FFFF8610
H'FFFF8611
H'FFFF8612
H'FFFF8613
H'FFFF8614
WDT
8*2/16*1 In φ cycles
B: 3
W: 3
*1:Write
16
cycle
Timer counter
8
*2:Read
Reset control/status register
Reset control/status register
Standby control register
16
8
cycle
Power-
8
In φ cycles
down state
B: 3
Rev.2.00 Sep. 27, 2007 Page 406 of 448
REJ09B0394-0200
18. List of Registers
Access Access
Register Name
Abbreviation Bits Address
Module
Size
States
⎯
⎯
⎯
H'FFFF8615 to
H'FFFF8617
⎯
⎯
⎯
System control register
SYSCR
8
H'FFFF8618
Power-
down state
8
In Pφ cycles
B: 3
W: 3
⎯
⎯
⎯
H'FFFF8619 to
H'FFFF861B
⎯
L: 6
Module standby control register 1 MSTCR1
Module standby control register 2 MSTCR2
16 H'FFFF861C
16 H'FFFF861E
16 H'FFFF8620
8, 16, 32
8, 16
Bus control register 1
BCR1
BSC
A/D
8, 16, 32 In φ cycles
B: 3
W: 3
L: 6
⎯
⎯
⎯
H'FFFF8622 to
H'FFFF8626
⎯
⎯
⎯
H'FFFF8628 to
H'FFFF87F3
⎯
AD trigger select register
ADTSR
8
H'FFFF87F4
8
In Pφ cycles
B: 3
⎯
⎯
H'FFFF87F5 to
H'FFFF89FF
⎯
⎯
⎯
H'FFFF8A00 to
H'FFFFB4F3
⎯
Rev.2.00 Sep. 27, 2007 Page 407 of 448
REJ09B0394-0200
18. List of Registers
18.2
Register Bits
On-chip peripheral module register addresses and bit names are shown in the following table.
16-bit and 32-bit registers are shown in two and four rows of 8 bits, respectively.
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
SMR_2
BRR_2
SCR_2
TDR_2
SSR_2
RDR_2
SDCR_2
SMR_3
BRR_3
SCR_3
TDR_3
SSR_3
RDR_3
SDCR_3
⎯
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
SCI
(channel 2)
TIE
RIE
TE
RE
MPIE
PER
TEIE
CKE1
MPB
CKE0
MPBT
TDRE
RDRF
ORER
FER
TEND
⎯
⎯
⎯
⎯
DIR
⎯
⎯
⎯
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
SCI
(channel 3)
TIE
RIE
TE
RE
MPIE
PER
TEIE
CKE1
MPB
CKE0
MPBT
TDRE
RDRF
ORER
FER
TEND
⎯
⎯
⎯
⎯
DIR
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
TCR_3
TCR_4
TMDR_3
TMDR_4
TIORH_3
TIORL_3
TIORH_4
TIORL_4
TIER_3
TIER_4
TOER
CCLR2
CCLR2
⎯
CCLR1
CCLR1
⎯
CCLR0
CCLR0
BFB
BFB
IOB1
IOD1
IOB1
IOD1
⎯
CKEG1
CKEG1
BFA
CKEG0
CKEG0
MD3
MD3
IOA3
IOC3
IOA3
IOC3
TGIED
TGIED
OE3D
⎯
TPSC2
TPSC2
MD2
MD2
IOA2
IOC2
IOA2
IOC2
TGIEC
TGIEC
OE4B
⎯
TPSC1
TPSC1
MD1
MD1
IOA1
IOC1
IOA1
IOC1
TGIEB
TGIEB
OE4A
OLSN
VF
TPSC0
TPSC0
MD0
MD0
IOA0
IOC0
IOA0
IOC0
TGIEA
TGIEA
OE3B
OLSP
UF
MTU
(channels 3
and 4)
⎯
⎯
BFA
IOB3
IOD3
IOB3
IOD3
TTGE
TTGE
⎯
IOB2
IOD2
IOB2
IOD2
⎯
IOB0
IOD0
IOB0
IOD0
TCIEV
TCIEV
OE4C
⎯
⎯
⎯
⎯
OE4D
⎯
TOCR
⎯
PSYE
BDC
TGCR
⎯
N
P
FB
WF
TCNT_3
Rev.2.00 Sep. 27, 2007 Page 408 of 448
REJ09B0394-0200
18. List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
TCNT_4
TCDR
MTU
(channels 3
and 4)
TDDR
TGRA_3
TGRB_3
TGRA_4
TGRB_4
TCNTS
TCBR
TGRC_3
TGRD_3
TGRC_4
TGRD_4
TSR_3
TSR_4
TSTR
TCFD
TCFD
CST4
SYNC4
CCLR2
⎯
⎯
⎯
TCFV
TCFV
⎯
TGFD
TGFD
⎯
TGFC
TGFC
CST2
SYNC2
TPSC2
MD2
TGFB
TGFB
CST1
SYNC1
TPSC1
MD1
TGFA
TGFA
CST0
SYNC0
TPSC0
MD0
⎯
⎯
CST3
SYNC3
CCLR1
⎯
⎯
TSYR
⎯
⎯
⎯
TCR_0
TMDR_0
TIORH_0
TIORL_0
TIER_0
TSR_0
CCLR0
BFB
IOB1
IOD1
⎯
CKEG1
BFA
CKEG0
MD3
MTU
(channel 0)
IOB3
IOD3
TTGE
⎯
IOB2
IOD2
⎯
IOB0
IOD0
TCIEV
TCFV
IOA3
IOC3
TGIED
TGFD
IOA2
IOA1
IOA0
IOC2
IOC1
IOC0
TGIEC
TGFC
TGIEB
TGFB
TGIEA
TGFA
⎯
⎯
Rev.2.00 Sep. 27, 2007 Page 409 of 448
REJ09B0394-0200
18. List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
TCNT_0
TGRA_0
TGRB_0
TGRC_0
TGRD_0
MTU
(channel 0)
TCR_1
⎯
CCLR1
⎯
CCLR0
⎯
CKEG1
⎯
CKEG0
MD3
IOA3
⎯
TPSC2
MD2
IOA2
⎯
TPSC1
MD1
TPSC0
MD0
MTU
(channel 1)
TMDR_1
TIOR_1
TIER_1
TSR_1
⎯
IOB3
TTGE
TCFD
IOB2
⎯
IOB1
TCIEU
TCFU
IOB0
TCIEV
TCFV
IOA1
IOA0
TGIEB
TGFB
TGIEA
TGFA
⎯
⎯
⎯
TCNT_1
TGRA_1
TGRB_1
TCR_2
⎯
CCLR1
⎯
CCLR0
⎯
CKEG1
⎯
CKEG0
MD3
IOA3
⎯
TPSC2
MD2
IOA2
⎯
TPSC1
MD1
TPSC0
MD0
MTU
(channel 2)
TMDR_2
TIOR_2
TIER_2
TSR_2
⎯
IOB3
TTGE
TCFD
IOB2
⎯
IOB1
TCIEU
TCFU
IOB0
TCIEV
TCFV
IOA1
IOA0
TGIEB
TGFB
TGIEA
TGFA
⎯
⎯
⎯
TCNT_2
TGRA_2
TGRB_2
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Rev.2.00 Sep. 27, 2007 Page 410 of 448
REJ09B0394-0200
18. List of Registers
Register
Abbreviation Bit 7
Bit 6
IRQ0
IRQ2
MTU0
MTU1
MTU2
MTU3
MTU4
⎯
Bit 5
IRQ0
IRQ2
MTU0
MTU1
MTU2
MTU3
MTU4
⎯
Bit 4
IRQ0
IRQ2
MTU0
MTU1
MTU2
MTU3
MTU4
⎯
Bit 3
IRQ1
IRQ3
MTU0
MTU1
MTU2
MTU3
MTU4
⎯
Bit 2
IRQ1
IRQ3
MTU0
MTU1
MTU2
MTU3
MTU4
⎯
Bit 1
IRQ1
IRQ3
MTU0
MTU1
MTU2
MTU3
MTU4
⎯
Bit 0
IRQ1
IRQ3
MTU0
MTU1
MTU2
MTU3
MTU4
⎯
Module
IPRA
IPRD
IPRE
IPRF
IPRG
IPRH
ICR1
ISR
IRQ0
IRQ2
MTU0
MTU1
MTU2
MTU3
MTU4
⎯
INTC
A/D0,1
CMT0
WDT
⎯
A/D0,1
CMT0
WDT
⎯
A/D0,1
CMT0
WDT
⎯
A/D0,1
CMT0
WDT
⎯
⎯
⎯
⎯
⎯
CMT1
CMT1
CMT1
CMT1
I/O(MTU) I/O(MTU) I/O(MTU) I/O(MTU)
⎯
⎯
⎯
⎯
NMIL
IRQ0S
⎯
⎯
⎯
⎯
⎯
⎯
⎯
NMIE
⎯
IRQ1S
⎯
IRQ2S
⎯
IRQ3S
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
IRQ0F
SCI2
⎯
IRQ1F
SCI2
⎯
IRQ2F
SCI2
⎯
IRQ3F
SCI2
⎯
⎯
⎯
⎯
⎯
IPRI
SCI3
⎯
SCI3
⎯
SCI3
⎯
SCI3
⎯
ICR2
IRQ0ES1 IRQ0ES0 IRQ1ES1 IRQ1ES0 IRQ2ES1 IRQ2ES0 IRQ3ES1 IRQ3ES0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PADRL
PA15DR PA14DR
PA7DR PA6DR
PA13DR PA12DR
PA5DR PA4DR
PA11DR PA10DR
PA3DR PA2DR
PA9DR
PA1DR
PA8DR
PA0DR
PA8IOR
PA0IOR
Port A
PAIORL
PACRL3
PACRL1
PACRL2
PA15IOR PA14IOR PA13IOR PA12IOR PA11IOR PA10IOR PA9IOR
PA7IOR PA6IOR PA5IOR PA4IOR PA3IOR PA2IOR PA1IOR
PA15MD2 PA14MD2 PA13MD2 PA12MD2 PA11MD2 PA10MD2 PA9MD2 PA8MD2
PA7MD2 PA6MD2 PA5MD2 PA4MD2 PA3MD2 PA2MD2 PA1MD2 PA0MD2
PA15MD1 PA15MD0 PA14MD1 PA14MD0 PA13MD1 PA13MD0 PA12MD1 PA12MD0
PA11MD1 PA11MD0 PA10MD1 PA10MD0 PA9MD1 PA9MD0 PA8MD1 PA8MD0
PA7MD1 PA7MD0 PA6MD1 PA6MD0 PA5MD1 PA5MD0 PA4MD1 PA4MD0
PA3MD1 PA3MD0 PA2MD1 PA2MD0 PA1MD1 PA1MD0 PA0MD1 PA0MD0
Rev.2.00 Sep. 27, 2007 Page 411 of 448
REJ09B0394-0200
18. List of Registers
Register
Abbreviation Bit 7
Bit 6
⎯
Bit 5
⎯
Bit 4
⎯
Bit 3
⎯
Bit 2
⎯
Bit 1
⎯
Bit 0
⎯
Module
PBDR
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Port B
⎯
PB5DR
⎯
PB4DR
⎯
PB3DR
⎯
PB2DR
⎯
⎯
⎯
PBIOR
PBCR1
PBCR2
PEDRL
PFDR
⎯
⎯
⎯
⎯
PB5IOR
PB4 IOR PB3 IOR PB2 IOR
⎯
⎯
⎯
PB5MD2 PB4MD2 PB3MD2 PB2MD2
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PB5MD1 PB5MD0 PB4MD1 PB4MD0
PB3MD1 PB3MD0 PB2MD1 PB2MD0
PE15DR PE14DR PE13DR PE12DR
⎯
⎯
⎯
⎯
PE11DR PE10DR
PE9DR
PE1DR
PF9DR
PF1DR
PE8DR
PE0DR
PF8DR
PF0DR
Port E
Port F
PE7DR
PF15DR
PF7DR
PE6DR
PF14DR
PF6DR
PE5DR
PF13DR
PF5DR
PE4DR
PF12DR
PF4DR
PE3DR
PF11DR
PF3DR
PE2DR
PF10DR
PF2DR
PEIORL
PEIORH
PECRL1
PECRL2
PECRH
PEDRH
PE15IOR PE14 IOR PE13 IOR PE12 IOR PE11 IOR PE10 IOR PE9 IOR PE8 IOR Port E
PE7IOR
PE6IOR
PE5IOR
PE4IOR
PE3IOR
PE2IOR
PE1IOR
PE0IOR
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PE21IOR PE20IOR PE19IOR PE18IOR PE17IOR PE16IOR
PE15MD1 PE15MD0 PE14MD1 PE14MD0 PE13MD1 PE13MD0 PE12MD1 PE12MD0
PE11MD1 PE11MD0 PE10MD1 PE10MD0 PE9MD1 PE9MD0 PE8MD1 PE8MD0
PE7MD1 PE7MD0 PE6MD1 PE6MD0 PE5MD1 PE5MD0 PE4MD1 PE4MD0
PE3MD1 PE3MD0 PE2MD1 PE2MD0 PE1MD1 PE1MD0 PE0MD1 PE0MD0
⎯
⎯
⎯
⎯
PE21MD1 PE21MD0 PE20MD1 PE20MD0
PE19MD1 PE19MD0 PE18MD1 PE18MD0 PE17MD1 PE17MD0 PE16MD1 PE16MD0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PE21DR PE20DR
PE19DR PE18DR
PE17DR PE16DR
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
ICSR1
POE3F
POE2F
POE1F
POE0F
PIE
MTU
POE3M1 POE3M0 POE2M1 POE2M0 POE1M1 POE1M0 POE0M1 POE0M0
OCSR
OSF
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
OCE
⎯
OIE
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PGDR
⎯
⎯
PG3DR
⎯
PG2DR
⎯
PG1DR
⎯
PG0DR
⎯
Port G
⎯
⎯
Rev.2.00 Sep. 27, 2007 Page 412 of 448
REJ09B0394-0200
18. List of Registers
Register
Abbreviation Bit 7
Bit 6
⎯
Bit 5
⎯
Bit 4
⎯
Bit 3
⎯
Bit 2
⎯
Bit 1
⎯
Bit 0
⎯
Module
CMSTR
⎯
CMT
⎯
⎯
⎯
⎯
⎯
⎯
STR1
⎯
STR0
⎯
CMCSR_0
CMCNT_0
CMCOR_0
CMCSR_1
CMCNT_1
CMCOR_1
⎯
⎯
⎯
⎯
⎯
⎯
CMF
CMIE
⎯
⎯
⎯
⎯
CKS1
CKS0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
CMF
CMIE
CKS1
CKS0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
ADDR8
AD9
AD1
AD9
AD1
AD9
AD1
AD9
AD1
AD9
AD1
AD9
AD1
AD9
AD1
AD9
AD1
ADF
ADF
TRGE
TRGE
⎯
AD8
AD0
AD8
AD0
AD8
AD0
AD8
AD0
AD8
AD0
AD8
AD0
AD8
AD0
AD8
AD0
ADIE
ADIE
CKS1
CKS1
⎯
AD7
⎯
AD6
⎯
AD5
⎯
AD4
⎯
AD3
⎯
AD2
⎯
A/D
ADDR9
AD7
⎯
AD6
⎯
AD5
⎯
AD4
⎯
AD3
⎯
AD2
⎯
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
AD7
⎯
AD6
⎯
AD5
⎯
AD4
⎯
AD3
⎯
AD2
⎯
AD7
⎯
AD6
⎯
AD5
⎯
AD4
⎯
AD3
⎯
AD2
⎯
AD7
⎯
AD6
⎯
AD5
⎯
AD4
⎯
AD3
⎯
AD2
⎯
AD7
⎯
AD6
⎯
AD5
⎯
AD4
⎯
AD3
⎯
AD2
⎯
AD7
⎯
AD6
⎯
AD5
⎯
AD4
⎯
AD3
⎯
AD2
⎯
AD7
⎯
AD6
⎯
AD5
⎯
AD4
⎯
AD3
⎯
AD2
⎯
ADCSR_0
ADCSR_1
ADCR_0
ADCR_1
⎯
ADM1
ADM1
CKS0
CKS0
⎯
ADM0
ADM0
ADST
ADST
⎯
⎯
CH2
CH2
⎯
CH1
CH1
⎯
CH0
CH0
⎯
⎯
ADCS
ADCS
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Rev.2.00 Sep. 27, 2007 Page 413 of 448
REJ09B0394-0200
18. List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
TCSR
OVF
WT/IT
TME
⎯
⎯
CKS2
CKS1
CKS0
WDT
TCNT
RSTCSR
⎯
WOVF
⎯
RSTE
⎯
RSTS
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
SBYCR
SYSCR
MSTCR1
SSBY
⎯
HIZ
⎯
⎯
IRQEL
RAME
⎯
Power-down
state
⎯
⎯
⎯
⎯
MSTP27 MSTP26
MSTP19 MSTP18
⎯
⎯
⎯
⎯
MSTCR2
⎯
⎯
MSTP13 MSTP12
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
MSTP5
MSTP4
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
BCR1
⎯
⎯
MTURWE
⎯
⎯
BSC
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
ADTSR
⎯
⎯
⎯
⎯
TRG1S1 TRG1S0 TRG0S1 TRG0S0 A/D
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Rev.2.00 Sep. 27, 2007 Page 414 of 448
REJ09B0394-0200
18. List of Registers
18.3
Register States in Each Operating Mode
Register
Power-On
Software
Module
Abbreviation Reset
Manual Reset Standby
Standby
Sleep
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Module
SMR_2
BRR_2
SCR_2
TDR_2
SSR_2
RDR_2
SDCR_2
SMR_3
BRR_3
SCR_3
TDR_3
SSR_3
RDR_3
SDCR_3
TCR_3
TCR_4
TMDR_3
TMDR_4
TIORH_3
TIORL_3
TIORH_4
TIORL_4
TIER_3
TIER_4
TOER
Initialized
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
SCI
(channel 2)
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
SCI
(channel 3)
MTU
(channels 3
and 4)
TOCR
TGCR
TCNT_3
TCNT_4
TCDR
TDDR
Rev.2.00 Sep. 27, 2007 Page 415 of 448
REJ09B0394-0200
18. List of Registers
Register
Power-On
Software
Module
Abbreviation Reset
Manual Reset Standby
Standby
Sleep
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Module
TGRA_3
TGRB_3
TGRA_4
TGRB_4
TCNTS
TCBR
Initialized
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
MTU
(channels 3
and 4)
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
TGRC_3
TGRD_3
TGRC_4
TGRD_4
TSR_3
TSR_4
TSTR
TSYR
TCR_0
MTU
(channel 0)
TMDR_0
TIORH_0
TIORL_0
TIER_0
TSR_0
TCNT_0
TGRA_0
TGRB_0
TGRC_0
TGRD_0
TCR_1
TMDR_1
TIOR_1
TIER_1
TSR_1
TCNT_1
Rev.2.00 Sep. 27, 2007 Page 416 of 448
REJ09B0394-0200
18. List of Registers
Register
Power-On
Software
Module
Abbreviation Reset
Manual Reset Standby
Standby
Sleep
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Module
TGRA_1
TGRB_1
TCR_2
TMDR_2
TIOR_2
TIER_2
TSR_2
TCNT_2
TGRA_2
TGRB_2
IPRA
Initialized
Held
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Held
Initialized
MTU
(channel 2)
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Held
Held
Initialized
Held
Initialized
Held
Initialized
Held
Initialized
Held
Initialized
Held
Initialized
Held
Initialized
Held
Initialized
Held
Initialized
⎯
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Held
INTC
IPRD
Held
⎯
IPRE
Held
⎯
IPRF
Held
⎯
IPRG
Held
⎯
IPRH
Held
⎯
ICR1
Held
⎯
ISR
Held
⎯
IPRI
Held
⎯
ICR2
Held
⎯
PADRL
PAIORL
PACRL3
PACRL1
PACRL2
PBDR
Held
⎯
Port A
Port B
Held
Held
⎯
Held
Held
⎯
Held
Held
⎯
Held
Held
⎯
Held
Held
⎯
PBIOR
PBCR1
PBCR2
PEDRL
PFDR
Held
Held
⎯
Held
Held
⎯
Held
Held
⎯
Held
Held
⎯
Port E
Port F
Held
Held
⎯
Rev.2.00 Sep. 27, 2007 Page 417 of 448
REJ09B0394-0200
18. List of Registers
Register
Power-On
Software
Module
Abbreviation Reset
Manual Reset Standby
Standby
Sleep
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Module
PEIORL
PEIORH
PECRL1
PECRL2
PECRH
Initialized
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Held
Initialized
Initialized
Held
Held
⎯
Port E
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Held
Held
⎯
Held
⎯
Held
⎯
Held
⎯
PEDRH
Held
⎯
ICSR1
Held
Held
MTU
OCSR
Held
Held
PGDR
Held
⎯
Port G
CMT
CMSTR
CMCSR_0
CMCNT_0
CMCOR_0
CMCSR_1
CMCNT_1
CMCOR_1
ADDR8
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Held
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
⎯
A/D
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADCSR_0
ADCSR_1
ADCR_0
ADCR_1
TCSR
WDT
TCNT
Held
⎯
RSTCSR
Initialized
⎯
Rev.2.00 Sep. 27, 2007 Page 418 of 448
REJ09B0394-0200
18. List of Registers
Register
Power-On
Software
Module
Abbreviation Reset
Manual Reset Standby
Standby
Sleep
Held
Held
Held
Held
Held
Held
Module
SBYCR
SYSCR
MSTCR1
MSTCR2
BCR1
Initialized
Initialized
Held
Held
Held
Held
Held
Held
Held
⎯
⎯
⎯
⎯
⎯
⎯
Power-down
state
Initialized
Initialized
Initialized
Initialized
Initialized
Held
Held
Held
BSC
A/D
ADTSR
Held
Rev.2.00 Sep. 27, 2007 Page 419 of 448
REJ09B0394-0200
18. List of Registers
Rev.2.00 Sep. 27, 2007 Page 420 of 448
REJ09B0394-0200
19. Electrical Characteristics
Section 19 Electrical Characteristics
19.1
Absolute Maximum Ratings
Table 19.1 shows the absolute maximum ratings.
Table 19.1 Absolute Maximum Ratings
Item
Symbol
VCC
Rating
Unit
V
Power supply voltage
–0.3 to +7.0
–0.3 to VCC +0.3
–0.3 to VCC +0.3
Input voltage
EXTAL pin
Vin
V
All pins other than analog
input and EXTAL pins
Vin
V
Analog supply voltage
Analog input voltage
AVCC
VAN
–0.3 to +7.0
V
–0.3 to AVCC +0.3
–20 to +75
V
Operating temperature Standard product*
Topr
°C
Wide temperature-range
–40 to +85
product*
Storage temperature
Tstg
–55 to +125
°C
[Operating precautions]
Operating the LSI in excess of the absolute maximum ratings may result in permanent
damage.
Note:
*
See page 2 for correspondence of the standard product, wide temperature-range
product, and product model name.
Rev.2.00 Sep. 27, 2007 Page 421 of 448
REJ09B0394-0200
19. Electrical Characteristics
19.2
DC Characteristics
Table 19.2 DC Characteristics
Conditions: VCC = 4.0 to 5.5 V, AVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C to
+75°C (Standard product)*, Ta = –40°C to +85°C (Wide temperature-range product)*
Measurement
Item
Symbol Min
VIH CC –0.7
Typ
Max
Unit
Conditions
Input high-level RES, MRES, NMI,
V
⎯
VCC +0.3
V
voltage (except FWP, MD3 to MD0
Schmitt trigger
input voltage)
EXTAL
VCC –0.7
2.2
⎯
⎯
⎯
⎯
VCC +0.3
V
V
V
V
A/D port
AVCC +0.3
Other input pins
2.2
VCC +0.3
Input low-level RES, MRES, NMI,
voltage (except FWP, MD3 to MD0,
Schmitt trigger EXTAL
VIL
–0.3
0.5
input voltage)
Other input pins
–0.3
⎯
⎯
⎯
⎯
0.8
V
V
V
V
Schmitt trigger IRQ3 to IRQ0,
input voltage
VT+
VT–
VCC –0.5
–0.3
VCC +0.3
1.0
POE3 to POE0, TCLKA
to TCLKD, TIOC0A to
TIOC0D, TIOC1A,
TIOC1B, TIOC2A,
TIOC2B, TIOC3A to
TIOC3D, TIOC4A to
TIOC4D
VT+–VT– 0.4
⎯
Input leak
current
RES, MRES, NMI,
FWP, MD3 to MD0
| Iin |
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
1.0
1.0
1.0
1.0
μA
μA
μA
μA
Vin = 0.5 to VCC
–0.5 V
Ports F and G
Vin = 0.5 to AVCC
–0.5 V
Other input pins
Vin = 0.5 to VCC
–0.5 V
Vin = 0.5 to VCC
–0.5 V
Three-state leak Port A, B, E
current (while
| Itsi |
OFF)
VOH
VOL
Rpull
VCC –0.5
VCC –0.5
⎯
⎯
⎯
⎯
⎯
50
⎯
V
IOH = –200 μA
IOH = –1 mA
IOL = 1.6 mA
IOL = 15 mA
Output high-
level voltage
All output pins
⎯
V
Output low-
level voltage
All output pins
0.4
1.5
80
V
PE9, PE11 to PE15
⎯
V
Pull-up resistor PA15 to PA12,
PE21 to PE16
20
kΩ
Rev.2.00 Sep. 27, 2007 Page 422 of 448
REJ09B0394-0200
19. Electrical Characteristics
Measurement
Item
Symbol Min
Typ
⎯
Max
80
Unit
pF
Conditions
Input
capacitance
Cin
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Vin = 0 V
φ = 1 MHz
Ta = 25°C
RES
⎯
50
pF
NMI
⎯
20
pF
All other input pins
Current
consumption
Normal
operation
Clock 1:1
Clock 1:1/2
Clock 1:1
Clock 1:1/2
ICC
110
100
70
60
1
130
120
90
mA
mA
mA
mA
μA
φ = 40 MHz
φ = 40 MHz
φ = 40 MHz
φ = 40 MHz
Ta ≤ 50°C
Sleep
80
Standby
10
⎯
50
μA
50°C < Ta
Analog supply
current
During A/D conversion, AICC
A/D converter idle state
3
5
mA
During standby
⎯
⎯
⎯
5
μA
RAM standby voltage
VRAM
2.0
⎯
V
VCC
[Operating precautions]
1. When the A/D converter is not used, the AVCC, and AVSS pins should not be open.
2. The current consumption is measured when VIHmin = VCC –0.5 V, VIL = 0.5 V, with all
output pins unloaded.
Note:
*
See page 2 for correspondence of the standard product, wide temperature-range
product, and product model name.
Rev.2.00 Sep. 27, 2007 Page 423 of 448
REJ09B0394-0200
19. Electrical Characteristics
Table 19.3 Permitted Output Current Values
Conditions: VCC = 4.0 V to 0.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C
to +75°C (Standard product)*1, Ta = –40°C to +85°C (Wide temperature-range
product)*1
Item
Symbol
Min
Typ
Max
Unit
Output low-level permissible current
(per pin)
IOL
⎯
⎯
2.0*2
mA
Output low-level permissible current
(total)
Σ IOL
–IOH
⎯
⎯
⎯
⎯
⎯
⎯
110
2.0
25
mA
mA
mA
Output high-level permissible current
(per pin)
Output high-level permissible current
(total)
Σ –IOH
[Operating precautions]
To assure LSI reliability, do not exceed the output values listed in this table.
Note: 1. See page 2 for correspondence of the standard product, wide temperature-range
product, and product model name.
2. IOL= 15 mA (max) about the pins PE9, PE11 to PE15. However, three pins at most are
permitted to have simultaneously IOL > 2.0 mA among these pins.
Rev.2.00 Sep. 27, 2007 Page 424 of 448
REJ09B0394-0200
19. Electrical Characteristics
19.3
AC Characteristics
19.3.1 Test Conditions for the AC Characteristics
Input reference levels
high level: VIH minimum value, low level: VIL maximum value
Output reference levels high level: 2.0 V, low level: 0.8 V
IOL
DUT output
LSI output pin
VREF
V
CL
30 pF
IOH
CL is a total value that includes the capacitance of measurement equipment, and is set as follows:
30 pF: IRQOUT
30 pF: Port output pins and peripheral module output pins other than the above
It is assumed that IOL = 1.6 mA, IOH = 200 µA in the test conditions.
Figure 19.1 Output Load Circuit
Rev.2.00 Sep. 27, 2007 Page 425 of 448
REJ09B0394-0200
19. Electrical Characteristics
19.3.2 Clock Timing
Table 19.4 shows the clock timing.
Table 19.4 Clock Timing
Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C
to +75°C (Standard product)*, Ta = –40°C to +85°C (Wide temperature-range
product)*
Item
Symbol Min
Max
40
250
⎯
Unit
MHz
ns
Figures
Operating frequency
fop
10
25
4
Figure 19.2
Clock cycle time
tcyc
Clock low-level pulse width
Clock high-level pulse width
Clock rise time
tCL
ns
tCH
4
⎯
ns
tCR
⎯
⎯
4
5
ns
Clock fall time
tCF
5
ns
EXTAL clock input frequency
EXTAL clock input cycle time
EXTAL clock input low-level pulse width
EXTAL clock input high-level pulse width
EXTAL clock input rise time
EXTAL clock input fall time
Reset oscillation settling time
Standby return oscillation settling time
fEX
10.0
250
⎯
MHz
ns
Figure 19.3
tEXcyc
tEXL
tEXH
tEXR
tEXF
tOSC1
tOSC2
100
45
45
⎯
⎯
10
10
25
ns
⎯
ns
5
ns
5
ns
⎯
ms
ms
ns
Figure 19.4
⎯
Clock cycle time for on-chip peripheral modules tpcyc
100
⎯
Note:
*
See page 2 for correspondence of the standard product, wide temperature-range
product, and product model name.
Rev.2.00 Sep. 27, 2007 Page 426 of 448
REJ09B0394-0200
19. Electrical Characteristics
tcyc
tCH
tCL
VOH
1/2VCC
VOH
VOH
1/2VCC
CK
VOL
tCF
VOL
tCR
Figure 19.2 System Clock Timing
tEXcyc
tEXH
tEXL
VIH
1/2VCC
V
IH
VIH
1/2VCC
EXTAL
VIL
VIL
tEXR
tEXF
Figure 19.3 EXTAL Clock Input Timing
CK
VCC min
VCC
tOSC1
RES
Figure 19.4 Oscillation Settling Time
Rev.2.00 Sep. 27, 2007 Page 427 of 448
REJ09B0394-0200
19. Electrical Characteristics
19.3.3 Control Signal Timing
Table 19.5 shows control signal timing.
Table 19.5 Control Signal Timing
Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C
to +75°C (Standard product)*1, Ta = –40°C to +85°C (Wide temperature-range
product)*1
Item
Symbol
RESr, tRESf
Min
⎯
Max
200
⎯
Unit
ns
tcyc
ns
tcyc
ns
tcyc
ns
ns
ns
ns
ns
ns
ns
Figures
RES rise time, fall time
RES pulse width
RES setup time
t
Figure 19.5
Figure 19.6
tRESW
25
19
20
19
20
⎯
tRESS
⎯
MRES pulse width
MRES setup time
MD3 to MD0, FWP setup time
NMI rise time, fall time
NMI setup time
IRQ3 to IRQ0 setup time*2 (edge detection) tIRQES
IRQ3 to IRQ0 setup time*2 (level detection) tIRQLS
tMRESW
tMRESS
tMDS
⎯
⎯
⎯
tNMIr, tNMIIf
tNMIS
200
⎯
19
19
19
19
19
⎯
Figure 19.7
Figure 19.8
⎯
⎯
NMI hold time
tNMIH
⎯
IRQ3 to IRQ0 hold time
IRQOUT output delay time
[Operating precautions]
tIRQEH
tIRQOD
⎯
100
Notes: 1. See page 2 for correspondence of the standard product, wide temperature-range
product, and product model name.
2. The RES, MRES, NMI and IRQ3 to IRQ0 signals are asynchronous inputs, but when
the setup times shown here are observed, the signals are considered to have been
changed at clock rise (RES, MRES) or fall (NMI and IRQ3 to IRQ0). If the setup times
are not observed, detection of these signals may be delayed until the next clock rise or
fall.
Rev.2.00 Sep. 27, 2007 Page 428 of 448
REJ09B0394-0200
19. Electrical Characteristics
VOH
CK
tRESS
tRESS
tRESW
VIH
VIH
VIL
RES
VIL
tMDS
VIH
VIL
MD3 to
MD0
FWP
Figure 19.5 Reset Input Timing
CK
tMRESS
tMRESS
VIH
MRES
VIL
VIL
tMRESW
Figure 19.6 Reset Input Timing
Rev.2.00 Sep. 27, 2007 Page 429 of 448
REJ09B0394-0200
19. Electrical Characteristics
CK
VOL
VOL
tNMIH
tNMIS
VIH
VIH
VIL
NMI
VIL
tIRQES
tIRQEH
IRQ edge
VIH
VIL
tIRQLS
IRQ level
VIL
Figure 19.7 Interrupt Signal Input Timing
VOH
CK
tIRQOD
tIRQOD
VOH
IRQOUT
VOL
Figure 19.8 Interrupt Signal Output Timing
Rev.2.00 Sep. 27, 2007 Page 430 of 448
REJ09B0394-0200
19. Electrical Characteristics
19.3.4
Multi-Function Timer Pulse Unit (MPU) Timing
Table 19.6 shows Multi-Function timer pulse unit timing.
Table 19.6 Multi-Function Timer Pulse Unit Timing
Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C
to +75°C (Standard product*), Ta = –40°C to +85°C (Wide temperature-range
product*)
Item
Symbol
tTOCD
Min
⎯
Max
100
⎯
Unit
ns
Figures
Output compare output delay time
Input capture input setup time
Timer input setup time
Figure 19.9
tTICS
19
ns
tTCKS
20
⎯
ns
Figure 19.10
Timer clock pulse width (single edge
specified)
tTCKWH/L
1.5
⎯
tpcyc
Timer clock pulse width (both edges
specified)
tTCKWH/L
tTCKWH/L
2.5
2.5
⎯
⎯
tpcyc
tpcyc
Timer clock pulse width (phase count
mode)
Note:
*
See page 2 for correspondence of the standard product, wide temperature-range
product, and product model name.
CK
tTOCD
Output compare
output
tTICS
Input capture
input
Figure 19.9 MTU Input/Output Timing
Rev.2.00 Sep. 27, 2007 Page 431 of 448
REJ09B0394-0200
19. Electrical Characteristics
CK
tTCKS
tTCKS
TCLKA to
TCLKD
tTCKWH
tTCKWL
Figure 19.10 MTU Clock Input Timing
19.3.5
I/O Port Timing
Table 19.7 shows I/O port timing.
Table 19.7 I/O Port Timing
Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C
to +75°C (Standard product*), Ta = –40°C to +85°C (Wide temperature-range
product*)
Item
Symbol
tPWD
Min
⎯
Max
100
⎯
Unit
ns
Figures
Port output data delay time
Port input hold time
Port input setup time
[Operating precautions]
Figure 19.11
tPRH
19
ns
tPRS
19
⎯
ns
The port input signals are asynchronous. They are, however, considered to have been
changed at CK clock fall with two-state intervals shown in figure 19.11. If the setup times
shown here are not observed, detection may be delayed until the clock fall two states after
that timing.
Note:
*
See page 2 for correspondence of the standard product, wide temperature-range
product, and product model name.
Rev.2.00 Sep. 27, 2007 Page 432 of 448
REJ09B0394-0200
19. Electrical Characteristics
CK
tPRH
tPRS
Port
(read)
tPWD
Port
(write)
Figure 19.11 I/O Port Input/Output Timing
Watchdog Timer (WDT) Timing
19.3.6
Table 19.8 shows watchdog timer timing.
Table 19.8 Watchdog Timer Timing
Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C
to +75°C (Standard product)*, Ta = –40°C to +85°C (Wide temperature-range
product)*
Item
Symbol
Min
Max
Unit
Figures
WDTOVF delay time
tWOVD
⎯
100
ns
Figure 19.12
Note:
CK
*
See page 2 for correspondence of the standard product, wide temperature-range
product, and product model name.
VOH
VOH
tWOVD
tWOVD
WDTOVF
Figure 19.12 WDT Timing
Rev.2.00 Sep. 27, 2007 Page 433 of 448
REJ09B0394-0200
19. Electrical Characteristics
19.3.7
Serial Communication Interface (SCI) Timing
Table 19.9 shows serial communication interface timing.
Table 19.9 Serial Communication Interface Timing
Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C
to +75°C (Standard product)*, Ta = –40°C to +85°C (Wide temperature-range
product)*
Item
Symbol
Min
4
Max
⎯
Unit
tpcyc
tpcyc
tscyc
tpcyc
tpcyc
ns
Figures
Input clock cycle
tscyc
Figure 19.13
Input clock cycle (clock sync) tscyc
6
⎯
Input clock pulse width
Input clock rise time
tsckw
tsckr
tsckf
tTxD
tRxS
tRxH
0.4
⎯
0.6
1.5
1.5
100
⎯
Input clock fall time
⎯
Transmit data delay time
Received data setup time
Received data hold time
[Operating precautions]
⎯
Figure 19.14
100
100
ns
⎯
ns
The inputs and outputs are asynchronous in asynchronous mode, but as shown in figure
19.14, the received data is considered to have been changed at CK clock rise (two-clock
intervals). The transmit signals change with a reference of CK clock rise (two-clock
intervals).
Note:
*
See page 2 for correspondence of the standard product, wide temperature-range
product, and product model name.
tsckr
tsckf
tsckw
VIH
VIH
VIH
VIH
SCK2, SCK3
VIL
VIL
VIL
tscyc
Figure 19.13 Input Clock Timing
Rev.2.00 Sep. 27, 2007 Page 434 of 448
REJ09B0394-0200
19. Electrical Characteristics
SCI input/output timing (clock synchronous mode)
tscyc
SCK2, SCK3
(input/output)
tTxD
TxD2, TxD3
(transmit data)
tRxS tRxH
RxD2, RxD3
(receive data)
SCI input/output timing (asynchronous mode)
T1
Tn
VOH
VOH
CK
tTxD
TxD2, TxD3
(transmit data)
tRxS tRxH
RxD2, RxD3
(receive data)
Figure 19.14 SCI Input/Output Timing
Rev.2.00 Sep. 27, 2007 Page 435 of 448
REJ09B0394-0200
19. Electrical Characteristics
19.3.8
Output Enable (POE) Timing
Table 19.10 Output Enable Timing
Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C
to +75°C (Standard product*), Ta = –40°C to +85°C (Wide temperature-range
product*)
Item
Symbol
tPOES
Min
100
1.5
Max
⎯
Unit
ns
Figures
POE input setup time
POE input pulse width
Figure 19.15
tPOEW
⎯
tcyc
Note:
*
See page 2 for correspondence of the standard product, wide temperature-range
product, and product model name.
CK
tPOES
POE input
tPOEW
Figure 19.15 POE Input/Output Timing
19.3.9
A/D Converter Timing
Table 19.11 shows A/D converter timing.
Table 19.11 A/D Converter Timing
Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C
to +75°C (Standard product*), Ta = –40°C to +85°C (Wide temperature-range
product*)
Item
Symbol
Min
Typ
Max
Unit
Figure
External trigger input start
delay time
tTRGS
50
⎯
⎯
ns
Figure 19.16
Note:
*
See page 2 for correspondence of the standard product, wide temperature-range
product, and product model name.
Rev.2.00 Sep. 27, 2007 Page 436 of 448
REJ09B0394-0200
19. Electrical Characteristics
3 to 5 states
VOH
CK
ADTRG input
tTRGS
ADCR
(ADST = 1 set)
Figure 19.16 External Trigger Input Timing
Rev.2.00 Sep. 27, 2007 Page 437 of 448
REJ09B0394-0200
19. Electrical Characteristics
19.4
A/D Converter Characteristics
Table 19.12 shows A/D converter characteristics.
Table 19.12 A/D Converter Characteristics
Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C
to +75°C (Standard product)*1, Ta = –40°C to +85°C (Wide temperature-range
product)*
Item
Min
10
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Typ
10
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Max
Unit
bit
Resolution
10/5.4
6.7*2/5.4*3
20
A/D conversion time
Analog input capacitance
Permitted analog signal source impedance
Non-linear error
μs
pF
3/1*3
kΩ
±3.0*2/±5.0*3 LSB
±3.0*2/±5.0*3 LSB
±3.0*2/±5.0*3 LSB
Offset error
Full-scale error
Quantization error
Absolute error
±0.5
LSB
±4.0*2/±6.0*3 LSB
Notes: 1. See page 2 for correspondence of the standard product, wide temperature-range
product, and product model name.
2. Value when (CKS1, 0) = (1, 1) and tpcyc = 50 ns
3. Value when (CKS1, 0) = (1, 1) and tpcyc = 40 ns
Rev.2.00 Sep. 27, 2007 Page 438 of 448
REJ09B0394-0200
Appendix A Pin States
Appendix A Pin States
The initial values differ in each MCU operating mode. For details, refer to section 13, Pin
Function Controller (PFC).
Table A.1 Pin States
Pin Function
Pin State
Power-Down State
Reset State
Software
Standby
Type
Pin Name
Power-On Manual
Sleep
Clock
XTAL
O
O
I
L
O
I
EXTAL
PLLCAP
RES
I
I
I
I
I
I
System Control
I
I
I
I
MRES
Z
O*3
I
Z*2
O
I
I
WDTOVF
MD0 to MD3
O
I
O
I
Operation Mode
Control
I
FWP
I
I
I
I
Interrupt
MTU
NMI
I
I
I
I
IRQ0 to IRQ3
IRQOUT
Z
Z
Z
Z
I
Z*4
K*1
Z
I
O
I
O
I
TCLKA to TCLKD
TIOC0A to TIOC0D
TIOC1A, TIOC1B
TIOC2A, TIOC2B
TIOC3A, TIOC3C
TIOC3B, TIOC3D
TIOC4A to TIOC4D
POE0 to POE3
SCK2, SCK3
RXD2, RXD3
TXD2, TXD3
I/O
K*1
I/O
Z
I/O
Z*2
I/O
Port control
SCI
Z
Z
Z
Z
I
Z
I
I/O
I
Z
I/O
I
Z
O*1
O
O
Rev.2.00 Sep. 27, 2007 Page 439 of 448
REJ09B0394-0200
Appendix A Pin States
Pin Function
Pin State
Power-Down State
Reset State
Software
Standby
Type
Pin Name
Power-On Manual
Sleep
A/D converter
AN8 to AN15
ADTRG
Z
Z
Z
I
Z
I
I
Z
K*1
I
I/O port
PA0 to PA15
PB2 to PB5
I/O
I/O
PE0 to PE8, PE10, PE16
to PE21
PE9,
Z
I/O
Z*2
I/O
PE11 to PE15
PF8 to PF15
PG0 to PG3
Z
Z
I
I
Z
Z
I
I
Legend:
I: Input
O: Output
H: High-level output
L: Low-level output
Z: High impedance
K: Input pins become high-impedance, and output pins retain their state.
Notes: 1. When the HIZ bit in SBYCR is set to 1, the output pins enter their high-impedance state.
2. Those pins multiplexed with large-current pins (PE9, PE11 to PE15) unconditionally
enter their high-impedance state.
3. This pin operates as an input pin during a power-on reset. This pin should be pulled up
to avoid malfunction.
4. This pin operates as an input pin when the IRQEL bit in SBYCR is cleared to 0.
Rev.2.00 Sep. 27, 2007 Page 440 of 448
REJ09B0394-0200
Appendix B Product Lineup
Appendix B Product Lineup
Package
Product Type
SH7101 Mask ROM version
Part No.
(Package Code)
Standard product HD6437101
QFP-80 (FP-80Q)
Rev.2.00 Sep. 27, 2007 Page 441 of 448
REJ09B0394-0200
Appendix B Product Lineup
Rev.2.00 Sep. 27, 2007 Page 442 of 448
REJ09B0394-0200
Appendix C Package Dimensions
Appendix C Package Dimensions
The package dimension that is shown in the Renesas Semiconductor Package Data Book has
priority.
JEITA Package Code
P-QFP80-14x14-0.65
RENESAS Code
PRQP0080JD-A
Previous Code
MASS[Typ.]
1.2g
FP-80Q/FP-80QV
HD
*1
D
NOTE)
60
41
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
61
40
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
Terminal cross section
D
E
14
14
21
80
A2
HD
HE
A
A1
bp
b1
c
2.70
17.0 17.2 17.4
17.0 17.2 17.4
3.05
0.00 0.10 0.25
0.24 0.32 0.40
0.30
1
20
ZD
F
θ
L
L1
0.12 0.17 0.22
0.15
c1
θ
e
Detail F
*3
0°
8°
e
bp
y
x
M
0.65
x
y
0.12
0.10
ZD
ZE
L
0.83
0.83
0.6 0.8 1.0
1.6
L1
Figure C.1 FP-80Q
Rev.2.00 Sep. 27, 2007 Page 443 of 448
REJ09B0394-0200
Appendix C Package Dimensions
Rev.2.00 Sep. 27, 2007 Page 444 of 448
REJ09B0394-0200
Index
Index
A/D conversion time............................... 335
A/D converter ......................................... 325
Absolute maximum ratings..................... 421
Address error exception processing.......... 60
Address map ............................................. 45
Addressing modes..................................... 20
I/O Ports..................................................371
Illegal slot exception processing ...............63
Input capture ...........................................141
Interrupt controller....................................67
Interrupt exception processing ..................61
Interrupt response time..............................84
Interval Timer Mode...............................271
IRQ interrupts ...........................................75
Buffer operation...................................... 145
Bus state controller ................................... 87
Byte........................................................... 15
Longword..................................................15
Cascaded operation................................. 149
Clock mode............................................... 43
Clock pulse generator ............................... 47
Clocked synchronous communication .... 313
Compare match....................................... 139
Compare match timer.............................. 343
Continuous scan mode............................ 333
Control registers........................................ 13
Crystal Resonator...................................... 47
Manual reset..............................................58
Mask ROM..............................................383
Module standby mode.............................398
Multi-function timer pulse unit .................91
Multiply-and-Accumulate Registers (MAC)
..................................................................14
Multiprocessor communication function.307
NMI interrupt............................................75
Data Formats............................................. 15
Delayed branch instructions...................... 17
On-chip peripheral module interrupts .......77
Operating modes .......................................43
Overrun error...........................................303
Exception processing................................ 53
Exception processing state........................ 42
Exception processing vector table ............ 55
External clock........................................... 49
Periodic counter ......................................137
Phase counting mode ..............................156
Pin function controller ............................353
Pin functions in each operating mode .....353
Power-down modes.................................387
Power-down state......................................42
Power-on reset...........................................57
Procedure Register (PR)............................14
Processing states .......................................41
Program Counter (PC) ..............................14
Program execution state............................42
PWM mode .............................................150
Free-running counters............................. 138
General illegal instruction exception
processing ................................................. 63
General registers ....................................... 13
Global Base Register (GBR)..................... 14
High-impedance state ............................. 252
Rev.2.00 Sep. 27, 2007 Page 445 of 448
REJ09B0394-0200
Index
RAM....................................................... 385
Reading from TCNT, TCSR, and RSTCSR
................................................................ 274
Registers
SDCR.......................... 287, 401, 408, 415
SMR............................ 281, 401, 408, 415
SSR ............................. 285, 401, 408, 415
SYSCR........................ 392, 407, 414, 419
TCBR.......................... 135, 402, 409, 416
TCDR.......................... 135, 402, 409, 415
TCNT......................... 126, 265, 402, 406,
................................ 408, 414, 415, 418
TCNTS........................ 135, 402, 409, 416
TCR............................... 98, 401, 408, 415
TCSR .......................... 266, 406, 414, 418
TDDR.......................... 135, 402, 409, 415
TDR ............................ 280, 401, 408, 415
TGCR.......................... 133, 402, 408, 415
TGR ............................ 127, 402, 409, 416
TIER............................ 122, 402, 408, 415
TIOR ........................... 104, 401, 408, 415
TMDR......................... 102, 401, 408, 415
TOCR.......................... 131, 402, 408, 415
TOER.......................... 130, 402, 408, 415
TSR ..................... 124, 280, 402, 409, 416
TSTR........................... 127, 402, 409, 416
TSYR .......................... 128, 402, 409, 416
Reset state .................................................42
Reset-synchronized PWM mode.............163
RISC..........................................................17
ADCR......................... 330, 406, 413, 418
ADCSR....................... 329, 406, 413, 418
ADDR................................................. 328
ADTSR ....................... 332, 407, 414, 419
BCR1 ............................ 89, 407, 414, 419
BRR ............................ 287, 401, 408, 415
CMCNT...................... 346, 405, 413, 418
CMCOR...................... 346, 405, 413, 418
CMCSR ...................... 345, 405, 413, 418
CMSTR....................... 344, 405, 413, 418
ICR1 ............................. 69, 404, 411, 417
ICR2 ............................. 70, 404, 411, 417
ICSR1 ......................... 254, 405, 412, 418
IPR................................ 73, 404, 411, 417
ISR................................ 72, 404, 411, 417
MSTCR....................... 393, 407, 414, 419
OCSR.......................... 257, 405, 412, 418
PACRL ....................... 361, 404, 411, 417
PADRL ....................... 372, 404, 411, 417
PAIORL...................... 360, 404, 411, 417
PBCR.......................... 365, 405, 412, 417
PBDR.......................... 374, 404, 412, 417
PBIOR ........................ 364, 405, 412, 417
PECRH ....................... 366, 405, 412, 418
PECRL........................ 366, 405, 412, 418
PEDRH ....................... 377, 405, 412, 418
PEDRL........................ 377, 405, 412, 417
PEIORH...................... 366, 405, 412, 418
PEIORL ...................... 366, 405, 412, 418
PFDR .......................... 379, 405, 412, 417
PGDR.......................... 381, 405, 412, 418
RDR............................ 280, 401, 408, 415
RSR..................................................... 280
RSTCSR ............................. 268, 406, 418
SBYCR ....................... 390, 406, 414, 419
SCR............................. 283, 401, 408, 415
Serial communication interface...............277
Single mode ............................................333
Single-cycle scan ....................................335
Sleep mode..............................................395
Software standby mode...........................396
Status Register (SR)..................................13
Synchronous operation............................142
System registers ........................................14
The functions of multiplexed pins...........353
Trap instruction exception processing.......62
Rev.2.00 Sep. 27, 2007 Page 446 of 448
REJ09B0394-0200
Index
Vector Base Register (VBR)..................... 14
Vector numbers......................................... 77
Vector table............................................... 77
Watchdog timer ...................................... 263
Watchdog Timer Mode ...........................269
Word .........................................................15
Writing to RSTCSR ................................274
Writing to TCNT and TCSR...................273
Rev.2.00 Sep. 27, 2007 Page 447 of 448
REJ09B0394-0200
Index
Rev.2.00 Sep. 27, 2007 Page 448 of 448
REJ09B0394-0200
Renesas 32-Bit RISC Microcomputer
Hardware Manual
SH7101
Publication Date: 1st Edition, February, 2003
Rev.2.00, September 27, 2007
Published by:
Sales Strategic Planning Div.
Renesas Technology Corp.
Customer Support Department
Global Strategic Communication Div.
Renesas Solutions Corp.
Edited by:
© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
RENESAS SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
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SH7101
Hardware Manual
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相关型号：
SH7136_09
SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer
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