R7FA4M3AF3CFB [RENESAS]
Armv8-M architecture with the main extension;型号: | R7FA4M3AF3CFB |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | Armv8-M architecture with the main extension |
文件: | 总92页 (文件大小:1112K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Datasheet
R01DS0368EJ0120
Rev.1.20
RA4M3 Group
Renesas Microcontrollers
Dec 2, 2020
Leading-performance 100 MHz Arm Cortex-M33 core, up to 1 MB code flash memory with background and SWAP operation,
8 KB Data flash memory, and 128 KB SRAM with Parity/ECC. High-integration with USB 2.0 Full-Speed, SDHI, Quad SPI,
and advanced analog. Integrated Secure Crypto Engine with cryptography accelerators, key management support, tamper
detection and power analysis resistance in concert with Arm TrustZone for integrated secure element functionality.
Features
®
®
● Independent Watchdog Timer (IWDT)
■
Arm Cortex -M33 Core
● Armv8-M architecture with the main extension
● Maximum operating frequency: 100 MHz
● Arm Memory Protection Unit (Arm MPU)
– Protected Memory System Architecture (PMSAv8)
– Secure MPU (MPU_S): 8 regions
■ Human Machine Interface (HMI)
● Capacitive Touch Sensing Unit (CTSU)
■ Multiple Clock Sources
– Non-secure MPU (MPU_NS): 8 regions
● SysTick timer
● Main clock oscillator (MOSC) (8 to 24 MHz)
● Sub-clock oscillator (SOSC) (32.768 kHz)
● High-speed on-chip oscillator (HOCO) (16/18/20 MHz)
● Middle-speed on-chip oscillator (MOCO) (8 MHz)
● Low-speed on-chip oscillator (LOCO) (32.768 kHz)
● IWDT-dedicated on-chip oscillator (15 kHz)
● Clock trim function for HOCO/MOCO/LOCO
● PLL/PLL2
– Embeds two Systick timers: Secure and Non-secure instance
– Driven by LOCO or system clock
™
● CoreSight ETM-M33
■ Memory
● Up to 1-MB code flash memory
● 8-KB data flash memory (100,000 program/erase (P/E) cycles)
● 128-KB SRAM
● Clock out support
■ General-Purpose I/O Ports
● 5-V tolerance, open drain, input pull-up, switchable driving ability
■ Connectivity
● Serial Communications Interface (SCI) × 6
– Asynchronous interfaces
– 8-bit clock synchronous interface
– Smart card interface
■ Operating Voltage
● VCC: 2.7 to 3.6 V
■ Operating Temperature and Packages
● Ta = -40℃ to +105℃
– Simple IIC
– Simple SPI
– Manchester coding (SCI3, SCI4)
– 144-pin LQFP (20 mm × 20 mm, 0.5 mm pitch)
– 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)
– 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)
2
● I C bus interface (IIC) × 2
● Serial Peripheral Interface (SPI)
● Quad Serial Peripheral Interface (QSPI)
● USB 2.0 Full-Speed Module (USBFS)
● Control Area Network module (CAN) × 2
● SD/MMC Host Interface (SDHI)
● Serial Sound Interface Enhanced (SSIE)
■ Analog
● 12-bit A/D Converter (ADC12) × 2
● 12-bit D/A Converter (DAC12) × 2
● Temperature Sensor (TSN)
■ Timers
● General PWM Timer 32-bit (GPT32) × 4
● General PWM Timer 16-bit (GPT16) × 4
● Low Power Asynchronous General Purpose Timer (AGT) × 6
■ Security and Encryption
● Secure Crypto Engine 9
– Symmetric algorithms: AES
– Asymmetric algorithms: RSA, ECC, and DSA
– Hash-value generation: SHA224, SHA256, GHASH
– 128-bit unique ID
®
®
● Arm TrustZone
– Up to three regions for the code flash
– Up to two regions for the data flash
– Up to three regions for the SRAM
– Individual secure or non-secure security attribution for each
peripheral
● Device lifecyle management
● Pin function
– Up to three tamper pins
– Secure pin multiplexing
■ System and Power Management
● Low power modes
● Battery backup function (VBATT)
● Realtime Clock (RTC) with calendar and VBATT support
● Event Link Controller (ELC)
● Data Transfer Controller (DTC)
● DMA Controller (DMAC) × 8
● Power-on reset
● Low Voltage Detection (LVD) with voltage settings
● Watchdog Timer (WDT)
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 1 of 92
RA4M3 Datasheet
1. Overview
1.
Overview
®
The MCU integrates multiple series of software- and pin-compatible Arm -based 32-bit cores that share a common set of
Renesas peripherals to facilitate design scalability and efficient platform-based product development.
®
The MCU in this series incorporates a high-performance Arm Cortex -M33 core running up to 100 MHz with the following
features:
● Up to 1 MB code flash memory
● 128 KB SRAM
● Quad Serial Peripheral Interface (QSPI)
● USBFS, SD/MMC Host Interface
● Capacitive Touch Sensing Unit (CTSU)
● Analog peripherals
● Security and safety features
1.1
Function Outline
Table 1.1
Feature
Arm core
Functional description
Arm Cortex-M33 core
●
●
Maximum operating frequency: up to 100 MHz
Arm Cortex-M33 core:
–
–
Armv8-M architecture with security extension
Revision: r0p4-00rel0
●
Arm Memory Protection Unit (Arm MPU)
–
–
–
Protected Memory System Architecture (PMSAv8)
Secure MPU (MPU_S): 8 regions
Non-secure MPU (MPU_NS): 8 regions
●
●
SysTick timer
–
–
Embeds two Systick timers: Secure and Non-secure instance
Driven by SysTick timer clock (SYSTICCLK) or system clock (ICLK)
™
CoreSight ETM-M33
Table 1.2
Memory
Feature
Functional description
Code flash memory
Data flash memory
Option-setting memory
SRAM
Maximum 1 MB of code flash memory.
8 KB of data flash memory.
The option-setting memory determines the state of the MCU after a reset.
On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC).
Table 1.3
System (1 of 2)
Functional description
Operating modes
Two operating modes:
●
●
Single-chip mode
SCI/USB boot mode
Resets
The MCU provides 14 resets.
Low Voltage Detection (LVD)
The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin. The
detection level can be selected by register settings. The LVD module consists of three separate
voltage level detectors (LVD0, LVD1, LVD2). LVD0, LVD1, and LVD2 measure the voltage level
input to the VCC pin. LVD registers allow your application to configure detection of VCC changes
at various voltage thresholds.
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RA4M3 Datasheet
1. Overview
Table 1.3
System (2 of 2)
Functional description
Clocks
●
●
●
●
●
●
●
●
Main clock oscillator (MOSC)
Sub-clock oscillator (SOSC)
High-speed on-chip oscillator (HOCO)
Middle-speed on-chip oscillator (MOCO)
Low-speed on-chip oscillator (LOCO)
IWDT-dedicated on-chip oscillator
PLL/PLL2
Clock out support
Clock Frequency Accuracy
Measurement Circuit (CAC)
The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be
measured (measurement target clock) within the time generated by the clock selected as the
measurement reference (measurement reference clock), and determines the accuracy
depending on whether the number of pulses is within the allowable range.When measurement is
complete or the number of pulses within the time generated by the measurement reference clock
is not within the allowable range, an interrupt request is generated.
Interrupt Controller Unit (ICU)
Low power modes
The Interrupt Controller Unit (ICU) controls which event signals are linked to the Nested Vector
Interrupt Controller (NVIC), the DMA Controller (DMAC), and the Data Transfer Controller (DTC)
modules. The ICU also controls non-maskable interrupts.
Power consumption can be reduced in multiple ways, including setting clock dividers, stopping
modules, selecting power control mode in normal operation, and transitioning to low power
modes.
Battery backup function
A battery backup function is provided for partial powering by a battery. The battery-powered area
includes the RTC, SOSC, backup memory, and switch between VCC and VBATT.
Register write protection
Memory Protection Unit (MPU)
The register write protection function protects important registers from being overwritten due to
software errors. The registers to be protected are set with the Protect Register (PRCR).
The MCU has one Memory Protection Unit (MPU).
Table 1.4
Feature
Event link
Functional description
Event Link Controller (ELC)
The Event Link Controller (ELC) uses the event requests generated by various peripheral
modules as source signals to connect them to different modules, allowing direct link between the
modules without CPU intervention.
Table 1.5
Direct memory access
Feature
Functional description
Data Transfer Controller (DTC)
A Data Transfer Controller (DTC) module is provided for transferring data when activated by an
interrupt request.
DMA Controller (DMAC)
The MCU includes an 8-channel direct memory access controller (DMAC) that can transfer data
without intervention from the CPU. When a DMA transfer request is generated, the DMAC
transfers data stored at the transfer source address to the transfer destination address.
Table 1.6
Feature
External bus interface
Functional description
External buses
● QSPI area (EQBIU): Connected to the QSPI (external device interface)
Table 1.7
Feature
Timers (1 of 2)
Functional description
General PWM Timer (GPT)
The General PWM Timer (GPT) is a 32-bit timer with GPT32 × 4 channels and a 16-bit timer with
GPT16 × 4 channels. PWM waveforms can be generated by controlling the up-counter, down-
counter, or the up- and down-counter. In addition, PWM waveforms can be generated for
controlling brushless DC motors. The GPT can also be used as a general-purpose timer.
Port Output Enable for GPT (POEG)
The Port Output Enable (POEG) function can place the General PWM Timer (GPT) output pins
in the output disable state
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RA4M3 Datasheet
1. Overview
Table 1.7
Feature
Timers (2 of 2)
Functional description
Low power Asynchronous General
Purpose Timer (AGT)
The low power Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used
for pulse output, external pulse width or period measurement, and counting external events. This
timer consists of a reload register and a down counter. The reload register and the down counter
are allocated to the same address, and can be accessed with the AGT register.
Realtime Clock (RTC)
The realtime clock (RTC) has two counting modes, calendar count mode and binary count mode,
that are used by switching register settings. For calendar count mode, the RTC has a 100-year
calendar from 2000 to 2099 and automatically adjusts dates for leap years. For binary count
mode, the RTC counts seconds and retains the information as a serial value. Binary count mode
can be used for calendars other than the Gregorian (Western) calendar.
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a 14-bit down counter that can be used to reset the MCU when
the counter underflows because the system has run out of control and is unable to refresh the
WDT. In addition, the WDT can be used to generate a non-maskable interrupt or an underflow
interrupt.
Independent Watchdog Timer (IWDT)
The Independent Watchdog Timer (IWDT) consists of a 14-bit down counter that must be
serviced periodically to prevent counter underflow. The IWDT provides functionality to reset the
MCU or to generate a non-maskable interrupt or an underflow interrupt. Because the timer
operates with an independent, dedicated clock source, it is particularly useful in returning the
MCU to a known state as a fail-safe mechanism when the system runs out of control. The IWDT
can be triggered automatically by a reset, underflow, refresh error, or a refresh of the count value
in the registers.
Table 1.8
Communication interfaces (1 of 2)
Feature
Functional description
Serial Communications Interface (SCI)
The Serial Communications Interface (SCI) × 6 channels have asynchronous and synchronous
serial interfaces:
●
Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter
(ACIA))
●
●
●
●
●
●
8-bit clock synchronous interface
Simple IIC (master-only)
Simple SPI
Smart card interface
Manchester interface
Extended Serial interface
The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and
transmission protocol. SCIn (n = 0, 3, 4, 9) has FIFO buffers to enable continuous and full-duplex
communication, and the data transfer speed can be configured independently using an on-chip
baud rate generator.
2
2
I C bus interface (IIC)
The I C bus interface (IIC) has 2 channels. The IIC module conforms with and provides a subset
2
of the NXP I C (Inter-Integrated Circuit) bus interface functions.
Serial Peripheral Interface (SPI)
Control Area Network (CAN)
The Serial Peripheral Interface (SPI) provides high-speed full-duplex synchronous serial
communications with multiple processors and peripheral devices.
The Controller Area Network (CAN) module uses a message-based protocol to receive and
transmit data between multiple slaves and masters in electromagnetically noisy applications. The
module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports up to 32
mailboxes, which can be configured for transmission or reception in normal mailbox and FIFO
modes. Both standard (11-bit) and extended (29-bit) messaging formats are supported. The CAN
module requires an additional external CAN transceiver.
USB 2.0 Full-Speed module (USBFS)
The USB 2.0 Full-Speed module (USBFS) can operate as a host controller or device controller.
The module supports full-speed and low-speed (host controller only) transfer as defined in
Universal Serial Bus Specification 2.0. The module has an internal USB transceiver and
supports all of the transfer types defined in Universal Serial Bus Specification 2.0. The USB has
buffer memory for data transfer, providing a maximum of 10 pipes. Pipes 1 to 9 can be assigned
any endpoint number based on the peripheral devices used for communication or based on your
system.
Quad Serial Peripheral Interface (QSPI) The Quad Serial Peripheral Interface (QSPI) is a memory controller for connecting a serial ROM
(nonvolatile memory such as a serial flash memory, serial EEPROM, or serial FeRAM) that has
an SPI-compatible interface.
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RA4M3 Datasheet
1. Overview
Table 1.8
Feature
Communication interfaces (2 of 2)
Functional description
Serial Sound Interface Enhanced (SSIE) The Serial Sound Interface Enhanced (SSIE) peripheral provides functionality to interface with
2
digital audio devices for transmitting I S/Monaural/TDM audio data over a serial bus. The SSIE
supports an audio clock frequency of up to 50 MHz, and can be operated as a slave or master
receiver, transmitter, or transceiver to suit various applications. The SSIE includes 32-stage
FIFO buffers in the receiver and transmitter, and supports interrupts and DMA-driven data
reception and transmission.
SD/MMC Host Interface (SDHI)
The SDHI and MultiMediaCard (MMC) interface module provides the functionality required to
connect a variety of external memory cards to the MCU. The SDHI supports both 1- and 4-bit
buses for connecting memory cards that support SD, SDHC, and SDXC formats. When
developing host devices that are compliant with the SD Specifications, you must comply with the
SD Host/Ancillary Product License Agreement (SD HALA). The MMC interface supports 1-bit, 4-
bit, and 8-bit MMC buses that provide eMMC 4.51 (JEDEC Standard JESD 84-B451) device
access. This interface also provides backward compatibility and supports high-speed SDR
transfer modes.
Table 1.9
Analog
Functional description
12-bit A/D Converter (ADC12)
A 12-bit successive approximation A/D converter is provided. Up to 22 analog input channels are
selectable. Temperature sensor output and internal reference voltage are selectable for
conversion.
12-bit D/A Converter (DAC12)
Temperature Sensor (TSN)
A 12-bit D/A converter (DAC12) is provided.
The on-chip Temperature Sensor (TSN) determines and monitors the die temperature for reliable
operation of the device. The sensor outputs a voltage directly proportional to the die
temperature, and the relationship between the die temperature and the output voltage is fairly
linear. The output voltage is provided to the ADC12 for conversion and can be further used by
the end application.
Table 1.10
Feature
Human machine interfaces
Functional description
Capacitive Touch Sensing Unit (CTSU) The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the touch
sensor. Changes in the electrostatic capacitance are determined by software that enables the
CTSU to detect whether a finger is in contact with the touch sensor. The electrode surface of the
touch sensor is usually enclosed with an electrical conductor so that a finger does not come into
direct contact with the electrode.
Table 1.11
Feature
Data processing
Functional description
Cyclic Redundancy Check (CRC)
calculator
The Cyclic Redundancy Check (CRC) calculator generates CRC codes to detect errors in the
data. The bit order of CRC calculation results can be switched for LSB-first or MSB-first
communication. Additionally, various CRC-generation polynomials are available.
Data Operation Circuit (DOC)
The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. When a selected
condition applies, 16-bit data is compared and an interrupt can be generated.
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RA4M3 Datasheet
1. Overview
1.2
Block Diagram
Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the
features.
Memory
Bus
Arm Cortex-M33
System
Clocks
1 MB code flash
MPU
DSP
FPU
POR/LVD
Reset
MOSC/SOSC
(H/M/L) OCO
PLL/PLL2
8 KB data flash
128 KB SRAM
IDAU
MPU
Mode control
1 KB Standby
SRAM
NVIC
Power control
ICU
CAC
DMA
DTC
System timer
Battery backup
Test and DBG interface
Register write
protection
DMAC × 8
Timers
Communication interfaces
Human machine interfaces
CTSU
QSPI
SCI × 6
IIC × 2
SPI
GPT32 x 4
GPT16 x 4
SDHI
AGT × 6
RTC
CAN × 2
USBFS
SSIE
WDT/IWDT
Event link
ELC
Data processing
Analog
TSN
CRC
ADC12 × 2
DAC12 × 2
DOC
Security
SCE9
Note:
Figure 1.1
1.3
Not available on all parts.
Block diagram
Part Numbering
Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.12 shows a
list of products.
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Dec 2, 2020
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RA4M3 Datasheet
1. Overview
# A A
R 7 F A 4 M 3 A F 3 C F B
0
Production identification code
Packaging, Terminal material (Pb-free)
#AA: Tray/Sn (Tin) only
#AC: Tray/others
Package type
FB: LQFP 144 pins
FP: LQFP 100 pins
FM: LQFP 64 pins
Quality Grade
Operating temperature
3: -40°C to 105°C
Code flash memory size
D: 512 KB
E: 768 KB
F: 1 MB
Feature set
Group number
Series name
RA family
Flash memory
Renesas microcontroller
Figure 1.2
Table 1.12
Part numbering scheme
Product list
Data
flash
Operating
temperature
Product part number
Package code
PLQP0144KA-B
PLQP0100KB-B
PLQP0064KB-C
PLQP0144KA-B
PLQP0100KB-B
PLQP0064KB-C
PLQP0144KA-B
Code flash
SRAM
R7FA4M3AF3CFB
R7FA4M3AF3CFP
R7FA4M3AF3CFM
R7FA4M3AE3CFB
R7FA4M3AE3CFP
R7FA4M3AE3CFM
R7FA4M3AD3CFB
1 MB
8 KB
8 KB
8 KB
128 KB
-40 to +105°C
768 KB
512 KB
128 KB
128 KB
-40 to +105°C
-40 to +105°C
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RA4M3 Datasheet
1. Overview
1.4
Function Comparison
Table 1.13
Function Comparison
R7FA4M3AF3CFB
R7FA4M3AE3CFB
R7FA4M3AD3CFB
R7FA4M3AF3CFP
R7FA4M3AE3CFP
R7FA4M3AF3CFM
R7FA4M3AE3CFM
Parts number
Pin count
144
100
64
Package
LQFP
Code flash memory
1 MB
768 KB
512 KB
1 MB
768 KB
Data flash memory
SRAM
8 KB
128 KB
64 KB
Parity
ECC
64 KB
Standby SRAM
DMA
1 KB
DTC
Yes
DMAC
8
System
CPU clock
CPU clock sources
CAC
100 MHz (max.)
MOSC, SOSC, HOCO, MOCO, LOCO, PLL
Yes
WDT/IWDT
Backup register
SCI
Yes
128 B
Communication
6
IIC
2
SPI
1
CAN
2
USBFS
QSPI
Yes
Yes
SSIE
Yes
Yes
4
No
No
SDHI/MMC
*1
Timers
Analog
GPT32
*1
4
6
GPT16
*1
AGT
RTC
Yes
ADC12
Unit 0: 12
Unit 1: 10
Unit 0: 11
Unit 1: 9
Unit 0: 7
Unit 1: 4
DAC12
TSN
2
Yes
12
HMI
CTSU
CRC
DOC
ELC
20
7
Data processing
Yes
Yes
Yes
Event control
Security
SCE9, TrustZone, and Lifecycle management
Note 1. Available pins depend on the Pin count, about details see section 1.7. Pin Lists.
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Dec 2, 2020
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RA4M3 Datasheet
1. Overview
1.5
Pin Functions
Table 1.14
Function
Pin functions (1 of 4)
Signal
I/O
Description
Power supply
VCC
Input
Power supply pin. Connect it to the system power supply. Connect
this pin to VSS by a 0.1-µF capacitor. The capacitor should be
placed close to the pin.
VCL/VCL0
I/O
Connect this pin to the VSS pin by the smoothing capacitor used to
stabilize the internal power supply. Place the capacitor close to the
pin.
VSS
Input
Ground pin. Connect it to the system power supply (0 V).
Battery Backup power pin
VBATT
XTAL
Input
Clock
Output
Input
Pins for a crystal resonator. An external clock signal can be input
through the EXTAL pin.
EXTAL
XCIN
Input
Input/output pins for the sub-clock oscillator. Connect a crystal
resonator between XCOUT and XCIN.
XCOUT
CLKOUT
Output
Output
Input
Clock output pin
Operating mode control
System control
MD
Pin for setting the operating mode. The signal level on this pin must
not be changed during operation mode transition on release from
the reset state.
RES
Input
Reset signal input pin. The MCU enters the reset state when this
signal goes low.
CAC
CACREF
TMS
Input
I/O
Measurement reference clock input pin
On-chip emulator or boundary scan pins
On-chip emulator
TDI
Input
Input
Output
Output
Output
Output
I/O
TCK
TDO
TCLK
Output clock for synchronization with the trace data
Trace data output
TDATA0 to TDATA3
SWO
Serial wire trace output pin
SWDIO
SWCLK
NMI
Serial wire debug data input/output pin
Serial wire clock pin
Input
Input
Input
Input
Interrupt
Non-maskable interrupt request pin
Maskable interrupt request pins
IRQn
IRQn-DS
Maskable interrupt request pins that can also be used in Deep
Software Standby mode
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RA4M3 Datasheet
1. Overview
Table 1.14
Function
GPT
Pin functions (2 of 4)
Signal
I/O
Description
GTETRGA, GTETRGB,
GTETRGC, GTETRGD
Input
External trigger input pins
GTIOCnA, GTIOCnB
GTIU
I/O
Input capture, output compare, or PWM output pins
Hall sensor input pin U
Input
GTIV
Input
Hall sensor input pin V
GTIW
Input
Hall sensor input pin W
GTOUUP
GTOULO
GTOVUP
GTOVLO
GTOWUP
GTOWLO
AGTEEn
AGTIOn
AGTOn
Output
Output
Output
Output
Output
Output
Input
3-phase PWM output for BLDC motor control (positive U phase)
3-phase PWM output for BLDC motor control (negative U phase)
3-phase PWM output for BLDC motor control (positive V phase)
3-phase PWM output for BLDC motor control (negative V phase)
3-phase PWM output for BLDC motor control (positive W phase)
3-phase PWM output for BLDC motor control (negative W phase)
External event input enable signals
AGT
I/O
External event input and pulse output pins
Output
Output
Output
Output
Input
Pulse output pins
AGTOAn
AGTOBn
RTCOUT
RTCICn
SCKn
Output compare match A output pins
Output compare match B output pins
RTC
SCI
Output pin for 1-Hz or 64-Hz clock
Time capture event input pins
I/O
Input/output pins for the clock (clock synchronous mode)
RXDn
Input
Input pins for received data (asynchronous mode/clock synchronous
mode)
TXDn
Output
I/O
Output pins for transmitted data (asynchronous mode/clock
synchronous mode)
CTSn_RTSn
Input/output pins for controlling the start of transmission and
reception (asynchronous mode/clock synchronous mode), active-
low.
CTSn
SCLn
Input
I/O
Input for the start of transmission.
Input/output pins for the IIC clock (simple IIC mode)
Input/output pins for the IIC data (simple IIC mode)
Input/output pins for the clock (simple SPI mode)
Input/output pins for slave transmission of data (simple SPI mode)
Input/output pins for master transmission of data (simple SPI mode)
Chip-select input pins (simple SPI mode), active-low
Input pins for received data (Extended Serial Mode)
Output pins for transmitted data (Extended Serial Mode)
SDAn
SCKn
MISOn
MOSIn
SSn
I/O
I/O
I/O
I/O
Input
Input
Output
I/O
RXDXn
TXDXn
SIOXn
Input/output pins for receivde or tramsmitted data (Extended Serial
Mode)
IIC
SCLn
SDAn
I/O
I/O
Input/output pins for the clock
Input/output pins for data
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RA4M3 Datasheet
1. Overview
Table 1.14
Function
SPI
Pin functions (3 of 4)
Signal
I/O
Description
RSPCKA
MOSIA
I/O
Clock input/output pin
I/O
Input or output pins for data output from the master
Input or output pins for data output from the slave
Input or output pin for slave selection
Output pins for slave selection
Receive data
MISOA
I/O
SSLA0
I/O
SSLA1 to SSLA3
CRXn
Output
Input
Output
Input
Input
I/O
CAN
CTXn
Transmit data
USBFS
VCC_USB
VSS_USB
USB_DP
Power supply pin
Ground pin
D+ pin of the USB on-chip transceiver. Connect this pin to the D+
pin of the USB bus.
USB_DM
I/O
D- pin of the USB on-chip transceiver. Connect this pin to the D- pin
of the USB bus.
USB_VBUS
Input
USB cable connection monitor pin. Connect this pin to VBUS of the
USB bus. The VBUS pin status (connected or disconnected) can be
detected when the USB module is operating as a function controller.
USB_EXICEN
USB_VBUSEN
Output
Output
Input
Low-power control signal for external power supply (OTG) chip
VBUS (5 V) supply enable signal for external power supply chip
USB_OVRCURA,
USB_OVRCURB
Connect the external overcurrent detection signals to these pins.
Connect the VBUS comparator signals to these pins when the OTG
power supply chip is connected.
USB_OVRCURA-DS,
USB_OVRCURB-DS
Input
Overcurrent pins for USBFS that can also be used in Deep Software
Standby mode.
Connect the external overcurrent detection signals to these pins.
Connect the VBUS comparator signals to these pins when the OTG
power supply chip is connected.
USB_ID
Input
Connect the MicroAB connector ID input signal to this pin during
operation in OTG mode
QSPI
SSIE
QSPCLK
Output
Output
I/O
QSPI clock output pin
QSSL
QSPI slave output pin
QIO0 to QIO3
SSIBCK0
Data0 to Data3
I/O
SSIE serial bit clock pins
SSILRCK0/SSIFS0
SSITXD0
I/O
LR clock/frame synchronization pins
Serial data output pin
Output
Input
I/O
SSIRXD0
Serial data input pin
SSIDATA0
AUDIO_CLK
SD0CLK
Serial data input/output pins
External clock pin for audio (input oversampling clock)
SD clock output pins
Input
Output
I/O
SDHI/MMC
SD0CMD
Command output pin and response input signal pins
SD and MMC data bus pins
SD card detection pins
SD0DAT0 to SD0DAT7
SD0CD
I/O
Input
Input
SD0WP
SD write-protect signals
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 11 of 92
RA4M3 Datasheet
1. Overview
Table 1.14
Pin functions (4 of 4)
Function
Signal
I/O
Description
Analog power supply
AVCC0
Input
Analog voltage supply pin. This is used as the analog power supply
for the respective modules. Supply this pin with the same voltage as
the VCC pin.
AVSS0
Input
Analog ground pin. This is used as the analog ground for the
respective modules. Supply this pin with the same voltage as the
VSS pin.
VREFH0
VREFL0
VREFH
Input
Input
Input
Analog reference voltage supply pin for the ADC12 (unit 0). Connect
this pin to AVCC0 when not using the ADC12 (unit 0).
Analog reference ground pin for the ADC12. Connect this pin to
AVSS0 when not using the ADC12 (unit 0).
Analog reference voltage supply pin for the ADC12 (unit 1) and D/A
Converter. Connect this pin to AVCC0 when not using the ADC12
(unit 1) and D/A Converter.
VREFL
ANmn
Input
Input
Input
Analog reference ground pin for the ADC12 and D/A Converter.
Connect this pin to AVSS0 when not using the ADC12 (unit 1) and
D/A Converter.
ADC12
Input pins for the analog signals to be processed by the A/D
converter.
(m: ADC unit number, n: pin number)
ADTRGm
Input pins for the external trigger signals that start the A/D
conversion, active-low.
DAC12
CTSU
DAn
Output
Input
I/O
Output pins for the analog signals processed by the D/A converter.
Capacitive touch detection pins (touch pins)
TSn
TSCAP
Pmn
Secondary power supply pin for the touch driver
I/O ports
I/O
General-purpose input/output pins
(m: port number, n: pin number)
P200
Input
General-purpose input pin
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 12 of 92
RA4M3 Datasheet
1. Overview
1.6
Pin Assignments
The following figures show the pin assignments from the top view.
109
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
P800
P300/TCK/SWCLK
110
P801
P301
P302
P303
VCC
VSS
111
VCC
112
VSS
113
P500
114
P501
115
P304
P305
P502
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
P503
P504
P505
P306
P307
P308
P309
P310
P506
P507
VCC
VSS
P311
P312
P015
P014
P200
P201/MD
RES
VREFL
VREFH
P208
P209
P210
P211
P214
VCC
AVCC0
AVSS0
VREFL0
VREFH0
P009
P008
VSS
P007
P006
P005
P004
P003
P002
P001
P000
P313
P202
P203
P204
P205
P206
P207
VSS
VCC
P512
P511
VCC_USB
USB_DP
USB_DM
VSS_USB
Figure 1.3
Pin assignment for LQFP 144-pin
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 13 of 92
RA4M3 Datasheet
1. Overview
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P500
P501
P300/TCK/SWCLK
P301
P502
P302
P503
P303
P504
VCC
P505
VSS
VCC
P304
VSS
P305
P015
P306
P014
P307
VREFL
VREFH
AVCC0
AVSS0
VREFL0
VREFH0
P008
P200
P201/MD
RES
P208
P209
P210
P211
P007
P214
P006
P205
P005
P206
P004
P207
P003
VCC_USB
USB_DP
USB_DM
VSS_USB
P002
P001
P000
Figure 1.4
Pin assignment for LQFP 100-pin
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P500
P300/TCK/SWCLK
P301
50
VCC
51
VSS
P302
52
P015
P303
53
P014
P304
54
VREFL
P200
55
VREFH
P201/MD
RES
56
AVCC0
57
AVSS0
P208
58
VREFL0
P205
59
VREFH0
P206
60
P004
P207
61
P003
VCC_USB
USB_DP
USB_DM
VSS_USB
62
P002
63
P001
64
P000
Figure 1.5
Pin assignment for LQFP 64-pin
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 14 of 92
RA4M3 Datasheet
1. Overview
1.7
Pin Lists
Table 1.15
Pin list (1 of 4)
Power, System,
Clock, Debug,
CAC
I/O
ports Ex. Interrupt SCI/IIC/SPI/CAN/USBFS/QSPI/SSIE/SDHI/MMC
GPT/AGT/RTC
ADC12/DAC12 CTSU
1
2
3
1
2
3
1
2
3
—
P400
P401
P402
IRQ0
SCK4/SCL0_A/AUDIO_CLK
CTS4_RTS4/SS4/SDA0_A/CTX0
CTS4/CRX0/AUDIO_CLK
GTIOC6A/AGTIO1
GTETRGA/GTIOC6B
ADTRG1
—
—
—
—
IRQ5-DS
IRQ4-DS
—
—
CACREF
AGTIO0/AGTIO1/AGTIO2/AGTIO3/
RTCIC0
4
5
4
5
—
—
—
—
P403
P404
IRQ14-DS
IRQ15-DS
SSIBCK0_A
GTIOC3A/AGTIO0/AGTIO1/AGTIO2/
AGTIO3/RTCIC1
—
—
—
—
SSILRCK0/SSIFS0_A
GTIOC3B/AGTIO0/AGTIO1/AGTIO2/
AGTIO3/RTCIC2
6
6
—
—
—
—
—
—
—
—
4
—
P405
P406
P700
P701
P702
P703
P704
P705
—
—
SSITXD0_A
GTIOC1A
—
—
7
7
—
—
SSLA3_C/SSIRXD0_A
GTIOC1B/AGTO5
—
—
8
—
—
—
—
—
—
8
—
—
MISOA_C
GTIOC5A/AGTO4
—
—
9
—
—
MOSIA_C
GTIOC5B/AGTO3
—
—
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
—
—
RSPCKA_C
GTIOC6A/AGTO2
—
—
—
—
SSLA0_C
GTIOC6B/AGTO1
—
—
—
—
SSLA1_C/CTX0
AGTO0
—
—
—
—
CTS3/SSLA2_C/CRX0
AGTIO0
—
—
VBATT
VCL0
XCIN
XCOUT
VSS
XTAL
—
—
—
—
—
9
5
—
—
—
—
—
—
10
11
12
13
14
15
—
—
—
—
—
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
6
—
—
—
—
—
—
7
—
—
—
—
—
—
8
—
—
—
—
—
—
9
P213
P212
—
IRQ2
IRQ3
—
TXD1/MOSI1/SDA1/TXDX1/SIOX1
GTETRGC/GTIOC0A/AGTEE2
ADTRG1
—
—
10 EXTAL
RXD1/MISO1/SCL1/RXDX1
GTETRGD/GTIOC0B/AGTEE1
—
11
—
—
—
—
—
—
—
—
—
—
12
13
14
15
16
VCC
—
—
—
—
—
P713
P712
P711
P710
P709
P708
P415
P414
P413
P412
P411
P410
P409
P408
P407
—
—
—
GTIOC2A/AGTOA0
—
TS17
TS16
TS15
TS14
TS13
TS12
TS11
TS10
TS09
TS08
TS07
TS06
TS05
TS04
TS03
—
—
—
—
GTIOC2B/AGTOB0
—
—
—
CTS1_RTS1/SS1
AGTEE0
—
—
—
SCK1
—
—
—
IRQ10
IRQ11
IRQ8
IRQ9
—
TXD1/MOSI1/SDA1/TXDX1/SIOX1
RXD1/MISO1/SCL1/RXDX1/AUDIO_CLK
USB_VBUSEN/SD0CD
—
—
CACREF
—
—
—
GTIOC0A/AGTIO4
—
—
CTS0/SD0WP
GTIOC0B/AGTIO5
—
—
CTS0_RTS0/SSL0/SD0CLK_A
SCK0/CTS3/SD0CMD_A
TXD0/MOSI0/SDA0/CTS3_RTS3/SS3/SD0DAT0_A
RXD0/MISO0/SCL0/SCK3/SD0DAT1_A
TXD3/MOSI3/SDA3/USB_EXICEN
CTS4/RXD3/MISO3/SCL3/SCL0_B/USB_ID
CTS4_RTS4/SS4/SDA0_B/SSLA3_A/USB_VBUS
—
GTOUUP/AGTEE3
—
—
—
GTOULO/AGTEE1
—
—
IRQ4
IRQ5
IRQ6
IRQ7
—
GTOVUP/AGTOA1
—
—
GTOVLO/AGTOB1
—
—
GTOWUP/AGTOA2
—
—
GTOWLO/GTIOC6B/AGTOB2
—
—
GTIOC6A/AGTIO0/RTCOUT
ADTRG0
—
17 VSS_USB
18 USB_DM
19 USB_DP
20 VCC_USB
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
21
22
—
—
P207
P206
—
TXD4/MOSI4/SDA4/SSLA2_A/QSSL
—
—
TSCAP
TS02
IRQ0-DS
RXD4/MISO4/SCL4/CTS9/SDA1_B/SSLA1_A/
USB_VBUSEN/SSIDATA0_C/SD0DAT2_A
GTIU
—
43
44
32
—
23 CLKOUT
P205
P204
IRQ1-DS
—
TXD4/MOSI4/SDA4/CTS9_RTS9/SS9/SCL1_B/SSLA0_A/
USB_OVRCURA-DS/SSILRCK0/SSIFS0_C/SD0DAT3_A
GTIV/GTIOC4A/AGTO1
GTIW/GTIOC4B/AGTIO1
—
—
TS01
TS00
—
CACREF
SCK4/SCK9/RSPCKA_A/USB_OVRCURB-DS/
SSIBCK0_C/SD0DAT4_A
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 15 of 92
RA4M3 Datasheet
1. Overview
Table 1.15
Pin list (2 of 4)
Power, System,
Clock, Debug,
CAC
I/O
ports Ex. Interrupt SCI/IIC/SPI/CAN/USBFS/QSPI/SSIE/SDHI/MMC
GPT/AGT/RTC
ADC12/DAC12 CTSU
45
—
—
—
P203
IRQ2-DS
CTS2_RTS2/SS2/TXD9/MOSI9/SDA9/MOSIA_A/CTX0/
SD0DAT5_A
GTIOC5A/AGTOA3
—
TS18
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
—
—
—
—
33
34
35
36
37
38
39
40
—
—
—
—
—
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
—
—
—
—
—
—
—
—
—
P202
P313
—
IRQ3-DS
—
SCK2/RXD9/MISO9/SCL9/MISOA_A/CRX0/SD0DAT6_A
GTIOC5B/AGTOB3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TS19
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SD0DAT7_A
—
VSS
—
—
—
VCC
—
—
—
—
TCLK
TDATA0
TDATA1
TDATA2
P214
P211
P210
P209
P208
—
—
QSPCLK/SD0CLK_B
GTIU/AGTO5
GTIV/AGTOA5
GTIW/AGTOB5
GTOVUP/AGTEE5
GTOVLO
—
QIO0/SD0CMD_B
—
QIO1/SD0CD
—
QIO2/SD0WP
24 TDATA3
25 RES
26 MD
—
QIO3/SD0DAT0_B
—
—
—
P201
P200
P312
P311
P310
P309
P308
P307
P306
P305
P304
—
—
—
—
27
—
—
—
—
—
—
—
—
28
—
—
29
30
31
—
NMI
—
—
—
—
CTS3_RTS3/SS3
AGTOA1
—
—
SCK3
AGTOB1
—
—
TXD3/MOSI3/SDA3/QIO3
AGTEE1
—
—
RXD3/MISO3/SCL3/QIO2
AGTOA4
—
—
CTS3/QIO1
AGTOB4
—
—
QIO0
GTOUUP_D/AGTEE4
GTOULO_D/AGTOA2
GTOWUP/AGTOB2
GTOWLO/GTIOC7A/AGTEE2
—
—
—
QSSL
—
IRQ8
IRQ9
—
QSPCLK
—
—
VSS
VCC
—
—
—
—
—
—
P303
P302
P301
P300
P108
—
CTS9
GTIOC7B
—
IRQ5
IRQ6
—
TXD2/MOSI2/SDA2/TXDX2/SIOX2/SSLA3_B
RXD2/MISO2/SCL2/RXDX2/CTS9_RTS9/SS9/SSLA2_B
SSLA1_B
GTOUUP/GTIOC4A
GTOULO/GTIOC4B/AGTIO0
GTOUUP/GTIOC0A
GTOULO/GTIOC0B/AGTOA3
GTOVUP/GTIOC1A/AGTOB3
GTOVLO/GTIOC1B/AGTEE3
GTIOC3A/AGTOA5
—
32 TCK/SWCLK
33 TMS/SWDIO
—
CTS9_RTS9/SS9/SSLA0_B
34 TDO/SWO/CLKOUT P109
—
TXD9/MOSI9/SDA9/MOSIA_B/CTX1
CTS2_RTS2/SS2/RXD9/MISO9/SCL9/MISOA_B/CRX1
SCK2/SCK9/RSPCKA_B
35 TDI
P110
P111
P112
IRQ3
IRQ4
—
36
37
—
—
TXD2/MOSI2/SDA2/TXDX2/SIOX2/SCK1/SSLA0_B/QSSL/ GTIOC3B/AGTOB5
SSIBCK0_B
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
56
57
58
—
—
59
60
61
—
—
—
—
62
63
64
38
—
—
—
—
—
—
—
—
—
—
—
—
P113
P114
P115
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RXD2/MISO2/SCL2/RXDX2/SSILRCK0/SSIFS0_B
GTIOC2A/AGTEE5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CTS9/SSIRXD0_B
GTIOC2B/AGTIO5
—
SSITXD0_B
GTIOC4A
VCC
—
—
VSS
—
—
—
—
P608
P609
P610
P611
P612
P613
P614
—
—
GTIOC4B
—
CTX1
CRX1
—
GTIOC5A/AGTO5
—
GTIOC5B/AGTO4
CACREF/CLKOUT
AGTO3
AGTO2
AGTO1
AGTO0
—
—
—
—
—
—
—
39 VCC
40 VSS
41 VCL
—
—
—
—
—
—
—
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 16 of 92
RA4M3 Datasheet
1. Overview
Table 1.15
Pin list (3 of 4)
Power, System,
Clock, Debug,
CAC
I/O
ports Ex. Interrupt SCI/IIC/SPI/CAN/USBFS/QSPI/SSIE/SDHI/MMC
GPT/AGT/RTC
ADC12/DAC12 CTSU
93
94
95
96
97
98
99
100
—
—
—
65
66
67
—
—
—
—
—
—
—
—
—
—
—
42
43
44
45
46
47
48
—
—
—
—
—
P605
P604
P603
P602
P601
P600
—
—
—
AGTO4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CTS9
AGTEE4
—
—
—
CTS9_RTS9/SS9
GTIOC7A/AGTIO4
—
—
—
TXD9/MOSI9/SDA9
GTIOC7B/AGTO3
—
—
—
RXD9/MISO9/SCL9
GTIOC6A/AGTEE3
—
CACREF/CLKOUT
—
SCK9
GTIOC6B/AGTIO3
—
VCC
VSS
—
—
—
—
—
—
—
—
—
—
101 68
102 69
103 70
104 71
105 72
106 73
107 74
108 75
P107
P106
P105
P104
P103
P102
P101
P100
P800
P801
—
—
—
AGTOA0
—
—
—
—
AGTOB0
—
—
IRQ0
—
GTETRGA/GTIOC1A/AGTO2
—
—
IRQ1
QIO2
GTETRGB/GTIOC1B/AGTEE2
—
—
—
CTS0_RTS0/SS0/CTX0/QIO3
GTOWUP/GTIOC2A/AGTIO2
—
—
—
SCK0/CRX0/QIO0
GTOWLO/GTIOC2B/AGTO0
ADTRG0
—
IRQ1
TXD0/MOSI0/SDA0/CTS1_RTS1/SS1/QIO1
GTETRGB/GTIOC5A/AGTEE0
—
—
IRQ2
RXD0/MISO0/SCL0/SCK1/QSPCLK
GTETRGA/GTIOC5B/AGTIO0
—
109
110
111
112
—
—
—
—
—
—
CTS0
AGTOA4
—
—
—
—
AGTOB4
—
VCC
VSS
—
—
—
—
—
—
—
—
—
113 76
114 77
115 78
116 79
117 80
118 81
49 CACREF
P500
P501
P502
P503
P504
P505
P506
P507
—
—
USB_VBUSEN/QSPCLK
GTIU/AGTOA0
AN116
AN117
AN118
AN119
AN120
AN121
AN122
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IRQ11
IRQ12
—
USB_OVRCURA/QSSL
GTIV/AGTOB0
USB_OVRCURB/QIO0
GTIW/AGTOA2
USB_EXICEN/QIO1
GTETRGC/AGTOB2
—
USB_ID/QIO2
GTETRGD/AGTOA3
IRQ14
IRQ15
—
QIO3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AGTOB3
—
119
120
—
—
—
121 82
122 83
123 84
124 85
125 86
126 87
127 88
128 89
129 90
130 91
50 VCC
51 VSS
—
—
—
—
—
—
—
52
53
—
—
P015
P014
—
IRQ13
—
—
AN013/DA1
AN012/DA0
—
—
54 VREFL
55 VREFH
56 AVCC0
57 AVSS0
58 VREFL0
59 VREFH0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
131
—
—
—
—
—
—
60
61
62
63
—
—
—
—
—
—
—
—
—
—
VSS
P009
P008
P007
P006
P005
P004
P003
P002
P001
P000
—
IRQ13-DS
IRQ12-DS
—
—
AN009
AN008
AN007
AN006
AN005
AN004
AN003
AN002/AN102
AN001/AN101
AN000/AN100
—
132 92
133 93
134 94
135 95
136 96
137 97
138 98
139 99
—
—
IRQ11-DS
IRQ10-DS
IRQ9-DS
—
—
—
—
—
IRQ8-DS
IRQ7-DS
IRQ6-DS
—
—
—
140 100 64
141
—
—
—
—
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 17 of 92
RA4M3 Datasheet
1. Overview
Table 1.15
Pin list (4 of 4)
Power, System,
Clock, Debug,
CAC
I/O
ports Ex. Interrupt SCI/IIC/SPI/CAN/USBFS/QSPI/SSIE/SDHI/MMC
GPT/AGT/RTC
—
ADC12/DAC12 CTSU
142
143
144
—
—
—
—
—
—
VCC
—
—
—
—
—
—
—
—
—
—
P512
P511
IRQ14
IRQ15
TXD4/MOSI4/SDA4/SCL1_A/CTX1
RXD4/MISO4/SCL4/SDA1_A/CRX1
GTIOC0A
GTIOC0B
—
Note:
Several pin names have the added suffix of _A, _B, and _C. The suffix can be ignored when assigning functionality.
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 18 of 92
RA4M3 Datasheet
2. Electrical Characteristics
2.
Electrical Characteristics
Supported peripheral functions and pins differ from one product name to another.
Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:
● VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V
● 2.7 ≤ VREFH0/VREFH ≤ AVCC0
● VSS = AVSS0 = VREFL0/VREFL = VSS_USB = 0 V
● T = T
a
opr
Figure 2.1 shows the timing conditions.
For example, P100
C
VOH = VCC × 0.7, VOL = VCC × 0.3
VIH = VCC × 0.7, VIL = VCC × 0.3
Load capacitance C = 30 pF
Figure 2.1
Input or output timing measurement conditions
The recommended measurement conditions for the timing specification of each peripheral provided are for the best
peripheral operation. Make sure to adjust the driving abilities of each pin to meet your conditions.
2.1
Absolute Maximum Ratings
Table 2.1
Parameter
Absolute maximum ratings
Symbol
Value
Unit
*2
Power supply voltage
–0.3 to +4.0
V
VCC, VCC_USB
VBATT
VBATT power supply voltage
–0.3 to +4.0
V
V
*1
V
–0.3 to VCC + 0.3
Input voltage (except for 5 V-tolerant ports )
in
*1
V
in
–0.3 to + VCC + 4.0 (max. 5.8)
V
Input voltage (5 V-tolerant ports )
Reference power supply voltage
Analog power supply voltage
VREFH/VREFH0
–0.3 to VCC + 0.3
–0.3 to +4.0
V
V
*2
AVCC0
Analog input voltage
V
T
–0.3 to AVCC0 + 0.3
–40 to +105
V
AN
*3 *4
°C
°C
Operating temperature
opr
stg
Storage temperature
T
–55 to +125
Note 1. Ports P205, P206, P400, P401, P407 to P415, and P708 to P713 are 5 V tolerant.
Note 2. Connect AVCC0 and VCC_USB to VCC.
Note 3. See section 2.2.1. Tj/Ta Definition.
Note 4. Contact a Renesas Electronics sales office for information on derating operation when Ta = +85°C to +105°C. Derating is the
systematic reduction of load for improved reliability.
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 19 of 92
RA4M3 Datasheet
2. Electrical Characteristics
Caution: Permanent damage to the MCU might result if absolute maximum ratings are exceeded.
Table 2.2
Parameter
Recommended operating conditions
Symbol
Value
Min
2.7
3.0
—
Typ
—
Max
3.6
3.6
—
Unit
V
Power supply voltages
VCC
When USB is not used
When USB is used
—
V
VSS
0
V
USB power supply voltages
VCC_USB
VSS_USB
VBATT
—
VCC
0
—
V
—
—
V
VBATT power supply voltage
Analog power supply voltages
1.8
—
—
3.6
—
V
*1
VCC
V
AVCC0
AVSS0
—
0
—
V
Note 1. Connect AVCC0 to VCC. When the A/D converter and the D/A converter are not in use, do not leave the AVCC0, VREFH/VREFH0,
AVSS0, and VREFL/VREFL0 pins open. Connect the AVCC0 and VREFH/VREFH0 pins to VCC, and the AVSS0 and VREFL/
VREFL0 pins to VSS, respectively.
2.2
DC Characteristics
2.2.1
Tj/Ta Definition
Table 2.3
DC characteristics
Conditions: Products with operating temperature (T ) -40 to +105°C
a
Parameter
Symbol
Typ
Max
Unit
Test conditions
Permissible junction temperature
T
—
125
°C
High-speed mode
Low-speed mode
Subosc-speed mode
j
Note:
Make sure that T = T + θja × total power consumption (W), where total power consumption = (VCC - V ) × ΣI + V × ΣI
+
OL
j
a
OH
OH
OL
I max × VCC.
CC
2.2.2
I/O V , V
IH
IL
Table 2.4
Parameter
I/O VIH, VIL (1 of 2)
Symbol Min
Typ Max
Unit
Input voltage
(except for
Schmitt trigger
input pins)
Peripheral
function pin
EXTAL (external clock input), SPI (except RSPCK)
IIC (SMBus)
V
VCC ×
0.8
—
—
V
IH
V
V
—
—
—
VCC × 0.2
IL
2.1
VCC + 3.6
(max 5.8)
IH
V
—
—
0.8
IL
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 20 of 92
RA4M3 Datasheet
2. Electrical Characteristics
Table 2.4
I/O VIH, VIL (2 of 2)
Parameter
Symbol Min
Typ Max
Unit
Schmitt trigger Peripheral
IIC (except for SMBus)
V
VCC ×
0.7
—
VCC + 3.6
V
IH
input voltage
function pin
(max 5.8)
VCC × 0.3
—
V
—
—
—
IL
ΔV
V
VCC ×
0.05
T
*1 *5
VCC ×
0.8
—
VCC + 3.6
(max 5.8)
5 V-tolerant ports
IH
V
—
—
—
VCC × 0.2
—
IL
ΔV
VCC ×
0.05
T
RTCIC0,
RTCIC1,
RTCIC2
When using the
Battery Backup
Function
When VBATT
power supply is
selected
V
V
0.8
×
—
V
+ 0.3
× 0.2
IH
BATT
BATT
V
—
—
—
V
IL
BATT
ΔV
V
×
—
T
BATT
0.05
When VCC
power supply is
selected
V
VCC ×
0.8
—
Higher
voltage
either
IH
VCC + 0.3 V
or
V
+ 0.3
BATT
V
V
—
—
—
VCC × 0.2
—
IL
ΔV
VCC ×
0.05
T
When not using the Battery Backup
Function
V
V
VCC ×
0.8
—
VCC + 0.3
IH
—
—
—
VCC × 0.2
—
IL
ΔV
VCC ×
0.05
T
*2
V
VCC ×
0.8
—
—
Other input pins
IH
V
—
—
—
VCC × 0.2
—
IL
ΔV
VCC ×
0.05
T
*3 *5
Ports
V
VCC ×
0.8
—
VCC + 3.6
(max 5.8)
V
5 V-tolerant ports
IH
V
V
—
—
—
VCC × 0.2
—
IL
*4
VCC ×
0.8
Other input pins
IH
V
—
—
VCC × 0.2
IL
Note 1. RES and peripheral function pins associated with Ports P205, P206, P400, P401, P407 to P415, and P708 to P713 (total 22 pins).
Note 2. All input pins except for the peripheral function pins already described in the table.
Note 3. Ports P205, P206, P400, P401, P407 to P415, and P708 to P713 (total 21 pins).
Note 4. All input pins except for the ports already described in the table.
Note 5. When VCC is less than 2.7 V, the input voltage of 5 V-tolerant ports should be less than 3.6 V, otherwise breakdown may occur
because 5 V-tolerant ports are electrically controlled so as not to violate the break down voltage.
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 21 of 92
RA4M3 Datasheet
2. Electrical Characteristics
2.2.3
I/O I , I
OH OL
Table 2.5
Parameter
I/O IOH, IOL
Symbol
Min Typ Max Unit
Permissible output current (average value
per pin)
Ports P000 to P009, P014, P015, P201
—
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–2.0 mA
2.0 mA
–2.0 mA
2.0 mA
–4.0 mA
4.0 mA
–20 mA
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
*1
Ports P205, P206, P407 to P415, P708
to P713 (total 17 pins)
Low drive
*2
Middle drive
*3
High drive
20
mA
*4
*1
–2.0 mA
2.0 mA
–4.0 mA
4.0 mA
–16 mA
Other output pins
Low drive
*2
Middle drive
*3
High drive
16
mA
Permissible output current (max value per
pin)
Ports P000 to P009, P014, P015, P201
—
–4.0 mA
4.0 mA
–4.0 mA
4.0 mA
–8.0 mA
8.0 mA
–40 mA
*1
Ports P205, P206, P407 to P415, P708
to P713 (total 17 pins)
Low drive
*2
Middle drive
*3
High drive
40
mA
*4
*1
–4.0 mA
4.0 mA
–8.0 mA
8.0 mA
–32 mA
Other output pins
Low drive
*2
Middle drive
*3
High drive
32
–80 mA
80 mA
mA
Permissible output current (maxvalue of total Maximum of all output pins
of all pins)
ΣI
ΣI
OH (max)
OL (max)
Note 1. This is the value when low driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving
ability is retained in Deep Software Standby mode.
Note 2. This is the value when middle driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving
ability is retained in Deep Software Standby mode.
Note 3. This is the value when high driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving
ability is retained in Deep Software Standby mode.
Note 4. Except for P200, which is an input port.
Caution: To protect the reliability of the MCU, the output current values should not exceed the values in this table.
The average output current indicates the average value of current measured during 100 µs.
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 22 of 92
RA4M3 Datasheet
2. Electrical Characteristics
2.2.4
I/O V , V , and Other Characteristics
OH OL
Table 2.6
I/O VOH, VOL, and other characteristics
Parameter
Symbol Min
Typ Max Unit Test conditions
Output voltage
IIC
V
OL
V
OL
V
OL
V
OL
V
OH
—
—
—
—
—
—
—
0.4
0.4
0.6
0.4
—
V
I
I
I
I
I
= 3.0 mA
OL
OL
OL
OL
OH
= 6.0 mA
*1
= 15.0 mA (ICFER.FMPE = 1)
= 20.0 mA (ICFER.FMPE = 1)
= –20 mA
IIC
Ports P205, P206, P407 to P415,
P708 to P713 (total of 17 pins)
VCC – 1.0 —
—
*2
VCC = 3.3 V
V
—
—
1.0
I
OL
= 20 mA
OL
VCC = 3.3 V
Other output pins
V
V
VCC – 0.5 —
—
I
= –1.0 mA
= 1.0 mA
OH
OL
OH
OL
—
—
—
—
0.5
I
Input leakage current
RES
|I |
in
5.0 µA
V
V
= 0 V
= 5.5 V
in
in
Port P200
—
—
—
—
—
—
1.0
V
V
= 0 V
= VCC
in
in
Three-state leakage current 5 V-tolerant ports
(off state)
|I
|
—
5.0 µA
1.0
V
V
= 0 V
= 5.5 V
TSI
in
in
Other ports (except for port P200)
—
V
V
= 0 V
= VCC
in
in
Input pull-up MOS current
Input capacitance
Ports P0 to P8
I
–300
—
–10 µA VCC = 2.7 to 3.6 V
= 0 V
p
V
in
USB_DP, USB_DM, and ports
P014, P015, P400, P401, P511,
P512
C
16
pF
Vbias = 0 V
Vamp = 20 mV
f = 1 MHz
in
Ta = 25°C
Other input pins
—
—
8
Note 1. SCL0_A, SDA0_A (total 2 pins).
Note 2. This is the value when high driving ability is selected in the Port Drive Capability bit in the PmnPFS register.
The selected driving ability is retained in Deep Software Standby mode.
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 23 of 92
RA4M3 Datasheet
2. Electrical Characteristics
2.2.5
Operating and Standby Current
Table 2.7
Parameter
Supply
Operating and standby current (1 of 2)
Symbol Min Typ
Max Unit Test conditions
*2 *13
*3
High-speed
mode
—
—
—
—
12
22
95
—
—
mA ICLK = 100 MHz
PCLKA = 100
MHz
Maximum
I
CC
*1
current
®*5 *6 *12
CoreMark
PCLKB = 50
MHz
Normal mode
All peripheral clocks enabled,
while (1) code executing from
flash
PCLKC = 50
MHz
*4 *12
PCLKD = 100
MHz
FCLK = 50 MHz
All peripheral clocks disabled,
while (1) code executing from
flash
—
—
12
—
*5 *6 *12
*5
*6
*7
Sleep mode
7
47
*13
*12
Increase during Data flash P/E
—
—
—
6
—
—
—
BGO operation
Code flash P/E
8
*5 *10
*5 *11
1.9
ICLK = 1 MHz
Low-speed mode
—
1.7
—
ICLK = 32.768
kHz
Subosc-speed mode
Software Standby mode
SNZCR.RXDREQEN = 1
SNZCR.RXDREQEN = 0
—
—
—
—
34
—
—
—
1.6
Deep Software Power supplied to Standby SRAM and USB
Standby mode resume detecting unit
16.9 131
µA
—
—
—
Power not
Power-on reset circuit low
power function disabled
—
—
11.8 31
supplied to
SRAM or USB
resume
Power-on reset circuit low
power function enabled
4.8
21
detecting unit
Increase when
the RTC and
AGT are
When the low-speed on-chip
oscillator (LOCO) is in use
—
—
—
—
—
—
—
4.0
1.2
1.5
0.9
1.3
1.0
1.7
—
—
—
—
—
—
—
—
—
—
When a crystal oscillator for low
clock loads is in use
operating
When a crystal oscillator for
standard clock loads is in use
RTC operating while VCC is off (with the
battery backup function, only the RTC and
sub-clock oscillator operate)
When a crystal
oscillator for low
clock loads is in use
V
= 1.8 V,
BATT
VCC = 0 V
V
= 3.3 V,
BATT
VCC = 0 V
V = 1.8 V,
BATT
When a crystal
oscillator for
standard clock loads
is in use
VCC = 0 V
V
= 3.3 V,
BATT
VCC = 0 V
*8
Inrush current on returning from deep
software standby mode
I
—
—
160
1.0
—
—
mA
µC
Inrush current
RUSH
Energy of inrush
E
RUSH
*8
current
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 24 of 92
RA4M3 Datasheet
2. Electrical Characteristics
Table 2.7
Parameter
Operating and standby current (2 of 2)
Symbol Min Typ
Max Unit Test conditions
Analog
power supply
current
During 12-bit A/D conversion
Temperature sensor
AI
—
—
—
—
—
—
0.8
0.1
0.1
0.6
0.9
2
1.1
0.2
0.2
1.1
1.6
8
mA
mA
mA
mA
mA
µA
—
—
—
—
—
—
CC
During D/A conversion (per unit)
Without AMP output
With AMP output
Waiting for A/D, D/A conversion (all units)
*9
ADC12, DAC12 in standby modes (all units)
During 12-bit A/D conversion (unit 0)
Waiting for 12-bit A/D conversion (unit 0)
ADC12 in standby modes (unit 0)
Reference
power supply
current
AI
AI
—
—
—
—
—
—
—
—
—
—
70
120
µA
µA
µA
µA
mA
mA
µA
µA
—
—
—
—
—
—
—
—
REFH0
0.07 0.5
0.07 0.5
(VREFH0)
Reference
power supply
current
During 12-bit A/D conversion (unit 1)
During D/A conversion (per unit)
70
120
0.4
0.4
REFH
Without AMP output
With AMP ouput
0.1
0.1
(VREFH)
Waiting for 12-bit A/D (unit 1), D/A (all units) conversion
ADC12 unit 1 in standby modes
0.07 0.8
0.07 0.8
USB
operating
current
Low speed
Full speed
USB
USB
I
I
3.5
4.0
6.5
mA VCC_USB
CCUSBLS
10.0 mA VCC_USB
CCUSBFS
Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.
Note 2. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation.
Note 3. I depends on f (ICLK) as follows.
CC
I
I
I
I
Max. = 0.53 × f + 42 (max. operation in high-speed mode)
Typ. = 0.09 × f + 3.6 (normal operation in high-speed mode, all peripheral clocks disabled)
Typ. = 0.2 × f + 1.7 (low-speed mode)
CC
CC
CC
CC
Max. = 0.05 × f + 42 (sleep mode)
Note 4. This does not include the BGO operation.
Note 5. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.
Note 6. FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (1.563 MHz).
Note 7. FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (3.125 MHz).
Note 8. Reference value
Note 9. When the MCU is in Software Standby mode or the MSTPCRD.MSTPD16 (12-Bit A/D Converter 0 Module Stop bit) and
MSTPCRD.MSTPD15 (12-bit A/D converter 1 module stop bit) are in the module-stop state.
Note 10. FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (15.6 kHz).
Note 11. PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (512 Hz). FCLK is the same frequency as that of ICLK.
Note 12. PLL output frequency = 100MHz.
Note 13. PLL output frequency = 200MHz.
Table 2.8
Coremark and normal mode current
Parameter
Symbol
Typ
119
115
Unit
Test conditions
*1
*2 *3
I
µA/MHz
ICLK = 100MHz
PCLKA
= PCLKB
= PCLKC
= PCLKD
= FCLK
Supply Current
Coremark
CC
Normal mode
All peripheral
clocks disabled,
cache on, while
(1) code
executing from
= 1.56 MHz
*2 *3
flash
All peripheral
clocks disabled,
cache off, while
(1) code
117
executing from
*2 *3
flash
Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.
Note 2. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 25 of 92
RA4M3 Datasheet
2. Electrical Characteristics
Note 3. PLL output frequency = 100MHz.
100.0
10.0
1.0
0.1
-40
-20
0
20
40
Ta (°C)
60
80
100
Average value of the tested middle samples during product evaluation.
Average value of the tested upper-limit samples during product evaluation.
Figure 2.2
Temperature dependency in Software Standby mode (reference data)
1000
100
10
1
-40
-20
0
20
40
Ta (°C)
60
80
100
Average value of the tested middle samples during product evaluation.
Average value of the tested upper-limit samples during product evaluation.
Figure 2.3
Temperature dependency in Deep Software Standby mode, power supplied to standby SRAM
and USB resume detecting unit (reference data)
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RA4M3 Datasheet
2. Electrical Characteristics
100
10
1
-40
-20
0
20
40
Ta (°C)
60
80
100
Average value of the tested middle samples during product evaluation.
Average value of the tested upper-limit samples during product evaluation.
Figure 2.4
Temperature dependency in Deep Software Standby mode, power not supplied to SRAM or
USB resume detecting unit, power-on reset circuit low power function disabled (reference
data)
100
10
1
-40
-20
0
20
40
Ta (°C)
60
80
100
Average value of the tested middle samples during product evaluation.
Average value of the tested upper-limit samples during product evaluation.
Figure 2.5
Temperature dependency in Deep Software Standby mode, power not supplied to SRAM or
USB resume detecting unit, power-on reset circuit low power function enabled (reference data)
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RA4M3 Datasheet
2. Electrical Characteristics
2.2.6
VCC Rise and Fall Gradient and Ripple Frequency
Table 2.9
Rise and fall gradient characteristics
Test
Parameter
Symbol
Min
Typ Max Unit
conditions
VCC rising gradient
VCC falling gradient
Voltage monitor 0 reset disabled at startup
Voltage monitor 0 reset enabled at startup
SrVCC
0.0084
0.0084
0.0084
—
—
—
20
—
20
ms/V
—
—
—
*1
SCI/USB boot mode
*2
SfVCC
0.0084
—
—
ms/V
—
Note 1. At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of the OFS1.LVDAS bit.
Note 2. This applies when VBATT is used.
Table 2.10
Rising and falling gradient and ripple frequency characteristics
The ripple voltage must meet the allowable ripple frequency f
within the range between the VCC upper limit (3.6 V) and lower limit (2.7
r(VCC)
V). When the VCC change exceeds VCC ±10%, the allowable voltage change rising and falling gradient dt/dVCC must be met.
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Allowable ripple
frequency
f
—
—
10
kHz
Figure 2.6
r (VCC)
V
≤ VCC × 0.2
r (VCC)
—
—
—
—
1
MHz
MHz
ms/V
Figure 2.6
≤ VCC × 0.08
V
r (VCC)
—
10
—
Figure 2.6
≤ VCC × 0.06
V
r (VCC)
Allowable voltage
change rising and
falling gradient
dt/dVCC
1.0
When VCC change
exceeds VCC ±10%
1 / fr(VCC)
VCC
Vr(VCC)
Figure 2.6
Ripple waveform
2.2.7
Thermal Characteristics
Maximum value of junction temperature (Tj) must not exceed the value of “section 2.2.1. Tj/Ta Definition”.
Tj is calculated by either of the following equations.
● Tj = Ta + θja × Total power consumption
● Tj = Tt + Ψjt × Total power consumption
– Tj : Junction Temperature (°C)
– Ta : Ambient Temperature (°C)
– Tt : Top Center Case Temperature (°C)
– θja : Thermal Resistance of “Junction”-to-“Ambient” (°C/W)
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RA4M3 Datasheet
2. Electrical Characteristics
– Ψjt : Thermal Resistance of “Junction”-to-“Top Center Case” (°C/W)
● Total power consumption = Voltage × (Leakage current + Dynamic current)
● Leakage current of IO = Σ (I × V ) /Voltage + Σ (|I | × |VCC – V |) /Voltage
OL
OL
OH
OH
● Dynamic current of IO = Σ IO (C + C ) × IO switching frequency × Voltage
in
load
– C : Input capacitance
in
– C : Output capacitance
load
Regarding θja and Ψjt, refer to Table 2.11.
Table 2.11
Parameter
Thermal Resistance
Package
*1
Symbol
Value
38.0
35.0
33.0
0.80
0.76
0.63
Unit
Test conditions
Thermal
Resistance
64-pin LQFP (PLQP0064KB-C)
100-pin LQFP (PLQP0100KB-B)
144-pin LQFP (PLQP0144KA-B)
64-pin LQFP (PLQP0064KB-C)
100-pin LQFP (PLQP0100KB-B)
144-pin LQFP (PLQP0144KA-B)
θja
°C/W JESD 51-2 and 51-7
compliant
Ψjt
°C/W JESD 51-2 and 51-7
compliant
Note 1. The values are reference values when the 4-layer board is used. Thermal resistance depends on the number of layers or size of the
board. For details, refer to the JEDEC standards.
2.2.7.1
Calculation guide of I max
CC
Table 2.12 shows the power consumption of each unit.
Table 2.12
Power consumption of each unit (1 of 2)
*1
Dynamic current/
Leakage current
MCU
Domain
Frequency
[MHz]
Current
[uA/MHz]
Current
[mA]
Category
Item
*2
*3
*3
*3
Leakage current
Analog
—
—
—
—
—
—
—
—
21.22
25.22
30.22
37.42
LDO and Leak
Ta = 75 °C
Ta = 85 °C
Ta = 95 °C
*3
Ta = 105 °C
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RA4M3 Datasheet
2. Electrical Characteristics
Table 2.12
Power consumption of each unit (2 of 2)
*1
Dynamic current/
Leakage current
MCU
Domain
Frequency
[MHz]
Current
[uA/MHz]
Current
[mA]
Category
Item
Dynamic current
CPU
Operation with
Coremark
100
86.493
8.65
Flash and SRAM
*4
*4
Peripheral Unit
Timer
100
100
3.548
3.946
0.35
0.39
GPT16 (4ch)
GPT32 (4ch)
POEG (4 Groups)
50
50
1.378
0.07
0.50
*4
10.095
AGT (6ch)
RTC
50
50
50
50
100
5.239
0.722
0.267
8.788
18.077
0.26
0.04
0.01
0.44
1.81
WDT
IWDT
USBFS
Communication
interfaces
*4
SCI (6ch)
*4
50
50
3.014
3.843
0.15
0.19
IIC (2ch)
*4
CAN (2ch)
SPI
100
100
50
3.394
2.587
3.131
7.074
4.697
0.34
0.26
0.16
0.35
0.47
QSPI
SSIE
SDHI
50
*4
Analog
100
ADC12 (2 Units)
*4
100
3.543
0.35
DAC12 (2ch)
TSN
50
50
0.166
0.678
0.01
0.03
Human machine
interfaces
CTSU
Event link
ELC
50
1.016
218.100
0.521
0.358
0.909
5.180
3.792
0.05
21.81
0.05
0.04
0.05
0.52
0.38
Security
SCE9
CRC
DOC
CAC
DMAC
DTC
100
100
100
50
Data processing
System
DMA
100
100
Note 1. The values are guaranteed by design.
Note 2. LDO and Leak are internal voltage regulator’s current and MCU’s leakage current.
It is selected according to the temperature of Ta.
Note 3. Δ(Tj-Ta) = 20 °C is considered to measure the current.
Note 4. To determine the current consumption per channel, group or unit, divide Current [mA] by the number of channels, groups or units.
Table 2.13 shows the outline of operation for each unit.
Table 2.13
Peripheral
GPT
Outline of operation for each unit (1 of 2)
Outline of operation
Operating modes is set to saw-wave PWM mode.
GPT is operating with PCLKD.
POEG
AGT
Only clear module stop bit.
AGT is operating with PCLKB.
RTC is operating with LOCO.
RTC
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RA4M3 Datasheet
2. Electrical Characteristics
Table 2.13
Peripheral
WDT
Outline of operation for each unit (2 of 2)
Outline of operation
WDT is operating with PCLKB.
IWDT is operating with IWDTCLK.
IWDT
USBFS
Transfer types is set to bulk transfer.
USBFS is operating using Full-speed transfer (12 Mbps).
SCI
IIC
SCI is transmitting data in clock synchronous mode.
Communication format is set to I2C-bus format.
IIC is transmitting data in master mode.
CAN
SPI
CAN is transmitting and receiving data in self-test mode 1.
SPI mode is set to SPI operation (4-wire method).
SPI master/slave mode is set to master mode.
SPI is transmitting 8-bit width data.
QSPI
SSIE
QSPI is issuing Fast Read Quad I/O Instruction.
Communication mode is set to Master.
System word length is set to 32 bits.
Data word length is set to 20 bits.
SSIE is transmitting data using I2S format.
SDHI
Transfer bus mode is set to 4-bit wide bus mode.
SDHI is issuing CMD24 (single-block write).
ADC12
Resolution is set to 12-bit accuracy.
Data registers is set to A/D-converted value addition mode.
ADC12 is converting the analog input in continuous scan mode.
DAC12
TSN
DAC12 is outputting the conversion result while updating the value of data register.
TSN is operating.
CTSU
ELC
CTSU is operating in self-capacitance single scan mode.
Only clear module stop bit.
SCE9
CRC
DOC
CAC
SCE9 is executing built-in self test.
CRC is generating CRC code using 32-bit CRC32-C polynomial.
DOC is operating in data addition mode.
Measurement target clocks is set to PCLKB.
Measurement reference clocks is set to PCLKB.
CAC is measuring the clock frequency accuracy.
DMAC
DTC
Bit length of transfer data is set to 32 bits.
Transfer mode is set to block transfer mode.
DMAC is transferring data from SRAM0 to SRAM0.
Bit length of transfer data is set to 32 bits.
Transfer mode is set to block transfer mode.
DTC is transferring data from SRAM0 to SRAM0.
2.2.7.2
Example of T calculation
j
Assumption :
● Package 144-pin LQFP : θja = 33.0 °C/W
● Ta = 100 °C
● I max = 70 mA
CC
● VCC = 3.5 V (VCC = AVCC = VCC_USB)
● I = 1 mA, V = VCC – 0.5 V, 12 Outputs
OH
OH
● I = 20 mA, V = 1.0 V, 8 Outputs
OL
OL
● I = 1 mA, V = 0.5 V, 12 Outputs
OL
OL
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RA4M3 Datasheet
● C = 8 pF, 32 pins, Input frequency = 10 MHz
2. Electrical Characteristics
in
● C
= 30 pF, 32 pins, Output frequency = 10 MHz
load
Leakage current of IO = Σ (V × I ) / Voltage + Σ ((VCC - V ) × I ) / Voltage
OL
OL
OH
OH
= (20 mA × 1 V) × 8 / 3.5 V + (1 mA × 0.5 V) × 12 / 3.5 V + ((VCC - (VCC - 0.5 V)) × 1 mA) × 12 / 3.5 V
= 45.7 mA + 1.71 mA + 1.71 mA
= 49.1 mA
Dynamic current of IO = Σ IO (C + C
) × IO switching frequency × Voltage
in
load
= ((8 pF × 32) × 10 MHz + (30 pF × 32) × 10 MHz) × 3.5 V
= 42.6 mA
Total power consumption = Voltage × (Leakage current + Dynamic current)
= (70 mA × 3.5 V) + (49.1 mA + 42.6 mA) × 3.5 V
= 566 mW (0.566 W)
Tj = Ta + θja × Total power consumption
= 100 °C + 33.0 °C/W × 0.566W
= 118.7 °C
2.3
AC Characteristics
Frequency
2.3.1
Table 2.14
Parameter
Operation frequency value in high-speed mode
Symbol Min
Typ
—
Max
100
100
50
Unit
Operation frequency
System clock (ICLK)
f
—
—
—
MHz
Peripheral module clock (PCLKA)
Peripheral module clock (PCLKB)
Peripheral module clock (PCLKC)
—
—
*2
*1
—
50
—
—
Peripheral module clock (PCLKD)
Flash interface clock (FCLK)
—
—
100
50
—
Note 1. FCLK must run at a frequency of at least 4 MHz when programming or erasing the flash memory.
Note 2. When the ADC12 is used, the PCLKC frequency must be at least 1 MHz.
Table 2.15
Parameter
Operation frequency value in low-speed mode
Symbol Min
Typ
—
Max
Unit
Operation frequency
System clock (ICLK)
f
—
—
—
1
1
1
1
MHz
Peripheral module clock (PCLKA)
Peripheral module clock (PCLKB)
—
—
*2
*2
—
Peripheral module clock (PCLKC)
Peripheral module clock (PCLKD)
—
—
—
—
—
1
1
*1
Flash interface clock (FCLK)
Note 1. Programming or erasing the flash memory is disabled in low-speed mode.
Note 2. When the ADC12 is used, the PCLKC frequency must be set to at least 1 MHz.
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RA4M3 Datasheet
2. Electrical Characteristics
Table 2.16
Operation frequency value in Subosc-speed mode
Parameter
Symbol Min
Typ
—
Max
36.1
36.1
36.1
36.1
Unit
Operation frequency
System clock (ICLK)
f
29.4
—
kHz
Peripheral module clock (PCLKA)
Peripheral module clock (PCLKB)
—
—
—
*2
—
—
Peripheral module clock (PCLKC)
Peripheral module clock (PCLKD)
—
—
—
36.1
36.1
*1
29.4
Flash interface clock (FCLK)
Note 1. Programming or erasing the flash memory is disabled in Subosc-speed mode.
Note 2. The ADC12 cannot be used.
2.3.2
Clock Timing
Table 2.17
Clock timing except for sub-clock oscillator (1 of 2)
Parameter
Symbol
Min
41.66
15.83
15.83
—
Typ
—
—
—
—
—
—
—
Max
—
Unit Test conditions
EXTAL external clock input cycle time
EXTAL external clock input high pulse width
EXTAL external clock input low pulse width
EXTAL external clock rise time
EXTAL external clock fall time
Main clock oscillator frequency
t
t
t
t
t
f
t
f
t
f
ns
ns
ns
ns
ns
Figure 2.7
EXcyc
—
EXH
—
EXL
5.0
5.0
24
EXr
—
EXf
8
MHz —
MAIN
*1
*1
—
ms Figure 2.8
Main clock oscillation stabilization wait time (crystal)
LOCO clock oscillation frequency
—
MAINOSCWT
LOCO
LOCOWT
ILOCO
29.4912 32.768 36.0448 kHz
—
LOCO clock oscillation stabilization wait time
ILOCO clock oscillation frequency
—
—
15
8
60.4
µs
Figure 2.9
—
13.5
6.8
16.5
kHz
MOCO clock oscillation frequency
F
9.2
MHz —
µs
MOCO
MOCO clock oscillation stabilization wait time
t
f
f
f
f
f
f
f
f
f
t
—
—
16
18
20
16
18
20
15.0
—
MOCOWT
HOCO16
HOCO18
HOCO20
HOCO16
HOCO18
HOCO20
HOCO16
HOCO18
HOCO20
HOCOWT
HOCO clock oscillator oscillation
frequency
Without FLL
15.78
17.75
19.72
15.71
17.68
19.64
16.22
18.25
20.28
16.29
18.32
20.36
16.040
18.045
20.050
64.7
MHz –20 ≤ Ta ≤ 105°C
–40 ≤ Ta ≤ –20°C
With FLL
15.960 16
17.955 18
19.950 20
–40 ≤ Ta ≤ 105°C
Sub-clock frequency accuracy
is ±50 ppm.
*2
—
—
µs
—
HOCO clock oscillation stabilization wait time
HOCO period jitter
—
—
±85
—
—
ps
—
—
FLL stabilization wait time
t
f
f
t
—
1.8
ms
FLLWT
PLL clock frequency
100
120
—
—
200
240
174.9
MHz —
MHz —
PLL
PLL2 clock frequency
—
PLL2
PLL/PLL2 clock oscillation stabilization wait time
—
µs
Figure 2.10
PLLWT
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RA4M3 Datasheet
2. Electrical Characteristics
Table 2.17
Clock timing except for sub-clock oscillator (2 of 2)
Parameter
Symbol
Min
—
Typ
Max
—
Unit Test conditions
PLL/PLL2 period jitter
f
f
, f
≥ 120MHz
—
±100
±120
±300
ps
ps
ps
—
PLL PLL2
, f
< 120MHz —
—
—
—
—
PLL PLL2
PLL/PLL2 long term jitter
—
—
Term: 1µs, 10µs
Note 1. When setting up the main clock oscillator, ask the oscillator manufacturer for an oscillation evaluation, and use the results as the
recommended oscillation stabilization time. Set the MOSCWTCR register to a value equal to or greater than the recommended
value.
After changing the setting in the MOSCCR.MOSTP bit to start main clock operation, read the OSCSF.MOSCSF flag to confirm that
it is 1, and then start using the main clock oscillator.
Note 2. This is the time from release from reset state until the HOCO oscillation frequency (f
) reaches the range for guaranteed
HOCO
operation.
Table 2.18
Parameter
Clock timing for the sub-clock oscillator
Symbol
Min Typ
Max Unit Test conditions
Sub-clock frequency
f
—
—
32.768
—
—
—
kHz
s
—
SUB
*1
Sub-clock oscillation stabilization wait time
t
Figure 2.11
SUBOSCWT
Note 1. When setting up the sub-clock oscillator, ask the oscillator manufacturer for an oscillation evaluation and use the results as the
recommended oscillation stabilization time.
After changing the setting in the SOSCCR.SOSTP bit to start sub-clock operation, only start using the sub-clock oscillator after the
sub-clock oscillation stabilization time elapses with an adequate margin. A value that is two times the value shown is recommended.
tXcyc
tXH
tXL
EXTAL external clock input
VCC × 0.5
tXr
tXf
Figure 2.7
EXTAL external clock input timing
MOSCCR.MOSTP
Main clock oscillator output
Main clock
tMAINOSCWT
Figure 2.8
Main clock oscillation start timing
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RA4M3 Datasheet
2. Electrical Characteristics
LOCOCR.LCSTP
On-chip oscillator output
tLOCOWT
LOCO clock
Figure 2.9
LOCO clock oscillation start timing
PLLCR.PLLSTP
PLL2CR.PLL2STP
PLL/PLL2 circuit output
tPLLWT
OSCSF.PLLSF
OSCSF.PLL2SF
PLL/PLL2 clock
Figure 2.10
PLL/PLL2 clock oscillation start timing
SOSCCR.SOSTP
Sub-clock oscillator output
tSUBOSCWT
Sub-clock
Figure 2.11
Sub-clock oscillation start timing
2.3.3
Reset Timing
Table 2.19
Parameter
Reset timing (1 of 2)
Symbol Min Typ Max Unit Test conditions
RES pulse width
Power-on
Deep Software Standby mode
t
t
t
0.7
0.6
0.3
—
—
—
—
—
—
ms Figure 2.12
ms Figure 2.13
ms
RESWP
RESWD
RESWS
Software Standby mode, Subosc-speed
mode
All other
t
t
200
—
—
—
µs
RESW
Wait time after RES cancellation
37.3 41.2 µs
Figure 2.12
RESWT
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RA4M3 Datasheet
2. Electrical Characteristics
Table 2.19
Parameter
Reset timing (2 of 2)
Symbol Min Typ Max Unit Test conditions
Wait time after internal reset cancellation
t
—
324 397.7 µs
—
RESW2
(IWDT reset, WDT reset, software reset, SRAM parity error reset, SRAM ECC error
reset, bus master MPU error reset, TrustZone error reset, Cache parity error reset)
VCC
RES
VCCmin
tRESWP
Internal reset signal
(low is valid)
tRESWT
Figure 2.12
RES pin input timing under the condition that VCC exceeds VPOR voltage threshold
tRESWD, tRESWS, tRESW
RES
Internal reset signal
(low is valid)
tRESWT
Figure 2.13
Reset input timing
2.3.4
Wakeup Timing
Table 2.20
Parameter
Timing of recovery from low power modes (1 of 2)
Symbol
Min Typ Max Unit Test conditions
*13
Recovery time from
Software Standby
mode
Crystal resonator
connected to main clock
oscillator
System clock source is
main clock oscillator
—
2.1
2.4
ms Figure 2.14
The division ratio of all
oscillators is 1.
t
SBYMC
*2
*1
*13
System clock source is
PLL with main clock
—
2.2
2.6
ms
t
SBYPC
*3
oscillator
*13
*13
External clock input to
main clock oscillator
System clock source is
main clock oscillator
—
—
45
125 μs
t
t
SBYEX
*4
System clock source is
PLL with main clock
170 255 μs
SBYPE
*5
oscillator
*6 *11
*13
*13
*13
—
—
—
—
—
0.7
0.7
55
0.8
0.9
ms
ms
System clock source is sub-clock oscillator
t
t
t
t
t
SBYSC
*7 *11
System clock source is LOCO
SBYLO
*8
130 µs
System clock source is HOCO clock oscillator
SBYHO
*9
*13
175 265 µs
35 65 µs
System clock source is PLL with HOCO
SBYPH
SBYMO
*10
*13
System clock source is MOCO clock oscillator
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RA4M3 Datasheet
2. Electrical Characteristics
Table 2.20
Parameter
Timing of recovery from low power modes (2 of 2)
Symbol
Min Typ Max Unit Test conditions
Recovery time from
Deep Software
Standby mode
DPSBYCR.DEEPCUT[1] = 0 and
DPSWCR.WTSTS[5:0] = 0x0E
t
—
0.38 0.54 ms Figure 2.15
DSBY
DPSBYCR.DEEPCUT[1] = 1 and
DPSWCR.WTSTS[5:0] = 0x19
t
—
0.55 0.73 ms
DSBY
Wait time after cancellation of Deep Software Standby mode
t
t
56
—
—
57
70
t
cyc
DSBYWT
*12
*12
*12
Recovery time from
Software Standby
mode to Snooze
mode
High-speed mode when system clock source is
HOCO (20 MHz)
μs
μs
Figure 2.16
35
SNZ
*12
High-speed mode when system clock source is
MOCO (8 MHz)
t
—
11
14
SNZ
Note 1. The recovery time is determined by the system clock source. When multiple oscillators are active, the recovery time can be
determined with the following equation:
Total recovery time = recovery time for an oscillator as the system clock source + the longest tSBYOSCWT in the active oscillators -
tSBYOSCWT for the system clock + 2 LOCO cycles (when LOCO is operating) + Subosc is oscillating and MSTPC0 = 0 (CAC
module stop))
Note 2. When the frequency of the crystal is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05) and the
greatest value of the internal clock division setting is 1.
Note 3. When the frequency of PLL is 200 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05) and the greatest
value of the internal clock division setting is 4.
Note 4. When the frequency of the external clock is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00) and
the greatest value of the internal clock division setting is 1.
Note 5. When the frequency of PLL is 200 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00) and the greatest
value of the internal clock division setting is 4.
Note 6. The Sub-clock oscillator frequency is 32.768 KHz and the greatest value of the internal clock division setting is 1.
Note 7. The LOCO frequency is 32.768 KHz and the greatest value of the internal clock division setting is 1.
Note 8. The HOCO frequency is 20 MHz and the greatest value of the internal clock division setting is 1.
Note 9. The PLL frequency is 200 MHz and the greatest value of the internal clock division setting is 4.
Note 10. The MOCO frequency is 8 MHz and the greatest value of the internal clock division setting is 1.
Note 11. In Subosc-speed mode, the sub-clock oscillator or LOCO continues oscillating in Software Standby mode.
Note 12. When the SNZCR.RXDREQEN bit is set to 0, the following time is added as the power supply recovery time: 16 µs (typical), 48 µs
(maximum).
Note 13. The recovery time can be calcurated with the equation of tSBYOSCWT + tSBYSEQ. And they can be determined with the fol-lowing
value and equation. For n, the greatest value is selected from among the internal clock division settings.
Wakeup time TYP
tSBYOSCWT
MAX
Unit
tSBYSEQ
tSBYOSCWT
tSBYSEQ
tSBYMC
(MSTS[7:0]*32 + 3) /
0.262
35 + 18 / fICLK + 4n / fMAIN
(MSTS[7:0]*32 + 14 /
0.236
62 + 18 / fICLK + 4n / fMAIN
µs
µs
tSBYPC
(MSTS[7:0]*32 + 34) /
0.262
35 + 18 / fICLK + 4n / fPLL
(MSTS[7:0]*32 + 45) /
0.236
62 + 18 / fICLK + 4n / fPLL
tSBYEX
tSBYPE
tSBYSC
tSBYLO
tSBYHO
tSBYPH
tSBYMO
10
135
0
35 + 18 / fICLK + 4n / fEXMAIN 62
62 + 18 / fICLK + 4n / fEXMAIN µs
35 + 18 / fICLK + 4n / fPLL
35 + 18 / fICLK + 4n / fSUB
35 + 18 / fICLK + 4n / fLOCO
35 + 18 / fICLK + 4n / fHOCO
35 + 18 / fICLK + 4n / fPLL
35 + 18 / fICLK + 4n / fMOCO
192
62 + 18 / fICLK + 4n / fPLL
62 + 18 / fICLK + 4n / fSUB
62 + 18 / fICLK + 4n / fLOCO
62 + 18 / fICLK + 4n / fHOCO
62 + 18 / fICLK + 4n / fPLL
µs
µs
µs
µs
µs
0
0
0
20
140
0
67
202
0
62 + 18 / fICLK + 4n / fMOCO µs
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RA4M3 Datasheet
2. Electrical Characteristics
Oscillator
(system clock)
tSBYOSCWT
tSBYSEQ
Oscillator
(not the system clock)
ICLK
IRQ
Software Standby mode
tSBYMC, tSBYEX, tSBYPC, tSBYPE,
tSBYPH, tSBYSC, tSBYHO, tSBYLO
When stabilization of the system clock oscillator is slower
Oscillator
(system clock)
tSBYSEQ
tSBYOSCWT
Oscillator
(not the system clock)
tSBYOSCWT
ICLK
IRQ
Software Standby mode
tSBYMC, tSBYEX, tSBYPC, tSBYPE,
tSBYPH, tSBYSC, tSBYHO, tSBYLO
When stabilization of an oscillator other than the system clock is slower
Figure 2.14
Software Standby mode cancellation timing
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2. Electrical Characteristics
Oscillator
IRQ
Deep Software Standby
reset
(low is valid)
Internal reset
(low is valid)
Deep Software Standby mode
tDSBY
tDSBYWT
Reset exception handling start
Figure 2.15
Deep Software Standby mode cancellation timing
Oscillator
ICLK (except DTC, SRAM)
ICLK (to DTC, SRAM)*1 PCLK
IRQ
Software Standby mode
Snooze mode
tSNZ
Note 1. When SNZCR.SNZDTCEN bit is set to 1, ICLK is supplied to DTC and SRAM.
Figure 2.16
Recovery timing from Software Standby mode to Snooze mode
2.3.5
NMI and IRQ Noise Filter
Table 2.21
Parameter
NMI and IRQ noise filter
Symbol
Min
Typ
—
Max
—
Unit
Test conditions
NMI pulse
width
t
200
ns
NMI digital filter
disabled
t
t
× 2 ≤ 200 ns
× 2 > 200 ns
NMIW
Pcyc
*1
—
—
t
× 2
Pcyc
Pcyc
200
—
—
—
—
NMI digital filter
enabled
t
t
× 3 ≤ 200 ns
× 3 > 200 ns
NMICK
NMICK
*2
t
× 3.5
NMICK
IRQ pulse
width
t
200
—
—
—
—
ns
IRQ digital filter
disabled
t
t
× 2 ≤ 200 ns
× 2 > 200 ns
IRQW
Pcyc
Pcyc
*1
t
× 2
Pcyc
200
—
—
—
—
IRQ digital filter
enabled
t
t
× 3 ≤ 200 ns
× 3 > 200 ns
IRQCK
IRQCK
*3
t
× 3.5
IRQCK
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RA4M3 Datasheet
2. Electrical Characteristics
Note:
Note:
200 ns minimum in Software Standby mode.
If the clock source is switched, add 4 clock cycles of the switched source.
Note 1. t
Note 2. t
Note 3. t
indicates the PCLKB cycle.
Pcyc
indicates the cycle of the NMI digital filter sampling clock.
indicates the cycle of the IRQi digital filter sampling clock.
NMICK
IRQCK
NMI
tNMIW
Figure 2.17
NMI interrupt input timing
IRQ
tIRQW
Figure 2.18
IRQ interrupt input timing
2.3.6
I/O Ports, POEG, GPT, AGT, and ADC12 Trigger Timing
Table 2.22
I/O ports, POEG, GPT, AGT, and ADC12 trigger timing
GPT32 Conditions:
High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
AGT Conditions:
Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter
I/O ports
POEG
Symbol
Min
1.5
3
Max
—
—
—
—
4
Unit
Test conditions
Figure 2.19
Input data pulse width
t
t
t
t
t
t
PRW
Pcyc
POEG input trigger pulse width
Input capture pulse width
Figure 2.20
POEW
GTICW
Pcyc
GPT
Single edge
1.5
2.5
—
Figure 2.21
PDcyc
Dual edge
*1
GTIOCxY output skew
(x = 0 to 3, Y = A or B)
Middle drive buffer
High drive buffer
Middle drive buffer
High drive buffer
Middle drive buffer
High drive buffer
ns
Figure 2.22
t
GTISK
—
4
GTIOCxY output skew
(x = 4 to 7, Y = A or B)
—
4
—
4
GTIOCxY output skew
(x = 0 to 7, Y = A or B)
—
6
—
6
OPS output skew
GTOUUP, GTOULO, GTOVUP,
GTOVLO, GTOWUP, GTOWLO
t
—
5
ns
ns
Figure 2.23
Figure 2.24
GTOSK
*2
ACYC
AGT
AGTIO, AGTEE input cycle
100
—
t
t
t
t
AGTIO, AGTEE input high width, low width
AGTIO, AGTO, AGTOA, AGTOB output cycle
ADC12 trigger input pulse width
, t
40
—
—
—
ns
ns
ACKWH ACKWL
62.5
1.5
ACYC2
ADC12
t
Figure 2.25
TRGW
Pcyc
Note:
t
: PCLKB cycle, t
: PCLKD cycle.
Pcyc
PDcyc
Note 1. This skew applies when the same driver I/O is used. If the I/O of the middle and high drivers is mixed, operation is not guaranteed.
Note 2. Constraints on input cycle:
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RA4M3 Datasheet
2. Electrical Characteristics
When not switching the source clock: t
× 2 < t
should be satisfied.
Pcyc
ACYC
When switching the source clock: t
× 6 < t
should be satisfied.
Pcyc
ACYC
Port
tPRW
Figure 2.19
I/O ports input timing
POEG input trigger
tPOEW
Figure 2.20
POEG input trigger timing
Input capture
tGTICW
Figure 2.21
GPT input capture timing
PCLKD
Output delay
GPT output
tGTISK
Figure 2.22
GPT output delay skew
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RA4M3 Datasheet
2. Electrical Characteristics
PCLKD
Output delay
GPT output
tGTOSK
Figure 2.23
GPT output delay skew for OPS
tACYC
tACKWL
tACKWH
AGTIO, AGTEE
(input)
tACYC2
AGTIO, AGTO,
AGTOA, AGTOB
(output)
Figure 2.24
AGT input/output timing
ADTRG0,
ADTRG1
tTRGW
Figure 2.25
ADC12 trigger input timing
2.3.7
CAC Timing
Table 2.23
Parameter
CAC
CAC timing
Symbol Min
Typ
Max
Unit
Test conditions
*1
CACREF input pulse
width
t
4.5 × t
+ 3 × t
—
—
ns
—
t
t
≤ t
> t
CACREF
cac
PBcyc
PBcyc
cac
*1
5 × t
+ 6.5 × t
—
—
ns
cac
PBcyc
PBcyc
cac
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2. Electrical Characteristics
Note:
t
: PCLKB cycle.
PBcyc
cac
Note 1. t : CAC count clock source cycle.
2.3.8
SCI Timing
Table 2.24
SCI timing (1)
Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter
Symbol Min
Max Unit Test conditions
SCI Input clock cycle
Asynchronous
t
4
—
—
0.6
5
t
Figure 2.26
Scyc
Pcyc
Clock synchronous
6
Input clock pulse width
Input clock rise time
Input clock fall time
Output clock cycle
t
t
t
t
0.4
—
—
t
SCKW
SCKr
SCKf
Scyc
Scyc
ns
ns
5
Asynchronous
6 (other than SCI1,
SCI2)
—
t
Pcyc
8 (SCI1, SCI2)
Clock synchronous
4
—
0.6
5
Output clock pulse width
Output clock rise time
Output clock fall time
Transmit data delay
t
t
t
t
0.4
—
—
—
t
SCKW
SCKr
SCKf
TXD
Scyc
ns
ns
ns
5
Clock synchronous master mode (internal
clock)
5
Figure 2.27
Clock synchronous slave mode (external
clock)
t
t
t
t
—
15
5
25
—
—
—
ns
ns
ns
ns
TXD
RXS
RXS
RXH
Receive data setup time Clock synchronous master mode (internal
clock)
Clock synchronous slave mode (external
clock)
Receive data hold time Clock synchronous
5
Note:
t
: PCLKA cycle.
Pcyc
tSCKW
tSCKr
tSCKf
SCKn
tScyc
Note:
n = 0 to 4, 9
Figure 2.26
SCK clock input/output timing
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2. Electrical Characteristics
SCKn
TXDn
RXDn
tTXD
tRXS tRXH
Note:
n = 0 to 4, 9
Figure 2.27
Table 2.25
SCI input/output timing in clock synchronous mode
SCI timing (2)
Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter
Symbol
Min
4
Max
65536
65536
0.6
0.6
5
Unit
Test conditions
Simple SPI
SCK clock cycle output (master)
SCK clock cycle input (slave)
SCK clock high pulse width
SCK clock low pulse width
SCK clock rise and fall time
Data input setup time
t
t
Figure 2.28
SPcyc
Pcyc
6
t
t
t
t
0.4
0.4
—
15
5
t
t
SPCKWH
SPcyc
SPCKWL
SPcyc
, t
ns
ns
ns
ns
SPCKr SPCKf
master
slave
—
Figure 2.29 to Figure
2.32
SU
—
Data input hold time
SS input setup time
SS input hold time
Data output delay
t
t
t
t
5
—
H
1
—
t
t
LEAD
LAG
OD
SPcyc
SPcyc
1
—
master
slave
—
—
-5
—
—
—
—
5
ns
25
ns
ns
Data output hold time
Data rise and fall time
SS input rise and fall time
Slave access time
t
t
t
t
t
—
OH
, t
Dr Df
5
ns
, t
5
ns
SSLr SSLf
3 × t
3 × t
+ 25 ns
+ 25 ns
Figure 2.32
SA
Pcyc
Slave output release time
REL
Pcyc
Note:
t
: PCLKA cycle.
Pcyc
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RA4M3 Datasheet
2. Electrical Characteristics
tSPCKr
tSPCKf
tSPCKWH
VOH
VOH
VOL
VOH
VOH
SCKn
master select
output
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKf
tSPCKWH
VIH
VIH
VIL
VIH
VIH
SCKn
slave select input
VIL
tSPCKWL
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Note:
n = 0 to 4, 9
Figure 2.28
SCI simple SPI mode clock timing
SCKn
CKPOL = 0
output
SCKn
CKPOL = 1
output
tSU
tH
MISOn
input
MSB IN
DATA
DATA
LSB IN
MSB IN
tDr, tDf
tOH
tOD
MOSIn
output
MSB OUT
LSB OUT
IDLE
MSB OUT
Note:
n = 0 to 4, 9
Figure 2.29
SCI simple SPI mode timing for master when CKPH = 1
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2. Electrical Characteristics
SCKn
CKPOL = 1
output
SCKn
CKPOL = 0
output
tSU
tH
MISOn
input
MSB IN
DATA
DATA
LSB IN
MSB IN
tOH
tOD
tDr, tDf
MOSIn
output
MSB OUT
LSB OUT
IDLE
MSB OUT
Note:
n = 0 to 4, 9
Figure 2.30
SCI simple SPI mode timing for master when CKPH = 0
tTD
SSn
input
tLEAD
tLAG
SCKn
CKPOL = 0
input
SCKn
CKPOL = 1
input
tSA
tOH
tOD
tREL
MISOn
output
MSB OUT
DATA
LSB OUT
LSB IN
MSB IN
MSB OUT
MSB IN
tSU
tH
tDr, tDf
MOSIn
input
MSB IN
DATA
Note:
n = 0 to 4, 9
Figure 2.31
SCI simple SPI mode timing for slave when CKPH = 1
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RA4M3 Datasheet
2. Electrical Characteristics
tTD
SSn
input
tLEAD
tLAG
SCKn
CKPOL = 1
input
SCKn
CKPOL = 0
input
tSA
tOH
tOD
tREL
MISOn
output
LSB OUT
(Last data)
MSB OUT
tH
DATA
LSB OUT
MSB OUT
MSB IN
tSU
tDr, tDf
MOSIn
input
MSB IN
DATA
LSB IN
Note:
n = 0 to 4, 9
Figure 2.32
Table 2.26
SCI simple SPI mode timing for slave when CKPH = 0
SCI timing (3)
Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter
Symbol
Min
—
—
0
Max
1000
300
Unit
ns
Test conditions
Simple IIC
(Standard mode)
SDA input rise time
t
t
t
t
t
Figure 2.33
Sr
SDA input fall time
ns
Sf
SDA input spike pulse removal time
Data input setup time
Data input hold time
4 × t
—
ns
SP
IICcyc
250
0
ns
SDAS
—
ns
SDAH
*1
SCL, SDA capacitive load
—
400
pF
C
b
Simple IIC
(Fast mode)
SDA input rise time
t
t
t
t
t
—
—
0
300
300
4 × t
—
ns
ns
ns
ns
ns
pF
Figure 2.33
Sr
SDA input fall time
Sf
SDA input spike pulse removal time
Data input setup time
Data input hold time
SP
SDAS
IICcyc
100
0
—
SDAH
*1
SCL, SDA capacitive load
—
400
C
b
Note:
t
: IIC internal reference clock (IICφ) cycle.
IICcyc
Note 1. C indicates the total capacity of the bus line.
b
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2. Electrical Characteristics
VIH
VIL
SDAn
tSr
tSf
tSP
SCLn
P*1
P*1
S*1
Sr*1
tSDAH
tSDAS
Test conditions:
VIH = VCC × 0.7, VIL = VCC × 0.3
VOL = 0.6 V, IOL = 6 mA
Note:
n = 0 to 4, 9
Note 1. S, P, and Sr indicate the following conditions:
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.33
SCI simple IIC mode timing
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RA4M3 Datasheet
2. Electrical Characteristics
2.3.9
SPI Timing
Table 2.27
SPI timing
Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter
SPI RSPCK clock cycle
Symbol
Min
2
Max
4096
4096
—
Unit
Test conditions
Master
Slave
t
t
t
Figure 2.34
SPcyc
Pcyc
4
RSPCK clock high
pulse width
Master
(t
– t
– t
– t
– t
) /
) /
ns
SPCKWH
SPcyc
SPCKr
SPCKf
2 – 3
Slave
0.4
0.6
—
t
SPcyc
RSPCK clock low
pulse width
Master
t
(t
ns
SPCKWL
SPcyc
SPCKr
SPCKf
2 – 3
0.4
—
—
4
Slave
0.6
5
t
SPcyc
RSPCK clock rise and Master
fall time
t
t
t
, t
ns
µs
ns
SPCKr SPCKf
Slave
1
Data input setup time Master
Slave
—
—
—
Figure 2.35 to Figure
2.40
SU
HF
5
Data input hold time
Master
0
ns
(PCLKA
division ratio
set to 1/2)
Master
t
H
t
—
Pcyc
(PCLKA
division ratio
set to a value
other than
1/2)
Slave
t
t
20
—
H
*1
SSL setup time
SSL hold time
Master
N × t
+
+
ns
N × t
- 10
LEAD
SPcyc
SPcyc
SPcyc
*1
100
Slave
4 × t
N × t
—
ns
ns
Pcyc
*2
Master
t
N × t
- 10
LAG
SPcyc
*2
100
Slave
4 × t
—
—
—
0
—
ns
ns
Pcyc
Data output delay
Master
t
t
t
t
6.3
6.3
20
OD1
OD2
OD
Slave
Data output hold time Master
Slave
—
ns
OH
0
—
Successive
Master
t
t
+ 2 × t
8 × t
+ 2 ns
TD
SPcyc
Pcyc
SPcyc
transmission delay
× t
Pcyc
Slave
4 × t
—
Pcyc
MOSI and MISO rise Output
t
t
, t
5
ns
µs
ns
µs
ns
Dr Df
and fall time
Input
—
1
SSL rise and fall time Output
Input
, t
—
5
SSLr SSLf
—
1
Slave access time
Slave output release time
t
t
—
25
25
Figure 2.39 and
Figure 2.40
SA
—
REL
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2. Electrical Characteristics
Note:
Note:
t
: PCLKA cycle.
Pcyc
Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the SPI
interface, the AC portion of the electrical characteristics is measured for each group.
Note 1. N is set to an integer from 1 to 8 by the SPCKD register.
Note 2. N is set to an integer from 1 to 8 by the SSLND register.
tSPCKr
tSPCKf
tSPCKWH
VOH
VOH
VOL
VOH
VOH
RSPCKn
master select
output
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKf
tSPCKWH
VIH
VIH
VIL
VIH
VIH
RSPCKn
slave select input
VIL
tSPCKWL
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Note:
n = A
Figure 2.34
SPI clock timing
SPI
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
tH
MISOn
input
MSB IN
DATA
DATA
LSB IN
MSB IN
tDr, tDf
tOH
tOD2
MOSIn
output
MSB OUT
LSB OUT
IDLE
MSB OUT
tOD1
Note:
n = A
Figure 2.35
SPI timing for master when CPHA = 0
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2. Electrical Characteristics
SPI
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
tHF
tHF
MISOn
input
LSB IN
MSB IN
DATA
MSB IN
tDr, tDf
tOH
tOD2
MOSIn
output
MSB OUT
DATA
LSB OUT
IDLE
MSB OUT
tOD1
Note:
n = A
Figure 2.36
SPI timing for master when CPHA = 0 and the bit rate is set to PCLKA/2
SPI
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
tH
MISOn
input
MSB IN
DATA
DATA
LSB IN
MSB IN
tOH
tOD2
tDr, tDf
MOSIn
output
MSB OUT
LSB OUT
IDLE
MSB OUT
Note:
n = A
Figure 2.37
SPI timing for master when CPHA = 1
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2. Electrical Characteristics
SPI
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
tHF
tH
MISOn
input
MSB IN
DATA
DATA
LSB IN
MSB IN
tOH
tOD2
tDr, tDf
MOSIn
output
MSB OUT
LSB OUT
IDLE
MSB OUT
Note:
n = A
Figure 2.38
RSPI timing for master when CPHA = 1 and the bit rate is set to PCLKA/2
tTD
SSLn0
input
tLEAD
tLAG
RSPCKn
CPOL = 0
input
RSPCKn
CPOL = 1
input
tSA
tOH
tOD
tREL
MISOn
output
MSB OUT
DATA
LSB OUT
LSB IN
MSB IN
MSB OUT
MSB IN
tSU
tH
tDr, tDf
MOSIn
input
MSB IN
DATA
Note:
n = A
Figure 2.39
SPI timing for slave when CPHA = 0
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2. Electrical Characteristics
tTD
SSLn0
input
tLEAD
tLAG
RSPCKn
CPOL = 0
input
RSPCKn
CPOL = 1
input
tSA
tOH
tOD
tREL
MISOn
output
LSB OUT
(Last data)
MSB OUT
tH
DATA
LSB OUT
MSB OUT
MSB IN
tSU
tDr, tDf
MOSIn
input
MSB IN
DATA
LSB IN
Note:
n = A
Figure 2.40
2.3.10
SPI timing for slave when CPHA = 1
QSPI Timing
Table 2.28
QSPI timing
Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter
Symbol
Min
Max
48
Unit
Test conditions
QSPI
QSPCK clock cycle
t
t
2
t
Figure 2.41
QScyc
QSWH
Pcyc
QSPCK clock high pulse
width
t
× 0.4
× 0.4
—
ns
ns
QScyc
QSPCK clock low pulse
width
t
t
—
QSWL
QScyc
Data input setup time
Data input hold time
QSSL setup time
t
t
t
10
0
—
ns
ns
ns
Figure 2.42
Su
—
IH
*1
*2
(N + 0.5) × t
+
+
(N + 0.5) × t
- 5
LEAD
Qscyc
Qscyc
Qscyc
*1
100
QSSL hold time
t
(N + 0.5) × t
ns
(N + 0.5) × t
- 5
LAG
Qscyc
*2
100
Data output delay
t
t
t
—
4
ns
ns
OD
OH
TD
Data output hold time
–3.3
1
—
16
Successive transmission
delay
t
QScyc
Note:
t
: PCLKA cycle.
Pcyc
Note 1. N is set to 0 or 1 in SFMSLD.
Note 2. N is set to 0 or 1 in SFMSHD.
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2. Electrical Characteristics
tQSWH
tQSWL
QSPCLK output
tQScyc
Figure 2.41
QSPI clock timing
tTD
QSSL
output
tLEAD
tLAG
QSPCLK
output
tSU
tH
QIO0-3
input
MSB IN
DATA
LSB IN
tOH
tOD
QIO0-3
output
MSB OUT
DATA
LSB OUT
IDLE
Figure 2.42
Transmit and receive timing
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RA4M3 Datasheet
2. Electrical Characteristics
2.3.11
IIC Timing
Table 2.29
IIC timing (1) (1 of 2)
(1) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_B,
SCL0_B, SDA1_B, SCL1_B.
(2) The following pins do not require setting: SCL0_A, SDA0_A, SCL1_A, SDA1_A.
(3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the
AC portion of the electrical characteristics is measured for each group.
Test
Parameter
Symbol
Min
Max
—
Unit conditions
IIC
SCL input cycle time
SCL input high pulse width
SCL input low pulse width
SCL, SDA rise time
t
t
t
t
t
t
6 (12) × t
+ 1300
IICcyc
ns
ns
ns
ns
ns
ns
Figure 2.43
SCL
SCLH
SCLL
Sr
(Standard mode,
SMBus)
ICFER.FMPE = 0
3 (6) × t
+ 300
+ 300
—
IICcyc
IICcyc
3 (6) × t
—
—
—
0
1000
300
1 (4) × t
SCL, SDA fall time
Sf
SCL, SDA input spike pulse
removal time
SP
IICcyc
SDA input bus free time when
wakeup function is disabled
t
t
t
t
t
3 (6) × t
+ 300
—
—
—
—
—
ns
ns
ns
ns
ns
BUF
BUF
IICcyc
SDA input bus free time when
wakeup function is enabled
3 (6) × t
300
+ 4 × t
+
IICcyc
Pcyc
START condition input hold time
when wakeup function is disabled
t
+ 300
IICcyc
STAH
STAH
STAS
START condition input hold time
when wakeup function is enabled
1 (5) × t
1000
+ t
+ 300
Pcyc
IICcyc
Repeated START condition input
setup time
STOP condition input setup time
Data input setup time
t
t
t
1000
—
ns
ns
ns
pF
STOS
SDAS
SDAH
t
+ 50
—
IICcyc
Data input hold time
0
—
SCL, SDA capacitive load
C
—
400
b
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RA4M3 Datasheet
2. Electrical Characteristics
Table 2.29
IIC timing (1) (2 of 2)
(1) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_B,
SCL0_B, SDA1_B, SCL1_B.
(2) The following pins do not require setting: SCL0_A, SDA0_A, SCL1_A, SDA1_A.
(3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the
AC portion of the electrical characteristics is measured for each group.
Test
Parameter
Symbol
Min
Max
—
Unit conditions
IIC
SCL input cycle time
t
t
t
t
6 (12) × t
+ 600
IICcyc
ns
ns
ns
ns
Figure 2.43
SCL
SCLH
SCLL
Sr
(Fast mode)
SCL input high pulse width
SCL input low pulse width
SCL, SDA rise time
3 (6) × t
3 (6) × t
+ 300
+ 300
—
IICcyc
IICcyc
—
20 × (external pullup
voltage/5.5V)
300
*1
SCL, SDA fall time
t
20 × (external pullup
voltage/5.5V)
300
ns
Sf
*1
SCL, SDA input spike pulse
removal time
t
t
t
t
t
t
0
1 (4) × t
ns
ns
ns
ns
ns
ns
SP
IICcyc
SDA input bus free time when
wakeup function is disabled
3 (6) × t
+ 300
—
—
—
—
—
BUF
BUF
IICcyc
SDA input bus free time when
wakeup function is enabled
3 (6) × t
300
+ 4 × t
+
IICcyc
Pcyc
START condition input hold time
when wakeup function is disabled
t
+ 300
IICcyc
STAH
STAH
STAS
START condition input hold time
when wakeup function is enabled
1 (5) × t
300
+ t
+ 300
Pcyc
IICcyc
Repeated START condition input
setup time
STOP condition input setup time
Data input setup time
t
t
t
300
—
ns
ns
ns
pF
STOS
SDAS
SDAH
t
+ 50
—
IICcyc
Data input hold time
0
—
SCL, SDA capacitive load
C
—
400
b
Note:
Note:
Note:
t
: IIC internal reference clock (IICφ) cycle, t
: PCLKB cycle.
Pcyc
IICcyc
Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.
Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the IIC
interface, the AC portion of the electrical characteristics is measured for each group.
Note 1. Only supported for SCL0_A, SDA0_A, SCL1_A, and SDA1_A.
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2. Electrical Characteristics
Table 2.30
IIC timing (2)
Setting of the SCL0_A, SDA0_A pins is not required with the Port Drive Capability bit in the PmnPFS register.
Parameter
Symbol Min
Max
Unit Test conditions
IIC
SCL input cycle time
t
6 (12) × t
240
+
IICcyc
—
ns
Figure 2.43
SCL
(Fast-mode+)
ICFER.FMPE = 1
SCL input high pulse width
SCL input low pulse width
SCL, SDA rise time
t
t
t
t
3 (6) × t
3 (6) × t
—
+ 120
+ 120
—
ns
ns
ns
ns
SCLH
SCLL
Sr
IICcyc
—
IICcyc
120
120
SCL, SDA fall time
20 × (external
pullup voltage/
5.5V)
Sf
SCL, SDA input spike pulse
removal time
t
t
t
0
1 (4) × tIICcyc
ns
ns
ns
SP
SDA input bus free time when
wakeup function is disabled
3 (6) × t
+ 120
+ 4 ×
—
—
BUF
BUF
IICcyc
IICcyc
SDA input bus free time when
wakeup function is enabled
3 (6) × t
t
t
+ 120
Pcyc
Start condition input hold time
when wakeup function is disabled
t
t
+ 120
—
—
ns
ns
STAH
STAH
IICcyc
START condition input hold time
when wakeup function is enabled
1 (5) × t
+
IICcyc
t
+ 120
Pcyc
Restart condition input setup time
Stop condition input setup time
Data input setup time
t
t
t
t
120
120
—
ns
ns
ns
ns
pF
STAS
STOS
SDAS
—
t
+ 30
—
IICcyc
Data input hold time
0
—
SDAH
*1
SCL, SDA capacitive load
—
550
C
b
Note:
Note:
t
: IIC internal reference clock (IICφ) cycle, t
: PCLKB cycle.
Pcyc
IICcyc
Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.
Note 1. Cb indicates the total capacity of the bus line.
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2. Electrical Characteristics
VIH
VIL
SDAn
tBUF
tSCLH
tSTAS
tSTOS
tSTAH
tSP
SCLn
P*1
P*1
S*1
tSf
Sr*1
tSCLL
tSr
tSDAS
tSCL
tSDAH
Note 1. S, P, and Sr indicate the following conditions:
S: Start condition
P: Stop condition
Sr: Restart condition
I2C bus interface input/output timing
SSIE Timing
Figure 2.43
2.3.12
Table 2.31
SSIE timing
(1) High drive output is selected with the Port Drive Capability bit in the PmnPFS register.
(2) Use pins that have a letter appended to their names, for instance “_A” or “_B” to indicate group membership. For the SSIE interface, the
AC portion of the electrical characteristics is measured for each group.
Target specification
Parameter
Symbol
Min.
80
Max.
—
Unit
ns
Comments
SSIBCK0
Cycle
Master
Slave
t
t
t
Figure 2.44
O
80
—
ns
I
High level/ low Master
level
/t
0.35
0.35
—
—
t
t
t
t
HC LC
O
I
Slave
—
Rising time/
falling time
Master
Slave
t
/t
0.15
0.15
—
/ t
/ t
RC FC
O
O
I
—
I
SSILRCK0/
SSIFS0,
SSITXD0,
SSIRXD0,
SSIDATA0
Input set up
time
Master
Slave
t
t
t
12
ns
ns
ns
ns
ns
ns
Figure 2.46,
Figure 2.47
SR
12
—
Input hold time Master
Slave
8
—
HR
15
—
Output delay
time
Master
Slave
-10
0
5
DTR
20
Figure 2.46,
Figure 2.47
*1
Output delay
time from
Slave
t
—
20
ns
Figure 2.48
DTRW
SSILRCK0/
SSIFS0 change
GTIOC2A,
AUDIO_CLK
Cycle
t
t
20
—
ns
Figure 2.45
EXcyc
High level/ low level
/t
0.4
0.6
t
EXcyc
EXL EXH
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RA4M3 Datasheet
2. Electrical Characteristics
Note 1. For slave-mode transmission, SSIE has a path, through which the signal input from the SSILRCK0/SSIFS0 pin is used to generate
transmit data, and the transmit data is logically output to the SSITXD0 or SSIDATA0 pin.
tHC
tRC
tFC
tLC
SSIBCK0
tO, tI
Figure 2.44
SSIE clock input/output timing
tEXcyc
tEXH
tEXL
GTIOC2A,
AUDIO_CLK
(input)
1/2 VCC
tEXf
tEXr
Figure 2.45
Clock input timing
SSIBCK0
(Input or Output)
SSILRCK0/SSIFS0 (input),
SSIRXD0,
SSIDATA0 (input)
tSR
tHR
SSILRCK0/SSIFS0 (output),
SSITXD0,
SSIDATA0 (output)
tDTR
Figure 2.46
SSIE data transmit and receive timing when SSICR.BCKP = 0
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2. Electrical Characteristics
SSIBCK0
(Input or Output)
SSILRCK0/SSIFS0 (input),
SSIRXD0,
SSIDATA0 (input)
tSR
tHR
SSILRCK0/SSIFS0 (output),
SSITXD0,
SSIDATA0 (output)
tDTR
Figure 2.47
SSIE data transmit and receive timing when SSICR.BCKP = 1
SSILRCK0/SSIFS0 (input)
SSITXD0,
SSIDATA0 (output)
tDTRW
MSB bit output delay after SSILRCK0/SSIFS0 change for slave
transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0] in SSICR.
Figure 2.48
2.3.13
SSIE data output delay after SSILRCK0/SSIFS0 change
SD/MMC Host Interface Timing
Table 2.32
SD/MMC Host Interface signal timing
Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Clock duty ratio is 50%.
Parameter
Symbol
Min
20
Max
—
—
—
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Test conditions
SDCLK clock cycle
T
T
T
T
T
T
T
T
Figure 2.49
SDCYC
SDWH
SDWL
SDLH
SDCLK clock high pulse width
SDCLK clock low pulse width
SDCLK clock rise time
6.5
6.5
—
SDCLK clock fall time
—
3
SDHL
SDCMD/SDDAT output data delay
SDCMD/SDDAT input data setup
SDCMD/SDDAT input data hold
–7
4
SDODLY
SDIS
4.5
1.5
—
—
SDIH
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RA4M3 Datasheet
2. Electrical Characteristics
Note:
Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the SD/MMC
Host interface, the AC portion of the electrical characteristics is measured for each group.
TSDCYC
TSDWL
TSDWH
SDnCLK
(output)
TSDLH
TSDHL
TSDODLY(max)
TSDODLY(min)
SDnCMD/SDnDATm
(output)
TSDIS
TSDIH
SDnCMD/SDnDATm
(input)
n = 0, 1, m = 0 to 7
Figure 2.49
SD/MMC Host Interface signal timing
2.4
USB Characteristics
USBFS Timing
2.4.1
Table 2.33
USBFS low-speed characteristics for host only (USB_DP and USB_DM pin characteristics)
Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, USBCLK = 48 MHz
Parameter
Symbol
Min
2.0
—
Typ
—
—
—
—
—
—
—
—
—
—
—
Max
—
Unit
V
Test conditions
Input
characteristics
Input high voltage
Input low voltage
V
V
V
V
V
V
V
—
IH
0.8
—
V
—
IL
Differential input sensitivity
Differential common-mode range
Output high voltage
Output low voltage
Cross-over voltage
Rise time
0.2
0.8
2.8
0.0
1.3
75
V
| USB_DP - USB_DM |
—
DI
2.5
3.6
0.3
2.0
300
300
125
V
CM
OH
OL
CRS
Output
characteristics
V
I
I
= –200 µA
= 2 mA
OH
OL
V
V
Figure 2.50
t
t
t
ns
ns
%
LR
LF
Fall time
75
Rise/fall time ratio
/ t
80
t / t
LR LF
LR LF
Pull-up and
pull-down
USB_DP and USB_DM pull-down
resistance in host controller mode
R
14.25
24.80 kΩ
—
pd
characteristics
90%
90%
VCRS
USB_DP,
USB_DM
10%
tLR
10%
tLF
Figure 2.50
USB_DP and USB_DM output timing in low-speed mode
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RA4M3 Datasheet
2. Electrical Characteristics
Observation
point
USB_DP
USB_DM
200 pF to
600 pF
3.6 V
27
1.5 K
200 pF to
600 pF
Figure 2.51
Table 2.34
Test circuit in low-speed mode
USBFS full-speed characteristics (USB_DP and USB_DM pin characteristics)
Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, USBCLK = 48 MHz
Parameter
Symbol
Min
2.0
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
—
Unit
V
Test conditions
Input
characteristics
Input high voltage
Input low voltage
V
V
V
V
V
V
V
—
IH
0.8
—
V
—
IL
Differential input sensitivity
Differential common-mode range
Output high voltage
Output low voltage
Cross-over voltage
Rise time
0.2
0.8
2.8
0.0
1.3
4
V
| USB_DP - USB_DM |
—
DI
2.5
3.6
0.3
2.0
20
V
CM
OH
OL
CRS
Output
characteristics
V
I
I
= –200 µA
= 2 mA
OH
OL
V
V
Figure 2.52
t
t
t
ns
ns
%
Ω
LR
LF
Fall time
4
20
Rise/fall time ratio
Output resistance
/ t
90
111.11
44
t / t
FR FF
LR LF
Z
28
USBFS: Rs = 27 Ω included
During idle state
DRV
Pull-up and
pull-down
characteristics
DM pull-up resistance in device controller
mode
R
0.900
1.425
1.575 kΩ
3.090 kΩ
pu
pd
During transmission and
reception
USB_DP and USB_DM pull-down
resistance in host controller mode
R
14.25
—
24.80 kΩ
—
90%
90%
VCRS
USB_DP,
USB_DM
10%
tFR
10%
tFF
Figure 2.52
USB_DP and USB_DM output timing in full-speed mode
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RA4M3 Datasheet
2. Electrical Characteristics
Observation
point
USB_DP
USB_DM
50 pF
50 pF
27
Figure 2.53
Table 2.35
Test circuit in full-speed mode
USBFS characteristics (USB_DP and USB_DM pin characteristics)
Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, USBCLK = 48 MHz
Parameter
Symbol
Min
25
Typ
—
Max
175
175
13
Unit
µA
µA
µA
V
Test conditions
Battery Charging D+ sink current
Specification
I
I
I
—
DP_SINK
DM_SINK
DP_SRC
D- sink current
25
—
—
DCD source current
Data detection voltage
D+ source voltage
D- source voltage
7
—
—
V
V
V
0.25
0.5
0.5
—
0.4
0.7
0.7
—
DAT_REF
DP_SRC
DM_SRC
—
V
Outout current = 250 µA
Outout current = 250 µA
—
V
2.5
ADC12 Characteristics
Table 2.36
A/D conversion characteristics for unit 0 (1 of 2)
Conditions: PCLKC = 1 to 50 MHz
Parameter
Min
1
Typ Max Unit Test conditions
Frequency
—
—
50
30
MHz —
Analog input capacitance
Quantization error
Resolution
—
—
—
pF
—
—
—
±0.5 —
LSB
Bits
μs
—
—
12
—
*1
*2
*2
High-precision high-speed
channels
(AN000 to AN005)
Permissible signal
source impedance
Max. = 1 kΩ
Sampling in 13
states
Conversion time
0.52 (0.26)
(operation at PCLKC =
50 MHz)
Max. = 400 Ω
—
—
μs
Sampling in 7 states
VCC = AVCC0 = 3.0
to 3.6 V
0.40 (0.14)
3.0 V ≤ VREFH0 ≤
AVCC0
Offset error
—
—
—
—
—
±1.0 ±2.5 LSB
±1.0 ±2.5 LSB
±2.0 ±4.5 LSB
±0.5 ±1.5 LSB
±1.0 ±2.5 LSB
—
—
—
—
—
Full-scale error
Absolute accuracy
DNL differential nonlinearity error
INL integral nonlinearity error
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RA4M3 Datasheet
2. Electrical Characteristics
Table 2.36
A/D conversion characteristics for unit 0 (2 of 2)
Conditions: PCLKC = 1 to 50 MHz
Parameter
Min
Typ Max Unit Test conditions
*1
*2
High-precision normal-speed
channels
(AN006 to AN009, AN012,
AN013)
Permissible signal
source impedance
Max. = 1 kΩ
—
—
μs
Sampling in 33
states
Conversion time
0.92 (0.66)
(Operation at PCLKC =
50 MHz)
Offset error
—
—
—
—
—
±1.0 ±2.5 LSB
±1.0 ±2.5 LSB
±2.0 ±4.5 LSB
±0.5 ±1.5 LSB
±1.0 ±2.5 LSB
—
—
—
—
—
Full-scale error
Absolute accuracy
DNL differential nonlinearity error
INL integral nonlinearity error
Note:
Note:
These specification values apply when there is no access to the external memory during A/D conversion. If access occurs during
A/D conversion, values might not fall within the indicated ranges.
The use of PORT0 as digital outputs is not allowed when the 12-Bit A/D converter is used.
The characteristics apply when AVCC0, AVSS0, VREFH0/VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage are
stable.
When both unit0 and unit1 are used, do not select the following analog input combinations at the same time except the interleave
function. If selected, values might not fall within the indicated ranges.
●
●
●
AN100 and AN000 or AN001 or AN002
AN101 and AN000 or AN001 or AN002 or AN003
AN102 and AN000 or AN001 or AN002 or AN003 or AN004
Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test
conditions.
Note 2. Values in parentheses indicate the sampling time.
Table 2.37
A/D conversion characteristics for unit 1
Conditions: PCLKC = 1 to 50 MHz
Parameter
Min
1
Typ Max Unit Test conditions
Frequency
—
—
50
30
MHz —
Analog input capacitance
Quantization error
Resolution
—
—
—
pF
—
—
—
±0.5 —
LSB
Bits
μs
—
—
12
—
*1
*2
*2
High-precision high-speed
channels
(AN100 to AN102)
Permissible signal
source impedance
Max. = 1 kΩ
Sampling in 13
states
Conversion time
0.52 (0.26)
(Operation at PCLKC =
50 MHz)
Max. = 400 Ω
—
—
μs
Sampling in 7 states
VCC = AVCC0 = 3.0
to 3.6 V
0.40 (0.14)
3.0 V ≤ VREFH ≤
AVCC0
Offset error
—
—
—
—
—
±1.0 ±2.5 LSB
±1.0 ±2.5 LSB
±2.0 ±4.5 LSB
±0.5 ±1.5 LSB
±1.0 ±2.5 LSB
—
—
—
—
—
Full-scale error
Absolute accuracy
DNL differential nonlinearity error
INL integral nonlinearity error
*1
*2
Normal-precision normal-
speed channels
(AN116 to AN122)
Permissible signal
source impedance
Max. = 1 kΩ
—
—
μs
Sampling in 33
states
Conversion time
(Operation at PCLKC =
50 MHz)
0.92 (0.66)
Offset error
—
—
—
—
—
±1.0 ±5.5 LSB
±1.0 ±5.5 LSB
±2.0 ±7.5 LSB
±0.5 ±4.5 LSB
±1.0 ±5.5 LSB
—
—
—
—
—
Full-scale error
Absolute accuracy
DNL differential nonlinearity error
INL integral nonlinearity error
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2. Electrical Characteristics
Note:
These specification values apply when there is no access to the external memory during A/D conversion. If access occurs during
A/D conversion, values might not fall within the indicated ranges.
The use of PORT0 as digital outputs is not allowed when the 12-Bit A/D converter is used.
The characteristics apply when AVCC0, AVSS0, VREFH0/VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage are
stable.
Note:
When both unit0 and unit1 are used, do not select the following analog input combinations at the same time except the interleave
function. If selected, values might not fall within the indicated ranges.
●
●
●
AN100 and AN000 or AN001 or AN002
AN101 and AN000 or AN001 or AN002 or AN003
AN102 and AN000 or AN001 or AN002 or AN003 or AN004
Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test
conditions.
Note 2. Values in parentheses indicate the sampling time.
Table 2.38
A/D conversion characteristics for interleaving
Conditions: PCLKC = 1 to 50 MHz
Parameter
Min Typ Max Unit Test conditions
Frequency
1
—
—
50
30
MHz —
Analog input capacitance
Quantization error
Resolution
—
—
—
pF
—
—
—
±0.5 —
LSB
Bits
µs
—
12
—
*1
High-precision high-speed channels
(AN000 & AN100, AN001 & AN101, AN002
& AN102))
Max. = 400 Ω 0.22 —
Sampling in 9 states
VCC = AVCC0 = 3.0 to
3.6 V
Conversion time
(operation at PCLKC = 50
MHz)
3.0 V ≤ VREFH0 ≤
AVCC0
Offset error
—
—
—
—
—
±1.0 ±2.5 LSB
±1.0 ±2.5 LSB
±2.0 ±4.5 LSB
±0.5 ±3.5 LSB
±1.0 ±3.5 LSB
—
—
—
—
—
Full-scale error
Absolute accuracy
DNL differential nonlinearity error
INL integral nonlinearity error
Note:
These specification values apply when there is no access to the external memory during A/D conversion. If access occurs during
A/D conversion, values might not fall within the indicated ranges.
The use of PORT0 as digital outputs is not allowed when the 12-Bit A/D converter is used.
The characteristics apply when AVCC0, AVSS0, VREFH0/VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage are
stable.
Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test
conditions.
Table 2.39
A/D internal reference voltage characteristics
Parameter
Min
1.13
4.15
Typ
1.18
—
Max
1.23
—
Unit
V
Test conditions
A/D internal reference voltage
Sampling time
—
—
µs
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2. Electrical Characteristics
0xFFF
Full-scale error
Integral nonlinearity
error (INL)
A/D converter
output code
Ideal line of actual A/D
conversion characteristic
Actual A/D conversion
characteristic
Ideal A/D conversion
characteristic
Differential nonlinearity error (DNL)
1-LSB width for ideal A/D
conversion characteristic
Differential nonlinearity error (DNL)
1-LSB width for ideal A/D
conversion characteristic
Absolute accuracy
Offset error
0x000
0
Analog input voltage
VREFH0
(full-scale)
Figure 2.54
Illustration of ADC12 characteristic terms
Absolute accuracy
Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the
actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of the analog
input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D
conversion characteristics, is used as an analog input voltage. For example, if 12-bit resolution is used and the reference
voltage VREFH0 = 3.072 V, then the 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, and 1.5 mV are used as the
analog input voltages. If the analog input voltage is 6 mV, an absolute accuracy of ±5 LSB means that the actual A/D
conversion result is in the range of 0x003 to 0x00D, though an output code of 0x008 can be expected from the theoretical
A/D conversion characteristics.
Integral nonlinearity error (INL)
Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale errors
are zeroed, and the actual output code.
Differential nonlinearity error (DNL)
Differential nonlinearity error is the difference between the 1-LSB width based on the ideal A/D conversion characteristics
and the width of the actual output code.
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2. Electrical Characteristics
Offset error
Offset error is the difference between the transition point of the ideal first output code and the actual first output code.
Full-scale error
Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code.
2.6
DAC12 Characteristics
Table 2.40
D/A conversion characteristics
Parameter
Min
Typ
Max
Unit
Test conditions
Resolution
—
—
12
Bits
—
Without output amplifier
Absolute accuracy
INL
—
—
—
—
—
0
—
±24
±8.0
±2.0
—
LSB
LSB
LSB
kΩ
Resistive load 2 MΩ
±2.0
±1.0
8.5
—
Resistive load 2 MΩ
DNL
—
Output impedance
Conversion time
Output voltage range
With output amplifier
INL
—
3
µs
Resistive load 2 MΩ, Capacitive load 20 pF
—
—
VREFH
V
—
—
—
5
±2.0
±1.0
—
±4.0
LSB
LSB
µs
—
—
—
—
—
—
DNL
±2.0
Conversion time
Resistive load
Capacitive load
Output voltage range
4.0
—
—
kΩ
pF
—
0.2
—
50
—
VREFH – 0.2
V
2.7
TSN Characteristics
Table 2.41
TSN characteristics
Parameter
Symbol
Min
—
Typ
± 1.0
4.0
Max
Unit
°C
Test conditions
Relative accuracy
Temperature slope
Output voltage (at 25 °C)
Temperature sensor start time
Sampling time
—
—
—
—
—
—
30
—
—
—
—
—
—
—
mV/°C
V
—
1.24
—
t
—
µs
START
—
4.15
—
µs
2.8
OSC Stop Detect Characteristics
Table 2.42
Parameter
Oscillation stop detection circuit characteristics
Symbol
Min
Typ
Max
Unit
ms
Test conditions
Detection time
t
—
—
1
Figure 2.55
dr
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2. Electrical Characteristics
Main clock
tdr
OSTDSR.OSTDF
MOCO clock
ICLK
Figure 2.55
Oscillation stop detection timing
2.9
POR and LVD Characteristics
Table 2.43
Power-on reset circuit and voltage detection circuit characteristics (1)
Un
Parameter
Symbol Min
Typ
2.6
Max it
Test conditions
Voltage detection Power-on reset
level
DPSBYCR.DEEPCUT[1:0] = 00b or
01b.
V
2.5
2.7
V
Figure 2.56
POR
(POR)
DPSBYCR.DEEPCUT[1:0] = 11b.
1.8
2.25 2.7
Voltage detection circuit (LVD0)
Voltage detection circuit (LVD1)
Voltage detection circuit (LVD2)
V
V
V
V
V
V
V
V
V
2.84 2.94 3.04
2.77 2.87 2.97
2.70 2.80 2.90
2.89 2.99 3.09
2.82 2.92 3.02
2.75 2.85 2.95
2.89 2.99 3.09
2.82 2.92 3.02
2.75 2.85 2.95
Figure 2.57
Figure 2.58
Figure 2.59
det0_1
det0_2
det0_3
det1_1
det1_2
det1_3
det2_1
det2_2
det2_3
POR
Internal reset time Power-on reset time
LVD0 reset time
t
t
t
t
t
—
4.5
—
—
—
—
—
ms Figure 2.56
Figure 2.57
—
0.51
0.38
0.38
—
LVD0
LVD1 reset time
—
Figure 2.58
LVD1
LVD2 reset time
—
Figure 2.59
LVD2
*1
200
µs Figure 2.56,
Figure 2.57
Minimum VCC down time
VOFF
Response delay
t
t
—
—
200
µs Figure 2.57 to
Figure 2.59
det
LVD operation stabilization time (after LVD is enabled)
Hysteresis width (LVD1 and LVD2)
—
—
—
10
—
µs Figure 2.58,
d(E-A)
Figure 2.59
V
70
m
LVH
V
Note 1. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels V
, V
POR
,
det0
V
, and V
det1
for POR and LVD.
det2
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2. Electrical Characteristics
tVOFF
VPOR
VCC
Internal reset signal
(active-low)
tdet
tPOR
tdet
tdet tPOR
Figure 2.56
Power-on reset timing
tVOFF
VLVH
VCC
Vdet0
Internal reset signal
(active-low)
tdet
tdet
tLVD0
Figure 2.57
Voltage detection circuit timing (Vdet0)
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2. Electrical Characteristics
tVOFF
VLVH
VCC
Vdet1
LVCMPCR.LVD1E
Td(E-A)
LVD1
Comparator output
LVD1CR0.CMPE
LVD1SR.MON
Internal reset signal
(active-low)
When LVD1CR0.RN = 0
tdet
tLVD1
tdet
When LVD1CR0.RN = 1
tLVD1
Figure 2.58
Voltage detection circuit timing (Vdet1)
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2. Electrical Characteristics
tVOFF
VLVH
VCC
Vdet2
LVCMPCR.LVD2E
Td(E-A)
LVD2
Comparator output
LVD2CR0.CMPE
LVD2SR.MON
Internal reset signal
(active-low)
When LVD2CR0.RN = 0
tdet
tdet
tLVD2
When LVD2CR0.RN = 1
tLVD2
Figure 2.59
2.10
Voltage detection circuit timing (Vdet2)
VBATT Characteristics
Table 2.44
Battery backup function characteristics
Conditions: VCC = AVCC0 = VCC_USB = 2.7 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, VBATT = 1.8 to 3.6 V
Parameter
Symbol
Min
2.50
2.70
Typ
2.60
—
Max
2.70
—
Unit
V
Test conditions
Voltage level for switching to battery backup
V
Figure 2.60
DETBATT
BATTSW
Lower-limit VBATT voltage for power supply
switching caused by VCC voltage drop
V
V
VCC-off period for starting power supply
switching
t
200
—
—
µs
VOFFBATT
VBATT low voltage detection level
Minimum VBATT down time
Response delay
V
1.8
200
—
1.9
—
—
—
2.0
—
V
Figure 2.61
battldet
BATTOFF
BATTdet
d(E-A)
t
t
t
µs
µs
µs
200
20
VBATT monitor operation stabilization time
(after VBATTMNSELR.VBATTMNSEL is
changed to 1)
—
VBATT current increase (when
VBATTMNSELR.VBATTMNSEL is 1 compared
to the case that VBATTMNSELR.VBATTMNSEL
is 0)
I
—
140
350
nA
VBATTSEL
Note:
The VCC-off period for starting power supply switching indicates the period in which VCC is below the minimum value of the voltage
level for switching to battery backup (V
).
DETBATT
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2. Electrical Characteristics
tVOFFBATT
VDETBATT
VCC
VBATT
VBATTSW
Backup power
area
VCC supply
VBATT supply
VCC supply
Figure 2.60
Battery backup function characteristics
tBATTOFF
Vbattldet
VBATT
td(E-A)
VBATTMON
tBATTdet
tBATTdet
VBATTMNSEL
Figure 2.61
Battery backup function characteristics
2.11
CTSU Characteristics
Table 2.45
CTSU characteristics
Parameter
Symbol
Min
9
Typ
10
—
Max
11
Unit
nF
Test conditions
External capacitance connected to TSCAP pin
TS pin capacitive load
C
C
—
—
tscap
base
IoH
—
—
50
pF
Permissible output high current
Σ
—
-40
mA
When the mutual capacitance
method is applied
2.12
Flash Memory Characteristics
2.12.1
Code Flash Memory Characteristics
Table 2.46
Code flash memory characteristics (1 of 2)
Conditions: Program or erase: FCLK = 4 to 50 MHz
Read: FCLK ≤ 50 MHz
FCLK = 4 MHz
20 MHz ≤ FCLK ≤ 50 MHz
Test
conditions
*6
*6
Parameter
Symbol Min
Typ
Max Min
Typ
0.34
22
Max
6.0
80
Unit
ms
Programming time
≤ 100 times
128-byte
8-KB
t
t
t
—
—
—
0.75 13.2
—
—
—
P128
N
PEC
49
176
704
ms
P8K
32-KB
194
88
320
ms
P32K
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2. Electrical Characteristics
Table 2.46
Code flash memory characteristics (2 of 2)
Conditions: Program or erase: FCLK = 4 to 50 MHz
Read: FCLK ≤ 50 MHz
FCLK = 4 MHz
20 MHz ≤ FCLK ≤ 50 MHz
Test
conditions
*6
*6
Parameter
Symbol Min
Typ
Max Min
Typ
Max
7.2
96
Unit
ms
ms
ms
ms
ms
ms
ms
Times
µs
Programming time
> 100 times
128-byte
8-KB
t
t
t
t
t
t
t
—
—
—
—
—
—
—
0.91 15.8
—
—
—
—
—
—
0.41
27
P128
N
PEC
60
212
848
216
864
260
P8K
32-KB
8-KB
234
78
106
43
384
120
480
144
576
—
P32K
E8K
Erasure time
≤ 100 times
N
PEC
32-KB
8-KB
283
94
157
52
E32K
E8K
Erasure time
> 100 times
N
PEC
32-KB
341
—
1040 —
189
—
E32K
*4
*1
*1
N
—
Reprogramming/erasure cycle
10000
—
10000
—
PEC
Suspend delay during programming
Programming resume time
t
t
t
—
264
110
216
—
120
50
SPD
—
—
—
—
µs
PRT
First suspend delay during erasure in suspend
priority mode
—
—
—
—
120
µs
SESD1
Second suspend delay during erasure in suspend
priority mode
t
t
t
—
—
—
—
—
—
1.7
1.7
1.7
—
—
—
—
—
—
1.7
1.7
1.7
ms
ms
ms
SESD2
SEED
Suspend delay during erasure in erasure priority
mode
First erasing resume time during erasure in suspend
REST1
*5
priority mode
Second erasing resume time during erasure in
suspend priority mode
t
t
—
—
—
—
—
144
144
—
—
—
—
—
80
80
µs
µs
REST2
REET
Erasing resume time during erasure in erasure
priority mode
Forced stop command
t
t
—
—
32
—
—
—
20
—
µs
FD
*2
*2 *3
*2 *3
Years
Data hold time
10
10
DRP
Note 1. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1 to
the minimum value.
Note 2. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range.
Note 3. This result is obtained from reliability testing.
Note 4. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 10,000),
erasing can be performed n times for each block. For example, when 128-byte programming is performed 64 times for different
addresses in 8-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming
the same address several times as one erasure is not enabled. Overwriting is prohibited.
Note 5. Time for resumption includes time for reapplying the erasing pulse (up to one full pulse) that was cut off at the time of suspension.
Note 6. The reference value at VCC = 3.3V and room temperature.
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2. Electrical Characteristics
• Suspension during programming
FACI command
Program
Ready
Suspend
Resume
tSPD
FSTATR.FRDY
Not Ready
Ready
tPRT
Programming pulse
Programming
Programming
• Suspension during erasure in suspend priority mode
FACI command
Erase
Suspend
Suspend
Resume
Resume
tSESD1
tSESD2
FSTATR.FRDY
Erasure pulse
Not Ready
Ready
Not Ready
Ready
Not Ready
Erasing
Ready
tREST1
tREST2
Erasing
Erasing
• Suspension during erasure in erasure priority mode
FACI command
FSTATR.FRDY
Erasure pulse
Erase
Suspend
Not Ready
Erasing
Resume
tSEED
Not Ready
Ready
Ready
tREET
Erasing
• Forced Stop
Forced Stop
FACI command
tFD
FSTATR.FRDY
Not Ready
Ready
Figure 2.62
Suspension and forced stop timing for flash memory programming and erasure
2.12.2
Data Flash Memory Characteristics
Table 2.47
Data flash memory characteristics (1 of 2)
Conditions: Program or erase: FCLK = 4 to 50 MHz
Read: FCLK ≤ 50 MHz
FCLK = 4 MHz
20 MHz ≤ FCLK ≤ 50 MHz
Test
*6
*6
Parameter
Symbol Min
Typ
Max Min
Typ
Max Unit conditions
Programming time
Erasure time
4-byte
8-byte
t
t
t
t
—
—
—
—
—
—
—
0.36 3.8
0.38 4.0
0.42 4.5
—
—
—
—
—
—
—
0.16
0.17
0.19
1.7
2.6
4.9
—
1.7
1.8
2.0
10
15
28
30
—
ms
DP4
DP8
16-byte
64-byte
DP16
DE64
DE128
DE256
DBC4
3.1
4.7
8.9
—
18
27
50
84
—
ms
128-byte t
256-byte t
Blank check time
4-byte
t
µs
—
µs
*1
*2
*2
N
—
—
Reprogramming/erasure cycle
125000
—
125000
—
DPEC
DSPD
Suspend delay during programming
4-byte
8-byte
16-byte
t
—
—
—
—
—
—
—
264
264
264
110
216
216
216
—
—
—
—
—
—
—
120
120
120
50
—
—
—
—
Programming resume time
t
t
—
—
µs
µs
DPRT
First suspend delay during erasure in
suspend priority mode
64-byte
—
—
120
120
120
DSESD1
128-byte
256-byte
—
—
—
—
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2. Electrical Characteristics
Table 2.47
Data flash memory characteristics (2 of 2)
Conditions: Program or erase: FCLK = 4 to 50 MHz
Read: FCLK ≤ 50 MHz
FCLK = 4 MHz
20 MHz ≤ FCLK ≤ 50 MHz
Test
*6
*6
Parameter
Symbol Min
Typ
—
—
—
—
—
—
—
Max Min
Typ
—
—
—
—
—
—
—
Max Unit conditions
Second suspend delay during erasure in
suspend priority mode
64-byte
t
t
t
—
—
—
—
—
—
—
300
390
570
300
390
570
300
—
—
—
—
—
—
—
300
390
570
300
390
570
300
µs
µs
µs
DSESD2
128-byte
256-byte
64-byte
Suspend delay during erasing in erasure
priority mode
DSEED
128-byte
256-byte
First erasing resume time during erasure in suspend
DREST1
*5
priority mode
Second erasing resume time during erasure in
suspend priority mode
t
t
—
—
—
—
126
126
—
—
—
—
70
70
µs
µs
DREST2
DREET
Erasing resume time during erasure in erasure
priority mode
Forced stop command
t
t
—
—
—
32
—
—
—
—
20
—
µs
FD
*3
*3 *4
*3 *4
Year
Data hold time
10
10
DRP
Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 125,000),
erasing can be performed n times for each block. For example, when 4-byte programming is performed 16 times for different
addresses in 64-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address several times as one erasure is not enabled. Overwriting is prohibited.
Note 2. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1 to
the minimum value.
Note 3. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range.
Note 4. This result is obtained from reliability testing.
Note 5. Time for resumption includes time for reapplying the erasing pulse (up to one full pulse) that was cut off at the time of suspension.
Note 6. The reference value at VCC = 3.3 V and room temperature.
2.12.3
Option Setting Memory Characteristics
Table 2.48
Option setting memory characteristics
Conditions: Program: FCLK = 4 to 50 MHz
Read: FCLK ≤ 50 MHz
FCLK = 4 MHz
20 MHz ≤ FCLK ≤ 50 MHz
*4
*4
Parameter
Symbol Min
Typ
Max
Min
Typ
Max
Unit
Test conditions
Programming time
t
—
83
309
—
45
162
ms
OP
N
OPC
≤ 100 times
Programming time
> 100 times
t
—
100
371
—
55
195
ms
OP
N
OPC
*1
*1
Reprogramming cycle
N
t
—
—
—
—
—
—
—
—
Times
Years
20000
20000
OPC
*2
*2 *3
*2 *3
Data hold time
10
10
DRP
Note 1. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1 to
the minimum value.
Note 2. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range.
Note 3. This result is obtained from reliability testing.
Note 4. The reference value at VCC = 3.3 V and room temperature.
2.13
Boundary Scan
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 75 of 92
RA4M3 Datasheet
2. Electrical Characteristics
Table 2.49
Boundary scan characteristics
Parameter
Symbol
Min
100
45
45
—
Typ
—
—
—
—
—
—
—
—
—
—
—
Max
—
—
—
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
Test conditions
TCK clock cycle time
TCK clock high pulse width
TCK clock low pulse width
TCK clock rise time
TCK clock fall time
TMS setup time
t
t
t
t
t
t
t
t
t
t
Figure 2.63
TCKcyc
TCKH
TCKL
TCKr
—
5
TCKf
20
20
20
20
—
—
—
—
—
40
—
Figure 2.64
TMSS
TMSH
TDIS
TMS hold time
TDI setup time
TDI hold time
TDIH
TDO data delay
TDOD
*1
T
t
Figure 2.65
Boundary scan circuit startup time
BSSTUP
RESWP
Note 1. Boundary scan does not function until the power-on reset becomes negative.
tTCKcyc
tTCKH
tTCKf
TCK
tTCKr
tTCKL
Figure 2.63
Boundary scan TCK timing
TCK
TMS
TDI
tTMSS
tTMSH
tTDIS
tTDIH
tTDOD
TDO
Figure 2.64
Boundary scan input/output timing
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 76 of 92
RA4M3 Datasheet
2. Electrical Characteristics
VCC
RES
tBSSTUP
(= tRESWP)
Boundary scan
execute
Figure 2.65
Boundary scan circuit startup timing
Joint European Test Action Group (JTAG)
JTAG
2.14
Table 2.50
Parameter
Symbol
Min
40
15
15
—
—
8
Typ
—
—
—
—
—
—
—
—
—
—
Max
—
—
—
5
Unit
Test conditions
TCK clock cycle time
TCK clock high pulse width
TCK clock low pulse width
TCK clock rise time
TCK clock fall time
TMS setup time
t
t
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 2.66
TCKcyc
TCKH
TCKL
TCKr
5
TCKf
—
—
—
—
20
Figure 2.67
TMSS
TMSH
TDIS
TMS hold time
8
TDI setup time
8
TDI hold time
8
TDIH
TDO data delay time
—
TDOD
tTCKcyc
tTCKH
TCK
tTCKf
tTCKr
tTCKL
Figure 2.66
JTAG TCK timing
R01DS0368EJ0120 Rev.1.20
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RA4M3 Datasheet
2. Electrical Characteristics
TCK
tTMSS
tTMSH
TMS
tTDIS
tTDIH
TDI
tTDOD
TDO
Figure 2.67
JTAG input/output timing
2.15
Serial Wire Debug (SWD)
Table 2.51
Parameter
SWD
Symbol
Min
40
15
15
—
—
8
Typ
—
—
—
—
—
—
—
—
Max
—
—
—
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Test conditions
SWCLK clock cycle time
SWCLK clock high pulse width
SWCLK clock low pulse width
SWCLK clock rise time
SWCLK clock fall time
SWDIO setup time
t
t
t
t
t
t
t
t
Figure 2.68
SWCKcyc
SWCKH
SWCKL
SWCKr
SWCKf
SWDS
5
—
—
28
Figure 2.69
SWDIO hold time
8
SWDH
SWDIO data delay time
2
SWDD
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Dec 2, 2020
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RA4M3 Datasheet
2. Electrical Characteristics
tSWCKcyc
tSWCKH
SWCLK
tSWCKL
Figure 2.68
SWD SWCLK timing
SWCLK
tSWDS
tSWDH
SWDIO
(Input)
tSWDD
tSWDD
tSWDD
SWDIO
(Output)
SWDIO
(Output)
SWDIO
(Output)
Figure 2.69
SWD input/output timing
2.16
Embedded Trace Macro Interface (ETM)
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 79 of 92
RA4M3 Datasheet
2. Electrical Characteristics
Table 2.52
ETM
Conditions: High speed high drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter
Symbol
Min
40
Typ
—
—
—
—
—
—
—
Max
—
—
—
3
Unit
ns
Test conditions
TCLK clock cycle time
TCLK clock high pulse width
TCLK clock low pulse width
TCLK clock rise time
t
t
t
t
t
t
t
Figure 2.70
TCLKcyc
TCLKH
TCLKL
TCLKr
TCLKf
TRDS
17
ns
17
ns
—
ns
TCLK clock fall time
—
3
ns
TDATA[3:0] output setup time
TDATA[3:0] output hold time
3.5
2.5
—
—
ns
Figure 2.71
ns
TRDH
tTCLKcyc
tTCLKH
TCLK
tTCLKf
tTCLKr
tTCLKL
Figure 2.70
ETM TCLK timing
TCLK
tTRDS
tTRDH
tTRDS
tTRDH
TDATA[3:0]
Figure 2.71
ETM output timing
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 80 of 92
RA4M3 Datasheet
Appendix 1. Port States in Each Processing Mode
Appendix 1.
Port States in Each Processing Mode
After Deep Software Standby
mode is canceled (return to
startup mode)
Deep Software
Standby mode
Function
Mode
Pin function
MD
Reset
Pull-up
Pull-up
output
Hi-Z
Software Standby mode
Keep-O
IOKEEP = 0
Hi-Z
IOKEEP = 1*1
Keep
Keep
Keep
Keep
Keep
JTAG
TCK/TMS/TDI
TDO
Keep-O
Hi-Z
Keep
Keep-O
TDO output
Hi-Z
Keep
Keep-O*2
Keep-O*2
Keep-O*2
Keep-O*2
Keep-O*2
Keep-O*2
Keep-O*2
Keep-O*2
IRQ
IRQx
Keep
Keep*3
Keep
IRQx-DS
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Keep
Keep
Keep
Keep
Keep
Keep
Keep
AGT
AGTIOn
Keep*3
Keep
AGTIOn (n=1,3)
RXD0
SCI
IIC
SCLn/SDAn
USB_OVRCURx
Keep
Keep
USBFS
Keep*3
USB_OVRCURx-DS/
USB_VBUS
Keep-O*4
Keep*3
USB_DP/USB_DM
RTCICx
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Keep
Keep
Keep-O*2
Keep*3
Keep
Keep
Keep
Keep
RTC
RTCOUT
CLKOUT
DAn
Hi-Z
Hi-Z
Hi-Z
Hi-Z
[RTCOUT selected] RTCOUT output
[CLKOUT selected] CLKOUT output
[DAn output (DAOE = 1)] D/A output retained
Keep-O
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Keep
Keep
Keep
Keep
CLKOUT
DAC
Others
—
Note:
H: High-level
L: Low-level
Hi-Z: High-impedance
Keep-O: Output pins retain their previous values. Input pins go to high-impedance.
Keep: Pin states are retained during periods in Software Standby mode.
Note 1. Retains the I/O port state until the DPSBYCR.IOKEEP bit is cleared to 0.
Note 2. Input is enabled if the pin is specified as the Software Standby canceling source while it is used as an external interrupt pin.
Note 3. Input is enabled if the pin is specified as the Deep Software Standby canceling source.
Note 4. Input is enabled while the pin is used as an input pin.
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 81 of 92
RA4M3 Datasheet
Appendix 2. Package Dimensions
Appendix 2.
Package Dimensions
Information on the latest version of the package dimensions or mountings is displayed in “Packages” on the Renesas
Electronics Corporation website.
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
1.2
P-LFQFP144-20x20-0.50
PLQP0144KA-B
—
HD
D
Unit: mm
*1
108
73
109
72
144
37
NOTE 4
1
36
NOTE)
Index area
NOTE 3
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
F
S
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Dimensions in millimeters
Min Nom Max
Reference
Symbol
*3
b
e
p
M
y
S
D
E
19.9
19.9
20.0 20.1
20.0 20.1
A2
HD
HE
A
1.4
21.8
21.8
22.0 22.2
22.0 22.2
1.7
A1
bp
c
0.05
0.17
0.09
0
0.15
0.20 0.27
3.5
0.5
0.20
8
Lp
L1
e
x
0.08
0.08
0.75
Detail F
y
Lp
L1
0.45
0.6
1.0
© 2016 Renesas Electronics Corporation. All rights reserved.
Figure 2.1
LQFP 144-pin
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 82 of 92
RA4M3 Datasheet
Appendix 2. Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
0.6
P-LFQFP100-14x14-0.50
PLQP0100KB-B
—
HD
Unit: mm
*1
D
75
51
76
50
100
26
1
25
NOTE 4
NOTE)
Index area
NOTE 3
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
F
S
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Dimensions in millimeters
Min Nom Max
Reference
Symbol
y
S
*3
b
p
e
M
D
E
13.9
13.9
14.0 14.1
14.0 14.1
A2
HD
HE
A
1.4
15.8
15.8
16.0 16.2
16.0 16.2
1.7
A1
bp
c
0.05
0.15
0.09
0
0.15
0.20 0.27
3.5
0.5
0.20
8
Lp
L1
e
Detail F
x
0.08
0.08
0.75
y
Lp
L1
0.45
0.6
1.0
© 2015 Renesas Electronics Corporation. All rights reserved.
Figure 2.2
LQFP 100-pin
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 83 of 92
RA4M3 Datasheet
Appendix 2. Package Dimensions
JEITA Package Code
P-LFQFP64-10x10-0.50
RENESAS Code
Previous Code
MASS (Typ) [g]
0.3
PLQP0064KB-C
—
Unit: mm
HD
*1
D
48
33
49
32
64
17
1
16
NOTE 4
Index area
NOTE 3
NOTE)
F
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
S
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
y
S
*3
Dimensions in millimeters
Min Nom Max
Reference
Symbol
b
p
e
M
D
E
9.9
9.9
10.0 10.1
10.0 10.1
A2
HD
HE
A
1.4
11.8
11.8
12.0 12.2
12.0 12.2
1.7
A1
bp
c
0.05
0.15
0.09
0
0.15
0.20 0.27
3.5
0.5
0.20
8
Lp
L1
e
Detail F
x
0.08
0.08
0.75
y
Lp
L1
0.45
0.6
1.0
© 2015 Renesas Electronics Corporation. All rights reserved.
Figure 2.3
LQFP 64-pin
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 84 of 92
RA4M3 Datasheet
Appendix 3. I/O Registers
Appendix 3.
I/O Registers
This appendix describes I/O register address and access cycles by function.
3.1
Peripheral Base Addresses
This section provides the base addresses for peripherals described in this manual. Table 3.1 shows the name, description,
and the base address of each peripheral.
Table 3.1
Name
RMPU
TZF
Peripheral base address (1 of 3)
Description
Base address
0x4000_0000
0x4000_0E00
0x4000_2000
0x4000_3000
0x4000_5000
0x4000_5040
0x4000_5080
0x4000_50C0
0x4000_5100
0x4000_5140
0x4000_5180
0x4000_51C0
0x4000_5200
0x4000_5400
0x4000_6000
0x4000_7000
0x4000_8000
0x400_1B000
0x400_1C100
0x4001_E000
0x4008_0000
0x4008_0020
0x4008_0040
0x4008_0060
0x4008_0080
0x4008_00A0
0x4008_00C0
0x4008_00E0
0x4008_0100
0x4008_0800
0x4008_2000
0x4008_3000
0x4008_3200
0x4008_3400
0x4008_3600
Renesas Memory Protection Unit
TrustZone Filter
SRAM
BUS
SRAM Control
BUS Control
DMAC0
DMAC1
DMAC2
DMAC3
DMAC4
DMAC5
DMAC6
DMAC7
DMA
Direct memory access controller 0
Direct memory access controller 1
Direct memory access controller 2
Direct memory access controller 3
Direct memory access controller 4
Direct memory access controller 5
Direct memory access controller 6
Direct memory access controller 7
DMAC Module Activation
Data Transfer Controller
Interrupt Controller
DTC
ICU
CACHE
CPSCU
DBG
CACHE
CPU System Security Control Unit
Debug Function
FCACHE
SYSC
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
PORT8
PFS
Flash Cache
System Control
Port 0 Control Registers
Port 1 Control Registers
Port 2 Control Registers
Port 3 Control Registers
Port 4 Control Registers
Port 5 Control Registers
Port 6 Control Registers
Port 7 Control Registers
Port 8 Control Registers
Pmn Pin Function Control Register
Event Link Controller
ELC
RTC
Realtime Clock
IWDT
Independent Watchdog Timer
Watchdog Timer
WDT
CAC
Clock Frequency Accuracy Measurement Circuit
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RA4M3 Datasheet
Appendix 3. I/O Registers
Table 3.1
Name
MSTP
POEG
USBFS
SDHI0
SSIE0
IIC0
Peripheral base address (2 of 3)
Description
Base address
Module Stop Control A, B, C, D
Port Output Enable Module for GPT
USB 2.0 FS Module
0x4008_4000
0x4008_A000
0x4009_0000
0x4009_2000
0x4009_D000
0x4009_F000
0x4009_F014
0x4009_F100
0x400A_8000
0x400A_9000
0x400D_0000
0x400E_0000
0x400E_8000
0x400E_8100
0x400E_8200
0x400E_8300
0x400E_8400
0x400E_8500
0x400F_3000
0x4010_8000
0x4010_9000
0x4011_8000
0x4011_8100
0x4011_8200
0x4011_8300
0x4011_8400
0x4011_8900
0x4011_A000
0x4016_1000
0x4016_9000
0x4016_9100
0x4016_9200
0x4016_9300
0x4016_9400
0x4016_9500
0x4016_9600
0x4016_9700
0x4016_9A00
0x4017_0000
0x4017_0200
0x4017_1000
SD Host Interface 0
Serial Sound Interface Enhanced (SSIE)
Inter-Integrated Circuit 0
IIC0WU
IIC1
Inter-Integrated Circuit 0 Wake-up Unit
Inter-Integrated Circuit 1
CAN0
CAN1
CTSU
PSCU
AGT0
CAN0 Module
CAN1 Module
Capacitive Touch Sensing Unit
Peripheral Security Control Unit
Low Power Asynchronous General purpose Timer 0
Low Power Asynchronous General purpose Timer 1
Low Power Asynchronous General purpose Timer 2
Low Power Asynchronous General purpose Timer 3
Low Power Asynchronous General purpose Timer 4
Low Power Asynchronous General purpose Timer 5
Temperature Sensor
AGT1
AGT2
AGT3
AGT4
AGT5
TSN
CRC
CRC Calculator
DOC
Data Operation Circuit
SCI0
Serial Communication Interface 0
Serial Communication Interface 1
Serial Communication Interface 2
Serial Communication Interface 3
Serial Communication Interface 4
Serial Communication Interface 9
Serial Peripheral Interface 0
SCI1
SCI2
SCI3
SCI4
SCI9
SPI0
SCE9
Secure Cryptographic Engine
General PWM 32-Bit Timer 0
General PWM 32-Bit Timer 1
General PWM 32-Bit Timer 2
General PWM 32-Bit Timer 3
General PWM 16-Bit Timer 4
General PWM 16-Bit Timer 5
General PWM 16-Bit Timer 6
General PWM 16-Bit Timer 7
Output Phase Switching Controller
12bit A/D Converter 0
GPT320
GPT321
GPT322
GPT323
GPT164
GPT165
GPT166
GPT167
GPT_OPS
ADC120
ADC121
DAC12
12bit A/D Converter 1
12-bit D/A converter
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Dec 2, 2020
Page 86 of 92
RA4M3 Datasheet
Appendix 3. I/O Registers
Table 3.1
Name
FLAD
Peripheral base address (3 of 3)
Description
Base address
Data Flash
0x407F_C000
0x407F_E000
0x6400_0000
FACI
Flash Application Command Interface
Quad-SPI
QSPI
Note:
Name = Peripheral name
Description = Peripheral functionality
Base address = Lowest reserved address or address used by the peripheral
3.2
Access Cycles
This section provides access cycle information for the I/O registers described in this manual.
● Registers are grouped by associated module.
● The number of access cycles indicates the number of cycles based on the specified reference clock.
● In the internal I/O area, reserved addresses that are not allocated to registers must not be accessed, otherwise operations
cannot be guaranteed.
● The number of I/O access cycles depends on bus cycles of the internal peripheral bus, divided clock synchronization
cycles, and wait cycles of each module. Divided clock synchronization cycles differ depending on the frequency ratio
between ICLK and PCLK.
● When the frequency of ICLK is equal to that of PCLK, the number of divided clock synchronization cycles is always
constant.
● When the frequency of ICLK is greater than that of PCLK, at least 1 PCLK cycle is added to the number of divided
clock synchronization cycles.
● The number of write access cycles indicates the number of cycles obtained by non-bufferable write access.
Note:
This applies to the number of cycles when access from the CPU does not conflict with the instruction fetching to the
external memory or bus access from other bus masters such as DTC or DMAC.
Table 3.2
Access cycles (1 of 3)
Number of access cycles
Address
From
ICLK = PCLK
ICLK > PCLK*1
Cycle
Unit
Peripherals
To
Read
Write
Read
Write
Related function
RMPU, TZF,
SRAM, BUS,
DMACn, DMA,
DTC, ICU
0x4000_0000
0x4000_6FFF
4
3
4
3
ICLK
Renesas Memory
Protection Unit,
TrustZone Filter,
SRAM Control, BUS
Control, Direct
memory access
controller n, DMAC
Module Activation,
DTC Control Register,
Interrupt Controller
CACHE
0x4000_7000
0x4000_8000
0x4000_7FFF
0x4001_CFFF
3
4
5
3
3
4
5
3
ICLK
ICLK
CACHE
CPSCU, DBG,
FCACHE
CPU System Security
Control Unit, Debug
Function, Flash Cache
SYSC
0x4001_E000
0x4001_E400
0x4008_0000
0x4001_E3FF
0x4001_E5FF
0x4008_0FFF
5
9
5
4
8
4
5
4
ICLK
System Control
SYSC
5 to 8
2 to 5
5 to 8
2 to 4
PCLKB System Control
PORTn, PFS
PCLKB Port n Control
Registers, Pmn Pin
Function Control
Register
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 87 of 92
RA4M3 Datasheet
Appendix 3. I/O Registers
Table 3.2
Access cycles (2 of 3)
Number of access cycles
ICLK = PCLK
Address
From
ICLK > PCLK*1
Read
Cycle
Unit
Peripherals
To
Read
Write
Write
Related function
ELC, RTC, IWDT, 0x4008_2000
WDT, CAC
0x4008_3FFF
5
4
3 to 5
2 to 4
PCLKB Event Link Controller,
Realtime Clock,
Independent
Watchdog Timer,
Watchdog Timer,
Clock Frequency
Accuracy
Measurement Circuit
MSTP
POEG
0x4008_4000
0x4008_A000
0x4008_4FFF
0x4008_AFFF
5
5
4
4
2 to 5
3 to 5
2 to 4
2 to 4
PCLKB Module Stop Control
PCLKB Port Output Enable
Module for GPT
USBFS
USBFS
0x4009_0000
0x4009_4000
0x4009_2000
0x4009_3FFF
0x4009_4FFF
0x4009_FFFF
6
4
5
5
3
4
3 to 6
1 to 4
2 to 5
3 to 5
1 to 3
2 to 4
PCLKB USB 2.0 FS Module
PCLKB USB 2.0 FS Module
SDHI0, SSIE0,
IICn, IIC0WU
PCLKB SD Host Interface 0,
Serial Sound Interface
Enhanced, Inter-
Integrated Circuit n,
Inter-Integrated Circuit
0 Wake-up Unit
CANn
CTSU
0x400A_8000
0x400D_0000
0x400A_9FFF
0x400D_FFFF
5
4
4
3
2 to 5
1 to 4
2 to 4
1 to 3
PCLKB CANn Module
PCLKB Capacitive Touch
Sensing Unit
PSCU
AGTn
0x400E_0000
0x400E_8000
0x400E_0FFF
0x400E_8FFF
5
7
4
4
2 to 5
5 to 7
2 to 4
2 to 4
PCLKB Peripheral Security
Control Unit
PCLKB Low Power
Asynchronous
General purpose
Timer n
TSN
0x400F_3000
0x4010_8000
0x400F_3FFF
0x4010_9FFF
5
5
4
4
2 to 5
2 to 5
2 to 4
2 to 4
PCLKB Temperature Sensor
CRC, DOC
PCLKA CRC Calculator, Data
Operation Circuit
5*2
4*2
2 to 5*2
2 to 4*2
SCIn
SPIn
SCE9
0x4011_8000
0x4011_A000
0x4016_1000
0x4011_8FFF
0x4011_AFFF
0x4016_1FFF
0x4016_9FFF
PCLKA Serial Communication
Interface n
5*3
6
4*3
4
2 to 5*3
3 to 6
2 to 4*3
2 to 4
PCLKA Serial Peripheral
Interface n
PCLKA Secure Cryptographic
Engine
GPT32n, GPT16n, 0x4016_9000
GPT_OPS
7
4
4 to 7
2 to 4
PCLKA General PWM 32-Bit
Timer n, General
PWM 16-Bit Timer n,
Output Phase
Switching Controller
ADC12n, DAC12
0x4017_0000
0x4017_2FFF
5
5
4
2 to 5
2 to 5
2 to 4
PCLKA 12bit A/D Converter n,
12-bit D/A converter
14 to *4
6 to *4
14 to *4
5 to *4
QSPI
QSPI
QSPI
QSPI
0x6400_0000
0x6400_0010
0x6400_0014
0x6400_0804
0x6400_000F
0x6400_0013
0x6400_0037
0x6400_0807
PCLKA Quad-SPI
PCLKA Quad-SPI
PCLKA Quad-SPI
PCLKA Quad-SPI
25 to *4
5
25 to *4
2 to 5
14 to *4
3
14 to *4
1 to 3
4
1 to 4
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 88 of 92
RA4M3 Datasheet
Appendix 3. I/O Registers
Table 3.2
Access cycles (3 of 3)
Number of access cycles
ICLK = FCLK
Address
From
ICLK > FCLK*1
Read
Cycle
Unit
Peripherals
To
Read
Write
Write
Related function
FLAD, FACI
0x407F_C000
0x407F_EFFF
5
4
2 to 5
2 to 4
FCLK
Data Flash, Flash
Application Command
Interface
Note 1. If the number of PCLK or FCLK cycles is non-integer (for example 1.5), the minimum value is without the decimal point, and the
maximum value is rounded up to the decimal point. For example, 1.5 to 2. 5 is 1 to 3.
Note 2. When accessing a 16-bit register (FTDRHL, FRDRHL, FCR, FDR, LSR, and CDR), access is 2 cycles more than the value shown in
Table 3.2. When accessing an 8-bit register (including FTDRH, FTDRL, FRDRH, and FRDRL), the access cycles are as shown in
Table 3.2.
Note 3. When accessing the 32-bit register (SPDR), access is 2 cycles more than the value in Table 3.2. When accessing an 8-bit or 16-bit
register (SPDR_HA), the access cycles are as shown in Table 3.2.
Note 4. The access cycles depend on the QSPI bus cycles.
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 89 of 92
RA4M3 Datasheet
Revision History
Revision History
Revision 1.20 — December 2, 2020
First edition, issued
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 90 of 92
General Precautions in the Handling of Microprocessing Unit and Microcontroller
Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the
products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
1. Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps
must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be
adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.
Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor
devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.
2. Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of
register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset
pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins
in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the
level at which resetting is specified.
3. Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal
elements. Follow the guideline for input signal during power-off state as described in your product documentation.
4. Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are
generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of
the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
become possible.
5. Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program
execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator
during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal
produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
6. Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the
input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.).
7. Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these
addresses as the correct operation of the LSI is not guaranteed.
8. Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.
The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms
of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,
operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-
evaluation test for the given product.
Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products
and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your
product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of
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3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
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and all liability for any losses or damages incurred by you or third parties arising from such alteration, modification, copying or reverse engineering.
5. Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The intended applications for
each Renesas Electronics product depends on the product's quality grade, as indicated below.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home
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"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key
financial terminal systems; safety control equipment; etc.
Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas
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any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is
inconsistent with any Renesas Electronics data sheet, user's manual or other Renesas Electronics document.
6. When using Renesas Electronics products, refer to the latest product information (data sheets, user's manuals, application notes, "General Notes for
Handling and Using Semiconductor Devices" in the reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by
Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation characteristics, installation, etc. Renesas
Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such
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7. Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific
characteristics, such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Unless designated as a high reliability
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are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury,
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(Note1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled
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