R5F6416KAPFD [RENESAS]
RENESAS MCU; 瑞萨MCU型号: | R5F6416KAPFD |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | RENESAS MCU |
文件: | 总102页 (文件大小:794K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
R32C/116A Group Datasheet
Datasheet
R32C/116A Group
RENESAS MCU
REJ03B0297-0100
Rev.1.00
Jul 16, 2010
1. Overview
1.1
Features
The M16C Family offers a robust platform of 32-/16-bit CISC microcomputers (MCUs) featuring high ROM
code efficiency, extensive EMI/EMS noise immunity, ultra-low power consumption, high-speed processing
in actual applications, and numerous and varied integrated peripherals. Extensive device scalability from
low- to high-end, featuring a single architecture as well as compatible pin assignments and peripheral
functions, provides support for a vast range of application fields.
The R32C/100 Series is a high-end microcontroller series in the M16C Family. With a 4-Gbyte memory
space, it achieves maximum code efficiency and high-speed processing with 32-bit CISC architecture,
multiplier, multiply-accumulate unit, and floating point unit. The selection from the broadest choice of on-
2
chip peripheral devices — UART, CRC, DMAC, A/D and D/A converters, timers, I C, and WDT enables to
minimize external components.
The R32C/100 Series, in particular, provides the R32C/116A Group as a standard product. This product,
provided as a 144/176-pin plastic molded LQFP package, configures 11 channels of serial interface and
2
one channel of multi-master I C-bus interface.
1.1.1
Applications
Car audio, audio, cameras, television, home appliance, printer, office/industrial equipment,
communication/portable devices, etc.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 1 of 99
R32C/116A Group
1. Overview
1.1.2
Performance Overview
Table 1.1 to Table 1.4 show the performance overview of the R32C/116A Group.
Table 1.1
Unit
R32C/116A Group Performance for the 176 pin-Package (1/2)
Function Performance
Central
CPU
R32C/100 Series CPU Core
• Basic instructions: 108
processing unit
• Minimum instruction execution time: 15.625 ns (f(CPU) = 64 MHz)
• Multiplier: 32-bit × 32-bit ꢀ 64-bit
• Multiply-accumulate unit: 32-bit × 32-bit + 64-bit ꢀ 64-bit
• IEEE-754 floating point standard: Single precision
• 32-bit barrel shifter
• Operating mode: Single-chip mode, memory expansion mode,
(1)
microprocessor mode (optional
)
Memory
Flash memory: 512 Kbytes to 1 Mbyte
RAM: 96 Kbytes
Data flash: 4 Kbytes × 2 blocks
Refer to Table 1.5 for memory size of each product group
(1)
Voltage
Detector
Low voltage
detector
Optional
Low voltage detection interrupt
Clock
Clock generator
• 4 circuits (main clock, sub clock, PLL, on-chip oscillator)
• Oscillation stop detector: Main clock oscillator stop/re-oscillation
detection
• Frequency divide circuit: Divide-by-2 to divide-by-24 selectable
• Low power modes: Wait mode, stop mode
External Bus Bus and memory • Address space: 4 Gbytes (of which up to 64 Mbytes is user
Expansion
expansion
accessible)
• External bus Interface: Support for wait-state insertion, 4 chip select
outputs
• Bus format: Separate bus/Multiplexed bus selectable, data bus width
selectable (8/16/32 bits)
Interrupts
Interrupt vectors: 261
External interrupt inputs: NMI, INT × 9, key input × 4
Interrupt priority levels: 7 levels
Watchdog Timer
DMA
15 bits × 1 (selectable input frequency from prescaler output)
• Automatic timer start function is available
DMAC
4 channels
• Cycle-steal transfer mode
• Request sources: 61
• 2 transfer modes: Single transfer, repeat transfer
DMAC II
• Can be activated by any peripheral interrupt source
• 3 transfer functions: Immediate data transfer, calculation transfer,
chained transfer
I/O Ports
Note:
Programmable
I/O ports
• 2 input-only ports
• 156 CMOS inputs/outputs
• 52 ports are 5 V tolerant
• A pull-up resistor is selectable for every 4 input ports (except 5 V
tolerant inputs)
1. Please contact a Renesas Electronics sales office to use the optional feature.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 2 of 99
R32C/116A Group
1. Overview
Table 1.2
Unit
R32C/116A Group Performance for the 176-pin Package (2/2)
Function Performance
Timer A
Timer
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse-width
modulation (PWM) mode
Two-phase pulse signal processing in event counter mode (two-
phase encoder input) × 3
Timer B
16-bit timer × 6
Timer mode, event counter mode, pulse frequency measurement
mode, pulse-width measurement mode
Three-phase
motor control
timer
Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)
8-bit programmable dead time timer
Serial
Interface
UART0 to
UART10
Asynchronous/synchronous serial interface × 11 channels
2
• I C-bus (UART0 to UART6)
• Special mode 2 (UART0 to UART6)
(1)
• IEBus (optional ) (UART0 to UART6)
A/D Converter
10-bit resolution × 34 channels
Sample and hold functionality integrated
Self test/Open-circuit detection assist
D/A Converter
CRC Calculator
X-Y Converter
Intelligent I/O
8-bit resolution × 2
16
12
5
CRC-CCITT (X + X + X + 1)
16 bits × 16 bits
Time measurement (input capture): 16 bits × 16
Waveform generation (output compare): 16 bits × 24
Serial interface: Variable-length synchronous serial I/O mode, IEBus
(1)
mode (optional
1 channel
)
2
Multi-master I C-bus Interface
Flash Memory
Programming and erasure supply voltage: VCC = 3.0 to 5.5 V
Minimum endurance: 1,000 program/erase cycles
Suspend/resume function available
Security protection: ROM code protect, ID code protect
Debugging: On-chip debug, on-board flash programming
Operating Frequency/Supply
Voltage
64 MHz/VCC = 3.0 to 5.5 V
Operating Temperature
-20°C to 85°C (N version)
-40°C to 85°C (D version)
-40°C to 85°C (P version)
Current Consumption
45 mA (VCC = 5.0 V, f(CPU) = 64 MHz)
8 µA (VCC = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode)
Package
Note:
176-pin plastic molded LQFP (PLQP0176KB-A)
1. Please contact a Renesas Electronics sales office to use the optional feature.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 3 of 99
R32C/116A Group
1. Overview
Table 1.3
Unit
R32C/116A Group Performance for the 144-pin Package (1/2)
Function Performance
Central
CPU
R32C/100 Series CPU Core
• Basic instructions: 108
processing unit
• Minimum instruction execution time: 15.625 ns (f(CPU) = 64 MHz)
• Multiplier: 32-bit × 32-bit ꢀ 64-bit
• Multiply-accumulate unit: 32-bit × 32-bit + 64-bit ꢀ 64-bit
• IEEE-754 floating point standard: Single precision
• 32-bit barrel shifter
• Operating mode: Single-chip mode, memory expansion mode,
(1)
microprocessor mode (optional
)
Memory
Flash memory: 512 Kbytes to 1 Mbyte
RAM: 96 Kbytes
Data flash: 4 Kbytes × 2 blocks
Refer to Table 1.5 for memory size of each product group
(1)
Voltage
Detector
Low voltage
detector
Optional
Low voltage detection interrupt
Clock
Clock generator
• 4 circuits (main clock, sub clock, PLL, on-chip oscillator)
• Oscillation stop detector: Main clock oscillator stop/re-oscillation
detection
• Frequency divide circuit: Divide-by-2 to divide-by-24 selectable
• Low power modes: Wait mode, stop mode
External Bus Bus and memory • Address space: 4 Gbytes (of which up to 64 Mbytes is user
Expansion
expansion
accessible)
• External bus Interface: Support for wait-state insertion, 4 chip select
outputs
• Bus format: Separate bus/Multiplexed bus selectable, data bus width
selectable (8/16/32 bits)
Interrupts
Interrupt vectors: 261
External interrupt inputs: NMI, INT × 9, key input × 4
Interrupt priority levels: 7 levels
Watchdog Timer
DMA
15 bits × 1 (selectable input frequency from prescaler output)
Automatic timer start function is available
DMAC
4 channels
• Cycle-steal transfer mode
• Request sources: 61
• 2 transfer modes: Single transfer, repeat transfer
DMAC II
• Can be activated by any peripheral interrupt source
• 3 transfer functions: Immediate data transfer, calculation transfer,
chained transfer
I/O Ports
Note:
Programmable
I/O ports
• 2 input-only ports
• 124 CMOS inputs/outputs
• 40 ports are 5 V tolerant
• A pull-up resistor is selectable for every 4 input ports (except 5 V
tolerant inputs)
1. Please contact a Renesas Electronics sales office to use the optional feature.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 4 of 99
R32C/116A Group
1. Overview
Table 1.4
Unit
R32C/116A Group Performance for the 144-pin Package (2/2)
Function Performance
Timer A
Timer
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse-width
modulation (PWM) mode
Two-phase pulse signal processing in event counter mode (two-
phase encoder input) × 3
Timer B
16-bit timer × 6
Timer mode, event counter mode, pulse frequency measurement
mode, pulse-width measurement mode
Three-phase
motor control
timer
Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)
8-bit programmable dead time timer
Serial
Interface
UART0 to
UART10
Asynchronous/synchronous serial interface × 11 channels
2
• I C-bus (UART0 to UART6)
• Special mode 2 (UART0 to UART6)
(1)
• IEBus (optional ) (UART0 to UART6)
A/D Converter
10-bit resolution × 34 channels
Sample and hold functionality integrated
Self test/Open-circuit detection assist
D/A Converter
CRC Calculator
X-Y Converter
Intelligent I/O
8-bit resolution × 2
16
12
5
CRC-CCITT (X + X + X + 1)
16 bits × 16 bits
Time measurement (input capture): 16 bits × 16
Waveform generation (output compare): 16 bits × 24
Serial interface: Variable-length synchronous serial I/O mode, IEBus
(1)
mode (optional
1 channel
)
2
Multi-master I C-bus Interface
Flash Memory
Programming and erasure supply voltage: VCC = 3.0 to 5.5 V
Minimum endurance: 1,000 program/erase cycles
Suspend/resume function available
Security protection: ROM code protect, ID code protect
Debugging: On-chip debug, on-board flash programming
Operating Frequency/Supply
Voltage
64 MHz/VCC = 3.0 to 5.5 V
Operating Temperature
-20°C to 85°C (N version)
-40°C to 85°C (D version)
-40°C to 85°C (P version)
Current Consumption
45 mA (VCC = 5.0 V, f(CPU) = 64 MHz)
8 µA (VCC = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode)
Package
Note:
144-pin plastic molded LQFP (PLQP0144KA-A)
1. Please contact a Renesas Electronics sales office to use the optional feature.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 5 of 99
R32C/116A Group
1. Overview
1.2
Product Information
Table 1.5 lists the product information and Figure 1.1 shows the details of the part number.
Table 1.5
R32C/116A Group Product List
As of July, 2010
Package Code (1)
ROM Capacity (2)
Part Number
RAM Capacity
96 Kbytes
Remarks
R5F6416JANFE
R5F6416JADFE
R5F6416JAPFE
R5F6416JANFD
R5F6416JADFD
R5F6416JAPFD
R5F6416KANFE
R5F6416KADFE
R5F6416KAPFE
R5F6416KANFD
R5F6416KADFD
R5F6416KAPFD
R5F6416LANFE
R5F6416LADFE
R5F6416LAPFE
R5F6416LANFD
R5F6416LADFD
R5F6416LAPFD
R5F6416MANFE
R5F6416MADFE
R5F6416MAPFE
R5F6416MANFD
R5F6416MADFD
R5F6416MAPFD
(P)
(P)
(P)
(P)
(P)
(P)
(P)
(P)
(P)
(P)
(P)
(P)
(P)
(D)
(D)
(P)
(D)
(D)
(P)
(D)
(D)
(P)
(D)
(D)
-20°C to 85°C (N version)
-40°C to 85°C (D version)
-40°C to 85°C (P version)
-20°C to 85°C (N version)
-40°C to 85°C (D version)
-40°C to 85°C (P version)
-20°C to 85°C (N version)
-40°C to 85°C (D version)
-40°C to 85°C (P version)
-20°C to 85°C (N version)
-40°C to 85°C (D version)
-40°C to 85°C (P version)
-20°C to 85°C (N version)
-40°C to 85°C (D version)
-40°C to 85°C (P version)
-20°C to 85°C (N version)
-40°C to 85°C (D version)
-40°C to 85°C (P version)
-20°C to 85°C (N version)
-40°C to 85°C (D version)
-40°C to 85°C (P version)
-20°C to 85°C (N version)
-40°C to 85°C (D version)
-40°C to 85°C (P version)
PLQP0176KB-A
512 Kbytes
+ 8 Kbytes
PLQP0144KA-A
PLQP0176KB-A
PLQP0144KA-A
PLQP0176KB-A
PLQP0144KA-A
PLQP0176KB-A
PLQP0144KA-A
640 Kbytes
+ 8 Kbytes
96 Kbytes
96 Kbytes
96 Kbytes
768 Kbytes
+ 8 Kbytes
1 Mbyte
+ 8 Kbytes
(D): Under development
(P): On planning phase
Notes:
1. The old package codes are as follows:PLQP0144KA-A: 144P6Q-A, PLQP0176KB-A: 176P6Q-A
2. Data flash memory provides an additional 8 Kbytes of ROM capacity.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 6 of 99
R32C/116A Group
1. Overview
Part Number
R5 F 64 16 M A P XXX FE
Package Code
FD : PLQP0144KA-A
FE : PLQP0176KB-A
ROM Number
Omitted in the flash memory version
Temperature Code
N : -20°C to 85°C
D : -40°C to 85°C
P : -40°C to 85°C
ROM/RAM Capacity
J : 512 KB/96 KB
K : 640 KB/96 KB
L : 768 KB/96 KB
M: 1 MB/96 KB
R32C/116A Group
R32C/100 Series
Memory Type
F : Flash memory version
Figure 1.1
Part Numbering
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 7 of 99
R32C/116A Group
1. Overview
1.3
Block Diagram
Figure 1.2 shows a block diagram of the R32C/116A Group.
8
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7
Peripheral functions
Timer:
Timer A 16 bits × 5 timers
Timer B 16 bits × 6 timers
A/D converter:
Clock generator:
4 circuits
- XIN-XOUT
- XCIN-XCOUT
- On-chip oscillator
- PLL frequency synthesizer
10 bits × 1 circuit
Standard: 10 inputs
Maximum: 34 inputs
Three-phase motor
controller
D/A converter:
8 bits × 2 channels
Serial interface:
11 channels
Watchdog timer:
15 bits
X-Y converter:
16 bits × 16 bits
Multi-master I2C-bus
interface:
DMAC
CRC calculator (CCITT)
X16 + X12 + X5 + 1
1 channel
DMAC II
Memory
ROM
Intelligent I/O
Time Measurement: 16
Wave generation: 24
Serial interface:
- Variable-length
synchronous serial I/O
- IEBus
R32C/100 Series CPU Core
R2R0
R2R0
FLG
INTB
ISP
USP
PC
SVF
SVP
VCT
R3R1
R6R4
RAM
R7R5
A0
A1
Multiplier
A2
A3
FB
Floating-point unit
SB
Port P19
Port P18
Port P17
Port P16
Port P15
Port P14
P14_1
Port P13
8
8
8
8
8
5
8
(Note 1)
Note:
1. Ports P16 to P19 are available in the 176-pin package only.
Figure 1.2
R32C/116A Group Block Diagram
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 8 of 99
R32C/116A Group
1. Overview
1.4
Pin Assignments
Figure 1.3 and Figure 1.4 show the pin assignments (top view) and Table 1.6 to Table 1.13 show the pin
characteristics.
(Note 1)
(Note 2)
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
IIO0_0 / IIO1_0 / D8 / P1_0
P4_4 / CS3 / A20 / CTS6 / RTS6 / SS6
AN0_7 / D7 / P0_7
P4_5 / CS2 / A21 / CLK6
AN0_6 / D6 / P0_6
P4_6 / CS1 / A22 / RXD6 / SCL6 / STXD6
AN0_5 / D5 / P0_5
P4_7 / CS0 / A23 / TXD6 / SDA6 / SRXD6
AN0_4 / D4 / P0_4
P19_2
P19_1
P17_0
WR3 / BC3 / P11_4
P17_1
P19_0
P17_2
IIO1_3 / CTS8 / RTS8 / WR2 / CS3 / P11_3
P17_3
IIO1_2 / RXD8 / CS2 / P11_2
P19_3
IIO1_1 / CLK8 / CS1 / P11_1
P12_5 / D21
P12_6 / D22
P12_7 / D23
P5_0 / WR0 / WR
P5_1 / WR1 / BC1
P5_2 / RD
IIO1_0 / TXD8 / CS0 / P11_0
P18_7
P18_6
P18_5
P18_4
P18_3
P5_3 / CLKOUT / BCLK
P13_0 / D24 / OUTC2_4
P13_1 / D25 / OUTC2_5
VCC
P18_2
AN0_3 / D3 / P0_3
R32C/116A GROUP
AN0_2 / D2 / P0_2
AN0_1 / D1 / P0_1
P13_2 / D26 / OUTC2_6
(Note 2)
AN0_0 / D0 / P0_0
VSS
PLQP0176KB-A
(176P6Q-A)
(Top view)
IIO0_7 / CTS6 / RTS6 / SS6 / AN15_7 / P15_7
IIO0_6 / CLK6 / AN15_6 / P15_6
IIO0_5 / RXD6 / SCL6 / STXD6 / AN15_5 / P15_5
IIO0_4 / TXD6 / SDA6 / SRXD6 / AN15_4 / P15_4
IIO0_3 / CTS7 / RTS7 / AN15_3 / P15_3
IIO0_2 / RXD7 / AN15_2 / P15_2
IIO0_1 / CLK7 / AN15_1 / P15_1
VSS
P13_3 / D27 / OUTC2_3
P5_4 / HLDA / CS1 / TXD7
P5_5 / HOLD / CLK7
P5_6 / ALE / CS2 / RXD7
P5_7 / RDY / CS3 / CTS7 / RTS7
P19_4
P13_4 / D28 / OUTC2_0 / ISTXD2 / IEOUT
P13_5 / D29 / OUTC2_2 / ISRXD2 / IEIN
P13_6 / D30 / OUTC2_1 / ISCLK2
P13_7 / D31 / OUTC2_7
IIO0_0 / TXD7 / AN15_0 / P15_0
VCC
KI3 / AN_7 / P10_7
P19_5
KI2 / AN_6 / P10_6
P6_0 / TB0IN / CTS0 / RTS0 / SS0
P6_1 / TB1IN / CLK0
KI1 / AN_5 / P10_5
KI0 / AN_4 / P10_4
P6_2 / TB2IN / RXD0 / SCL0 / STXD0
P6_3 / TXD0 / SDA0 / SRXD0
P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2
P6_5 / CLK1
AN_3 / P10_3
AN_2 / P10_2
AN_1 / P10_1
AVSS
P11_7
AN_0 / P10_0
P6_6 / RXD1 / SCL1 / STXD1
P14_7
VREF
AVCC
P6_7 / TXD1 / SDA1 / SRXD1
P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT / MSDA
STXD4 / SCL4 / RXD4 / ADTRG / P9_7
(Note 3)
(Note 2)
Notes:
1. Pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins.
2. The following pins are 5 V tolerant inputs: P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_3, P12_0 to P12_7, P16_0 to P16_7, and P17_0 to P17_3.
3. The position of pin number 1 varies by product. Refer to the index mark in attached “Package Dimensions”.
Figure 1.3
Pin Assignment for the 176-pin Package (top view)
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 9 of 99
R32C/116A Group
1. Overview
Table 1.6
Pin Characteristics for the 176-pin Package (1/5)
Pin Control
Interrupt
Analog BusControl
Port
Timer Pin
UART Pin
Intelligent I/O Pin
No.
Pin
Pin
Pin
ANEX1
ANEX0
DA1
Pin
1
2
3
4
5
P9_6
P9_5
P9_4
P9_3
P9_2
TXD4/SDA4/SRXD4
CLK4
TB4IN
TB3IN
TB2IN
CTS4/RTS4/SS4
CTS3/RTS3/SS3
TXD3/SDA3/SRXD3
DA0
OUTC2_0/ISTXD2/
IEOUT
6
7
8
9
P9_1
P9_0
P19_7
TB1IN
TB0IN
RXD3/SCL3/STXD3
CLK3
ISRXD2/IEIN
P14_6 INT8
P19_6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
P14_5 INT7
P14_4 INT6
P14_3
VDC0
P14_1
VDC1
NSD
CNVSS
XCIN
P8_7
XCOUT P8_6
RESET
XOUT
VSS
XIN
VCC
P8_5 NMI
P8_4 INT2
P8_3 INT1
P8_2 INT0
P8_1
TA4IN/U
CTS5/RTS5/SS5
IIO1_5/UD0B/UD1B
UD0A/UD1A
P8_0
TA4OUT/U RXD5/SCL5/STXD5
P18_1
P18_0
P7_7
TA3IN
CLK5
IIO1_4/UD0B/UD1B
IIO1_3/UD0A/UD1A
P7_6
TA3OUT
TXD5/SDA5/SRXD5/
CTS8/RTS8
36
P7_5
TA2IN/W
RXD8
IIO1_2
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 10 of 99
R32C/116A Group
1. Overview
Table 1.7
Pin Characteristics for the 176-pin Package (2/5)
Pin Control
Interrupt
Analog BusControl
Pin Pin
Port
Timer Pin
UART Pin
Intelligent I/O Pin
IIO1_1
No.
Pin
Pin
37
P7_4
TA2OUT/W CLK8
38
39
40
41
42
43
44
P17_7
P17_6
P17_5
P17_4
P7_3
TA1IN/V
CTS2/RTS2/SS2/TXD8 IIO1_0
P7_2
TA1OUT/V CLK2
P7_1
TB5IN/
TA0IN
RXD2/SCL2/STXD2/
IIO1_7/OUTC2_2/
ISRXD2/IEIN
MSCL
45
P7_0
TA0OUT
TXD2/SDA2/SRXD2/
MSDA
IIO1_6/OUTC2_0/
ISTXD2/IEOUT
46
47
48
49
50
51
52
53
54
55
56
57
58
59
P6_7
P14_7
P6_6
P11_7
P6_5
P6_4
P6_3
P6_2
TXD1/SDA1/SRXD1
RXD1/SCL1/STXD1
CLK1
CTS1/RTS1/SS1
TXD0/SDA0/SRXD0
RXD0/SCL0/STXD0
CLK0
OUTC2_1/ISCLK2
TB2IN
TB1IN
TB0IN
P6_1
P6_0
P19_5
P13_7
P13_6
P13_5
CTS0/RTS0/SS0
OUTC2_7
D31
D30
D29
OUTC2_1/ISCLK2
OUTC2_2/ISRXD2/
IEIN
60
P13_4
OUTC2_0/ISTXD2/
IEOUT
D28
61
62
63
64
65
66
67
68
69
70
71
72
P19_4
P5_7
P5_6
P5_5
P5_4
P13_3
CTS7/RTS7
RXD7
RDY/CS3
ALE/CS2
HOLD
CLK7
TXD7
HLDA/CS1
D27
OUTC2_3
OUTC2_6
VSS
P13_2
D26
VCC
P13_1
P13_0
P5_3
OUTC2_5
OUTC2_4
D25
D24
CLKOUT/
BCLK
73
74
P5_2
P5_1
RD
WR1/BC1
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 11 of 99
R32C/116A Group
1. Overview
Table 1.8
Pin Characteristics for the 176-pin Package (3/5)
Pin Control
Interrupt
Analog BusControl
Port
Timer Pin
UART Pin
Intelligent I/O Pin
No.
Pin
Pin
Pin
Pin
WR0/WR
D23
75
P5_0
76
77
78
79
80
81
82
83
84
85
86
87
88
89
P12_7
P12_6
P12_5
P19_3
P17_3
P17_2
P17_1
P17_0
P19_2
P4_7
D22
D21
TXD6/SDA6/SRXD6
RXD6/SCL6/STXD6
CLK6
CS0/A23
CS1/A22
CS2/A21
CS3/A20
A19
P4_6
P4_5
P4_4
CTS6/RTS6/SS6
TXD3/SDA3/SRXD3
P4_3
OUTC2_0/ISTXD2/
IEOUT
90
P11_6
P4_2
91
RXD3/SCL3/STXD3
ISRXD2/IEIN
A18
92
P11_5
P4_1
93
CLK3
A17
A16
94
P4_0
CTS3/RTS3/SS3
TXD10
95
P16_7
P16_6
P16_5
P16_4
P3_7
96
RXD10
97
CLK10
98
CTS10/RTS10
99
TA4IN/U
A15(/D15)
A14(/D14)
A13(/D13)
A12(/D12)
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
P3_6
TA4OUT/U
TA2IN/W
P3_5
P3_4
TA2OUT/W
P16_3
P16_2
P16_1
P16_0
P3_3
TXD9
RXD9
CLK9
CTS9/RTS9
TA1IN/V
A11(/D11)
A10(/D10)
A9(/D9)
D20
P3_2
TA1OUT/V
TA3OUT
P3_1
UD0B/UD1B
P12_4
P12_3
P12_2
P12_1
P12_0
CTS6/RTS6/SS6
RXD6/SCL6/STXD6
CLK6
D19
D18
D17
TXD6/SDA6/SRXD6
D16
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 12 of 99
R32C/116A Group
1. Overview
Table 1.9
Pin Characteristics for the 176-pin Package (4/5)
Pin Control
Interrupt
Analog BusControl
Port
Timer Pin
UART Pin
Intelligent I/O Pin
No.
Pin
Pin
Pin
Pin
115
VCC
116
117
118
119
120
121
122
123
124
P3_0
TA0OUT
UD0A/UD1A
A8(/D8)
VSS
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
TXD10
RXD10
CLK10
AN2_7
AN2_6
AN2_5
AN2_4
AN2_3
AN2_2
AN2_1
A7(/D7)
A6(/D6)
A5(/D5)
A4(/D4)
A3(/D3)
A2(/D2)
CTS10/RTS10
TXD9
RXD9
CLK9
A1(/D1)/
BC2(/D1)
125
P2_0
CTS9/RTS9
AN2_0
A0(/D0)/
BC0(/D0)
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
P1_7 INT5
P1_6 INT4
P1_5 INT3
P1_4
IIO0_7/IIO1_7
IIO0_6/IIO1_6
IIO0_5/IIO1_5
IIO0_4/IIO1_4
IIO0_3/IIO1_3
IIO0_2/IIO1_2
IIO0_1/IIO1_1
IIO0_0/IIO1_0
D15
D14
D13
D12
D11
D10
D9
P1_3
P1_2
P1_1
P1_0
D8
P0_7
AN0_7
AN0_6
AN0_5
AN0_4
D7
P0_6
D6
P0_5
D5
P0_4
D4
P19_1
P11_4
P19_0
P11_3
P11_2
P11_1
P11_0
P18_7
P18_6
P18_5
P18_4
P18_3
P18_2
P0_3
BC3/WR3
CTS8/RTS8
RXD8
IIO1_3
IIO1_2
IIO1_1
IIO1_0
CS3/WR2
CS2
CLK8
CS1
TXD8
CS0
AN0_3
AN0_2
AN0_1
AN0_0
AN15_7
D3
D2
D1
D0
P0_2
P0_1
P0_0
P15_7
CTS6/RTS6/SS6
IIO0_7
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 13 of 99
R32C/116A Group
1. Overview
Table 1.10
Pin Characteristics for the 176-pin Package (5/5)
Pin Control
Interrupt
Analog BusControl
Port
Timer Pin
UART Pin
Intelligent I/O Pin
No.
Pin
Pin
Pin
Pin
156
P15_6
P15_5
P15_4
P15_3
P15_2
P15_1
CLK6
IIO0_6
AN15_6
AN15_5
AN15_4
AN15_3
AN15_2
AN15_1
157
158
159
160
161
RXD6/SCL6/STXD6
TXD6/SDA6/SRXD6
CTS7/RTS7
RXD7
IIO0_5
IIO0_4
IIO0_3
IIO0_2
IIO0_1
CLK7
162 VSS
163
P15_0
TXD7
IIO0_0
AN15_0
164 VCC
165
P10_7 KI3
P10_6 KI2
P10_5 KI1
P10_4 KI0
P10_3
AN_7
AN_6
AN_5
AN_4
AN_3
AN_2
AN_1
166
167
168
169
170
P10_2
171
P10_1
172 AVSS
173
P10_0
P9_7
AN_0
174 VREF
175 AVCC
176
RXD4/SCL4/STXD4
ADTRG
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 14 of 99
R32C/116A Group
1. Overview
(Note 1)
(Note 2)
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
IIO0_0 / IIO1_0 / D8 / P1_0
P4_4 / CS3 / A20 / CTS6 / RTS6 / SS6
P4_5 / CS2 / A21 / CLK6
P4_6 / CS1 / A22 / RXD6 / SCL6 / STXD6
P4_7 / CS0 / A23 / TXD6 / SDA6 / SRXD6
P12_5 / D21
AN0_7 / D7 / P0_7
AN0_6 / D6 / P0_6
AN0_5 / D5 / P0_5
AN0_4 / D4 / P0_4
WR3 / BC3 / P11_4
P12_6 / D22
IIO1_3 / CTS8 / RTS8 / WR2 / CS3 / P11_3
IIO1_2 / RXD8 / CS2 / P11_2
IIO1_1 / CLK8 / CS1 / P11_1
IIO1_0 / TXD8 / CS0 / P11_0
AN0_3 / D3 / P0_3
P12_7 / D23
P5_0 / WR0 / WR
P5_1 / WR1 / BC1
P5_2 / RD
P5_3 / CLKOUT / BCLK
P13_0 / D24 / OUTC2_4
P13_1 / D25 / OUTC2_5
VCC
AN0_2 / D2 / P0_2
AN0_1 / D1 / P0_1
AN0_0 / D0 / P0_0
IIO0_7 / CTS6 / RTS6 / SS6 / AN15_7 / P15_7
IIO0_6 / CLK6 / AN15_6 / P15_6
IIO0_5 / RXD6 / SCL6 / STXD6 / AN15_5 / P15_5
IIO0_4 / TXD6 / SDA6 / SRXD6 / AN15_4 / P15_4
IIO0_3 / CTS7 / RTS7 / AN15_3 / P15_3
IIO0_2 / RXD7 / AN15_2 / P15_2
IIO0_1 / CLK7 / AN15_1 / P15_1
VSS
P13_2 / D26 / OUTC2_6
VSS
R32C/116A GROUP
(Note 2)
P13_3 / D27 / OUTC2_3
P5_4 / HLDA / CS1 / TXD7
P5_5 / HOLD / CLK7
PLQP0144KA-A
(144P6Q-A)
(Top view)
P5_6 / ALE / CS2 / RXD7
P5_7 / RDY / CS3 / CTS7 / RTS7
P13_4 / D28 / OUTC2_0 / ISTXD2 / IEOUT
P13_5 / D29 / OUTC2_2 / ISRXD2 / IEIN
P13_6 / D30 / OUTC2_1 / ISCLK2
P13_7 / D31 / OUTC2_7
P6_0 / TB0IN / CTS0 / RTS0 / SS0
P6_1 / TB1IN / CLK0
IIO0_0 / TXD7 / AN15_0 / P15_0
VCC
KI3 / AN_7 / P10_7
KI2 / AN_6 / P10_6
KI1 / AN_5 / P10_5
KI0 / AN_4 / P10_4
P6_2 / TB2IN / RXD0 / SCL0 / STXD0
P6_3 / TXD0 / SDA0 / SRXD0
AN_3 / P10_3
AN_2 / P10_2
P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2
AN_1 / P10_1
P6_5 / CLK1
AVSS
P11_7
AN_0 / P10_0
P6_6 / RXD1 / SCL1 / STXD1
P14_7
VREF
AVCC
P6_7 / TXD1 / SDA1 / SRXD1
STXD4 / SCL4 / RXD4 / ADTRG / P9_7
P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT / MSDA
(Note 3)
(Note 2)
Notes:
1. Pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins.
2. The following pins are 5 V tolerant inputs: P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_3, P12_0 to P12_7.
3. The position of pin number 1 varies by product. Refer to the index mark in attached “Package Dimensions”.
Figure 1.4
Pin Assignment for the 144-pin Package (top view)
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 15 of 99
R32C/116A Group
1. Overview
Table 1.11
Pin Characteristics for the 144-pin Package (1/4)
Pin Control
Interrupt
Analog BusControl
Port
Timer Pin
UART Pin
Intelligent I/O Pin
No.
Pin
Pin
Pin
ANEX1
ANEX0
DA1
Pin
1
2
3
4
5
P9_6
P9_5
P9_4
P9_3
P9_2
TXD4/SDA4/SRXD4
CLK4
TB4IN
TB3IN
TB2IN
CTS4/RTS4/SS4
CTS3/RTS3/SS3
TXD3/SDA3/SRXD3
DA0
OUTC2_0/ISTXD2/
IEOUT
6
7
8
9
P9_1
P9_0
TB1IN
TB0IN
RXD3/SCL3/STXD3
CLK3
ISRXD2/IEIN
P14_6 INT8
P14_5 INT7
P14_4 INT6
P14_3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VDC0
P14_1
VDC1
NSD
CNVSS
XCIN
P8_7
XCOUT P8_6
RESET
XOUT
VSS
XIN
VCC
P8_5 NMI
P8_4 INT2
P8_3 INT1
P8_2 INT0
P8_1
TA4IN/U
CTS5/RTS5/SS5
IIO1_5/UD0B/UD1B
UD0A/UD1A
P8_0
TA4OUT/U RXD5/SCL5/STXD5
P7_7
TA3IN
CLK5
IIO1_4/UD0B/UD1B
IIO1_3/UD0A/UD1A
P7_6
TA3OUT
TXD5/SDA5/SRXD5/
CTS8/RTS8
32
33
34
35
36
P7_5
P7_4
P7_3
P7_2
P7_1
TA2IN/W
RXD8
IIO1_2
IIO1_1
TA2OUT/W CLK8
TA1IN/V
CTS2/RTS2/SS2/TXD8 IIO1_0
TA1OUT/V CLK2
TB5IN/
TA0IN
RXD2/SCL2/STXD2/
MSCL
IIO1_7/OUTC2_2/
ISRXD2/IEIN
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 16 of 99
R32C/116A Group
1. Overview
Table 1.12
Pin Characteristics for the 144-pin Package (2/4)
Pin Control
Interrupt
Analog BusControl
Pin Pin
Port
Timer Pin
TA0OUT
UART Pin
Intelligent I/O Pin
No.
Pin
Pin
37
P7_0
TXD2/SDA2/SRXD2/
MSDA
IIO1_6/OUTC2_0/
ISTXD2/IEOUT
38
39
40
41
42
43
44
45
46
47
48
49
50
P6_7
P14_7
P6_6
P11_7
P6_5
P6_4
P6_3
P6_2
P6_1
P6_0
P13_7
P13_6
P13_5
TXD1/SDA1/SRXD1
RXD1/SCL1/STXD1
CLK1
CTS1/RTS1/SS1
TXD0/SDA0/SRXD0
RXD0/SCL0/STXD0
CLK0
OUTC2_1/ISCLK2
TB2IN
TB1IN
TB0IN
CTS0/RTS0/SS0
OUTC2_7
D31
D30
D29
OUTC2_1/ISCLK2
OUTC2_2/ISRXD2/
IEIN
51
P13_4
OUTC2_0/ISTXD2/
IEOUT
D28
52
53
54
55
56
57
58
59
60
61
62
P5_7
P5_6
P5_5
P5_4
P13_3
CTS7/RTS7
RXD7
RDY/CS3
ALE/CS2
HOLD
CLK7
TXD7
HLDA/CS1
D27
OUTC2_3
OUTC2_6
VSS
P13_2
D26
VCC
P13_1
P13_0
P5_3
OUTC2_5
OUTC2_4
D25
D24
CLKOUT/
BCLK
63
64
65
66
67
68
69
70
71
72
73
P5_2
P5_1
P5_0
P12_7
P12_6
P12_5
P4_7
P4_6
P4_5
P4_4
P4_3
RD
WR1/BC1
WR0/WR
D23
D22
D21
TXD6/SDA6/SRXD6
RXD6/SCL6/STXD6
CLK6
CS0/A23
CS1/A22
CS2/A21
CS3/A20
A19
CTS6/RTS6/SS6
TXD3/SDA3/SRXD3
OUTC2_0/ISTXD2/
IEOUT
74
P11_6
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 17 of 99
R32C/116A Group
1. Overview
Table 1.13
Pin Characteristics for the 144-pin Package (3/4)
Pin Control
Interrupt
Analog BusControl
Port
Timer Pin
UART Pin
Intelligent I/O Pin
ISRXD2/IEIN
No.
Pin
Pin
Pin
Pin
75
P4_2
P11_5
P4_1
P4_0
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
P12_4
P12_3
P12_2
P12_1
P12_0
RXD3/SCL3/STXD3
A18
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
CLK3
A17
A16
CTS3/RTS3/SS3
TA4IN/U
A15(/D15)
A14(/D14)
A13(/D13)
A12(/D12)
A11(/D11)
A10(/D10)
A9(/D9)
D20
TA4OUT/U
TA2IN/W
TA2OUT/W
TA1IN/V
TA1OUT/V
TA3OUT
UD0B/UD1B
CTS6/RTS6/SS6
RXD6/SCL6/STXD6
CLK6
D19
D18
D17
TXD6/SDA6/SRXD6
D16
VCC
P3_0
TA0OUT
UD0A/UD1A
A8(/D8)
VSS
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
TXD10
RXD10
CLK10
AN2_7
AN2_6
AN2_5
AN2_4
AN2_3
AN2_2
AN2_1
A7(/D7)
A6(/D6)
A5(/D5)
A4(/D4)
A3(/D3)
A2(/D2)
CTS10/RTS10
TXD9
RXD9
CLK9
A1(/D1)/
BC2(/D1)
101
P2_0
CTS9/RTS9
AN2_0
A0(/D0)/
BC0(/D0)
102
103
104
105
106
107
108
109
110
111
P1_7 INT5
P1_6 INT4
P1_5 INT3
P1_4
IIO0_7/IIO1_7
IIO0_6/IIO1_6
IIO0_5/IIO1_5
IIO0_4/IIO1_4
IIO0_3/IIO1_3
IIO0_2/IIO1_2
IIO0_1/IIO1_1
IIO0_0/IIO1_0
D15
D14
D13
D12
D11
D10
D9
P1_3
P1_2
P1_1
P1_0
D8
P0_7
AN0_7
AN0_6
D7
P0_6
D6
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 18 of 99
R32C/116A Group
1. Overview
Table 1.14
Pin Characteristics for the 144-pin Package (4/4)
Pin Control
Interrupt
Analog BusControl
Port
Timer Pin
UART Pin
Intelligent I/O Pin
No.
Pin
Pin
Pin
AN0_5
AN0_4
Pin
112
P0_5
D5
D4
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
P0_4
P11_4
P11_3
P11_2
P11_1
P11_0
P0_3
BC3/WR3
CS3/WR2
CS2
CTS8/RTS8
IIO1_3
RXD8
CLK8
TXD8
IIO1_2
IIO1_1
IIO1_0
CS1
CS0
AN0_3
D3
P0_2
AN0_2
D2
P0_1
AN0_1
D1
P0_0
AN0_0
D0
P15_7
P15_6
P15_5
P15_4
P15_3
P15_2
P15_1
CTS6/RTS6/SS6
CLK6
IIO0_7
IIO0_6
IIO0_5
IIO0_4
IIO0_3
IIO0_2
IIO0_1
AN15_7
AN15_6
AN15_5
AN15_4
AN15_3
AN15_2
AN15_1
RXD6/SCL6/STXD6
TXD6/SDA6/SRXD6
CTS7/RTS7
RXD7
CLK7
130 VSS
131
P15_0
TXD7
IIO0_0
AN15_0
132 VCC
133
P10_7 KI3
P10_6 KI2
P10_5 KI1
P10_4 KI0
P10_3
AN_7
AN_6
AN_5
AN_4
AN_3
AN_2
AN_1
134
135
136
137
138
P10_2
139
P10_1
140 AVSS
141
P10_0
P9_7
AN_0
142 VREF
143 AVCC
144
RXD4/SCL4/STXD4
ADTRG
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 19 of 99
R32C/116A Group
1. Overview
1.5
Pin Definitions and Functions
Table 1.15 to Table 1.19 show the pin definitions and functions.
Table 1.15
Function
Power supply
Pin Definitions and Functions (1/4)
Symbol
VCC, VSS
I/O
I
Description
Applicable as follows: VCC = 3.0 to 5.5 V, VSS = 0 V
Connecting pins VDC0, VDC1
for decoupling
A decoupling capacitor for internal voltage should be
connected between VDC0 and VDC1
—
capacitor
Analog power
supply
AVCC, AVSS
Power supply for the A/D converter. AVCC and AVSS
should be connected to VCC and VSS, respectively
I
Reset input
CNVSS
RESET
CNVSS
NSD
I
I
The MCU is reset when this pin is driven low
This pin should be connected to VSS via a resistor
Debug port
This pin is to communicate with a debugger. It should be
connected to VCC via a resistor of 1 to 4.7 kΩ
I/O
Main clock input XIN
Input/output for the main clock oscillator. A crystal, or a
ceramic resonator should be connected between pins XIN
and XOUT. An external clock should be input at the XIN
while leaving the XOUT open
I
O
I
Main clock output XOUT
Sub clock input
XCIN
Input/output for the sub clock oscillator. A crystal oscillator
should be connected between pins XCIN and XCOUT. An
external clock should be input at the XCIN while leaving the
XCOUT open
Sub clock output XCOUT
O
O
BCLK output
Clock output
BCLK
BCLK output
CLKOUT
Output of the clock with the same frequency as low speed
clocks, f8, or f32
O
I
External interrupt INT0 to INT8
input
Input for external interrupts
NMI input
P8_5/NMI
I
I
Input for NMI
Key input interrupt KI0 to KI3
Input for the key input interrupt
Bus control pins D0 to D7
Input/output of data (D0 to D7) while accessing an external
memory space with a separate bus
I/O
I/O
D8 to D15
D16 to D31
A0 to A23
Input/output of data (D8 to D15) while accessing an
external memory space with 16-bit or 32-bit separate bus
Input/output of data (D16 to D31) while accessing an
external memory space with 32-bit separate bus
I/O
O
Output of address bits A0 to A23
A0/D0 to A7/D7
Output of address bits (A0 to A7) and input/output of data
I/O (D0 to D7) by time-division while accessing an external
memory space with multiplexed bus
A8/D8 to
A15/D15
Output of address bits (A8 to A15) and input/output of data
I/O (D8 to D15) by time-division while accessing an external
memory space with 16-bit or 32-bit multiplexed bus
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R32C/116A Group
1. Overview
Table 1.16
Pin Definitions and Functions (2/4)
Symbol I/O
Function
Description
Output of byte control (BC0 and BC2) and input/output of
Bus control pins BC0/D0, BC2/D1
I/O data (D0 and D1) by time-division while accessing an
external memory space with multiplexed bus
CS0 to CS3
O
Chip select output
WR0/WR1/WR2/
WR3,
WR/BC0/BC1/
BC2/BC3,
RD
Output of write, byte control, and read signals. Either WRx
or WR and BCx can be selected by a program.
Data is read when RD is low.
• When WR0, WR1, WR2, WR3, and RD are selected,
data is written to the following address:
4n+0, when WR0 is low
4n+1, when WR1 is low
4n+2, when WR2 is low
4n+3, when WR3 is low
on 32-bit external data bus
or
an even address, when WR0 is low
an odd address, when WR1 is low
on 16-bit external data bus
O
• When WR, BC0, BC1, BC2, BC3, and RD are selected,
data is written, when WR is low
and
the following address is accessed:
4n+0, when BC0 is low
4n+1, when BC1 is low
4n+2, when BC2 is low
4n+3, when BC3 is low
on 32-bit external data bus
or
an even address, when BC0 is low
an odd address, when BC1 is low
on 16-bit external data bus
ALE
O
I
Latch enable signal in multiplexed bus format
HOLD
HLDA
RDY
The MCU is in a hold state while this pin is held low
This pin is driven low while the MCU is held in a hold state
O
Bus cycle is extended by the CPU if this pin is low on the
falling edge of the BCLK
I
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R32C/116A Group
1. Overview
Table 1.17
Pin Definitions and Functions (3/4)
Function
Symbol
I/O
Description
(1)
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_7,
P4_0 to P4_7,
P5_0 to P5_7,
P6_0 to P6_7,
P7_0 to P7_7,
P8_0 to P8_4,
P8_6, P8_7,
I/O ports in CMOS. Each port can be programmed to input
or output under the control of the direction register.
Some ports are 5 V tolerant inputs.
Pull-up resistors and N-channel open drain setting can be
enabled on some ports. Refer to Table 1.19 “Pin
Specifications” for details
I/O port
P9_0 to P9_7,
P10_0 to P10_7,
P11_0 to P11_7,
P12_0 to P12_7,
P13_0 to P13_7,
P14_3 to P14_7,
P15_0 to P15_7,
P16_0 to P16_7,
P17_0 to P17_7,
P18_0 to P18_7,
P19_0 to P19_7
I/O
Input port
Timer A
P14_1
Input port in CMOS
Pull-up resistor is selectable.
Refer to Table 1.19 “Pin Specifications” for details
I
TA0OUT to
TA4OUT
Timers A0 to A4 input/output
I/O
TA0IN to TA4IN
TB0IN to TB5IN
U, U, V, V, W, W
I
I
Timers A0 to A4 input
Timer B
Timers B0 to B5 input
Three-phase
motor control
timer output
Three-phase motor control timer output
O
Serial interface
CTS0 to CTS10
RTS0 to RTS10
CLK0 to CLK10
RXD0 to RXD10
TXD0 to TXD10
SDA0 to SDA6
SCL0 to SCL6
STXD0 to
I
Handshake input
Handshake output
O
I/O Transmit/receive clock input/output
I
Serial data input
Serial data output
O
2
I/O Serial data input/output
I C bus
(simplified)
I/O Transmit/receive clock input/output
Serial interface
special functions STXD6
Serial data output in slave mode
O
SRXD0 to
SRXD6
Serial data input in slave mode
I
SS0 to SS6
I
Input to control serial interface special functions
Note:
1. Ports P16 to P19 are available in the 176-pin package only.
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Page 22 of 99
R32C/116A Group
1. Overview
Table 1.18
Function
Pin Definitions and Functions (4/4)
Symbol
I/O
Description
A/D converter
AN_0 to AN_7,
AN0_0 to AN0_7,
AN2_0 to AN2_7,
AN15_0 to
Analog input for the A/D converter
I
AN15_7
ADTRG
I
External trigger input for the A/D converter
ANEX0
Expanded analog input for the A/D converter and output in
external op-amp connection mode
I/O
ANEX1
I
Expanded analog input for the A/D converter
Output for the D/A converter
D/A converter
DA0, DA1
O
Referencevoltage VREF
input
Reference voltage input for the A/D converter and D/A
converter
I
Intelligent I/O
IIO0_0 to IIO0_7
Input/output for the Intelligent I/O group 0. Either input
capture or output compare is selectable
I/O
I/O
I
IIO1_0 to IIO1_7
Input/output for the Intelligent I/O group 1. Either input
capture or output compare is selectable
UD0A, UD0B,
UD1A, UD1B
Input for the two-phase encoder
OUTC2_0 to
OUTC2_7
Output for OC (output compare) of the Intelligent I/O group
2
O
ISCLK2
ISRXD2
ISTXD2
IEIN
I/O Clock input/output for the serial interface
I
Receive data input for the serial interface
Transmit data output for the serial interface
Receive data input for the serial interface
Transmit data output for the serial interface
O
I
IEOUT
MSDA
MSCL
O
2
I/O Serial data input/output
Multi-master I C-
bus
I/O Transmit/receive clock input/output
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R32C/116A Group
1. Overview
Table 1.19
Pin Specifications
Package
176- 144-
Selectable Functions
(3)
Pin names
5 V tolerant input
N-channel
(1)
Pull-up resistor
(2)
pin
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
pin
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
open drain
P0_0 to P0_7
3
3
3
3
P1_0 to P1_7
P2_0 to P2_7
P3_0 to P3_7
P4_0 to P4_7
3
3
P5_0 to P5_3
3
P5_4 to P5_7
3
3
3
3
3
3
3
3
P6_0 to P6_7
P7_0 to P7_7
P8_0 to P8_3
P8_4, P8_6, P8_7
P9_0 to P9_7
3
3
3
3
3
3
3
3
P10_0 to P10_7
P11_0 to P11_3
P11_4 to P11_7
P12_0 to P12_7
P13_0 to P13_7
P14_1, P14_3
P14_4 to P14_7
P15_0 to P15_7
P16_0 to P16_7
P17_0 to P17_3
P17_4 to P17_7
P18_0 to P18_7
P19_0 to P19_7
3
3
3
3
3
3
3
3
3
3
3
3
3
Notes:
1. Pull-up resistors are selected in 4-pin units, but are only enabled for those pins set as input ports.
2. N-channel open drain output can be enabled on the applicable pins on a discrete pin basis.
3. 5 V tolerant input is enabled when an applicable pin is set as an input port. When it is set as an I/O
port, to enable 5 V tolerant input, this pin should be set as N-channel open drain output.
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R32C/116A Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
The CPU contains registers as shown below. There are two register banks each consisting of registers
R2R0, R3R1, R6R4, R7R5, A0 to A3, SB, and FB.
General purpose
registers
b31
b23
b15
b7
b0
R2R0
R3R1
R6R4
R7R5
R2H
R2L
R3L
R0H
R1H
R0L
R1L
R3H
Data registers (1)
R6
R7
R4
R5
A0
A1
A2
A3
SB
FB
Address registers (1)
Static base register (1)
Frame base register (1)
USP
ISP
User stack pointer
Interrupt stack pointer
Interrupt vector table base register
Program counter
INTB
PC
FLG
Flag register
b31
b24 b23
b16 b15
b8 b7
b0
RND
IPL
U I O B S Z D C
DP
FU
FO
Blank fields represent reserved.
b31
b31
b0
Fast interrupt
registers
SVF
SVP
VCT
Save flag register
Save PC register
Vector register
b23
b0
DMAC-associated
registers (2)
DMD0
DMA mode register
DCT0
DMA terminal count register
DMA terminal count reload register
DMA source address register
DMA source address reload register
DMA destination address register
DCR0
DSA0
DSR0
DDA0
DDR0
DMA destination address reload register
Notes:
1.There are two banks of these registers.
2.There are four identical sets of DMAC-associated registers.
Figure 2.1
CPU Registers
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R32C/116A Group
2. Central Processing Unit (CPU)
2.1
2.1.1
General Purpose Registers
Data Registers (R2R0, R3R1, R6R4, and R7R5)
These 32-bit registers are primarily used for transfers and arithmetic/logic operations.
Each of the registers can be divided into upper and lower 16-bit registers, e.g. R2R0 can be divided into
R2 and R0, R3R0 can be divided into R3 and R1, etc.
Moreover, data registers R2R0 and R3R1 can be divided into four 8-bit data registers: upper (R2H and
R3H), mid-upper (R2L and R3L), mid-lower (R0H and R1H), and lower (R0L and R1L).
2.1.2
Address Registers (A0, A1, A2, and A3)
These 32-bit registers have functions similar to data registers. They are also used for address register
indirect addressing and address register relative addressing.
2.1.3
Static Base Register (SB)
This 32-bit register is used for SB relative addressing.
2.1.4
Frame Base Register (FB)
This 32-bit register is used for FB relative addressing.
2.1.5
Program Counter (PC)
This 32-bit counter indicates the address of the instruction to be executed next.
2.1.6
Interrupt Vector Table Base Register (INTB)
This 32-bit register indicates the start address of a relocatable vector table.
2.1.7
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Two types of 32-bit stack pointers (SPs) are provided: user stack pointer (USP) and interrupt stack
pointer (ISP).
Use the stack pointer select flag (U flag) to select either the user stack pointer (USP) or the interrupt
stack pointer (ISP). The U flag is bit 7 in the flag register (FLG). Refer to 2.1.8 “Flag Register (FLG)” for
details.
To minimize the overhead of interrupt sequence due to less memory access, set the user stack pointer
(USP) or the interrupt stack pointer (ISP) to a multiple of 4.
2.1.8
Flag Register (FLG)
This 32-bit register indicates the CPU status.
2.1.8.1
Carry Flag (C flag)
This flag becomes 1 when any of the carry, borrow, shifted-out bit, etc. is generated in the arithmetic
logic unit (ALU).
2.1.8.2
Debug Flag (D flag)
This flag is only for debugging. Only set this bit to 0.
2.1.8.3
Zero Flag (Z flag)
This flag becomes 1 when the result of an operation is 0; otherwise it is 0.
2.1.8.4
Sign Flag (S flag)
This flag becomes 1 when the result of an operation is a negative value; otherwise it is 0.
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R32C/116A Group
2. Central Processing Unit (CPU)
2.1.8.5
Register Bank Select Flag (B flag)
This flag selects a register bank. It indicates 0 when the register bank 0 is selected, and 1 when the
register bank 1 is selected.
2.1.8.6
Overflow Flag (O flag)
This flag becomes 1 if an overflow occurs in an operation; otherwise it is 0.
2.1.8.7
Interrupt Enable Flag (I flag)
This flag enables maskable interrupts. To disable maskable interrupts, set this flag to 0. To enable
them, set this flag to 1. When an interrupt is accepted, the flag becomes 0.
2.1.8.8
Stack Pointer Select Flag (U flag)
To select the interrupt stack pointer (ISP), set this flag to 0. To select the user stack pointer (USP), set
this flag to 1.
It becomes 0 when a hardware interrupts is accepted or when an INT instruction designated by a
software interrupt number from 0 to 127 is executed.
2.1.8.9
Floating-point Underflow Flag (FU flag)
This flag becomes 1 when an underflow occurs in a floating-point operation; otherwise it is 0. It also
becomes 1 when the operand has invalid numbers (subnormal numbers).
2.1.8.10 Floating-point Overflow Flag (FO flag)
This flag becomes 1 when an overflow occurs in a floating-point operation; otherwise it is 0. It also
becomes 1 when the operand has invalid numbers (subnormal numbers).
2.1.8.11 Processor Interrupt Priority Level (IPL)
The processor interrupt priority level (IPL), consisting of three bits, selects a processor interrupt priority
level from level 0 to 7. An interrupt is acceptable when the interrupt request level is higher than the
selected IPL.
When the processor interrupt priority level (IPL) is set to 111b (level 7), all interrupts are disabled.
2.1.8.12 Fixed-point Radix Point Designation Bit (DP bit)
This bit designates the radix point. It also specifies which portion of the fixed-point multiplication result
to take. It is used in the MULX instruction.
2.1.8.13 Floating-point Rounding Mode (RND)
The 2-bit floating-point rounding mode selects a rounding mode for floating-point calculation results.
2.1.8.14 Reserved
Only set this bit to 0. The read value is undefined.
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R32C/116A Group
2. Central Processing Unit (CPU)
2.2
Fast Interrupt Registers
The following three registers are provided to minimize the overhead of interrupt sequence.
2.2.1
Save Flag Register (SVF)
This 32-bit register is used to save the flag register when a fast interrupt is generated.
2.2.2
Save PC Register (SVP)
This 32-bit register is used to save the program counter when a fast interrupt is generated.
2.2.3
Vector Register (VCT)
This 32-bit register is used to indicate a jump address when a fast interrupt is generated.
2.3
DMAC-associated Registers
There are seven types of DMAC-associated registers.
2.3.1
DMA Mode Registers (DMD0, DMD1, DMD2, and DMD3)
These 32-bit registers are used to set DMA transfer mode, bit rate, etc.
2.3.2
DMA Terminal Count Registers (DCT0, DCT1, DCT2, and DCT3)
These 24-bit registers are used to set DMA transfer counting.
2.3.3
DMA Terminal Count Reload Registers (DCR0, DCR1, DCR2, and DCR3)
These 24-bit registers are used to set the reloaded values for DMA terminal count registers.
2.3.4
DMA Source Address Registers (DSA0, DSA1, DSA2, and DSA3)
These 32-bit registers are used to set DMA source addresses.
2.3.5
DMA Source Address Reload Registers (DSR0, DSR1, DSR2, and DSR3)
These 32-bit registers are used to set the reloaded value for DMA source address register.
2.3.6
DMA Destination Address Registers (DDA0, DDA1, DDA2, and DDA3)
These 32-bit registers are used to set DMA destination address.
2.3.7
DMA Destination Address Reload Registers (DDR0, DDR1, DDR2, and
DDR3)
These 32-bit registers are used to set reloaded values for DMA destination address registers.
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R32C/116A Group
3. Memory
3. Memory
Figure 3.1 shows the memory map of the R32C/116A Group.
The R32C/116A Group provides a 4-Gbyte address space from 00000000h to FFFFFFFFh.
The internal ROM is mapped to the end of the memory map with the ending address fixed at FFFFFFFFh.
Therefore, the 1-Mbyte internal ROM is mapped from FFF00000h to FFFFFFFFh.
The fixed interrupt vector table which contains each start address of interrupt handlers is mapped from
FFFFFFDCh to FFFFFFFFh.
The internal RAM is mapped to the beginning of the memory map with the starting address fixed at
00000400h. Therefore, the 96-Kbyte internal RAM is mapped from 00000400h to 000183FFh. Besides
being used for data storage, the internal RAM functions as a stack(s) for subroutines and/or interrupt
handlers.
Special Function Registers (SFRs), which are control registers for peripheral functions, are mapped from
00000000h to 000003FFh, and from 00040000h to 0004FFFFh. Unoccupied SFR locations are reserved.
No access is allowed.
In memory expansion mode or microprocessor mode, some spaces are reserved for internal use and should
not be accessed.
00000000h
SFR1
00000400h
Internal RAM
00018400h
Reserved
00040000h
SFR2
00050000h
Reserved
00060000h
Internal ROM
(Data space) (1)
00062000h
Reserved
Internal ROM
FFFFFFDCh
Undefined instruction
Overflow
00080000h
FFE00000h
Capacity YYYYYYYYh
512 Kbytes FFF80000h
640 Kbytes FFF60000h
768 Kbytes FFF40000h
External space (2)
BRK instruction
Reserved
Reserved
Watchdog timer (5)
Reserved (3)
1 Mbyte
FFF00000h
Reserved
YYYYYYYYh
FFFFFFFFh
NMI
Internal ROM (4)
Reset
FFFFFFFFh
Notes:
1. Additional two 4-Kbyte spaces (blocks A and B) for storing data are provided in the flash memory version.
2. This space can be used in memory expansion mode or microprocessor mode. Addresses from 02000000h
to FDFFFFFFh are inaccessible.
3. This space is reserved in memory expansion mode. It can be external space in microprocessor mode.
4. This space can be used in single-chip mode or memory expansion mode. It can be external space in
microprocessor mode.
5. The watchdog timer interrupt shares the vector table with the oscillator stop detection interrupt and low
voltage detection interrupt.
Figure 3.1
Memory Map
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R32C/116A Group
4. Special Function Registers (SFRs)
4. Special Function Registers (SFRs)
SFRs are memory-mapped peripheral registers that control the operation of peripherals. Table 4.1 SFR List
(1) to Table 4.27 SFR List (27) list the SFR details.
Table 4.1
Address
000000h
000001h
000002h
000003h
SFR List (1)
Register
Symbol
Reset Value
000004h Clock Control Register
000005h
CCR
0001 1000b
000006h Flash Memory Control Register
000007h Protect Release Register
FMCR
PRR
0000 0001b
00h
000008h Flash Memory Rewrite Bus Control Register
FEBC
0000h
000009h
00000Ah
00000Bh
00000Ch
00000Dh
00000Eh
00000Fh
000010h External Bus Control Register 3
000011h
000012h Chip Selects 2 and 3 Boundary Setting Register
000013h
000014h External Bus Control Register 2
000015h
000016h Chip Selects 1 and 2 Boundary Setting Register
000017h
000018h External Bus Control Register 1
000019h
00001Ah Chip selects 0 and 1 Boundary Setting Register
00001Bh
00001Ch External Bus Control Register 0
00001Dh
00001Eh Peripheral Bus Control Register
EBC3
CB23
EBC2
CB12
EBC1
CB01
EBC0
PBC
0000h
00h
0000h
00h
0000h
00h
0000h
0504h
00001Fh
000020h to
00005Fh
X: Undefined
Blanks are reserved. No access is allowed.
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R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.2
Address
SFR List (2)
Register
Symbol
Reset Value
000060h
000061h Timer B5 Interrupt Control Register
000062h UART5 Transmit/NACK Interrupt Control Register
TB5IC
S5TIC
S2RIC/I2CLIC
XXXX X000b
XXXX X000b
XXXX X000b
UART2 Receive/ACK Interrupt Control Register/I2C Bus Line
Interrupt Control Register
000063h
000064h UART6 Transmit/NACK Interrupt Control Register
000065h UART3 Receive/ACK Interrupt Control Register
000066h UART5/6 Bus Collision, Start Condition/Stop Condition
Detection Interrupt Control Register
S6TIC
S3RIC
BCN5IC/BCN6IC
XXXX X000b
XXXX X000b
XXXX X000b
000067h UART4 Receive/ACK Interrupt Control Register
000068h DMA0 Transfer Complete Interrupt Control Register
000069h UART0/3 Bus Collision, Start Condition/Stop Condition
Detection Interrupt Control Register
S4RIC
DM0IC
BCN0IC/BCN3IC
XXXX X000b
XXXX X000b
XXXX X000b
00006Ah DMA2 Transfer Complete Interrupt Control Register
00006Bh A/D Converter 0 Convert Completion Interrupt Control Register
00006Ch Timer A0 Interrupt Control Register
00006Dh Intelligent I/O Interrupt Control Register 0
00006Eh Timer A2 Interrupt Control Register
00006Fh Intelligent I/O Interrupt Control Register 2
000070h Timer A4 Interrupt Control Register
000071h Intelligent I/O Interrupt Control Register 4
000072h UART0 Receive/ACK Interrupt Control Register
000073h Intelligent I/O Interrupt Control Register 6
000074h UART1 Receive/ACK Interrupt Control Register
000075h Intelligent I/O Interrupt Control Register 8
000076h Timer B1 Interrupt Control Register
000077h Intelligent I/O Interrupt Control Register 10
000078h Timer B3 Interrupt Control Register
000079h
DM2IC
AD0IC
TA0IC
IIO0IC
TA2IC
IIO2IC
TA4IC
IIO4IC
S0RIC
IIO6IC
S1RIC
IIO8IC
TB1IC
IIO10IC
TB3IC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
00007Ah INT5 Interrupt Control Register
00007Bh
00007Ch INT3 Interrupt Control Register
00007Dh
00007Eh INT1 Interrupt Control Register
00007Fh
INT5IC
INT3IC
INT1IC
XX00 X000b
XX00 X000b
XX00 X000b
000080h
UART2 Transmit/NACK Interrupt Control Register/I2C-Bus
Interrupt Control Register
000081h
S2TIC/I2CIC
XXXX X000b
000082h UART5 Receive/ACK Interrupt Control Register
000083h UART3 Transmit/NACK Interrupt Control Register
000084h UART6 Receive/ACK Interrupt Control Register
000085h UART4 Transmit/NACK Interrupt Control Register
000086h
S5RIC
S3TIC
S6RIC
S4TIC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
000087h UART2 Bus Collision, Start Condition/Stop Condition Detection BCN2IC
XXXX X000b
Interrupt Control Register
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 31 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.3
SFR List (3)
Address
Register
Symbol
DM1IC
BCN1IC/BCN4IC
Reset Value
XXXX X000b
XXXX X000b
000088h DMA1 Transfer Complete Interrupt Control Register
000089h UART1/4 Bus Collision, Start Condition/Stop Condition
Detection Interrupt Control Register
00008Ah DMA3 Transfer Complete Interrupt Control Register
00008Bh Key Input Interrupt Control Register
00008Ch Timer A1 Interrupt Control Register
00008Dh Intelligent I/O Interrupt Control Register 1
00008Eh Timer A3 Interrupt Control Register
00008Fh Intelligent I/O Interrupt Control Register 3
000090h UART0 Transmit/NACK Interrupt Control Register
000091h Intelligent I/O Interrupt Control Register 5
000092h UART1 Transmit/NACK Interrupt Control Register
000093h Intelligent I/O Interrupt Control Register 7
000094h Timer B0 Interrupt Control Register
000095h Intelligent I/O Interrupt Control Register 9
000096h Timer B2 Interrupt Control Register
000097h Intelligent I/O Interrupt Control Register 11
000098h Timer B4 Interrupt Control Register
000099h
DM3IC
KUPIC
TA1IC
IIO1IC
TA3IC
IIO3IC
S0TIC
IIO5IC
S1TIC
IIO7IC
TB0IC
IIO9IC
TB2IC
IIO11IC
TB4IC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
00009Ah INT4 Interrupt Control Register
00009Bh
00009Ch INT2 Interrupt Control Register
00009Dh
00009Eh INT0 Interrupt Control Register
00009Fh
INT4IC
INT2IC
INT0IC
XX00 X000b
XX00 X000b
XX00 X000b
0000A0h Intelligent I/O Interrupt Request Register 0
0000A1h Intelligent I/O Interrupt Request Register 1
0000A2h Intelligent I/O Interrupt Request Register 2
0000A3h Intelligent I/O Interrupt Request Register 3
0000A4h Intelligent I/O Interrupt Request Register 4
0000A5h Intelligent I/O Interrupt Request Register 5
0000A6h Intelligent I/O Interrupt Request Register 6
0000A7h Intelligent I/O Interrupt Request Register 7
0000A8h Intelligent I/O Interrupt Request Register 8
0000A9h Intelligent I/O Interrupt Request Register 9
0000AAh Intelligent I/O Interrupt Request Register 10
0000ABh Intelligent I/O Interrupt Request Register 11
0000ACh
IIO0IR
IIO1IR
IIO2IR
IIO3IR
IIO4IR
IIO5IR
IIO6IR
IIO7IR
IIO8IR
IIO9IR
IIO10IR
IIO11IR
0000 0XX1b
0000 0XX1b
0000 0X01b
0000 XXX1b
000X 0XX1b
000X 0XX1b
000X 0XX1b
X00X 0XX1b
XX0X 0XX1b
0X00 0XX1b
0X00 0XX1b
0X00 0XX1b
0000ADh
0000AEh
0000AFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 32 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.4
SFR List (4)
Address
Register
Symbol
Reset Value
0000B0h Intelligent I/O Interrupt Enable Register 0
0000B1h Intelligent I/O Interrupt Enable Register 1
0000B2h Intelligent I/O Interrupt Enable Register 2
0000B3h Intelligent I/O Interrupt Enable Register 3
0000B4h Intelligent I/O Interrupt Enable Register 4
0000B5h Intelligent I/O Interrupt Enable Register 5
0000B6h Intelligent I/O Interrupt Enable Register 6
0000B7h Intelligent I/O Interrupt Enable Register 7
0000B8h Intelligent I/O Interrupt Enable Register 8
0000B9h Intelligent I/O Interrupt Enable Register 9
0000BAh Intelligent I/O Interrupt Enable Register 10
0000BBh Intelligent I/O Interrupt Enable Register 11
IIO0IE
IIO1IE
IIO2IE
IIO3IE
IIO4IE
IIO5IE
IIO6IE
IIO7IE
IIO8IE
IIO9IE
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
IIO10IE
IIO11IE
0000BCh
0000BDh
0000BEh
0000BFh
0000C0h
0000C1h
0000C2h
0000C3h
0000C4h
0000C5h
0000C6h
0000C7h
0000C8h
0000C9h
0000CAh
0000CBh
0000CCh
0000CDh
0000CEh
0000CFh
0000D0h
0000D1h
0000D2h
0000D3h
0000D4h
0000D5h
0000D6h
0000D7h
0000D8h
0000D9h UART9 Transmit Interrupt Control Register
0000DAh
0000DBh UART10 Transmit Interrupt Control Register
0000DCh
S9TIC
XXXX X000b
XXXX X000b
S10TIC
0000DDh UART7 Transmit Interrupt Control Register
0000DEh INT7 Interrupt Control Register
0000DFh UART8 Transmit Interrupt Control Register
X: Undefined
S7TIC
INT7IC
S8TIC
XXXX X000b
XX00 X000b
XXXX X000b
Blanks are reserved. No access is allowed.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 33 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.5
Address
0000E0h
0000E1h
0000E2h
0000E3h
0000E4h
0000E5h
0000E6h
0000E7h
0000E8h
0000E9h
0000EAh
0000EBh
0000ECh
0000EDh
0000EEh
0000EFh
0000F0h
0000F1h
0000F2h
0000F3h
0000F4h
0000F5h
0000F6h
0000F7h
0000F8h
SFR List (5)
Register
Symbol
Reset Value
0000F9h UART9 Receive Interrupt Control Register
0000FAh
S9RIC
XXXX X000b
0000FBh UART10 Receive Interrupt Control Register
0000FCh INT8 Interrupt Control Register
0000FDh UART7 Receive Interrupt Control Register
0000FEh INT6 Interrupt Control Register
0000FFh UART8 Receive Interrupt Control Register
S10RIC
INT8IC
S7RIC
INT6IC
S8RIC
XXXX X000b
XX00 X000b
XXXX X000b
XX00 X000b
XXXX X000b
XXXXh
000100h Group 1 Time Measurement/Waveform Generation Register 0 G1TM0/G1PO0
000101h
000102h Group 1 Time Measurement/Waveform Generation Register 1 G1TM1/G1PO1
000103h
000104h Group 1 Time Measurement/Waveform Generation Register 2 G1TM2/G1PO2
000105h
XXXXh
XXXXh
XXXXh
000106h Group 1 Time Measurement/Waveform Generation Register 3 G1TM3/G1PO3
000107h
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 34 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.6
SFR List (6)
Address
Register
Symbol
Reset Value
XXXXh
000108h Group 1 Time Measurement/Waveform Generation Register 4 G1TM4/G1PO4
000109h
00010Ah Group 1 Time Measurement/Waveform Generation Register 5 G1TM5/G1PO5
00010Bh
00010Ch Group 1 Time Measurement/Waveform Generation Register 6 G1TM6/G1PO6
00010Dh
00010Eh Group 1 Time Measurement/Waveform Generation Register 7 G1TM7/G1PO7
00010Fh
XXXXh
XXXXh
XXXXh
000110h Group 1 Waveform Generation Control Register 0
000111h Group 1 Waveform Generation Control Register 1
000112h Group 1 Waveform Generation Control Register 2
000113h Group 1 Waveform Generation Control Register 3
000114h Group 1 Waveform Generation Control Register 4
000115h Group 1 Waveform Generation Control Register 5
000116h Group 1 Waveform Generation Control Register 6
000117h Group 1 Waveform Generation Control Register 7
000118h Group 1 Time Measurement Control Register 0
000119h Group 1 Time Measurement Control Register 1
00011Ah Group 1 Time Measurement Control Register 2
00011Bh Group 1 Time Measurement Control Register 3
00011Ch Group 1 Time Measurement Control Register 4
00011Dh Group 1 Time Measurement Control Register 5
00011Eh Group 1 Time Measurement Control Register 6
00011Fh Group 1 Time Measurement Control Register 7
000120h Group 1 Base Timer Register
000121h
G1POCR0
G1POCR1
G1POCR2
G1POCR3
G1POCR4
G1POCR5
G1POCR6
G1POCR7
G1TMCR0
G1TMCR1
G1TMCR2
G1TMCR3
G1TMCR4
G1TMCR5
G1TMCR6
G1TMCR7
G1BT
0000 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
00h
00h
00h
00h
00h
00h
00h
00h
XXXXh
000122h Group 1 Base Timer Control Register 0
000123h Group 1 Base Timer Control Register 1
000124h Group 1 Time Measurement Prescaler Register 6
000125h Group 1 Time Measurement Prescaler Register 7
000126h Group 1 Function Enable Register
000127h Group 1 Function Select Register
000128h
G1BCR0
G1BCR1
G1TPR6
G1TPR7
G1FE
00h
0000 0000b
00h
00h
00h
G1FS
00h
000129h
00012Ah
00012Bh
00012Ch
00012Dh
00012Eh
00012Fh
000130h to
00013Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 35 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.7
SFR List (7)
Address
Register
Symbol
G2PO0
Reset Value
XXXXh
000140h Group 2 Waveform Generation Register 0
000141h
000142h Group 2 Waveform Generation Register 1
000143h
000144h Group 2 Waveform Generation Register 2
000145h
000146h Group 2 Waveform Generation Register 3
000147h
000148h Group 2 Waveform Generation Register 4
000149h
00014Ah Group 2 Waveform Generation Register 5
00014Bh
00014Ch Group 2 Waveform Generation Register 6
00014Dh
G2PO1
G2PO2
G2PO3
G2PO4
G2PO5
G2PO6
G2PO7
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
00014Eh Group 2 Waveform Generation Register 7
00014Fh
000150h Group 2 Waveform Generation Control Register 0
000151h Group 2 Waveform Generation Control Register 1
000152h Group 2 Waveform Generation Control Register 2
000153h Group 2 Waveform Generation Control Register 3
000154h Group 2 Waveform Generation Control Register 4
000155h Group 2 Waveform Generation Control Register 5
000156h Group 2 Waveform Generation Control Register 6
000157h Group 2 Waveform Generation Control Register 7
G2POCR0
G2POCR1
G2POCR2
G2POCR3
G2POCR4
G2POCR5
G2POCR6
G2POCR7
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
000158h
000159h
00015Ah
00015Bh
00015Ch
00015Dh
00015Eh
00015Fh
000160h Group 2 Base Timer Register
000161h
G2BT
XXXXh
000162h Group 2 Base Timer Control Register 0
000163h Group 2 Base Timer Control Register 1
000164h Base Timer Start Register
000165h
G2BCR0
G2BCR1
BTSR
00h
0000 0000b
XXXX 0000b
000166h Group 2 Function Enable Register
000167h Group 2 RTP Output Buffer Register
000168h
G2FE
G2RTP
00h
00h
000169h
00016Ah Group 2 Serial Interface Mode Register
00016Bh Group 2 Serial Interface Control Register
00016Ch Group 2 SI/O Transmit Buffer Register
00016Dh
G2MR
G2CR
G2TB
00XX X000b
0000 X110b
XXXXh
00016Eh Group 2 SI/O Receive Buffer Register
00016Fh
G2RB
XXXXh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 36 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.8
SFR List (8)
Address
Register
Symbol
Reset Value
XXXXh
000170h Group 2 IEBus Address Register
000171h
IEAR
000172h Group 2 IEBus Control Register
000173h Group 2 IEBus Transmit Interrupt Source Detect Register
000174h Group 2 IEBus Receive Interrupt Source Detect Register
IECR
IETIF
IERIF
00XX X000b
XXX0 0000b
XXX0 0000b
000175h
000176h
000177h
000178h
000179h
00017Ah
00017Bh
00017Ch
00017Dh
00017Eh
00017Fh
000180h Group 0 Time Measurement/Waveform Generation Register 0 G0TM0/G0PO0
000181h
000182h Group 0 Time Measurement/Waveform Generation Register 1 G0TM1/G0PO1
000183h
000184h Group 0 Time Measurement/Waveform Generation Register 2 G0TM2/G0PO2
000185h
000186h Group 0 Time Measurement/Waveform Generation Register 3 G0TM3/G0PO3
000187h
000188h Group 0 Time Measurement/Waveform Generation Register 4 G0TM4/G0PO4
000189h
00018Ah Group 0 Time Measurement/Waveform Generation Register 5 G0TM5/G0PO5
00018Bh
00018Ch Group 0 Time Measurement/Waveform Generation Register 6 G0TM6/G0PO6
00018Dh
00018Eh Group 0 Time Measurement/Waveform Generation Register 7 G0TM7/G0PO7
00018Fh
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
000190h Group 0 Waveform Generation Control Register 0
000191h Group 0 Waveform Generation Control Register 1
000192h Group 0 Waveform Generation Control Register 2
000193h Group 0 Waveform Generation Control Register 3
000194h Group 0 Waveform Generation Control Register 4
000195h Group 0 Waveform Generation Control Register 5
000196h Group 0 Waveform Generation Control Register 6
000197h Group 0 Waveform Generation Control Register 7
000198h Group 0 Time Measurement Control Register 0
000199h Group 0 Time Measurement Control Register 1
00019Ah Group 0 Time Measurement Control Register 2
00019Bh Group 0 Time Measurement Control Register 3
00019Ch Group 0 Time Measurement Control Register 4
00019Dh Group 0 Time Measurement Control Register 5
00019Eh Group 0 Time Measurement Control Register 6
00019Fh Group 0 Time Measurement Control Register 7
X: Undefined
G0POCR0
G0POCR1
G0POCR2
G0POCR3
G0POCR4
G0POCR5
G0POCR6
G0POCR7
G0TMCR0
G0TMCR1
G0TMCR2
G0TMCR3
G0TMCR4
G0TMCR5
G0TMCR6
G0TMCR7
0000 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
0X00 X000b
00h
00h
00h
00h
00h
00h
00h
00h
Blanks are reserved. No access is allowed.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 37 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.9
SFR List (9)
Address
Register
Symbol
Reset Value
XXXXh
0001A0h Group 0 Base Timer Register
0001A1h
G0BT
0001A2h Group 0 Base Timer Control Register 0
0001A3h Group 0 Base Timer Control Register 1
0001A4h Group 0 Time Measurement Prescaler Register 6
0001A5h Group 0 Time Measurement Prescaler Register 7
G0BCR0
G0BCR1
G0TPR6
G0TPR7
G0FE
00h
0000 0000b
00h
00h
00h
0001A6h Group 0 Function Enable Register
0001A7h Group 0 Function Select Register
G0FS
00h
0001A8h
0001A9h
0001AAh
0001ABh
0001ACh
0001ADh
0001AEh
0001AFh
0001B0h
0001B1h
0001B2h
0001B3h
0001B4h
0001B5h
0001B6h
0001B7h
0001B8h
0001B9h
0001BAh
0001BBh
0001BCh
0001BDh
0001BEh
0001BFh
0001C0h
0001C1h
0001C2h
0001C3h
0001C4h UART5 Special Mode Register 4
0001C5h UART5 Special Mode Register 3
0001C6h UART5 Special Mode Register 2
0001C7h UART5 Special Mode Register
0001C8h UART5 Transmit/Receive Mode Register
0001C9h UART5 Bit Rate Register
0001CAh UART5 Transmit Buffer Register
0001CBh
U5SMR4
U5SMR3
U5SMR2
U5SMR
U5MR
00h
00h
00h
00h
00h
XXh
XXXXh
U5BRG
U5TB
0001CCh UART5 Transmit/Receive Control Register 0
0001CDh UART5 Transmit/Receive Control Register 1
0001CEh UART5 Receive Buffer Register
0001CFh
U5C0
U5C1
U5RB
0000 1000b
0000 0010b
XXXXh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 38 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.10
Address
SFR List (10)
Register
Symbol
Reset Value
0001D0h
0001D1h
0001D2h
0001D3h
0001D4h UART6 Special Mode Register 4
0001D5h UART6 Special Mode Register 3
0001D6h UART6 Special Mode Register 2
0001D7h UART6 Special Mode Register
0001D8h UART6 Transmit/Receive Mode Register
0001D9h UART6 Bit Rate Register
0001DAh UART6 Transmit Buffer Register
U6SMR4
00h
00h
00h
00h
00h
XXh
U6SMR3
U6SMR2
U6SMR
U6MR
U6BRG
U6TB
XXXXh
0001DBh
0001DCh UART6 Transmit/Receive Control Register 0
0001DDh UART6 Transmit/Receive Control Register 1
0001DEh UART6 Receive Buffer Register
U6C0
U6C1
U6RB
0000 1000b
0000 0010b
XXXXh
0001DFh
0001E0h UART7 Transmit/Receive Mode Register
0001E1h UART7 Bit Rate Register
0001E2h UART7 Transmit Buffer Register
U7MR
U7BRG
U7TB
00h
XXh
XXXXh
0001E3h
0001E4h UART7 Transmit/Receive Control Register 0
0001E5h UART7 Transmit/Receive Control Register 1
0001E6h UART7 Receive Buffer Register
U7C0
U7C1
U7RB
00X0 1000b
XXXX 0010b
XXXXh
0001E7h
0001E8h UART8 Transmit/Receive Mode Register
0001E9h UART8 Bit Rate Register
0001EAh UART8 Transmit Buffer Register
U8MR
U8BRG
U8TB
00h
XXh
XXXXh
0001EBh
0001ECh UART8 Transmit/Receive Control Register 0
0001EDh UART8 Transmit/Receive Control Register 1
0001EEh UART8 Receive Buffer Register
U8C0
U8C1
U8RB
00X0 1000b
XXXX 0010b
XXXXh
0001EFh
0001F0h UART7, UART8 Transmit/Receive Control Register 2
U78CON
X000 0000b
0001F1h
0001F2h
0001F3h
0001F4h
0001F5h
0001F6h
0001F7h
0001F8h
0001F9h
0001FAh
0001FBh
0001FCh
0001FDh
0001FEh
0001FFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 39 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.11
SFR List (11)
Address
000200h to
0002BFh
Register
Symbol
Reset Value
0002C0h X0 Register/Y0 Register
X0R/Y0R
XXXXh
0002C1h
0002C2h X1 Register/Y1 Register
0002C3h
0002C4h X2 Register/Y2 Register
0002C5h
0002C6h X3 Register/Y3 Register
0002C7h
0002C8h X4 Register/Y4 Register
0002C9h
0002CAh X5 Register/Y5 Register
0002CBh
0002CCh X6 Register/Y6 Register
0002CDh
0002CEh X7 Register/Y7 Register
0002CFh
0002D0h X8 Register/Y8 Register
0002D1h
0002D2h X9 Register/Y9 Register
0002D3h
0002D4h X10 Register/Y10 Register
0002D5h
0002D6h X11 Register/Y11 Register
0002D7h
0002D8h X12 Register/Y12 Register
0002D9h
0002DAh X13 Register/Y13 Register
0002DBh
0002DCh X14 Register/Y14 Register
0002DDh
0002DEh X15 Register/Y15 Register
0002DFh
0002E0h X-Y Control Register
0002E1h
X1R/Y1R
X2R/Y2R
X3R/Y3R
X4R/Y4R
X5R/Y5R
X6R/Y6R
X7R/Y7R
X8R/Y8R
X9R/Y9R
X10R/Y10R
X11R/Y11R
X12R/Y12R
X13R/Y13R
X14R/Y14R
X15R/Y15R
XYC
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
XXXX XX00b
0002E2h
0002E3h
0002E4h UART1 Special Mode Register 4
0002E5h UART1 Special Mode Register 3
0002E6h UART1 Special Mode Register 2
0002E7h UART1 Special Mode Register
0002E8h UART1 Transmit/Receive Mode Register
0002E9h UART1 Bit Rate Register
0002EAh UART1 Transmit Buffer Register
0002EBh
U1SMR4
U1SMR3
U1SMR2
U1SMR
U1MR
00h
00h
00h
00h
00h
XXh
XXXXh
U1BRG
U1TB
0002ECh UART1 Transmit/Receive Control Register 0
0002EDh UART1 Transmit/Receive Control Register 1
0002EEh UART1 Receive Buffer Register
0002EFh
U1C0
U1C1
U1RB
0000 1000b
0000 0010b
XXXXh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 40 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.12
Address
SFR List (12)
Register
Symbol
Reset Value
0002F0h
0002F1h
0002F2h
0002F3h
0002F4h UART4 Special Mode Register 4
U4SMR4
00h
00h
00h
00h
00h
XXh
0002F5h UART4 Special Mode Register 3
0002F6h UART4 Special Mode Register 2
0002F7h UART4 Special Mode Register
0002F8h UART4 Transmit/Receive Mode Register
0002F9h UART4 Bit Rate Register
0002FAh UART4 Transmit Buffer Register
0002FBh
U4SMR3
U4SMR2
U4SMR
U4MR
U4BRG
U4TB
XXXXh
0002FCh UART4 Transmit/Receive Control Register 0
0002FDh UART4 Transmit/Receive Control Register 1
0002FEh UART4 Receive Buffer Register
0002FFh
U4C0
U4C1
U4RB
0000 1000b
0000 0010b
XXXXh
000300h Count Start Register for Timers B3, B4, and B5
000301h
000302h Timer A1-1 Register
000303h
000304h Timer A2-1 Register
000305h
000306h Timer A4-1 Register
000307h
TBSR
TA11
TA21
TA41
000X XXXXb
XXXXh
XXXXh
XXXXh
000308h Three-phase PWM Control Register 0
000309h Three-phase PWM Control Register 1
00030Ah Three-phase Output Buffer Register 0
00030Bh Three-phase Output Buffer Register 1
00030Ch Dead Time Timer
00030Dh Timer B2 Interrupt Generating Frequency Set Counter
00030Eh
INVC0
INVC1
IDB0
IDB1
DTT
00h
00h
XX11 1111b
XX11 1111b
XXh
ICTB2
XXh
00030Fh
000310h Timer B3 Register
000311h
000312h Timer B4 Register
000313h
000314h Timer B5 Register
000315h
TB3
TB4
TB5
XXXXh
XXXXh
XXXXh
000316h
000317h
000318h
000319h
00031Ah
00031Bh Timer B3 Mode Register
00031Ch Timer B4 Mode Register
00031Dh Timer B5 Mode Register
00031Eh
TB3MR
TB4MR
TB5MR
00XX 0000b
00XX 0000b
00XX 0000b
00031Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 41 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.13
Address
SFR List (13)
Register
Symbol
Reset Value
000320h
000321h
000322h
000323h
000324h UART3 Special Mode Register 4
U3SMR4
00h
00h
00h
00h
00h
XXh
000325h UART3 Special Mode Register 3
000326h UART3 Special Mode Register 2
000327h UART3 Special Mode Register
000328h UART3 Transmit/Receive Mode Register
000329h UART3 Bit Rate Register
00032Ah UART3 Transmit Buffer Register
00032Bh
U3SMR3
U3SMR2
U3SMR
U3MR
U3BRG
U3TB
XXXXh
00032Ch UART3 Transmit/Receive Control Register 0
00032Dh UART3 Transmit/Receive Control Register 1
00032Eh UART3 Receive Buffer Register
00032Fh
U3C0
U3C1
U3RB
0000 1000b
0000 0010b
XXXXh
000330h
000331h
000332h
000333h
000334h UART2 Special Mode Register 4
000335h UART2 Special Mode Register 3
000336h UART2 Special Mode Register 2
000337h UART2 Special Mode Register
000338h UART2 Transmit/Receive Mode Register
000339h UART2 Bit Rate Register
00033Ah UART2 Transmit Buffer Register
00033Bh
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
00h
00h
00h
00h
00h
XXh
XXXXh
U2BRG
U2TB
00033Ch UART2 Transmit/Receive Control Register 0
00033Dh UART2 Transmit/Receive Control Register 1
00033Eh UART2 Receive Buffer Register
00033Fh
U2C0
U2C1
U2RB
0000 1000b
0000 0010b
XXXXh
000340h Count Start Register
000341h Clock Prescaler Reset Register
000342h One-shot Start Register
000343h Trigger Select Register
000344h Increment/Decrement Counting Select Register
000345h
TABSR
CPSRF
ONSF
TRGSR
UDF
0000 0000b
0XXX XXXXb
0000 0000b
0000 0000b
0000 0000b
000346h Timer A0 Register
000347h
000348h Timer A1 Register
000349h
00034Ah Timer A2 Register
00034Bh
00034Ch Timer A3 Register
00034Dh
TA0
TA1
TA2
TA3
TA4
XXXXh
XXXXh
XXXXh
XXXXh
XXXXh
00034Eh Timer A4 Register
00034Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 42 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.14
SFR List (14)
Address
000350h Timer B0 Register
000351h
000352h Timer B1 Register
000353h
Register
Symbol
Reset Value
XXXXh
TB0
TB1
TB2
XXXXh
XXXXh
000354h Timer B2 Register
000355h
000356h Timer A0 Mode Register
000357h Timer A1 Mode Register
000358h Timer A2 Mode Register
000359h Timer A3 Mode Register
00035Ah Timer A4 Mode Register
00035Bh Timer B0 Mode Register
00035Ch Timer B1 Mode Register
00035Dh Timer B2 Mode Register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
TCSPR
0000 0000b
0000 0000b
0000 0000b
0000 0000b
0000 0000b
00XX 0000b
00XX 0000b
00XX 0000b
XXXX XXX0b
0000 0000b
00035Eh Timer B2 Special Mode Register
00035Fh Count Source Prescaler Register
000360h
000361h
000362h
000363h
000364h UART0 Special Mode Register 4
000365h UART0 Special Mode Register 3
000366h UART0 Special Mode Register 2
000367h UART0 Special Mode Register
U0SMR4
U0SMR3
U0SMR2
U0SMR
U0MR
00h
00h
00h
00h
000368h UART0 Transmit/Receive Mode Register
00h
000369h UART0 Bit Rate Register
00036Ah UART0 Transmit Buffer Register
U0BRG
U0TB
XXh
XXXXh
00036Bh
00036Ch UART0 Transmit/Receive Control Register 0
00036Dh UART0 Transmit/Receive Control Register 1
00036Eh UART0 Receive Buffer Register
U0C0
U0C1
U0RB
0000 1000b
0000 0010b
XXXXh
00036Fh
000370h
000371h
000372h
000373h
000374h
000375h
000376h
000377h
000378h
000379h
00037Ah
00037Bh
00037Ch CRC Data Register
00037Dh
00037Eh CRC Input Register
00037Fh
CRCD
CRCIN
XXXXh
XXh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 43 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.15
SFR List (15)
Address
000380h A/D0 Register 0
000381h
000382h A/D0 Register 1
000383h
000384h A/D0 Register 2
000385h
000386h A/D0 Register 3
000387h
000388h A/D0 Register 4
000389h
00038Ah A/D0 Register 5
00038Bh
Register
Symbol
Reset Value
00XXh
AD00
AD01
AD02
AD03
AD04
AD05
AD06
AD07
00XXh
00XXh
00XXh
00XXh
00XXh
00XXh
00XXh
00038Ch A/D0 Register 6
00038Dh
00038Eh A/D0 Register 7
00038Fh
000390h
000391h
000392h A/D0 Control Register 4
000393h A/D0 Control Register 5
000394h A/D0 Control Register 2
000395h A/D0 Control Register 3
000396h A/D0 Control Register 0
000397h A/D0 Control Register 1
000398h D/A Register 0
000399h
AD0CON4
AD0CON5
AD0CON2
AD0CON3
AD0CON0
AD0CON1
DA0
XXXX 00XXb
00h
XX0X X000b
XXXX X000b
00h
00h
XXh
00039Ah D/A Register 1
00039Bh
DA1
XXh
00039Ch D/A Control Register
00039Dh
DACON
XXXX XX00b
00039Eh
00039Fh
0003A0h
0003A1h
0003A2h
0003A3h
0003A4h
0003A5h
0003A6h
0003A7h
0003A8h
0003A9h
0003AAh
0003ABh
0003ACh
0003ADh
0003AEh
0003AFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 44 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.16
Address
SFR List (16)
Register
Symbol
Reset Value
0003B0h
0003B1h
0003B2h
0003B3h
0003B4h
0003B5h
0003B6h
0003B7h
0003B8h
0003B9h
0003BAh
0003BBh
0003BCh
0003BDh
0003BEh
0003BFh
0003C0h Port P0 Register
P0
P1
PD0
PD1
P2
XXh
XXh
0000 0000b
0000 0000b
XXh
0003C1h Port P1 Register
0003C2h Port P0 Direction Register
0003C3h Port P1 Direction Register
0003C4h Port P2 Register
0003C5h Port P3 Register
P3
XXh
0003C6h Port P2 Direction Register
0003C7h Port P3 Direction Register
0003C8h Port P4 Register
PD2
PD3
P4
0000 0000b
0000 0000b
XXh
0003C9h Port P5 Register
P5
XXh
0003CAh Port P4 Direction Register
0003CBh Port P5 Direction Register
0003CCh Port P6 Register
PD4
PD5
P6
0000 0000b
0000 0000b
XXh
0003CDh Port P7 Register
P7
XXh
0003CEh Port P6 Direction Register
0003CFh Port P7 Direction Register
0003D0h Port P8 Register
PD6
PD7
P8
0000 0000b
0000 0000b
XXh
0003D1h Port P9 Register
P9
XXh
0003D2h Port P8 Direction Register
0003D3h Port P9 Direction Register
0003D4h Port P10 Register
PD8
PD9
P10
P11
PD10
PD11
P12
P13
PD12
PD13
P14
P15
PD14
PD15
00X0 0000b
0000 0000b
XXh
0003D5h Port P11 Register
XXh
0003D6h Port P10 Direction Register
0003D7h Port P11 Direction Register
0003D8h Port P12 Register
0000 0000b
0000 0000b
XXh
0003D9h Port P13 Register
XXh
0003DAh Port P12 Direction Register
0003DBh Port P13 Direction Register
0003DCh Port P14 Register
0000 0000b
0000 0000b
XXh
XXh
0000 0000b
0000 0000b
0003DDh Port P15 Register
0003DEh Port P14 Direction Register
0003DFh Port P15 Direction Register
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 45 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.17
SFR List (17)
Address
Register
Symbol
Reset Value
0003E0h Port P16 Register
P16
P17
PD16
PD17
P18
P19
PD18
PD19
XXh
XXh
0000 0000b
0000 0000b
XXh
XXh
0000 0000b
0000 0000b
0003E1h Port P17 Register
0003E2h Port P16 Direction Register
0003E3h Port P17 Direction Register
0003E4h Port P18 Register
0003E5h Port P19 Register
0003E6h Port P18 Direction Register
0003E7h Port P19 Direction Register
0003E8h
0003E9h
0003EAh
0003EBh
0003ECh
0003EDh
0003EEh
0003EFh
0003F0h Pull-up Control Register 0
0003F1h Pull-up Control Register 1
0003F2h Pull-up Control Register 2
0003F3h Pull-up Control Register 3
0003F4h Pull-up Control Register 4
0003F5h Pull-up Control Register 5
0003F6h
PUR0
PUR1
PUR2
PUR3
PUR4
PUR5
0000 0000b
XXXX X0XXb
X00X XXXXb
00XX 0000b
0XXX 0000b
XXXX 0000b
0003F7h
0003F8h
0003F9h
0003FAh
0003FBh
0003FCh
0003FDh
0003FEh
?0XX 0XX0b (1)
0003FFh Port Control Register
PCR
X: Undefined
Blanks are reserved. No access is allowed.
Note:
1. The bit 7 is 0 in the 144-pin package and 1 in the 176-pin package.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 46 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.18
SFR List (18)
Address
Register
Symbol
Reset Value
0001 XX00b
040000h Flash Memory Control Register 0
FMR0
040001h Flash Memory Status Register 0
FMSR0
1000 0000b
040002h
040003h
040004h
040005h
040006h
040007h
040008h Flash Register Protection Unlock Register 0
FPR0
00h
040009h Flash Memory Control Register 1
04000Ah Block Protect Bit Monitor Register 0
FMR1
FBPM0
FBPM1
0000 0010b
??X? ????b (1)
XXX? ????b (1)
04000Bh Block Protect Bit Monitor Register 1
04000Ch
04000Dh
04000Eh
04000Fh
040010h
???? ????b (1)
040011h Block Protect Bit Monitor Register 2
FBPM2
040012h
040013h
040014h
040015h
040016h
040017h
040018h
040019h
04001Ah
04001Bh
04001Ch
04001Dh
04001Eh
04001Fh
040020h PLL Control Register 0
040021h PLL Control Register 1
PLC0
PLC1
0000 0001b
0001 1111b
040022h
040023h
040024h
040025h
040026h
040027h
040028h
040029h
04002Ah
04002Bh
04002Ch
04002Dh
04002Eh
04002Fh
X: Undefined
Blanks are reserved. No access is allowed.
Note:
1. The status of protect bit of each block in flash memory is reflected.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 47 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.19
SFR List (19)
Address
040030h to
04003Fh
040040h
040041h
040042h
040043h
040044h
Register
Symbol
Reset Value
Processor Mode Register 0 (1)
PM0
1000 0000b
(CNVSS pin = Low)
0000 0011b
(CNVSS pin = High)
040045h
040046h System Clock Control Register 0
040047h System Clock Control Register 1
040048h Processor Mode Register 3
CM0
CM1
PM3
0000 1000b
0010 0000b
00h
040049h
04004Ah Protect Register
PRCR
XXXX X000b
04004Bh
04004Ch Protect Register 3
04004Dh Oscillator Stop Detection Register
PRCR3
CM2
0000 0000b
00h
04004Eh
04004Fh
040050h
040051h
040052h
040053h Processor Mode Register 2
PM2
00h
040054h Chip Select Output Pin Setting Register 0
040055h Chip Select Output Pin Setting Register 1
040056h Chip Select Output Pin Setting Register 2
CSOP0
CSOP1
CSOP2
1000 XXXXb
01X0 XXXXb
XXXX 0000b
040057h
040058h
040059h
04005Ah Low Speed Mode Clock Control Register
CM3
XXXX XX00b
04005Bh
04005Ch
04005Dh
04005Eh
04005Fh
040060h Voltage Regulator Control Register
040061h
040062h Low Voltage Detector Control Register
040063h
VRCR
LVDC
DVCR
0000 0000b
0000 XX00b
0000 XXXXb
040064h Detection Voltage Configuration Register
040065h
040066h
040067h
040068h to
040093h
X: Undefined
Blanks are reserved. No access is allowed.
Note:
1. The value in the PM0 register remains unchanged even after a software reset or watchdog timer reset.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 48 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.20
Address
SFR List (20)
Register
Symbol
Reset Value
040094h
040095h
040096h
040097h Three-phase Output Buffer Control Register
040098h Input Function Select Register 0
040099h
IOBC
IFS0
0XXX XXXXb
X000 0000b
04009Ah Input Function Select Register 2
04009Bh Input Function Select Register 3
04009Ch
IFS2
IFS3
0000 00X0b
XX00 XX00b
04009Dh
04009Eh
04009Fh
0400A0h Port P0_0 Function Select Register
0400A1h Port P1_0 Function Select Register
0400A2h Port P0_1 Function Select Register
0400A3h Port P1_1 Function Select Register
0400A4h Port P0_2 Function Select Register
0400A5h Port P1_2 Function Select Register
0400A6h Port P0_3 Function Select Register
0400A7h Port P1_3 Function Select Register
0400A8h Port P0_4 Function Select Register
0400A9h Port P1_4 Function Select Register
0400AAh Port P0_5 Function Select Register
0400ABh Port P1_5 Function Select Register
0400ACh Port P0_6 Function Select Register
0400ADh Port P1_6 Function Select Register
0400AEh Port P0_7 Function Select Register
0400AFh Port P1_7 Function Select Register
0400B0h Port P2_0 Function Select Register
0400B1h Port P3_0 Function Select Register
0400B2h Port P2_1 Function Select Register
0400B3h Port P3_1 Function Select Register
0400B4h Port P2_2 Function Select Register
0400B5h Port P3_2 Function Select Register
0400B6h Port P2_3 Function Select Register
0400B7h Port P3_3 Function Select Register
0400B8h Port P2_4 Function Select Register
0400B9h Port P3_4 Function Select Register
0400BAh Port P2_5 Function Select Register
0400BBh Port P3_5 Function Select Register
0400BCh Port P2_6 Function Select Register
0400BDh Port P3_6 Function Select Register
0400BEh Port P2_7 Function Select Register
0400BFh Port P3_7 Function Select Register
X: Undefined
P0_0S
P1_0S
P0_1S
P1_1S
P0_2S
P1_2S
P0_3S
P1_3S
P0_4S
P1_4S
P0_5S
P1_5S
P0_6S
P1_6S
P0_7S
P1_7S
P2_0S
P3_0S
P2_1S
P3_1S
P2_2S
P3_2S
P2_3S
P3_3S
P2_4S
P3_4S
P2_5S
P3_5S
P2_6S
P3_6S
P2_7S
P3_7S
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
00XX X000b
XXXX X000b
00XX X000b
XXXX X000b
00XX X000b
XXXX X000b
00XX X000b
XXXX X000b
00XX X000b
XXXX X000b
00XX X000b
XXXX X000b
00XX X000b
XXXX X000b
00XX X000b
XXXX X000b
Blanks are reserved. No access is allowed.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 49 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.21
SFR List (21)
Address
Register
Symbol
P4_0S
Reset Value
X0XX X000b
0400C0h Port P4_0 Function Select Register
0400C1h Port P5_0 Function Select Register
0400C2h Port P4_1 Function Select Register
0400C3h Port P5_1 Function Select Register
0400C4h Port P4_2 Function Select Register
0400C5h Port P5_2 Function Select Register
0400C6h Port P4_3 Function Select Register
0400C7h Port P5_3 Function Select Register
0400C8h Port P4_4 Function Select Register
0400C9h Port P5_4 Function Select Register
0400CAh Port P4_5 Function Select Register
0400CBh Port P5_5 Function Select Register
0400CCh Port P4_6 Function Select Register
0400CDh Port P5_6 Function Select Register
0400CEh Port P4_7 Function Select Register
0400CFh Port P5_7 Function Select Register
0400D0h Port P6_0 Function Select Register
0400D1h Port P7_0 Function Select Register
0400D2h Port P6_1 Function Select Register
0400D3h Port P7_1 Function Select Register
0400D4h Port P6_2 Function Select Register
0400D5h Port P7_2 Function Select Register
0400D6h Port P6_3 Function Select Register
0400D7h Port P7_3 Function Select Register
0400D8h Port P6_4 Function Select Register
0400D9h Port P7_4 Function Select Register
0400DAh Port P6_5 Function Select Register
0400DBh Port P7_5 Function Select Register
0400DCh Port P6_6 Function Select Register
0400DDh Port P7_6 Function Select Register
0400DEh Port P6_7 Function Select Register
0400DFh Port P7_7 Function Select Register
0400E0h Port P8_0 Function Select Register
0400E1h Port P9_0 Function Select Register
0400E2h Port P8_1 Function Select Register
0400E3h Port P9_1 Function Select Register
0400E4h Port P8_2 Function Select Register
0400E5h Port P9_2 Function Select Register
0400E6h Port P8_3 Function Select Register
0400E7h Port P9_3 Function Select Register
0400E8h Port P8_4 Function Select Register
0400E9h Port P9_4 Function Select Register
0400EAh
P5_0S
P4_1S
P5_1S
P4_2S
P5_2S
P4_3S
P5_3S
P4_4S
P5_4S
P4_5S
P5_5S
P4_6S
P5_6S
P4_7S
P5_7S
P6_0S
P7_0S
P6_1S
P7_1S
P6_2S
P7_2S
P6_3S
P7_3S
P6_4S
P7_4S
P6_5S
P7_5S
P6_6S
P7_6S
P6_7S
P7_7S
P8_0S
P9_0S
P8_1S
P9_1S
P8_2S
P9_2S
P8_3S
P9_3S
P8_4S
P9_4S
XXXX X000b
X0XX X000b
XXXX X000b
X0XX X000b
XXXX X000b
X0XX X000b
XXXX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
00XX X000b
XXXX X000b
00XX X000b
0400EBh Port P9_5 Function Select Register
0400ECh Port P8_6 Function Select Register
0400EDh Port P9_6 Function Select Register
0400EEh Port P8_7 Function Select Register
0400EFh Port P9_7 Function Select Register
X: Undefined
P9_5S
P8_6S
P9_6S
P8_7S
P9_7S
00XX X000b
XXXX X000b
00XX X000b
XXXX X000b
X0XX X000b
Blanks are reserved. No access is allowed.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 50 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.22
SFR List (22)
Address
Register
Symbol
P10_0S
Reset Value
0XXX X000b
0400F0h Port P10_0 Function Select Register
0400F1h Port P11_0 Function Select Register
0400F2h Port P10_1 Function Select Register
0400F3h Port P11_1 Function Select Register
0400F4h Port P10_2 Function Select Register
0400F5h Port P11_2 Function Select Register
0400F6h Port P10_3 Function Select Register
0400F7h Port P11_3 Function Select Register
0400F8h Port P10_4 Function Select Register
0400F9h Port P11_4 Function Select Register
0400FAh Port P10_5 Function Select Register
0400FBh Port P11_5 Function Select Register
0400FCh Port P10_6 Function Select Register
0400FDh Port P11_6 Function Select Register
0400FEh Port P10_7 Function Select Register
0400FFh Port P11_7 Function Select Register
040100h Port P12_0 Function Select Register
040101h Port P13_0 Function Select Register
040102h Port P12_1 Function Select Register
040103h Port P13_1 Function Select Register
040104h Port P12_2 Function Select Register
040105h Port P13_2 Function Select Register
040106h Port P12_3 Function Select Register
040107h Port P13_3 Function Select Register
040108h Port P12_4 Function Select Register
040109h Port P13_4 Function Select Register
04010Ah Port P12_5 Function Select Register
04010Bh Port P13_5 Function Select Register
04010Ch Port P12_6 Function Select Register
04010Dh Port P13_6 Function Select Register
04010Eh Port P12_7 Function Select Register
04010Fh Port P13_7 Function Select Register
040110h
P11_0S
P10_1S
P11_1S
P10_2S
P11_2S
P10_3S
P11_3S
P10_4S
P11_4S
P10_5S
P11_5S
P10_6S
P11_6S
P10_7S
P11_7S
P12_0S
P13_0S
P12_1S
P13_1S
P12_2S
P13_2S
P12_3S
P13_3S
P12_4S
P13_4S
P12_5S
P13_5S
P12_6S
P13_6S
P12_7S
P13_7S
X0XX X000b
0XXX X000b
X0XX X000b
0XXX X000b
X0XX X000b
0XXX X000b
X0XX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
0XXX X000b
XXXX X000b
X0XX X000b
XXXX X000b
X0XX X000b
XXXX X000b
X0XX X000b
XXXX X000b
X0XX X000b
XXXX X000b
X0XX X000b
XXXX X000b
X0XX X000b
XXXX X000b
X0XX X000b
XXXX X000b
X0XX X000b
XXXX X000b
040111h Port P15_0 Function Select Register
040112h
040113h Port P15_1 Function Select Register
040114h
P15_0S
P15_1S
00XX X000b
00XX X000b
040115h Port P15_2 Function Select Register
040116h Port P14_3 Function Select Register
040117h Port P15_3 Function Select Register
040118h Port P14_4 Function Select Register
040119h Port P15_4 Function Select Register
04011Ah Port P14_5 Function Select Register
04011Bh Port P15_5 Function Select Register
04011Ch Port P14_6 Function Select Register
04011Dh Port P15_6 Function Select Register
04011Eh Port P14_7 Function Select Register
04011Fh Port P15_7 Function Select Register
X: Undefined
P15_2S
P14_3S
P15_3S
P14_4S
P15_4S
P14_5S
P15_5S
P14_6S
P15_6S
P14_7S
P15_7S
00XX X000b
XXXX X000b
00XX X000b
XXXX X000b
00XX X000b
XXXX X000b
00XX X000b
XXXX X000b
00XX X000b
XXXX X000b
00XX X000b
Blanks are reserved. No access is allowed.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 51 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.23
SFR List (23)
Address
Register
Symbol
P16_0S
Reset Value
X0XX X000b
040120h Port P16_0 Function Select Register
040121h Port P17_0 Function Select Register
040122h Port P16_1 Function Select Register
040123h Port P17_1 Function Select Register
040124h Port P16_2 Function Select Register
040125h Port P17_2 Function Select Register
040126h Port P16_3 Function Select Register
040127h Port P17_3 Function Select Register
040128h Port P16_4 Function Select Register
040129h Port P17_4 Function Select Register
04012Ah Port P16_5 Function Select Register
04012Bh Port P17_5 Function Select Register
04012Ch Port P16_6 Function Select Register
04012Dh Port P17_6 Function Select Register
04012Eh Port P16_7 Function Select Register
04012Fh Port P17_7 Function Select Register
040130h Port P18_0 Function Select Register
040131h Port P19_0 Function Select Register
040132h Port P18_1 Function Select Register
040133h Port P19_1 Function Select Register
040134h Port P18_2 Function Select Register
040135h Port P19_2 Function Select Register
040136h Port P18_3 Function Select Register
040137h Port P19_3 Function Select Register
040138h Port P18_4 Function Select Register
040139h Port P19_4 Function Select Register
04013Ah Port P18_5 Function Select Register
04013Bh Port P19_5 Function Select Register
04013Ch Port P18_6 Function Select Register
04013Dh Port P19_6 Function Select Register
04013Eh Port P18_7 Function Select Register
04013Fh Port P19_7 Function Select Register
040140h
P17_0S
P16_1S
P17_1S
P16_2S
P17_2S
P16_3S
P17_3S
P16_4S
P17_4S
P16_5S
P17_5S
P16_6S
P17_6S
P16_7S
P17_7S
P18_0S
P19_0S
P18_1S
P19_1S
P18_2S
P19_2S
P18_3S
P19_3S
P18_4S
P19_4S
P18_5S
P19_5S
P18_6S
P19_6S
P18_7S
P19_7S
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
X0XX X000b
XXXX X000b
X0XX X000b
XXXX X000b
X0XX X000b
XXXX X000b
X0XX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
040141h
040142h
040143h
040144h
040145h
040146h
040147h
040148h
040149h
04014Ah
04014Bh
04014Ch
04014Dh
04014Eh
04014Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 52 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.24
SFR List (24)
Address
040150h to
0402FFh
Register
Symbol
Reset Value
040300h UART9 Transmit/Receive Mode Register
U9MR
00h
040301h UART9 Bit Rate Register
040302h UART9 Transmit Buffer Register
U9BRG
U9TB
XXh
XXXXh
040303h
040304h UART9 Transmit/Receive Control Register 0
040305h UART9 Transmit/Receive Control Register 1
040306h UART9 Receive Buffer Register
U9C0
U9C1
U9RB
00X0 1000b
XXXX 0010b
XXXXh
040307h
040308h UART10 Transmit/Receive Mode Register
040309h UART10 Bit Rate Register
04030Ah UART10 Transmit Buffer Register
U10MR
U10BRG
U10TB
00h
XXh
XXXXh
04030Bh
04030Ch UART10 Transmit/Receive Control Register 0
04030Dh UART10 Transmit/Receive Control Register 1
04030Eh UART10 Receive Buffer Register
U10C0
U10C1
U10RB
00X0 1000b
XXXX 0010b
XXXXh
04030Fh
040310h UART9, UART10 Transmit/Receive Control Register 2
U910CON
X000 0000b
040311h
040312h
040313h
040314h
040315h
040316h
040317h
040318h to
041FFFh
042000h to Protected Area 0
04201Fh
042020h to Protected Area 1
04203Fh
042040h to Protected Area 2
04205Fh
042060h to Protected Area 3
04207Fh
Undefined
Undefined
Undefined
Undefined
Undefined
—
—
—
—
—
042080h to Protected Area 4
04209Fh
0420A0h to
0420EFh
0420F0h Protected Area Protect Release Register
0420F1h
0420F2h Protected Area Write Access Flag Register
PAPR
PAWF
XXX0 0000b
XXX0 0000b
0420F3h
0420F4h
0420F5h
0420F6h
0420F7h
0420F8h to
043FFFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 53 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.25
SFR List (25)
Address
044000h to
04403Fh
044040h
044041h
044042h
044043h
044044h
044045h
044046h
044047h
044048h
044049h
04404Ah
04404Bh
Register
Symbol
Reset Value
04404Ch Protect Register 4
PRCR4
0000 0000b
0000 000?b (1)
XXXX XXXXb
000X XXXXb
04404Dh Watchdog Timer Clock Control Register
WDK
WDTS
WDC
04404Eh Watchdog Timer Start Register
04404Fh Watchdog Timer Control Register
044050h
044051h
044052h
044053h
044054h
044055h
044056h
044057h
044058h
044059h
04405Ah
04405Bh
04405Ch
04405Dh
04405Eh
04405Fh Protect Register 2
PRCR2
0XXX XXXXb
X: Undefined
Blanks are reserved. No access is allowed.
Note:
1. The bit 0 is set to 1 when the most recent reset is caused by the watchdog timer. Otherwise, it is set
to 0.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 54 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.26
Address
044060h
044061h
044062h
044063h
044064h
044065h
044066h
044067h
044068h
044069h
04406Ah
04406Bh
04406Ch
SFR List (26)
Register
Symbol
Reset Value
04406Dh External Interrupt Request Source Select Register 1
04406Eh
04406Fh External Interrupt Request Source Select Register 0
044070h DMA0 Request Source Select Register 2
044071h DMA1 Request Source Select Register 2
044072h DMA2 Request Source Select Register 2
044073h DMA3 Request Source Select Register 2
IFSR1
IFSR0
DM0SL2
DM1SL2
DM2SL2
DM3SL2
X0XX X000b
0000 0000b
XX00 0000b
XX00 0000b
XX00 0000b
XX00 0000b
044074h
044075h
044076h
044077h
044078h DMA0 Request Source Select Register
044079h DMA1 Request Source Select Register
04407Ah DMA2 Request Source Select Register
04407Bh DMA3 Request Source Select Register
DM0SL
DM1SL
DM2SL
DM3SL
XXX0 0000b
XXX0 0000b
XXX0 0000b
XXX0 0000b
04407Ch
04407Dh Wake-up IPL Setting Register 2
04407Eh
04407Fh Wake-up IPL Setting Register 1
RIPL2
RIPL1
XX0X 0000b
XX0X 0000b
044080h
044081h
044082h
044083h
044084h
044085h
044086h
044087h
044088h
044089h
04408Ah
04408Bh
04408Ch
04408Dh
04408Eh
04408Fh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 55 of 99
R32C/116A Group
4. Special Function Registers (SFRs)
Table 4.27
SFR List (27)
Address
044090h to
0443FFh
044400h
Register
Symbol
Reset Value
I2C Bus Transmit/Receive Shift Register
I2CTRSR
XXh
00h
044401h
044402h
044403h
044404h
044405h
I2C Bus Slave Address Register
I2C Bus Control Register 0
I2C Bus Clock Control Register
I2C Bus START Condition/STOP Condition Control
Register
I2CSAR
I2CCR0
I2CCCR
I2CSSCR
0000 0000b
0000 0000b
0000 0000b
I2C Bus Control Register 1
I2C Bus Control Register 2
I2C Bus Status Register
044406h
044407h
044408h
044409h
04440Ah
04440Bh
04440Ch
04440Dh
04440Eh
04440Fh
044410h
I2CCR1
I2CCR2
I2CSR
0000 0000b
0000 0000b
0000 0000b
I2C Bus Mode Register
I2CMR
0000 0000b
044411h
044412h
044413h
044414h
044415h
044416h
044417h
044418h
044419h
04441Ah
04441Bh
04441Ch
04441Dh
04441Eh
04441Fh
044420h to
04FFFFh
X: Undefined
Blanks are reserved. No access is allowed.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 56 of 99
R32C/116A Group
5. Electrical Characteristics
5. Electrical Characteristics
(1)
Table 5.1
Absolute Maximum Ratings
Symbol
Characteristic
Condition
Value
Unit
V
V
Supply voltage
Analog supply voltage
V
= AV
-0.3 to 6.0
-0.3 to 6.0
CC
CC
CC
CC
AV
V
= AV
V
CC
CC
V
Input
XIN, RESET, CNVSS, NSD, V
,
I
REF
voltage
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P3_0 to P3_7,
P5_0 to P5_3, P8_4 to P8_7,
-0.3 to V + 0.3
V
V
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P13_0 to P13_7,
P14_1, P14_3 to P14_7,
P15_0 to P15_7, P17_4 to P17_7,
P18_0 to P18_7, P19_0 to P19_7
CC
(2)
(2)
P4_0 to P4_7, P5_4 to P5_7,
P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_3, P12_0 to P12_7,
P16_0 to P16_7, P17_0 to P17_3
-0.3 to 6.0
V
Output
voltage
XOUT, P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7,
O
-0.3 to V + 0.3
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7,
P13_0 to P13_7, P14_3 to P14_7,
P15_0 to P15_7, P16_0 to P16_7,
P17_0 to P17_7, P18_0 to P18_7,
V
CC
(2)
P19_0 to P19_7
P
T
Power consumption
T = 25°C
a
500
mW
°C
d
—
Operating temperature range
Storage temperature range
-40 to 85
-65 to 150
°C
stg
Notes:
1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. Ports P16 to P19 are available in the 176-pin package only.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 57 of 99
R32C/116A Group
5. Electrical Characteristics
(1)
Table 5.2
Operating Conditions (1/5)
Value
Unit
Symbol
Characteristic
Min.
3.0
Typ.
5.0
Max.
5.5
V
Digital supply voltage
V
V
CC
V
AV
V
Analog supply voltage
Reference voltage
CC
CC
V
3.0
V
REF
SS
CC
V
Digital ground voltage
Analog ground voltage
0
0
V
AV
V
SS
dV /dt V ramp up rate (V < 2.0 V)
0.05
V/ms
CC
CC
CC
V
High level
input
voltage
XIN, RESET, CNVSS, NSD, P2_0 to P2_7,
P3_0 to P3_7, P5_0 to P5_3, P8_4 to P8_7
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_1, P14_3 to P14_7,
P15_0 to P15_7, P17_4 to P17_7,
IH
(2)
,
0.8 × V
V
V
CC
CC
(3)
P18_0 to P18_7, P19_0 to P19_7
P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7,
0.8 × V
P7_0 to P7_7, P8_0 to P8_3, P16_0 to P16_7,
6.0
V
CC
(3)
P17_0 to P17_3
P0_0 to P0_7,
P1_0 to P1_7,
P13_0 to P13_7
in single-chip mode
0.8 × V
0.5 × V
0.8 × V
0.5 × V
V
V
V
V
V
CC
CC
CC
CC
CC
in memory expansion mode
or microprocessor mode
V
CC
P12_0 to P12_7 in single-chip mode
6.0
6.0
in memory expansion mode
or microprocessor mode
V
Low level
input
voltage
XIN, RESET, CNVSS, NSD, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7
P9_0 to P9_7, P10_0 to P10_7,
IL
(2)
,
0.2 × V
0
V
CC
P11_0 to P11_7, P14_1, P14_3 to P14_7,
P15_0 to P15_7, P16_0 to P16_7,
P17_0 to P17_7, P18_0 to P18_7,
(3)
P19_0 to P19_7
P0_0 to P0_7,
P1_0 to P1_7,
P12_0 to P12_7,
P13_0 to P13_7
in single-chip mode
0.2 × V
CC
0
0
V
V
in memory expansion mode
or microprocessor mode
0.16 × V
CC
T
Operating
temperature
range
N version
D version
P version
-20
-40
-40
85
85
85
°C
°C
°C
opr
Notes:
1. The device is operationally guaranteed under these operating conditions.
2. and V for P8_7 are specified for P8_7 as a programmable port. These values are not applicable
V
IH
IL
to P8_7 as XCIN.
3. Ports P16 to P19 are available in the 176-pin package only.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 58 of 99
R32C/116A Group
5. Electrical Characteristics
Table 5.3
Operating Conditions (2/5)
(1)
(V = 3.0 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
(2)
Value
Min. Typ. Max.
Symbol
Characteristic
Unit
C
Decoupling capacitance for voltage
regulator
Inter-pin voltage: 1.5 V
VDC
2.4
10.0 µF
Notes:
1. The device is operationally guaranteed under these operating conditions.
2. This value should be satisfied with due consideration of every condition as follows: operating
temperature, DC bias, aging, etc.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 59 of 99
R32C/116A Group
5. Electrical Characteristics
Table 5.4
Operating Conditions (3/5)
(V = 3.0 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)
(1)
CC
SS
a
opr
Value
Typ.
Symbol
Characteristic
High level P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
Unit
Min.
Max.
I
I
I
I
OH
(peak)
peak
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7,
output
current
(2)
-10.0 mA
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_7, P15_0 to P15_7, P16_0 to P16_7,
P17_0 to P17_7, P18_0 to P18_7, P19_0 to P19_7
(3)
(3)
(3)
(3)
High level P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
average P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
OH
(avg)
output
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_7, P15_0 to P15_7, P16_0 to P16_7,
P17_0 to P17_7, P18_0 to P18_7, P19_0 to P19_7
(4)
-5.0
mA
current
Low level P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
OL
(peak)
peak
output
current
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_7, P15_0 to P15_7, P16_0 to P16_7,
P17_0 to P17_7, P18_0 to P18_7, P19_0 to P19_7
(2)
10.0 mA
Low level P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
average P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
OL
(avg)
output
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_7, P15_0 to P15_7, P16_0 to P16_7,
P17_0 to P17_7, P18_0 to P18_7, P19_0 to P19_7
(4)
5.0
mA
current
Notes:
1. The device is operationally guaranteed under these operating conditions.
2. The following conditions should be satisfied:
• The sum of I
of ports P0, P1, P2, P8_6, P8_7, P9, P10, P11_0 to P11_4, P14_3 to P14_6,
OL(peak)
P15, P18_2 to P18_7, P19_0, P19_1, P19_6, and P19_7 is 80 mA or less.
• The sum of I of ports P3, P4, P5, P6, P7, P8_0 to P8_4, P11_5 to P11_7, P12, P13, P14_7,
OL(peak)
P16, P17, P18_0, P18_1, and P19_2 to P19_5 is 80 mA or less.
• The sum of I
of ports P0, P1, P2, P11_0 to P11_4, P18_2 to P18_7, P19_0, and P19_1 is
of ports P8_6, P8_7, P9, P10, P14_3 to P14_6, P15, P19_6, and P19_7 is -40
of ports P3, P4, P5, P11_5, P11_6, P12, P13, P16, P17_0 to P17_3, and
OH(peak)
-40 mA or less.
• The sum of I
OH(peak)
mA or less.
• The sum of I
OH(peak)
P19_2 to P19_5 is -40 mA or less.
• The sum of I of ports P6, P7, P8_0 to P8_4, P11_7, P14_7, P17_4 to P17_7, P18_0, and
OH(peak)
P18_1 is -40 mA or less.
3. Ports P16 to P19 are available in the 176-pin package only.
4. Average value within 100 ms.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 60 of 99
R32C/116A Group
5. Electrical Characteristics
Table 5.5
Operating Conditions (4/5)
(1)
(V = 3.0 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
Value
Typ.
Symbol
Characteristic
Unit
Min.
4
Max.
16
f
f
f
f
t
f
t
f
t
f
f
Main clock oscillator frequency
Reference clock frequency
PLL clock oscillator frequency
Base clock frequency
MHz
MHz
MHz
MHz
ns
(XIN)
2
4
(XRef)
(PLL)
96
128
64
(Base)
c(Base)
(CPU)
Base clock cycle time
15.625
15.625
31.25
CPU operating frequency
CPU clock cycle time
64
32
MHz
ns
(CPU)
c
Peripheral bus clock operating frequency
Peripheral bus clock cycle time
Peripheral clock source frequency
Sub clock oscillator frequency
MHz
ns
(BCLK)
(BCLK)
c
32
MHz
kHz
(PER)
32.768
62.5
(XCIN)
Note:
1. The device is operationally guaranteed under these operating conditions.
tc(Base)
Base clock
(Internal signal)
tc(CPU)
CPU clock
(Internal signal)
tc(BCLK)
Peripheral bus clock
(Internal signal)
Figure 5.1
Clock Cycle Time
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 61 of 99
R32C/116A Group
5. Electrical Characteristics
Table 5.6
Operating Conditions (5/5)
(1)
(V = 3.0 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
Value
Symbol
Characteristic
Unit
Min.
Typ. Max.
0.5
V
Allowable ripple voltage
V
V
V
V
= 5.0 V
= 3.0 V
= 5.0 V
= 3.0 V
Vp-p
Vp-p
r(VCC)
CC
CC
CC
CC
0.3
dV
/dt Ripple voltage gradient
±0.3 V/ms
±0.3 V/ms
r(VCC)
f
Allowable ripple frequency
10
kHz
r(VCC)
Note:
1. The device is operationally guaranteed under these operating conditions.
1 / fr(VCC)
VCC
Vr(VCC)
Figure 5.2
Ripple Waveform
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 62 of 99
R32C/116A Group
5. Electrical Characteristics
Table 5.7
RAM Electrical Characteristics
(V = 3.0 to 5.5 V, V = 0 V, and Ta = T , unless otherwise noted)
CC
SS
opr
Value
Measurement
Symbol
Characteristic
Unit
V
condition
Min.
2.0
Typ. Max.
V
RAM data retention voltage
in stop mode
RDR
Table 5.8
Flash Memory Electrical Characteristics
(V = 3.0 to 5.5 V, V = 0 V, and Ta = T , unless otherwise noted)
CC
SS
opr
Value
Symbol
—
Characteristic
Unit
Min.
1000
Typ. Max.
Programming and erasure endurance of flash Program area
times
times
µs
(1)
memory
Data area
10000
—
—
—
4-word program time
Program area
Data area
150
300
70
900
1700 µs
500 µs
1000 µs
Lock bit-program time
Block erasure time
Program area
Data area
140
0.12
0.17
0.20
4 Kbyte block
32 Kbyte block
64 Kbyte block
3.0
3.0
3.0
250
s
s
s
t
Suspend latency
µs
SUSP
(2)
(3)
T = 55°C
a
Data retention
—
10
years
Notes:
1. Program/erase definition
This value represents the number of erasures per block.
If the flash memory is programmed/erased n times, each block can be erased n times.
i.e. If 4-word write is performed in 512 different addresses in the block A of 4 Kbyte and then the
block is erased, it is considered the programming/erasure is performed just once.
However a write in the same address more than once for one erasure is disabled (overwrite
disabled).
2. The data retention time includes the periods when the supply voltage is not applied and no clock is
provided.
3. Please contact a Renesas Electronics sales office regarding data retention time other than the
above.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 63 of 99
R32C/116A Group
5. Electrical Characteristics
Table 5.9
Power Supply Circuit Timing Characteristics
(V = 3.0 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
Value
Measurement
condition
Symbol
Characteristic
Unit
ms
Min. Typ. Max.
t
Internal power supply start-up stabilization
time after the main power supply is turned on
d(P-R)
2
td(P-R)
Recommended
Internal power supply start-up
stabilization time after the main
power supply is turned on
VCC
operating voltage
td(P-R)
Supply voltage for
internal logic
PLL oscillator-
output waveform
Figure 5.3
Table 5.10
Symbol
Power Supply Circuit Timing
Electrical Characteristics of Voltage Regulator for Internal Logic
(V = 3.0 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
Value
Min. Typ. Max.
1.5
Measurement
condition
Characteristics
Unit
V
V
Output voltage
VDC1
Table 5.11
Electrical Characteristics of Low Voltage Detector
(V = 4.2 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
Value
Measurement
Symbol
Characteristics
Unit
condition
Min. Typ. Max.
ΔVdet
Detected voltage error
±0.3
V
V
Vdet(R)-Vdet(F) Hysteresis width
Self-consuming current
0
V
= 5.0 V, low voltage
CC
—
4
µA
µs
detector enabled
Operation start time of low voltage detector
t
150
d(E-A)
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 64 of 99
R32C/116A Group
5. Electrical Characteristics
Table 5.12
Electrical Characteristics of Oscillator
(V = 3.0 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
Value
Measurement
condition
Symbol
Characteristics
Unit
Min. Typ. Max.
f
t
t
f
PLL clock self-oscillation frequency
MHz
ms
35
55
80
1
SO(PLL)
LOCK(PLL)
jitter(p-p)
(OCO)
(1)
PLL lock time
PLL jitter period (p-p)
2.0
ns
On-chip oscillator frequency
62.5 125 250 kHz
Note:
1. This value is applicable only when the main clock oscillation is stable.
Table 5.13
Electrical Characteristics of Clock Circuitry
(V = 3.0 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
Value
Measurement
condition
Symbol
Characteristics
Unit
Min. Typ. Max.
t
Recovery time from wait mode to low power mode
225 µs
225 µs
rec(WAIT)
(1)
t
Recovery time from stop mode
rec(STOP)
Note:
1. This recovery time does not include the period until the main clock oscillator is stabilized. The CPU
starts operating before the oscillator is stabilized.
trec(WAIT)
Interrupt for exiting
wait mode
Recovery time from wait mode
to low power mode
Sub clock oscillator
output
On-chip oscillator
output
CPU clock
trec(WAIT)
trec(STOP)
Interrupt for exiting
stop mode
Recovery time from stop mode
Main clock oscillator
output
On-chip oscillator
output
CPU clock
trec(STOP)
Figure 5.4
Clock Circuit Timing
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 65 of 99
R32C/116A Group
5. Electrical Characteristics
Timing Requirements (V = 3.0 to 5.5 V, V = 0 V, and Ta = T , unless otherwise noted)
CC
SS
opr
Table 5.14
Flash Memory CPU Rewrite Mode Timing
Value
Min. Max.
Symbol
Characteristics
Unit
t
Read cycle time
200
200
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cR
t
Chip-select setup time for read
Chip-select hold time after read
Address setup time for read
Address hold time after read
Read pulse width
su(S-R)
t
h(R-S)
t
200
0
su(A-R)
t
h(R-A)
t
100
200
0
w(R)
t
Write cycle time
cW
t
Chip-select setup time for write
Chip-select hold time after write
Address setup time for write
Address hold time after write
Write pulse width
su(S-W)
t
30
0
h(W-S)
t
su(A-W)
t
30
50
h(W-A)
t
w(W)
tcR
Read cycle
tsu(S-R)
th(R-S)
Chip select
Address
RD
tsu(A-R)
th(R-A)
tw(R)
tcW
Write cycle
tsu(S-W)
th(W-S)
Chip select
Address
WR
tsu(A-W)
th(W-A)
tw(W)
Figure 5.5
Flash Memory CPU Rewrite Mode Timing
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 66 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 5 V
Table 5.15
Electrical Characteristics (1/3)
(V = 4.2 to 5.5 V, V = 0 V, T = T , and f = 64 MHz, unless otherwise noted)
(CPU)
CC
SS
a
opr
Value
Typ. Max.
Measurement
Symbol
Characteristic
Unit
condition
Min.
V
High
level
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
OH
output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
voltage P8_6, P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_7,
I
= -5 mA
V
- 2.0
V
CC
V
OH
CC
P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_7, P15_0 to P15_7,
P16_0 to P16_7, P17_0 to P17_7,
(1)
P18_0 to P18_7, P19_0 to P19_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,
I
= -200 µA V - 0.3
V
CC
P10_0 to P10_7, P11_0 to P11_7,
P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_7, P15_0 to P15_7,
P16_0 to P16_7, P17_0 to P17_7,
V
V
V
OH
CC
(1)
P18_0 to P18_7, P19_0 to P19_7
V
Low
level
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
voltage P8_6, P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_7,
OL
I
= 5 mA
2.0
OL
P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_7, P15_0 to P15_7,
P16_0 to P16_7, P17_0 to P17_7,
(1)
P18_0 to P18_7, P19_0 to P19_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_7,
P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_7, P15_0 to P15_7,
P16_0 to P16_7, P17_0 to P17_7,
I
= 200 µA
0.45
OL
(1)
P18_0 to P18_7, P19_0 to P19_7
Note:
1. Ports P16 to P19 are available in the 176-pin package only.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 67 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 5 V
Table 5.16
Electrical Characteristics (2/3)
(V = 4.2 to 5.5 V, V = 0 V, T = T , and f = 64 MHz, unless otherwise noted)
(CPU)
CC
SS
a
opr
Value
Measurement
condition
Symbol
Characteristic
Unit
Min. Typ. Max.
V
- V Hysteresis HOLD, RDY, NMI, INT0 to INT8, KI0 to KI3,
T+
T-
TA0IN to TA4IN, TA0OUT to TA4OUT,
TB0IN to TB5IN, CTS0 to CTS10,
CLK0 to CLK10, RXD0 to RXD10,
0.2
0.2
1.0
1.8
V
V
SCL0 to SCL6, SDA0 to SDA6, SS0 to SS6,
SRXD0 to SRXD6, ADTRG, IIO0_0 to IIO0_7,
IIO1_0 to IIO1_7, UD0A, UD0B, UD1A,
UD1B, ISCLK2, ISRXD2, IEIN
RESET
I
High level XIN, RESET, CNVSS, NSD,
IH
input
current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
V = 5 V
5.0 µA
I
P11_0 to P11_7, P12_0 to P12_7,
P13_0 to P13_7, P14_1, P14_3 to P14_7,
P15_0 to P15_7, P16_0 to P16_7,
P17_0 to P17_7, P18_0 to P18_7,
(1)
P19_0 to P19_7
I
Low level XIN, RESET, CNVSS, NSD,
IL
input
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
current
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
V = 0 V
-5.0 µA
I
P11_0 to P11_7, P12_0 to P12_7,
P13_0 to P13_7, P14_1, P14_3 to P14_7,
P15_0 to P15_7, P16_0 to P16_7,
P17_0 to P17_7, P18_0 to P18_7,
(1)
P19_0 to P19_7
R
Pull-up
resistor
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P5_0 to P5_3, P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P13_0 to P13_7, P14_1,
P14_3 to P14_7, P15_0 to P15_7,
PULLUP
V = 0 V
30
50 170 kΩ
I
P17_4 to P17_7, P18_0 to P18_7,
(1)
P19_0 to P19_7
R
R
Feedback XIN
resistor
XIN
f
1.5
15
MΩ
MΩ
Feedback XCIN
resistor
XCIN
f
Note:
1. Ports P16 to P19 are available in the 176-pin package only.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 68 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 5 V
Table 5.17
Electrical Characteristics (3/3)
(V = 4.2 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
Value
Characterist
ic
Symbol
ICC
Measurement condition
Unit
mA
Min. Typ. Max.
Power supply In single-chip mode,
current output pins are left open
f(CPU) = 64 MHz, f(BCLK) = 32 MHz,
f(XIN) = 8 MHz,
45
12
60
and others are
connected to V
Active: XIN, PLL,
Stopped: XCIN, OCO
SS
f(CPU) = fSO(PLL)/24 MHz,
XIN-XOUT
Drive power:
mA
mA
Active: PLL (self-oscillation),
Stopped: XIN, XCIN, OCO
f(CPU) = f(BCLK) = f(XIN)/256 MHz,
f(XIN) = 8 MHz,
XCIN-XCOUT
Drive power: low
1.2
Active: XIN,
Stopped: PLL, XCIN, OCO
f(CPU) = f(BCLK) = 32.768 kHz,
Active: XCIN,
Stopped: XIN, PLL, OCO,
Main regulator: shutdown
220
230
µA
µA
f(CPU) = f(BCLK) = f(OCO)/4 kHz,
Active: OCO,
Stopped: XIN, PLL, XCIN,
Main regulator: shutdown
f(CPU) = f(BCLK) = f(XIN)/256 MHz,
f(XIN) = 8 MHz,
960 1600 µA
Active: XIN,
Stopped: PLL, XCIN, OCO,
Ta = 25°C, Wait mode
f(CPU) = f(BCLK) = 32.768 kHz,
Active: XCIN,
Stopped: XIN, PLL, OCO,
Main regulator: shutdown,
Ta = 25°C, Wait mode
8
140
µA
f
(CPU) = f(BCLK) = f(OCO)/4 kHz,
Active: OCO,
Stopped: XIN, PLL, XCIN,
Main regulator: shutdown,
Ta = 25°C, Wait mode
10
5
150
70
µA
µA
Stopped: all clocks,
Main regulator: shutdown,
Ta = 25°C
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 69 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 5 V
Table 5.18
A/D Conversion Characteristics (V = AV = V
= 4.2 to 5.5 V, V = AV = 0 V,
CC
CC
REF SS SS
T = T , and f = 32 MHz, unless otherwise noted)
(BCLK)
a
opr
Value
Min. Typ. Max.
Symbol
Characteristic
Measurement condition
Unit
Resolution
V
V
= V
CC
—
10 Bits
REF
REF
Absolute error
= V = 5 V
AN_0 to AN_7,
CC
AN0_0 to AN0_7,
AN2_0 to AN2_7,
AN15_0 to AN15_7,
ANEX0, ANEX1
±3 LSB
—
External op-amp
connection mode
±7 LSB
±3 LSB
INL
Integral non-linearity
error
V
= V = 5 V
AN_0 to AN_7,
REF
CC
AN0_0 to AN0_7,
AN2_0 to AN2_7,
AN15_0 to AN15_7,
ANEX0, ANEX1
External op-amp
connection mode
±7 LSB
±1 LSB
DNL
Differential non-linearity
error
—
Offset error
Gain error
±3 LSB
±3 LSB
—
R
t
Resistor ladder
V
= V
4
20
kΩ
LADDER
REF
CC
Conversion time
(10 bits)
φ
= 16 MHz, with sample and hold
AD
CONV
CONV
SAMP
2.06
µs
function
= 16 MHz, without sample and hold
φ
AD
3.69
1.75
µs
µs
µs
function
φ = 16 MHz, with sample and hold
AD
t
Conversion time
(8 bits)
function
= 16 MHz, without sample and hold
φ
AD
3.06
function
φ = 16 MHz
AD
t
Sampling time
0.188
µs
V
V
Analog input voltage
V
REF
0
0.25
1
IA
φ
Operating clock
frequency
without sample and hold function
with sample and hold function
16 MHz
16 MHz
AD
R
Pull-up resistor for open-
circuit detection
PU(AST)
5
5
10
10
15
15
kΩ
kΩ
R
Pull-down resistor for
open-circuit detection
PD(AST)
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 70 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 5 V
Table 5.19
D/A Conversion Characteristics (V = AV = V
= 4.2 to 5.5 V, V = AV = 0 V,
CC
CC
REF SS SS
and T = T , unless otherwise noted)
a
opr
Value
Symbol
Characteristic
Measurement condition
Unit
Min. Typ. Max.
—
—
Resolution
8
1.0
3
Bits
%
Absolute precision
Settling time
t
µs
S
R
Output resistance
4
10
20
kΩ
O
(1)
I
Reference input current
1.5 mA
VREF
Note:
1. One D/A converter is used. The DAi register (i = 0, 1) of the other unused converter is set to 00h. The
resistor ladder for A/D converter is not considered.
Even when the VCUT bit in the AD0CON1 register is set to 0 (V
disconnected), I
is supplied.
REF
VREF
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 71 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 5 V
Timing Requirements (V = 4.2 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
Table 5.20
External Clock Input
Value
Min.
Symbol
t
Characteristic
Unit
Max.
250
External clock input period
62.5
25
ns
ns
ns
ns
ns
%
(X)
c
t
t
t
t
External clock input high level pulse width
External clock input low level pulse width
External clock input rise time
w(XH)
w(XL)
25
5
5
(X)
r
External clock input fall time
(X)
f
t
/ t
External clock input duty
40
60
w
c
Table 5.21
External Bus Timing
Value
Symbol
t
Characteristic
Unit
Min.
Max.
Data setup time for read
Data hold time after read
Data disable time after read
ns
ns
ns
40
0
(D-R)
su
t
(R-D)
h
t
0.5 × t
+ 10
(R-D)
dis
c(Base)
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 72 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 5 V
Timing Requirements (V = 4.2 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
Table 5.22
Timer A Input (Counting input in event counter mode)
Value
Min. Max.
Symbol
t
Characteristic
Unit
TAiIN input clock cycle time
200
80
ns
ns
ns
(TA)
c
t
TAiIN input high level pulse width
TAiIN input low level pulse width
(TAH)
(TAL)
w
w
t
80
Table 5.23
Timer A Input (Gating input in timer mode)
Value
Symbol
t
Characteristic
Unit
Min.
400
Max.
Max.
Max.
TAiIN input clock cycle time
ns
ns
ns
(TA)
c
t
TAiIN input high level pulse width
TAiIN input low level pulse width
180
180
(TAH)
(TAL)
w
w
t
Table 5.24
Timer A Input (External trigger input in one-shot timer mode)
Value
Symbol
t
Characteristic
Unit
Min.
200
TAiIN input clock cycle time
ns
ns
ns
(TA)
c
t
TAiIN input high level pulse width
TAiIN input low level pulse width
80
80
(TAH)
(TAL)
w
w
t
Table 5.25
Timer A Input (External trigger input in pulse-width modulation mode)
Value
Symbol
t
Characteristic
Unit
Min.
80
TAiIN input high level pulse width
TAiIN input low level pulse width
ns
ns
(TAH)
(TAL)
w
w
t
80
Table 5.26
Timer A Input (Increment/decrement count switching input in event counter mode)
Value
Symbol
t
Characteristic
TAiOUT input clock cycle time
Unit
Min.
Max.
2000
ns
ns
ns
ns
ns
(UP)
c
t
t
t
t
TAiOUT input high level pulse width
TAiOUT input low level pulse width
TAiOUT input setup time
1000
1000
400
(UPH)
w
w
su
(UPL)
(UP-TIN)
TAiOUT input hold time
400
(TIN-UP)
h
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 73 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 5 V
Timing Requirements (V = 4.2 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
Table 5.27
Timer B Input (Counting input in event counter mode)
Value
Min. Max.
Symbol
Characteristic
Unit
t
TBiIN input clock cycle time (one edge counting)
TBiIN input high level pulse width (one edge counting)
TBiIN input low level pulse width (one edge counting)
TBiIN input clock cycle time (both edges counting)
TBiIN input high level pulse width (both edges counting)
TBiIN input low level pulse width (both edges counting)
200
80
ns
ns
ns
ns
ns
ns
c(TB)
t
(TBH)
(TBL)
w
t
t
t
t
80
w
200
80
(TB)
c
(TBH)
(TBL)
w
w
80
Table 5.28
Timer B Input (Pulse period measure mode)
Value
Max.
Symbol
Characteristic
Unit
Min.
400
t
TBiIN input clock cycle time
ns
ns
ns
c(TB)
t
TBiIN input high level pulse width
TBiIN input low level pulse width
180
180
(TBH)
(TBL)
w
t
w
Table 5.29
Timer B Input (Pulse-width measure mode)
Value
Max.
Symbol
Characteristic
Unit
Min.
400
t
TBiIN input clock cycle time
ns
ns
ns
c(TB)
t
TBiIN input high level pulse width
TBiIN input low level pulse width
180
180
(TBH)
(TBL)
w
t
w
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 74 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 5 V
Timing Requirements (V = 4.2 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
Table 5.30
Serial Interface
Value
Min. Max.
Symbol
t
Characteristic
Unit
CLKi input clock cycle time
CLKi input high level pulse width
CLKi input low level pulse width
RXDi input setup time
200
80
80
80
ns
ns
ns
ns
ns
(CK)
c
t
t
t
t
(CKH)
w
w
su
(CKL)
(D-C)
RXDi input hold time
90
(C-D)
h
Table 5.31
A/D Trigger Input
Value
Symbol
t
Characteristic
ADTRG input high level pulse width
Unit
Min.
Max.
3
(ADH)
w
---------
ns
ns
Hardware trigger input high level pulse width
φ
AD
t
ADTRG input low level pulse width
Hardware trigger input high level pulse width
(ADL)
w
125
Table 5.32
External Interrupt INTi Input
Value
Min.
250
+ 200
Symbol
t
Characteristic
Unit
Max.
INTi input high level pulse width
INTi input low level pulse width
Edge sensitive
Level sensitive
Edge sensitive
Level sensitive
ns
ns
ns
ns
(INH)
w
t
t
(CPU)
c
c
t
250
+ 200
(INL)
w
(CPU)
Table 5.33
Intelligent I/O
Value
Min. Max.
Symbol
Characteristic
Unit
t
ISCLK2 input clock cycle time
ISCLK2 input high level pulse width
ISCLK2 input low level pulse width
ISRXD2 input setup time
600
270
270
150
100
ns
ns
ns
ns
ns
c(ISCLK2)
t
w(ISCLK2H)
t
w(ISCLK2L)
t
su(RXD-ISCLK2)
t
ISRXD2 input hold time
h(ISCLK2-RXD)
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 75 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 5 V
Timing Requirements (V = 4.2 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
2
Table 5.34
Multi-master I C-bus Interface
Value
Symbol
Characteristic
Standard-mode
Fast-mode
Min.
Unit
Min.
600
600
Max.
Max.
t
MSCL input high level pulse width
MSCL input low level pulse width
MSCL input rise time
600
600
ns
ns
ns
ns
ns
ns
w(SCLH)
t
w(SCLL)
t
1000
300
300
300
300
300
r(SCL)
t
MSCL input fall time
f(SCL)
t
MSDA input rise time
1000
300
r(SDA)
t
MSDA input fall time
f(SDA)
t
t
t
MSCL high level hold time after start
condition/restart condition
h(SDA-SCL)S
su(SCL-SDA)P
w(SDAH)P
(1)
(1)
(1)
2 × t
2 × t
4 × t
+ 40
+ 40
+ 40
ns
ns
ns
c(φIIC)
c(φIIC)
c(φIIC)
MSCL high level setup time for
restart condition/stop condition
MSDA high level pulse width after
stop condition
t
t
MSDA input setup time
MSDA input hold time
100
0
100
0
ns
ns
su(SDA-SCL)
h(SCL-SDA)
Note:
1. The value is calculated by the following formulas based on a value SSC set by bits SSC4 to SSC0 in
the I2CSSCR register:
t
t
t
= SSC ÷ 2 × t
+ 40 [ns]
c(φIIC)
h(SDA-SCL)S
= (SSC ÷ 2 + 1) × t
+ 40 [ns]
su(SCL-SDA)P
c(φIIC)
= (SSC + 1) × t
+ 40 [ns]
c(φIIC)
w(SDAH)P
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 76 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 5 V
Switching Characteristics (V = 4.2 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
Table 5.35
External Bus Timing (Separate bus)
Value
Measurement
Symbol
t
Characteristic
Unit
condition
Min.
Max.
(1)
Chip-select setup time for read
Chip-select hold time after read
Address setup time for read
Address hold time after read
Read pulse width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(S-R)
su
t
t
t
t
t
t
t
t
t
t
t
t
-15
-15
(R-S)
h
c(Base)
(1)
(A-R)
su
t
(R-A)
h
c(Base)
(1)
(R)
w
(1)
Chip-select setup time for write
Chip-select hold time after write
Address setup time for write
Address hold time after write
Write pulse width
(S-W)
su
Refer to
Figure 5.6
1.5 × t
-15
c(Base)
(W-S)
h
(1)
(A-W)
su
1.5 × t
-15
(W-A)
h
c(Base)
(1)
(W)
w
(1)
Data setup time for write
Data hold time after write
(D-W)
su
0
(W-D)
h
Note:
1. The value is calculated by the following formulas based on the base clock cycles (t
) and
c(Base)
respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the
calculation results in a negative value, modify the value to be set. For the details of how to set values,
refer to the User’s manual.
t
t
t
t
= t
= Tsu(A-R) × t
- 15 [ns]
c(Base)
su(S-R)
su(A-R)
= Tw(R) × t
- 10 [ns]
w(R)
c(Base)
= t
= Tsu(A-W) × t
- 15 [ns]
su(S-W)
su(A-W)
c(Base)
= t
= Tw(W) × t
- 10 [ns]
w(W)
su(D-W)
c(Base)
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 77 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 5 V
Switching Characteristics (V = 4.2 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
Table 5.36
External Bus Timing (Multiplexed bus)
Value
Measurement
Symbol
t
Characteristic
Unit
condition
Min.
Max.
(1)
Chip-select setup time for ALE
Chip-select hold time after read
Address setup time for ALE
Address hold time after ALE
Address hold time after read
ALE-read delay time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(S-ALE)
su
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1.5 × t
-15
h(R-S)
c(Base)
(1)
su(A-ALE)
h(ALE-A)
h(R-A)
(2)
t
- 5
c(Base)
1.5 × t
-15
c(Base)
(2)
(2)
t
- 5
t
+ 10
c(Base)
d(ALE-R)
w(ALE)
dis(R-A)
w(R)
c(Base)
(1)
ALE pulse width
Refer to
Figure 5.6
Address disable time after read
Read pulse width
8
(1)
Chip-select hold time after write
Address hold time after write
ALE-write delay time
1.5 × t
1.5 × t
t
-15
-15
h(W-S)
h(W-A)
d(ALE-W)
w(W)
c(Base)
c(Base)
(2)
(2)
- 5
t
+ 10
c(Base)
c(Base)
(1)
(1)
Write pulse width
Data setup time for write
Data hold time after write
su(D-W)
h(W-D)
0.5 × t
c(Base)
Notes:
1. The value is calculated by the following formulas based on the base clock cycles (t
) and
c(Base)
respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the
calculation results in a negative value, modify the value to be set. For the details of how to set values,
refer to the User’s manual.
t
= t
= t
= (Tsu(A-R) - 1) × t
-15 [ns]
su(S-ALE)
su(A-ALE)
w(ALE)
c(Base)
(when Tsu(A-R) is greater than 1)
t
t
t
= t
= t
= 0.5 × t
-15 [ns] (when Tsu(A-R) is 1)
su(S-ALE)
su(A-ALE)
w(ALE)
c(Base)
= Tw(R) × t
-10 [ns]
w(R)
c(Base)
= t
= Tw(W) × t
-10 [ns]
w(W)
su(D-W)
c(Base)
2. When Tsu(A-R) is greater than 1 or Tsu(A-W) is greater than 1. Change “t
when Tsu(A-R) is 1 or Tsu(A-W) is 1.
” to “0.5 × t
”
c(Base)
c(Base)
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 78 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 5 V
Switching Characteristics (V = 4.2 to 5.5 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
Table 5.37
Serial Interface
Value
Max.
Measurement
condition
Symbol
t
Characteristic
Unit
Min.
TXDi output delay time
TXDi output hold time
80
ns
ns
(C-Q)
d
h
Refer to
Figure 5.6
t
0
(C-Q)
Table 5.38
Intelligent I/O
Value
Measurement
condition
Symbol
t
Characteristic
Unit
Min.
Max.
180
ISTXD2 output delay time
ISTXD2 output hold time
ns
ns
(ISCLK2-TXD)
d
h
Refer to
Figure 5.6
t
0
(ISCLK2-RXD)
2
Table 5.39
Multi-master I C-bus Interface (Standard-mode)
Value
Measurement
Characteristic
Symbol
Unit
condition
Min.
2
Max.
t
MSCL output fall time
ns
ns
f(SCL)
t
MSDA output fall time
2
f(SDA)
t
MSCL output delay time after start
condition/restart condition
d(SDA-SCL)S
20 × t
- 120 52 × t - 40
c(φIIC)
ns
c(φIIC)
Refer to
Figure 5.6
t
Restart condition/stop condition
output delay time after MSCL
becomes high
d(SCL-SDA)P
20 × t
2 × t
+ 40 52 × t
+ 120
+ 120
ns
ns
c(φIIC)
c(φIIC)
t
MSDA output delay time
+ 40 3 × t
c(φIIC)
d(SCL-SDA)
c(φIIC)
2
Table 5.40
Multi-master I C-bus Interface (Fast-mode)
Value
Measurement
Symbol
Characteristic
Unit
condition
Min.
Max.
(1)
t
MSCL output fall time
MSDA output fall time
ns
ns
2
f(SCL)
(1)
t
2
f(SDA)
t
MSCL output delay time after start
condition/restart condition
d(SDA-SCL)S
10 × t
- 120 26 × t - 40
c(φIIC)
ns
c(φIIC)
Refer to
Figure 5.6
t
Restart condition/stop condition
output delay time after MSCL
becomes high
d(SCL-SDA)P
10 × t
+ 40 26 × t
+ 120
+ 120
ns
ns
c(φIIC)
c(φIIC)
t
MSDA output delay time
2 × t
+ 40 3 × t
c(φIIC)
d(SCL-SDA)
c(φIIC)
Note:
2
1. External circuits are required to satisfy the I C-bus specification.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 79 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 3.3 V
Table 5.41
Electrical Characteristics (1/3) (V = 3.0 to 3.6 V, V = 0 V, T = T , and
CC
SS
a
opr
f
= 64 MHz, unless otherwise noted)
(CPU)
Value
Measurement
condition
Symbol
Characteristic
Unit
Min.
Typ. Max.
V
High
level
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
OH
output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
voltage P8_6, P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_7,
I
= -1 mA
V
- 0.6
V
V
OH
CC
CC
P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_7, P15_0 to P15_7,
P16_0 to P16_7, P17_0 to P17_7,
(1)
P18_0 to P18_7, P19_0 to P19_7
V
Low
level
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
OL
output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
voltage P8_6, P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_7,
I
= 1 mA
0.5
V
OL
P12_0 to P12_7, P13_0 to P13_7,
P14_3 to P14_7, P15_0 to P15_7,
P16_0 to P16_7, P17_0 to P17_7,
(1)
P18_0 to P18_7, P19_0 to P19_7
Note:
1. Ports P16 to P19 are available in the 176-pin package only.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 80 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 3.3 V
Table 5.42
Electrical Characteristics (2/3) (V = 3.0 to 3.6 V, V = 0 V, T = T , and
CC SS a opr
f
= 64 MHz, unless otherwise noted)
(CPU)
Value
Min. Typ. Max.
Measurement
condition
Symbol
Characteristic
Unit
V
- V
Hysteresis HOLD, RDY, NMI, INT0 to INT8, KI0 to KI3,
TA0IN to TA4IN, TA0OUT to TA4OUT,
TB0IN to TB5IN, CTS0 to CTS10,
CLK0 to CLK10, RXD0 to RXD10,
SCL0 to SCL6, SDA0 to SDA6, SS0 to SS6,
SRXD0 to SRXD6, ADTRG,
T+
T-
0.2
0.2
1.0
1.8
V
V
IIO0_0 to IIO0_7, IIO1_0 to IIO1_7, UD0A,
UD0B, UD1A, UD1B, ISCLK2, ISRXD2,
IEIN
RESET
I
High level XIN, RESET, CNVSS, NSD,
IH
input
current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
V = 3.3 V
4.0
µA
I
P11_0 to P11_7, P12_0 to P12_7,
P13_0 to P13_7, P14_1, P14_3 to P14_7,
P15_0 to P15_7, P16_0 to P16_7,
P17_0 to P17_7, P18_0 to P18_7,
(1)
P19_0 to P19_7
I
Low level XIN, RESET, CNVSS, NSD,
IL
input
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
current
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
V = 0 V
-4.0 µA
I
P11_0 to P11_7, P12_0 to P12_7,
P13_0 to P13_7, P14_1, P14_3 to P14_7,
P15_0 to P15_7, P16_0 to P16_7,
P17_0 to P17_7, P18_0 to P18_7,
(1)
P19_0 to P19_7
R
Pull-up
resistor
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P5_0 to P5_3, P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P13_0 to P13_7, P14_1,
P14_3 to P14_7, P15_0 to P15_7,
PULLUP
V = 0 V
50 100 500 kΩ
I
P17_4 to P17_7, P18_0 to P18_7,
(1)
P19_0 to P19_7
R
R
Feedback XIN
resistor
XIN
f
3
MΩ
MΩ
Feedback XCIN
resistor
XCIN
f
25
Note:
1. Ports P16 to P19 are available in the 176-pin package only.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 81 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 3.3 V
Table 5.43
Electrical Characteristics (3/3)
(V = 3.0 to 3.6 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
Value
Characte
ristic
Symbol
ICC
Measurement condition
Unit
mA
Min. Typ. Max.
Power
supply
current
In single-chip mode,
f(CPU) = 64 MHz, f(BCLK) = 32 MHz,
output pins are left open
and others are
f(XIN) = 8 MHz,
40
9
55
Active: XIN, PLL,
connected to VSS
Stopped: XCIN, OCO
XIN-XOUT
Drive power: low
f(CPU) = fSO(PLL)/24 MHz,
mA
µA
Active: PLL (self-oscillation),
Stopped: XIN, XCIN, OCO
XCIN-XCOUT
Drive power: low
f(CPU) = f(BCLK) = f(XIN)/256 MHz,
f(XIN) = 8 MHz,
670
Active: XIN,
Stopped: PLL, XCIN, OCO
f(CPU) = f(BCLK) = 32.768 kHz,
Active: XCIN,
Stopped: XIN, PLL, OCO,
Main regulator: shutdown
180
190
µA
µA
f(CPU) = f(BCLK) = f(OCO)/4 kHz,
Active: OCO,
Stopped: XIN, PLL, XCIN,
Main regulator: shutdown
f(CPU) = f(BCLK) = f(XIN)/256 MHz,
f(XIN) = 8 MHz,
500 900
µA
µA
Active: XIN,
Stopped: PLL, XCIN, OCO,
Ta = 25°C, Wait mode
f(CPU) = f(BCLK) = 32.768 kHz,
Active: XCIN,
Stopped: XIN, PLL, OCO,
Main regulator: shutdown,
Ta = 25°C, Wait mode
8
140
f(CPU) = f(BCLK) = f(OCO)/4 kHz,
Active: OCO,
Stopped: XIN, PLL, XCIN,
Main regulator: shutdown,
Ta = 25°C, Wait mode
10
5
150
70
µA
µA
Stopped: all clocks,
Main regulator: shutdown,
Ta = 25°C
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 82 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 3.3 V
Table 5.44
A/D Conversion Characteristics (V = AV = V
= 3.0 to 3.6 V, V = AV = 0 V,
CC
CC
REF SS SS
T = T , and f = 32 MHz, unless otherwise noted)
(BCLK)
a
opr
Value
Symbol
Characteristic
Measurement condition
Unit
Bits
Min. Typ. Max.
10
Resolution
V
= V
CC
—
REF
REF
Absolute error
V
V
V
= V = 3.3 V AN_0 to AN_7,
CC
AN0_0 to AN0_7,
AN2_0 to AN2_7,
AN15_0 to AN15_7,
ANEX0, ANEX1
±5
±7
±5
LSB
LSB
LSB
—
External op-amp
connection mode
INL
Integral non-linearity
error
= V = 3.3 V AN_0 to AN_7,
REF
CC
AN0_0 to AN0_7,
AN2_0 to AN2_7,
AN15_0 to AN15_7,
ANEX0, ANEX1
External op-amp
connection mode
±7
±1
LSB
LSB
DNL
Differential non-
linearity error
= V = 3.3 V
REF
CC
—
Offset error
Gain error
±3
±3
LSB
LSB
kΩ
—
R
t
Resistor ladder
V
= V
4
20
LADDER
REF
CC
Conversion time
(10 bits)
φ
= 10 MHz,
CONV
CONV
SAMP
AD
3.3
µs
with sample and hold function
φ = 10 MHz,
AD
t
t
Conversion time
(8 bits)
2.8
0.3
µs
µs
with sample and hold function
φ = 10 MHz
AD
Sampling time
V
Analog input voltage
V
0
0.25
1
V
IA
REF
φ
Operating clock
frequency
without sample and hold function
with sample and hold function
10
MHz
MHz
AD
10
R
Pull-up resistor for
open-circuit detection
PU(AST)
5
5
10
10
15
15
kΩ
kΩ
R
Pull-down resistor for
open-circuit detection
PD(AST)
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 83 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 3.3 V
Table 5.45
D/A Conversion Characteristics (V = AV = V
= 3.0 to 3.6 V, V = AV = 0 V,
CC
CC
REF SS SS
and T = T , unless otherwise noted)
a
opr
Measurement condition
Value
Symbol
Characteristic
Unit
Min. Typ. Max.
—
—
Resolution
8
1.0
3
Bits
%
Absolute precision
Settling time
t
µs
S
R
Output resistance
4
10
20
kΩ
O
(1)
I
Reference input current
1.0
mA
VREF
Note:
1. One D/A converter is used. The DAi register (i = 0, 1) of the other unused converter is set to 00h. The
resistor ladder for A/D converter is not considered.
Even when the VCUT bit in the AD0CON1 register is set to 0 (V
disconnected), I
is supplied.
REF
VREF
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 84 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 3.3 V
Timing Requirements (V = 3.0 to 3.6 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
Table 5.46
External Clock Input
Value
Min.
Symbol
t
Characteristic
Unit
Max.
250
External clock input period
62.5
25
ns
ns
ns
ns
ns
%
(X)
c
t
t
t
t
External clock input high level pulse width
External clock input low level pulse width
External clock input rise time
w(XH)
w(XL)
r(X)
25
5
5
External clock input fall time
(X)
f
t
/ t
External clock input duty
40
60
w
c
Table 5.47
External Bus Timing
Value
Symbol
Characteristic
Unit
Min.
Max.
t
Data setup time for read
Data hold time after read
Data disable time after read
ns
ns
ns
40
0
su(D-R)
t
h(R-D)
t
0.5 × t
+ 10
dis(R-D)
c(Base)
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 85 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 3.3 V
Timing Requirements (V = 3.0 to 3.6 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
Table 5.48
Timer A Input (Counting input in event counter mode)
Value
Min. Max.
Symbol
Characteristic
Unit
t
TAiIN input clock cycle time
200
80
ns
ns
ns
c(TA)
t
TAiIN input high level pulse width
TAiIN input low level pulse width
w(TAH)
t
80
w(TAL)
Table 5.49
Timer A Input (Gating input in timer mode)
Value
Symbol
Characteristic
Unit
Min.
400
180
180
Max.
Max.
Max.
t
TAiIN input clock cycle time
ns
ns
ns
c(TA)
t
TAiIN input high level pulse width
TAiIN input low level pulse width
w(TAH)
t
w(TAL)
Table 5.50
Timer A Input (External trigger input in one-shot timer mode)
Value
Symbol
Characteristic
Unit
Min.
200
80
t
TAiIN input clock cycle time
ns
ns
ns
c(TA)
t
TAiIN input high level pulse width
TAiIN input low level pulse width
w(TAH)
t
80
w(TAL)
Table 5.51
Timer A Input (External trigger input in pulse-width modulation mode)
Value
Symbol
Characteristic
Unit
Min.
80
t
TAiIN input high level pulse width
TAiIN input low level pulse width
ns
ns
w(TAH)
t
80
(TAL)
w
Table 5.52
Timer A Input (Increment/decrement count switching input in event counter mode)
Value
Symbol
Characteristic
TAiOUT input clock cycle time
Unit
Min.
2000
1000
1000
400
Max.
t
ns
ns
ns
ns
ns
c(UP)
t
TAiOUT input high level pulse width
TAiOUT input low level pulse width
TAiOUT input setup time
w(UPH)
t
w(UPL)
t
su(UP-TIN)
t
TAiOUT input hold time
400
h(TIN-UP)
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 86 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 3.3 V
Timing Requirements (V = 3.0 to 3.6 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
Table 5.53
Timer B Input (Counting input in event counter mode)
Value
Min. Max.
Symbol
Characteristic
Unit
t
TBiIN input clock cycle time (one edge counting)
TBiIN input high level pulse width (one edge counting)
TBiIN input low level pulse width (one edge counting)
TBiIN input clock cycle time (both edges counting)
TBiIN input high level pulse width (both edges counting)
TBiIN input low level pulse width (both edges counting)
200
80
ns
ns
ns
ns
ns
ns
c(TB)
t
w(TBH)
t
80
w(TBL)
t
200
80
c(TB)
t
w(TBH)
t
80
w(TBL)
Table 5.54
Timer B Input (Pulse period measure mode)
Value
Max.
Symbol
Characteristic
Unit
Min.
400
180
180
t
TBiIN input clock cycle time
ns
ns
ns
c(TB)
t
TBiIN input high level pulse width
TBiIN input low level pulse width
w(TBH)
t
w(TBL)
Table 5.55
Timer B Input (Pulse-width measure mode)
Value
Max.
Symbol
Characteristic
Unit
Min.
400
180
180
t
TBiIN input clock cycle time
ns
ns
ns
c(TB)
t
TBiIN input high level pulse width
TBiIN input low level pulse width
w(TBH)
t
w(TBL)
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 87 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 3.3 V
Timing Requirements (V = 3.0 to 3.6 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
Table 5.56
Serial Interface
Value
Min. Max.
Symbol
Characteristic
Unit
t
CLKi input clock cycle time
CLKi input high level pulse width
CLKi input low level pulse width
RXDi input setup time
200
80
80
80
ns
ns
ns
ns
ns
c(CK)
t
w(CKH)
t
w(CKL)
t
su(D-C)
t
RXDi input hold time
90
h(C-D)
Table 5.57
A/D Trigger Input
Value
Symbol
Characteristic
ADTRG input high level pulse width
Unit
ns
Min.
Max.
t
3
w(ADH)
---------
Hardware trigger input high level pulse width
φ
AD
t
ADTRG input low level pulse width
Hardware trigger input high level pulse width
w(ADL)
125
ns
Table 5.58
External Interrupt INTi Input
Value
Min.
250
+ 200
Symbol
Characteristic
Unit
Max.
t
INTi input high level pulse width
INTi input low level pulse width
Edge sensitive
Level sensitive
Edge sensitive
Level sensitive
ns
ns
ns
ns
w(INH)
t
t
(CPU)
c
c
t
250
+ 200
(INL)
w
(CPU)
Table 5.59
Intelligent I/O
Value
Min. Max.
Symbol
t
Characteristic
Unit
ISCLK2 input clock cycle time
ISCLK2 input high level pulse width
ISCLK2 input low level pulse width
ISRXD2 input setup time
600
270
270
150
100
ns
ns
ns
ns
ns
(ISCLK2)
c
t
t
t
t
(ISCLK2H)
w
w
su
(ISCLK2L)
(RXD-ISCLK2)
ISRXD2 input hold time
(ISCLK2-RXD)
h
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 88 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 3.3 V
Timing Requirements (V = 3.0 to 3.6 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
2
Table 5.60
Multi-master I C-bus Interface
Value
Symbol
Characteristic
Standard-mode
Fast-mode
Min.
Unit
Min.
600
600
Max.
Max.
t
MSCL input high level pulse width
MSCL input low level pulse width
MSCL input rise time
600
600
ns
ns
ns
ns
ns
ns
w(SCLH)
t
w(SCLL)
t
1000
300
300
300
300
300
r(SCL)
t
MSCL input fall time
f(SCL)
t
MSDA input rise time
1000
300
r(SDA)
t
MSDA input fall time
f(SDA)
t
t
t
MSCL high level hold time after start
condition/restart condition
MSCL high level setup time for
restart condition/stop condition
MSDA high level pulse width after
stop condition
h(SDA-SCL)S
su(SCL-SDA)P
w(SDAH)P
(1)
(1)
(1)
2 × t
2 × t
4 × t
+ 40
+ 40
+ 40
ns
ns
ns
c(φIIC)
c(φIIC)
c(φIIC)
t
t
MSDA input setup time
100
0
100
0
ns
ns
su(SDA-SCL)
MSDA input hold time
h(SCL-SDA)
Note:
1. The value is calculated by the following formulas based on a value SSC set by bits SSC4 to SSC0 in
the I2CSSCR register:
t
t
t
= SSC ÷ 2 × t
+ 40 [ns]
c(φIIC)
h(SDA-SCL)S
= (SSC ÷ 2 + 1) × t
+ 40 [ns]
su(SCL-SDA)P
c(φIIC)
= (SSC + 1) × t
+ 40 [ns]
c(φIIC)
w(SDAH)P
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 89 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 3.3 V
Switching Characteristics (V = 3.0 to 3.6 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
Table 5.61
External Bus Timing (Separate bus)
Value
Measurement
Symbol
Characteristic
Unit
condition
Min.
Max.
(1)
t
Chip-select setup time for read
Chip-select hold time after read
Address setup time for read
Address hold time after read
Read pulse width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
su(S-R)
t
t
- 15
- 15
h(R-S)
c(Base)
(1)
t
su(A-R)
t
t
h(R-A)
c(Base)
(1)
t
w(R)
(1)
t
Chip-select setup time for write
Chip-select hold time after write
Address setup time for write
Address hold time after write
Write pulse width
Refer to
Figure 5.6
su(S-W)
t
1.5 × t
- 15
c(Base)
h(W-S)
(1)
t
su(A-W)
t
1.5 × t
- 15
h(W-A)
c(Base)
(1)
t
w(W)
(1)
t
Data setup time for write
Data hold time after write
su(D-W)
t
0
h(W-D)
Note:
1. The value is calculated by the following formulas based on the base clock cycles (t
) and
c(Base)
respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the
calculation results in a negative value, modify the value to be set. For the details of how to set values,
refer to the User’s manual.
t
t
t
t
= t
= Tsu(A-R) × t
- 15 [ns]
c(Base)
su(S-R)
su(A-R)
= Tw(R) × t
- 10 [ns]
w(R)
c(Base)
= t
= Tsu(A-W) × t
- 15 [ns]
su(S-W)
su(A-W)
c(Base)
= t
= Tw(W) × t
- 10 [ns]
w(W)
su(D-W)
c(Base)
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 90 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 3.3 V
Switching Characteristics (V = 3.0 to 3.6 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
Table 5.62
External Bus Timing (Multiplexed bus)
Value
Measurement
Symbol
Characteristic
Unit
condition
Min.
Max.
(1)
t
Chip-select setup time for ALE
Chip-select hold time after read
Address setup time for ALE
Address hold time after ALE
Address hold time after read
ALE-read delay time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
su(S-ALE)
t
1.5 × t
- 15
h(R-S)
c(Base)
(1)
t
su(A-ALE)
(2)
t
t
- 5
h(ALE-A)
c(Base)
t
1.5 × t
- 15
h(R-A)
c(Base)
(2)
(2)
t
t
- 5
t
+ 10
d(ALE-R)
c(Base)
c(Base)
(1)
t
ALE pulse width
(ALE)
w
Refer to
Figure 5.6
t
t
t
t
t
t
t
t
Address disable time after read
Read pulse width
8
dis(R-A)
w(R)
(1)
Chip-select hold time after write
Address hold time after write
ALE-write delay time
1.5 × t
1.5 × t
t
- 15
- 15
(2)
h(W-S)
h(W-A)
d(ALE-W)
w(W)
c(Base)
c(Base)
- 5
(2)
t
+ 10
c(Base)
c(Base)
(1)
(1)
Write pulse width
Data setup time for write
Data hold time after write
su(D-W)
h(W-D)
0.5 × t
c(Base)
Notes:
1. The value is calculated by the following formulas based on the base clock cycles (t
) and
c(Base)
respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the
calculation results in a negative value, modify the value to be set. For the details of how to set values,
refer to the User’s manual.
t
t
t
t
t
t
= t
= t
= (Tsu(A-R) - 1) × t
-15 [ns] (when Tsu(A-R) is greater than 1)
su(S-ALE)
su(S-ALE)
su(A-ALE)
su(A-ALE)
c(Base)
= 0.5 × t
-15 [ns] (when Tsu(A-R) is 1)
c(Base)
= (Tsu(A-R) - 1) × t
- 20 [ns] (when Tsu(A-R) is greater than 1)
w(ALE)
w(ALE)
c(Base)
= 0.5 × t
- 20 [ns] (when Tsu(A-R) is 1)
-10 [ns]
c(Base)
c(Base)
= Tw(R) × t
w(R)
= t
= Tw(W) × t
-10 [ns]
w(W)
su(D-W)
c(Base)
2. When Tsu(A-R) is greater than 1 or Tsu(A-W) is greater than 1. Change “t
when Tsu(A-R) is 1 or Tsu(A-W) is 1.
” to “0.5 × t
”
c(Base)
c(Base)
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 91 of 99
R32C/116A Group
5. Electrical Characteristics
VCC = 3.3 V
Switching Characteristics (V = 3.0 to 3.6 V, V = 0 V, and T = T , unless otherwise noted)
CC
SS
a
opr
Table 5.63
Serial Interface
Value
Max.
Measurement
condition
Symbol
t
Characteristic
Unit
Min.
TXDi output delay time
TXDi output hold time
80
ns
ns
(C-Q)
d
h
Refer to
Figure 5.6
t
0
(C-Q)
Table 5.64
Intelligent I/O
Value
Measurement
condition
Symbol
t
Characteristic
Unit
Min.
Max.
180
ISTXD2 output delay time
ISTXD2 output hold time
ns
ns
(ISCLK2-TXD)
d
h
Refer to
Figure 5.6
t
0
(ISCLK2-RXD)
2
Table 5.65
Multi-master I C-bus Interface (Standard-mode)
Value
Measurement
Characteristic
Symbol
Unit
condition
Min.
2
Max.
t
MSCL output fall time
ns
ns
f(SCL)
t
MSDA output fall time
2
f(SDA)
t
MSCL output delay time after start
condition/restart condition
d(SDA-SCL)S
20 × t
- 120 52 × t - 40
c(φIIC)
ns
c(φIIC)
Refer to
Figure 5.6
t
Restart condition/stop condition
output delay time after MSCL
becomes high
d(SCL-SDA)P
20 × t
2 ×t
+ 40 52 × t
+ 120
+ 120
ns
ns
c(φIIC)
c(φIIC)
t
MSDA output delay time
+ 40 3 × t
c(φIIC)
d(SCL-SDA)
c(φIIC)
2
Table 5.66
Multi-master I C-bus Interface (Fast-mode)
Value
Measurement
Symbol
Characteristic
Unit
condition
Min.
Max.
(1)
t
MSCL output fall time
MSDA output fall time
ns
ns
2
f(SCL)
(1)
t
2
f(SDA)
t
MSCL output delay time after start
condition/restart condition
d(SDA-SCL)S
10 × t
- 120 26 × t - 40
c(φIIC)
ns
c(φIIC)
Refer to
Figure 5.6
t
Restart condition/stop condition
output delay time after MSCL
becomes high
d(SCL-SDA)P
10 × t
+ 40 26 × t
+ 120
+ 120
ns
ns
c(φIIC)
c(φIIC)
t
MSDA output delay time
2 × t
+ 40 3 × t
c(φIIC)
d(SCL-SDA)
c(φIIC)
Note:
2
1. External circuits are required to satisfy the I C-bus specification.
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 92 of 99
R32C/116A Group
5. Electrical Characteristics
MCU
Pin to be
measured
30 pF
Figure 5.6
Switching Characteristic Measurement Circuit
tc(X)
XIN
tw(XH)
tw(XL)
tr(X)
tf(X)
Figure 5.7
External Clock Input Timing
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 93 of 99
R32C/116A Group
5. Electrical Characteristics
External bus timing (Separate bus)
Read cycle
tcR
tsu(S-R)
th(R-S)
CS0 to CS3
tsu(A-R)
th(R-A)
A23 to A0, BC0 to BC3
tw(R)
RD
tsu(D-R)
th(R-D)
D31 to D0
Write cycle
tcW
tsu(S-W)
th(W-S)
CS0 to CS3
tsu(A-W)
th(W-A)
A23 to A0, BC0 to BC3
WR, WR0 to WR3
D31 to D0
tw(W)
tsu(D-W)
th(W-D)
Measurement conditions
VCC = 4.2 to 5.5 V
VCC = 3.0 to 3.6 V
Item
2.5 V
0.8 V
2.0 V
0.8 V
1.5 V
0.5 V
2.4 V
0.5 V
VIH
VIL
Criterion for
input voltage
VOH
VOL
Criterion for
output voltage
Figure 5.8
External Bus Timing (Separate Bus)
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 94 of 99
R32C/116A Group
5. Electrical Characteristics
External bus timing (Multiplexed bus)
Read timing
tcR
tsu(S-ALE)
tsu(A-ALE)
tw(ALE)
th(R-S)
CS0 to CS3
th(R-A)
A23 to A8, BC0 to BC3
ALE
th(ALE-A)
tsu(A-ALE)
tdis(R-A)
tsu(D-R)
Data
th(R-D)
tdis(R-D)
th(R-D)
A15/D15 to A0/D0,
BC0/D0, BC2/D1
Address
td(ALE-R)
tw(R)
RD
tsu(D-R)
D31 to D8
tcW
Write cycle
tsu(S-ALE)
tsu(A-ALE)
tw(ALE)
th(W-S)
CS0 to CS3
A23 to A8, BC0 to BC3
ALE
th(W-A)
tsu(A-ALE)
th(ALE-A)
tsu(D-W)
Data
th(W-D)
A15/D15 to A0/D0,
BC0/D0, BC2/D1
Address
td(ALE-W)
tw(W)
WR, WR0 to WR3
D31 to D8
tsu(D-W)
th(W-D)
Measurement conditions
Item
VCC = 4.2 to 5.5 V
VCC = 3.0 to 3.6 V
2.5 V
0.8 V
2.0 V
0.8 V
1.5 V
0.5 V
2.4 V
0.5 V
VIH
VIL
Criterion for
input voltage
VOH
VOL
Criterion for
output voltage
Figure 5.9
External Bus Timing (Multiplexed Bus)
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 95 of 99
R32C/116A Group
5. Electrical Characteristics
tc(TA)
tw(TAL)
tw(TAH)
TAiIN input
tc(UP)
tw(UPL)
tw(UPH)
TAiOUT input
In event counter mode
TAiOUT input (input for increment/
decrement count switching)
tsu(UP-TIN)
th(TIN-UP)
TAiIN input (in falling edge counting)
TAiIN input (in rising edge counting)
tc(TB)
tw(TBH)
tw(TBL)
TBiIN input
tc(CK)
tw(CKH)
tw(CKL)
CLKi
TXDi
RXDi
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
tw(ADL)
tw(ADH)
ADTRG input
INTi input
tw(INL)
tw(INH)
2 CPU clock cycles +
300 ns or more
2 CPU clock cycles +
300 ns or more
NMI input
Figure 5.10 Timing of Peripheral Functions
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 96 of 99
R32C/116A Group
5. Electrical Characteristics
tc(SCL)
MSCL
MSDA
tw(SCLH)
tw(SCLL)
tr(SCL)
tf(SCL)
tr(SDA)
tf(SDA)
tw(SDAH)P
tsu(SCL-SDA)P
th(SDA-SCL)S
tsu(SCL-SDA)P
MSCL
MSDA (input)
th(SDA-SCL)S
td(SDA-SCL)S
td(SCL-SDA)P
td(SCL-SDA)P
MSCL
MSDA (output)
td(SDA-SCL)S
tsu(SDA-SCL)
th(SCL-SDA)
MSCL
MSDA (input)
td(SCL-SDA)
MSCL
MSDA (output)
2
Figure 5.11 Timing of Multi-master I C-bus Interface
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 97 of 99
R32C/116A Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS[Typ.]
1.8g
P-LQFP176-24x24-0.50
PLQP0176KB-A 176P6Q-A/FP-176E/FP-176EV
HD
*1
D
132
89
133
88
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
bp
b1
Dimension in Millimeters
Reference
Symbol
Terminal cross section
Min Nom Max
D
23.9 24.0 24.1
23.9 24.0 24.1
1.4
E
A2
HD
HE
25.8 26.0 26.2
25.8 26.0 26.2
1.7
176
45
A
A1
bp
0.05 0.1 0.15
0.15 0.20 0.25
0.18
1
44
Index mark
F
ZD
b1
c
c1
S
0.09 0.145 0.20
0.125
L
θ
e
0°
8°
L1
*3
0.5
y
S
bp
e
x
M
x
0.08
0.10
Detail F
y
ZD
ZE
1.25
1.25
0.35 0.5 0.65
1.0
L
L1
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 98 of 99
R32C/116A Group
Appendix 1. Package Dimensions
JEITA Package Code
RENESAS Code
PLQP0144KA-A
Previous Code
MASS[Typ.]
1.2g
P-LQFP144-20x20-0.50
144P6Q-A / FP-144L / FP-144LV
HD
*1
D
108
73
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
109
72
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
Terminal cross section
D
E
19.9 20.0 20.1
19.9 20.0 20.1
1.4
A2
HD
HE
A
21.8 22.0 22.2
21.8 22.0 22.2
1.7
144
37
A1
bp
b1
c
0.1
0.05
0.15
1
ZD
36
0.17 0.22 0.27
0.20
Index mark
F
0.09
0.20
0.145
0.125
S
c1
L
L1
0°
8°
*3
e
x
0.5
bp
e
y
S
x
Detail F
0.08
0.10
y
ZD
ZE
L
1.25
1.25
0.5
0.35
0.65
L1
1.0
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 99 of 99
Revision History
R32C/116A Group Datasheet
Description
Summary
Rev.
Date
Page
—
0.50
1.00
Mar 05, 2010
Jul 16, 2010
Initial release
—
Second edition released
This manual in general
—
• Applied new Renesas templates and formats to the manual
• Changed company name to “Renesas Electronics Corporation” and
changed related descriptions due to business merger of Renesas
Technology Corporation and NEC Electronics Corporation (under
Chapters 1 and 5)
• Modified expressions “version N”, “version D”, and “version P” to “N
version”, “D version”, and “P version”, respectively (under Chapters 1
and 5)
Chapter 1. Overview
3, 5
6
• Specified current consumptions in Tables 1.2 and 1.4; Deleted Note 1
• Corrected package codes in Table 1.5
8
• Deleted Note 1 from Figure 1.2
20
• Modified expression “fC” in Table 1.15 to “low speed clock”
Chapter 4. SFRs
35, 38 • Changed register name “Group i Timer Measurement Prescaler
Register” in Tables 4.6 and 4.9 to “Group i Time Measurement
Prescaler Register”
40
• Modified expression “XY Control Register” in Table 4.11 to “X-Y
Control Register”
42
• Changed register name “UART2 Transmission/Receive Mode
Register” in Table 4.13 to “UART2 Transmit/Receive Mode Register”;
Changed hexadecimal format of reset values for registers TABSR,
ONSF, and TRGSR to binary
44
55
56
—
• Modified reset value “X00X X000b” for AD0CON2 register in Table
4.15 to “XX0X X000b”
• Changed register name “External Interrupt Source Select Register i” in
Table 4.26 to “External Interrupt Request Source Select Register i”
• Added addresses “044420h to 0467FFh” to Table 4.27
Chapter 5. Electrical Characteristics
• Initially added
Appendix 1. Package Dimensions
98, 99 • Added a seating plane to the drawing of package dimension
All trademarks and registered trademarks are the property of their respective owners.
A- 1
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
be disclosed by Renesas Electronics such as that disclosed through our website.
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technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
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4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and
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the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is
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assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
7. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product
depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas
Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the
use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.
The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;
personal electronic equipment; and industrial robots.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically
designed for life support.
"Specific":
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implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or system manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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Refer to "http://www.renesas.com/" for the latest and detailed information.
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