R1RW0404DGE-2PR [RENESAS]
4M HIGH SPEED SRAM (1-MWORD X 4-BIT); 4M高速SRAM （ 1 - MWORD X 4 - BIT ）
| 型号： | R1RW0404DGE-2PR |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 4M HIGH SPEED SRAM (1-MWORD X 4-BIT) |
| 文件： | 总13页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
R1RW0404D Series
4M High Speed SRAM (1-Mword × 4-bit)
REJ03C0115-0100Z
Rev. 1.00
Mar.12.2004
Description
The R1RW0404D is a 4-Mbit high speed static RAM organized 1-Mword × 4-bit. It has realized high
speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit
designing technology. It is most appropriate for the application which requires high speed and high density
memory, such as cache and buffer memory in system. The R1RW0404D is packaged in 400-mil 32-pin
SOJ for high density surface mounting.
Features
•
•
•
Single supply: 3.3 V ± 0.3 V
Access time: 12 ns (max)
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Directly TTL compatible
•
•
All inputs and outputs
•
•
•
Operating current: 100 mA (max)
TTL standby current: 40 mA (max)
CMOS standby current: 5 mA (max)
: 0.8 mA (max) (L-version)
•
•
•
Data retention current: 0.4 mA (max) (L-version)
Data retention voltage: 2 V (min) (L-version)
Center VCC and VSS type pin out
Rev.1.00, Mar.12.2004, page 1 of 11
R1RW0404D Series
Ordering Information
Type No.
Access time
12 ns
Package
R1RW0404DGE-2PR
R1RW0404DGE-2LR
400-mil 32-pin plastic SOJ (32P0K)
12 ns
Pin Arrangement
32-pin SOJ
1
A0
A1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A19
2
A18
A17
A16
A15
OE#
I/O4
VSS
VCC
I/O3
A14
A13
A12
A11
A10
NC
3
A2
4
A3
5
A4
6
CS#
I/O1
VCC
VSS
I/O2
WE#
A5
7
8
9
10
11
12
13
14
15
16
A6
A7
A8
A9
(Top view)
Pin Description
Pin name
A0 to A19
I/O1 to I/O4
CS#
Function
Address input
Data input/output
Chip select
OE#
Output enable
Write enable
Power supply
Ground
WE#
VCC
VSS
NC
No connection
Rev.1.00, Mar.12.2004, page 2 of 11
R1RW0404D Series
Block Diagram
(LSB)
A14
A13
A12
A5
VCC
VSS
1024-row × 64-column ×
16-block × 4-bit
A6
A7
Row
decoder
A11
A10
A3
(4,194,304 bits)
A1
(MSB)
CS
Column I/O
I/O1
.
Input
data
control
Column decoder
CS
.
.
I/O4
A8 A9 A19 A17 A18 A15 A0 A2 A4 A16
(LSB)
(MSB)
WE#
CS#
OE#
CS
Rev.1.00, Mar.12.2004, page 3 of 11
R1RW0404D Series
Operation Table
CS#
H
OE#
×
WE#
Mode
VCC current
I/O
Ref. cycle
×
Standby
Output disable
Read
ISB, ISB1
ICC
High-Z
High-Z
DOUT
DIN
L
H
H
H
L
L
L
ICC
Read cycle (1) to (3)
Write cycle (1)
L
H
Write
ICC
L
L
L
Write
ICC
DIN
Write cycle (2)
Note: H: VIH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Supply voltage relative to VSS
Voltage on any pin relative to VSS
Power dissipation
VCC
−0.5 to +4.6
−0.5*1 to VCC + 0.5*2
V
VT
V
PT
1.0
W
°C
°C
°C
Operating temperature
Storage temperature
Topr
Tstg
Tbias
0 to +70
−55 to +125
−10 to +85
Storage temperature under bias
Notes: 1. VT (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns.
2. VT (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns.
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Parameter
Symbol
VCC*3
VSS*4
VIH
Min
3.0
Typ
3.3
0
Max
Unit
V
Supply voltage
3.6
0
0
V
Input voltage
2.0
VCC + 0.5*2
V
VIL
−0.5*1
0.8
V
Notes: 1. VIL (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns.
2. VIH (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns.
3. The supply voltage with all VCC pins must be on the same level.
4. The supply voltage with all VSS pins must be on the same level.
Rev.1.00, Mar.12.2004, page 4 of 11
R1RW0404D Series
DC Characteristics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
Parameter
Symbol
IILII
Min
Max
2
Unit
µA
Test conditions
VIN = VSS to VCC
VIN = VSS to VCC
Input leakage current
Output leakage current
Operation power supply current
IILOI
2
µA
ICC
100
mA
Min cycle
CS# = VIL, lOUT = 0 mA
Other inputs = VIH/VIL
Standby power supply current
ISB
40
5
mA
mA
Min cycle, CS# = VIH,
Other inputs = VIH/VIL
ISB1
f = 0 MHz
VCC ≥ CS# ≥ VCC − 0.2 V,
(1) 0 V ≤ VIN ≤ 0.2 V or
(2) VCC ≥ VIN ≥ VCC − 0.2 V
1
*
0.8*1
Output voltage
VOL
VOH
0.4
V
V
IOL = 8 mA
2.4
IOH = −4 mA
Note: 1. This characteristics is guaranteed only for L-version.
Capacitance
(Ta = +25°C, f = 1.0 MHz)
Parameter
Symbol
CIN
Min
Max
6
Unit
Test conditions
VIN = 0 V
Input capacitance*1
Input/output capacitance*1
pF
pF
CI/O
8
VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
Rev.1.00, Mar.12.2004, page 5 of 11
R1RW0404D Series
AC Characteristics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.)
Test Conditions
•
•
•
•
Input pulse levels: 3.0 V/0.0 V
Input rise and fall time: 3 ns
Input and output timing reference levels: 1.5 V
Output load: See figures (Including scope and jig)
1.5 V
3.3 V
319Ω
RL=50 Ω
DOUT
Zo=50 Ω
DOUT
353Ω
30 pF
5 pF
Output load (A)
Output load (B)
(for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW
)
Read Cycle
R1RW0404D
-2
Parameter
Symbol
tRC
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Read cycle time
12
Address access time
tAA
12
12
6
Chip select access time
tACS
tOE
Output enable to output valid
Output hold from address change
Chip select to output in low-Z
Output enable to output in low-Z
Chip deselect to output in high-Z
Output disable to output in high-Z
tOH
3
3
0
tCLZ
1
1
1
1
tOLZ
tCHZ
tOHZ
6
6
Rev.1.00, Mar.12.2004, page 6 of 11
R1RW0404D Series
Write Cycle
R1RW0404D
-2
Min
12
8
Parameter
Symbol
tWC
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Write cycle time
Address valid to end of write
Chip select to end of write
Write pulse width
tAW
tCW
8
9
8
6
7
tWP
8
Address setup time
tAS
0
Write recovery time
tWR
0
Data to write time overlap
Data hold from write time
Write disable to output in low-Z
Output disable to output in high-Z
Write enable to output in high-Z
tDW
6
tDH
0
tOW
3
1
1
1
tOHZ
tWHZ
6
6
Notes: 1. Transition is measured ±200 mV from steady voltage with output load (B). This parameter is
sampled and not 100% tested.
2. Address should be valid prior to or coincident with CS# transition low.
3. WE# and/or CS# must be high during address transition time.
4. If CS# and OE# are low during this period, I/O pins are in the output state. Then, the data input
signals of opposite phase to the outputs must not be applied to them.
5. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE#
transition, output remains a high impedance state.
6. tAS is measured from the latest address transition to the later of CS# or WE# going low.
7. tWR is measured from the earlier of CS# or WE# going high to the first address transition.
8. A write occurs during the overlap of a low CS# and a low WE#. A write begins at the latest
transition among CS# going low and WE# going low. A write ends at the earliest transition
among CS# going high and WE# going high. tWP is measured from the beginning of write to the
end of write.
9. tCW is measured from the later of CS# going low to the end of write.
Rev.1.00, Mar.12.2004, page 7 of 11
R1RW0404D Series
Timing Waveforms
Read Timing Waveform (1) (WE# = VIH)
tRC
Address
Valid address
tAA
tOH
tCHZ
tACS
CS#
OE#
tOE
tOHZ
tOLZ
tCLZ
High impedance
DOUT
Valid data
Read Timing Waveform (2) (WE# = VIH, CS# = VIL, OE# = VIL)
tRC
Address
Valid address
tAA
tOH
tOH
Valid data
DOUT
Rev.1.00, Mar.12.2004, page 8 of 11
R1RW0404D Series
Read Timing Waveform (3) (WE# = VIH, CS# = VIL, OE# = VIL)*2
tRC
CS#
tACS
tCHZ
tCLZ
High
impedance
High
impedance
DOUT
Valid data
Write Timing Waveform (1) (WE# Controlled)
tWC
Valid address
tAW
Address
tWR
OE#
tCW
CS#*3
tAS
tWP
WE#*3
DOUT
DIN
tOHZ
High impedance*5
tDW
tDH
4
4
*
*
Valid data
Rev.1.00, Mar.12.2004, page 9 of 11
R1RW0404D Series
Write Timing Waveform (2) (CS# Controlled)
tWC
Valid address
tCW
Address
CS# *3
tWR
tAW
tWP
WE# *3
DOUT
DIN
tAS
tWHZ
tOW
High impedance*5
tDW
tDH
4
4
*
*
Valid data
Rev.1.00, Mar.12.2004, page 10 of 11
R1RW0404D Series
Low VCC Data Retention Characteristics
(Ta = 0 to +70°C)
This characteristics is guaranteed only for L-version.
Parameter
Symbol
Min
Max
Unit Test conditions
VCC for data retention
VDR
2.0
V
VCC ≥ CS# ≥ VCC − 0.2 V
(1) 0 V ≤ VIN ≤ 0.2 V or
(2) VCC ≥ VIN ≥ VCC − 0.2 V
Data retention current
ICCDR
400
µA
VCC = 3 V, VCC ≥ CS# ≥ VCC − 0.2 V
(1) 0 V ≤ VIN ≤ 0.2 V or
(2) VCC ≥ VIN ≥ VCC − 0.2 V
Chip deselect to data
retention time
tCDR
0
5
ns
See retention waveform
Operation recovery time tR
ms
Low VCC Data Retention Timing Waveform
Data retention mode
tR
tCDR
VCC
3.0 V
VDR
2.0 V
CS#
0 V
V
CC ≥ CS# ≥ VCC − 0.2 V
Rev.1.00, Mar.12.2004, page 11 of 11
Revision History
R1RW0404D Series Data Sheet
Rev. Date
Contents of Modification
Page Description
0.01 Oct. 01, 2003
1.00 Mar.12.2004
Initial issue
Deletion of Preliminary
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