PD46184184BF1-E33-EQ1-A [RENESAS]
18M-BIT DDR II SRAM 4-WORD BURST OPERATION; 18M位DDR II SRAM 4字突发操作
| 型号： | PD46184184BF1-E33-EQ1-A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 18M-BIT DDR II SRAM 4-WORD BURST OPERATION |
| 文件： | 总39页 (文件大小：598K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
μPD46185084B
μPD46185094B
μPD46185184B
μPD46185364B
R10DS0113EJ0200
Rev.2.00
18M-BIT QDRTM II SRAM
4-WORD BURST OPERATION
Nov 09, 2012
Description
The μPD46185084B is a 2,097,152-word by 8-bit, the μPD46185094B is a 2,097,152-word by 9-bit, the
μPD46185184B is a 1,048,576-word by 18-bit and the μPD46185364B is a 524,288-word by 36-bit synchronous
quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory
cell.
The μPD46185084B, μPD46185094B, μPD46185184B and μPD46185364B integrate unique synchronous
peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are
latched on the positive edge of K and K#. These products are suitable for application which require
synchronous operation, high speed, low voltage, high density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
• 1.8 ± 0.1 V power supply
• 165-pin PLASTIC BGA (13 x 15)
• HSTL interface
• PLL circuitry for wide output data valid window and future frequency scaling
• Separate independent read and write data ports with concurrent transactions
• 100% bus utilization DDR READ and WRITE operation
• Four-tick burst for reduced address frequency
• Two input clocks (K and K#) for precise DDR timing at clock rising edges only
• Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
• Internally self-timed write control
• Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.
• User programmable impedance output (35 to 70 Ω)
• Fast clock cycle time : 3.3 ns (300 MHz), 4.0 ns (250 MHz)
• Simple control logic for easy depth expansion
• JTAG 1149.1 compatible test access port
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 1 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Ordering Information
Core
Supply
Voltage
Operating
Ambient
Organization
(word x bit)
Cycle
time
Clock
frequency
Part No.
Package
Temperature
μPD46185084BF1-E33-EQ1-A
μPD46185084BF1-E40-EQ1-A
μPD46185094BF1-E33-EQ1-A
μPD46185094BF1-E40-EQ1-A
μPD46185184BF1-E33-EQ1-A
μPD46185184BF1-E40-EQ1-A
μPD46185364BF1-E33-EQ1-A
μPD46185364BF1-E40-EQ1-A
μPD46185084BF1-E33Y-EQ1-A
μPD46185084BF1-E40Y-EQ1-A
μPD46185094BF1-E33Y-EQ1-A
μPD46185094BF1-E40Y-EQ1-A
μPD46185184BF1-E33Y-EQ1-A
μPD46185184BF1-E40Y-EQ1-A
μPD46185364BF1-E33Y-EQ1-A
μPD46185364BF1-E40Y-EQ1-A
μPD46185084BF1-E33-EQ1
μPD46185084BF1-E40-EQ1
μPD46185094BF1-E33-EQ1
μPD46185094BF1-E40-EQ1
μPD46185184BF1-E33-EQ1
μPD46185184BF1-E40-EQ1
μPD46185364BF1-E33-EQ1
μPD46185364BF1-E40-EQ1
μPD46185084BF1-E33Y-EQ1
μPD46185084BF1-E40Y-EQ1
μPD46185094BF1-E33Y-EQ1
μPD46185094BF1-E40Y-EQ1
μPD46185184BF1-E33Y-EQ1
μPD46185184BF1-E40Y-EQ1
μPD46185364BF1-E33Y-EQ1
μPD46185364BF1-E40Y-EQ1
2M x 8
2M x 9
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
3.3ns
4.0ns
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
300MHz
250MHz
TA = 0 to 70°C
165-pin
PLASTIC
BGA
1.8 0.1 V
(13 x 15)
Lead-free
1M x 18
512K x 36
2M x 8
1.8 0.1 V TA = −40 to 85°C
2M x 9
1M x 18
512K x 36
2M x 8
TA = 0 to 70°C
165-pin
PLASTIC
BGA
1.8 0.1 V
2M x 9
(13 x 15)
Lead
1M x 18
512K x 36
2M x 8
1.8 0.1 V TA = −40 to 85°C
2M x 9
1M x 18
512K x 36
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 2 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[μPD46185084B]
2M x 8
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
CQ#
NC
A
NC
NC
NC
Q4
NC
Q5
VDDQ
NC
NC
D6
W#
A
NW1#
NC/288M
A
K#
K
R#
A
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
VSS/72M
NC
NC/144M
NW0#
A
VSS/36M
NC
NC
NC
VSS
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
NC
NC
D4
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
NC
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
D2
NC
NC
NC
G
H
J
NC
D5
NC
DLL#
NC
VREF
NC
VREF
Q1
K
L
NC
NC
NC
NC
Q6
NC
M
N
P
R
NC
NC
NC
NC
Q7
A
NC
NC
D7
VSS
VSS
NC
NC
NC
A
A
C
A
A
NC
TDO
TCK
A
A
C#
A
A
TMS
A
: Address inputs
: Data inputs
: Data outputs
: Read input
TMS
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
D0 to D7
Q0 to Q7
R#
TDI
TCK
TDO
VREF
VDD
W#
: Write input
NW0#, NW1#
K, K#
: Nibble Write data select
: Input clock
VDD
VSS
NC
Q
: Power Supply
C, C#
: Output clock
: Ground
CQ, CQ#
ZQ
: Echo clock
: No connection
: Output impedance matching
: PLL disable
NC/xxM : Expansion address for xxMb
DLL#
Remarks 1. ×××# indicates active LOW.
2. Refer to Package Dimensions for the index mark.
3. 2A, 7A, 10A and 5B are expansion addresses : 10A for 36Mb
: 10A and 2A for 72Mb
: 10A, 2A and 7A for 144Mb.
: 10A, 2A, 7A and 5B for 288Mb.
2A and 10A of this product can also be used as NC.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 3 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[μPD46185094B]
2M x 9
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
CQ#
NC
A
NC
NC
NC
Q5
NC
Q6
VDDQ
NC
NC
D7
W#
A
NC
NC/288M
A
K#
K
R#
A
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
VSS/72M
NC
NC/144M
BW0#
A
VSS/36M
NC
NC
NC
VSS
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
NC
NC
D5
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
NC
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
D3
NC
NC
NC
G
H
J
NC
D6
NC
DLL#
NC
VREF
NC
VREF
Q2
K
L
NC
NC
NC
NC
Q7
NC
M
N
P
R
NC
NC
NC
NC
Q8
A
NC
NC
D8
VSS
VSS
NC
NC
NC
A
A
C
A
A
D0
TDO
TCK
A
A
C#
A
A
TMS
A
: Address inputs
: Data inputs
: Data outputs
: Read input
TMS
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
D0 to D8
Q0 to Q8
R#
TDI
TCK
TDO
VREF
VDD
W#
: Write input
BW0#
K, K#
C, C#
CQ, CQ#
ZQ
: Byte Write data select
: Input clock
V
DDQ
: Power Supply
: Output clock
VSS
NC
: Ground
: Echo clock
: No connection
: Output impedance matching
: PLL disable
NC/xxM : Expansion address for xxMb
DLL#
Remarks 1. ×××# indicates active LOW.
2. Refer to Package Dimensions for the index mark.
3. 2A, 7A, 10A and 5B are expansion addresses : 10A for 36Mb
: 10A and 2A for 72Mb
: 10A, 2A and 7A for 144Mb
: 10A, 2A, 7A and 5B for 288Mb
2A and 10A of this product can also be used as NC.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 4 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[μPD46185184B]
1M x 18
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
CQ#
NC
W#
A
BW1#
NC
A
K#
K
R#
A
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
VSS/144M NC/36M
NC/288M
BW0#
A
VSS/72M
NC
Q9
NC
D9
D10
Q10
Q11
D12
Q13
VDDQ
D14
Q14
D15
D16
Q16
Q17
A
NC
VSS
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
Q7
NC
D11
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
D6
NC
Q12
D13
VREF
NC
NC
G
H
J
NC
NC
DLL#
NC
VREF
Q4
K
L
NC
NC
D3
NC
Q15
NC
NC
M
N
P
R
NC
Q1
NC
D17
NC
VSS
VSS
NC
NC
A
A
C
A
A
D0
TDO
TCK
A
A
C#
A
A
TMS
A
: Address inputs
: Data inputs
: Data outputs
: Read input
TMS
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
D0 to D17
Q0 to Q17
R#
TDI
TCK
TDO
VREF
VDD
W#
: Write input
BW0#, BW1#
K, K#
: Byte Write data select
: Input clock
VDD
VSS
NC
Q
: Power Supply
C, C#
: Output clock
: Ground
CQ, CQ#
ZQ
: Echo clock
: No connection
: Output impedance matching
: PLL disable
NC/xxM : Expansion address for xxMb
DLL#
Remarks 1. ×××# indicates active LOW.
2. Refer to Package Dimensions for the index mark.
3. 2A, 3A, 7A and 10A are expansion addresses : 3A for 36Mb
: 3A and 10A for 72Mb
: 3A, 10A and 2A for 144Mb
: 3A, 10A, 2A and 7A for 288Mb
2A and 10A of this product can also be used as NC.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 5 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[μPD46185364B]
512K x 36
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
CQ#
Q27
D27
D28
Q29
Q30
D30
DLL#
D31
Q32
Q33
D33
D34
Q35
TDO
W#
A
BW2#
BW3#
A
K#
K
BW1#
BW0#
A
R#
A
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
VSS/288M NC/72M
NC/36M VSS/144M
Q18
Q28
D20
D29
Q21
D22
VREF
Q31
D32
Q24
Q34
D26
D35
TCK
D18
D19
Q19
Q20
D21
Q22
VDDQ
D23
Q23
D24
D25
Q25
Q26
A
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
D10
Q10
Q9
Q17
Q7
VSS
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
D15
D6
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
Q14
D13
VREF
Q4
G
H
J
K
L
D3
Q11
Q1
M
N
P
R
VSS
VSS
D9
A
A
C
A
A
D0
A
A
C#
A
A
A
TMS
A
: Address inputs
: Data inputs
: Data outputs
: Read input
TMS
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
D0 to D35
Q0 to Q35
R#
TDI
TCK
TDO
VREF
VDD
W#
: Write input
BW0# to BW3# : Byte Write data select
K, K#
C, C#
CQ, CQ#
ZQ
: Input clock
VDD
VSS
NC
Q
: Power Supply
: Output clock
: Ground
: Echo clock
: No connection
: Output impedance matching
: PLL disable
NC/xxM : Expansion address for xxMb
DLL#
Remarks 1. ×××# indicates active LOW.
2. Refer to Package Dimensions for the index mark.
3. 2A, 3A and 10A are expansion addresses : 9A for 36Mb
: 9A and 3A for 72Mb
: 9A, 3A and 10A for 144Mb
: 9A, 3A, 10A and 2A for 288Mb
2A and 10A of this product can also be used as NC.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 6 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Pin Description
(1/2)
Symbol
Type
Input
Description
A
Synchronous Address Inputs: These inputs are registered and must meet the setup and
hold times around the rising edge of K. All transactions operate on a burst of four words
(two clock periods of bus activity). These inputs are ignored when device is deselected,
i.e., NOP (R# = W# = HIGH).
D0 to Dxx
Input
Synchronous Data Inputs: Input data must meet setup and hold times around the rising
edges of K and K# during WRITE operations. See Pin Arrangement for ball site location
of individual signals.
x8 device uses D0 to D7.
x9 device uses D0 to D8.
x18 device uses D0 to D17.
x36 device uses D0 to D35.
Q0 to Qxx
Output
Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to
K and K# rising edges if C and C# are tied HIGH. Data is output in synchronization with C
and C# (or K and K#), depending on the R# command. See Pin Arrangement for ball site
location of individual signals.
x8 device uses Q0 to Q7.
x9 device uses Q0 to Q8.
x18 device uses Q0 to Q17.
x36 device uses Q0 to Q35.
R#
Synchronous Read: When LOW this input causes the address inputs to be registered and
a READ cycle to be initiated. This input must meet setup and hold times around the rising
edge of K. If a READ command (R# = LOW) is input, an input of R# on the subsequent
rising edge of K is ignored.
Synchronous Write: When LOW this input causes the address inputs to be registered and
a WRITE cycle to be initiated. This input must meet setup and hold times around the rising
edge of K. If a WRITE command (W# = LOW) is input, an input of W# on the subsequent
rising edge of K is ignored.
Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their
respective byte or nibble to be registered and written during WRITE cycles. These signals
must meet setup and hold times around the rising edges of K and K# for each of the two
rising edges comprising the WRITE cycle. See Pin Arrangement for signal to data
relationships.
Input
Input
Input
W#
BWx#
NWx#
x8 device uses NW0#, NW1#.
x9 device uses BW0#.
x18 device uses BW0#, BW1#.
x36 device uses BW0# to BW3#.
See Byte Write Operation for relation between BWx#, NWx# and Dxx.
Input Clock: This input clock pair registers address and control inputs on the rising edge of
K, and registers data on the rising edge of K and the rising edge of K#. K# is ideally 180
degrees out of phase with K. All synchronous inputs must meet setup and hold times
around the clock rising edges.
Output Clock: This clock pair provides a user controlled means of tuning device output
data. The rising edge of C# is used as the output timing reference for first and third output
data. The rising edge of C is used as the output reference for second and fourth output
data. Ideally, C# is 180 degrees out of phase with C. When use of K and K# as the
reference instead of C and C#, then fixed C and C# to HIGH. Operation cannot be
guaranteed unless C and C# are fixed to HIGH (i.e. toggle of C and C#).
K, K#
C, C#
Input
Input
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 7 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
(2/2)
Symbol
Type
Output
Description
CQ, CQ#
Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched
to the synchronous data outputs and can be used as a data valid indication. These signals
run freely and do not stop when Q tristates. If C and C# are stopped (if K and K# are
stopped in the single clock mode), CQ and CQ# will also stop.
ZQ
Input
Input
Output Impedance Matching Input: This input is used to tune the device outputs to the
system data bus impedance. Q, CQ and CQ# output impedance are set to 0.2 x RQ,
where RQ is a resistor from this bump to ground. The output impedance can be minimized
by directly connect ZQ to VDDQ. This pin cannot be connected directly to GND or left
unconnected. The output impedance is adjusted every 20 μs upon power-up to account
for drifts in supply voltage and temperature. After replacement for a resistor, the new
output impedance is reset by implementing power-on sequence.
PLL Disable: When debugging the system or board, the operation can be performed at a
clock frequency slower than TKHKH (MAX.) without the PLL circuit being used, if DLL# =
LOW. The AC/DC characteristics cannot be guaranteed. For normal operation, DLL#
must be HIGH and it can be connected to VDDQ through a 10 kΩ or less resistor.
IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the
JTAG function is not used in the circuit.
IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to VSS if the JTAG function
is not used in the circuit.
IEEE 1149.1 Test Output: 1.8 V I/O level.
When providing any external voltage to TDO signal, it is recommended to pull up to VDD.
HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the
input buffers.
Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC
Characteristics for range.
DLL#
TMS
TDI
TCK
Input
Input
Output
−
TDO
VREF
VDD
Supply
Supply
VDDQ
Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible. See
Recommended DC Operating Conditions and DC Characteristics for range.
VSS
Supply
Power Supply: Ground
NC
−
No Connect: These signals are not connected internally.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 8 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Block Diagram
[μPD46185084B]
19
ADDRESS
R#
ADDRESS
19
REGISTRY
W#
& LOGIC
K
W#
MUX
NW0#
8
2
16
16
16
NW1#
Q0 to Q7
219x 32
DATA
32
8
D0 to D7
R#
REGISTRY
& LOGIC
MEMORY
ARRAY
16
K
CQ,
CQ#
MUX
K
K
C, C#
K#
OR
K, K#
[μPD46185094B]
19
ADDRESS
R#
ADDRESS
REGISTRY
& LOGIC
19
W#
K
W#
MUX
MUX
BW0#
9
18
18
18
18
Q0 to Q8
219x 36
DATA
36
9
D0 to D8
REGISTRY
& LOGIC
MEMORY
ARRAY
2
CQ,
CQ#
R#
K
K
K
C, C#
OR
K#
K, K#
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 9 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
[μPD46185184B]
18
ADDRESS
R#
ADDRESS
18
REGISTRY
W#
& LOGIC
K
W#
MUX
BW0#
36
36
36
18
2
BW1#
218x 72
Q0 to Q17
DATA
72
18
D0 to D17
R#
REGISTRY
& LOGIC
MEMORY
ARRAY
36
K
CQ,
CQ#
MUX
K
K
C, C#
K#
OR
K, K#
[μPD46185364B]
17
ADDRESS
R#
ADDRESS
REGISTRY
& LOGIC
17
W#
K
W#
MUX
MUX
BW0#
BW1#
BW2#
72
72
72
36
2
217x 144
MEMORY
ARRAY
Q0 to Q35
DATA
144
BW3#
36
D0 to D35
REGISTRY
& LOGIC
72
K
CQ,
CQ#
R#
K
K
C, C#
OR
K#
K, K#
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 10 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Power-On Sequence in QDR II SRAM
QDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
The following timing charts show the recommended power-on sequence.
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ
can be applied simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during power-up. The
following power-down supply voltage removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ
can be removed simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during power-down.
Power-On Sequence
Apply power and tie DLL# to HIGH.
Apply VDDQ before VREF or at the same time as VREF
.
Provide stable clock for more than 20 μs to lock the PLL.
Continuous min.4 NOP(R# = high) cycles are required after PLL lock up is done.
PLL Constraints
The PLL uses K clock as its synchronizing input and the input should have low phase jitter which is specified as
TKC var. The PLL can cover 120 MHz as the lowest frequency. If the input clock is unstable and the PLL is
enabled, then the PLL may lock onto an undesired clock frequency.
Power-On Waveforms
V
DD/VDDQ
V
DD/VDDQ Stable (< ±0.1 V DC per 50 ns)
Fix HIGH (or tied to VDDQ)
DLL#
Clock
20 μs or more
Stable Clock
Unstable Clock
Normal Operation
Start
4 Times NOP
R#
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 11 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Truth Table
Operation
CLK
R# W#
D or Q
WRITE cycle
L → H
H
L
Data in
Load address, input write data on
consecutive K and K# rising edge
READ cycle
Input data DA(A+0) DA(A+1) DA(A+2) DA(A+3)
Input clock K(t+1) ↑ K#(t+1) ↑ K(t+2) ↑ K#(t+2) ↑
L → H
L
×
Data out
Load address, read data on
consecutive C and C# rising edge
NOP (No operation)
Output data QA(A+0) QA(A+1) QA(A+2) QA(A+3)
Output clock C#(t+1) ↑ C(t+2) ↑ C#(t+2) ↑ C(t+3) ↑
L → H
H
H
D = ×, Q = High-Z
Previous state
Clock stop
Stopped
×
×
Remarks 1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges
except if C and C# are HIGH then data outputs are delivered at K and K# rising edges.
3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of
K. All control inputs are registered during the rising edge of K.
4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most
rapid restart by overcoming transmission line charging symmetrically.
7. If R# was LOW to initiate the previous cycle, this signal becomes a don't care for this WRITE operation
however it is strongly recommended that this signal is brought HIGH as shown in the truth table.
8. W# during write cycle and R# during read cycle were HIGH on previous K clock rising edge. Initiating
consecutive READ or WRITE operations on consecutive K clock rising edges is not permitted. The
device will ignore the second request.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 12 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Byte Write Operation
[μPD46185084B]
Operation
Write D0 to D7
K
L → H
−
L → H
−
L → H
−
L → H
−
K#
−
L → H
−
L → H
−
L → H
−
NW0#
NW1#
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Write D0 to D3
Write D4 to D7
Write nothing
L → H
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. NW0# and NW1# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
[μPD46185094B]
Operation
K
L → H
−
L → H
−
K#
−
L → H
−
BW0#
Write D0 to D8
0
0
1
1
Write nothing
L → H
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# can be altered for any portion of the BURST WRITE
operation provided that the setup and hold requirements are satisfied.
[μPD46185184B]
Operation
K
L → H
−
L → H
−
L → H
−
L → H
−
K#
−
L → H
−
L → H
−
L → H
−
BW0#
BW1#
Write D0 to D17
Write D0 to D8
Write D9 to D17
Write nothing
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
L → H
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 13 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
[μPD46185364B]
Operation
K
L → H
−
L → H
−
L → H
−
L → H
−
L → H
−
L → H
−
K#
BW0#
BW1#
BW2#
BW3#
Write D0 to D35
−
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
L → H
−
L → H
−
L → H
−
L → H
−
Write D0 to D8
Write D9 to D17
Write D18 to D26
Write D27 to D35
Write nothing
L → H
−
L → H
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# to BW3# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 14 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Bus Cycle State Diagram
LOAD NEW
READ ADDRESS;
R_Count = 0;
R_Init = 1
LOAD NEW
WRITE ADDRESS;
W_Count = 0
Always
W# = LOW & W_Count = 4
R# = LOW & R_Count = 4
Always
WRITE DOUBLE;
READ DOUBLE;
W_Count = W_Count+2
R_Count = R_Count+2
R# = HIGH
& R_Count = 4
W# = LOW
R_Init = 0
W_Count = 2
Always
R_Count = 2
Always
R# = LOW
W# = HIGH
& W_Count = 4
INCREMENT READ
ADDRESS BY TWO
R_Init = 0
INCREMENT WRITE
ADDRESS BY TWO
R# = HIGH
W# = HIGH
READ PORT NOP
R_Init = 0
WRITE PORT NOP
Power UP
Supply voltage
provided
Supply voltage
provided
Remarks 1. The address is concatenated with two additional internal LSBs to facilitate burst operation.
The address order is always fixed as: xxx...xxx+0, xxx...xxx+1, xxx...xxx+2, xxx...xxx+3.
Bus cycle is terminated at the end of this sequence (burst count = 4).
2. Read and write state machines can be active simultaneously.
Read and write cannot be simultaneously initiated. Read takes precedence.
3. State machine control timing is controlled by K.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 15 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Electrical Characteristics
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
Conditions
Rating
−0.5 to +2.5
Unit
V
VDD
Output supply voltage
Input voltage
VDD
Q
−0.5 to VDD
V
VIN
VI/O
TA
−0.5 to VDD+0.5 (2.5 V MAX.)
−0.5 to VDDQ+0.5 (2.5 V MAX.)
0 to 70
V
Input / Output voltage
Operating ambient temperature
V
(E** series)
°C
°C
°C
(E**Y series)
−40 to 85
Storage temperature
Tstg
−55 to +125
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to 70°C, TA = −40 to 85°C)
Parameter
Supply voltage
Symbol Conditions
MIN.
1.7
TYP.
MAX.
1.9
Unit Note
VDD
1.8
V
Output supply voltage
Input HIGH voltage
Input LOW voltage
Clock input voltage
Reference voltage
VDD
Q
1.4
VDD
V
V
V
V
V
1
VIH (DC)
VIL (DC)
VIN
VREF +0.1
−0.3
VDDQ+0.3
VREF −0.1
VDDQ+0.3
0.95
1, 2
1, 2
1, 2
−0.3
VREF
0.68
Notes 1. During normal operation, VDDQ must not exceed VDD
.
2. Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms
Recommended AC Operating Conditions (TA = 0 to 70°C, TA = −40 to 85°C)
Parameter
Input HIGH voltage
Input LOW voltage
Symbol Conditions
MIN.
MAX.
Unit Note
VIH (AC)
VIL (AC)
VREF +0.2
V
V
1
1
VREF −0.2
Note 1. Overshoot: VIH (AC) ≤ VDD + 0.7 V (2.5 V MAX.) for t ≤ TKHKH/2
Undershoot: VIL (AC) ≥ −0.5 V for t ≤ TKHKH/2
Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than
TKHKH (MIN.).
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 16 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
DC Characteristics 1 (TA = 0 to 70°C, VDD = 1.8 0.1 V)
Parameter
Symbol
Test condition
MIN.
MAX.
Unit Note
x8 x9 x18 x36
Input leakage current
I/O leakage current
ILI
−2
−2
+2
+2
μA
μA
ILO
IDD
Operating supply current
(Read cycle / Write cycle)
VIN ≤ VIL or VIN ≥ VIH,
-E33
-E40
-E33
-E40
520 520 580 740 mA
II/O = 0 mA, Cycle = MAX.
460 460 520 650
Standby supply current
(NOP)
ISB1
VIN ≤ VIL or VIN ≥ VIH,
II/O = 0 mA, Cycle = MAX.
Inputs static
390 390 400 430 mA
370 370 380 400
Output HIGH voltage
Output LOW voltage
VOH(Low)
VOH
|IOH| ≤ 0.1 mA
Note1
VDDQ − 0.2
VDDQ/2−0.12
VSS
VDDQ
VDDQ/2+0.12
0.2
V
V
V
V
3, 4
3, 4
3, 4
3, 4
VOL(Low)
VOL
IOL ≤ 0.1 mA
Note2
VDDQ/2−0.12
VDDQ/2+0.12
Notes 1. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) 15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
2. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) 15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
3. AC load current is higher than the shown DC values.
4. HSTL outputs meet JEDEC HSTL Class I standards.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 17 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
DC Characteristics 2 (TA = −40 to 85°C, VDD = 1.8 0.1 V)
Parameter
Symbol
Test condition
MIN.
MAX.
Unit Note
x8
x9 x18 x36
Input leakage current
I/O leakage current
ILI
−2
−2
+2
+2
μA
μA
ILO
IDD
Operating supply current
(Read cycle / Write cycle)
VIN ≤ VIL or VIN ≥ VIH,
-E33Y
-E40Y
-E33Y
-E40Y
640 640 710 870 mA
II/O = 0 mA, Cycle = MAX.
580 580 650 780
Standby supply current
(NOP)
ISB1
VIN ≤ VIL or VIN ≥ VIH,
II/O = 0 mA, Cycle = MAX.
Inputs static
510 510 520 550 mA
490 490 500 520
Output HIGH voltage
Output LOW voltage
VOH(Low) |IOH| ≤ 0.1 mA
VOH
VOL(Low) IOL ≤ 0.1 mA
VOL
VDDQ − 0.2
VDDQ/2−0.12
VSS
VDDQ
VDDQ/2+0.12
0.2
V
V
V
V
3, 4
3, 4
3, 4
3, 4
Note1
Note2
VDDQ/2−0.12
VDDQ/2+0.12
Notes 1. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) 15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
2. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) 15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
3. AC load current is higher than the shown DC values.
4. HSTL outputs meet JEDEC HSTL Class I standards.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 18 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Capacitance (TA = 25°C, f = 1 MHz)
Parameter
Symbol
CIN
Test conditions
MIN.
MAX.
Unit
pF
Input capacitance (Address, Control)
Input / Output capacitance
(D, Q, CQ, CQ#)
VIN = 0 V
5
7
CI/O
VI/O = 0 V
pF
Clock Input capacitance
Cclk
Vclk = 0 V
6
pF
Remark These parameters are periodically sampled and not 100% tested.
Thermal Characteristics
Parameter
Thermal resistance
Symbol
Substrate
4-layer
Airflow
0 m/s
1 m/s
0 m/s
1 m/s
0 m/s
1 m/s
0 m/s
1 m/s
TYP.
Unit
θ ja
16.5
13.2
15.5
12.6
0.07
0.13
0.06
0.12
3.86
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
from junction to ambient air
8-layer
4-layer
8-layer
Thermal characterization parameter
from junction to the top center
of the package surface
Ψ jt
θ jc
Thermal resistance
from junction to case
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 19 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
AC Characteristics (TA = 0 to 70°C, TA = −40 to 85°C, VDD = 1.8 0.1 V)
AC Test Conditions (VDD = 1.8 0.1 V, VDDQ = 1.4 V to VDD)
Input waveform (Rise / Fall time ≤ 0.3 ns)
1.25 V
0.75 V
0.75 V
Test Points
0.25 V
Output waveform
V
DDQ / 2
Test Points
VDDQ / 2
Output load condition
Figure 1. External load at test
V
DDQ / 2
0.75 V
50 Ω
V
REF
ZO = 50 Ω
SRAM
250 Ω
ZQ
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 20 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Read and Write Cycle
Parameter
Symbol
-E33, -E33Y
(300 MHz)
-E40, -E40Y
(250 MHz)
Unit
ns
Note
MIN.
MAX.
MIN.
MAX.
Clock
Average Clock cycle time
(K, K#, C, C#)
TKHKH
3.3
8.4
0.2
4.0
8.4
0.2
1
2
Clock phase jitter (K, K#, C, C#)
Clock HIGH time (K, K#, C, C#)
Clock LOW time (K, K#, C, C#)
Clock HIGH to Clock# HIGH
(K → K#, C → C#)
TKC var
TKHKL
TKLKH
ns
ns
ns
ns
1.32
1.32
1.49
1.6
1.6
1.8
TKHK#H
Clock# HIGH to Clock HIGH
(K# → K, C# → C)
Clock to data clock
TK#HKH
TKHCH
1.49
0
1.8
0
ns
ns
1.45
1.8
(K → C, K# → C#)
PLL lock time (K, C)
TKC lock
20
30
20
30
μs
ns
3
4
K static to PLL reset
TKC reset
Output Times
CQ HIGH to CQ# HIGH
(CQ → CQ#)
CQ# HIGH to CQ HIGH
TCQHCQ#H
TCQ#HCQH
1.24
1.24
1.55
1.55
ns
ns
5
5
(CQ# → CQ)
C, C# HIGH to output valid
C, C# HIGH to output hold
C, C# HIGH to echo clock valid
C, C# HIGH to echo clock hold
CQ, CQ# HIGH to output valid
CQ, CQ# HIGH to output hold
C HIGH to output High-Z
C HIGH to output Low-Z
TCHQV
TCHQX
0.45
0.45
0.27
0.45
0.45
0.45
0.3
ns
ns
ns
ns
ns
ns
ns
ns
–0.45
–0.45
–0.27
–0.45
–0.45
–0.45
–0.3
TCHCQV
TCHCQX
TCQHQV
TCQHQX
TCHQZ
6
6
0.45
TCHQX1
–0.45
Setup Times
Address valid to K rising edge
Control inputs (R#, W#) valid to
K rising edge
TAVKH
TIVKH
0.4
0.4
0.5
0.5
ns
ns
7
7
Data inputs and write data
select
TDVKH
0.3
0.35
ns
7
inputs (BWx#, NWx#) valid to
K, K# rising edge
Hold Times
K rising edge to address hold
K rising edge to control inputs
(R#, W#) hold
TKHAX
TKHIX
0.4
0.4
0.5
0.5
ns
ns
7
7
K, K# rising edge to data inputs
and write data select inputs
(BWx#, NWx#) hold
TKHDX
0.3
0.35
ns
7
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 21 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Notes 1. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH
(MAX.) without the PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.0 clock
cycle in this operation. The AC/DC characteristics cannot be guaranteed, however.
2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var
(MAX.) indicates a peak-to-peak value.
3. VDD slew rate must be less than 0.1 V DC per 50 ns for PLL lock retention.
PLL lock time begins once VDD and input clock are stable.
It is recommended that the device is kept NOP (R# = W# = HIGH) during these cycles.
4. K input is monitored for this operation. See below for the timing.
K
TKC reset
or
K
TKC reset
5. Guaranteed by design.
6. Echo clock is very tightly controlled to data valid / data hold. By design, there is a 0.1 ns variation from
echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
7. This is a synchronous device. All addresses, data and control lines must meet the specified setup
and hold times for all latching clock edges.
Remarks 1. This parameter is sampled.
2. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise
noted.
3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).
4. If C, C# are tied HIGH, K, K# become the references for C, C# timing parameters.
5. VDDQ is 1.5 V DC.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 22 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Read and Write Timing
WRITE
READ
NOP
WRITE
READ
NOP
1
2
3
4
5
6
7
K
TKHKL TKLKH
TKHKH
TKHK#H TK#HKH
K#
R#
TKHIX
TIVKH
TKHIX
TIVKH
W#
A0
A2
A1
A3
Address
Data in
TDVKH TKHDX
TDVKH
TKHDX
TAVKH TKHAX
D10
D11
D12
Q02
D13
Q03
D30
D31
Q21
D32
D33
Q23
Data out
Q20
Q22
Q00
Q01
Qx2
Qx3
TCQHQX
TCHQX1
TCHQX TCHQX
TCHQZ
TCQHQV
TCHQV TCHQV
CQ
TCHCQX
TCQHCQ#H TCQ#HCQH
TCHCQV
CQ#
TCHCQX
TCHCQV
TKHCH
C
TKHKL TKLKH
TKHKH
TKHK#H TK#HKH
TKHCH
C#
Remarks 1. Q00 refers to output from address A0+0.
Q01 refers to output from the next internal burst address following A0,i.e.,A0+1.
2. Outputs are disabled (high impedance) 3.5 clock cycles after the last READ (R# = LOW) is input in the
sequences of [READ]-[NOP]-[NOP], [READ]-[WRITE]-[NOP] and [READ]-[NOP]-[WRITE].
3. In this example, if address A2 = A1, data Q20 = D10, Q21 = D11, Q22 = D12 and Q23 = D13.
Write data is forwarded immediately as read results.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 23 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Application Example
R =
250 Ω
R =
250 Ω
ZQ
CQ#
CQ
Q
ZQ
CQ#
CQ
Q
SRAM#1
SRAM#4
. . .
D
A
D
A
R# W# BWx# C/C# K/K#
R# W# BWx# C/C# K/K#
V
t
SRAM
Controller
R
Data In
Vt
Data Out
Address
R#
R
Vt
R
W#
BW#
SRAM#1 CQ/CQ#
Vt
R
R
SRAM#4 CQ/CQ#
Vt
Source CLK/CLK#
Return CLK/CLK#
Vt
R
R = 50 Ω
Vt = Vref
Remark AC Characteristics are defined at the condition of SRAM outputs, CQ, CQ# and Q with termination.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 24 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Pin name
TCK
Pin assignments
Description
2R
Test Clock Input. All input are captured on the rising edge of TCK and all
outputs propagate from the falling edge of TCK.
TMS
TDI
10R
11R
Test Mode Select. This is the command input for the TAP controller state
machine.
Test Data Input. This is the input side of the serial registers placed between
TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP controller state machine and the instruction that is currently
loaded in the TAP instruction.
TDO
1R
Test Data Output. This is the output side of the serial registers placed between
TDI and TDO. Output changes in response to the falling edge of TCK.
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (TA = 0 to 70°C, VDD = 1.8 0.1 V, unless otherwise noted)
Parameter
Symbol
Conditions
MIN.
−5.0
−5.0
MAX.
+5.0
+5.0
Unit
μA
JTAG Input leakage current
JTAG I/O leakage current
ILI
0 V ≤ VIN ≤ VDD
0 V ≤ VIN ≤ VDDQ,
Outputs disabled
ILO
μA
JTAG input HIGH voltage
JTAG input LOW voltage
JTAG output HIGH voltage
VIH
VIL
1.3
−0.3
1.6
VDD+0.3
+0.5
V
V
V
V
V
V
VOH1
VOH2
VOL1
VOL2
| IOHC | = 100 μA
| IOHT | = 2 mA
1.4
JTAG output LOW voltage
I
OLC = 100 μA
0.2
0.4
IOLT = 2 mA
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 25 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
JTAG AC Test Conditions
Input waveform (Rise / Fall time ≤ 1 ns)
1.8 V
0.9 V
0.9 V
Test Points
0 V
Output waveform
0.9 V
Test Points
0.9 V
Output load
Figure 2. External load at test
V
TT = 0.9 V
50 Ω
ZO = 50 Ω
TDO
20 pF
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 26 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
JTAG AC Characteristics (TA = 0 to 70°C)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
tTHTH
fTF
tTHTL
tTLTH
50
ns
MHz
ns
20
20
20
ns
Output time
TCK LOW to TDO unknown
TCK LOW to TDO valid
tTLOX
tTLOV
0
ns
ns
10
Setup time
TMS setup time
TDI valid to TCK HIGH
Capture setup time
tMVTH
tDVTH
tCS
5
5
5
ns
ns
ns
Hold time
TMS hold time
tTHMX
tTHDX
tCH
5
5
5
ns
ns
ns
TCK HIGH to TDI invalid
Capture hold time
JTAG Timing Diagram
t
THTH
TCK
t
MVTH
t
THTL
t
TLTH
TMS
TDI
t
THMX
t
DVTH
t
THDX
t
TLOV
t
TLOX
TDO
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 27 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Scan Register Definition (1)
Register name
Description
Instruction register
The instruction register holds the instructions that are executed by the TAP controller
when it is moved into the run-test/idle or the various data register state. The register can
be loaded when it is placed between the TDI and TDO pins. The instruction register is
automatically preloaded with the IDCODE instruction at power-up whenever the controller
is placed in test-logic-reset state.
Bypass register
ID register
The bypass register is a single bit register that can be placed between TDI and TDO. It
allows serial test data to be passed through the RAMs TAP to another device in the scan
chain with as little delay as possible.
The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit
code when the controller is put in capture-DR state with the IDCODE command loaded in
the instruction register. The register is then placed between the TDI and TDO pins when
the controller is moved into shift-DR state.
Boundary register
The boundary register, under the control of the TAP controller, is loaded with the contents
of the RAMs I/O ring when the controller is in capture-DR state and then is placed
between the TDI and TDO pins when the controller is moved to shift-DR state. Several
TAP instructions can be used to activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary
register location. The first column defines the bit’s position in the boundary register. The
second column is the name of the input or I/O at the bump and the third column is the
bump number.
Scan Register Definition (2)
Register name
Instruction register
Bypass register
ID register
Bit size
Unit
bit
3
1
bit
32
107
bit
Boundary register
bit
ID Register Definition
ID [31:28] vendor
revision no.
ID [11:1] vendor
ID no.
Part number
Organization
2M x 8
ID [27:12] part no.
ID [0] fix bit
μPD46185084B
μPD46185094B
μPD46185184B
μPD46185364B
XXXX
XXXX
XXXX
XXXX
0000 0000 0000 1111
0000 0000 0101 0010
0000 0000 0001 0000
0000 0000 0001 0001
00000010000
00000010000
00000010000
00000010000
1
1
1
1
2M x 9
1M x 18
512K x 36
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 28 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
SCAN Exit Order
Bit
Signal name
Bump
ID
Bit
Signal name
Bump
ID
Bit
Signal name
Bump
ID
no.
x8
x9
x18
x36
no.
x8
x9
x18
x36
no.
x8
x9
x18
NC
x36
1
C#
C
A
6R
6P
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
NC
NC
NC
NC
NC
NC
Q3
D3
NC
NC
NC
NC
NC
NC
Q4
D4
NC
NC
Q7
D7
NC
NC
Q8
D8
NC
NC
D15
Q15
Q7
10D
9E
73 NC
NC
Q5
D5
Q28
2C
3E
2D
2E
1E
2F
3F
1G
1F
3G
2G
1J
2
74
75
Q4
D4
Q11 Q20
D11 D20
3
6N
10C
11D
9C
4
A
7P
D7
76 NC
77 NC
78 NC
79 NC
80 NC
81 NC
NC
NC
NC
NC
NC
NC
Q6
D6
NC
NC
NC
NC
NC
NC
Q7
D7
NC
NC
NC
NC
NC
NC
Q8
D8
NC
NC
NC
NC
D29
Q29
5
A
7N
D16
Q16
Q8
6
A
7R
9D
Q12 Q21
D12 D21
7
A
8R
11B
11C
9B
8
A
8P
D8
NC
NC
D30
Q30
9
A
9R
NC
NC
NC
NC
D17
Q17
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
NC
NC
NC
NC
NC
NC
NC
NC
Q0
D0
Q0
D0
NC
NC
NC
NC
NC
NC
Q1
D1
NC
NC
NC
NC
NC
NC
Q2
D2
Q0
D0
NC
NC
Q1
D1
NC
NC
Q2
D2
NC
NC
Q3
D3
NC
NC
Q4
D4
Q0
D0
11P
10P
10N
9P
10B
11A
Internal
82
83
Q5
D5
Q13 Q22
D13 D22
CQ
–
D9
84 NC
85 NC
86 NC
87 NC
88 NC
89 NC
NC
NC
D31
Q31
A
A
A
NC
Q9
9A
8B
7C
6C
8A
7A
7B
6B
6A
5B
5A
4A
5C
4B
3A
1H
1A
2B
3B
1C
1B
3D
3C
1D
2J
Q1
10M
11N
9M
A
A
Q14 Q23
D14 D23
3K
3J
D1
D10
Q10
Q2
NC
R#
NC
NC
D32
Q32
2K
1K
2L
9N
11L
11M
9L
NC
NC
NC BW1#
90
91
Q6
D6
Q15 Q24
D15 D24
D2
55 NW0# BW0# BW0# BW0#
3L
NC
NC
NC
NC
NC
NC
Q1
D1
D11
Q11
Q3
56
57
58
K
92 NC
93 NC
94 NC
95 NC
96 NC
97 NC
NC
NC
D33
Q33
1M
1L
10L
11K
10K
9J
K#
NC
NC
NC BW3#
Q16 Q25
D16 D25
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
D3
59 NW1# NC BW1# BW2#
D12
Q12
Q4
60
61
62
63
64
65
66
67
68
69
70
71
72
W#
A
NC
NC
D34
Q34
9K
10J
11J
11H
10G
9G
A
98
99
Q7
D7
Q17 Q26
D17 D26
D4
A
A
NC
NC
ZQ
DLL#
CQ#
100 NC
101 NC
102
NC
NC
D35
Q35
NC
NC
NC
NC
NC
NC
Q2
D2
NC
NC
NC
NC
NC
NC
Q3
D3
NC
NC
Q5
D5
NC
NC
Q6
D6
D13
Q13
Q5
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q9
D9
NC
NC
Q18
D18
D27
Q27
A
A
A
A
A
A
11F
11G
9F
103
D5
104
D14
Q14
Q6
105
10F
11E
10E
Q10 Q19
106
D10
NC
D19
D28
107
D6
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 29 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
JTAG Instructions
Instructions
EXTEST
Description
The EXTEST instruction allows circuitry external to the component package to be tested.
Boundary-scan register cells at output pins are used to apply test vectors, while those at
input pins capture test results. Typically, the first test vector to be applied using the
EXTEST instruction will be shifted into the boundary scan register using the PRELOAD
instruction. Thus, during the update-IR state of EXTEST, the output drive is turned on and
the PRELOAD data is driven onto the output pins.
IDCODE
BYPASS
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the
controller is in capture-DR mode and places the ID register between the TDI and TDO pins
in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up
and any time the controller is placed in the test-logic-reset state.
When the BYPASS instruction is loaded in the instruction register, the bypass register is
placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-
DR state. This allows the board level scan path to be shortened to facilitate testing of other
devices in the scan path.
SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the
SAMPLE / PRELOAD instruction is loaded in the instruction register, moving the TAP
controller into the capture-DR state loads the data in the RAMs input and Q pins into the
boundary scan register. Because the RAM clock(s) are independent from the TAP clock
(TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input
buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample
metastable input will not harm the device, repeatable results cannot be expected. RAM
input signals must be stabilized for long enough to meet the TAPs input data capture setup
plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other
TAP operation except capturing the I/O ring contents into the boundary scan register.
Moving the controller to shift-DR state then places the boundary scan register between the
TDI and TDO pins.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM Q pins are forced
to an inactive drive state (high impedance) and the boundary register is connected between
TDI and TDO when the TAP controller is moved to the shift-DR state.
JTAG Instruction Coding
IR2
0
IR1
0
IR0
0
Instruction
EXTEST
Note
0
0
1
IDCODE
0
1
0
SAMPLE-Z
1
2
0
1
1
RESERVED
SAMPLE / PRELOAD
RESERVED
RESERVED
BYPASS
1
0
0
1
0
1
2
2
1
1
0
1
1
1
Notes 1. TRISTATE all Q pins and CAPTURE the pad values into a SERIAL SCAN LATCH.
2. Do not use this instruction code because the vendor uses it to evaluate this product.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 30 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Output Pin States of CQ, CQ# and Q
Instructions
Control-Register Status
Output Pin Status
CQ,CQ#
Update
Update
SRAM
SRAM
High-Z
High-Z
SRAM
SRAM
SRAM
SRAM
Q
EXTEST
0
1
0
1
0
1
0
1
0
1
High-Z
Update
SRAM
SRAM
High-Z
High-Z
SRAM
SRAM
SRAM
SRAM
IDCODE
SAMPLE-Z
SAMPLE
BYPASS
Remark The output pin statuses during each instruction vary according
to the Control-Register status (value of Boundary Scan
Register, bit no. 48).
Boundary Scan
Register
CAPTURE
Register
There are three statuses:
Update : Contents of the “Update Register” are output to
the output pin (QDR Pad).
SRAM
Output
Update
Register
SRAM : Contents of the SRAM internal output “SRAM
Output” are output to the output pin (QDR Pad).
High-Z : The output pin (QDR Pad) becomes high
impedance by controlling of the “High-Z JTAG
ctrl”.
Update
QDR
Pad
SRAM
SRAM
Output
Driver
High-Z
The Control-Register status is set during Update-DR at the
EXTEST or SAMPLE instruction.
High-Z
JTAG ctrl
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 31 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Boundary Scan Register Status of Output Pins CQ, CQ# and Q
Instructions
SRAM Status
Boundary Scan Register Status
Note
CQ,CQ#
Pad
Pad
–
Q
Pad
Pad
–
EXTEST
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
IDCODE
SAMPLE-Z
SAMPLE
BYPASS
No definition
–
–
Pad
Pad
Internal
Internal
–
Pad
Pad
Internal
Pad
–
No definition
–
–
Remark The Boundary Scan Register statuses during execution each
instruction vary according to the instruction code and SRAM
operation mode.
Boundary Scan
Register
CAPTURE
Register
There are two statuses:
Internal
Pad
: Contents of the output pin (QDR Pad) are captured
in the “CAPTURE Register” in the Boundary Scan
Register.
SRAM
Output
Update
Register
Pad
Internal : Contents of the SRAM internal output “SRAM
Output” are captured in the “CAPTURE Register”
in the Boundary Scan Register.
QDR
Pad
SRAM
Output
Driver
High-Z
JTAG ctrl
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 32 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
TAP Controller State Diagram
1
0
Test-Logic-Reset
0
1
1
1
Run-Test / Idle
Select-DR-Scan
0
Select-IR-Scan
0
1
1
Capture-DR
0
Capture-IR
0
0
0
Shift-DR
1
Shift-IR
1
1
1
Exit1-DR
0
Exit1-IR
0
0
0
Pause-DR
1
Pause-IR
1
0
0
Exit2-DR
1
Exit2-IR
1
Update-DR
Update-IR
1
0
1
0
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with
normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS may be left open
but fix them to VDD via a resistor of about 1 kΩ when the TAP controller is not used. TDO should be left unconnected
also when the TAP controller is not used.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 33 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Run-Test/Idle
Update-IR
Exit1-IR
Shift-IR
Exit2-IR
Pause-IR
Exit1-IR
Shift-IR
Capture-IR
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Test-Logic-Reset
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 34 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Test-Logic-Reset
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Update-DR
Exit1-DR
Shift-DR
Exit2-DR
Pause-DR
Exit1-DR
Shift-DR
Capture-DR
Select-DR-Scan
Run-Test/Idle
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 35 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Package Dimensions
165-PIN PLASTIC BGA(13x15)
w
S
B
ZD
B
E
ZE
11
10
9
8
7
A
6
5
D
4
3
2
1
R P N M L K J H G F E D C B A
w
S A
INDEX MARK
A
(UNIT:mm)
ITEM DIMENSIONS
A2
y1
S
D
E
13.00±0.10
15.00±0.10
0.30
S
w
A
1.35±0.11
0.37±0.05
0.98
A1
A2
e
y
e
x
A1
S
S
1.00
M
b
A B
+0.10
−0.05
b
0.50
x
0.10
0.15
y
y1
ZD
ZE
0.25
1.50
0.50
T165F1-100-EQ1
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 36 of 38
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of these products.
Types of Surface Mount Devices
μPD46185084BF1-EQ1
μPD46185094BF1-EQ1
μPD46185184BF1-EQ1
μPD46185364BF1-EQ1
:
:
:
:
165-pin PLASTIC BGA (13 x 15)
165-pin PLASTIC BGA (13 x 15)
165-pin PLASTIC BGA (13 x 15)
165-pin PLASTIC BGA (13 x 15)
Quality Grade
• A quality grade of the products is “Standard”.
• Anti-radioactive design is not implemented in the products.
• Semiconductor devices have the possibility of unexpected defects by affection of cosmic ray that reach to
the ground and so forth.
R10DS0113EJ0200 Rev.2.00
Nov 09, 2012
Page 37 of 38
Revision History
μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B
Description
Summary
Rev.
Date
Page
-
Rev.1.00
Rev.2.00
’12.06.01
’12.11.09
New Data Sheet
Addition : -E33,-E33Y series, Lead series
Deletion : -E50,-E50Y series
ALL
All trademarks and registered trademarks are the property of their respective owners.
C - 38
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
be disclosed by Renesas Electronics such as that disclosed through our website.
2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
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others.
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4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and
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the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is
prohibited under any applicable domestic or foreign laws or regulations.
6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
7. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product
depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas
Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the
use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.
The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;
personal electronic equipment; and industrial robots.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically
designed for life support.
"Specific":
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical
implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or system manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-585-100, Fax: +44-1628-585-900
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632
Tel: +65-6213-0200, Fax: +65-6278-8001
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2012 Renesas Electronics Corporation. All rights reserved.
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