M38C81EF [RENESAS]
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER; 单片8位CMOS微机型号: | M38C81EF |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
文件: | 总55页 (文件大小:973K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ꢀLCD drive control circuit
DESCRIPTION
Bias ................................................................................... 1/5, 1/7
Duty .............................................................................. 1/16, 1/32
Common output ............................................................... 16 or 32
Segment output ............................................................... 52 or 68
ꢀMain clock generating circuit (RC oscillation selectable)
...................... (connect to external ceramic resonator or resistor)
ꢀSub-clock generating circuit
The 38C8 group is the 8-bit microcomputer based on the 740 family
core technology.
The 38C8 group has a LCD drive control circuit (bias control, time
sharing control), a 10-bit A-D converter, and a Serial I/O as additional
functions.
The various microcomputers in the 38C8 group include variations of
internal memory type and packaging. For details, refer to the section
on part numbering.
............................... (connect to external quartz-crystal oscilaltor)
ꢀPower source voltage
In high-speed mode .................................................... 4.0 to 5.5 V
In middle-speed mode ................................................ 2.2 to 5.5 V
In low-speed mode ..................................................... 2.2 to 5.5 V
ꢀPower dissipation
FEATURES
ꢀBasic machine-language instructions ....................................... 71
ꢀThe minimum instruction execution time ............................ 0.5 µs
(at 8 MHz oscillation frequency)
In high-speed mode ........................................................... 30 mW
(at 8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode .............................................................60 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage, at
WIT state, at voltage multiplier operating, LCD drive waveform
generating state)
ꢀMemory size
ROM ............................................................................ 60 K bytes
RAM ............................................................................ 2048 bytes
ꢀProgrammable input/output ports ............................................. 35
ꢀSoftware pull-up resistors
.................................................................. Ports P0–P3, P41–P47
ꢀInterrupts ................................................... 14 sources, 14 vectors
(includes key input interrupt)
ꢀOperating temperature range ................................... – 20 to 85°C
APPLICATIONS
Dot-matrix-type LCD displays
ꢀTimers ............................................................8-bit ꢀ 3, 16-bit ꢀ 2
ꢀSerial I/O ........................ 8-bit ꢀ 1 (UART or Clock-synchronized)
ꢀA-D converter (32 kHz operating available) ... 10-bit ꢀ 8 channels
1
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW)
109
72
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
COM13
COM12
COM11
COM10
110
71
111
70
112
69
113
68
COM
COM
9
114
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
8
115
P3
P3
P3
P3
0/AIN0
1/AIN1
2/AIN2
3/AIN3
116
117
118
119
NC
XIN
NC
120
121
122
V
SS
123
X
OUT
124
OSCSEL
125
V
CC
126
NC
M38C89MF-XXXFP
127
X
CIN
128
X
COUT
129
NC
RESET
130
131
P1
P1
P12
0
/AIN4
/AIN5
/AIN6
132
1
133
SEG
SEG
9
134
135
136
137
138
139
140
141
142
143
144
P1
P1
P1
P1
P1
3/AIN7
8
4
5
6
7
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
7
6
5
4
3
2
1
0
/COM23
/COM22
/COM21
/COM20
/COM19
/COM18
/COM17
/COM16
P0
P0
P0
P0
P0
P0
0
1
2
3
4
5
COM
COM
7
6
Package type : 144P6Q-A
Fig. 1 M38C89MF-XXXFP pin configuration
2
FUNCTIONAL BLOCK DIAGRAM (Package: 144P6Q-A)
Sub-clock
input
RC
Clock Clock oscillation
input output select
Sub-clock
output
Reset input
X
54
CIN
X
IN
X
OUT OSCSEL
VSS
59
X
COUT
RESET
51
V
56
CC
V
18
SS
58
57
53
61
6
5
4
3
2
COM
COM
COM
COM
COM
COM
COM
COM
0
1
2
3
4
5
6
7
Data bus
1
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
CPU
Clock generating circuit
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
0/COM16
RAM
1
2
3
4
5
6
7
8
9
/COM17
/COM18
/COM19
/COM20
/COM21
/COM22
/COM23
A
X
Y
S
ROM
LCD RAM
(240 byte)
LCD
controller
φ
Timer
PC
H
PC
PS
L
Timer X (16)
Timer Y (16)
SEG10
SEG11
SEG12
Timer 1 (8)
Timer 2 (8)
Timer 3 (8)
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60/COM31
SEG61/COM30
SEG62/COM29
SEG63/COM28
SEG64/COM27
SEG65/COM26
SEG66/COM25
SEG67/COM24
COM15
A-D converter (10)
Serial I/O (8)
COM14
P4 (7)
P0 (8)
P1 (8)
P2 (8)
P3 (4)
COM13
COM12
COM11
COM10
COM
COM
9
8
27 28 29 30 31 32 33 34
63 64
66
36
38 39 40 41 42
44 45 46 47 48 49 50
20 21 22 23 24 25 26
19
65
35
37
43
15
14
13
12
11
L1
10
L2
9
8
7
VL5
C3
VL3
VL4
C1
C2
V
V
V
LIN
I/O port P3
I/O port P0
I/O port P1
I/O port P2
I/O port P4
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1 Pin description
Pin
Name
Function
Function except a port function
• Apply voltage of 4.0–5.5 V to VCC, and 0 V to VSS. (at high-speed mode)
• Reset input pin for active “L.”
VCC, VSS
RESET
XIN
Power source
Reset input
Clock input
• Input and output pins for the main clock generating circuit.
• Feedback resistor is built in between XIN pin and XOUT pin.
• Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the
oscillation frequency.
XOUT
Clock output
• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• This pin determines the oscillation between XIN and XOUT. The oscillation method can be selected from
either by an oscillator or by a resistor.
OSCSEL
RC oscillation
select
• Input and output pins for sub-clock generating circuit. (Connect a quartz-crystal oscillator between the
XCIN and XCOUT pins to set the oscillation frequency. The clock generated the externals cannot be input
directly.)
XCIN
Sub-clock input
Sub-clock output
XCOUT
• Reference voltage input pin for LCD.
• The input voltage to this pin is boosted threefold by voltage multiplier.
VLIN
Power source
input for LCD
• LCD drive power source pins.
VL1 – VL5
LCD power
source
• LCD common output pins.
COM0 –
Common output
COM15
• LCD segment/common output pins.
SEG
0
/COM16
/COM23
–
,
Segment output/
Common output
SEG
7
SEG60COM31
–
SEG67/COM24
• LCD segment output pins.
• 8-bit I/O port.
SEG8–SEG59 Segment output
P00–P07
P14–P17
I/O port P0
I/O port P1
• CMOS compatible input level.
• CMOS 3-state output structure.
• A-D converter analog input pin
P10/AIN4–
P13/AIN7
• Key-on wake-up interrupt input pin
• A-D converter analog input pin
P20–P27
I/O port P2
I/O port P3
• 4-bit I/O port.
P30/AIN0 –
• CMOS compatible input level.
• CMOS 3-state output structure.
P33/AIN3
• 1-bit input port.
• External interrupt pin
P40/INT0
Input port P4
• CMOS compatible input level.
• 7-bit I/O port.
• External interrupt pin
• A-D trigger input pin
P41/INT1/ADT I/O port P4
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually
programmed as either input or output.
•Timer function I/O pin
P42/CNTR0/
BEEP+,
P43/CNTR1/
BEEP-
• Serial I/O I/O pin
P44/RxD,
P45/TxD,
P46/SCLK,
P47/SRDY
• External capacitor connect pins for a voltage multiplier of LCD.
C1,
C2,
C3
Voltage multiplier
• Non-function pins.
VSS (NC), NC
• Leave the VSS (NC) pin open.
4
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product
M38C8
9
M
F
–XXX FP
Package type
FP: 144P6Q-A package
ROM number
Omitted in One Time PROM version.
ROM/PROM size
1: 4096 bytes
2: 8192 bytes
3: 12288 bytes
4: 16384 bytes
5: 20480 bytes
6: 24576 bytes
7: 28672 bytes
8: 32768 bytes
9: 36864 bytes
A: 40960 bytes
B: 45056 bytes
C: 49152 bytes
D: 53248 bytes
E: 57344 bytes
F: 61440 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas; they cannot be used.
Memory type
M: Mask ROM version
E: One Time PROM version
RAM size
0: 192 bytes
1: 256 bytes
2: 384 bytes
3: 512 bytes
4: 640 bytes
5: 768 bytes
6: 896 bytes
7: 1024 bytes
8: 1536 bytes
9: 2048 bytes
Fig. 3 Part numbering
5
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Mitsubishi plans to expand the 38C8 group as follows.
Packages
144P6Q-A ................................... 0.5 mm-pitch plastic molded QFP
Memory Type
Support for mask ROM and One Time PROM versions
Memory Size
ROM/PROM size ............................................................ 60 K bytes
RAM size........................................................................ 2048 bytes
Memory Expansion Plan
ROM size (bytes)
M38C89MF/EF
60K
56K
48K
40K
32K
28K
24K
20K
16K
12K
8K
4K
1,024
1,536
2,048
192 256
384
512
640
768
896
RAM size (bytes)
Fig. 4 Memory expansion plan
Currently products are listed below.
Table 2 List of products
(P) ROM size (bytes)
ROM size for User in ( )
RAM size
(bytes)
Remarks
Product name
Package
M38C89MF-XXXFP
M38C89EFFP
61440 (61310)
61440 (61310)
2048
2048
144P6Q-A
144P6Q-A
Mask ROM version
One Time PROM version
6
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Stack Pointer (S)]
FUNCTIONAL DESCRIPTION
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the con-
tents of the stack pointer. The high-order 8 bits of the stack address
are determined by the stack page selection bit. If the stack page
selection bit is “0” , the high-order 8 bits becomes “0016”. If the stack
page selection bit is “1”, the high-order 8 bits becomes “0116”.
The operations of pushing register contents onto the stack and pop-
ping them from the stack are shown in Figure 6.
CENTRAL PROCESSING UNIT (CPU)
The 38C8 group uses the standard 740 family instruction set. Refer
to the table of 740 family addressing modes and machine instruc-
tions or the 740 Family Software Manual for details on the instruction
set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
Store registers other than those described in Figure 6 with program
when the user needs them during interrupts or subroutine calls.
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
[Program Counter (PC)]
The index register X is an 8-bit register. In the index addressing modes,
the value of the OPERAND is added to the contents of register X and
specifies the real address.
The program counter is a 16-bit counter consisting of two 8-bit regis-
ters PCH and PCL. It is used to indicate the address of the next in-
struction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b7
X
Index register X
b7
b0
Y
Index register Y
b7
b0
S
Stack pointer
b15
b7
b7
b0
PCH
PCL
Program counter
b0
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 5 740 Family CPU register structure
7
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
On-going Routine
Execute JSR
Interrupt request
(Note)
M (S) (PCH)
(S) (S) – 1
Push return address
on stack
M (S) (PCH)
(S) (S) – 1
M (S) (PCL)
(S) (S)– 1
Subroutine
M (S) (PCL)
(S) (S) – 1
Push return address
on stack
Push contents of processor
status register on stack
M (S) (PS)
(S) (S) – 1
Interrupt
Service Routine
I Flag is set from “0” to “1”
Execute RTS
(S) (S) + 1
Fetch the jump vector
Execute RTI
(S) (S) + 1
POP return
address from stack
POP contents of
processor status
register from stack
(PCL) M (S)
(S) (S) + 1
(PCH) M (S)
(PS)
M (S)
(S) (S) + 1
(PCL) M (S)
(S) (S) + 1
(PCH) M (S)
POP return
address
from stack
Note: Condition for acceptance of an interrupt
Interrupt disable flag is “0” and
Interrupt enable bit corresponding to
each interrupt is “1”
Fig. 6 Register push and pop at interrupt generation and subroutine call
Table 3 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PHP
PLA
PLP
Processor status register
8
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
•Bit 4: Break flag (B)
[Processor status register (PS)]
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
The processor status register is an 8-bit register consisting of 5 flags
which indicate the status of the processor after an arithmetic opera-
tion and 3 flags which decide MCU operation. Branch operations can
be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow
(V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags
are not valid.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
Table 4 Set and clear instructions of each bit of processor status register
N flag
C flag
SEC
CLC
Z flag
I flag
SEI
D flag
SED
CLD
B flag
T flag
SET
CLT
V flag
–
–
–
–
–
–
–
Set instruction
CLI
CLV
Clear instruction
9
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and the
internal system clock selection bit.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM (CM) : address 003B16
)
Processor mode bits
b1 b0
0
0
1
1
0 : Single-chip mode
1 :
0 :
1 :
Not available
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (returns “1” when read)
(Do not write “0” to this bit)
Sub-clock (XCIN–XCOUT) oscillating bit
0 : Stopped
1 : Oscillating
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
0 : f(XIN)/2 (high-speed mode)
1 : f(XIN)/8 (middle-speed mode)
Internal system clock selection bit
0 : XIN–XOUT selected (middle-/high-speed mode)
1 : XCIN–XCOUT selected (low-speed mode)
Fig. 7 Structure of CPU mode register
10
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY
Zero Page
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains control
registers such as I/O ports and timers.
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
Special Page
RAM
Access to this area with only 2 bytes is possible in the special page
RAM is used for data storage and for stack area of subroutine calls
addressing mode.
and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
000016
Address
XXXX16
RAM size
(bytes)
SFR area
004016
192
256
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
Zero page
ꢀ
LCD display RAM area
384
RAM
013016
512
640
XXXX16
034016
768
896
1024
1536
2048
ꢀ
LCD display RAM area
043016
ROM area
084016
Address
YYYY16
Address
ZZZZ16
ROM size
(bytes)
Not used
4096
8192
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
YYYY16
Reserved ROM area
(128 bytes)
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
ZZZZ16
ROM
FF0016
FFDC16
Special page
Interrupt vector area
FFFE16
Reserved ROM area
FFFF16
ꢀ The start address of the LCD display area can be switched either zero page (addresses 004016–012F16) or 3 page (addresses
034016–042F16) by software. Immediately after reset released, 3 page is selected.
Fig. 8 Memory map diagram
11
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016
000116
000216
000316
000416
000516
000616
000716
Port P0 (P0)
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Timer X (low-order) (TXL)
Timer X (high-order) (TXH)
Port P0 direction register (P0D)
Port P1 (P1)
Timer Y (low-order) (TYL)
Timer Y (high-order) (TYH)
Port P1 direction register (P1D)
Port P2 (P2)
Timer 1 (T1)
Timer 2 (T2)
Port P2 direction register (P2D)
Port P3 (P3)
Timer 3 (T3)
Port P3 direction register (P3D)
Timer X mode register (TXM)
Timer Y mode register (TYM)
Timer 123 mode register (T123M)
000816 Port P4 (P4)
000916 Port P4 direction register (P4D)
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
A-D control register (ADCON)
A-D conversion register (low-order) (ADL)
A-D conversion register (high-order) (ADH)
PULL register A (PULLA)
PULL register B (PULLB)
001616
001716
001816
001916
LCD control register 1 (LC1)
LCD control register 2 (LC2)
Transmit/Receive buffer register (TB/RB)
Serial I/O status register (SIOSTS)
LCD mode register (LM)
16 Serial I/O control register (SIOCON)
001A
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
001B16
001C16
001D16
001E16
001F16
UART control register (UARTCON)
Baud rate generator (BRG)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Fig. 9 Memory map of special function register (SFR)
12
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
[Direction Registers]
b7
b0
PULL register A
(PULLA: address 001616
)
The I/O ports P0–P3 and P41–P47 have direction registers which
determine the input/output direction of each individual pin. Each bit
in a direction register corresponds to one pin, each pin can be set to
be input port or output port.
P00
P04
P10
P14
P20
P24
P30
–P0
–P0
–P1
–P1
–P2
–P2
–P3
3
7
3
7
3
7
3
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin becomes
an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are float-
ing. If a pin set to input is written to, only the port output latch is
written to and the pin remains floating.
Not used (return “0” when read)
b7
b0
PULL register B
(PULLB: address 001716
)
Not used (return “0” when read)
P41
P42
P43
P44
P45
P46
P47
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
Pull-up Control
By setting the PULL register A (address 001616) or the PULL register
B (address 001716), ports P0 to P4 except for port P40 can control
pull-up with a program.
However, the contents of PULL register A and PULL register B do not
affect ports programmed as the output ports.
0: No pull-up
1: Pull-up
Note: The contents of PULL register A and PULL register B do
not affect ports programmed as the output port.
Fig. 10 Structure of PULL register A and PULL register B
13
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 5 List of I/O port function
Name
Port P0
Input/Output
I/O format
Non-port function
Related SFRs
PULL register A
Ref. No.
(1)
Pin
Input/Output,
individual bits
CMOS compatible input
level
CMOS 3-state output
P00–P07
Port P1
A-D converter input PULL register A
A-D control register
(2)
P10/AIN4–
P13/AIN7
PULL register A
(1)
(1)
P14–P17
P20–P27
Port P2
Port P3
Input/Output,
individual bits
CMOS compatible input Key input (key-on PULL register A
level
wake-up) interrupt in- Interrupt control register 2
put
CMOS 3-state output
Input/Output,
individual bits
CMOS compatible input A-D converter input
level
CMOS 3-state output
PULL register A
A-D control register
(2)
(3)
P30/AIN0–
P33/AIN3
Port P4
Input
CMOS compatible input External interrupt in- PULL register B
P40/INT0
level
put
Interrupt edge select
register
Input/Output,
individual bits
CMOS compatible input
level
CMOS 3-state output
(1)
(4)
P41/INT1/ADT
Timer X function I/O
PULL register B
Timer X mode register
P42/CNTR0/
BEEP+
Timer Y function I/O PULL register B
Timer Y mode register
PULL register B
(5)
P43/CNTR1/
BEEP-
Serial I/O funtion
I/O
(6)
(7)
(8)
(9)
P44/RxD
P45/TxD
P46/SCLK
P47/SRDY
Serial I/O control register
Serial I/O status register
UART control register
LCD mode register
Common
Output
LCD common output
COM
COM
0
–COM
7,
8
–COM15
Segment/
Common
LCD segment output
LCD common ouput
SEG
0
/COM16
–
,
SEG
7
/COM23
SEG60/COM31
–
SEG67/COM24
Segment
LCD segment output
SEG8–SEG59
14
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Ports P10–P13, P3
(1) Ports P0, P14–P17, P2, P41
Pull-up control
Pull-up control
Direction
register
Direction
register
Port latch
Data bus
Port latch
Data bus
A-D converter input
Key-on wake-up interrupt input
Analog input pin selection bit
INT
1
interrupt input, ADT
Except P0, P14–P17
(3) Port P4
0
Data bus
0 interrupt input
INT
(4) Port P4
2
(5) Port P43
Pull-up control
Pull-up control
Direction
register
Direction
register
Port latch
Port latch
Data bus
Data bus
Buzzer output mode
Timer output
Buzzer output mode
Timer output
CNTR
0
interrupt input
CNTR1 interrupt input
Fig. 11 Port block diagram (1)
15
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(6) Port P4
4
(7) Port P4
5
Pull-up control
Serial I/O enable bit
Receive enalble bit
Pull-up control
P45
/TxD P-channel output disable bit
Serial I/O enable bit
Transmit enable bit
Direction
Direction
register
register
Port latch
Data bus
Databus
Port latch
Serial I/O input
Serial I/O output
(8) Port P4
6
(9) Port P47
Serial I/O synchronous
clock selection bit
Serial I/O enable bit
Pull-up control
Pull-up control
Serial I/O mode selection bit
Serial I/O enable bit
Serial I/O mode selection bit
Serial I/O enable bit
Direction
S
RDY output enable bit
Direction
register
register
Data bus
Port latch
Data bus
Port latch
Serial I/O ready output
Serial I/O clock output
Serial I/O clock input
Fig. 12 Port block diagram (2)
16
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts occur by fourteen sources: five external, eight internal, and
Interrupt Operation
By acceptance of an interrupt, the following operations are automati-
one software.
cally performed:
1. The contents of the program counter and processor status reg-
ister are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
Interrupt Control
Each interrupt except the BRK instruction interrupt have both an in-
terrupt request bit and an interrupt enable bit, and is controlled by the
interrupt disable flag. An interrupt occurs if the corresponding inter-
rupt request and enable bits are “1” and the interrupt disable flag is
“0”.
3. The interrupt jump destination address is read from the vector
table into the program counter.
Interrupt enable bits can be set or cleared by software. Interrupt re-
quest bits can be cleared by software, but cannot be set by software.
The BRK instruction interrupt and reset cannot be disabled with any
flag or bit. The I flag disables all interrupts except the BRK instruction
interrupt and reset. If several interrupts requests occurs at the same
time the interrupt with highest priority is accepted first.
ꢀNotes on interrupts
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
Timer X mode register (address 2716)
Timer Y mode register (address 2816)
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: A-D control regsiter (address 3116)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
ꢀSet the corresponding interrupt enable bit to “0” (disabled).
ꢀSet the interrupt edge select bit (active edge switch bit) or the inter-
rupt source select bit to “1”.
ꢀSet the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
ꢀSet the corresponding interrupt enable bit to “1” (enabled).
Table 6 Interrupt vector addresses and priority
Vector Addresses (Note 1)
Interrupt Request
Remarks
Interrupt Source Priority
Generating Conditions
High
Low
Reset (Note 2)
1
2
FFFD16
FFFB16
FFFC16
FFFA16
At reset
Non-maskable
INT0
At detection of either rising or falling edge of External interrupt
INT0 intput
(active edge selectable)
INT1
3
4
5
FFF916
FFF716
FFF516
FFF816
FFF616
FFF416
At detection of either rising or falling edge of External interrupt
INT1 input
(active edge selectable)
Serial I/O
reception
At completion of serial I/O data reception Valid when serial I/O is selected
Serial I/O
transmission
At completion of serial I/O transmission shift Valid when serial I/O is selected
or when transmission buffer is empty
Timer X
Timer Y
Timer 2
Timer 3
CNTR0
6
7
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFF216
FFF016
FFEE16
FFEC16
FFEA16
At timer X underflow
At timer Y underflow
8
At timer 2 underflow
9
At timer 3 underflow
10
At detection of either rising or falling edge of External interrupt
CNTR0 input
(active edge selectable)
CNTR1
Timer 1
11
FFE916
FFE816
At detection of either rising or falling edge of External interrupt
CNTR1 input
(active edge selectable)
12
13
FFE716
FFE116
FFE616
FFE016
At timer 1 underflow
Key input (Key-
on wake-up)
At falling of port P2 (at input) input logical level External interrupt
AND
(falling valid)
A-D conversion
14
15
FFDF16
FFDD16
FFDE16
FFDC16
At completion of A-D conversion
Valid when A-D conversion interrupt
is selected
BRK instruction
At BRK instruction execution
Non-maskable software interrupt
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
17
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
Interrupt request
BRK instruction
Reset
Fig. 13 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16
)
INT
INT
0
1
interrupt edge selection bit
interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
Not used (return “0” when read)
b7
b0
b7
b0
Interrupt request register 2
Interrupt request register 1
(IREQ2 : address 003D16
)
(IREQ1 : address 003C16
)
INT
INT
0
1
interrupt request bit
interrupt request bit
CNTR
CNTR
0
1
interrupt request bit
interrupt request bit
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 2 interrupt request bit
Timer 1 interrupt request bit
Not used (returns “0” when read)
Key input interrupt request bit
A-D conversion interrupt request bit
Not used (returns “0” when read)
Timer 3 interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b7
b0
Interrupt control register 2
Interrupt control register 1
(ICON2 : address 003F16
)
(ICON1 : address 003E16
)
CNTR
CNTR
0
1
interrupt enable bit
interrupt enable bit
INT
INT
0
1
interrupt enable bit
interrupt enable bit
Timer 1 interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
Timer X interrupt enable bit
Key input interrupt enable bit
A-D conversion interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
Timer Y interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 14 Structure of interrupt-related registers
18
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
of using a key input interrupt is shown in Figure 15, where an inter-
rupt request is generated by pressing one of the keys consisted as
an active-low key matrix which inputs to ports P20–P23.
Key Input Interrupt (Key-on Wake-Up)
A key input interrupt request is generated by applying “L” level to any
pin of port P2 that have been set to input mode. In other words, it is
generated when AND of input level goes from “1” to “0”. An example
Port PXx
“L” level output
PULL register A
Bit 5 = “1”
Key input interrupt request
Port P27 direction
register = “1”
ꢀ
ꢀ
ꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀꢀ
Port P2
latch
7
P2
P2
P2
7
output
output
Port P2
6 direction
register = “1”
Port P2
latch
6
6
Port P2
5 direction
register = “1”
ꢀ
ꢀ
Port P2
latch
5
5
output
output
Port P2
4 direction
register = “1”
Port P2
latch
4
P2
4
PULL register A
Bit 4 = “1”
Port P23 direction
register = “0”
Port P2
Input reading circuit
ꢀ
ꢀ
ꢀꢀ
Port P2
latch
3
P2
3
input
input
input
input
Port P2
2 direction
register = “0”
ꢀꢀ
Port P2
latch
2
P2
P2
2
Port P2
1 direction
register = “0”
ꢀ
ꢀꢀ
ꢀꢀ
Port P2
latch
1
1
Port P2
0 direction
register = “0”
ꢀ
Port P2
latch
0
P2
0
ꢀ
ꢀ
P-channel transistor for pull-up
ꢀꢀ CMOS output buffer
Fig. 15 Connection example when using key input interrupt and port P2 block diagram
19
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
is set to “1”.
TIMERS
Read and write operation on 16-bit timer must be performed for both
high and low-order bytes. When reading a 16-bit timer, read the high-
order byte first. When writing to a 16-bit timer, write the low-order
byte first. The 16-bit timer cannot perform the correct operation when
reading during the write operation, or when writing during the read
operation.
The 38C8 group has five timers: timer X, timer Y, timer 1, timer 2, and
timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2,
and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0016”, an
underflow occurs at the next count pulse and the corresponding timer
latch is reloaded into the timer and the count is continued. When a
timer underflows, the interrupt request bit corresponding to that timer
Data bus
f(XIN)/16
(f(XCIN)/16 in low-speed mode✽)
f(XIN
)
Timer X count source
selection bit
“1”
“00”,“11”
Timer X write control bit
f(XCIN
)
Timer X stop control bit
“0”
0 active
edge switch bit
“01”
Timer X operating
mode bits
Timer X operating
mode bits
CNTR
Timer X (low) latch (8) Timer X (high) latch (8)
“00”,“01”,“11”
Timer X interrupt
request
“0”
P42/CNTR0/BEEP+
Timer X (low) (8)
Timer X (high) (8)
“10”
“1”
Pulse width
measurement
mode
CNTR
request
0
interrupt
CNTR
edge switch bit
0
active
Buzzer output mode
“0”
“1”
S
Q
Q
Timer Y operating mode bits
T
P4
2
direction register
“00”,“01”,“10”
CNTR
1
interrupt
Pulse width HL continuously
measurement mode
P4
2 latch
request
“11”
Rising edge detection
Buzzer output mode
Period measure-
ment mode
Falling edge detection
(f(XCIN)/16 in low-speed mode✽)
f(XIN)/16
Timer Y stop
control bit
CNTR
1 active
edge switch bit
Timer Y (low) latch (8)
Timer Y (low) (8)
Timer Y (low) high (8)
Timer Y (high) (8)
“00”,“01”,“11”
Timer Y interrupt
request
“0”
“1”
P43/CNTR1/BEEP-
Timer Y operating
“10”
mode bits
P43 direction register
P4
3 latch
BEEP- valid bit
f(XIN)/16
(f(XCIN)/16 in low-speed mode✽)
Timer 1 interrupt
request
Timer 2 write control bit
Timer 2 latch (8)
Timer 2 (8)
Timer 2 count source
selection bit
Timer 1 count source
selection bit
“0”
Timer 1 latch (8)
Timer 1 (8)
“0”
Timer 2 interrupt
request
f(XCIN)/32
“1”
“1”
f(XIN)/16
(f(XCIN)/16 in low-speed mode✽)
Timer 3 latch (8)
“0”
Timer 3 interrupt
request
Timer 3 (8)
f(XCIN)/32
“1”
Timer 3 count source
selection bit
✽ Internal clock φ = XCIN divided by 2 in low-speed mode
Fig. 16 Timer block diagram
20
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer X
Timer X is a 16-bit timer that can be selected in one of four modes
and can be controlled the timer X write by setting the timer X mode
register.
b7
b0
Timer X mode register
(TXM : address 002716)
Timer X write control bit
0 : Write value in latch and counter
1 : Write value in latch only
BEEP- valid bit
0 : Invalid
1 : Valid
(1) Timer Mode
When the timer X count source selection bit is “0”, the timer counts
f(XIN)/16 (or f(XCIN)/16 in low-speed mode). When it is “1”, the timer
counts f(XIN).
Not used
Timer X operating mode bits
b5 b4
(2) Buzzer Output Mode
When the timer X count source selection bit is “0”, the timer counts
0
0
1
1
0 : Timer mode
1 : Buzzer output mode
0 : Event counter mode
1 : Pulse width measurement mode
f(XCIN). When it is “1”, the timer counts f(XIN).
Each time the timer underflows, a signal output from the BEEP+ pin
is inverted. When the BEEP- valid bit is “1”, the opposite phase of
BEEP+ signal is output from the BEEP- pin. When using the BEEP+
pin and the BEEP- pin, set ports shared with these pins to output.
CNTR0 active edge switch bit
0 : Count at rising edge in event counter mode
Start from “H” output in buzzer output mode
Measure “H” pulse width in pulse width
measurement mode
Falling edge active for interrupt
1 : Count at falling edge in event counter mode
Start from “L” output in buzzer output mode
Measure “L” pulse width in pulse width
measurement mode
Rising edge active for interrupt
Timer X stop control bit
0 : Count start
(3) Event Counter Mode
The timer counts signals input through the CNTR0 pin.
Except for this, the operation in event counter mode is the same as
in timer mode. When using a timer in this mode, set the port shared
with the CNTR0 pin to input.
1 : Count stop
(4) Pulse Width Measurement Mode
When the timer X count source selection bit is “0”, the count source
is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). When it is “1”, the
count source is f(XIN).
Fig. 17 Structure of timer X mode register
If CNTR0 active edge switch bit is “0”, the timer counts while the
input signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while
the input signal of CNTR0 pin is at “L”. When using a timer in this
mode, set the port shared with the CNTR0 pin to input.
●Timer X write control
If the timer X write control bit is “0”, when the value is written in the
address of timer X, the value is loaded in the timer X and the latch
at the same time.
If the timer X write control bit is “1”, when the value is written in the
address of timer X, the value is loaded only in the latch. The value
in the latch is loaded in timer X after timer X underflows.
If the value is written in latch only, unexpected value may be set in
the high-order counter when the writing in high-order latch and the
underflow of timer X are performed at the same timing.
●Notes on CNTR0 interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
21
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer Y
b7
b0
Timer Y is a 16-bit timer that can be selected in one of four modes.
Timer Y mode register
(TYM : address 002816
)
Timer X count source selection bit
(1) Timer Mode
0 : f(XIN)/16 (f(XCIN)/16 in low-speed mode✽)
1 : f(XIN
)
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
Not used (return “0” when read)
Timer Y operating mode bits
b5 b4
(2) Period Measurement Mode
0
0
1
1
0 : Timer mode
CNTR1 interrupt request is generated at rising/falling edge of CNTR1
pin input signal. Simultaneously, the value in timer Y latch is reloaded
in timer Y and timer Y continues counting down. Except for the above-
mentioned, the operation in period measurement mode is the same
as in timer mode.
1 : Period measurement mode
0 : Event counter mode
1 : Pulse width HL continuously
measurement mode
CNTR1 active edge switch bit
0 : Count at rising edge in event counter mode
Measure the falling edge to falling edge
period in period measurement mode
Interrupt falling edge active
1 : Count at falling edge in event counter mode
Measure the rising edge period in period
measurement mode
Interrupt rising edge active
Timer Y stop control bit
0 : Count start
1 : Count stop
The timer value just before the reloading at rising/falling of CNTR1
pin input signal is retained until the timer Y is read once after the
reload.
The rising/falling timing of CNTR1 pin input signal is found by CNTR1
interrupt. When using a timer in this mode, set the port shared with
the CNTR1 pin to input.
✽ Internal clock φ in low-speed mode is XCIN divided by 2.
When the timer X operating mode bits are “00” or “11”, the timer X count source is
f(XCIN)/16. When the timer X operating mode bits are “01”, the timer X count source
is f(XCIN).
(3) Event Counter Mode
The timer counts signals input through the CNTR1 pin.
Except for this, the operation in event counter mode is the same as
in timer mode. When using a timer in this mode, set the port shared
with the CNTR1 pin to input.
Fig. 18 Structure of timer Y mode register
(4) Pulse Width HL Continuously Measurement
Mode
CNTR1 interrupt request is generated at both rising and falling edges
of CNTR1 pin input signal. Except for this, the operation in pulse
width HL continuously measurement mode is the same as in period
measurement mode. When using a timer in this mode, set the port
shared with the CNTR1 pin to input.
✽Notes on CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit. However, in the pulse width HL continuously measure-
ment mode, CNTR1 interrupt request is generated at both rising and
falling edges of CNTR1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
22
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for
each timer can be selected by the timer 123 mode register. The timer
latch value is not affected by a change of the count source. However,
because changing the count source may cause an inadvertent count
down of the timer. Therefore, rewrite the value of timer whenever the
count source is changed.
b7
b0
Timer 123 mode register
(T123M :address 002916
)
Not used
Timer 2 write control bit
0 : Write data in latch and counter
1 : Write data in latch only
✽Timer 2 write control
Timer 2 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16
If the timer 2 write control bit is “0”, when the value is written in the
address of timer 2, the value is loaded in the timer 2 and the latch at
the same time.
(or f(XCIN)/16 in low-speed mode*)
Timer 3 count source selection bit
0 : Timer 1 output
1 : f(XCIN)/32
If the timer 2 write control bit is “1”, when the value is written in the
address of timer 2, the value is loaded only in the latch. The value in
the latch is loaded in timer 2 after timer 2 underflows.
Timer 1 count source selection bit
0 : f(XIN)/16
✽Notes on timer 1 to timer 3
(or f(XCIN)/16 in low-speed mode*)
1 : f(XCIN)/32
When the count source of timer 1 to 3 is changed, the timer counting
value may be changed large because a thin pulse is generated in
count input of timer. If timer 1 output is selected as the count source
of timer 2 or timer 3, when timer 1 is written, the counting value of
timer 2 or timer 3 may be changed large because a thin pulse is
generated in timer 1 output.
Not used (return “0” when read)
* Internal clock φ is XCIN/2 in the low-speed mode.
Therefore, set the value of timer in the order of timer 1, timer 2 and
timer 3 after the count source selection of timer 1 to 3.
Fig. 19 Structure of timer 123 mode register
23
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O can be selected by setting the mode
selection bit of the serial I/O control register to “1”.
SERIAL I/O
Serial I/O can be used as either clock synchronous or asynchronous
(UART) serial I/O. A dedicated timer (baud rate generator) is also
provided for baud rate generation.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is started
by a write signal to the transmit/receive buffer registers.
Data bus
Address 001A16
Receive buffer full flag (RBF)
Serial I/O control register
Address 001816
Receive buffer register
Receive interrupt request (RI)
Receive shift register
P44/RXD
Shift clock
Clock control circuit
P46/SCLK
Serial I/O
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
f(XIN
)
Baud rate generator
Address 001C16
1/4
(f(XCIN) in low-speed mode)
1/4
Clock control circuit
P47/SRDY
Falling-edge detector
F/F
Transmit shift register shift completion flag (TSC)
Shift clock
Transmit interrupt source selection bit
P45/TXD
Transmit shift register
Transmit buffer register
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Address 001916
Serial I/O status register
Address 001816
Data bus
Fig. 20 Block diagram of clock synchronous serial I/O
Transmit/receive shift clock
(1/2 to 1/2048 of internal clock,
or an external clock)
Serial output TXD
D
0
0
D
1
1
D
2
D
3
3
D
4
4
D
5
5
D
6
6
D
7
7
Serial input RXD
D
D
D
D
D
D
D
D
2
Receive enable signal SRDY
Write signal to receive/transmit
buffer register (address 001816
)
RBF = 1
TSC = 1
Overrun error (OE)
detection
TBE = 0
TBE = 1
TSC = 0
Notes 1: The transmit interrupt (TI) can be selected to occur either when the transmit buffer register has emptied (TBE=1) or after
the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial
I/O control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the T
XD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 21 Operation of clock synchronous serial I/O function
24
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
but the two buffers have the same address in memory. Since the shift
register cannot be written to or read from directly, transmit data is
written to the transmit buffer, and receive data is read from the re-
ceive buffer.
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by clear-
ing the serial I/O mode selection bit of the serial I/O control register
to “0”.
The transmit buffer can also hold the next data to be transmitted, and
the receive buffer register can hold a character while the next char-
acter is being received.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer register,
Data bus
Address 001816
Serial I/O control register
Address 001A16
Receive buffer register
OE
Receive buffer full flag (RBF)
Receive interrupt request (RI)
1/16
Character length selection bit
P44/RXD
STdetector
7 bits
Receive shift register
8 bits
UART control register
SP detector
PE FE
Address 001B16
Clock control circuit
Serial I/O clock selection bit
P46/SCLK
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
f(XIN
)
Baud rate generator
Address 001C16
(f(XCIN) in low-
speed mode)
ST/SP/PA generator
1/16
Transmit shift register shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit shift register
P45/TXD
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
Transmit buffer register
Address 001916
Serial I/O status register
Address 001816
Data bus
Fig. 22 Block diagram of UART serial I/O
Transmit or receive clock
Transmit buffer write signal
TBE=0
TSC=0
TBE=1
TBE=0
TSC=1✽
SP
TBE=1
ST
D
0
D1
ST
D0
D
1
SP
Serial output TXD
1 start bit
✽Generated at 2nd bit in 2-stop-bit mode
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read signal
RBF=0
RBF=1
SP
RBF=1
SP
ST
ST
D
0
D1
D
0
D1
Serial input RXD
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1” by the setting of the transmit interrupt source
selection bit (TIC) of the serial I/O control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1”.
4: After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 23 Operation of UART serial I/O function
25
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ꢀNotes on serial I/O
[Transmit Buffer/Receive Buffer Register
(TB/RB)] 001816
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer register is write-only
and the receive buffer register is read-only. If a character bit length is
7 bits, the MSB of data stored in the receive buffer register is “0”.
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission enabled,
take the following sequence.
ꢀSet the serial I/O transmit interrupt enable bit to “0” (disabled).
ꢀSet the transmit enable bit to “1”.
ꢀSet the serial I/O transmit interrupt request bit to “0” after 1 or more
instructions have been executed.
[Serial I/O Status Register (SIOSTS)] 001916
The read-only serial I/O status register consists of seven flags (bits 0
to 6) which indicate the operating status of the serial I/O function and
various errors.
ꢀSet the serial I/O transmit interrupt enable bit to “1” (enabled).
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is trans-
ferred from the receive shift register to the receive buffer register,
and the receive buffer full flag is set. A write to the serial I/O status
register clears all the error flags OE, PE, FE, and SE. Writing “0” to
the serial I/O enable bit (SIOE) also clears all the status flags, includ-
ing the error flags.
All bits of the serial I/O status register are initialized to “0” at reset,
but if the transmit enable bit (bit 4) of the serial I/O control register
has been set to “1”, the transmit shift register shift completion flag
(bit 2) and the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O Control Register (SIOCON)] 001A16
The serial I/O control register contains eight control bits for the serial
I/O function.
[UART Control Register (UARTCON)] 001B16
This is a 5 bit register containing four control bits, which are valid
when UART is selected and set the data format of an data receiver/
transfer, and one control bit, which is always valid and sets the out-
put structure of the P45/TXD pin.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
26
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b7
b0
Serial I/O status register
(SIOSTS : address 001916
Serial I/O control register
(SIOCON : address 001A16
)
)
BRG count source selection bit (CSS)
0: f(XIN) (f(XCIN) in low-speed mode)
1: f(XIN)/4 (f(XCIN)/4 in low-speed mode)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Serial I/O synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous serial
I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronous serial I/O is
selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
External clock input divided by 16 when UART is selected.
S
0: P4
1: P4
RDY output enable bit (SRDY)
Overrun error flag (OE)
0: No error
1: Overrun error
7
pin operates as ordinary I/O pin.
pin operates as SRDY output pin.
7
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: OE U PE U FE =0
1: OE U PE U FE =1
Serial I/O mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Not used (returns “1” when read)
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
b7
b0
UART control register
(UARTCON : address 001B16
(pins P4
1: Serial I/O enabled
(pins P4 –P4 operate as serial I/O pins)
4–P47 operate as ordinary I/O pins)
)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
4
7
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P45/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
Not used (return “1” when read)
Fig. 24 Structure of serial I/O control registers
27
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
[A-D Conversion Registers (ADL, ADH)] 003216,
003316
Resistor ladder
The resistor ladder outputs the comparison voltage by dividing the
voltage between VDD and VSS by resistance.
The A-D conversion registers are read-only registers that contain the
result of an A-D conversion. During A-D conversion, do not read these
registers.
Channel Selector
The channel selector selects one of the ports P33/AIN3–P30/AIN0 and
ports P10/AIN4–P13/AIN7, and inputs it to the comparator.
[A-D Control Register (ADCON)] 003116
The A-D control register controls the A-D conversion process. Bits 0
to 2 are analog input pin selection bits. Bit 3 is an A-D conversion
completion bit and “0” during A-D conversion, then changes to “1”
when the A-D conversion is completed. Writing “0” to this bit starts
the A-D conversion. When bit 5, which is the A-D external trigger
valid bit, is set to “1”, A-D conversion is started even by a rising edge
or falling edge of an ADT input.
b7
b0
A-D control register
(ADCON : address 003116
)
Analog input pin selection bits
0 0 0 : P3
0 0 1 : P3
0 1 0 : P3
0 1 1 : P3
1 0 0 : P1
1 0 1 : P1
1 1 0 : P1
1 1 1 : P1
0/AIN0
1/AIN1
2/AIN2
3/AIN3
0/AIN4
1/AIN5
2/AIN6
3/AIN7
Comparator and Control Circuit
A-D conversion completion bit
0 : Conversion in progress
1 : Conversion completed
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the con-
trol circuit sets the A-D conversion completion bit and the A-D inter-
rupt request bit to “1”.
Not used (return “0” when read)
A-D external trigger valid bit
0 : A-D external trigger invalid
1 : A-D external trigger valid
Not used (return “0” when read)
Because the comparator consists of a capacitor coupling, a deficient
conversion speed may cause lack of electric charge and make the
conversion accuracy worse. When A-D conversion is performed, set
f(XIN) to at least 500 kHz.
•8-bit read (Read only address 003216.)
b7
b0
A-D conversion register (low-order)
(ADL: Address 003216
b9 b8 b7 b6 b5 b4 b3 b2
)
When both bit 5 and bit 4 of the CPU mode register are set to “1”,
A-D conversion is performed by using the built-in self-oscillation
circuit.
•10-bit read (Read address 003316 first.)
b0
b7
A-D conversion register (high-order)
b9 b8
(ADH: Address 003316
)
b0
b7
A-D conversion register (low-order)
(ADL: Address 003216
b7 b6 b5 b4 b3 b2 b1 b0
Trigger Start
)
When using the A-D external trigger, set the port shared with the
ADT pin to input. The polarity of INT1 interrupt edge also applies to
the A-D external trigger. When the INT1 interrupt edge polarity is
switched after an external trigger is validated, an A-D conversion
may be started.
Note: High-order 6 bits of address 003316 becomes “0” at reading.
Fig. 25 Structure of A-D control register
Data bus
b0
b7
A-D control register
P41/INT1/ADT
3
A-D control circuit
A-D interrupt request
(L)
P30/AIN0
P31/AIN1
P32/AIN2
P33/AIN3
P10/AIN4
P11/AIN5
P12/AIN6
P13/AIN7
(H)
Comparater
A-D conversion register A-D conversion register
10
Resistor ladder
VSS
VCC
Fig. 26 A-D converter block diagram
28
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
✽Bias controller
LCD CONTROLLER/DRIVER
The 38C8 group has the built-in Liquid Crystal Display (LCD)
controller/driver consisting of the following.
✽240-byte LCD display RAM
✽Voltage multiplier
✽LCD mode register
✽LCD control registers 1, 2
A maximum of 68 segment output pins and 32 common output pins
can be used for control of external LCD display.
✽52 or 68 segment driver
✽16 or 32 common driver
✽LCD clock generator
✽Timing controller
Fig. 27 Block diagram of LCD controller/driver
29
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 7 Maximum number of display pixels at each duty ratio
LCD Controller/Driver Function
Duty ratio
16
Maximum number of display pixel
16 ✕ 68 dots
The controller/driver performs the bias control and the time sharing
control by the LCD control registers 1, 2 (LC1, LC2), and the LCD
mode register (LM). The data of corresponding LCDRAM is output
from the segment pins according to the output timing of the common
pins.
(5 ✕ 7 dots + cursor 2 lines)
32 ✕ 52 dots
32
(5 ✕ 7 dots + cursor 4 lines)
The 38C8 group has the voltage multiplier only for LCD in addition to
LCD controller/driver .
Note: When executing the STP instruction while operating LCD, ex-
ecute the STP instruction after prohibiting LCD (set “0” to bit 3
of the LCD mode regsiter).
[LCD mode register (LM)] 003916
The LCD mode register is used for setting the LCD controller/driver
according to the LCD panel used.
[LCD control register 1 (LC1)] 003716
The LCD control register 1 controls the voltage multiplier and built-in
resistance.
[LCD control register 2 (LC2)] 003816
The LCD control register 2 is write-only. Setting “1” to bit 5 makes
built-in resistance low resistance, and can raise drivability of the seg-
ment pins and the common pins.
b7
b0
b7
b0
LCD mode register
(LM: address 003916)
LCD control register 1
(LC1: address 003716)
✕
Duty ratio selsection bit
Not used
1 : 32 duty (use COM0–COM31)
0 : 16 duty (use COM0–COM15)
Not used
(Do not write “0” to this bit.)
LCD display RAM address selection bit
0 : 3 page
(Do not write “1” to these bits.)
Drivability selection bit 1
0 : Normal (Drivability selection
bit 2 valid)
1 : Restraint (Note 1)
Not used
1 : 0 page
(Do not write “1” to this bit.)
LCD enable bit
0 : LCD OFF
1 : LCD ON
LCD drive timing selection bit
0 : A type
Voltage multiplier enable bit
0 : Voltage multiplier stop
1 : Voltage multiplier operating
1 : B type
LCDCK division ratio selection bits
b6 b5
Note 1: Consumption current can be reduced by restraint of drivability. But
an irregular display might be caused according to the panel or the
display pattern.
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit (Note 3)
0 : f(XIN)/1024
1 : f(XCIN)/16
Note 3: LCDCK is a clock for a LCD timing controller.
b7
b0
Internal clock φ is XCIN divided by 2 in the low-speed mode.
✕ When selecting 32 duty, functions of pins 135 to 142 become COM16 to COM23,
and functions of pins 75 to 82 become COM24 to COM31.
LCD control register 2
(LC2: address 003816)
Not used (Do not write “1” to these bits.)
Drivability selection bit 2
0 : Normal
1 : Reinforcing (Note 2)
Not used (Do not write “1” to these bits.)
Note 2: The drive of a more large-scale LCD panel becomes easy by setting “1”
to this bit. But consumption current is increased at LCD drive. When
the drivability selection bit 1 is “1”, this function is invaid.
Fig. 28 Structure of LCD control register
30
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Bias Control
Voltage Multiplier
In the LCD power source pins (VL1–VL5), 1/7 bias is automatically
generated in 32 duty ratio and 1/5 bias is done in 16 duty ratio as
well. Be sure to connect the capacitor for smoothness to these pins.
When requiring 1/5 bias in 32 duty ratio, use an external resistor to
generate a necessary level. In this case the drivability selection bit 1
of LCD control register 1 must be “1”.
When the voltage multiplier is operated after a reference voltage for
boosting is applied to LCD power supply VLIN, a voltage that is ap-
proximately three times as large as that of VLIN pin occurs at the VL5
pin. Operate the voltage multiplier after applying a reference voltage
for boosting to VLIN.
The voltage multiplier multiplies a VLIN voltage by charge/discharge
of capacitors between C1 and C2 pins and to C3 pin. Accordingly, if a
large LCD panel is driven or a vias value is changed owing to an
external resistor, a level from VL5 pin might be not a requested level.
To prevent this, we recommend use of an external power source
which can supply stabilized power.
Additionally, when using the voltage multiplier, set a higher resistor
value (the sum of R1 to R5) as possible (100 kΩ or more recom-
mended).
Table 8 Bias control and applied voltage to VL1–VL5
Bias value
Voltage value
VL5 = VLCD
VL4 = 6/7 VLCD
VL3 = 5/7 VLCD
VL2 = 2/7 VLCD
VL1 = 1/7 VLCD
VL5 = VLCD
1/7 bias
in 32 duty ratio
VL4 = 4/5 VLCD
VL3 = 3/5 VLCD
VL2 = 2/5 VLCD
VL1 = 1/5 VLCD
1/5 bias
in 16 duty ratio
Note: VLCD is a value which can be supplied to the LCD panel. Set value
which is less than maximum ratings to VLCD.
RT
RT
R1
V
L5
V
L5
V
L5
V
V
L4
L3
V
V
L4
L3
V
V
L4
L3
R2
R3
R4
R5
V
L2
L1
V
L2
L1
V
L2
V
L1
V
V
C
C
C
3
C
C
C
3
C
3
2
2
1
2
1
C
•At 1/5 bias
C
1
R1=R2=R3=R4=R5
•At 1/7 bias
R1=R2=R4=R5
R3=3•R1
V
LIN
V
LIN
V
LIN
1.3 to
2.33 V
1/5, 1/7 bias
When using voltage multiplier
circuit
1/5, 1/7 bias
When not using voltage
multiplier circuit (1)
1/5, 1/7 bias
When not using voltage
multiplier circuit (2)
Fig. 29 Example of circuit at each bias
31
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Common Pin and Duty Ratio Control
The common pins (COM0–COM31) to be used are determined by
duty ratio.
LCD Display RAM
When LCD display RAM address selection bit is “0”, the area of ad-
dresses 034016 to 042F16 is the designated RAM for the LCD dis-
play. When the bit is “1”, the area of addresses 004016 to 012F16 is
the designated RAM for it. When “1”s are written to these addresses,
the corresponding segments of the LCD display panel are turned on.
Select duty ratio by the duty ratio selection bit (bit 0 of the LCD mode
register).
Table 9 Duty ratio control and common pins used
Duty ratio
selection bit
Duty
ratio
LCD Drive Timing
Common pins used
The LCDCK timing frequency (LCD drive timing) is generated inter-
nally and the frame frequency can be determined with the following
equation;
16
32
0
1
COM0–COM15 (Note)
COM0–COM31
Note: The SEG0/COM16–SEG7/COM23 pins are used as the SEG0–SEG7.
(frequency of count source for LCDCK)
f(LCDCK) =
The SEG67/COM24–SEG60/COM31 pins are used as the SEG67–SEG60.
(divider division ratio for LCD)
f(LCDCK)
Frame frequency =
(duty ratio)
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
1
1
0
1
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
0
1
1
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
0
0
0
0
1
0
1
0
0
1
0
0
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
1
0
0
0
0
0
1
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
1
1
1
1
1
1
1
0
1
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LSB
MSB
LSB
MSB
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
1
1
0
1
0
0
1
0
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LSB
MSB
LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MSB
LCD display map
When selecting 3 page
When selecting 0 page
Fig. 30 LCD display RAM map
32
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
LCDCK
COM23
1 frame (16 clocks)
1 frame (16 clocks)
VL5
VL4
VL3
VL2
VL1
VSS
VL5
VL4
VL3
VL2
VL1
VSS
COM22
VL5
VL4
VL3
VL2
VL1
VSS
SEG0
VL5
VL4
VL3
VL2
VL1
VSS
VL1
VL2
VL3
VL4
VL5
SEG0 –
COM23
ON
OFF
ON
OFF
VL5
VL4
VL3
VL2
VL1
VSS
VL1
VL2
VL3
VL4
VL5
SEG0 –
COM22
OFF
OFF
Fig. 31 LCD drive waveform (16 duty ratio, 1/5 bias, A type)
33
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
LCDCK
1 frame (32 clocks)
1 frame (32 clocks)
V
V
L5
L4
31 VL3
COM
V
V
V
L2
L1
SS
V
V
V
L5
L4
L3
COM30
V
V
V
L2
L1
SS
V
V
V
L5
L4
L3
SEG
0
V
V
V
L2
L1
SS
V
V
V
L5
L4
L3
V
V
V
V
V
L2
L1
SS
L1
L2
SEG
COM31
0 –
V
V
V
L3
L4
L5
ON
OFF
ON
OFF
ON
OFF
V
V
V
L5
L4
L3
V
V
V
V
V
L2
L1
SS
L1
L2
SEG
COM30
0 –
V
V
V
L3
L4
L5
OFF
OFF
OFF
Fig. 32 LCD drive waveform (32 duty ratio, 1/7 bias, B type)
34
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is returned to an “H” level
(the power source voltage should be between VCC (min.) and 5.5 V,
and the quartz-crystal oscillator should be stable), reset is released.
After the reset is completed, the program starts from the address
contained in address FFFD16 (high-order byte) and address FFFC16
(low-order byte). Make sure that the reset input voltage is less than
0.2Vcc when a power source voltage passes VCC (min.).
Poweron
Power source
voltage
0V
RESET
VCC
Reset input
voltage
0V
0.2VCC
RESET
VCC
Power source
voltage detection
circuit
Fig. 33 Reset circuit example
X
IN
φ
RESET
Internal
reset
Reset address from
vector table
Address
Data
?
?
?
?
ADH, AD
L
FFFC
FFFD
AD
L
ADH
SYNC
XIN : about 8200 cycles
Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN) = 8 • f(φ).
2: The question marks (?) indicate an undefined state that
depends on the previous state.
Fig. 34 Reset sequence
35
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address Register contents
Address Register contents
(1) Port P0 direction register
(2) Port P1 direction register
(3) Port P2 direction register
(4) Port P3 direction register
(5) Port P4 direction register
(6) PULL register A
000116
000316
000516
000716
000916
001616
001716
001916
001A16
001B16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
0016
0016
0016
0016
0016
0016
0016
8016
0016
E016
FF16
FF16
FF16
FF16
FF16
0116
FF16
0016
0016
0016
003116
003216
003316
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
(21) A-D control register
0816
XX16
XX16
0016
0016
0316
0016
4C16
0016
0016
0016
0016
(22) A-D conversion register
(low-order)
(23) A-D conversion register
(high-order)
(24) LCD control register 1
(25) LCD control register 2
(26) LCD mode register
(7) PULL register B
(27) Interrupt edge selection register
(28) CPU mode register
(8) Serial I/O status register
(9) Serial I/O control register
(10) UART control register
(11) Timer X (low-order)
(12) Timer X (high-order)
(13) Timer Y (low-order)
(14) Timer Y (high-order)
(15) Timer 1
(29) Interrupt request register 1
(30) Interrupt request register 2
(31) Interrupt control register 1
(32) Interrupt control register 2
(33) Processor status register
(34) Program counter
1
(PS) ✕ ✕ ✕ ✕ ✕ ✕ ✕
Contents of address FFFD16
(PCH)
Contents of address FFFC16
(PCL)
(16) Timer 2
(17) Timer 3
(18) Timer X mode register
(19) Timer Y mode register
(20) Timer 123 mode register
Note: The contents of all other register and RAM are undefined after reset, so they must be initialized by software.
✕ : Undefined
Fig. 35 Internal status at reset
36
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
Oscillation Control
The 38C8 group has two built-in oscillation circuits: main clock XIN-
XOUT oscillation circuit and sub-clock XCIN-XCOUT oscillation circuit.
An oscillation circuit can be formed by connecting a resonator be-
tween XIN and XOUT (XCIN and XCOUT). RC oscillation is available for
XIN-XOUT.
(1) Stop Mode
If the STP instruction is executed, the internal clock φ stops at an “H”
level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16” and
timer 2 is set to “0116.”
Either XIN divided by 16 or XCIN divided by 16 is input to timer 1 as
count source, and the output of timer 1 is connected to timer 2. The
bits except bit 4 of the timer 123 mode register are cleared to “0.” Set
the interrupt enable bits of timer 1 and timer 2 to disabled (“0”) before
executing the STP instruction.
Immediately after reset is released, the XIN-XOUT oscillation circuit
starts oscillating, and XCIN and XCOUT pins go to high impedance
state.
Main Clock
Oscillator restarts at reset or when an external interrupt is received,
but the internal clock φ is not supplied to the CPU until timer 2
underflows. This allows time for the clock circuit oscillation to stabi-
lize.
An oscillation circuit by a resonator can be formed by setting the
OSCSEL pin is set to “L” level and connecting a resonator between
XIN and XOUT. Use the circuit constants in accordance with the reso-
nator manufacturer’s recommended values. No external resistor is
needed between XIN and XOUT since a feed-back resistor exists on-
chip. To supply a clock signal externally, make the XOUT pin open in
the “L” level state of the OSCSEL pin, and supply the clock from the
XIN pin. The RC oscillation circuit can be formed by setting the
OSCSEL pin to “H” level and connecting a resistor between the XIN
pin and the XOUT pin. At this time, the feed-back resistor is cut off.
The frequency of the RC oscillation changes owing to a parasitic
capacitance or the wiring length etc. of the printed circuit board. Do
not use the RC oscillation in the usage which the frequency accuracy
of the main clock is needed.
(2) Wait Mode
If the WIT instruction is executed, the internal clock φ stops at an “H”
level. The states of XIN and XCIN are the same as the state before
executing the WIT instruction. The internal clock φ restarts at reset
or when an interrupt is received. Since the oscillator does not stop,
normal operation can be started immediately after the clock is re-
started.
Sub-clock
Connect a resonator between XCIN and XCOUT. An external feed-
back resistor is needed between XCIN and XCOUT since a feed-back
resistor does not exist on-chip. The sub-clock XCIN-XCOUT oscillation
circuit cannot directly input clocks that are externally generated. Ac-
cordingly, be sure to cause an external resonator to oscillate.
X
CIN
X
COUT OSCSEL
Rd
XIN
XOUT
Rf
Rosc
Frequency Control
C
CIN
(1) Middle-speed Mode
The internal clock φ is the frequency of XIN divided by 8. After reset is
released, this mode is selected.
Fig. 36 RC oscillation circuit
(2) High-speed Mode
The internal clock φ is the frequency of XIN divided by 2.
(3) Low-speed Mode
The internal clock φ is the frequency of XCIN divided by 2.
A low-power consumption operation can be realized by stopping the
main clock XIN in this mode. To stop the main clock, set bit 5 of the
CPU mode register to “1”. When the main clock XIN is restarted, set
enough time for oscillation to stabilize by programming.
XCIN
XCOUT OSCSEL XIN
XOUT
■Notes on clock generating circuit
Rf
Rd
If you switch the mode between middle/high-speed and low-speed,
stabilize both XIN and XCIN oscillations. The sufficient time is required
for the sub-clock to stabilize, especially immediately after power on
and at returning from stop mode. When switching the mode between
middle/high-speed and low-speed, set the frequency on condition
that f(XIN) > 3•f(XCIN).
C
OUT
C
COUT
CIN
C
CIN
Fig. 37 Resonator circuit
37
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
X
COUT
X
CIN
Timer 1 count
source selection
bit
Timer 2 count
source selection
bit
Internal system clock selection bit
X
IN
X
OUT
(Note)
Low-speed mode
“1”
“0”
“1”
Timer 1
Timer 2
1/2
1/2
1/4
“0”
“0”
Middle-/High-speed mode
“1”
Main clock division ratio selection bit
Middle-speed mode
“1”
Timing φ
(Internal clock)
“0”
High-speed mode
or Low-speed mode
Main clock stop bit
Q
S
R
S
R
Q
S
R
Q
WIT
instruction
STP instruction
STP instruction
Reset
Interrupt disable flag
I
Interrupt request
Note: When selecting the XC oscillation, set the sub-clock (XCIN –XCOUT) oscillating bit to “1”.
Fig. 38 Clock generating circuit block diagram
38
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
CM
6
Middle-speed mode (f(φ) = 0.5 MHz)
High-speed mode (f(φ) = 2 MHz)
CM
CM
CM
CM
7
6
5
4
= 0 (4 MHz selected)
= 1 (Middle-speed)
= 0 (4 MHz oscillating)
= 0 (32 kHz stoped)
“1”
“0”
CM
CM
CM
CM
7
6
5
4
= 0 (4 MHz selected)
= 0 (High-speed)
= 0 (4 MHz oscillating)
= 0 (32 kHz stoped)
C
M
“
0
4
”
”
0
C
“
M
M4
“
1
6
”
”
0
C
“
“
”
1
M6
1
”
“
C
“
”
0
1
”
“
CM
6
Middle-speed mode (f(φ) = 0.5 MHz)
High-speed mode (f(φ) = 2 MHz)
CM
CM
CM
CM
7
6
5
4
= 0 (4 MHz selected)
= 1 (Middle-speed)
= 0 (4 MHz oscillating)
= 1 (32 kHz oscillating)
CM
CM
CM
CM
7
6
5
4
= 0 (4 MHz selected)
= 0 (High-speed)
= 0 (4 MHz oscillating)
= 1 (32 kHz oscillating)
“0”
“1”
Low-speed mode (f(φ) = 16 kHz)
Low-speed mode (f(φ) =16 kHz)
CM
6
CM
CM
CM
CM
7
6
5
4
= 1 (32 kHz selected)
= 1 (Middle-speed)
= 0 (4 MHz oscillating)
= 1 (32 kHz oscillating)
CM
CM
CM
CM
7
6
5
4
= 1 (32 kHz selected)
= 0 (High-speed)
= 0 (4 MHz oscillating)
= 1 (32 kHz oscillating)
“1”
“0”
b7
b4
CPU mode register
(CPUM : address 003B16
)
C
M
“
0
5
CM
CM
CM
CM
4 : Sub-clock (XCIN –XCOUT) oscillating bit
0: Stopped
1: Oscillating
”
C
”
0
M
“
“
1
6
M5
”
”
“
0
1
C
“
”
”
5
: Main clock (XIN–XOUT) stop bit
M6
1
“
“
0
C
0: Oscillating
1: Stopped
”
”
1
“
6
: Main clock division ratio selection bit
Low-speed mode (f(φ) =16 kHz)
Low-speed mode (f(φ) =16 kHz)
CM6
0: f(XIN)/2 (high-speed mode)
1: f(XIN)/8 (middle-speed mode)
CM
CM
CM
CM
7
6
5
4
= 1 (32 kHz selected)
= 1 (Middle-speed)
= 1 (4 MHz stopped)
CM
CM
CM
CM
7
6
5
4
= 1 (32 kHz selected)
= 0 (High-speed)
= 1 (4 MHz stopped)
= 1 (32 kHz oscillating)
“1”
“0”
7
: Internal system clock selection bit
0: XIN–XOUT selected
= 1 (32 kHz oscillating)
(middle-/high-speed mode)
1: XCIN–XCOUT selected
(low-speed mode)
Notes
1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is ended.
3 : Timer and LCD operate in the wait mode.
4 : When the stop mode is ended, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2 in middle-/high-speed mode.
5 : When the stop mode is ended, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2 in low-speed mode.
6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle-/high-speed mode.
7 : The example assumes that 4 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
Fig. 39 State transitions of system clock
39
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING
A-D Converter
Processor Status Register
The comparator is constructed linked to a capacitor. When the con-
version speed is not enough, the conversion accuracy might be ru-
ined by the disappearance of the charge. When A-D conversion is
performed, set f(XIN) to at least 500 kHz.
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. After a
reset, initialize flags which affect program execution. In particular, it
is essential to initialize the index X mode (T) and the decimal mode
(D) flags because of their effect on calculations.
When the following operations are performed, the A-D conversion
operation cannot be guaranteed.
•When the CPU mode register is operated during A-D conversion
operation,
Interrupts
The contents of the interrupt request bits do not change immediately
after they have been written. After writing to an interrupt request reg-
ister, execute at least one instruction before performing a BBC or
BBS instruction.
•When the A-D control register is operated during A-D conversion
operation,
•When STP or WIT instruction is executed during A-D conversion
operation.
Decimal Calculations
Instruction Execution Time
• To calculate in decimal notation, set the decimal mode flag (D) to
“1”, then execute an ADC or SBC instruction. After executing an
ADC or SBC instruction, execute at least one instruction before
executing a SEC, CLC, or CLD instruction.
The instruction execution time is obtained by multiplying the frequency
of the internal clock φ by the number of cycles needed to execute an
instruction.
The number of cycles required to execute an instruction is shown in
the list of machine instructions.
• In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
LCD Control
Timers
When using the voltage multiplier, apply prescribed voltage to the
VLIN pin in the state in which the LCD enable bit is “0”, and set the
voltage multiplier enable bit to “1”.
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n+1).
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
• The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read. The fol-
lowing cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction register
as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a
direction register.
Use instructions such as LDM and STA, etc., to set the port direction
registers.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an exter-
nal clock and it is to output the SRDY signal, set the transmit enable
bit, the receive enable bit, and the SRDY output enable bit to “1”.
Serial I/O continues to output the final bit from the TxD pin after trans-
mission is completed.
40
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON USE
Countermeasures Against Noise
Noise
(1) Shortest wiring length
➀ Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin as
short as possible. Especially, connect a capacitor across the RESET
pin and the VSS pin with the shortest possible wiring (within 20mm).
X
X
IN
X
X
IN
OUT
OUT
V
SS
V
SS
➀ Reason
The width of a pulse input into the RESET pin is determined by the
timing necessary conditions. If noise having a shorter pulse width
than the standard is input to the RESET pin, the reset is released
before the internal state of the microcomputer is completely initial-
ized. This may cause a program runaway.
O.K.
N.G.
Fig. 41 Wiring for clock I/O pins
(2) Connection of bypass capacitor across VSS line and VCC line
In order to stabilize the system operation and avoid the latch-up,
connect an approximately 0.1 µF bypass capacitor across the VSS
line and the VCC line as follows:
Noise
• Connect a bypass capacitor across the VSS pin and the VCC pin at
equal length.
Reset
RESET
circuit
• Connect a bypass capacitor across the VSS pin and the VCC pin
with the shortest possible wiring.
V
SS
V
SS
• Use lines with a larger diameter than other signal lines for VSS line
and VCC line.
N.G.
• Connect the power source wiring via a bypass capacitor to the VSS
pin and the VCC pin.
Reset
circuit
RESET
V
CC
V
CC
V
SS
V
SS
O.K.
Fig. 40 Wiring for the RESET pin
V
SS
V
SS
➀ Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as
short as possible.
N.G.
O.K.
• Make the length of wiring (within 20 mm) across the grounding
lead of a capacitor which is connected to an oscillator and the
VSS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS pat-
terns.
Fig. 42 Bypass capacitor across the VSS line and the VCC line
➀ Reason
If noise enters clock I/O pins, clock waveforms may be deformed.
This may cause a program failure or program runaway. Also, if a
potential difference is caused by the noise between the VSS level
of a microcomputer and the VSS level of an oscillator, the correct
clock will not be input in the microcomputer.
41
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(3) Oscillator concerns
(4) Analog input
In order to obtain the stabilized operation clock on the user system
and its condition, contact the oscillator manufacturer and select the
oscillator and oscillation circuit constants. Be careful especially when
range of voltage or/and temperature is wide.
The analog input pin is connected to the capacitor of a comparator.
Accordingly, sufficient accuracy may not be obtained by the charge/
discharge current at the time of A-D conversion when the analog
signal source of high-impedance is connected to an analog input pin.
In order to obtain the A-D conversion result stabilized more, please
lower the impedance of an analog signal source, or add the smooth-
ing capacitor to an analog input pin.
Also, take care to prevent an oscillator that generates clocks for a
microcomputer operation from being affected by other signals.
➀ Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as pos-
sible from signal lines where a current larger than the tolerance of
current value flows.
(5) Difference of memory type and size
When Mask ROM and PROM version and memory size differ in one
group, actual values such as an electrical characteristics, A-D con-
version accuracy, and the amount of proof of noise incorrect opera-
tion may differ from the ideal values.
➀ Reason
In the system using a microcomputer, there are signal lines for
controlling motors, LEDs, and thermal heads or others. When a
large current flows through those signal lines, strong noise occurs
because of mutual inductance.
When these products are used switching, perform system evaluation
for each product of every after confirming product specification.
(6) Wiring to VPP pin of One Time PROM version
Connect an approximately 5 kΩ resistor to the VPP pin the shortest
possible in series.
➀ Installing oscillator away from signal lines where potential levels
change frequently
Install an oscillator and a connecting pattern of an oscillator away
from signal lines where potential levels change frequently. Also,
do not cross such signal lines over the clock lines or the signal
lines which are sensitive to noise.
Note: Even when a circuit which included an approximately 5 kΩ
resistor is used in the Mask ROM version, the microcomputer
operates correctly.
➀ Reason
➀ Reason
The VPP pin of the One Time PROM version is the power source
input pin for the built-in PROM. When programming in the built-in
PROM, the impedance of the VPP pin is low to allow the electric cur-
rent for writing flow into the built-in PROM. Because of this, noise
can enter easily. If noise enters the VPP pin, abnormal instruction
codes or data are read from the built-in PROM, which may cause a
program runaway.
Signal lines where potential levels change frequently (such as the
CNTR pin signal line) may affect other lines at signal rising edge
or falling edge. If such lines cross over a clock line, clock wave-
forms may be deformed, which causes a microcomputer failure or
a program runaway.
➀ Keeping oscillator away from large current signal lines
Microcomputer
Mutual inductance
M
About 5kΩ
P40/VPP
Source signal
X
X
IN
Large
current
VSS
OUT
V
SS
GND
➀ Installing oscillator away from signal lines where potential lev-
Fig. 44 Wiring for the VPP pin of One Time PROM
els change frequently
N.G.
CNTR
Do not cross
X
X
V
IN
OUT
SS
Fig. 43 Wiring for a large current signal line/Wiring of signal lines
where potential levels change frequently
42
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and built-in
EPROM version can be read or programmed with a general-purpose
PROM programmer using a special programming adapter
(PCA7447FP).
✽
1. Mask ROM Order Confirmation Form
✽
2. Mark Specification Form
3. Data to be written to ROM, in EPROM form (three identical copies)
or one floppy disk.
Table 10 Programming adapter
Name of Programming Adapter
PCA7447FP
Package
✽For the mask ROM confirmation and the mark specifications, refer
to the “Mitsubishi MCU Technical Information” Homepage
(http://www.infomicom.maec.co.jp/indexe.htm).
144P6Q-A
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 45 is recommended to verify programming.
Programming with PROM
programmer
Screening (Caution)
(150°C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Caution :
Fig. 45 Programming and testing of One Time PROM version
43
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
Table 11 Absolute maximum ratings
Parameter
Power source voltage
Conditions
Ratings
–0.3 to 7.0
Unit
V
Symbol
VCC
Input voltage
P00–P07, P10–P17, P20–P27,
P30–P33, P40–P47
–0.3 to VCC+0.3
V
VI
All voltages are based on
Vss. Output transistors
are cut off.
Input voltage
Input voltage
Input voltage
C1, C2
–0.3 to 7.0
–0.3 to VCC+0.3
–0.3 to 7.0
V
V
V
VI
VI
VI
RESET, XIN, XCIN
VLIN
When voltage multiplier is
not operated.
Input voltage
VL1, VL2, VL3, VL4, VL5
VL1≤VL2≤VL3≤VL4≤VL5
–0.3 to 7.0
V
V
VI
Output voltage P00–P07, P10–P17, P20–P27,
P30–P33, P41–P47
–0.3 to VCC+0.3
VO
Output voltage C1, C2, C3
Output voltage COM0–COM31, SEG0–SEG67
Output voltage XOUT, XCOUT
Power dissipation
–0.3 to 7.0
–0.3 to VL5+0.3
–0.3 to VCC+0.3
300
V
V
VO
VO
VO
Pd
V
Ta = 25°C
mW
°C
°C
Operating temperature
–20 to 85
Topr
Tstg
Storage temperature
–40 to 125
Table 12 Recommended operating conditions (Vcc = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
VCC
Parameter
Unit
Min.
4.0
2.7
2.2
2.5
2.2
2.5
Typ.
5.0
5.0
5.0
5.0
5.0
5.0
0
Max.
5.5
5.5
5.5
5.5
5.5
5.5
Power source
voltage
High-speed mode f(XIN) ≤ 8 MHz
V
V
Middle-speed mode f(XIN) ≤ 8 MHz
Middle-speed mode (mask ROM version) f(XIN) ≤ 4 MHz
Middle-speed mode (One Time PROM version) f(XIN) ≤ 4 MHz
Low-speed mode (mask ROM version)
V
V
V
Low-speed mode (One Time PROM version)
V
VSS
Power source voltage
Power source voltage
Power source voltage
Analog input voltage
“H” input voltage
V
VLIN
VLIN
V
2.33
7.0
VL5
VL5
V
VIA
AIN0–AIN7
V
VSS
0.7VCC
0.8VCC
0.8VCC
0.8VCC
VSS
VCC
VIH
P00–P07, P10–P17, P45, P47
V
VCC
VIH
“H” input voltage
P20–P27, P30–P33, P40–P43, P44, P46
V
VCC
VIH
“H” input voltage
RESET
V
VCC
VIH
“H” input voltage
XIN
V
VCC
VIL
“L” input voltage
P00–P07, P10–P17, P45, P47
V
0.3VCC
0.2VCC
0.2VCC
0.2VCC
–60.0
60.0
VIL
“L” input voltage
P20–P27, P30–P33, P40–P43, P44, P46
V
VSS
VIL
“L” input voltage
RESET
XIN
V
VSS
VIL
“L” input voltage
V
VSS
ΣIOH(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOL(avg)
IOH(peak)
IOL(peak)
IOH(avg)
IOL(avg)
ROSC
“H” total peak output current
“L” total peak output current
All ports
All ports
(Note 1)
(Note 1)
(Note 2)
(Note 2)
(Note 3)
(Note 3)
(Note 4)
(Note 4)
mA
mA
mA
mA
mA
mA
mA
mA
kΩ
“H” total average output current All ports
“L” total average output current All ports
–30.0
30.0
“H” peak output current
“L” peak output current
“H” average output current
“L” average output current
All ports
All ports
All ports
All ports
–5.0
10.0
–2.5
5.0
Oscillation resistor at selecting RC oscillation
5
8.2
10
Notes 1: The total peak output current is the peak value of the peak currents flowing through all the applicable ports.
2: The total average output current is the average value measured over 100 ms flowing through all the applicable ports.
3: The peak output current is the peak current flowing in each port.
4: The average output current is an average value measured over 100 ms.
44
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 13 Recommended operating conditions (mask ROM version) (Vcc = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Unit
Hz
Parameter
Conditions
Min.
Typ.
Max.
f(CNTR0)
f(CNTR1)
f(XIN)
Timer X, timer Y input frequency (duty cycle 50%)
f(XIN)/2
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
Main clock input oscillation frequency (Note 1)
MHz
MHz
MHz
MHz
kHz
8.0
2.9✽VCC–3.6
8.0
High-speed mode
(2.2 V ≤ VCC < 4.0 V)
Middle-speed mode
(2.7 V ≤ VCC ≤ 5.5 V)
Middle-speed mode
(2.2 V ≤ VCC < 2.7 V)
8✽(VCC–1.7)
50
f(XCIN)
Sub-clock input oscillation frequency (Notes 1, 2)
32.768
Notes 1: When the oscillation frequency has a duty cycle of 50 %.
2: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
Table 14 Recommended operating conditions (PROM version) (Vcc = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Conditions
Symbol
Unit
Hz
Parameter
Min.
Typ.
Max.
f(CNTR0)
f(CNTR1)
f(XIN)
Timer X, timer Y input frequency (duty cycle 50%)
f(XIN)/2
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
Main clock input oscillation frequency (Note 1)
MHz
MHz
MHz
MHz
kHz
8.0
4✽VCC–8
8.0
High-speed mode
(2.5 V ≤ VCC < 4.0 V)
Middle-speed mode
(2.7 V ≤ VCC ≤ 5.5 V)
Middle-speed mode
(2.5 V ≤ VCC < 2.7 V)
20✽(VCC–2.3)
50
f(XCIN)
Sub-clock input oscillation frequency (Notes 1, 2)
32.768
Notes 1: When the oscillation frequency has a duty cycle of 50 %.
2: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
45
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 15 Electrical characteristics (Vcc = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol Parameter Test conditions
IOH = –5.0 mA
Limits
Typ.
Unit
V
Min.
Max.
VOH
“H” output voltage
VCC–2.0
P00–P07, P10–P17, P30–P33
VCC = 5.0 V
IOH = –1.5 mA
VCC = 5.0 V
VCC–0.5
VCC–1.0
VCC–2.0
VCC–0.5
VCC–1.0
V
V
V
V
V
V
V
V
V
V
V
V
IOH = –1.25 mA
VCC = 2.2 V
VOH
“H” output voltage
P20–P27, P41–P47
IOH = –5.0 mA
VCC = 5.0 V
IOH = –1.5 mA
VCC = 5.0 V
IOH = –1.25 mA
VCC = 2.2 V
VOL
“L” output voltage
IOL = 5.0 mA
VCC = 5.0 V
2.0
0.5
1.0
2.0
0.5
1.0
P00–P07, P10–P17, P30–P33
IOL = 1.5 mA
VCC = 5.0 V
IOL = 1.25 mA
VCC = 2.2 V
VOL
“L” output voltage
P20–P27, P41–P47
IOL = 5.0 mA
VCC = 5.0 V
IOL = 1.5 mA
VCC = 5.0 V
IOL = 1.25 mA
VCC = 2.2 V
VT+–VT-
Hysteresis
0.5
INT0, INT1, ADT, CNTR0, CNTR1, P20–P27
VT+–VT-
VT+–VT-
IIH
Hysteresis SCLK, RxD
Hysteresis RESET
0.5
0.5
V
V
“H” input current All ports
“H” input current RESET
“H” input current XIN
5.0
5.0
µA
µA
µA
µA
IIH
IIH
4.0
IIL
“L” input current All ports
VI = VSS
Pull-ups “off”
–5.0
–240.0
–40.0
–5.0
VCC = 5.0 V, VI = VSS
Pull-ups “on”
–60.0
–5.0
–120.0
–20.0
µA
µA
VCC = 2.2 V, VI = VSS
Pull-ups “on”
IIL
IIL
“L” input current RESET
“L” input current XIN
VI = VSS
VI = VSS
µA
µA
–4.0
46
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 16 Electrical characteristics (Vcc = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
5.0
Symbol
Parameter
Test conditions
Unit
Min.
2.0
Max.
5.5
VRAM
ICC
RAM hold voltage
When clock is stopped
V
Power source current
High-speed mode, Vcc = 5.0 V
f(XIN) = 8.0 MHz
5.5
11.0
mA
f(XCIN) = 32.768 kHz
Middle-speed mode, Vcc = 5.0 V
f(XIN) = 8.0 MHz
f(XCIN) = 32.768 kHz
3.0
1.0
6.0
2.0
mA
mA
µA
Middle-speed mode, Vcc = 3.0 V
f(XIN) = 8.0 MHz
f(XCIN) = 32.768 kHz
Low-speed mode, VCC = 3.0 V,
f(XIN) = stopped
f(XCIN) = 32.768 kHz
20.0
0.9
40.0
1.8
High-/Middle-speed mode, VCC =
5.0 V,
mA
f(XIN) = 8.0 MHz (in WIT state)
f(XCIN) = 32.768 kHz
High-/Middle-speed mode, Vcc = 3.0 V
f(XIN) = 8.0 MHz (in WIT state)
f(XCIN) = 32.768 kHz
0.3
4.5
0.1
0.6
9.0
mA
µA
Low-speed mode, VCC = 3.0 V,
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
All oscillation stopped
Ta = 25 °C, Output transistors “off”
(in STP state)
1.0
µA
µA
mA
All oscillation stopped
Ta = 85 °C, Output transistors “off”
(in STP state)
10.0
1.6
IAD
A-D converter current
dissipation
Current increase at A-D converter
operated, f(XIN) = 8.0 MHz
0.8
IL5
VL5 input current (Note)
VL5 = 6.0 V, Ta = 25 °C
ROSC = 8.2 kΩ
3
6
µA
FROSC
RC oscillation frequency
1.5
2.5
3.5
MHz
Note: When normal drivability (drivability selection bit 1 = “0”, drivability selection bit 2 = “0”) is selected.
47
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 17 A-D converter characteristics
(Vcc = 2.2 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, f(XIN) ≤ 4 MHz, in middle-speed/high-speed mode)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
30.5
Max.
10
—
—
Resolution
Bits
LSB
LSB
µs
Absolute accuracy
VCC = 2.7–5.5 V
±4
(excluding quantization error)
Conversion time
VCC = 2.5–2.7 V (Ta = –10 to 50 °C)
f(XIN) = 4 MHz (Note)
±6
tconv
IIA
34
Analog port input current
0.5
5.0
µA
Note: When main clock is selected as system clock.
Table 18 Timing requirements 1 (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
2
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0, INT1 input “H” pulse width
INT0, INT1 input “L” pulse width
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input setup time
125
45
twH(XIN)
twL(XIN)
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
250
105
105
80
twL(INT)
80
tc(SCLK)
(Note)
(Note)
(Note)
800
370
370
220
100
twH(SCLK)
twL(SCLK)
tsu(RxD-SCLK)
th(SCLK-RxD)
Serial I/O input hold time
Note: When bit 6 of address 001A16 is “1”.
Divide this value by four when bit 6 of address 001A16 is “0”.
Table 19 Timing requirements 2 (mask ROM version) (Vcc = 2.2 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Reset input “L” pulse width
Unit
Min.
Typ.
Max.
tw(RESET)
tc(XIN)
2
µs
ns
ns
ns
ns
ns
ns
s
Main clock input cycle time (XIN input) Vcc = 2.7 to 4.0 V
Main clock input cycle time (XIN input) Vcc = 2.2 to 2.7 V
Main clock input “H” pulse width Vcc = 2.7 to 4.0 V
Main clock input “H” pulse width Vcc = 2.2 to 2.7 V
Main clock input “L” pulse width Vcc = 2.7 to 4.0 V
Main clock input “L” pulse width Vcc = 2.2 to 2.7 V
CNTR0, CNTR1 input cycle time
125
250
twH(XIN)
twL(XIN)
45
100
40
100
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
2/f(XIN)
tc(CNTR)/2–20
tc(CNTR)/2–20
230
CNTR0, CNTR1 input “H” pulse width
ns
ns
ns
ns
ns
ns
ns
ns
ns
CNTR0, CNTR1 input “L” pulse width
INT0, INT1 input “H” pulse width
twL(INT)
INT0, INT1 input “L” pulse width
230
tc(SCLK)
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input setup time
(Note)
2000
twH(SCLK)
twL(SCLK)
tsu(RxD-SCLK)
th(SCLK-RxD)
(Note)
(Note)
950
950
400
Serial I/O input hold time
200
Note: When bit 6 of address 001A16 is “1”.
Divide this value by four when bit 6 of address 001A16 is “0”.
48
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 20 Timing requirements 2 (One Time PROM version) (Vcc = 2.5 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Reset input “L” pulse width
Unit
Min.
Typ.
Max.
tw(RESET)
tc(XIN)
2
µs
ns
ns
ns
ns
ns
ns
s
Main clock input cycle time (XIN input) Vcc = 2.7 to 4.0 V
Main clock input cycle time (XIN input) Vcc = 2.5 to 2.7 V
Main clock input “H” pulse width Vcc = 2.7 to 4.0 V
Main clock input “H” pulse width Vcc = 2.5 to 2.7 V
Main clock input “L” pulse width Vcc = 2.7 to 4.0 V
Main clock input “L” pulse width Vcc = 2.5 to 2.7 V
CNTR0, CNTR1 input cycle time
125
250
twH(XIN)
twL(XIN)
45
100
40
100
tc(CNTR)
2/f(XIN)
tc(CNTR)/2–20
tc(CNTR)/2–20
230
twH(CNTR)
twL(CNTR)
twH(INT)
CNTR0, CNTR1 input “H” pulse width
ns
ns
ns
ns
ns
ns
ns
ns
ns
CNTR0, CNTR1 input “L” pulse width
INT0, INT1 input “H” pulse width
twL(INT)
INT0, INT1 input “L” pulse width
230
tc(SCLK)
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input setup time
(Note)
2000
twH(SCLK)
twL(SCLK)
tsu(RxD-SCLK)
th(SCLK-RxD)
(Note)
(Note)
950
950
400
Serial I/O input hold time
200
Note: When bit 6 of address 001A16 is “1”.
Divide this value by four when bit 6 of address 001A16 is “0”.
49
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 21 Switching characteristics 1 (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
twH(SCLK)
Parameter
Unit
Min.
Typ.
Max.
140
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
tc(SCLK)/2–30
tc(SCLK)/2–30
ns
ns
ns
ns
ns
ns
ns
ns
twL(SCLK)
td(SCLK-TxD)
tV(SCLK-TxD)
tr(SCLK)
(Note 1)
(Note 1)
Serial I/O output valid time
–30
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time
30
30
30
30
tf(SCLK)
tr(CMOS)
tf(CMOS)
(Note 2)
(Note 2)
10
10
CMOS output falling time
Notes 1: When the P45/TxD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: The XOUT and XCOUT pins are excluded.
Table 22 Switching characteristics 2 (Vcc = 2.2 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
twH(SCLK)
Parameter
Unit
Min.
Typ.
Max.
350
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
tC(SCLK)/2–50
tC(SCLK)/2–50
ns
ns
ns
ns
ns
ns
ns
ns
twL(SCLK)
td(SCLK-TxD)
tV(SCLK-TxD)
tr(SCLK)
(Note 1)
(Note 1)
Serial I/O output valid time
–30
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time
50
50
50
50
tf(SCLK)
tr(CMOS)
tf(CMOS)
(Note 2)
(Note 2)
20
20
CMOS output falling time
Notes 1: When the P45/TxD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: The XOUT and XCOUT pins are excluded.
1 kΩ
Measurement output pin
Measurement output pin
100 pF
100 pF
CMOS output
N-channel open-drain output (Note)
Note: When bit 4 of the UART control register
(address 001B16) is “1”. (N-channel open-
drain output mode)
Fig. 46 Circuit for measuring output switching characteristics
50
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
0.8VCC
CNTR0, CNTR1
0.2VCC
tWL(INT)
tWH(INT)
INT0, INT
1
0.8VCC
0.2VCC
tW(RESET)
0.8VCC
RESET
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
X
S
IN
0.2VCC
tC(SCLK)
tr
tf
tWL(SCLK)
tWH(SCLK)
0.8VCC
CLK
0.2VCC
tsu(RXD-SCLK)
th(SCLK-RXD)
0.8VCC
0.2VCC
R
X
D
td(SCLK-TXD)
tv(SCLK-TXD)
T
X
D
Fig. 47 Timing diagram
51
MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
MMP
144P6Q-A
Plastic 144pin 20✕20mm body LQFP
EIAJ Package Code
JEDEC Code
–
Weight(g)
1.23
Lead Material
Cu Alloy
M
D
LQFP144-P-2020-0.50
HD
D
144
109
l2
1
108
Recommended Mount Pad
Dimension in Millimeters
Symbol
A
Min
–
Nom
–
Max
1.7
0.2
–
A
A
1
0.05
–
0.125
1.4
2
b
0.17
0.105
19.9
19.9
–
0.22
0.125
20.0
20.0
0.5
0.27
0.175
20.1
20.1
–
c
D
E
e
36
73
H
H
L
D
21.8
21.8
0.35
–
0.45
–
–
–
0°
22.0
22.0
0.5
1.0
0.6
0.25
–
–
22.2
22.2
0.65
–
0.75
–
0.08
0.1
8°
E
37
72
A
L1
L1
F
Lp
A3
x
e
y
–
b
2
–
0.95
–
0.225
–
20.4
20.4
–
–
–
–
b
L
y
x
M
I
2
Lp
Detail F
M
M
D
E
–
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•
•
•
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rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
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contained in these materials.
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•
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
© 2002MITSUBISHI ELECTRIC CORP.
New publication, effective Oct. 2002.
Specifications subject to change without notice.
REVISION HISTORY
38C8 GROUP DATA SHEET
Rev.
Date
Description
Summary
Page
First Edition
1.0
1.1
01/18/01
03/21/01
2
3
Figure 1 is partly revised.
Figure 2 is partly revised.
4
Pin name into Table 1 is partly revised.
14
17
26
33
34
37
37
Pin name into Table 5 is partly revised.
Explanations of “Interrupt Operation” are partly eliminated.
Address of [Baud Rate Generator (BRG)] is revised.
Figure name of Figure 31 is partly revised.
Figure name of Figure 32 is partly revised.
Explanations of “CLOCK GENERATING CIRCUIT” are partly revised.
Explanations of “(1) Middle-speed Mode” of “Frequency Control” are partly re-
vised.
40
41
42
42
“At STP Instruction Release” is eliminated.
Explanations of “DATA REQUIRED FOR MASK ORDERS” are partly revised.
Pin name of VIA into Table 11 is revised.
Limits of VIH, VIL of P40, P43 are revised.
1.2
10/15/01
3
Figure 2 is partly revised.
15
16
41
42
43
43
43
43
43
46
46
47
Figure 11 is partly revised.
Figure 12 is partly revised.
Table 10 is added.
Vcc parameter into Table 12 is partly eliminated.
Unit of f(CNTR0), f(CNTR1) into Table 13 is revised.
Limits of f(XIN) in high-speed mode (2.2 V ≤ Vcc < 4.0 V) into Table 13 is revised.
f(XIN) in middle-speed mode (2.2 V ≤ Vcc < 2.7 V) into Table 13 is added.
Unit of f(CNTR0), f(CNTR1) into Table 14 is revised.
f(XIN) in middle-speed mode (2.5 V ≤ Vcc < 2.7 V) into Table 14 is added.
Limits of tc(XIN), tWH(XIN), tWL(XIN) into Table 19 are added.
Limits and unit of tc(CNTR) into Table 19 are revised.
Table 20 is added.
1.3
12/05/01
3
Figure 2 is partly revised.
14
17
18
28
28
28
40
Table 5 is partly revised.
Explanations of “■Notes on interrupts” are partly revised.
Figure 14 is partly revised.
Explanations of “[A-D Control Register (ADCON)]” are partly revised.
Explanations of “Comparator and Control Circuit” are partly revised.
Figure 25 is partly revised.
Explanations of “A-D Converter” of “NOTES ON PROGRAMMING” are partly re-
vised.
1.4
06/25/02 All pages Preliminary Notice in the header is eliminated.
1
3
Interrupts of “[FEATURES]” are corrected.
Figure 2 is partly revised.
4
6
Pin COM0–COM15 in Table 1 is revised.
Figure 4 is partly revised.
8
9
10
11
14
Note in Figure 4 is partly revised.
Explanations of bit 3 are added.
Bit 4 name in Figure 7 is revised.
Remarks in Figure 7 are partly revised.
Table 5 is partly revised.
(1/2)
REVISION HISTORY
38C8 GROUP DATA SHEET
Rev.
1.4
Date
Description
Page
Summary
06/25/02 15
(1) in Figure 11 is partly revised.
17
19
20
20
21
25
30
31
31
32
35
37
38
39
40
Some source numbers in “[INTERRUPTS]” are corrected.
Figure 15 is partly revised.
The mode name (buzzer output mode) in Figure 16 is corrected.The mode name
of bit 6 in Figure 17 is corrected.
Explanations of “[(2) Buzzer Output Mode]” are partly added.
f(XCIN) in Figure 22 is added.
Explanations of “[LC2]” are partly revised.
Explanations of “[Bias Control]” and “[Voltage Multiplier]” are partly revised.
Table 8 is partly revised.
Explanations of “[LCD Display RAM]” is partly revised.
Note in Figure 33 is eliminated.
Explanations of “[(1) Stop Mode]” is partly revised.
Note in Figure 38 is partly revised.
Bit 4 name in Figure 39 is revised.
Explanations of “[A-D Converter]” is partly revised.
“[NOTES ON USE]” is added.
41, 42
44
46
47
Table 12 is partly revised.
Table 15 is partly revised.
Table 16 is partly revised.
1.5
10/23/02 15
(3), (4) and (5) in Figure 11 are partly revised.
(2/2)
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