M38B59EFFS [RENESAS]
8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES; 8位单片机系列740 / 38000系列
| 型号： | M38B59EFFS |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES |
| 文件： | 总356页 (文件大小：3304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 38000 SERIES
38B5
Group
User’s Manual
keep safety first in your circuit designs !
● Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury,
fire or property damage. Remember to give due consideration to safety when
making your circuit designs, with appropriate measures such as (i) placement
of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention
against any malfunction or mishap.
Notes regarding these materials
● These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the customer’s
application; they do not convey any license under any intellectual property rights,
or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
● Mitsubishi Electric Corporation assumes no responsibility for any damage, or
infringement of any third-party’s rights, originating in the use of any product
data, diagrams, charts or circuit application examples contained in these materials.
● All information contained in these materials, including product data, diagrams
and charts, represent information on products at the time of publication of these
materials, and are subject to change by Mitsubishi Electric Corporation without
notice due to product improvements or other reasons. It is therefore recommended
that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for the latest product information before
purchasing a product listed herein.
● Mitsubishi Electric Corporation semiconductors are not designed or manufactured
for use in a device or system that is used under circumstances in which human
life is potentially at stake. Please contact Mitsubishi Electric Corporation or an
authorized Mitsubishi Semiconductor product distributor when considering the
use of a product contained herein for any specific purposes, such as apparatus
or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea
repeater use.
● The prior written approval of Mitsubishi Electric Corporation is necessary to
reprint or reproduce in whole or in part these materials.
● If these products or technologies are subject to the Japanese export control
restrictions, they must be exported under a license from the Japanese government
and cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of
JAPAN and/or the country of destination is prohibited.
● Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or the
products contained therein.
Preface
This user’s manual describes Mitsubishi’s CMOS 8-
bit microcomputers 38B5 Group.
After reading this manual, the user should have a
through knowledge of the functions and features of
the 38B5 Group, and should be able to fully utilize
the product. The manual starts with specifications
and ends with application examples.
For details of software, refer to the “740 Family
Software Manual.”
For details of development support tools, refer to the
“DEVELOPMENT SUPPORT TOOLS FOR
MICROCOMPUTERS” data book.
BEFORE USING THIS USER’S MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development.
1. Organization
● CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
● CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on
setting examples of relevant registers.
● CHAPTER 3 APPENDIX
This chapter includes a list of registers, and necessary information for systems development using
the microcomputer, the mask ROM confirmation (for mask ROM version), ROM programming confirmation,
and the mark specifications which are to be submitted when ordering.
2. Structure of Register
The figure of each register structure describes its functions, contents at reset, and attributes as follows:
(Note 2)
Bit attributes
Bits
(Note 1)
Contents immediately after reset release
b7 b6 b5 b4 b3 b2 b1 b0
0
CPU mode register (CPUM) [Address : 3B 16
]
At reset
b
0
1
2
Name
Functions
R W
b1 b0
0 0 : Single-chip mode
0 1 :
Processor mode bits
0
0
0
Not available
1 0 :
1 1 :
0 : 0 page
1 : 1 page
Stack page selection bit
3
4
5
✕
✕
0
0
0
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
Fix this bit to “0.”
b7 b6
0 0 : φ = XIN/2 (High-speed mode)
0 1 : φ = XIN/8 (Middle-speed mode)
1 0 : φ = XIN/8 (Middle-speed mode)
1 1 : φ = XIN (Double-speed mode)
Main clock division ratio selection
bits
1
0
6
7
: Bit in which nothing is arranged
: Bit that is not used for control of the corresponding function
Notes 1: Contents immediately after reset release
0••••••“0” at reset release
1••••••“1” at reset release
Undefined••••••Undefined or reset release
✻
••••••Contents determined by option at reset release
2: Bit attributes••••••The attributes of control register bits are classified into 3 bytes : read-only, write-only
and read and write. In the figure, these attributes are represented as follows :
R••••••Read
W••••••Write
••••••Read enabled
✕••••••Read disabled
••••••Write enabled
✕ ••••••Write disabled
Table of contents
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................ 1-2
FEATURES.................................................................................................................................... 1-2
APPLICATION ................................................................................................................................ 1-2
PIN CONFIGURATION .................................................................................................................. 1-2
FUNCTIONAL BLOCK .................................................................................................................. 1-3
PIN DESCRIPTION ........................................................................................................................ 1-4
PART NUMBERING ....................................................................................................................... 1-6
GROUP EXPANSION .................................................................................................................... 1-7
Memory Type ............................................................................................................................ 1-7
Memory Size ............................................................................................................................. 1-7
Package ..................................................................................................................................... 1-7
FUNCTIONAL DESCRIPTION ...................................................................................................... 1-8
Central Processing Unit (CPU) .............................................................................................. 1-8
Memory .................................................................................................................................... 1-12
I/O Ports .................................................................................................................................. 1-14
Interrupts .................................................................................................................................1-20
Timers ......................................................................................................................................1-23
Serial I/O .................................................................................................................................1-28
FLD Controller ........................................................................................................................1-40
A-D Converter ......................................................................................................................... 1-52
Pulse Width Modulation (PWM) ...........................................................................................1-53
Interrupt Interval Determination Function............................................................................ 1-56
Watchdog Timer ..................................................................................................................... 1-58
Buzzer Output Circucit ..........................................................................................................1-59
Reset Circuit ........................................................................................................................... 1-60
Clock Generating Circuit ....................................................................................................... 1-62
NOTES ON PROGRAMMING..................................................................................................... 1-65
NOTES ON USE ..........................................................................................................................1-65
DATA REQUIRED FOR MASK ORDERS ................................................................................ 1-66
DATA REQUIRED FOR ROM WRITING ORDERS................................................................. 1-66
ROM PROGRAMMING METHOD .............................................................................................. 1-66
MASK OPTION OF PULL-DOWN RESISTOR......................................................................... 1-67
FUNCTIONAL DESCRIPTION SUPPLEMENT ......................................................................... 1-69
CHAPTER 2 APPLICATION
2.1 I/O port ..................................................................................................................................... 2-2
2.1.1 Memory assignment ....................................................................................................... 2-2
2.1.2 Relevant registers .......................................................................................................... 2-3
2.1.3 Terminate unused pins .................................................................................................. 2-6
2.1.4 Notes on use .................................................................................................................. 2-7
2.1.5 Termination of unused pins .......................................................................................... 2-8
2.2 Timer....................................................................................................................................... 2-10
2.2.1 Memory map .................................................................................................................2-10
2.2.2 Relevant registers ........................................................................................................2-11
38B5 Group User’s Manual
i
Table of contents
2.2.3 Timer application examples ........................................................................................ 2-19
2.3 Serial I/O................................................................................................................................ 2-35
2.3.1 Memory map ................................................................................................................. 2-35
2.3.2 Relevant registers ........................................................................................................ 2-36
2.3.3 Serial I/O1 connection examples ............................................................................... 2-47
2.3.4 Serial I/O1’s modes ..................................................................................................... 2-49
2.3.5 Serial I/O1 application examples ............................................................................... 2-50
2.3.6 Serial I/O2 connection examples ............................................................................... 2-56
2.3.7 Serial I/O2’s modes ..................................................................................................... 2-58
2.3.8 Serial I/O2 application examples ............................................................................... 2-59
2.3.9 Notes on serial I/O1 .................................................................................................... 2-78
2.3.10 Notes on serial I/O2 .................................................................................................. 2-80
2.4 FLD controller ...................................................................................................................... 2-83
2.4.1 Memory assignment ..................................................................................................... 2-83
2.4.2 Relevant registers ........................................................................................................ 2-84
2.4.3 FLD controller application examples ......................................................................... 2-93
2.4.4 Notes on use ..............................................................................................................2-124
2.5 A-D converter .....................................................................................................................2-125
2.5.1 Memory assignment ...................................................................................................2-125
2.5.2 Relevant registers ......................................................................................................2-125
2.5.3 A-D converter application examples........................................................................2-129
2.5.4 Notes on use ..............................................................................................................2-131
2.6 PWM......................................................................................................................................2-132
2.6.1 Memory assignment ...................................................................................................2-132
2.6.2 Relevant registers ......................................................................................................2-132
2.6.3 PWM application example......................................................................................... 2-134
2.6.4 Notes on use ..............................................................................................................2-135
2.7 Interrupt interval determination function.....................................................................2-136
2.7.1 Memory assignment ...................................................................................................2-136
2.7.2 Relevant registers ......................................................................................................2-136
2.7.3 Interrupt interval determination function application examples............................ 2-140
2.8 Watchdog timer.................................................................................................................. 2-144
2.8.1 Memory assignment ...................................................................................................2-144
2.8.2 Relevant register ........................................................................................................2-144
2.8.3 Watchdog timer application examples.....................................................................2-145
2.8.4 Notes on use ..............................................................................................................2-146
2.9 Buzzer output circuit ........................................................................................................2-147
2.9.1 Memory assignment ...................................................................................................2-147
2.9.2 Relevant register ........................................................................................................2-147
2.9.3 Buzzer output circuit application examples ............................................................2-148
2.10 Reset circuit .....................................................................................................................2-149
2.10.1 Connection example of reset IC ............................................................................2-149
2.10.2 Notes on use ............................................................................................................2-150
2.11 Clock generating circuit ................................................................................................2-151
2.11.1 Relevant register ......................................................................................................2-151
2.11.2 Clock generating circuit application examples .....................................................2-152
38B5 Group User’s Manual
ii
Table of contents
CHAPTER 3 APPENDIX
3.1 Electrical characteristics ..................................................................................................... 3-2
3.1.1 Absolute maximum ratings............................................................................................ 3-2
3.1.2 Recommended operating conditions............................................................................ 3-3
3.1.3 Electrical characteristics ................................................................................................ 3-4
3.1.4 A-D converter characteristics ....................................................................................... 3-5
3.1.5 Timing requirements and switching characteristics ................................................... 3-6
3.2 Standard characteristics ...................................................................................................... 3-8
3.2.1 Power source current standard characteristics.......................................................... 3-8
3.2.2 Port standard characteristics ........................................................................................ 3-9
3.2.3 A-D conversion standard characteristics................................................................... 3-13
3.3 Notes on use ........................................................................................................................ 3-14
3.3.1 Notes on interrupts ...................................................................................................... 3-14
3.3.2 Notes on serial I/O1 .................................................................................................... 3-15
3.3.3 Notes on serial I/O2 .................................................................................................... 3-16
3.3.4 Notes on FLD controller.............................................................................................. 3-19
3.3.5 Notes on A-D converter .............................................................................................. 3-19
3.3.6 Notes on PWM ............................................................................................................. 3-19
3.3.7 Notes on watchdog timer ............................................................................................ 3-20
3.3.8 Notes on reset circuit .................................................................................................. 3-20
3.3.9 Notes on input and output pins ................................................................................. 3-20
3.3.10 Notes on programming.............................................................................................. 3-22
3.3.11 Programming and test of built-in PROM version................................................... 3-23
3.3.12 Notes on built-in PROM version .............................................................................. 3-24
3.3.13 Termination of unused pins ...................................................................................... 3-25
3.4 Countermeasures against noise ...................................................................................... 3-26
3.4.1 Shortest wiring length .................................................................................................. 3-26
3.4.2 Connection of bypass capacitor across VSS line and VCC line............................... 3-28
3.4.3 Wiring to analog input pins ........................................................................................ 3-29
3.4.4 Oscillator concerns....................................................................................................... 3-29
3.4.5 Setup for I/O ports....................................................................................................... 3-31
3.4.6 Providing of watchdog timer function by software .................................................. 3-32
3.5 Control registers.................................................................................................................. 3-33
3.6 Mask ROM confirmation form........................................................................................... 3-67
3.7 ROM programming confirmation form............................................................................ 3-75
3.8 Mark specification form ..................................................................................................... 3-77
3.9 Package outline ................................................................................................................... 3-78
3.10 List of instruction code ................................................................................................... 3-79
3.11 Machine instructions ........................................................................................................ 3-80
3.12 M35501FP ............................................................................................................................ 3-91
3.13 SFR memory map............................................................................................................3-103
3.14 Pin configuration .............................................................................................................3-104
38B5 Group User’s Manual
iii
List of figures
List of figures
CHAPTER 1 HARDWARE
Fig. 1 Pin configuration of M38B5xMxH-XXXXFP ..................................................................... 1-2
Fig. 2 Functional block diagram................................................................................................... 1-3
Fig. 3 Part numbering.................................................................................................................... 1-6
Fig. 4 Memory expansion plan..................................................................................................... 1-7
Fig. 5 740 Family CPU register structure................................................................................... 1-8
Fig. 6 Register push and pop at interrupt generation and subroutine call ........................... 1-9
Fig. 7 Structure of CPU mode register ..................................................................................... 1-11
Fig. 8 Memory map diagram ......................................................................................................1-12
Fig. 9 Memory map of special function register (SFR) .......................................................... 1-13
Fig. 10 Structure of pull-up control registers (PULL1 and PULL2) ...................................... 1-14
Fig. 11 Port block diagram (1) ................................................................................................... 1-17
Fig. 12 Port block diagram (2) ................................................................................................... 1-18
Fig. 13 Port block diagram (3) ................................................................................................... 1-19
Fig. 14 Interrupt control...............................................................................................................1-22
Fig. 15 Structure of interrupt related registers ........................................................................ 1-22
Fig. 16 Structure of timer related register ................................................................................ 1-23
Fig. 17 Block diagram of timer .................................................................................................. 1-24
Fig. 18 Timing chart of timer 6 PWM mode ...........................................................................1-25
1
Fig. 19 Block diagram of timer X .............................................................................................. 1-27
Fig. 20 Structure of timer X related registers .......................................................................... 1-27
Fig. 21 Block diagram of serial I/O1 ......................................................................................... 1-28
Fig. 22 Structure of serail I/O1 control registers 1, 2 ............................................................ 1-29
Fig. 23 Structure of serial I/O1 control register 3 ................................................................... 1-30
Fig. 24 Structure of serial I/O1 automatic transfer data pointer ...........................................1-31
Fig. 25 Automatic transfer serial I/O operation ....................................................................... 1-32
Fig. 26 SSTB1 output operation ....................................................................................................1-33
Fig. 27 SBUSY1 input operation (internal synchronous clock)................................................... 1-33
Fig. 28 SBUSY1 input operation (external synchronous clock)..................................................1-33
Fig. 29 SBUSY1 output operation (internal synchronous clock, 8-bits serial I/O) ................... 1-34
Fig. 30 SBUSY1 output operation (external synchronous clock, 8-bits serial I/O) ..................1-34
Fig. 31 SBUSY1 output operation in automatic transfer serial I/O mode (internal synchronous
clock, SBUSY1 output function outputs each 1-byte) ................................................... 1-34
Fig. 32 SRDY1 output operation ....................................................................................................1-35
Fig. 33 SRDY1 input operation (internal synchronous clock) ....................................................1-35
Fig. 34 Handshake operation at serial I/O1 mutual connecting (1)...................................... 1-36
Fig. 35 Handshake operation at serial I/O1 mutual connecting (2)...................................... 1-36
Fig. 36 Block diagram of clock snchronous serial I/O2 ......................................................... 1-37
Fig. 37 Operation of clock synchronous serial I/O2 function ................................................ 1-37
Fig. 38 Block diagram of UART serial I/O2 .............................................................................1-38
Fig. 39 Operation of UART serial I/O2 function ......................................................................1-38
Fig. 40 Structure of serial I/O2 related register ......................................................................1-39
Fig. 41 Block diagram for FLD control circuit.......................................................................... 1-40
Fig. 42 Structure of FLDC mode register ................................................................................. 1-41
Fig. 43 Segment/Digit setting example ..................................................................................... 1-42
Fig. 44 FLD automatic display RAM assignment ....................................................................1-43
Fig. 45 Example of using FLD automatic display RAM in 16-timing•ordinary mode .........1-44
38B5 Group User’s Manual
i
List of figures
Fig. 46 Example of using FLD automatic display RAM in 16-timing•gradation display mode
........................................................................................................................................................ 1-45
Fig. 47 Example of using FLD automatic display RAM in 32-timing mode......................... 1-46
Fig. 48 Structure of FLDRAM write disable register............................................................... 1-47
Fig. 49 Example of digit timing using grid scan type............................................................. 1-48
Fig. 50 Example of using FLD automatic display RAM using grid scan type .................... 1-48
Fig. 51 FLDC timing .................................................................................................................... 1-50
Fig. 52 P8
4
to P8 FLD output waveform ................................................................................. 1-51
7
Fig. 53 Structure of port P8 FLD output control register ....................................................... 1-51
Fig. 54 Structure of A-D control register .................................................................................. 1-52
Fig. 55 Black diagram of A-D converter ................................................................................... 1-52
Fig. 56 PWM block diagram ....................................................................................................... 1-53
Fig. 57 PWM timing ..................................................................................................................... 1-54
Fig. 58 Structure of PWM control register ............................................................................... 1-55
Fig. 59 14-bit PWM timing .......................................................................................................... 1-55
Fig. 60 Interrupt interval determination circuit block diagram ............................................... 1-56
Fig. 61 Structure of itnerrupt interval determination control register.................................... 1-57
Fig. 62 Interrupt inteval determination operation example (at rising edge active) ............. 1-57
Fig. 63 Interrupt interval determination operation example (at both-sided edge active) ... 1-57
Fig. 64 Block diagram of watchdog timer................................................................................. 1-58
Fig. 65 Structure of watchdog timer control register .............................................................. 1-58
Fig. 66 Block diagram of buzzer output circuit........................................................................ 1-59
Fig. 67 Structure of buzzer output control register ................................................................ 1-59
Fig. 68 Reset circuit example .................................................................................................... 1-60
Fig. 69 Reset sequence .............................................................................................................. 1-60
Fig. 70 Internal status at reset .................................................................................................. 1-61
Fig. 71 Ceramic resonator circuit .............................................................................................. 1-62
Fig. 72 External clock input circuit ............................................................................................ 1-62
Fig. 73 Clock generating circuit block diagram ....................................................................... 1-63
Fig. 74 State transitions of system clock ................................................................................. 1-64
Fig. 75 Programming and testing of One Time PROM version ............................................ 1-66
Fig. 76 Digit timing waveform (1) .............................................................................................. 1-67
Fig. 77 Digit timing waveform (2) .............................................................................................. 1-68
Fig. 78 Timing chart after interrupt occurs............................................................................... 1-70
Fig. 79 TIme up to execution of interrupt processing routine ............................................... 1-70
Fig. 80 A-D conversion equivalent circuit................................................................................. 1-72
Fig. 81 A-D conversion timing chart.......................................................................................... 1-72
CHAPTER 2 APPLICATION
Fig. 2.1.1 Memory assignment of I/O port relevant registers.................................................. 2-2
Fig. 2.1.2 Structure of port Pi (i = 0, 1, 2, 3, 4, 5, 7, 8) ........................................................ 2-3
Fig. 2.1.3 Structure of port P6 ..................................................................................................... 2-3
Fig. 2.1.4 Structure of port P9 ..................................................................................................... 2-3
Fig. 2.1.5 Structure of port Pi (i = 0, 2, 4, 5, 7, 8) direction register ................................... 2-4
Fig. 2.1.6 Structure of port P6 direction register ...................................................................... 2-4
Fig. 2.1.7 Structure of port P9 direction register ...................................................................... 2-5
Fig. 2.1.8 Structure of pull-up control register 1 ....................................................................... 2-5
Fig. 2.1.9 Structure of pull-up control register 2 ....................................................................... 2-6
Fig. 2.2.1 Memory map of registers relevant to timers .......................................................... 2-10
38B5 Group User’s Manual
ii
List of figures
Fig. 2.2.2 Structure of Timer i (i=1, 3, 4, 5, 6) ....................................................................... 2-11
Fig. 2.2.3 Structure of Timer 2 .................................................................................................. 2-11
Fig. 2.2.4 Structure of Timer 6 PWM register ......................................................................... 2-11
Fig. 2.2.5 Structure of Timer 12 mode register ....................................................................... 2-12
Fig. 2.2.6 Structure of Timer 34 mode register ....................................................................... 2-12
Fig. 2.2.7 Structure of Timer 56 mode register ....................................................................... 2-13
Fig. 2.2.8 Structure of Timer X (low-order, high-order).......................................................... 2-13
Fig. 2.2.9 Structure of Timer X mode register 1 ..................................................................... 2-14
Fig. 2.2.10 Structure of Timer X mode register 2................................................................... 2-15
Fig. 2.2.11 Structure of Interrupt request register 1 ............................................................... 2-16
Fig. 2.2.12 Structure of Interrupt request register 2 ............................................................... 2-17
Fig. 2.2.13 Structure of Interrupt control register 1 ................................................................ 2-18
Fig. 2.2.14 Structure of Interrupt control register 2 ................................................................ 2-18
Fig. 2.2.15 Timers connection and setting of division ratios ................................................. 2-20
Fig. 2.2.16 Relevant registers setting ....................................................................................... 2-21
Fig. 2.2.17 Control procedure..................................................................................................... 2-22
Fig. 2.2.18 Peripheral circuit example....................................................................................... 2-23
Fig. 2.2.19 Timers connection and setting of division ratios ................................................. 2-23
Fig. 2.2.20 Relevant registers setting ....................................................................................... 2-24
Fig. 2.2.21 Control procedure..................................................................................................... 2-24
Fig. 2.2.22 Judgment method of valid/invalid of input pulses ............................................... 2-25
Fig. 2.2.23 Relevant registers setting ....................................................................................... 2-26
Fig. 2.2.24 Control procedure..................................................................................................... 2-27
Fig. 2.2.25 Timers connection and setting of division ratios ................................................. 2-28
Fig. 2.2.26 Relevant registers setting ....................................................................................... 2-29
Fig. 2.2.27 Control procedure..................................................................................................... 2-30
Fig. 2.2.28 Timers connection and table example of timer X/RTP setting values ............. 2-32
Fig. 2.2.29 RTP output example ................................................................................................ 2-32
Fig. 2.2.30 Relevant registers setting ....................................................................................... 2-33
Fig. 2.2.31 Control procedure..................................................................................................... 2-34
Fig. 2.3.1 Memory map of registers relevant to Serial I/O .................................................... 2-35
Fig. 2.3.2 Structure of Serial I/O1 automatic transfer data pointer ...................................... 2-36
Fig. 2.3.3 Structure of Serial I/O1 control register 1 .............................................................. 2-37
Fig. 2.3.4 Structure of Serial I/O1 control register 2 .............................................................. 2-38
Fig. 2.3.5 Structure of Serial I/O1 register/Transfer counter ................................................. 2-39
Fig. 2.3.6 Structure of Serial I/O1 control register 3 .............................................................. 2-40
Fig. 2.3.7 Structure of Baud rate generator............................................................................. 2-41
Fig. 2.3.8 Structure of UART control register .......................................................................... 2-41
Fig. 2.3.9 Structure of Serial I/O2 control register.................................................................. 2-42
Fig. 2.3.10 Structure of Serial I/O2 status register................................................................. 2-43
Fig. 2.3.11 Structure of Serial I/O2 transmit/receive buffer register..................................... 2-43
Fig. 2.3.12 Structure of Interrupt source switch register........................................................ 2-44
Fig. 2.3.13 Structure of Interrupt request register 1 ............................................................... 2-44
Fig. 2.3.14 Structure of Interrupt request register 2 ............................................................... 2-45
Fig. 2.3.15 Structure of Interrupt control register 1 ................................................................ 2-46
Fig. 2.3.16 Structure of Interrupt control register 2 ................................................................ 2-46
Fig. 2.3.17 Serial I/O1 connection examples (1) ..................................................................... 2-47
Fig. 2.3.18 Serial I/O1 connection examples (2) ..................................................................... 2-48
Fig. 2.3.19 Serial I/O1’s modes ................................................................................................. 2-49
Fig. 2.3.20 Connection diagram ................................................................................................. 2-50
Fig. 2.3.21 Timing chart .............................................................................................................. 2-50
38B5 Group User’s Manual
iii
List of figures
Fig. 2.3.22 Registers setting relevant to transmission side ................................................... 2-51
Fig. 2.3.23 Setting of transmission data ................................................................................... 2-51
Fig. 2.3.24 Control procedure..................................................................................................... 2-52
Fig. 2.3.25 Connection diagram ................................................................................................. 2-53
Fig. 2.3.26 Timing chart of serial data transmission/reception.............................................. 2-53
Fig. 2.3.27 Relevant registers setting ....................................................................................... 2-54
Fig. 2.3.28 Control procedure..................................................................................................... 2-55
Fig. 2.3.29 Serial I/O2 connection examples (1) ..................................................................... 2-56
Fig. 2.3.30 Serial I/O2 connection examples (2) ..................................................................... 2-57
Fig. 2.3.31 Serial I/O2’s modes ................................................................................................. 2-58
Fig. 2.3.32 Serial I/O2 transfer data format ............................................................................. 2-58
Fig. 2.3.33 Connection diagram ................................................................................................. 2-59
Fig. 2.3.34 Timing chart .............................................................................................................. 2-59
Fig. 2.3.35 Registers setting relevant to transmission side ................................................... 2-60
Fig. 2.3.36 Registers setting relevant to reception side......................................................... 2-61
Fig. 2.3.37 Control procedure of transmission side ................................................................ 2-62
Fig. 2.3.38 Control procedure of reception side ...................................................................... 2-63
Fig. 2.3.39 Connection diagram ................................................................................................. 2-64
Fig. 2.3.40 Timing chart .............................................................................................................. 2-64
Fig. 2.3.41 Relevant registers setting ....................................................................................... 2-65
Fig. 2.3.42 Setting of transmission data ................................................................................... 2-65
Fig. 2.3.43 Control procedure..................................................................................................... 2-66
Fig. 2.3.44 Connection diagram ................................................................................................. 2-67
Fig. 2.3.45 Timing chart .............................................................................................................. 2-68
Fig. 2.3.46 Relevant registers setting in master unit .............................................................. 2-68
Fig. 2.3.47 Relevant registers setting in slave unit ................................................................ 2-69
Fig. 2.3.48 Control procedure of master unit........................................................................... 2-70
Fig. 2.3.49 Control procedure of slave unit ............................................................................. 2-71
Fig. 2.3.50 Connection diagram ................................................................................................. 2-72
Fig. 2.3.51 Timing chart .............................................................................................................. 2-72
Fig. 2.3.52 Registers setting relevant to transmission side ................................................... 2-74
Fig. 2.3.53 Registers setting relevant to reception side......................................................... 2-75
Fig. 2.3.54 Control procedure of transmission side ................................................................ 2-76
Fig. 2.3.55 Control procedure of reception side ...................................................................... 2-77
Fig. 2.3.56 Sequence of setting serial I/O2 control register again....................................... 2-81
Fig. 2.4.1 Memory assignment of FLD controller relevant registers..................................... 2-83
Fig. 2.4.2 Structure of P1FLDRAM write disable register ...................................................... 2-84
Fig. 2.4.3 Structure of P3FLDRAM write disable register ...................................................... 2-85
Fig. 2.4.4 Structure of FLD mode register ............................................................................... 2-86
Fig. 2.4.5 Structure of Tdisp time set register......................................................................... 2-87
Fig. 2.4.6 Structure of Toff1 time set register ......................................................................... 2-88
Fig. 2.4.7 Structure of Toff2 time set register ......................................................................... 2-88
Fig. 2.4.8 Structure of FLD data pointer/FLD data pointer reload register ......................... 2-89
Fig. 2.4.9 Structure of port P0FLD/port switch register.......................................................... 2-89
Fig. 2.4.10 Structure of port P2FLD/port switch register ....................................................... 2-90
Fig. 2.4.11 Structure of port P8FLD/port switch register ....................................................... 2-90
Fig. 2.4.12 Structure of port P8FLD output control register .................................................. 2-91
Fig. 2.4.13 Structure of interrupt request register 2 ............................................................... 2-91
Fig. 2.4.14 Structure of interrupt control register 2 ................................................................ 2-92
Fig. 2.4.15 Connection diagram ................................................................................................. 2-93
Fig. 2.4.16 Timing chart of key-scan using FLD automatic display mode and segments. 2-93
38B5 Group User’s Manual
iv
List of figures
Fig. 2.4.17 Enlarged view of FLD
0
(P2
0
) to FLD
7
(P2
7
) Tscan .............................................. 2-93
Fig. 2.4.18 Setting of relevant registers ................................................................................... 2-94
Fig. 2.4.19 FLD digit allocation example .................................................................................. 2-97
Fig. 2.4.20 Control procedure..................................................................................................... 2-98
Fig. 2.4.21 Connection diagram ...............................................................................................2-100
Fig. 2.4.22 Timing chart of key-scan using FLD automatic display mode and digits ......2-101
Fig. 2.4.23 Setting of relevant registers .................................................................................2-102
Fig. 2.4.24 FLD digit allocation example ................................................................................2-105
Fig. 2.4.25 Control procedure...................................................................................................2-106
Fig. 2.4.26 Connection diagram ...............................................................................................2-108
Fig. 2.4.27 Timing chart of FLD display by software ...........................................................2-108
Fig. 2.4.28 Enlarged view of P2
0
to P2 key-scan ................................................................ 2-108
7
Fig. 2.4.29 Setting of relevant registers .................................................................................2-109
Fig. 2.4.30 FLD digit allocation example ................................................................................2-110
Fig. 2.4.31 Control procedure...................................................................................................2-111
Fig. 2.4.32 Connection diagram ...............................................................................................2-112
Fig. 2.4.33 Timing chart of 38B5 Group and M35501FP .....................................................2-113
Fig. 2.4.34 Timing chart (enlarged view) of digit and segment output .............................. 2-113
Fig. 2.4.35 Setting of relevant registers .................................................................................2-114
Fig. 2.4.36 FLD digit allocation example ................................................................................2-117
Fig. 2.4.37 Control procedure...................................................................................................2-117
Fig. 2.4.38 Connection diagram ...............................................................................................2-118
Fig. 2.4.39 Timing chart (at correct state) of 38B5 Group and M35501FP ......................2-119
Fig. 2.4.40 Timing chart (at incorrect state) of 38B5 Group and M35501FP ................... 2-119
Fig. 2.4.41 Setting of relevant registers .................................................................................2-120
Fig. 2.4.42 Control procedure...................................................................................................2-122
Fig. 2.5.1 Memory assignment of A-D converter relevant registers ...................................2-125
Fig. 2.5.2 Structure of A-D control register............................................................................2-125
Fig. 2.5.3 Structure of A-D conversion register (low-order).................................................2-126
Fig. 2.5.4 Structure of A-D conversion register (high-order) ...............................................2-126
Fig. 2.5.5 Structure of interrupt request register 2 ...............................................................2-127
Fig. 2.5.6 Structure of interrupt control register 2 ................................................................ 2-128
Fig. 2.5.7 Connection diagram .................................................................................................2-129
Fig. 2.5.8 Setting of relevant registers ...................................................................................2-129
Fig. 2.5.9 Control procedure.....................................................................................................2-130
Fig. 2.6.1 Memory assignment of PWM relevant registers ..................................................2-132
Fig. 2.6.2 Structure of PWM register (high-order).................................................................2-132
Fig. 2.6.3 Structure of PWM register (low-order) ..................................................................2-133
Fig. 2.6.4 Structure of PWM control register ......................................................................... 2-133
Fig. 2.6.5 Connection diagram .................................................................................................2-134
Fig. 2.6.6 Setting of relevant registers ...................................................................................2-134
Fig. 2.6.7 Control procedure.....................................................................................................2-135
Fig. 2.6.8 PWM output .............................................................................................................2-135
0
Fig. 2.7.1 Memory assignment of interrupt interval determination function relevant registers
......................................................................................................................................................2-136
Fig. 2.7.2 Structure of interrupt interval determination register...........................................2-136
Fig. 2.7.3 Structure of interrupt interval determination control register .............................2-137
Fig. 2.7.4 Structure of interrupt edge selection register....................................................... 2-137
Fig. 2.7.5 Structure of interrupt request register 1 ...............................................................2-138
Fig. 2.7.6 Structure of interrupt control register 1 ................................................................ 2-139
Fig. 2.7.7 Connection diagram .................................................................................................2-140
38B5 Group User’s Manual
v
List of figures
Fig. 2.7.8 Function block diagram ...........................................................................................2-140
Fig. 2.7.9 Timing chart of data determination........................................................................2-140
Fig. 2.7.10 Setting of relevant registers .................................................................................2-141
Fig. 2.7.11 Control procedure...................................................................................................2-142
Fig. 2.7.12 Reception of remote-control data (timer 2 interrupt) ........................................2-143
Fig. 2.8.1 Memory assignment of watchdog timer relevant register ...................................2-144
Fig. 2.8.2 Structure of watchdog timer control register ........................................................2-144
Fig. 2.8.3 Connection of watchdog timer and setting of division ratio...............................2-145
Fig. 2.8.4 Setting of relevant registers ...................................................................................2-145
Fig. 2.8.5 Control procedure.....................................................................................................2-146
Fig. 2.9.1 Memory assignment of buzzer output circuit relevant register ..........................2-147
Fig. 2.9.2 Structure of buzzer output control register...........................................................2-147
Fig. 2.9.3 Connection of buzzer output circuit and setting of division ratio......................2-148
Fig. 2.9.4 Setting of relevant register .....................................................................................2-148
Fig. 2.9.5 Control procedure.....................................................................................................2-148
Fig. 2.10.1 Example of power-on reset circuit .......................................................................2-149
Fig. 2.10.2 RAM backup system example ..............................................................................2-149
Fig. 2.11.1 Structure of CPU mode register ..........................................................................2-151
Fig. 2.11.2 Connection diagram ...............................................................................................2-152
Fig. 2.11.3 Status transition diagram during power failure ..................................................2-152
Fig. 2.11.4 Setting of relevant registers .................................................................................2-153
Fig. 2.11.5 Control procedure...................................................................................................2-154
Fig. 2.11.6 Structure of clock counter.....................................................................................2-155
Fig. 2.11.7 Initial setting of relevant registers .......................................................................2-156
Fig. 2.11.8 Setting of relevant registers after detecting power failure ...............................2-157
Fig. 2.11.9 Control procedure...................................................................................................2-158
CHAPTER 3 APPENDIX
Fig. 3.1.1 Circuit for measuring output switching characteristics............................................ 3-6
Fig. 3.1.2 Timing diagram .............................................................................................................3-7
Fig. 3.2.1 Power source current standard characteristics ........................................................ 3-8
Fig. 3.2.2 Power source current standard characteristics (in wait mode) ............................. 3-8
Fig. 3.2.3 High-breakdown P-channel open-drain output port characteristics (25 °C)......... 3-9
Fig. 3.2.4 High-breakdown P-channel open-drain output port characteristics (90 °C)......... 3-9
Fig. 3.2.5 CMOS output port P-channel side characteristics (25 °C) .................................. 3-10
Fig. 3.2.6 CMOS output port P-channel side characteristics (90 °C) .................................. 3-10
Fig. 3.2.7 CMOS output port N-channel side characteristics (25 °C) .................................. 3-11
Fig. 3.2.8 CMOS output port N-channel side characteristics (90 °C) .................................. 3-11
Fig. 3.2.9 N-channel open-drain output port characteristics (25 °C).................................... 3-12
Fig. 3.2.10 N-channel open-drain output port characteristics (90 °C).................................. 3-12
Fig. 3.2.11 A-D conversion standard characteristics............................................................... 3-13
Fig. 3.3.1 Sequence of switch detection edge......................................................................... 3-14
Fig. 3.3.2 Sequence of check of interrupt request bit ............................................................ 3-14
Fig. 3.3.3 Structure of interrupt control register 2 .................................................................. 3-15
Fig. 3.3.4 Sequence of setting serial I/O2 control register again......................................... 3-18
Fig. 3.3.5 PWM output ................................................................................................................ 3-19
Fig. 3.3.6 Initialization of processor status register ................................................................ 3-22
Fig. 3.3.7 Sequence of PLP instruction execution .................................................................. 3-22
Fig. 3.3.8 Stack memory contents after PHP instruction execution ..................................... 3-22
38B5 Group User’s Manual
vi
List of figures
Fig. 3.3.9 Status flag at decimal calculations .......................................................................... 3-23
Fig. 3.3.10 Programming and testing of One Time PROM version ...................................... 3-23
Fig. 3.4.1 Selection of packages ............................................................................................... 3-26
Fig. 3.4.2 Wiring for the RESET pin ......................................................................................... 3-26
Fig. 3.4.3 Wiring for clock I/O pins ........................................................................................... 3-27
Fig. 3.4.4 Wiring for the VPP pin of the One Time PROM and the EPROM version ......... 3-28
Fig. 3.4.5 Bypass capacitor across the VSS line and the VCC line ........................................ 3-28
Fig. 3.4.6 Analog signal line and a resistor and a capacitor ................................................ 3-29
Fig. 3.4.7 Wiring for a large current signal line ...................................................................... 3-29
Fig. 3.4.8 Wiring of signal lines where potential levels change frequently ......................... 3-30
Fig. 3.4.9 VSS pattern on the underside of an oscillator ........................................................ 3-30
Fig. 3.4.10 Setup for I/O ports................................................................................................... 3-31
Fig. 3.4.11 Watchdog timer by software ................................................................................... 3-32
Fig. 3.5.1 Structure of port Pi .................................................................................................... 3-33
Fig. 3.5.2 Structure of port Pi direction register...................................................................... 3-33
Fig. 3.5.3 Structure of port P6 ................................................................................................... 3-34
Fig. 3.5.4 Structure of port P6 direction register .................................................................... 3-34
Fig. 3.5.5 Structure of port P9 ................................................................................................... 3-35
Fig. 3.5.6 Structure of port P9 direction register .................................................................... 3-35
Fig. 3.5.7 Structure of PWM register (high-order)................................................................... 3-36
Fig. 3.5.8 Structure of PWM register (low-order) .................................................................... 3-36
Fig. 3.5.9 Structure of baud rate generator ............................................................................. 3-37
Fig. 3.5.10 Structure of UART control register ........................................................................ 3-37
Fig. 3.5.11 Structure of serial I/O1 automatic transfer data pointer..................................... 3-38
Fig. 3.5.12 Structure of serial I/O1 control register 1 ............................................................ 3-38
Fig. 3.5.13 Structure of serial I/O1 control register 2 ............................................................ 3-39
Fig. 3.5.14 Structure of serial I/O1 register/Transfer counter................................................ 3-40
Fig. 3.5.15 Structure of serial I/O1 control register 3 ............................................................ 3-41
Fig. 3.5.16 Structure of serial I/O2 control register ................................................................ 3-42
Fig. 3.5.17 Structure of serial I/O2 status register ................................................................. 3-43
Fig. 3.5.18 Structure of serial I/O2 transmit/receive buffer register ..................................... 3-43
Fig. 3.5.19 Structure of timer i................................................................................................... 3-44
Fig. 3.5.20 Structure of timer 2 ................................................................................................. 3-44
Fig. 3.5.21 Structure of PWM control register ......................................................................... 3-44
Fig. 3.5.22 Structure of timer 6 PWM register ........................................................................ 3-45
Fig. 3.5.23 Structure of timer 12 mode register ...................................................................... 3-45
Fig. 3.5.24 Structure of timer 34 mode register ...................................................................... 3-46
Fig. 3.5.25 Structure of timer 56 mode register ...................................................................... 3-46
Fig. 3.5.26 Structure of watchdog timer control register ........................................................ 3-47
Fig. 3.5.27 Structure of timer X (low-order, high-order)......................................................... 3-47
Fig. 3.5.28 Structure of timer X mode register 1 .................................................................... 3-48
Fig. 3.5.29 Structure of timer X mode register 2 .................................................................... 3-49
Fig. 3.5.30 Structure of interrupt interval determination register .......................................... 3-49
Fig. 3.5.31 Structure of interrupt interval determination control register ............................. 3-50
Fig. 3.5.32 Structure of A-D control register............................................................................ 3-50
Fig. 3.5.33 Structure of A-D conversion register (low-order)................................................. 3-51
Fig. 3.5.34 Structure of A-D conversion register (high-order) ............................................... 3-51
Fig. 3.5.35 Structure of interrupt source switch register ........................................................ 3-52
Fig. 3.5.36 Structure of interrupt edge selection register ...................................................... 3-52
Fig. 3.5.37 Structure of CPU mode register ............................................................................ 3-53
Fig. 3.5.38 Structure of interrupt request register 1 ............................................................... 3-54
38B5 Group User’s Manual
vii
List of figures
Fig. 3.5.39 Structure of interrupt request register 2 ............................................................... 3-55
Fig. 3.5.40 Structure of interrupt control register 1 ................................................................ 3-56
Fig. 3.5.41 Structure of interrupt control register 2 ................................................................ 3-57
Fig. 3.5.42 Structure of pull-up control register 1 ................................................................... 3-58
Fig. 3.5.43 Structure of pull-up control register 2 ................................................................... 3-58
Fig. 3.5.44 Structure of P1FLDRAM write disable register .................................................... 3-59
Fig. 3.5.45 Structure of P3FLDRAM write disable register .................................................... 3-60
Fig. 3.5.46 Structure of FLDC mode register .......................................................................... 3-61
Fig. 3.5.47 Structure of Tdisp time set register ...................................................................... 3-62
Fig. 3.5.48 Structure of Toff1 time set register ....................................................................... 3-63
Fig. 3.5.49 Structure of Toff2 time set register ....................................................................... 3-63
Fig. 3.5.50 Structure of FLD data pointer/FLD data pointer reload register ....................... 3-64
Fig. 3.5.51 Structure of port P0FLD/Port switch register ....................................................... 3-64
Fig. 3.5.52 Structure of port P2FLD/port switch register ....................................................... 3-65
Fig. 3.5.53 Structure of port P8FLD/port switch register ....................................................... 3-65
Fig. 3.5.54 Structure of port P8FLD output control register .................................................. 3-66
Fig. 3.5.55 Structure of buzzer output control register........................................................... 3-66
Fig. 3.12.1 Pin configuration of M35501FP.............................................................................. 3-91
Fig. 3.12.2 Functional block diagram ........................................................................................ 3-92
Fig. 3.12.3 Port block diagram................................................................................................... 3-93
Fig. 3.12.4 Digit setting ............................................................................................................... 3-94
Fig. 3.12.5 16-digit mode output waveform.............................................................................. 3-95
Fig. 3.12.6 Optional digit mode output waveform ................................................................... 3-95
Fig. 3.12.7 Cascade mode connection example: 17 digits or more selected ..................... 3-96
Fig. 3.12.8 Cascade mode output waveform ........................................................................... 3-96
Fig. 3.12.9 Connection example with 38B5 Group microcomputer (1 to 16 digits) ........... 3-97
Fig. 3.12.10 Connection example with 38B5 Group microccomputer (17 to 32 digits) ..... 3-97
Fig. 3.12.11 Digit output waveform when reset signal is input ............................................. 3-98
Fig. 3.12.12 Power-on reset circuit ........................................................................................... 3-99
Fig. 3.12.13 Timing diagram.....................................................................................................3-102
38B5 Group User’s Manual
viii
List of tables
List of tables
CHAPTER 1 HARDWARE
Table 1 Pin description (1) ........................................................................................................... 1-4
Table 2 Pin description (2) ........................................................................................................... 1-5
Table 3 List of supported products ............................................................................................. 1-7
Table 4 Push and pop instructions of accumulator or processor status register ................. 1-9
Table 5 Set and clear instructions of each bit of processor status register....................... 1-10
Table 6 List of I/O port functions (1) ........................................................................................ 1-15
Table 7 List of I/O port functions (2) ........................................................................................ 1-16
Table 8 Interrupt vector addresses and priority ...................................................................... 1-21
Table 9 Pins in FLD automatic display mode.......................................................................... 1-42
Table 10 Relationship between low-order 6-bit data and setting period of ADD bit ......... 1-54
Table 11 Special programming adapter .................................................................................... 1-66
Table 12 Mask option type of pull-down resistor .................................................................... 1-67
Table 13 Interrupt sources, vector addresses and interrupt priority..................................... 1-69
Table 14 Relative formula for a refernece voltage VREF of A-D converter and Vref ..................... 1-71
Table 15 Change of A-D conversion register during A-D conversion .................................. 1-71
CHAPTER 2 APPLICATION
Table 2.1.1 Termination of unused pins ..................................................................................... 2-6
Table 2.3.1 Setting examples of baud rate generator values and transfer bit rate values
........................................................................................................................................................ 2-73
Table 2.4.1 FLD automatic display RAM map ......................................................................... 2-96
Table 2.4.2 FLD automatic display RAM map example ......................................................... 2-97
Table 2.4.3 FLD automatic display RAM map .......................................................................2-104
Table 2.4.4 FLD automatic display RAM map example ....................................................... 2-105
Table 2.4.5 FLD automatic display RAM map example ....................................................... 2-110
Table 2.4.6 FLD automatic display RAM map .......................................................................2-116
CHAPTER 3 APPENDIX
Table 3.1.1 Absolute maximum ratings ....................................................................................... 3-2
Table 3.1.2 Recommended operating conditions (1) ................................................................ 3-3
Table 3.1.3 Recommended operating conditions (2) ................................................................ 3-4
Table 3.1.4 Electrical characteristics (1)..................................................................................... 3-4
Table 3.1.5 Electrical characteristics (2)..................................................................................... 3-5
Table 3.1.6 A-D converter characteristics .................................................................................. 3-5
Table 3.1.7 Timing requirements ................................................................................................. 3-6
Table 3.1.8 Switching characteristics .......................................................................................... 3-6
Table 3.3.1 Programming adapter ............................................................................................. 3-24
Table 3.3.2 PROM programmer address setting ..................................................................... 3-24
Table 3.12.1 Pin description ....................................................................................................... 3-92
Table 3.12.2 Absolute maximum ratings.................................................................................3-100
Table 3.12.3 Recommended operating conditions.................................................................3-100
Table 3.12.4 Recommended operating conditions.................................................................3-100
Table 3.12.5 Electrical characteristics.....................................................................................3-101
Table 3.12.6 Timing requirements ...........................................................................................3-102
38B5 Group User’s Manual
i
CHAPTER 1
HARDWARE
DESCRIPTION
FEATURES
APPLICATION
PIN CONFIGURATION
FUNCTIONAL BLOCK
PIN DESCRIPTION
PART NUMBERING
GROUP EXPANSION
FUNCTIONAL DESCRIPTION
NOTES ON PROGRAMMING
NOTES ON USE
DATA REQUIRED FOR MASK
ORDERS
DATA REQUIRED FOR ROM WRITING
ORDERS
ROM PROGRAMMING METHOD
MASK OPTION OF PULL-DOWN
RESISTOR
F U N C T I O N A L D E S C R I P T I O N
SUPPLEMENT
HARDWARE
DESCRIPTION/FEATURES/APPLICATION/PIN CONFIGURATION
Serial I/O2 (UART or Clock-synchronized) .................... 8-bit ✕ 1
•
•
DESCRIPTION
PWM ............................................................................ 14-bit ✕ 1
8-bit ✕ 1 (also functions as timer 6)
The 38B5 group is the 8-bit microcomputer based on the 740 family
core technology.
A-D converter .............................................. 10-bit ✕ 12 channels
Fluorescent display function ......................... Total 40 control pins
Interrupt interval determination function ..................................... 1
Watchdog timer ............................................................ 20-bit ✕ 1
Buzzer output ............................................................................. 1
2 Clock generating circuit
•
•
•
•
•
•
The 38B5 group has six 8-bit timers, a 16-bit timer, a fluorescent dis-
play automatic display circuit, 12-channel 10-bit A-D converter, a se-
rial I/O with automatic transfer function, which are available for con-
trolling musical instruments and household appliances.
The 38B5 group has variations of internal memory size and packag-
ing. For details, refer to the section on part numbering.
For details on availability of microcomputers in the 38B5 group, refer
to the section on group expansion.
Main clock (XIN–XOUT) .......................... Internal feedback resistor
Sub-clock (XCIN–XCOUT) .......... Without internal feedback resistor
(connect to external ceramic resonator or quartz-crystal
oscillator)
Built-in pull-down resistors connected to high-breakdown voltage ports
are available by specifying with the mask option in some products. For
the details, refer to the section on the mask option of pull-down resis-
tor.
Power source voltage
•
In high-speed mode ................................................... 4.0 to 5.5 V
(at 4.19 MHz oscillation frequency and high-speed selected)
In middle-speed mode ................................................ 2.7 to 5.5 V
(at 4.19 MHz oscillation frequency and middle-speed selected)
In low-speed mode ..................................................... 2.7 to 5.5 V
(at 32 kHz oscillation frequency)
FEATURES
Basic machine-language instructions....................................... 71
•
•
The minimum instruction execution time .......................... 0.48 µs
(at 4.19 MHz oscillation frequency)
Memory size
•
Power dissipation
•
•
ROM ............................................. 24K to 60K bytes
RAM ..........................................1024 to 2048 bytes
In high-speed mode .......................................................... 35 mW
(at 4.19 MHz oscillation frequency)
Programmable input/output ports ............................................. 55
•
In low-speed mode ............................................................. 60 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
Operating temperature range ................................... –20 to 85 °C
High-breakdown-voltage output ports ...................................... 36
•
Software pull-up resistors....... (PortsP5,P61toP65,P7,P84toP87,P9)
•
Interrupts .................................................. 21 sources, 16 vectors
•
Timers ........................................................... 8-bit ✕ 6, 16-bit ✕ 1
•
APPLICATION
Musical instruments, VCR, household appliances, etc.
Serial I/O1 (Clock-synchronized) ................................... 8-bit ✕ 1
•
...................... (max. 256-byte automatic transfer function)
PIN CONFIGURATION (TOP VIEW)
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P3
P3
P3
P3
P3
P3
P3
P3
P8
P8
P8
P8
0
1
2
3
4
5
6
7
0
1
2
3
/FLD24
/FLD25
/FLD26
/FLD27
/FLD28
/FLD29
/FLD30
/FLD31
/FLD32
/FLD33
/FLD34
/FLD35
P5
7
/SRDY2/
SCLK22
P5
P5
P5
6
/SCLK21
5
/TxD
4
/RxD
P5
3
/SCLK12
/SCLK11
P52
P51
/SOUT1
/SIN1
AVSS
REF
/SSTB1/AN11
/SBUSY1/AN10
P5
0
M38B5xMxH-XXXXFP
V
P6
/INT
5
P64
4
VEE
P6
3
/AN
9
8
7
6
P84
P85
P86
/FLD36
P6
2/SRDY1/AN
P7
P7
/RTP
/RTP
0
/FLD37
/FLD38
7
6
/AN
/AN
1
Note: In the mask option type P, INT
3
and CNTR
1
cannot be used.
Package type : 80P6N-A
80-pin plastic-molded QFP
Fig. 1 Pin configuration of M38B5xMxH-XXXXFP
38B5 Group User’s Manual
1-2
HARDWARE
FUNCTIONAL BLOCK
FUNCTIONAL BLOCK
Fig. 2 Functional block diagram
38B5 Group User’s Manual
1-3
HARDWARE
PIN DESCRIPTION
PIN DESCRIPTION
Table 1 Pin description (1)
Pin
Name
Function
Function except a port function
VCC, VSS
VEE
Power source
Pull-down
power source
Reference
voltage
• Apply voltage of 4.0–5.5 V to VCC, and 0 V to VSS.
• Apply voltage supplied to pull-down resistors of ports P0, P1, and P3.
VREF
AVSS
• Reference voltage input pin for A-D converter.
Analog power
source
• Analog power source input pin for A-D converter.
• Connect to VSS.
______
RESET
Reset input
Clock input
• Reset input pin for active “L.”
XIN
• Input and output pins for the main clock generating circuit.
• Feedback resistor is built in between XIN pin and XOUT pin.
• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the
oscillation frequency.
XOUT
Clock output
• When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• The clock is used as the oscillating source of system clock.
P00/FLD8– I/O port P0
P07/FLD15
• 8-bit I/O port.
• FLD automatic display
• I/O direction register allows each pin to be individually programmed as either pins
input or output.
• At reset, this port is set to input mode.
• A pull-down resistor is built in between port P0 and the VEE pin.
• CMOS compatible input level.
• High-breakdown-voltage P-channel open-drain output structure.
• At reset, this port is set to VEE level.
P10/FLD16– Output port P1
P17/FLD23
• 8-bit output port.
• FLD automatic display
• A pull-down resistor is built in between port P1 and the VEE pin.
• High-breakdown-voltage P-channel open-drain output structure.
• At reset, this port is set to VEE level.
pins
P20/BUZ02/ I/O port P2
FLD0–
• 8-bit I/O port with the same function as port P0.
• Low-voltage input level.
• FLD automatic display
pins
P27/FLD7
• High-breakdown-voltage P-channel open-drain output structure.
• 8-bit output port.
• Buzzer output pin (P20)
• FLD automatic display
pins
P30/FLD24– Output port P3
P37/FLD31
• A pull-down resistor is built in between port P3 and the VEE pin.
• High-breakdown-voltage P-channel open-drain output structure.
• At reset, this port is set to VEE level.
P40/INT0,
P41/INT1,
P42/INT3
P43/BUZ01
P44/PWM1
I/O port P4
• 7-bit I/O port with the same function as port P0.
• CMOS compatible input level
• Interrupt input pins
In the mask option type P,
INT3 cannot be used.
• Buzzer output pin
• PWM output pin
• N-channel open-drain output structure.
(Timer output pin)
P45/T1OUT,
P46/T3OUT
P47/INT2
• Timer output pin
Input port P4
• 1-bit input port.
• Interrupt input pin
• CMOS compatible input level.
38B5 Group User’s Manual
1-4
HARDWARE
PIN DESCRIPTION
Table 2 Pin description (2)
Pin
Name
Function
Function except a port function
• Serial I/O1 function pins
P50/SIN1,
I/O port P5
• 8-bit CMOS I/O port with the same function as port P0.
• CMOS compatible input level.
P51/SOUT1,
P52/SCLK11,
P53/SCLK12
P54/RXD,
P55/TXD,
• CMOS 3-state output structure.
• Serial I/O2 function pins
P56/SCLK21,
P57/SRDY2/
SCLK22
P60/CNTR1 I/O port P6
• 1-bit I/O port with the same function as port P0.
• CMOS compatible input level.
• Timer input pin
In the mask option type P,
CNTR1 cannot be used.
• Timer I/O pin
• N-channel open-drain output structure.
• 5-bit CMOS I/O port with the same function as port P0.
• CMOS compatible input level.
P61/CNTR0/
CNTR2
P62/SRDY1/
AN8
• CMOS 3-state output structure.
• Serial I/O1 function pin
• A-D conversion input pin
• A-D conversion input pin
• Dimmer signal output pin
• Serial I/O1 function pin
• A-D conversion input pin
• Interrupt input pin (P64)
P63/AN9
P64/INT4/
SBUSY1/AN10,
P65/SSTB1/
AN11
P70/AN0–
P77/AN7
I/O port P7
• 8-bit CMOS I/O port with the same function as port P0.
• CMOS compatible input level.
• A-D conversion input pin
• CMOS 3-state output structure.
P80/FLD32– I/O port P8
P83/FLD35
• 4-bit I/O port with the same function as port P0.
• Low-voltage input level.
•
•
FLD automatic display pins
FLD automatic display pins
• High-breakdown-voltage P-channel open-drain output structure.
• 4-bit CMOS I/O port with the same function as port P0.
• Low-voltage input level.
P84/FLD36
P85/RTP0/
FLD37,
• CMOS 3-state output structure
• Real time port output
P86/RTP1/
FLD38
P87/PWM0/
FLD39
•
FLD automatic display pins
• 14-bit PWM output
P90/XCIN,
I/O port P9
• 2-bit CMOS I/O port with the same function as port P0.
• CMOS compatible input level.
•
I/O pins for sub-clock generating
circuit (connect a ceramic resona-
tor or a quarts-crystal oscillator)
P91/XCOUT
• CMOS 3-state output structure.
38B5 Group User’s Manual
1-5
HARDWARE
PART NUMBERING
PART NUMBERING
Product
M38B5 7 M C H - XXXX FP
Package type
FP : 80P6N-A package
FS : 80D0 package
ROM number
Omitted in One Time PROM version shipped in
blank and EPROM version.
3 digits for M38B57M6-XXXFP and One Time
PROM version.
High-breakdown voltage pull-down option
Regarding option contents, refer to section “
MASK OPTION OF PULL-DOWN RESISTOR”.
For the M38B57M6-XXXFP, One Time PROM
version, and EPROM version, there is not the
option specification.
ROM/PROM size
: 4096 bytes
: 8192 bytes
: 12288 bytes
: 16384 bytes
: 20480 bytes
: 24576 bytes
: 28672 bytes
: 32768 bytes
: 36864 bytes
: 40960 bytes
: 45056 bytes
: 49152 bytes
: 53248 bytes
: 57344 bytes
: 61440 bytes
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used for
users.
Memory type
: Mask ROM version
M
E : EPROM or One Time PROM version
RAM size
: 192 bytes
: 256 bytes
: 384 bytes
: 512 bytes
: 640 bytes
: 768 bytes
: 896 bytes
: 1024 bytes
: 1536 bytes
: 2048 bytes
0
1
2
3
4
5
6
7
8
9
Fig. 3 Part numbering
38B5 Group User’s Manual
1-6
HARDWARE
GROUP EXPANSION
GROUP EXPANSION
Mitsubishi plans to expand the 38B5 group as follows:
Memory Type
Support for Mask ROM, One Time PROM and EPROM versions.
Memory Size
ROM/PROM size .................................................. 24K to 60K bytes
RAM size ............................................................1024 to 2048 bytes
Package
80P6N-A ..................................... 0.8 mm-pitch plastic molded QFP
80D0 ........................ 0.8 mm-pitch ceramic LCC (EPROM version)
Mass product
M38B59EF
ROM size (bytes)
60K
56K
M38B59MFH
New product
52K
48K
44K
40K
36K
32K
28K
24K
20K
16K
12K
8K
Mass product
M38B57MCH
Mass product
M38B57M6
4K
256
512
768
1,024
1,536
2,048
RAM size (bytes)
Note : Products under development or planning : the development schedule and specifications may be revised without notice.
Fig. 4 Memory expansion plan
Currently supported products are listed below.
Table 3 List of supported products
(P) ROM size (bytes)
As of Nov. 1998
Remarks
RAM size (bytes)
1024
Product
M38B57M6-XXXFP
M38B57MCH-XXXXFP
M38B59MFH-XXXXFP
M38B59EF-XXXFP
M38B59EFFP
Package
80P6N-A
80P6N-A
80P6N-A
80P6N-A
80P6N-A
80D0
ROM size for User ( )
24576
Mask ROM version
Corresponded to mask option
(24446)
49152
(49022)
61440
(61310)
61440
(61310)
61440
1024
Mask ROM version
Mask ROM version
Corresponded to mask option
2048
2048
One Time PROM version
One Time PROM version (blank)
EPROM version
2048
(61310)
61440
2048
M38B59EFFS
(61310)
38B5 Group User’s Manual
1-7
HARDWARE
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION
[Stack Pointer (S)]
Central Processing Unit (CPU)
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack ad-
dress are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“0116”.
The 38B5 group uses the standard 740 Family instruction set. Re-
fer to the table of 740 Series addressing modes and machine
instructions or the 740 Series Software Manual for details on the
instruction set.
Machine-resident 740 Series instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 6.
Store registers other than those described in Figure 6 with pro-
gram when the user needs them during interrupts or subroutine
calls.
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b0
b0
b0
b0
b0
b7
A
Accumulator
b7
X
Index register X
Index register Y
b7
Y
b7
S
Stack pointer
b15
b7
PCH
PC
L
Program counter
b7
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 5 740 Family CPU register structure
38B5 Group User’s Manual
1-8
HARDWARE
FUNCTIONAL DESCRIPTION
On-going Routine
Execute JSR
Interrupt request
(Note)
M (S) (PC
(S) (S) – 1
M (S) (PC
H
)
Push return address
on stack
M (S) (PC
(S) (S) – 1
M (S) (PC
H)
L
)
(S) (S) – 1
M (S) (PS)
(S) (S) – 1
Push return address
on stack
Push contents of processor
status register on stack
L
)
(S) (S)– 1
Subroutine
Interrupt
Service Routine
I Flag is set from “0” to “1”
Fetch the jump vector
Execute RTS
(S) (S) + 1
Execute RTI
(S) (S) + 1
POP return
POP contents of
processor status
register from stack
address from stack
(PC
(S) (S) + 1
(PC M (S)
L
)
M (S)
(PS)
(S) (S) + 1
(PC M (S)
(S) (S) + 1
(PC M (S)
M (S)
H
)
L)
POP return
address
from stack
H)
Note: Condition for acceptance of an interrupt
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 6 Register push and pop at interrupt generation and subroutine call
Table 4 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PHP
PLA
PLP
Processor status register
38B5 Group User’s Manual
1-9
HARDWARE
FUNCTIONAL DESCRIPTION
•Bit 4: Break flag (B)
[Processor status register (PS)]
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
Table 5 Set and clear instructions of each bit of processor status register
C flag
Z flag
I flag
D flag
B flag
T flag
V flag
_
N flag
_
_
_
_
_
_
SEC
CLC
SEI
CLI
SED
CLD
SET
CLT
Set instruction
Clear instruction
CLV
38B5 Group User’s Manual
1-10
HARDWARE
FUNCTIONAL DESCRIPTION
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit etc.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(
CPUM: address 003B16)
Processor mode bits
b1 b0
0
0
1
1
0 : Single-chip mode
1 :
0 : Not available
1 :
Stack page selection bit
0: Page 0
1: Page 1
X
COUT drivability selection bit
0: Low drive
1: High drive
Port XC switch bit
0: I/O port function
1: XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0: Oscillating
1: Stopped
Main clock division ratio selection bit
0: f(XIN) (high-speed mode)
1: f(XIN)/4 (middle-speed mode)
Internal system clock selection bit
0: XIN-XOUT selection (middle-/high-speed mode)
1: XCIN-XCOUT selection (low-speed mode)
Fig. 7 Structure of CPU mode register
38B5 Group User’s Manual
1-11
HARDWARE
FUNCTIONAL DESCRIPTION
Memory
Special function register (SFR) area
The special function register (SFR) area in the zero page contains
control registers such as I/O ports and timers.
Zero page
The 256 bytes from addresses 000016 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
ROM
Special page
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing, and the other areas are user areas for storing pro-
grams.
The 256 bytes from addresses FF0016 to FFFF16 are called the spe-
cial page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM size
(byte)
Address
XXXX16
000016
SFR area 1
RAM
192
256
384
512
640
768
896
1024
1536
2048
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
Zero page
004016
010016
XXXX16
Reserved area
044016
Not used (Note)
0EF0
0EFF1166
ROM area
SFR area 2
0F0016
ROM size
(byte)
Address
YYYY16
Address
ZZZZ16
RAM area for Serial I/O automatic
transfer
RAM area for FLD automatic display
ROM
0FFF16
YYYY16
4096
8192
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
Reserved ROM area
(common ROM area,128 byte)
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
ZZZZ16
FF0016
Special page
FFDC16
Interrupt vector area
Reserved ROM area
FFFE16
FFFF16
Note: When 1024 bytes or more are used as RAM area, this area can be used.
Fig. 8 Memory map diagram
38B5 Group User’s Manual
1-12
HARDWARE
FUNCTIONAL DESCRIPTION
000016 Port P0 (P0)
Port P0 direction register (P0D)
002016 Timer 1 (T1)
Timer 2 (T2)
Timer 3 (T3)
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
002116
002216
Port P1 (P1)
002316 Timer 4 (T4)
002416 Timer 5 (T5)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Timer 6 (T6)
002516
002616 PWM control register (PWMCON)
002716 Timer 6 PWM register (T6PWM)
002816 Timer 12 mode register (T12M)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Timer 34 mode register (T34M)
Timer 56 mode register (T56M)
002916
002A16
Port P5 direction register (P5D)
Port P6 (P6)
002B16 Watchdog timer control register (WDTCON)
002C16 Timer X (low-order) (TXL)
Port P6 direction register (P6D)
Port P7 (P7)
002D16 Timer X (high-order) (TXH)
002E16 Timer X mode register 1 (TXM1)
002F16 Timer X mode register 2 (TXM2)
003016 Interrupt interval determination register (IID)
Port P7 direction register (P7D)
Port P8 (P8)
Port P8 direction register (P8D)
Interrupt interval determination control register (IIDCON)
003116
001216 Port P9 (P9)
003216 A-D control register (ADCON)
001316 Port P9 direction register (P9D)
003316 A-D conversion register (low-order) (ADL)
PWM register (high-order) (PWMH)
PWM register (low-order) (PWM L)
Baud rate generator (BRG)
001416
001516
001616
001716
001816
001916
003416 A-D conversion register (high-order) (ADH)
003516
003616
003716
003816
UART control register (UARTCON)
Serial I/O1 automatic transfer data pointer (SIO1DP)
Serial I/O1 control register 1 (SIO1CON1)
Interrupt source switch register (IFR)
003916
001A16 Serial I/O1 control register 2 (SIO1CON2)
001B16 Serial I/O1 register/Transfer counter (SIO1)
003A16 Interrupt edge selection register (INTEDGE)
003B16 CPU mode register (CPUM)
Serial I/O1 control register 3 (SIO1CON3)
Serial I/O2 control register (SIO2CON)
Interrupt request register 1(IREQ1)
Interrupt request register 2(IREQ2)
001C16
001D16
003C16
003D16
001E16 Serial I/O2 status register (SIO2STS)
003E16 Interrupt control register 1(ICON1)
003F16 Interrupt control register 2(ICON2)
Serial I/O2 transmit/receive buffer register (TB/RB)
001F16
Pull-up control register 1 (PULL1)
Pull-up control register 2 (PULL2)
P1FLDRAM write disable register (P1FLDRAM)
P3FLDRAM write disable register (P3FLDRAM)
FLDC mode register (FLDM)
FLD data pointer (FLDDP)
0EF016
0EF116
0EF216
0EF316
0EF416
0EF816
0EF916
Port P0FLD/port switch register (P0FPR)
0EFA16 Port P2FLD/port switch register (P2FPR)
0EFB16 Port P8FLD/port switch register (P8FPR)
Port P8FLD output control register (P8FLDCON)
0EFC16
0EF516 Tdisp time set register (TDISP)
0EF616 Toff1 time set register (TOFF1)
0EF716 Toff2 time set register (TOFF2)
0EFD16 Buzzer output control register (BUZCON)
0EFE16
0EFF16
Fig. 9 Memory map of special function register (SFR)
38B5 Group User’s Manual
1-13
HARDWARE
FUNCTIONAL DESCRIPTION
I/O Ports
[Direction Registers] PiD
The 38B5 group has 55 programmable I/O pins arranged in eight
individual I/O ports (P0, P2, P40–P46, and P5–P9). The I/O ports
have direction registers which determine the input/output direction of
each individual pin. Each bit in a direction register corresponds to
one pin, and each pin can be set to be input port or output port. When
“0” is written to the bit corresponding to a pin, that pin becomes an
input pin. When “1” is written to that pin, that pin becomes an output
pin. If data is read from a pin set to output, the value of the port
output latch is read, not the value of the pin itself. Pins set to input
(the bit corresponding to that pin must be set to “0”) are floating and
the value of that pin can be read. If a pin set to input is written to, only
the port output latch is written to and the pin remains floating.
b7
b0
Pull-up control register 1
(PULL1 : address 0EF0 16)
P50, P51 pull-up control bit
P52, P53 pull-up control bit
P54, P55 pull-up control bit
P56, P57 pull-up control bit
P61 pull-up control bit
0: No pull-up
1: Pull-up
P62, P63 pull-up control bit
P64, P65 pull-up control bit
Not used
(returns “0” when read)
[High-Breakdown-Voltage Output Ports]
The 38B5 group has 5 ports with high-breakdown-voltage pins (ports
P0–P3 and P80–P83). The high-breakdown-voltage ports have P-
channel open-drain output with Vcc- 45 V of breakdown voltage. Each
pin in ports P0, P1, and P3 has an internal pull-down resistor con-
nected to VEE. At reset, the P-channel output transistor of each port
latch is turned off, so that it goes to VEE level (“L”) by the pull-down
resistor.
b7
b0
Pull-up control register 2
(PULL2 : address 0EF1 16)
P70, P71 pull-up control bit
P72, P73 pull-up control bit
P74, P75 pull-up control bit
P76, P77 pull-up control bit
P84, P85 pull-up control bit
P86, P87 pull-up control bit
P90, P91 pull-up control bit
0: No pull-up
1: Pull-up
Writing “1” (weak drivability) to bit 7 of the FLDC mode register (ad-
dress 0EF416) shows the rising transition of the output transistors for
reducing transient noise. At reset, bit 7 of the FLDC mode register is
set to “0” (strong drivability).
Not used
(returns “0” when read)
[Pull-up Control Register] PULL
Ports P5, P61–P65, P7, P84–P87 and P9 have built-in programmable
pull-up resistors. The pull-up resistors are valid only in the case that
the each control bit is set to “1” and the corresponding port direction
registers are set to input mode.
Fig. 10 Structure of pull-up control registers (PULL1 and
PULL2)
38B5 Group User’s Manual
1-14
HARDWARE
FUNCTIONAL DESCRIPTION
Table 6 List of I/O port functions (1)
Pin Name Input/Output
P00/FLD8– Port P0 Input/output,
I/O Format
Non-Port Function
Related SFRs
Ref.No.
(1)
CMOS compatible input level FLD automatic display function FLDC mode register
P07/FLD15
individual bits High-breakdown voltage P-
Port P0FLD/port switch register
channel open-drain output
with pull-down resistor
P10/FLD16– Port P1 Output
P17/FLD23
High-breakdown voltage P-
channel open-drain output
with pull-down resistor
FLDC mode register
FLDC mode register
(2)
P20/BUZ02/ Port P2 Input/output,
Low-voltage input level
Buzzer output (P20)
(3)
(1)
(2)
FLD0
individual bits High-breakdown voltage P- FLD automatic display function Port P2FLD/port switch register
P21/FLD1–
channel open-drain output
FLD automatic display function Buzzer output control register
FLDC mode register
P27/FLD7
P30/FLD24– Port P3 Output
P37/FLD31
High-breakdown voltage P-
channel open-drain output
with pull-down resistor
P40/INT0,
P41/INT1,
P42/INT3
P43/BUZ01
P44/PWM1
P45/T1OUT
P46/T3OUT
P47/INT2
Port P4 Input/output,
CMOS compatible input level External interrupt input
Interrupt edge selection register
(5-1)
(5-2)
individual bits N-channel open-drain output In the mask option type P, INT3
cannot be used.
Buzzer output
PWM output
Timer output
Timer output
Buzzer output control register
Timer 56 mode register
Timer 12 mode register
Timer 34 mode register
(4)
(6)
(7)
(7)
(8)
Input
CMOS compatible input level External interrput input
Interrupt edge selection register
Interrupt interval determination
control register
P50/SIN1
Port P5 Input/output,
CMOS compatible input level Serial I/O1 function I/O
Serial I/O1 control register 1, 2
(9)
P51/SOUT1,
P52/SCLK11,
P53/SCLK12
P54/RXD,
P55/TXD,
P56/SCLK21
P57/SRDY2/
SCLK22
individual bits CMOS 3-state output
(10)
Serial I/O2 function I/O
Serial I/O2 control register
UART control register
(9)
(10)
(11)
P60/CNTR1 Port P6
CMOS compatible input level External count input
N-channel open-drain output In the mask option type P,
CMOS compatible input level CNTR1 cannot be used.
CMOS 3-state output
Interrupt edge selection register
(5-1)
(5-2)
(12)
P61/CNTR0/
CNTR2
P62/SRDY1/
AN8
Serial I/O1 function I/O
Serial I/O1 control register 1, 2
A-D control register
(13)
(14)
(15)
A-D conversion input
P63/AN9
A-D conversion input
A-D control register
Dimmer signal output
P8FLD output control bit
Serial I/O1 control register 1, 2
A-D control register
P64/INT4/
Serial I/O1 function I/O
S
BUSY1
/
AN10
A-D conversion input
External interrupt input
Interrupt edge selection register
Serial I/O1 control register 1, 2
A-D control register
P65/SSTB1/
AN11
Serial I/O1 function I/O
(16)
(14)
A-D conversion input
P70/AN0–
P77/AN7
Port P7
A-D conversion input
A-D control register
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HARDWARE
FUNCTIONAL DESCRIPTION
Table 7 List of I/O port functions (2)
Pin
Name
Input/Output
I/O Format
Non-Port Function
Related SFRs
Ref.No.
(1)
P80/FLD32– Port P8 Input/output, Low-voltage input level
FLD automatic display function FLDC mode register
P83/FLD35
individual bits High-breakdown voltage P-
channel open-drain output
Low-voltage input level
Port P8FLD/port switch register
P84/FLD36
P85/RTP0/
FLD37,
(17)
(18)
CMOS 3-state output
FLD automatic display function FLDC mode register
Real time port output
Port P8FLD/port switch register
P86/RTP1/
FLD38
Timer X mode register 2
P87/PWM0/
FLD39
FLD automatic display function FLDC mode register
(19)
PWM output
Port P8FLD/port switch register
PWM control register
P90/XCIN
Port P9
CMOS compatible input level Sub-clock generating circuit I/O CPU mode register
CMOS 3-state output
(20)
(21)
P91/XCOUT
Notes 1 : How to use double-function ports as function I/O ports, refer to the applicable sections.
2 : Make sure that the input level at each pin is either 0 V or Vcc during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from Vcc to Vss through the input-stage gate.
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HARDWARE
FUNCTIONAL DESCRIPTION
(1) Ports P0, P2
1–P2
7
, P8
0
–P8
3
(2) Ports P1, P3
FLD/Port
switch register
Dimmer signal (Note 1)
Direction register
Dimmer signal (Note 1)
Local data
bus
Local data
bus
Port latch
*
*
Data bus
Port latch
Data bus
read
VEE
(Note 2)
VEE
(3) Port P2
0
(4) Port P43
Buzzer control signal
Buzzer signal output
FLD/Port
switch register
Buzzer control signal
Buzzer signal output
Direction register
Port latch
Dimmer signal (Note 1)
Direction register
Local data
bus
Data bus
Port latch
*
Data bus
read
(Note 2)
V
EE
(5-1) Ports P4
0–P4
2, P6
0
(5-2) Ports P42, P60 (in mask option type P)
Direction register
Port latch
Direction register
Port latch
Data bus
Data bus
INT
CNTR
Timer 4 external clock input
0
,
INT
1
,
INT
3
interrupt input
1
input
(6) Port P4
4
(7) Ports P45, P4
6
Timer 1 output bit
Timer 3 output bit
Timer 6 output selection bit
Direction register
Direction register
Port latch
Data bus
Port latch
Data bus
Timer 1 output
Timer 3 output
(Note 3)
Timer 6 output
* High-breakdown-voltage P-channel transistor
Notes 1: The dimmer signal sets the Toff timing.
2: A pull-down resistor is not built in to ports P2 and P8.
3: In the mask option type P, the hysteresis circuit of
part is not built-in.
Fig. 11 Port block diagram (1)
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HARDWARE
FUNCTIONAL DESCRIPTION
(8) Port P4
7
(9) Ports P50, P54
Pull-up control
Data bus
Direction register
Port latch
INT2 interrupt
input
Data bus
Serial I/O input
(10) Ports P5
1–P5
3
, P5
5
, P5
6
(11) Port P57
Pull-up control
,P5
Pull-up control
P-channel output disable signal (P5
Output OFF control signal
Serial I/O2 mode selection bit
1
5)
S
RDY2 output enable bit
Direction register
Direction register
Data bus
Port latch
Port latch
Data bus
T
X
D, SOUT or SCLK
Serial ready output
Serial clock input
Serial clock input
P5 ,P5 ,P5
2
3
6
(12) Port P6
1
(13) Port P62
Pull-up control
Pull-up control
P6
2/SRDY1•P64/SBUSY1
Timer X operating mode bit
Direction register
pin control bit
Direction register
Port latch
Port latch
Data bus
Data bus
Timer X output
Serial ready output
CNTR
0,CNTR2 input
Serial ready input
A-D conversion input
Analog input pin selection bit
Timer 2, Timer X external clock input
Fig. 12 Port block diagram (2)
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HARDWARE
FUNCTIONAL DESCRIPTION
(14) Ports P6
3, P7
(15) Port P64
Pull-up control
P6
2/SRDY1•P64/SBUSY1
Pull-up control
pin control bit
Dimmer output control bit (P6
Direction register
3)
Direction register
Port latch
Data bus
Port latch
Data bus
Analog
input
pin
selection
bit
S
BUSY1 output
INT
4 interrupt input, SBUSY1 input
Dimmer signal output (P6
A-D conversion input
Analog input pin selection bit
3)
A-D conversion input
(16) Port P6
5
(17) Port P84
Pull-up control
P65
/SSTB1 pin control bit
Direction register
Dimmer signal
(Note)
Pull-up control
FLD/Port
switch register
Direction register
Port latch
Port latch
Data bus
Local data
bus
Data bus
SSTB1 output
A-D conversion input
(18) Ports P8
5,
P8
6
(19) Port P87
Dimmer signal
(Note)
Pull-up control
Dimmer signal
(Note)
Pull-up control
P87/PWM
output enable
bit
FLD/Port
FLD/Port
switch register
switch register
Real time port
control bit
Direction register
Port latch
Direction register
Port latch
Local data
bus
Local data
bus
Data bus
Data bus
RTP output
PWM0 output
(20) Port P9
0
(21) Port P9
1
Pull-up control
Pull-up control
Port Xc switch bit
Direction register
Port Xc switch bit
Direction register
Port latch
Port latch
Data bus
Data bus
Oscillator
Port P9
0
Sub-clock generating circuit input
Port Xc switch bit
* High-breakdown-voltage P-channel transistor
Note: The dimmer signal sets the Toff timing.
Fig. 13 Port block diagram (3)
38B5 Group User’s Manual
1-19
HARDWARE
FUNCTIONAL DESCRIPTION
Interrupts
Interrupts occur by twenty one sources: five external, fifteen internal,
and one software.
(1) Interrupt Control
Each interrupt except the BRK instruction interrupt have both an
interrupt request bit and an interrupt enable bit, and is controlled by
the interrupt disable flag. An interrupt occurs if the corresponding
interrupt request and enable bits are “1” and the interrupt disable flag
is “0.” Interrupt enable bits can be set or cleared by software. Inter-
rupt request bits can be cleared by software, but cannot be set by
software. The BRK instruction interrupt and reset cannot be disabled
with any flag or bit. The I flag disables all interrupts except the BRK
instruction interrupt and reset. If several interrupts requests occurs
at the same time the interrupt with highest priority is accepted first.
(2) Interrupt Operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
1. The contents of the program counter and processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding
interrupt request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
■Notes on Use
When the active edge of an external interrupt (INT0–INT4) is set or
when switching interrupt sources in the same vector address, the
corresponding interrupt request bit may also be set. Therefore, please
take following sequence:
(1) Disable the external interrupt which is selected.
(2) Change the active edge in interrupt edge selection register
(3) Clear the set interrupt request bit to “0.”
(4) Enable the external interrupt which is selected.
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HARDWARE
FUNCTIONAL DESCRIPTION
Table 8 Interrupt vector addresses and priority
Vector Addresses (Note 1)
Interrupt Request
Interrupt Source Priority
Remarks
High
Low
Generating Conditions
Reset (Note 2)
1
2
FFFD16
FFFB16
FFFC16
FFFA16
At reset
Non-maskable
INT0
At detection of either rising or falling edge of
INT0 input
External interrupt
(active edge selectable)
External interrupt
INT1
INT2
3
4
FFF916
FFF716
FFF816
FFF616
At detection of either rising or falling edge of
INT1 input
(active edge selectable)
External interrupt
At detection of either rising or falling edge of
INT2 input
(active edge selectable)
Valid when interrupt interval
determination is operating
Valid when serial I/O ordinary
mode is selected
Remote control/
counter overflow
Serial I/O1
At 8-bit counter overflow
5
FFF516
FFF416
At completion of data transfer
Serial I/O auto-
matic transfer
Timer X
At completion of the last data transfer
Valid when serial I/O automatic
transfer mode is selected
6
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
At timer X underflow
Timer 1
7
At timer 1 underflow
Timer 2
8
At timer 2 underflow
STP release timer underflow
Timer 3
9
At timer 3 underflow
Timer 4
10
11
12
13
14
At timer 4 underflow
(Note 3)
Timer 5
At timer 5 underflow
Timer 6
At timer 6 underflow
Serial I/O2 receive
INT3
At completion of serial I/O2 data receive
At detection of either rising or falling edge of
INT3 input
External interrupt (Note 4)
(active edge selectable)
Serial I/O2 transmit
INT4
At completion of serial I/O2 data transmit
At detection of either rising or falling edge of
INT4 input
15
FFE116
FFE016
External interrupt
(active edge selectable)
Valid when INT4 interrupt is selected
A-D conversion
FLD blanking
At completion of A-D conversion
At falling edge of the last timing immediately
before blanking period starts
Valid when A-D conversion is selected
Valid when FLD blanking
16
17
FFDF16
FFDD16
FFDE16
FFDC16
interrupt is selected
FLD digit
At rising edge of digit (each timing)
At BRK instruction execution
Valid when FLD digit interrupt is selected
Non-maskable software interrupt
BRK instruction
Notes 1 : Vector addresses contain interrupt jump destination addresses.
2 : Reset function in the same way as an interrupt with the highest priority.
3 : In the mask option type P, timer 4 interrupt whose count source is CNTR1 input cannot be used.
4 : In the mask option type P, INT3 interrupt cannot be used.
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HARDWARE
FUNCTIONAL DESCRIPTION
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset
Interrupt request
Fig. 14 Interrupt control
b7
b0
Interrupt source switch register
(IFR : address 003916
)
INT
0 : INT
1 : Serial I/O2 transmit interrupt
INT /AD conversion interrupt switch bit
0 : INT interrupt
3
/serial I/O2 transmit interrupt switch bit (Note 1)
3
interrupt
4
4
1 : A-D conversion interrupt
Not used (return “0” when read)
(Do not write “1” to these bits.)
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16
)
INT
INT
INT
INT
INT
0
interrupt edge selection bit
interrupt edge selection bit
interrupt edge selection bit
interrupt edge selection bit (Note 1)
interrupt edge selection bit
1
2
3
4
0 : Falling edge active
1 : Rising edge active
Not used (return "0" when read)
0 : Rising edge count
1 : Falling edge count
CNTR
CNTR
0
1
pin edge switch bit
pin edge switch bit (Note 1)
b7
b0
b7
b0
Interrupt request register 2
(IREQ2 : address 003D16
Interrupt request register 1
(IREQ1 : address 003C16
)
)
INT
INT
INT
0
interrupt request bit
interrupt request bit
interrupt request bit
Timer 4 interrupt request bit (Note 2)
Timer 5 interrupt request bit
1
2
Timer 6 interrupt request bit
Remote controller/counter overflow interrupt
request bit
Serial I/O2 receive interrupt request bit
INT
INT
3
4
/serial I/O2 transmit interrupt request bit (Note 2)
Serial I/O1 interrupt request bit
Serial I/O automatic transfer interrupt request bit
Timer X interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
interrupt request bit
AD conversion interrupt request bit
FLD blanking interrupt request bit
FLD digit interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0 Interrupt control register 1
(ICON1 : address 003E16
b7
b0
Interrupt control register 2
(ICON2 : address 003F16
)
)
INT
INT
INT
0
interrupt enable bit
interrupt enable bit
interrupt enable bit
Timer 4 interrupt enable bit (Note 3)
Timer 5 interrupt enable bit
1
2
Timer 6 interrupt enable bit
Remote controller/counter overflow interrupt
enable bit
Serial I/O2 receive interrupt enable bit
INT
INT
3
4
/serial I/O2 transmit interrupt enable bit (Note 3)
interrupt enable bit
Serial I/O1 interrupt enable bit
Serial I/O automatic transfer interrupt enable bit
Timer X interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
AD conversion interrupt enable bit
FLD blanking interrupt enable bit
FLD digit interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
0 : Interrupt disabled
1 : Interrupt enabled
Notes 1: In the mask option type P, these bits are not available because CNTR
1
function and INT
3
function cannot be used.
interrupt are selected, these bits do not become “1”.
interrupt are not available.
2: In the mask option type P, if timer 4 interrupt whose count source is CNTR
1
input and INT3
3: In the mask option type P, timer 4 interrupt whose count source is CNTR
1
input and INT
3
Fig. 15 Structure of interrupt related registers
38B5 Group User’s Manual
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HARDWARE
FUNCTIONAL DESCRIPTION
Timers
8-Bit Timer
The 38B5 group has six built-in timers : Timer 1, Timer 2, Timer 3,
Timer 4, Timer 5, and Timer 6.
b7
b7
b7
b0
Timer 12 mode register
(T12M: address 002816)
Each timer has the 8-bit timer latch. All timers are down-counters.
When the timer reaches “0016,” an underflow occurs with the next
count pulse. Then the contents of the timer latch is reloaded into the
timer and the timer continues down-counting. When a timer
underflows, the interrupt request bit corresponding to that timer is
set to “1.”
Timer 1 count stop bit
0 : Count operation
1 : Count stop
Timer 2 count stop bit
0 : Count operation
1 : Count stop
Timer 1 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : f(XCIN)
10 : f(XIN)/16 or f(XCIN)/32
11 : f(XIN)/64 or f(XCIN)/128
Timer 2 count source selection bits
00 : Underflow of Timer 1
01 : f(XCIN)
10 : External count input CNTR0
11 : Not available
Timer 1 output selection bit (P45)
0 : I/O port
The count can be stopped by setting the stop bit of each timer to “1.”
The internal system clock can be set to either the high-speed mode
or low-speed mode with the CPU mode register. At the same time,
timer internal count source is switched to either f(XIN) or f(XCIN).
●Timer 1, Timer 2
1 : Timer 1 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
The count sources of timer 1 and timer 2 can be selected by setting
the timer 12 mode register. A rectangular waveform of timer 1 under-
flow signal divided by 2 can be output from the P45/T1OUT pin. The
active edge of the external clock CNTR0 can be switched with the bit
6 of the interrupt edge selection register.
b0
Timer 34 mode register
(T34M: address 002916)
Timer 3 count stop bit
0 : Count operation
1 : Count stop
Timer 4 count stop bit
0 : Count operation
1 : Count stop
Timer 3 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : Underflow of Timer 2
10 : f(XIN)/16 or f(XCIN)/32
11 : f(XIN)/64 or f(XCIN)/128
Timer 4 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : Underflow of Timer 3
10 : External count input CNTR1 (Note)
11 : Not available
Timer 3 output selection bit (P46)
0 : I/O port
1 : Timer 3 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
At reset or when executing the STP instruction, all bits of the timer 12
mode register are cleared to “0,” timer 1 is set to “FF16,” and timer 2
is set to “0116.”
●Timer 3, Timer 4
The count sources of timer 3 and timer 4 can be selected by setting
the timer 34 mode register. A rectangular waveform of timer 3 under-
flow signal divided by 2 can be output from the P46/T3OUT pin. The
active edge of the external clock CNTR1 (Note) can be switched with
the bit 7 of the interrupt edge selection register.
Note: In the mask option type P, CNTR1 function cannot be used.
b0
Timer 56 mode register
(T56M: address 002A16)
●Timer 5, Timer 6
The count sources of timer 5 and timer 6 can be selected by setting
the timer 56 mode register. A rectangular waveform of timer 6 under-
flow signal divided by 2 can be output from the P44/PWM1 pin.
Timer 5 count stop bit
0 : Count operation
1 : Count stop
Timer 6 count stop bit
0 : Count operation
1 : Count stop
Timer 5 count source selection bit
0 : f(XIN)/8 or f(XCIN)/16
1 : Underflow of Timer 4
Timer 6 operation mode selection bit
0 : Timer mode
●Timer 6 PWM1 Mode
Timer 6 can output a PWM rectangular waveform with “H” duty cycle
n/(n+m) from the P44/PWM1 pin by setting the timer 56 mode regis-
ter (refer to Figure 18). The n is the value set in timer 6 latch (address
002516) and m is the value in the timer 6 PWM register (address
002716). If n is “0,” the PWM output is “L,” if m is “0,” the PWM output
is “H” (n = 0 is prior than m = 0). In the PWM mode, interrupts occur
at the rising edge of the PWM output.
1 : PWM mode
Timer 6 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : Underflow of Timer 5
10 : Underflow of Timer 4
11 : Not available
Timer 6 (PWM) output selection bit (P44)
0 : I/O port
1 : Timer 6 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
Note: In the mask option type P, CNTR1 function cannot be used.
Fig. 16 Structure of timer related register
38B5 Group User’s Manual
1-23
HARDWARE
FUNCTIONAL DESCRIPTION
Data bus
X
CIN
RESET
Timer 1 latch (8)
Timer 1 count source
selection bits
1/2
“01”
FF16
Internal system clock
selection bit
STP instruction
Timer 1 interrupt request
“1”
Timer 1 (8)
1/8
X
IN
“00”
“10”
“11”
Timer 1 count
stop bit
“0”
1/16
1/64
P45 latch
P45/T1OUT
1/2
Timer 1 output selection bit
Timer 2 latch (8)
Timer 2 count source
selection bits
“00”
“01”
0116
Timer 2 interrupt request
Timer 2 (8)
P45 direction register
Timer 2 count
stop bit
“10”
Rising/Falling
active edge switch
P61/CNTR0/CNTR2
Timer 3 latch (8)
Timer 3 count source
selection bits
“01”
“00”
Timer 3 interrupt request
Timer 3 (8)
Timer 3 count
stop bit
P46 latch
“10”
“11”
P46/T3OUT
1/2
Timer 3 output selection bit
Timer 4 latch (8)
Timer 4 count source
selection bits
“01”
Timer 4 (8)
Timer 4 interrupt request
P46
direction register
Rising/Falling
“00”
“10”
Timer 4 count
stop bit
P6
0/CNTR1
active edge switch
(Note)
Timer 5 latch (8)
Timer 5 count source
“1” selection bit
Timer 5 interrupt request
Timer 5 (8)
“0”
Timer 5 count
stop bit
Timer 6 latch (8)
Timer 6 count source
“01”
selection bits
Timer 6 (8)
Timer 6 interrupt request
“00”
“10”
Timer 6 count
stop bit
Timer 6 PWM register (8)
P44 latch
P44/PWM1
PWM
1/2
“1”
“0”
Timer 6 output selection bit
Timer 6 operation
mode selection bit
Note: In the mask option type P, CNTR1 function cannot be used.
P44 direction register
Fig. 17 Block diagram of timer
38B5 Group User’s Manual
1-24
HARDWARE
FUNCTIONAL DESCRIPTION
ts
Timer 6
count source
Timer 6 PWM
mode
n
✕
ts
m
ts
✕ ts
(n+m)
✕
Timer 6 interrupt request
Timer 6 interrupt request
Note: PWM waveform (duty : n/(n + m) and period: (n + m)
n : setting value of Timer 6
✕ ts) is output.
m: setting value of Timer 6 PWM register
ts: period of Timer 6 count source
Fig. 18 Timing chart of timer 6 PWM1 mode
38B5 Group User’s Manual
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HARDWARE
FUNCTIONAL DESCRIPTION
16-Bit Timer
■ Note
Timer X is a 16-bit timer that can be selected in one of four modes by
the Timer X mode registers 1, 2 and can be controlled the timer X
write and the real time port by setting the timer X mode registers.
Read and write operation on 16-bit timer must be performed for both
high- and low-order bytes. When reading a 16-bit timer, read from
the high-order byte first. When writing to 16-bit timer, write to the low-
order byte first. The 16-bit timer cannot perform the correct operation
when reading during write operation, or when writing during read
operation.
•Timer X Write Control
If the timer X write control bit is “0,” when the value is written in the
address of timer X, the value is loaded in the timer X and the latch at
the same time.
If the timer X write control bit is “1,” when the value is written in the
address of timer X, the value is loaded only in the latch. The value in
the latch is loaded in timer X after timer X underflows.
When the value is written in latch only, unexpected value may be set
in the high-order counter if the writing in high-order latch and the
underflow of timer X are performed at the same timing.
●Timer X
Timer X is a down-counter. When the timer reaches “000016,” an
underflow occurs with the next count pulse. Then the contents of the
timer latch is reloaded into the timer and the timer continues down-
counting. When a timer underflows, the interrupt request bit corre-
sponding to that timer is set to “1.”
•Real Time Port Control
While the real time port function is valid, data for the real time port
are output from ports P85 and P86 each time the timer X underflows.
(However, if the real time port control bit is changed from “0” to “1,”
data are output without the timer X.) When the data for the real time
port is changed while the real time port function is valid, the changed
data are output at the next underflow of timer X.
(1) Timer mode
A count source can be selected by setting the Timer X count source
selection bits (bits 1 and 2) of the Timer X mode register 1.
Before using this function, set the corresponding port direction regis-
ters to output mode.
(2) Pulse output mode
Each time the timer underflows, a signal output from the CNTR2 pin
is inverted. Except for this, the operation in pulse output mode is the
same as in timer mode. When using a timer in this mode, set the port
shared with the CNTR2 pin to output.
(3) Event counter mode
The timer counts signals input through the CNTR2 pin. Except for
this, the operation in event counter mode is the same as in timer
mode. When using a timer in this mode, set the port shared with the
CNTR2 pin to input.
(4) Pulse width measurement mode
A count source can be selected by setting the Timer X count source
selection bits (bits 1 and 2) of the Timer X mode register 1. When
CNTR2 active edge switch bit is “0,” the timer counts while the input
signal of the CNTR2 pin is at “H.” When it is “1,” the timer counts
while the input signal of the CNTR2 pin is at “L.” When using a timer
in this mode, set the port shared with the CNTR2 pin to input.
38B5 Group User’s Manual
1-26
HARDWARE
FUNCTIONAL DESCRIPTION
Real time port
Data bus
control bit
“1”
Q D
P85 data for real time port
P85
Real time port
control bit (P85)
“0”
Latch
“0”
“1”
P85 direction
register
Timer X mode register
write signal
P85 latch
Real time port
“1”
control bit
Q D
P86 data for real time port
P86
1/2
“0”
Real time port
control bit (P86)
Latch
P86 direction
register
“0”
“1”
Timer X mode register
write signal
P86 latch
XCIN
XIN
Internal system clock
selection bit
1/2
@“1”
Count source selection bit
1/8
“0”
1/64
Timer X stop
control bit
Timer X write
control bit
Timer X operating
mode bits
CNTR2 active
edge switch bit
Timer X latch (high-order) (8)
Timer X latch (low-order) (8)
“00”,“01”,“11”
“0”
Timer X
P61/CNTR0/CNTR2
Timer X (low-order) (8)
Timer X (high-order) (8)
interrupt request
“10”
“1”
Pulse width
measurement mode
CNTR2 active
Pulse output mode
“0”
“1”
edge switch bit
Q
Q
T
P61 direction
register
P61 latch
Pulse output mode
CNTR0
Fig. 19 Block diagram of timer X
b7
b0
b7
b0
Timer X mode register 2
(TXM2 : address 002F16
Timer X mode register 1
(TXM1 : address 002E16
)
)
Timer X write control bit
Real time port control bit (P85)
0 : Real time port function is invalid
1 : Real time port function is valid
Real time port control bit (P86)
0 : Real time port function is invalid
1 : Real time port function is valid
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer X count source selection bits
b2 b1
0
0
1
1
0 : f(XIN)/2 or f(XCIN)/4
1 : f(XIN)/8 or f(XCIN)/16
0 : f(XIN)/64 or f(XCIN)/128
1 : Not available
P8
P8
5
6
data for real time port
data for real time port
Not used (returns "0" when read)
Not used (returns "0" when read)
Timer X operating mode bits
b5 b4
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement mode
CNTR2 active edge switch bit
0 : • Event counter mode ; counts rising edges
• Pulse output mode ; output starts with “H” level
• Pulse width measurement mode ; measures “H” periods
1 : • Event counter mode ; counts falling edges
• Pulse output mode ; output starts with “L” level
• Pulse width measurement mode ; measures “L” periods
Timer X stop control bit
0 : Count operating
1 : Count stop
Fig. 20 Structure of timer X related registers
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HARDWARE
FUNCTIONAL DESCRIPTION
FLD automatic display RAM).
Serial I/O
The P62/SRDY1/AN8, P64/INT4/SBUSY1/AN10, and P65/SSTB1/AN11
pins each have a handshake I/O signal function and can select
either “H” active or “L” active for active logic.
●Serial I/O1
Serial I/O1 is used as the clock synchronous serial I/O and has an
ordinary mode and an automatic transfer mode. In the automatic
transfer mode, serial transfer is performed through the serial I/O
automatic transfer RAM which has up to 256 bytes (addresses
0F0016 to 0FFF16: addresses 0F6016 to 0FFF16 are also used as
Main address
bus
Local address
bus
Main
data bus
Local
data bus
Serial I/O automatic
transfer RAM
(0F0016—0FFF16)
Serial I/O1
automatic transfer
data pointer
Address decoder
Serial I/O1
automatic transfer
controller
XCIN
1/2
Serial I/O1
control register 3
Internal system
clock selection bit
“1”
“0”
1/4
1/8
XIN
P65 latch
“0”
1/16
1/32
1/64
1/128
1/256
(P65/SSTB1 pin control bit)
P65/SSTB1
“1”
P62/SRDY1•P64/SBUSY1
pin control bit
P64 latch
Internal synchronous
clock selection bits
“0”
Serial I/O1
synchronous clock
P64/SBUSY1
“1”
selection bit
“0”
P62/SRDY1•P64/SBUSY1
pin control bit
Synchronous
circuit
P62 latch
“0”
“1”
Serial I/O1 clock
P62/SRDY1
pin selection bit
“1”
“0”
“1”
Serial transfer
status flag
Serial I/O1
interrupt request
P52 latch
“0”
P52/SCLK11
P53/SCLK12
“0”
“1”
“1”
“1”
Serial I/O1 counter
Serial I/O1 clock
pin selection bits
“0”
P53 latch
“0”
P51 latch
P51/SOUT1
P50/SIN1
“1”
Serial transfer selection bits
Serial I/O1 register (8)
Fig. 21 Block diagram of serial I/O1
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HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
Serial I/O1 control register 1
(SIO1CON1 (SC11):address 001916)
Serial transfer selection bits
00: Serial I/O disabled (pins P62,P64,P65,and P50—P53 are I/O ports)
01: 8-bit serial I/O
10: Not available
11: Automatic transfer serial I/O (8-bits)
Serial I/O1 synchronous clock selection bits (P65/SSTB1 pin control bit)
00: Internal synchronous clock (P65 pin is an I/O port.)
01: External synchronous clock (P65 pin is an I/O port.)
10: Internal synchronous clock (P65 pin is an SSTB1 output.)
11: Internal synchronous clock (P65 pin is an SSTB1 output.)
Serial I/O initialization bit
0: Serial I/O initialization
1: Serial I/O enabled
Transfer mode selection bit
0: Full duplex (transmit and receive) mode (P50 pin is an SIN1 input.)
1: Transmit-only mode (P50 pin is an I/O port.)
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O1 clock pin selection bit
0:SCLK11 (P53/SCLK12 pin is an I/O port.)
1:SCLK12 (P52/SCLK11 pin is an I/O port.)
b7
b0
Serial I/O1 control register 2
(SIO1CON2 (SC12): address 001A16)
P62/SRDY1 • P64/SBUSY1 pin control bits
0000: Pins P62 and P64 are I/O ports
0001: Not used
0010: P62 pin is an SRDY1 output, P64 pin is an I/O port.
0011: P62 pin is an SRDY1 output, P64 pin is an I/O port.
0100: P62 pin is an I/O port, P64 pin is an SBUSY1 input.
0101: P62 pin is an I/O port, P64 pin is an SBUSY1 input.
0110: P62 pin is an I/O port, P64 pin is an SBUSY1 output.
0111: P62 pin is an I/O port, P64 pin is an SBUSY1 output.
1000: P62 pin is an SRDY1 input, P64 pin is an SBUSY1 output.
1001: P62 pin is an SRDY1 input, P64 pin is an SBUSY1 output.
1010: P62 pin is an SRDY1 input, P64 pin is an SBUSY1 output.
1011: P62 pin is an SRDY1 input, P64 pin is an SBUSY1 output.
1100: P62 pin is an SRDY1 output, P64 pin is an SBUSY1 input.
1101: P62 pin is an SRDY1 output, P64 pin is an SBUSY1 input.
1110: P62 pin is an SRDY1 output, P64 pin is an SBUSY1 input.
1111: P62 pin is an SRDY1 output, P64 pin is an SBUSY1 input.
SBUSY1 output • SSTB1 output function selection bit
(Valid in automatic transfer mode)
0: Functions as each 1-byte signal
1: Functions as signal for all transfer data
Serial transfer status flag
0: Serial transfer completion
1: Serial transferring
SOUT1 pin control bit (at no-transfer serial data)
0: Output active
1: Output high-impedance
P51/SOUT1 P-channel output disable bit
0: CMOS 3-state (P-channel output is valid.)
1: N-channel open-drain (P-channel output is invalid.)
Fig. 22 Structure of serial I/O1 control registers 1, 2
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HARDWARE
FUNCTIONAL DESCRIPTION
(1) Serial I/O1 Operation
When the SCLK1 input is “H” after completion of transfer, set the
SOUT1 pin control bit to “1.”
Either the internal synchronous clock or external synchronous clock
can be selected by the serial I/O1 synchronous clock selection bits
(b2 and b3 of address 001916) of serial I/O1 control register 1 as
synchronous clock for serial transfer.
When the SCLK1 input goes to “L” after the start of the next serial
transfer, the SOUT1 pin control bit is automatically reset to “0” and
put into an output active state.
The internal synchronous clock has a built-in dedicated divider where
7 different clocks are selected by the internal synchronous clock
selection bits (b5, b6 and b7 of address 001C16) of serial I/O1
control register 3.
Regardless of whether the internal synchronous clock or external
synchronous clock is selected, the full duplex mode and the trans-
mit-only mode are available for serial transfer, one of which is se-
lected by the transfer mode selection bit (b5 of address 001916) of
serial I/O1 control register 1.
The P62/SRDY1/AN8, P64/INT4/SBUSY1/AN10, and P65/SSTB1/AN11
pins each select either I/O port or handshake I/O signal by the
serial I/O1 synchronous clock selection bits (b2 and b3 of address
001916) of serial I/O1 control register 1 as well as the P62/SRDY1 •
P64/SBUSY1 pin control bits (b0 to b3 of address 001A16) of serial
I/O1 control register 2.
Either LSB first or MSB first is selected for the I/O sequence of the
serial transfer bit strings by the transfer direction selection bit (b6 of
address 001916) of serial I/O1 control register 1.
When using serial I/O1, first select either 8-bit serial I/O or auto-
matic transfer serial I/O by the serial transfer selection bits (b0 and
b1 of address 001916) of serial I/O1 control register 1, after comple-
tion of the above bit setup. Next, set the serial I/O initialization bit
(b4 of address 001916) of serial I/O1 control register 1 to “1” (Serial
I/O enable) .
For the SOUT1 being used as an output pin, either CMOS output or
N-channel open-drain output is selected by the P51/SOUT1 P-chan-
nel output disable bit (b7 of address 001A16) of serial I/O1 control
register 2.
Either output active or high-impedance can be selected as a SOUT1
pin state at serial non-transfer by the SOUT1 pin control bit (b6 of
address 001A16) of serial I/O1 control register 2. However, when
the external synchronous clock is selected, perform the following
setup to put the SOUT1 pin into a high-impedance state.
When stopping serial transfer while data is being transferred, re-
gardless of whether the internal or external synchronous clock is
selected, reset the serial I/O initialization bit (b4) to “0.”
b7
b0
Serial I/O1 control register 3
(SIO1CON3 (SC13): address 001C16
)
Automatic transfer interval set bits
00000: 2 cycles of transfer clocks
00001: 3 cycles of transfer clocks
:
11110: 32 cycles of transfer clocks
11111: 33 cycles of transfer clocks
Data is written to a latch and read from a decrement counter.
Internal synchronous clock selection bits
000: f(XIN)/4 or f(XCIN)/8
001: f(XIN)/8 or f(XCIN)/16
010: f(XIN)/16 or f(XCIN)/32
011: f(XIN)/32 or f(XCIN)/64
100: f(XIN)/64 or f(XCIN)/128
101: f(XIN)/128 or f(XCIN)/256
110: f(XIN)/256 or f(XCIN)/512
Fig. 23 Structure of serial I/O1 control register 3
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HARDWARE
FUNCTIONAL DESCRIPTION
(2) 8-bit Serial I/O Mode
that the automatic transfer interval setting is valid, a transfer inter-
val is placed before the start of transmission/reception of the first
data and after the end of transmission/reception of the last data.
For SSTB1 output, regardless of the contents of the SBUSY1 output •
SSTB1 output function selection bit (b4), the transfer interval for each
1-byte data is longer than the set value by 2 cycles.
Address 001B16 is assigned to the serial I/O1 register.
When the internal synchronous clock is selected, a serial transfer
of the 8-bit serial I/O is started by a write signal to the serial I/O1
register (address 001B16).
The serial transfer status flag (b5 of address 001A16) of serial I/O1
control register 2 indicates the shift register status of serial I/O1,
and is set to “1” by writing into the serial I/O1 register, which be-
comes a transfer start trigger and reset to “0” after completion of 8-
bit transfer. At the same time, a serial I/O1 interrupt request occurs.
When the external synchronous clock is selected, the contents of
the serial I/O1 register are continuously shifted while transfer clocks
are input to SCLK1. Therefore, the clock needs to be controlled ex-
ternally.
Furthermore, when using a combination of SBUSY1 output and SSTB1
output as a signal for all transfer data, the transfer interval after the
end of transmission/reception of the last data is longer than the set
value by 2 cycles.
When the external synchronous clock is selected, automatic trans-
fer interval setting is disabled.
After completion of the above bit setup, if the internal synchronous
clock is selected, automatic serial transfer is started by writing the
value of “number of transfer bytes - 1” into the transfer counter
(address 001B16).
(3) Automatic Transfer Serial I/O Mode
The serial I/O1 automatic transfer controller controls the write and
read operations of the serial I/O1 register, so the function of ad-
dress 001B16 is used as a transfer counter (1-byte units).
When performing serial transfer through the serial I/O automatic
transfer RAM (addresses 0F0016 to 0FFF16), it is necessary to set
the serial I/O1 automatic transfer data pointer (address 001816)
beforehand.
When the external synchronous clock is selected, write the value of
“number of transfer bytes - 1” into the transfer counter and input an
internal system clock interval of 5 cycles or more. After that, input
transfer clock to SCLK1.
As a transfer interval for each 1-byte data transfer, input an internal
system clock interval of 5 cycles or more from the clock rise time of
the last bit.
Input the low-order 8 bits of the first data store address to be seri-
ally transferred to the automatic transfer data pointer set bits.
When the internal synchronous clock is selected, the transfer inter-
val for each 1-byte data can be set by the automatic transfer inter-
val set bits (b0 to b4 of address 001C16) of serial I/O1 control regis-
ter 3 in the following cases:
Regardless of whether the internal or external synchronous clock
is selected, the automatic transfer data pointer and the transfer
counter are decremented after each 1-byte data is received and
then written into the automatic transfer RAM. The serial transfer
status flag (b5 of address 001A16) is set to “1” by writing data into
the transfer counter. Writing data becomes a transfer start trigger,
and the serial transfer status flag is reset to “0” after the last data is
written into the automatic transfer RAM. At the same time, a serial
I/O1 interrupt request occurs.
1. When using no handshake signal
2. When using the SRDY1 output, SBUSY1 output, and SSTB1 output
of the handshake signal independently
3. When using a combination of SRDY1 output and SSTB1 output or a
combination of SBUSY1 output and SSTB1 output of the handshake
signal
The values written in the automatic transfer data pointer set bits
(b0 to b7 of address 001816) and the automatic transfer interval set
bits (b0 to b4 of address 001C16) are held in the latch.
When data is written into the transfer counter, the values latched in
the automatic transfer data pointer set bits (b0 to b7) and the auto-
matic transfer interval set bits (b0 to b4) are transferred to the
decrement counter.
It is possible to select one of 32 different values, namely 2 to 33
cycles of the transfer clock, as a setting value.
When using the SBUSY1 output and selecting the SBUSY1 output •
SSTB1 output function selection bit (b4 of address 001A16) of serial
I/O1 control register 2 as the signal for all transfer data, provided
b7
b0
Serial I/O1 automatic transfer data pointer
(SIO1DP: address 001816
)
Automatic transfer data pointer set bits
Specify the low-order 8 bits of the first data store address on the serial I/O automatic
transfer RAM. Data is written into the latch and read from the decrement counter.
Fig. 24 Structure of serial I/O1 automatic transfer data pointer
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HARDWARE
FUNCTIONAL DESCRIPTION
Automatic transfer RAM
FFF16
Automatic transfer
data pointer
5216
F5216
F5116
F5016
F4F16
F4E16
Transfer counter
0416
F0016
S
IN1
SOUT1
Serial I/O1 register
Fig. 25 Automatic transfer serial I/O operation
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HARDWARE
FUNCTIONAL DESCRIPTION
(4) Handshake Signal
1. SSTB1 output signal
The SSTB1 output is a signal to inform an end of transmission/re-
ception to the serial transfer destination . The SSTB1 output signal
can be used only when the internal synchronous clock is selected.
In the initial status, namely, in the status in which the serial I/O
initialization bit (b4) is reset to “0,” the SSTB1 output goes to “L,” or
the SSTB1 output goes to “H.”
SBUSY1
SCLK1
SOUT1
At the end of transmit/receive operation, when the data of the serial
I/O1 register is all output from SOUT1, pulses are output in the pe-
riod of 1 cycle of the transfer clock so as to cause the SSTB1 output
to go “H” or the SSTB1 output to go “L.” After that, each pulse is
returned to the initial status in which SSTB1 output goes to “L” or the
SSTB1 output goes to “H.”
Fig. 27 SBUSY1 input operation (internal synchronous clock)
Furthermore, after 1 cycle, the serial transfer status flag (b5) is re-
set to “0.”
When the external synchronous clock is selected, input an “H” level
signal into the SBUSY1 input and an “L” level signal into the SBUSY1
input in the initial status in which transfer is stopped. At this time,
the transfer clocks to be input in SCLK1 become invalid.
During serial transfer, the transfer clocks to be input in SCLK1 be-
come valid, enabling a transmit/receive operation, while an “L” level
signal is input into the SBUSY1 input and an “H” level signal is input
into the SBUSY1 input.
In the automatic transfer serial I/O mode, whether the SSTB1 output
is to be active at an end of each 1-byte data or after completion of
transfer of all data can be selected by the SBUSY1 output • SSTB1
output function selection bit (b4 of address 001A16) of serial I/O1
control register 2.
When changing the input values in the SBUSY1 input and the SBUSY1
input at these operations, change them when the SCLK1 input is in a
high state.
SSTB1
When the high impedance of the SOUT1 output is selected by the
SOUT1 pin control bit (b6), the SOUT1 output becomes active, en-
abling serial transfer by inputting a transfer clock to SCLK1, while an
“L” level signal is input into the SBUSY1 input and an “H” level signal
is input into the SBUSY1 input.
Serial transfer
status flag
SCLK1
SOUT1
SBUSY1
Fig. 26 SSTB1 output operation
2. SBUSY1 input signal
SCLK1
The SBUSY1 input is a signal which receives a request for a stop of
transmission/reception from the serial transfer destination.
When the internal synchronous clock is selected, input an “H” level
signal into the SBUSY1 input and an “L” level signal into the SBUSY1
input in the initial status in which transfer is stopped.
Invalid
SOUT1
(Output high-impedance)
When starting a transmit/receive operation, input an “L” level signal
into the SBUSY1 input and an “H” level signal into the SBUSY1 input in
the period of 1.5 cycles or more of the transfer clock. Then, transfer
clocks are output from the SCLK1 output.
Fig. 28 SBUSY1 input operation (external synchronous clock)
3. SBUSY1 output signal
When an “H” level signal is input into the SBUSY1 input and an “L”
level signal into the SBUSY1 input after a transmit/receive operation
is started, this transmit/receive operation are not stopped immedi-
ately and the transfer clocks from the SCLK1 output is not stopped
until the specified number of bits are transmitted and received.
The handshake unit of the 8-bit serial I/O is 8 bits and that of the
automatic transfer serial I/O is 8 bits.
The SBUSY1 output is a signal which requests a stop of transmis-
sion/reception to the serial transfer destination. In the automatic
transfer serial I/O mode, regardless of the internal or external syn-
chronous clock, whether the SBUSY1 output is to be active at trans-
fer of each 1-byte data or during transfer of all data can be selected
by the SBUSY1 output • SSTB1 output function selection bit (b4).
In the initial status, the status in which the serial I/O initialization bit
(b4) is reset to “0,” the SBUSY1 output goes to “H” and the SBUSY1
output goes to “L.”
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HARDWARE
FUNCTIONAL DESCRIPTION
When the internal synchronous clock is selected, in the 8-bit serial
I/O mode and the automatic transfer serial I/O mode (SBUSY1 out-
put function outputs in 1-byte units), the SBUSY1 output goes to “L”
and the SBUSY1 output goes to “H” before 0.5 cycle (transfer clock)
of the timing at which the transfer clock from the SCLK1 output goes
to “L” at a start of transmit/receive operation.
data is written into the serial I/O1 register to start a transmit opera-
tion, regardless of the serial I/O transfer mode.
At termination of transmit/receive operation, the SBUSY1 output re-
turns to “H” and the SBUSY1 output returns to “L”, the initial status,
when the serial transfer status flag is set to "0", regardless of whether
the internal or external synchronous clock is selected.
In the automatic transfer serial I/O mode (the SBUSY1 output func-
tion outputs all transfer data), the SBUSY1 output goes to “L” and the
SBUSY1 output goes to “H” when the first transmit data is written into
the serial I/O1 register (address 001B16).
Furthermore, in the automatic transfer serial I/O mode (SBUSY1 out-
put function outputs in 1-byte units), the SBUSY1 output goes to “H”
and the SBUSY1 output goes to “L” each time 1-byte of receive data
is written into the automatic transfer RAM.
When the external synchronous clock is selected, the SBUSY1 out-
put goes to “L” and the SBUSY1 output goes to “H” when transmit
SBUSY1
SBUSY1
Serial transfer
status flag
Serial transfer
status flag
SCLK1
SCLK1
SOUT1
Write to Serial
I/O1 register
Fig. 29 SBUSY1 output operation
Fig. 30 SBUSY1 output operation
(internal synchronous clock, 8-bits serial I/O)
(external synchronous clock, 8-bits serial I/O)
Automatic transfer
interval
SCLK1
Serial I/O1 register
→Automatic transfer RAM
Automatic transfer RAM
→Serial I/O1 register
SBUSY1
Serial transfer
status flag
SOUT1
Fig. 31 SBUSY1 output operation in automatic transfer serial I/O mode
(internal synchronous clock, SBUSY1 output function outputs each 1-byte)
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HARDWARE
FUNCTIONAL DESCRIPTION
4. SRDY1 output signal
The SRDY1 output is a transmit/receive enable signal which informs
the serial transfer destination that transmit/receive is ready. In the
initial status, when the serial I/O initialization bit (b4) is reset to “0,”
the SRDY1 output goes to “L” and the SRDY1 output goes to “H”. After
transmitted data is stored in the serial I/O1 register (address 001B16)
and a transmit/receive operation becomes ready, the SRDY1 output
goes to “H” and the SRDY1 output goes to “L”. When a transmit/
receive operation is started and the transfer clock goes to “L”, the
SRDY1 output goes to “L” and the SRDY1 output goes to “H”.
SRDY1
SCLK1
Write to serial
I/O1 register
5. SRDY1 input signal
Fig. 32 SRDY1 output operation
The SRDY1 input signal becomes valid only when the SRDY1 input
and the SBUSY1 output are used. The SRDY1 input is a signal for
receiving a transmit/receive ready completion signal from the serial
transfer destination.
When the internal synchronous clock is selected, input a low level
signal into the SRDY1 input and a high level signal into the SRDY1
input in the initial status in which the transfer is stopped.
When an “H” level signal is input into the SRDY1 input and an “L”
level signal is input into the SRDY1 input for a period of 1.5 cycles or
more of transfer clock, transfer clocks are output from the SCLK1
output and a transmit/receive operation is started.
SRDY1
SCLK1
SOUT1
After the transmit/receive operation is started and an “L” level sig-
nal is input into the SRDY1 input and an “H” level signal into the
SRDY1 input, this operation cannot be immediately stopped.
After the specified number of bits are transmitted and received, the
transfer clocks from the SCLK1 output is stopped. The handshake
unit of the 8-bit serial I/O and that of the automatic transfer serial
I/O are of 8 bits.
Fig. 33 SRDY1 input operation (internal synchronous clock)
When the external synchronous clock is selected, the SRDY1 input
becomes one of the triggers to output the SBUSY1 signal.
To start a transmit/receive operation (SBUSY1 output: “L,” SBUSY1
output: “H”), input an “H” level signal into the SRDY1 input and an “L”
level signal into the SRDY1 input, and also write transmit data into
the serial I/O1 register.
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HARDWARE
FUNCTIONAL DESCRIPTION
Write to serial
I/O1 register
A:
S
CLK1
SCLK1
S
RDY1
S
RDY1
S
RDY1
S
BUSY1
S
BUSY1
SBUSY1
S
CLK1
A:
B:
Internal synchronous
clock selection
External synchronous
clock selection
Write to serial
I/O1 register
B:
Fig. 34 Handshake operation at serial I/O1 mutual connecting (1)
Write to serial
I/O1 register
A:
SCLK1
SRDY1
SCLK1
SRDY1
SRDY1
SBUSY1
SBUSY1
SBUSY1
SCLK1
A:
B:
Internal synchronous
clock selection
External synchronous
clock selection
Write to serial
I/O1 register
B:
Fig. 35 Handshake operation at serial I/O1 mutual connecting (2)
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HARDWARE
FUNCTIONAL DESCRIPTION
ister (address 001D16) to “1.” For clock synchronous serial I/O, the
transmitter and the receiver must use the same clock for serial I/O2
operation. If an internal clock is used, transmit/receive is started by
a write signal to the serial I/O2 transmit/receive buffer register (TB/
RB) (address 001F16).
●Serial I/O2
Serial I/O2 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation during serial I/O2 operation.
(1) Clock Synchronous Serial I/O Mode
When P57 (SCLK22) is selected as a clock I/O pin, SRDY2 output
function is invalid, and P56 (SCLK21) is used as an I/O port.
The clock synchronous serial I/O mode can be selected by setting
the serial I/O2 mode selection bit (b6) of the serial I/O2 control reg-
Data bus
Serial I/O2 control register
Address 001D16
Address 001F16
Receive buffer register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive shift register
P5
P5
4/RXD
Shift clock
“0”
Clock control circuit
6
/SCLK21
/SRDY2/ CLK22
IN
Serial I/O2 clock I/O pin selection bit
P5
7
S
“1”
“0”
“1”
Internal system clock selection bit
Serial I/O2 synchronous clock selection bit
X
“0”
BRG count source selection bit
Division ratio 1/(n+1)
Baud rate generator
Address 001616
1/4
X
CIN
“1”
1/2
BRG clock
switch bit
1/4
Falling edge detector
Clock control circuit
F/F
P57/SRDY2/SCLK22
Transmit shift register shift
completion flag (TSC)
Serial I/O2
clock I/O pin
selection bit
Shift clock
Transmit interrupt source selection bit
Transmit shift register
Transmit buffer register
P55/TXD
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Serial I/O2 status register
Address 001E16
Address 001F16
Data bus
Fig. 36 Block diagram of clock synchronous serial I/O2
Transmit/Receive shift clock
(1/2—1/2048 of internal
clock or external clock)
Serial I/O2 output TxD
Serial I/O2 input RxD
D
D
0
0
D
D
1
1
D
D
2
2
D
D
3
3
D
D
4
4
D
D
5
5
D
D
6
6
D
D
7
7
Receive enable signal SRDY2
Write-in signal to serial I/O2 transmit/receive
buffer register (address 001F16
)
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Overrun error (OE)
detection
Notes
1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting transmit interrupt source selection bit (TIC) of the serial I/O2
control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1.”
Fig. 37 Operation of clock synchronous serial I/O2 function
38B5 Group User’s Manual
1-37
HARDWARE
FUNCTIONAL DESCRIPTION
(2) Asynchronous Serial I/O (UART) Mode
The transmit and receive shift registers each have a buffer (the two
buffers have the same address in memory). Since the shift register
cannot be written to or read from directly, transmit data is written to
the transmit buffer, and receive data is read from the receive buffer.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer can receive 2-byte data continuously.
The asynchronous serial I/O (UART) mode can be selected by clear-
ing the serial I/O2 mode selection bit (b6) of the serial I/O2 control
register (address 001D16) to “0.” Eight serial data transfer formats
can be selected and the transfer formats used by the transmitter
and receiver must be identical.
Data bus
Serial I/O2 control register
Address 001D16
Address 001F16
Receive buffer full flag (RBF)
Receive interrupt request (RI)
OE
Receive buffer register
Character length selection bit
7 bit
ST detector
P54/RXD
Receive shift register
1/16
8 bit
UART control register
SP detector
PE FE
Address 001716
Clock control circuit
Serial I/O2 synchronous
clock selection bit
“0”
“1”
Serial I/O2 clock I/O pin
selection bit
P56/SCLK21
P5
7
/SRDY2/SCLK22
X
IN
Internal system clock selection bit
“0”
BRG count source
“1”
1/2
selection bit
“1”
Division ratio 1/(n+1)
Baud rate generator
X
CIN
Address 001616
BRG clock
1/4
switch bit
ST/SP/PA generator
Transmit shift register shift
completion flag (TSC)
1/16
Transmit interrupt source selection bit
Transmit shift register
P55/TXD
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
Transmit buffer register
Serial I/O2 status register
Address 001E16
Address 001F16
Data bus
Fig. 38 Block diagram of UART serial I/O2
Transmit or receive clock
Write-in signal to
transmit buffer register
TBE=0
TSC=0
TBE=1
TBE=0
TBE=1
TSC=1*
SP
D0
D1
D1
Serial I/O2 output T
XD
ST
D0
SP
ST
* Generated at 2nd bit in 2-stop
bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit
Read-out signal from receive
buffer register
RBF=0
RBF=1
SP
RBF=1
SP
D
0
D1
D1
ST
D0
ST
Serial I/O2 input RXD
Fig. 39 Operation of UART serial I/O2 function
38B5 Group User’s Manual
1-38
HARDWARE
FUNCTIONAL DESCRIPTION
[Serial I/O2 Control Register] SIO2CON (001D16
)
ter clears error flags OE, PE, FE, and SE (b3 to b6, respectively).
Writing “0” to the serial I/O2 enable bit (SIOE : b7 of the serial I/O2
control register) also clears all the status flags, including the error
flags.
The serial I/O2 control register contains eight control bits for serial
I/O2 functions.
[UART Control Register] UARTCON (001716)
This is a 7 bit register containing four control bits, which are valid
when UART is selected, two control bits, which are valid when using
serial I/O2, and one control bit, which is always valid.
All bits of the serial I/O2 status register are initialized to “0” at reset,
but if the transmit enable bit (b4) of the serial I/O2 control register
has been set to “1,” the transmit shift register shift completion flag
(b2) and the transmit buffer empty flag (b0) become “1.”
Data format of serial data receive/transfer and the output structure of
the P55/TxD pin, etc. are set by this register.
[Serial I/O2 Transmit Buffer Register/Receive
Buffer Register] TB/RB (001F16)
[Serial I/O2 Status Register] SIO2STS (001E16)
The read-only serial I/O2 status register consists of seven flags (b0
to b6) which indicate the operating status of the serial I/O2 function
and various errors. Three of the flags (b4 to b6) are only valid in the
UART mode. The receive buffer full flag (b1) is cleared to “0” when
the receive buffer is read.
The transmit buffer and the receive buffer are located in the same
address. The transmit buffer is write-only and the receive buffer is
read-only. If a character bit length is 7 bits, the MSB of data stored in
the receive buffer is "0".
[Baud Rate Generator] BRG (001616)
The error detection is performed at the same time data is transferred
from the receive shift register to the receive buffer register, and the
receive buffer full flag is set. A writing to the serial I/O2 status regis-
The baud rate generator determines the baud rate for serial transfer.
With the 8-bit counter having a reload register, the baud rate genera-
tor divides the frequency of the count source by 1/(n+1), where n is
the value written to the baud rate generator.
b7
b0
b7
b0
Serial I/O2 control register
(SIO2CON : address 001D16
Serial I/O2 status register
(SIO2STS : address 001E16
)
)
BRG count source selection bit (CSS)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
0: f(XIN) or f(XCIN)/2 or f(XCIN
)
1: f(XIN)/4 or f(XCIN)/8 or f(XCIN)/4
Serial I/O2 synchronous clock selection bit (SCS)
0: BRG/ 4
(when clock synchronous serial I/O is selected)
BRG/16 (UART is selected)
1: External clock input
(when clock synchronous serial I/O is selected)
External clock input/16 (UART is selected)
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
S
RDY2 output enable bit (SRDY)
Overrun error flag (OE)
0: No error
1: Overrun error
0: P5
7
pin operates as ordinary I/O pin
pin operates as SRDY2 output pin
1: P5
7
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Serial I/O2 mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Not used (returns "1" when read)
Serial I/O2 enable bit (SIOE)
0: Serial I/O2 disabled
b7
b0
(pins P5
1: Serial I/O2 enabled
(pins P5 to P5 operate as serial I/O pins)
4 to P57 operate as ordinary I/O pins)
UART control register
(UARTCON : address 001716
)
4
7
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P55/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
BRG clock switch bit
0: XIN or XCIN (depends on internal system clock)
1: XCIN
Serial I/O2 clock I/O pin selection bit
0: SCLK21 (P5
7
/SCLK22 pin is used as I/O port or SRDY2 output pin.)
/SCLK21 pin is used as I/O port.)
1: SCLK22 (P5
6
Not used (return "1" when read)
Fig. 40 Structure of serial I/O2 related register
38B5 Group User’s Manual
1-39
HARDWARE
FUNCTIONAL DESCRIPTION
FLD Controller
The 38B5 group has fluorescent display (FLD) drive and control cir-
•Toff1 time set register
•Toff2 time set register
cuits.
•Port P0FLD/port switch register
•Port P2FLD/port switch register
•Port P8FLD/port switch register
•Port P8 FLD output control register
•FLD automatic display RAM (max. 160 bytes)
A gradation display mode can be used for bright/dark display as a
display function.
The FLD controller consists of the following components:
•40 pins for FLD control pins
•FLDC mode register
•FLD data pointer
•FLD data pointer reload register
•Tdisp time set register
Main
Local
Main address bus
data bus data bus
FLD/P P2
FLD/P P2
0
1
2
3
4
5
6
7
/FLD
/FLD
/FLD
/FLD
/FLD
/FLD
/FLD
/FLD
0
1
2
3
4
5
6
7
P2
FLD/P
FLD/P P2
P2
0F6016
8
8
8
8
8
FLD/P
FLD/P P2
P2
FLD/P
FLD/P P2
0EFA16
Local address bus
000416
FLD/P P0
FLD/P P0
0
1
2
3
4
5
6
7
/FLD
/FLD
8
9
P0
/FLD10
/FLD11
/FLD12
/FLD13
/FLD14
/FLD15
000016
FLD/P
FLD/P P0
P0
FLD/P
FLD/P P0
P0
0FFF16
FLD/P
FLD/P P0
0EF916
P1
P1
P1
P1
P1
P1
P1
P1
0
1
2
3
4
5
6
7
/FLD16
/FLD17
/FLD18
/FLD19
/FLD20
/FLD21
/FLD22
/FLD23
000216
P3
P3
P3
P3
P3
P3
P3
P3
0
1
2
3
4
5
6
7
/FLD24
/FLD25
/FLD26
/FLD27
/FLD28
/FLD29
/FLD30
FLDC mode register
(0EF416
)
FLD data pointer
reload register
/FLD31
000616
(0EF816
)
P8
0
1
2
3
4
5
6
7
/FLD32
/FLD33
/FLD34
/FLD35
/FLD36
/FLD37
/FLD38
FLD/P
FLD/P P8
FLD/P P8
FLD/P P8
Address
decoder
FLD data pointer
(0EF816
)
P8
P8
FLD/P
FLD/P
FLD/P P8
FLD/P P8
0EFB16
/FLD39
001016
FLD blanking interrupt
FLD digit interrupt
Timing generator
Fig. 41 Block diagram for FLD control circuit
38B5 Group User’s Manual
1-40
HARDWARE
FUNCTIONAL DESCRIPTION
[FLDC Mode Register] FLDM
The FLDC mode register is a 8-bit register respectively which is used
to control the FLD automatic display and to set the blanking time
Tscan for key-scan.
b7
b0
FLDC mode register
(FLDM: address 0EF416
)
Automatic display control bit (P0, P1, P2, P3, P8)
0 : General-purpose mode
1 : Automatic display mode
Display start bit
0 : Stop display
1 : Display
(start to display by switching “0” to “1”)
Tscan control bits
00 : FLD digit interrupt (at rising edge of each digit)
01 : 1 ✕ Tdisp
FLD blanking interrupt
10 : 2 ✕ Tdisp
(at falling edge of the last digit)
11 : 3 ✕ Tdisp
Timing number control bit
0 : 16 timing mode
1 : 32 timing mode
Gradation display mode selection control bit
0 : Not selecting
1 : Selecting (Note)
Tdisp counter count source selection bit
0 : f(XIN)/16 or f(XCIN)/32
1 : f(XIN)/64 or f(XCIN)/128
High-breakdown voltage port drivability selection bit
0 : Drivability strong
1 : Drivability weak
Notes 1: When a gradation display mode is selected, a number of timing is max. 16
timing. (Set the timing number control bit to “0.”)
2: When changing bit 4 (timing number control bit) or bit 5 (gradation display
mode selection control bit), set “0” to bit 1 (display start bit) to perform at
display stop state.
Fig. 42 Structure of FLDC mode register
38B5 Group User’s Manual
1-41
HARDWARE
FUNCTIONAL DESCRIPTION
FLD automatic display pins
This setting is performed by writing a value into the FLD/port switch
register (addresses 0EF916 to 0EFB16) of each port.
When the automatic display control bits of the FLDC mode register
(address 0EF416) are set to “1,” the ports of P0, P1, P2, P3 and P8
are used as FLD automatic display pins.
This setting can be performed in units of bit. When “0” is set, the port
is set to the general-purpose port. When “1” is set, the port is set to
the FLD pin. There is no restriction on whether the FLD pin is to be
used as a segment pin or a digit pin.
When using the FLD automatic display mode, set each port to the
FLD pin or the general-purpose port using the respective switch reg-
ister in accordance with the number of segments and the number of
digits.
Table 9 Pins in FLD automatic display mode
Port Name
Automatic Display Pins
Setting Method
P0, P2,
P80–P83
P1, P3
FLD0–FLD15
FLD32–FLD35
FLD16–FLD31
FLD36–FLD39
The individual bits of the FLD/port switch register (addresses 0EF916–0EFB16) can be set each pin
either FLD port (“1”) or general-purpose port (“0”).
None (FLD only)
P84–P87
The individual bits of the FLD/port switch register (address 0EFB16) can be set each pin to either
FLD port (“1”) or general-purpose port (“0”).
The output can be reversed by the port P8 FLD output control register (address 0EFC16).
The port output format is the CMOS output format. When using the port as a display pin, a driver
must be installed externally.
Setting example 2
Setting example 3
Setting example 4
Setting example 1
18
20
16
10
15
8
25
15
Number of segments
Number of digits
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FLD0(SEG1)
FLD1(SEG2)
FLD2(SEG3)
FLD3(SEG4)
FLD4(SEG5)
FLD5(SEG6)
FLD6(SEG7)
FLD7(SEG8)
P20
P21
P22
P23
P24
P25
P26
P27
0
0
1
1
1
1
1
1
P20
0
0
0
0
0
0
1
1
P20
Port P2
P21
P21
FLD2(SEG1)
P22
FLD3(SEG2)
FLD4(SEG3)
FLD5(SEG4)
FLD6(SEG5)
FLD7(SEG6)
P23
P24
P25
FLD4(SEG1)
FLD5(SEG2)
1
1
1
1
1
1
1
1
FLD8(DIG1)
FLD9(DIG2)
FLD10(DIG3)
FLD11(DIG4)
FLD12(DIG5)
FLD13(DIG6)
FLD14(DIG7)
FLD15(DIG8)
1
0
0
0
0
0
1
1
FLD8(SEG1)
P01
1
1
1
1
1
1
1
1
FLD8(SEG9)
1
1
1
1
1
1
1
1
Port P0
Port P1
Port P3
FLD6(SEG3)
FLD7(SEG4)
FLD8(SEG5)
FLD9(SEG6)
FLD10(SEG7)
FLD11(SEG8)
FLD12(SEG9)
FLD13(SEG10)
FLD9(SEG10)
FLD10(SEG11)
FLD11(SEG12)
FLD12(SEG13)
FLD13(SEG14)
FLD14(SEG15)
FLD15(SEG16)
P02
P03
P04
P05
FLD14(SEG2)
FLD15(SEG3)
FLD16(DIG1)
FLD17(DIG2)
FLD18(DIG3)
FLD19(DIG4)
FLD20(DIG5)
FLD21(DIG6)
FLD22(DIG7)
FLD23(DIG8)
1
1
1
1
1
1
1
1
FLD16(DIG9)
FLD17(DIG10)
FLD18(DIG11)
FLD19(DIG12)
FLD20(DIG13)
FLD21(DIG14)
FLD22(DIG15)
FLD23(DIG16)
FLD16(DIG1)
FLD17(DIG2)
FLD18(DIG3)
FLD19(DIG4)
FLD20(SEG4)
FLD21(SEG5)
FLD22(SEG6)
FLD23(SEG7)
1
1
1
1
0
0
0
0
FLD16(DIG1)
FLD17(DIG2)
FLD18(DIG3)
FLD19(DIG4)
FLD20(DIG5)
FLD21(DIG6)
FLD22(DIG7)
FLD23(DIG8)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FLD24(DIG17)
FLD25(DIG18)
FLD26(DIG19)
FLD27(DIG20)
FLD28(SEG7)
FLD29(SEG8)
FLD30(SEG9)
FLD31(SEG10)
FLD24(DIG9)
FLD25(DIG10)
FLD26(DIG11)
FLD27(DIG12)
FLD28(DIG13)
FLD29(DIG14)
FLD30(DIG15)
FLD31(SEG17)
1
1
1
1
0
0
0
0
FLD24(SEG8)
FLD25(SEG9)
FLD26(SEG10)
FLD27(SEG11)
FLD28(DIG5)
FLD29(DIG6)
FLD30(DIG7)
FLD31(DIG8)
1
FLD24(DIG9)
FLD25(DIG10)
FLD14(SEG11)
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
FLD15(SEG12)
FLD26(SEG13)
FLD27(SEG14)
FLD28(SEG15)
FLD29(SEG16)
FLD32(SEG11)
FLD33(SEG12)
FLD34(SEG13)
FLD35(SEG14)
FLD36(SEG15)
FLD37(SEG16)
FLD38(SEG17)
FLD39(SEG18)
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
FLD32(SEG18)
FLD33(SEG19)
FLD34(SEG20)
FLD35(SEG21)
FLD36(SEG22)
FLD37(SEG23)
FLD38(SEG24)
FLD39(SEG25)
FLD32(SEG12)
FLD33(SEG13)
FLD34(SEG14)
FLD35(SEG15)
P84
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
P80
P81
P82
P83
P84
P85
P86
P87
Port P8
Value of FLDRAM write disable register
If data is set to “1”, data is protected.
This setting does not decide the FLD
port function (SEG/DIG).
P85
P86
P87
Value of FLD/port switch register
Fig. 43 Segment/Digit setting example
38B5 Group User’s Manual
1-42
HARDWARE
FUNCTIONAL DESCRIPTION
FLD automatic display RAM
[FLD Data Pointer and FLD Data Pointer Reload Register]
FLDDP (0EF816)
Both the FLD data pointer and FLD data pointer reload register are
8-bit registers assigned at address 0EF816. When writing data to this
address, the data is written to the FLD data pointer reload register;
when reading data from this address, the value in the FLD data pointer
is read.
The FLD automatic display RAM uses the 160 bytes of addresses
0F6016 to 0FFF16. For FLD, the 3 modes of 16-timing ordinary mode,
16-timing•gradation display mode and 32-timing mode are available
depending on the number of timings and the presence/absence of
gradation display.
The automatic display RAM in each mode is as follows:
(1) 16-timing•Ordinary Mode
The 80 bytes of addresses 0FB016 to 0FFF16 are used as a FLD
display data store area. Because addresses 0F6016 to 0FAF16
are not used as the automatic display RAM, they can be the ordi-
nary RAM or serial I/O automatic transfer RAM.
(2) 16-timing•Gradation Display Mode
The 160 bytes of addresses 0F6016 to 0FFF16 are used. The 80
bytes of addresses 0FB016 to 0FFF16 are used as an FLD dis-
play data store area, while the 80 bytes of addresses 0F6016 to
0FAF16 are used as a gradation display control data store area.
(3) 32-timing Mode
The 160 bytes of addresses 0F6016 to 0FFF16 are used as an
FLD display data store area.
16-timing•ordinary mode
Not used
16-timing•gradation display mode
32-timing mode
0F6016
0F6016
0F6016
Gradation display
control data stored
area
1 to 32 timing display
data stored area
0FB016
0FB016
0FFF16
1 to 16 timing display
data stored area
1 to 16 timing display
data stored area
0FFF16
0FFF16
Fig. 44 FLD automatic display RAM assignment
38B5 Group User’s Manual
1-43
HARDWARE
FUNCTIONAL DESCRIPTION
Data setup
(1) 16-timing•Ordinary Mode
Number of FLD segments: 15
Number of timing: 8
(FLD data pointer reload register = 7)
Bit
The area of addresses 0FB016 to 0FFF16 are used as a
FLD automatic display RAM.
Address
7
6
5
4
3
2
1
0
0FB016
The last timing
(The last data of FLDP2)
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
0FEA16
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
0FFA16
0FFB16
0FFC16
0FFD16
0FFE16
0FFF16
Note:
When data is stored in the FLD automatic display RAM,
the last data of FLD port P2 is stored at address 0FB016,
the last data of FLD port P0 is stored at address 0FC016,
the last data of FLD port P1 is stored at address 0FD016,
the last data of FLD port P3 is stored at address 0FE016,
and the last data of FLD port P8 is stored at address 0FF016,
to assign in sequence from the last data respectively.
The first data of the FLD port P2, P0, P1, P3, and P8 is stored at
an address which adds the value of (the timing number – 1) to the
corresponding address 0FB016, 0FC016, 0FD016, 0FE016, and
0FF016.
Timing for start
(The first data of FLDP2)
FLDP2 data area
The last timing
(The last data of FLDP0)
Set the FLD data pointer reload register to the value given by the
timing number – 1. “1” is always written to bits 7, 6, and 5. Note
that “0” is always read from bits 7, 6, and 5 when reading. “1” is
always set to bit 4, but this bit become written value when read-
ing.
Timing for start
(The first data of FLDP0)
FLDP0 data area
(2) 16-timing•Gradation Display Mode
Display data setting is performed in the same way as that of the
16-timing•ordinary mode. Gradation display control data is ar-
ranged at an address resulting from subtracting 005016 from
the display data store address of each timing and pin. Bright dis-
play is performed by setting “0,” and dark display is performed by
setting “1.”
The last timing
(The last data of FLDP1)
Set the FLD data pointer reload register to the value given by the
timing number – 1. “1” is always written to bits 7, 6, and 5. Note
that “0” is always read from bits 7, 6, and 5 when reading. “1” is
always set to bit 4, but this bit become written value when read-
ing.
Timing for start
(The first data of FLDP1)
FLDP1 data area
(3) 32-timing Mode
The last timing
(The last data of FLDP3)
The area of addresses 0F6016 to 0FFF16 are used as a FLD au-
tomatic display RAM. When data is stored in the FLD automatic
display RAM, the last data of FLD port P2 is stored at address
0F6016, the last data of FLD port P0 is stored at address 0F8016,
the last data of FLD port P1 is stored at address 0FA016,
the last data of FLD port P3 is stored at address 0FC016,
and the last data of FLD port P8 is stored at address 0FE016,
to assign in sequence from the last data respectively.
The first data of the FLD port P2, P0, P1, P3, and P8 is stored
at an address which adds the value of (the timing number – 1)
to the corresponding address 0F6016, 0F8016, 0FA016, 0FC016,
and 0FE016.
Timing for start
(The first data of FLDP3)
FLDP3 data area
The last timing
(The last data of FLDP8)
Set the FLD data pointer reload register to the value given by
the timing number –1. “1” is always written to bits 7, 6, and 5.
Note that “0” is always read from bits 7, 6, and 5 when reading.
Timing for start
(The first data of FLDP8)
FLDP8 data area
shaded area is used for segment.
shaded area is used for digit.
Fig. 45 Example of using FLD automatic display RAM in
16-timing•ordinary mode
38B5 Group User’s Manual
1-44
HARDWARE
FUNCTIONAL DESCRIPTION
Number of FLD segments: 25
Number of timing: 15
(FLD data pointer reload register = 14)
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Address
Address
0FB016
0F6016
0F6116
0F6216
0F6316
0F6416
0F6516
0F6616
0F6716
0F6816
0F6916
0F6A16
0F6B16
0F6C16
0F6D16
0F6E16
0F6F16
0F7016
0F7116
0F7216
0F7316
0F7416
0F7516
0F7616
0F7716
0F7816
0F7916
0F7A16
0F7B16
0F7C16
0F7D16
0F7E16
0F7F16
0F8016
0F8116
0F8216
0F8316
0F8416
0F8516
0F8616
0F8716
0F8816
0F8916
0F8A16
0F8B16
0F8C16
0F8D16
0F8E16
0F8F16
0F9016
0F9116
0F9216
0F9316
0F9416
0F9516
0F9616
0F9716
0F9816
0F9916
0F9A16
0F9B16
0F9C16
0F9D16
0F9E16
0F9F16
0FA016
0FA116
0FA216
0FA316
0FA416
0FA516
0FA616
0FA716
0FA816
0FA916
0FAA16
0FAB16
0FAC16
0FAD16
0FAE16
0FAF16
The last timing
The last timing
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
0FEA16
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
0FFA16
0FFB16
0FFC16
0FFD16
0FFE16
0FFF16
Note:
(The last data of FLDP2)
(The last data of FLDP2)
FLDP2 gradation
display data area
FLDP2 data area
Timing for start
(The first data of FLDP2)
The last timing
Timing for start
(The first data of FLDP2)
The last timing
(The last data of FLDP0)
(The last data of FLDP0)
FLDP0 gradation
display data area
FLDP0 data area
Timing for start
(The first data of FLDP0)
The last timing
Timing for start
(The first data of FLDP0)
The last timing
(The last data of FLDP1)
(The last data of FLDP1)
FLDP1 gradation
display data area
FLDP1 data area
Timing for start
(The first data of FLDP1)
The last timing
Timing for start
(The first data of FLDP1)
The last timing
(The last data of FLDP3)
(The last data of FLDP3)
FLDP3 gradation
display data area
FLDP3 data area
Timing for start
(The first data of FLDP3)
The last timing
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP8)
(The last data of FLDP8)
FLDP8 gradation
display data area
FLDP8 data area
Timing for start
(The first data of FLDP8)
Timing for start
(The first data of FLDP8)
shaded area is used for segment.
shaded area is used for digit.
Note:
shaded area is used for gradation display data.
Fig. 46 Example of using FLD automatic display RAM in 16-timing•gradation display mode
38B5 Group User’s Manual
1-45
HARDWARE
FUNCTIONAL DESCRIPTION
Number of FLD segments: 18
Number of timing: 20
(FLD data pointer reload register = 19)
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Address
Address
The last timing
0FB016
0F6016
0F6116
0F6216
0F6316
0F6416
0F6516
0F6616
0F6716
0F6816
0F6916
0F6A16
0F6B16
0F6C16
0F6D16
0F6E16
0F6F16
0F7016
0F7116
0F7216
0F7316
0F7416
0F7516
0F7616
0F7716
0F7816
0F7916
0F7A16
0F7B16
0F7C16
0F7D16
0F7E16
0F7F16
0F8016
0F8116
0F8216
0F8316
0F8416
0F8516
0F8616
0F8716
0F8816
0F8916
0F8A16
0F8B16
0F8C16
0F8D16
0F8E16
0F8F16
0F9016
0F9116
0F9216
0F9316
0F9416
0F9516
0F9616
0F9716
0F9816
0F9916
0F9A16
0F9B16
0F9C16
0F9D16
0F9E16
0F9F16
0FA016
0FA116
0FA216
0FA316
0FA416
0FA516
0FA616
0FA716
0FA816
0FA916
0FAA16
0FAB16
0FAC16
0FAD16
0FAE16
0FAF16
(The last data of FLDP2)
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
0FEA16
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
0FFA16
0FFB16
0FFC16
0FFD16
0FFE16
0FFF16
Note:
Timing for start
(The first data of FLDP1)
FLDP2 data area
The last timing
(The last data of FLDP3)
Timing for start
(The first data of FLDP2)
FLDP3 data area
The last timing
(The last data of FLDP0)
Timing for start
(The first data of FLDP3)
FLDP0 data area
The last timing
(The last data of FLDP8)
Timing for start
(The first data of FLDP0)
FLDP8 data area
The last timing
(The last data of FLDP1)
Timing for start
(The first data of FLDP8)
FLDP1 data area
shaded area is used for segment.
shaded area is used for digit.
Fig. 47 Example of using FLD automatic display RAM in 32-timing mode
38B5 Group User’s Manual
1-46
HARDWARE
FUNCTIONAL DESCRIPTION
Digit data protect function
The FLD automatic display RAM is provided with a data protect
function that disables the RAM area data to be rewritten as digit
data.
This function can disable data from being written in optional bits in
the RAM area corresponding to P1 to P3. A programming load can
be reduced by protecting an area that requires no change after
data such as digit data is written.
Write digit data beforehand; then set “1” in the corresponding bits.
With this, the setting is completed.
The data protect area becomes the maximum RAM area of P1 and
P3. For example, when bit 0 of P1 is protected in the 16-
timing•ordinary mode, bits 0 of RAM addresses 0FD016 to 0FDF16
can be protected. Likewise, in the 16-timing•gradation display mode,
bits 0 of addresses 0FD016 to 0FDF16 and 0F8016 to 0F8F16 can be
protected. In the 32-timing mode, bits 0 of addresses 0FA016 to
0FBF16 can be protected.
b7
b7
b0
b0
P1FLDRAM write disable register
(P1FLDRAM : address 0EF216
P3FLDRAM write disable register
)
(P3FLDRAM : address 0EF316
FLDRAM corresponding to P3
FLDRAM corresponding to P3
)
FLDRAM corresponding to P1
FLDRAM corresponding to P1
0
0
1
1
FLDRAM corresponding to P1
FLDRAM corresponding to P1
2
3
FLDRAM corresponding to P3
FLDRAM corresponding to P3
2
3
FLDRAM corresponding to P1
FLDRAM corresponding to P1
FLDRAM corresponding to P1
FLDRAM corresponding to P1
4
5
6
7
FLDRAM corresponding to P3
FLDRAM corresponding to P3
FLDRAM corresponding to P3
FLDRAM corresponding to P3
4
5
6
7
0: Operating normally
1: Write disabled
0: Operating normally
1: Write disabled
Fig. 48 Structure of FLDRAM write disable register
38B5 Group User’s Manual
1-47
HARDWARE
FUNCTIONAL DESCRIPTION
Setting method when using the grid scan type FLD
When using the grid scan type FLD, set “1” in the RAM area corre-
sponding to the digit ports that output “1” at each timing. Set “0” in
the RAM area corresponding to the other digit ports.
Number of FLD segments: 16
Number of timing: 10
(FLD data pointer reload register = 9)
Bit
7
6
5
4
3
2
1
0
Address
0FB016
0FB116
0FB216
The last timing
(The last data of FLDP2)
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
Number of timing: 10
FLDP2 data area
The first second third.......................9th
10th
Timing for start
(The first data of FLDP2)
DIG10 (P3
1
)
)
)
DIG9 (P3
0
7
The last timing
(The last data of FLDP0)
DIG8 (P1
FLDP0 data area
Timing for start
(The first data of FLDP0)
DIG2 (P1
1
)
)
The last timing
(The last data of FLDP1)
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
DIG1 (P1
0
Segment output
FLDP1 data area
Timing for start
(The first data of FLDP1)
Fig. 49 Example of digit timing using grid scan type
The last timing
(The last data of FLDP3)
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
FLDP3 data area
0FE816
0FE916
0FEA16
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
0FFA16
0FFB16
0FFC16
0FFD16
0FFE16
0FFF16
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP8)
FLDP8 data area
Timing for start
(The first data of FLDP8)
Note:
shaded area is used for segment.
shaded area is used for digit.
Fig. 50 Example of using FLD automatic display RAM
using grid scan type
38B5 Group User’s Manual
1-48
HARDWARE
FUNCTIONAL DESCRIPTION
Timing setting
Key-scan
Each timing is set by the FLDC mode register, Tdisp time set regis-
ter, Toff1 time set register, and Toff2 time set register.
•Tdisp time setting
When a key-scan is performed with the segment during key-scan
blanking period Tscan, take the following sequence:
1. Write “0” to bit 0 of the FLDC mode register (address 0EF416).
2. Set the port corresponding to the segment for key-scan to the
output port.
Set the Tdisp time by the Tdisp counter count source selection bit of
the FLDC mode register and the Tdisp time set register.
Supposing that the value of the Tdisp time set register is n, the
Tdisp time is represented as Tdisp = (n+1) ✕ t (t: count source
synchronization).
3. Perform the key-scan.
4. After the key-scan is performed, write “1” to bit 0 of FLDC mode
register (address 0EF416).
When the Tdisp counter count source selection bit of the FLDC mode
register is “0” and the value of the Tdisp time set register is 200
(C816), the Tdisp time is: Tdisp = (200+1) ✕ 4 (at XIN= 4 MHz) = 804
µs. When reading the Tdisp time set register, the value in the
counter is read out.
■ Note
When performing a key-scan according to the above step 1 to 4, take
the following points into consideration.
1. Do not set “0” in bit 1 of the FLDC mode register (address 0EF416).
2. Do not set “1” in the ports corresponding to digits.
•Toff1 time setting
Set the Toff1 time by the Toff1 time set register.
Supposing that the value of the Toff1 time set register is n1, the
Toff1 time is represented as Toff1 = n1 ✕ t.
When the Tdisp counter count source selection bit of the FLDC mode
register is “0” and the value of the Toff1 time set register is 30
(1E16), Toff1 = 30 ✕ 4 (at XIN = 4 MHz) = 120 µs.
Set a value of 0316 or more to the Toff1 time set register (address
0EF616).
•Toff2 time setting
Set the Toff2 time by the Toff2 time set register.
Supposing that the value of the Toff2 time set register is n2, the
Toff2 time is represented as Toff2 = n2 ✕ t.
When the Tdisp counter count source selection bit of the FLDC mode
register is “0” and the value of the Toff2 time set register is 180
(B416), Toff2 = 180 ✕ 4 (at XIN = 4 MHz) = 720 µs.
This Toff2 time setting is valid only for FLD ports which are in the
gradation display mode and whose gradation display control RAM
value is “1.”
When setting “1” to bit 7 of the P8FLD output control register (ad-
dress 0EFC16), set a value of 0316 or more to the Toff2 time set
register (address 0EF716).
FLD automatic display start
To perform FLD automatic display, set the following registers.
•Port P0FLD/port switch register
•Port P2FLD/port switch register
•Port P8FLD/port switch register
•FLDC mode register
•Tdisp time set register
•Toff1 time set register
•Toff2 time set register
•FLD data pointer
FLD automatic display mode is selected by writing “1” to the bit 0 of
the FLDC mode register (address 0EF416), and the automatic dis-
play is started by writing “1” to bit 1. During FLD automatic display,
bit 1 of the FLDC mode register (address 0EF416) always keeps “1,”
and FLD automatic display can be interrupted by writing “0” to bit 1.
38B5 Group User’s Manual
1-49
HARDWARE
FUNCTIONAL DESCRIPTION
Repeat synchronous
Tdisp
Tscan
Tn Tn-1 Tn-2
T4
T3
T2
T1
Segment
Digit output
Segment setting by software
FLD digit interrupt request occurs at the rising
edge of digit (each timing).
FLD blanking interrupt request occurs
at the falling edge of the last timing.
Segment
Digit
Toff1
Tdisp
Segment
Digit
When a gradation display mode is selected
Pin under the condition that bit 5 of the
FLDC mode register is “1,” and the
corresponding gradation display control
data value is “1.”
Toff1
Toff2
Tdisp
n: Number of timing
Fig. 51 FLDC timing
38B5 Group User’s Manual
1-50
HARDWARE
FUNCTIONAL DESCRIPTION
P84 to P87 FLD output reverse function
P84 to P87 are provided with a function to reverse the polarity of the
FLD output. This function is useful in adjusting the polarity when
using an externally installed driver.
Segment
Digit
The output polarity can be reversed by setting “1” to bit 0 of the port
P8 FLD output control register.
At Toff2 control bit = “0” in
gradation display mode
(at gradation display
control data= “1”)
At Toff2 control bit = “1” in
gradation display mode
(at gradation display
control data= “1”)
P84 to P87 FLDRAM write disable function
This function can disable writing data in the RAM area correspond-
ing to P84 to P87. This function can be set by setting “1” to bit 1 of the
port P8FLD output control register (address 0EFC16).
Toff1
Toff2
Tdisp
P84 to P87 Toff invalid function
P84 to P87 can output waveform in which Toff is invalid, when P84 to
Dimmer signal
P87 is selected FLD ports (See Figure 52).
P84–P87
The function is useful when using a 4 bits →16 bits decoder. The Toff
can be invalid by setting “1” to bit 2 of the port P8FLD output control
register (address 0EFC16).
Toff invalid
P84–P87
Toff invalid
Delay
P84 to P87 output delay function
16 µs
P84 to P87 can output waveform in which is delayed for 16 µs, when
selecting FLD port and selecting Toff invalid function (See Figure
52). When using a 4 bits →16 bits decoder, the function can be use-
ful for prevention of leak radiation caused by phase discrepancy be-
tween segment output waveform and digit output waveform. This func-
tion can be set by setting “1” to bit 3 of the port P8FLD output control
register (address 0EFC16).
Fig. 52 P84 to P87 FLD output waveform
Toff2 SET/RESET change function
The value of the Toff2 time set register is valid when gradation dis-
play mode is selected. The FLD ports output (set) the data of display
RAM at the end of the Toff1 time and output “0” (reset) at the end of
the Toff2 time, when bit 7 of the port P8FLD output control register is
“0”.
Dimmer signal output function
P63 can output the dimmer signal. When using a 4 bits →16 bits
decoder, the dimmer signal can be used as a control signal for a 4
bits →16 bits decoder. When using M35501FP, the dimmer signal
can be used as the CLK signal. The dimmer signal can be output by
setting “1” to bit 4 of the port P8FLD output control register (address
0EFC16).
The FLD ports output (set) the data of display RAM at the end of the
Toff2 time and output “0” (reset) at the end of Tdisp time, when bit 7
of the port P8FLD output control register is “1”.
b7
b0
Port P8FLD output control register
(P8FLDCON: address 0EFC16
)
P84–P87 FLD output reverse bit
0: Output normally
1: Reverse output
P84–P87 FLDRAM write disable bit
0: Operating normally
1: Write disabled
P84–P87 Toff invalid bit
0: Operating normally
1: Toff invalid
P84–P87 delay control bit (Note)
0: No delay
1: Delay
P63/AN9 dimmer output control bit
0: Ordinary port
1: Dimmer output
Not used (“0” at reading)
Toff2 control bit
0: Gradation display data is reset at Toff2
(set at Toff1)
1: Gradation display data is set at Toff2
(reset at Tdisp)
Note: Valid only when selecting FLD port and P84–P87 Toff invalid function
Fig. 53 Structure of port P8 FLD output control register
38B5 Group User’s Manual
1-51
HARDWARE
FUNCTIONAL DESCRIPTION
A-D Converter
conversion interrupt request bit to “1.”
The 38B5 group has a 10-bit A-D converter. The A-D converter per-
Note that the comparator is constructed linked to a capacitor, so set
f(XIN) to at least 250 kHz during A-D conversion. Use a CPU system
clock dividing the main clock XIN as the internal system clock.
forms successive approximation conversion.
[A-D Conversion Register] AD
One of these registers is a high-order register, and the other is a low-
order register. The high-order 8 bits of a conversion result is stored
in the A-D conversion register (high-order) (address 003416), and
the low-order 2 bits of the same result are stored in bit 7 and bit 6 of
the A-D conversion register (low-order) (address 003316).
During A-D conversion, do not read these registers.
b7
b0
A-D control register
(ADCON: address 003216
)
Analog input pin selection bits
0000: P7 /AN
0001: P7 /AN
0
0
1
1
0010: P7
0011: P7
0100: P7
0101: P7
0110: P7
0111: P7
1000: P6
1001: P6
1010: P6
1011: P6
2
3
4
5
6
7
2
3
4
5
/AN
/AN
/AN
/AN
/AN
/AN
/SRDY1/AN
/AN
/INT
2
3
4
5
6
7
[A-D Control Register] ADCON
This register controls A-D converter. Bits 3 to 0 are analog input pin
selection bits. Bit 4 is an AD conversion completion bit and “0” during
A-D conversion. This bit is set to “1” upon completion of A-D conver-
sion.
8
9
4
/SBUSY1/AN10
/SSTB1/AN11
A-D conversion is started by setting “0” in this bit.
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between AVSS
Not used (returns “0” when read)
and VREF, and outputs the divided voltages.
b7
b0
[Channel Selector]
A-D conversion register (high-order)
(ADH: address 003416
)
The channel selector selects one of the input ports P77/AN7–P70/
AN0, and P65/SSTB1/AN11–P62/SRDY1/AN8 and inputs it to the com-
parator.
AD conversion result stored bits
When port P64 is selected as an analog input pin, an external inter-
rupt function (INT4) is invalid.
b7
b0
A-D conversion register (low-order)
(ADL: address 003316
)
[Comparator and Control Circuit]
Not used (returns “0” when read)
AD conversion result stored bits
The comparator and control circuit compares an analog input
voltage with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
Fig. 54 Structure of A-D control register
Data bus
b7
b0
A-D control register
4
P70/AN0
P71/AN1
A-D control circuit
A-D interrupt request
P72/AN2
P73/AN3
Comparator
A-D conversion register (H) A-D conversion register (L)
P74/AN4
P75/AN5
(Address 003416)
(Address 003316)
P76/AN6
P77/AN7
Resistor ladder
P62/SRDY1/AN8
P63/AN9
P64/INT4/SBUSY1/AN10
P65/SSTB1/AN11
AVSS
@VREF
Fig. 55 Block diagram of A-D converter
38B5 Group User’s Manual
1-52
HARDWARE
FUNCTIONAL DESCRIPTION
Pulse Width Modulation (PWM)
The 38B5 group has a PWM function with a 14-bit resolution. When
the oscillation frequency XIN is 4 MHz, the minimum resolution bit
width is 250 ns and the cycle period is 4096 µs. The PWM timing
generator supplies a PWM control signal based on a signal that is
the frequency of the XIN clock.
The explanation in the rest assumes XIN = 4 MHz.
Data bus
PWM register (low-order)
(address 001516)
It is set to “1”
when write.
bit7
bit5
bit0
bit0
bit7
PWM register (high-order)
(address 001416)
PWM latch (14-bit)
MSB
LSB
14
P87 latch
P87/PWM0
PWM
14-bit PWM circuit
P87/PWM output
selection bit
When an internal
XCIN
1/2
system clock
P87/PWM output
selection bit
selection bit is set
to “0”
(64 µs cycle)
Timing
generating
unit for PWM
“1”
“0”
P87 direction
register
XIN
(4MHz)
(4096 µs cycle)
Fig. 56 PWM block diagram
38B5 Group User’s Manual
1-53
HARDWARE
FUNCTIONAL DESCRIPTION
1. Data setup
The PWM output pin also function as port P87. Set port P87 to be the
PWM output pin by setting bit 0 of the PWM control register (address
002616) to “1.” The high-order 8 bits of output data are set in the
high-order PWM register PWMH (address 001416) and the low-order
6 bits are set in the low-order PWM register PWML (address 001516).
3. Transfer from register to latch
Data written to the PWML register is transferred to the PWM latch
once in each PWM period (every 4096 µs), and data written to the
PWMH register is transferred to the PWM latch once in each sub-
period (every 64 µs). When the PWML register is read, the contents
of the latch are read. However, bit 7 of the PWML register indicates
whether the transfer to the PWM latch is completed; the transfer is
completed when bit 7 is “0.”
2. PWM operation
The timing of the 14-bit PWM function is shown in Figure 57.
The 14-bit PWM data is divided into the low-order 6 bits and the
high-order 8 bits in the PWM latch.
Table 10 Relationship between low-order 6-bit data and setting
period of ADD bit
The high-order 8 bits of data determine how long an “H” level signal
is output during each sub-period. There are 64 sub-periods in each
period, and each sub-period t is 256 ✕ τ (= 64 µs) long. The signal’s
“H” has a length equal to N times τ, and its minimum resolution = 250
ns.
Low-order
Sub-periods tm lengthened (m = 0 to 63)
6-bit data
LSB
0 0 0 0 0 0 None
0 0 0 0 0 1 m = 32
0 0 0 0 1 0 m = 16, 48
The last bit of the sub-period becomes the ADD bit which is specified
either “H” or “L,” by the contents of PWML. As shown in Table 10, the
ADD bit is decided either “H” or “L.”
0 0 0 1 0 0 m = 8, 24, 40, 56
0 0 1 0 0 0 m = 4, 12, 20, 28, 36, 44, 52, 60
0 1 0 0 0 0 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62
1 0 0 0 0 0 m = 1, 3, 5, 7, .................................................., 57, 59, 61, 63
That is, only in the sub-period tm shown in Table 10 in the PWM
cycle period T = 64t, the “H” duration is lengthened during the mini-
mum resolution width τ period in comparison with the other period.
For example, if the high-order eight bits of the 14-bit data are “0316”
and the low-order six bits are “0516,” the length of the “H” level output
in sub-periods t8, t24, t32, t40 and t56 is 4 τ, and its length 3 τ in all
other sub-periods.
Time at the “H” level of each sub-period almost becomes equal be-
cause the time becomes length set in the high-order 8 bits or be-
comes the value plus τ, and this sub-period t (= 64 µs, approximate
15.6 kHz) becomes cycle period approximately.
4096 µs
64 µs
64 µs
m = 7
64 µs
64 µs
64 µs
m = 0
m = 8
m = 9
m = 63
15.75 µs
15.75 µs
15.75 µs
16.0 µs
15.75 µs
15.75 µs
15.75 µs
Pulse width modulation register H: 00111111
Pulse width modulation register L: 000101
Sub-periods where “H” pulse width is 16.0 µs: m = 8, 24, 32, 40, 56
Sub-periods where “H” pulse width is 15.75 µs: m = all other values
Fig. 57 PWM timing
38B5 Group User’s Manual
1-54
HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
PWM control register
(PWMCON: address 002616)
P87/PWM output selection bit
0: I/O port
1: PWM output
Not used (return “0” when read)
Fig. 58 Structure of PWM control register
Data 6A16 stored at address 001416
5916 6A16
Data 2416 stored at address 001516
1316 A416
Data 7B16 stored at address 001416
PWM register
(high-order)
7B16
Bit 7 cleared after transfer
2416
Data 3516 stored at address 001516
3516
PWM register
(low-order)
Transfer from register to latch
1AA416
Transfer from register to latch
1EF516
B516
1EE416
PWM latch
(14-bit)
165316
1A9316
1AA416
When bit 7 of PWML is “0,” transfer
from register to latch is disabled.
T = 4096 µs
(64 ✕ 64 µs)
t = 64 µs
6A 6B 6A 6B 6A 6B 6A 6B 6A 6B 6B 6B 6A 6B 6A 6B 6A 6B 6A
6B 6A 6B 6A 6B 6A 6B 6A
(Example 1)
PWM output
1
Low-order 6-bits
output
5
5
5
5
5
2
5
5
5
5
5
5
5
5
5
H = 6A16
L = 2416
6B16............36 times
(107)
6A16............28 times
(106)
106 ✕ 64 + 36
6A 6A 6A 6A 6B 6A 6B 6A 6B 6A 6A 6A 6B 6A 6B 6A 6B 6A 6A
6A 6B 6A 6B 6A 6B 6A 6A
(Example 2)
PWM output
Low-order 6 bits
output
4
3
4
4
3
4
4
3
4
H = 6A16
6B16............24 times
6A16............40 times
106 ✕ 64 + 24
L = 1816
t = 64 µs
(256 ✕ 0.25 µs)
Minimum bit width
τ
= 0.25 µs
PWM output
2
..........
..........
.........
6B 6A 69 68 67
ADD
02 01 00 FF FE FD FC
02 01
6A 69 68 67
02 01
ADD
02 01 00 FF FE FD FC
............
..........
8-bit counter
..........
97 96 95
97 96 95
The ADD portions with
additional are determined
either “H” or “L” by low-order
6-bit data.
τ
“H” period length specified by PWMH
256 (64 µs), fixed
τ
Fig. 59 14-bit PWM timing
38B5 Group User’s Manual
1-55
HARDWARE
FUNCTIONAL DESCRIPTION
Interrupt Interval Determination Function
The 38B5 group has an interrupt interval determination circuit.
This interrupt interval determination circuit has an 8-bit binary up
counter. Using this counter, it determines a duration of time from the
rising edge (falling edge) of an input signal pulse on the P47/INT2 pin
to the rising edge (falling edge) of the signal pulse that is input next.
How to determine the interrupt interval is described below.
1. Enable the INT2 interrupt by setting bit 2 of the interrupt control
register 1 (address 003E16). Select the rising interval or falling
interval by setting bit 2 of the interrupt edge selection register
(address 003A16).
Noise filter
The P47/INT2 pin builds in the noise filter.
The noise filter operation is described below.
1. Select the sampling clock of the input signal with bits 2 and 3 of
the interrupt interval determination control register. When not
using the noise filter, set “00.”
2. The P47/INT2 input signal is sampled in synchronization with the
selected clock. When sampling the same level signal in a series
of three sampling, the signal is recognized as the interrupt
signal, and the interrupt request occurs.
When setting bit 4 of interrupt interval determination control
register to “1,” the interrupt request can occur at both rising and
falling edges.
2. Set bit 0 of the interrupt interval determination control register
(address 003116) to “1” (interrupt interval determination operat-
ing).
When using the noise filter, set the minimum pulse width of the
INT2 input signal to 3 cycles or more of the sample clock.
3. Select the sampling clock of 8-bit binary up counter by setting bit
1 of the interrupt interval determination control register. When
writing “0,” f(XIN)/128 is selected (the sampling interval: 32 µs at
f(XIN) = 4.19 MHz); when “1,” f(XIN)/256 is selected (the sampling
interval: 64 µs at f(XIN) = 4.19 MHz).
Note: In the low-speed mode (CM7 = 1), the interrupt interval deter-
mination function cannot operate.
4. When the signal of polarity which is set on the INT2 pin (rising or
falling edge) is input, the 8-bit binary up counter starts count-
ing up of the selected counter sampling clock.
5. When the signal of polarity above 4 is input again, the value of the
8-bit binary up counter is transferred to the interrupt interval
determination register (address 003016), and the remote control
interrupt request occurs. Immediately after that, the 8-bit binary
up counter continues to count up again from “0016.”
6. When count value reaches “FF16,” the 8-bit binary up counter stops
counting up. Then, simultaneously when the next counter sam-
pling clock is input, the counter sets value “FF16” to the interrupt
interval determination register to generate the counter overflow
interrupt request.
f(XIN)/128
f(XIN)/256
Counter sampling
clock selection bit
8-bit binary up
counter
Counter overflow
interrupt request
or remote control
interrupt request
INT2 interrupt input
Noise filter
Interrupt interval
determination register
address 003016
One-sided/both-sided
detection selection bit
Noise filter sampling
clock selection bit
1/128
1/64
Data bus
1/32
Divider
f(XIN)
Fig. 60 Interrupt interval determination circuit block diagram
38B5 Group User’s Manual
1-56
HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
Interrupt interval determination control register
(IIDCON: address 003116
)
Interrupt interval determination circuit operating selection bit
0 : Stopped
1 : Operating
Counter sampling clock selection bit
0 : f(XIN)/128
1 : f(XIN)/256
Noise filter sampling clock selection bits (INT
00 : Filter stop
2)
01 : f(XIN)/32
10 : f(XIN)/64
11 : f(XIN)/128
One-sided/both-sided edge detection selection bit
0 : One-sided edge detection
1 : Both-sided edge detection (can be used when using a noise filter)
Not used (return “0” when read)
Fig. 61 Structure of interrupt interval determination control register
(When IIDCON4 = “0”)
Noise filter
sampling clock
INT pin
2
Acceptance of
interrupt
Counter sampling
clock
FF
N
FE
6
5
4
3
8-bit binary up
counter value
3
2
2
1
1
1
0
0
0
FF
6
N
Interrupt interval
determination
register value
N
FF
6
Remote control
interrupt request
Counter overflow
interrupt request
Remote control
interrupt request
Fig. 62 Interrupt interval determination operation example (at rising edge active)
(When IIDCON
Noise filter
4 = “1”)
sampling clock
INT pin
2
Acceptance of
interrupt
Counter sampling
clock
FF
FE
N
3
2
2
2
2
2
1
1
1
3
1
1
8-bit binary up
counter value
0
0
0
0
0
N
2
3
2
FF
Interrupt interval
determination
register value
N
2
FF
Counter overflow
interrupt request
Remote control
interrupt request
Remote control
interrupt request
Remote control
interrupt request
Remote control
interrupt request
Fig. 63 Interrupt interval determination operation example (at both-sided edge active)
38B5 Group User’s Manual
1-57
HARDWARE
FUNCTIONAL DESCRIPTION
Watchdog Timer
“0,” the underflow signal of watchdog timer L becomes the count
source. The detection time is set then to f(XIN) = 2.1 s at 4 MHz
frequency and f(XCIN) = 512 s at 32 kHz frequency.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because
of a software runaway). The watchdog timer consists of an 8-bit watch-
dog timer L and a 12-bit watchdog timer H.
When this bit is set to “1,” the count source becomes the signal
divided by 8 for f(XIN) (or divided by 16 for f(XCIN)). The detection
time in this case is set to f(XIN) = 8.2 ms at 4 MHz frequency and
f(XCIN) = 2 s at 32 KHz frequency. This bit is cleared to “0” after
resetting.
●Standard operation of watchdog timer
When any data is not written into the watchdog timer control register
(address 002B16) after resetting, the watchdog timer is in the stop
state. The watchdog timer starts to count down by writing an optional
value into the watchdog timer control register (address 002B16) and
an internal reset occurs at an underflow of the watchdog timer H.
Accordingly, programming is usually performed so that writing to the
watchdog timer control register (address 002B16) may be started
before an underflow. When the watchdog timer control register
(address 002B16) is read, the values of the high-order 6 bits of the
watchdog timer H, STP instruction disable bit, and watchdog timer H
count source selection bit are read.
(3) Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 002B16) permits
disabling the STP instruction when the watchdog timer is in opera-
tion.
When this bit is “0,” the STP instruction is enabled.
When this bit is “1,” the STP instruction is disabled.
Once the STP instruction is executed, an internal resetting occurs.
When this bit is set to “1,” it cannot be rewritten to “0” by program.
This bit is cleared to “0” after resetting.
(1) Initial value of watchdog timer
■ Note
At reset or writing to the watchdog timer control register (address
002B16), a watchdog timer H is set to “FFF16” and a watchdog timer
L to “FF16.”
When releasing the stop mode, the watchdog timer performs its count
operation even in the stop release waiting time. Be careful not to
cause the watchdog timer H to underflow in the stop release waiting
time, for example, by writing data in the watchdog timer control reg-
ister (address 002B16) before executing the STP instruction.
(2) Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 002B16) permits
selecting a watchdog timer H count source. When this bit is set to
“FF16” is set when
watchdog timer
control register is
written to.
Data bus
“FFF16” is set
when watchdog
timer control
register is written
to.
X
CIN
1/2
“0”
“1”
“0”
Watchdog timer L (8)
Internal system clock
selection bit
(Note)
Watchdog timer H (12)
“1”
1/8
Watchdog timer H count
source selection bit
X
IN
STP instruction disable bit
STP instruction
Reset
circuit
Internal reset
RESET
Note: Either high-speed, middle-speed or low-speed mode is selected by bit 7 of CPU mode register.
Fig. 64 Block diagram of watchdog timer
b0
b7
Watchdog timer control register
(WDTCON : address 002B16
)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/8 or f(XCIN)/16
Fig. 65 Structure of watchdog timer control register
38B5 Group User’s Manual
1-58
HARDWARE
FUNCTIONAL DESCRIPTION
Buzzer Output Circuit
The 38B5 group has a buzzer output circuit. One of 1 kHz, 2 kHz and
4 kHz (at XIN = 4.19 MHz) frequencies can be selected by the buzzer
output control register (address 0EFD16). Either P43/BUZ01 or P20/
BUZ02/FLD0 can be selected as a buzzer output port by the output
port selection bits (b2 and b3 of address 0EFD16).
The buzzer output is controlled by the buzzer output ON/OFF bit
(b4).
Port latch
1/1024
1/2048
1/4096
f(XIN
)
Buzzer output
Divider
Buzzer output ON/OFF bit
Output port control signal
Port direction register
Fig. 66 Block diagram of buzzer output circuit
b7
b0
Buzzer output control register
(BUZCON: address 0EFD16
)
Output frequency selection bits (XIN = 4.19 MHz)
00 : 1 kHz (f(XIN)/4096)
01 : 2 kHz (f(XIN)/2048)
10 : 4 kHz (f(XIN)/1024)
11 : Not available
Output port selection bits
00 : P2
01 : P4
10 : P2
0
3
0
and P4
/BUZ01 functions as a buzzer output.
/BUZ02/FLD functions as a buzzer output.
3 function as ordinary ports.
0
11 : Not available
Buzzer output ON/OFF bit
0 : Buzzer output OFF (“0” output)
1 : Buzzer output ON
Not used (return “0” when read)
Fig. 67 Structure of buzzer output control register
38B5 Group User’s Manual
1-59
HARDWARE
FUNCTIONAL DESCRIPTION
Reset Circuit
______
Poweron
(Note)
To reset the microcomputer, RESET pin should be held at an “L”
______
level for 2 µs or more. Then the RESET pin is returned to an “H” level
(the power source voltage should be between 2.7 V and 5.5 V, and
the oscillation should be stable), reset is released. After the reset is
completed, the program starts from the address contained in address
FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make
sure that the reset input voltage is less than 0.5 V for VCC of 2.7 V
(switching to the high-speed mode, a power source voltage must be
between 4.0 V and 5.5 V).
Power source
voltage
0V
RESET
VCC
Reset input
voltage
0V
0.2VCC
Note : Reset release voltage ; Vcc=2.7 V
RESET
V
CC
Power source
voltage detection
circuit
Fig. 68 Reset circuit example
X
IN
φ
RESET
Internal
reset
ADH, ADL
Address
?
?
?
?
FFFC
FFFD
ADH
Data
ADL
SYNC
X
IN: about 4000 cycles
Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN)=4 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 69 Reset sequence
38B5 Group User’s Manual
1-60
HARDWARE
FUNCTIONAL DESCRIPTION
Address Register contents
Address Register contents
000016
000116
000216
000416
000516
000616
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001716
001916
001A16
001C16
001D16
001E16
002016
002116
002216
002316
002416
002516
002616
002816
(1)
(2)
(3)
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
8016
0016
0016
0016
0016
8016
FF16
(33)
Timer 34 mode register
002916
002A16
Port P0
0016
0016
3F16
FF16
Port P0 direction register
Port P1
(34)
(35)
(36)
(37)
(38)
(39)
(40)
(41)
Timer 56 mode register
Watchdog timer control register
Timer X (low-order)
002B16
002C16
002D16
002E16
002F16
(4) Port P2
(5) Port P2 direction register
(6) Port P3
FF16
0016
Timer X (high-order)
Timer X mode register 1
Timer X mode register 2
0016
0016
1016
(7)
(8)
(9)
Port P4
Port P4 direction register
Port P5
Interrupt interval determination
control register
A-D control register
003116
003216
(10) Port P5 direction register
(11) Port P6
(42)
(43)
(44)
(45)
(46)
(47)
(48)
(49)
(50)
(51)
(52)
(53)
(54)
(55)
(56)
(57)
(58)
(59)
(60)
(61)
(62)
(63)
003916
003A16
003B16
003C16
003D16
003E16
003F16
0EF016
0EF116
0EF216
0EF316
0EF416
0EF516
0EF616
0EF716
0EF916
0EFA16
0EFB16
0EFC16
0EFD16
Interrupt source switch register
Interrupt edge selection register
CPU mode register
0016
0016
(12) Port P6 direction register
0 1 0 0 1 0 0 0
(13)
(14)
(15)
Port P7
Interrupt request register 1
Interrupt request register 2
Interrupt control register 1
Interrupt control register 2
Pull-up control register 1
0016
0016
0016
0016
0016
0016
0016
Port P7 direction register
Port P8
(16) Port P8 direction register
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
Port P9
Port P9 direction register
UART control register
Serial I/O1 control register 1
Serial I/O1 control register 2
Serial I/O1 control register 3
Serial I/O2 control register
Serial I/O2 status register
Timer 1
Pull-up control register 2
P1FLDRAM write disable register
P3FLDRAM write disable register
FLDC mode register
0016
0016
0016
FF16
FF16
0016
0016
0016
0016
0016
Tdisp time set register
Toff1 time set register
Toff2 time set register
Port P0FLD/port switch register
Port P2FLD/port switch register
Port P8FLD/port switch register
Port P8FLD output control register
Timer 2
0116
FF16
FF16
Timer 3
Timer 4
Timer 5
FF16
FF16
0016
0016
Buzzer output control register
Processor status register
Program counter
Timer 6
(PS) ✕ ✕ ✕ ✕ ✕
✕ ✕
1
PWM control register
Timer 12 mode register
(PCH)
(PCL)
FFFD16 contents
FFFC16 contents
✕: Not fixed
Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.
Fig. 70 Internal status at reset
38B5 Group User’s Manual
1-61
HARDWARE
FUNCTIONAL DESCRIPTION
Clock Generating Circuit
●Oscillation control
The 38B5 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance with
the resonator manufacturer's recommended values. No
external resistor is needed between XIN and XOUT since a feedback
resistor exists on-chip. However, an external feedback resistor is
needed between XCIN and XCOUT.
(1) Stop mode
If the STP instruction is executed, the internal system clock stops at
an “H” level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16”
and timer 2 is set to “0116.”
Either XIN divided by 8 or XCIN divided by 16 is input to timer 1 as
count source, and the output of timer 1 is connected to timer 2. The
bits of the timer 12 mode register are cleared to “0.” Set the interrupt
enable bits of the timer 1 and timer 2 to disabled (“0”) before execut-
ing the STP instruction. Oscillator restarts when an external interrupt
is received, but the internal system clock is not supplied to the CPU
until timer 1 underflows. This allows time for the clock circuit oscilla-
tion to stabilize.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
●Frequency control
(1) Middle-speed mode
The internal system clock is the frequency of XIN divided by 4. After
reset, this mode is selected.
(2) Wait mode
If the WIT instruction is executed, the internal system clock stops at
an “H” level. The states of XIN and XCIN are the same as the state
before executing the WIT instruction. The internal system clock re-
starts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after the
clock is restarted.
(2) High-speed mode
The internal system clock is the frequency of XIN.
(3) Low-speed mode
The internal system clock is the frequency of XCIN divided by 2.
■Note
If you switch the mode between middle/high-speed and low-speed,
stabilize both XIN and XCIN oscillations. The sufficient time is required
for the sub clock to stabilize, especially immediately after power on
and at returning from stop mode. When switching the mode between
middle/high-speed and low-speed, set the frequency on condition
that f(XIN) > 3f(XCIN).
X
CIN
XCOUT
XIN
XOUT
(4) Low power consumption mode
Rf
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set bit
5 of the CPU mode register to “1.” When the main clock XIN is re-
started (by setting the main clock stop bit to “0”), set enough time for
oscillation to stabilize.
Rd
C
OUT
C
COUT
CIN
C
CIN
By clearing furthermore the XCOUT drivability selection bit (b3) of CPU
mode register to “0,” low power consumption operation of less than
200 µA (f(XCIN) = 32 kHz) can be realized by reducing the drivability
between XCIN and XCOUT. At reset or during STP instruction execu-
tion this bit is set to “1” and a strong drivability that has an easy
oscillation start is set.
Fig. 71 Ceramic resonator circuit
X
CIN
X
COUT
X
IN
XOUT
open
open
External oscillation circuit
External oscillation circuit
or external pulse
CC
V
V
CC
SS
V
SS
V
Fig. 72 External clock input circuit
38B5 Group User’s Manual
1-62
HARDWARE
FUNCTIONAL DESCRIPTION
XCOUT
XCIN
“0”
“1”
Port X
C
switch bit (Note 3)
1/2
Timer 2 count source
selection bit (Note 2)
Timer 1 count source
selection bit (Note 2)
Internal system clock
XOUT
XIN
selection bit (Notes 1, 3)
“1”
“0”
Low-speed mode
“1”
Timer 1
Timer 2
“0”
1/4
1/2
“0”
“1”
High-speed or
middle-speed
mode
Main clock division ratio
selection bits (Note 3)
Middle-speed mode
“1”
Timing φ (internal clock)
“0”
High-speed or
low-speed mode
Main clock stop bit
(Note 3)
Q
S
R
S
R
Q
Q
S
R
STP instruction
STP instruction
WIT instruction
Reset
Interrupt disable flag l
Interrupt request
Notes 1: When low-speed mode is selected, set the port Xc switch bit (b4) to “1.”
2: Refer to the structure of the timer 12 mode register.
3: Refer to the structure of the CPU mode register.
Fig. 73 Clock generating circuit block diagram
38B5 Group User’s Manual
1-63
HARDWARE
FUNCTIONAL DESCRIPTION
Reset
High-speed mode
Middle-speed mode
(φ =4 MHz)
(φ =1 MHz)
CM6
“1”
CM7=0(4 MHz selected)
CM6=0(high-speed)
CM5=0(XIN oscillating)
“0”
CM7=0(4 MHz selected)
CM6=1(middle-speed)
CM5=0(XIN oscillating)
CM4=0(32 kHz stopped)
CM4=0(32 kHz stopped)
Middle-speed mode
High-speed mode
CM6
(φ =1 MHz)
(φ =4 MHz)
“1”
“1”
“1”
“0”
“0”
“0”
CM7=0(4 MHz selected)
CM6=1(middle-speed)
CM5=0(XIN oscillating)
CM4=1(32 kHz oscillating)
CM7=0(4 MHz selected)
CM6=0(high-speed)
CM5=0(XIN oscillating)
CM4=1(32 kHz oscillating)
Low-speed mode
(φ =16 kHz)
Low-speed mode
(φ =16 kHz)
CM6
CM7=1(32 kHz selected)
CM6=1(middle-speed)
CM5=0(XIN oscillating)
CM4=1(32 kHz oscillating)
CM7=1(32 kHz selected)
CM6=0(high-speed)
CM5=0(XIN oscillating)
CM4=1(32 kHz oscillating)
b7
b4
CPU mode register
(CPUM : address 003B16)
CM4 : Port Xc switch bit
0: I/O port function
1: XCIN-XCOUT oscillating function
CM5 : Main clock (XIN- XOUT) stop bit
0: Oscillating
1: Stopped
CM6: Main clock division ratio selection bit
0: f(XIN) (High-speed mode)
1: f(XIN)/4 (Middle-speed mode)
CM7: Internal system clock selection bit
0: XIN–XOUT selected (Middle-/High-speed mode)
1: XCIN–XCOUT selected (Low-speed mode)
Low-power dissipation mode
Low-power dissipation mode
(
=16 kHz)
φ
(
φ
=16 kHz)
CM6
CM7=1(32 kHz selected)
CM6=1(middle-speed)
CM5=1(XIN stopped)
CM7=1(32 kHz selected)
CM6=0(high-speed)
CM5=1(XIN stopped)
CM4=1(32 kHz oscillating)
CM4=1(32 kHz oscillating)
Notes 1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2: The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait
mode is ended.
3: Timer operates in the wait mode.
4: When the stop mode is ended, a delay of approximately 1 ms occurs by Timer 1 in middle-/high-speed mode.
5: When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 in low-speed mode.
6: The example assumes that 4 MHz is being applied to the X IN pin and 32 kHz to the X CIN pin. φ indicates the internal system clock.
Fig. 74 State transitions of system clock
38B5 Group User’s Manual
1-64
HARDWARE
NOTES ON PROGRAMMING/NOTES ON USE
NOTES ON PROGRAMMING
A-D Converter
Processor Status Register
The comparator uses internal capacitors whose charge will be lost if
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” After a
reset, initialize flags which affect program execution. In particular, it
is essential to initialize the index X mode (T) and the decimal mode
(D) flags because of their effect on calculations.
the clock frequency is too low.
Therefore, make sure that f(XIN) is at least on 250 kHz during an A-D
conversion.
Do not execute the STP or WIT instruction during an A-D conver-
sion.
Interrupts
Instruction Execution Time
The contents of the interrupt request bits do not change immediately
after they have been written. After writing to an interrupt request reg-
ister, execute at least one instruction before performing a BBC or
BBS instruction.
The instruction execution time is obtained by multiplying the frequency
of the internal system clock by the number of cycles needed to ex-
ecute an instruction.
The number of cycles required to execute an instruction is shown in
the list of machine instructions.
Decimal Calculations
The frequency of the internal system clock is the same of the XIN
frequency in high-speed mode.
•To calculate in decimal notation, set the decimal mode flag (D) to
“1,” then execute an ADC or SBC instruction. Only the ADC and
SBC instructions yield proper decimal results. After executing an
ADC or SBC instruction, execute at least one instruction before ex-
ecuting a SEC, CLC, or CLD instruction.
At STP Instruction Release
At the STP instruction release, all bits of the timer 12 mode register
are cleared.
•In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
The XCOUT drivability selection bit (the CPU mode register) is set to
“1” (high drive) in order to start oscillating.
Timers
NOTES ON USE
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n+1).
Notes on Built-in EPROM Version
The P47 pin of the One Time PROM version or the EPROM version
functions as the power source input pin of the internal EPROM.
Therefore, this pin is set at low input impedance, thereby being af-
fected easily by noise.
Multiplication and Division Instructions
•The index X mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
•The execution of these instructions does not change the contents of
the processor status register.
To prevent a malfunction due to noise, insert a resistor (approx. 5
kΩ) in series with the P47 pin.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
•The data transfer instruction (LDA, etc.)
•The operation instruction when the index X mode flag (T) is “1”
•The addressing mode which uses the value of a direction register
as an index
•The bit-test instruction (BBC or BBS, etc.) to a direction register
•The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a
direction register.
Use instructions such as LDM and STA, etc., to set the port direction
registers.
Serial I/O
•Using an external clock
When using an external clock, input “H” to the external clock input
pin and clear the serial I/O interrupt request bit before executing
serial I/O transfer and serial I/O automatic transfer.
•Using an internal clock
When using an internal clock, set the synchronous clock to the in-
ternal clock, then clear the serial I/O interrupt request bit before ex-
ecuting a serial I/O transfer and serial I/O automatic transfer.
38B5 Group User’s Manual
1-65
HARDWARE
DATA REQUIRED FOR MASK ORDERS/DATA REQUIRED FOR ROM WRITING ORDERS/ROM PROGRAMMING METHOD
DATA REQUIRED FOR MASK ORDERS
ROM PROGRAMMING METHOD
The following are necessary when ordering a mask ROM produc-
The built-in PROM of the blank One Time PROM version and the
EPROM version can be read or programmed with a general purpose
PROM programmer using a special programming adapter. Set the
address of PROM programmer in the user ROM area.
tion:
(1) Mask ROM Order Confirmation Form
(2) Mark Specification Form
(3) Data to be written to ROM, in EPROM form (three identical cop-
ies)
Table 11 Special programming adapter
Package
80P6N-A
80D0
Name of Programming Adapter
PCA7438F-80A
DATA REQUIRED FOR ROM WRITING OR-
DERS
The following are necessary when ordering a ROM writing:
(1) ROM Writing Confirmation Form
(2) Mark Specification Form
PCA7438L-80A
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 75 is recommended to verify programming.
(3) Data to be written to ROM, in EPROM form (three identical cop-
ies)
Programming with PROM
programmer
Screening (Note)
(150°C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Note:
Fig. 75 Programming and testing of One Time PROM version
38B5 Group User’s Manual
1-66
HARDWARE
MASK OPTION OF PULL-DOWN RESISTOR
MASK OPTION OF PULL-DOWN RESISTOR
(object product: M38B5XMXH-XXXFP)
Whether built-in pull-down resistors are connected or not to high-
breakdown voltage ports P20 to P27 and P80 to P83 can be specified
in ordering mask ROM. The option type can be specified from among
8 types; A to G, P as shown Table 12.
Power Dissipation Calculating example 1
● Fixed number depending on microcomputer’s standard
• VOH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value 43 V / 900 µA = 48 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V ✕
15 mA = 75 mW
Table 12 Mask option type of pull-down resistor
Connective port of pull-down resistor
Option
type
(connected at “1” writing)
Restriction
● Fixed number depending on use condition
• Apply voltage to VEE pin: Vcc – 45 V
P20 P21
P22 P23 P24 P25 P26 P27 P80 P81 P82 P83
A ($41)
B ($42)
C ($43)
D ($44)
E ($45)
F ($46)
G ($47)
• Timing number 17; digit number 16; segment number 20
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: 31
• All segment number during repeat cycle: 340 (= 17 ✕ 20)
• Total number of built-in resistor: for digit; 16, for segment; 20
• Digit pin current value: 18 (mA)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P ($50)
(Note 4)
• Segment pin current value: 3 (mA)
Notes 1: The electrical characteristics of high-breakdown voltage ports
P20 to P27 and P80 to P83’s built-in pull-down resistors are the
same as that of high-breakdown voltage ports P00 to P07.
2: The absolute maximum ratings of power dissipation may be
exceed owing to the number of built-in pull-down resistor. After
calculating the power dissipation, specify the option type.
3: One time PROM version and EPROM version cannot be
specified whether built-in pull-down resistors are connected or not
likewise option type A.
(1) Digit pin power dissipation
{18 ✕ 16 ✕ (1–1/16) ✕ 2} / 17 = 31.77 mW
(2) Segment pin power dissipation
{3 ✕ 31 ✕ (1–1/16) ✕ 2} / 17 = 10.26 mW
(3) Pull-down resistor power dissipation (digit)
2
(45 – 2) /48 ✕ (16 ✕ 16/16) ✕ (1 – 1/16) / 17 = 33.99 mW
4: INT3 function and CNTR1 function cannot be used in the option
type P.
(4) Pull-down resistor power dissipation (segment)
2
(45 – 2) /48 ✕ (31 ✕ 20/20) ✕ (1 – 1/16) / 17 = 65.86 mW
Power Dissipation Calculating Method
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 75 mW
(1) + (2)+ (3) + (4) + (5) = 217 mW
● Fixed number depending on microcomputer’s standard
• VOH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value 43 V / 900 µA = 48 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V ✕
15 mA = 75 mW
DIG0
DIG1
DIG2
● Fixed number depending on use condition
• Apply voltage to VEE pin: Vcc – 45 V
DIG3
• Timing number a; digit number b; segment number c
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: d
• All segment number during repeat cycle: c (= a ✕ c)
• Total number of built-in resistor: for digit; f, for segment; g
• Digit pin current value h (mA)
DIG14
DIG15
DIG16
• Segment pin current value i (mA)
1
2
3
14
15
16
17
Timing number
Repeat cycle
(1) Digit pin power dissipation
Tscan
{h ✕ b ✕ (1–Toff/Tdisp) ✕ voltage} / a
(2) Segment pin power dissipation
Fig. 76 Digit timing waveform (1)
{i ✕ d ✕ (1–Toff/Tdisp) ✕ voltage} / a
(3) Pull-down resistor power dissipation (digit)
{power dissipation per 1 digit ✕ (b ✕ f / b) ✕ (1–Toff/Tdisp) } / a
(4) Pull-down resistor power dissipation (segment)
{power dissipation per 1 segment ✕ (d ✕ g / c) ✕ (1–Toff/Tdisp) } / a
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 75 mW
(1) + (2)+ (3) + (4) + (5) = X mW
38B5 Group User’s Manual
1-67
HARDWARE
MASK OPTION OF PULL-DOWN RESISTOR
Power Dissipation Calculating example 2
(when 2 or more digit is turned ON at same
time)
● Fixed number depending on microcomputer’s standard
• VOH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value 43 V / 900 µA = 48 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V ✕
15 mA = 75 mW
● Fixed number depending on use condition
• Apply voltage to VEE pin: Vcc – 45 V
• Timing number 11; digit number 12; segment number 24
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: 114
• All segment number during repeat cycle: 264 (= 11 ✕ 24)
• Total number of built-in resistor: for digit; 10, for segment; 22
• Digit pin current value: 18 (mA)
• Segment pin current value: 3 (mA)
(1) Digit pin power dissipation
{18 ✕ 12 ✕ (1–1/16) ✕ 2} / 11 = 36.82 mW
(2) Segment pin power dissipation
{3 ✕ 114 ✕ (1–1/16) ✕ 2} / 11 = 58.30 mW
(3) Pull-down resistor power dissipation (digit)
2
(45 – 2) /48 ✕ (12 ✕ 10/12) ✕ (1 – 1/16) / 11 = 32.84 mW
(4) Pull-down resistor power dissipation (segment)
2
(45 – 2) /48 ✕ (114 ✕ 22/24) ✕ (1 – 1/16) / 11 = 343.08 mW
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 75 mW
(1) + (2)+ (3) + (4) + (5) = 547 mW
DIG0
DIG1
DIG2
DIG3
DIG4
DIG5
DIG6
DIG7
DIG8
DIG9
1
2
3
4
5
6
7
8
9
10
11
Timing number
Repeat cycle
Tscan
Fig. 77 Digit timing waveform (2)
38B5 Group User’s Manual
1-68
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
higher-priority interrupt is accepted first. This priority is determined
by hardware, but various priority processing can be performed by
software, using an interrupt enable bit and an interrupt disable flag.
For interrupt sources, vector addresses and interrupt priority, refer to
Table 13.
FUNCTIONAL DESCRIPTION SUPPLEMENT
Interrupt
38B5 group permits interrupts on the basis of 21 sources.
It is vector interrupts with a fixed priority system. Accordingly, when
two or more interrupt requests occur during the same sampling, the
Table 13 Interrupt sources, vector addresses and interrupt priority
Vector Addresses (Note 1)
Interrupt source
Priority
Remarks
High
Low
Reset (Note 2)
1
2
3
4
FFFD16
FFFB16
FFF916
FFF716
Non-maskable
FFFC16
FFFA16
FFF816
FFF616
INT0
External interrupt (active edge selectable)
External interrupt (active edge selectable)
External interrupt (active edge selectable)
Valid when interrupt interval determination is operating
Valid when serial I/O1 ordinary mode is selected
Valid when serial I/O1 automatic transfer mode is selected
INT1
INT2
Remote control/counter overflow
Serial I/O1
Serial I/O1 automatic transfer
Timer X
5
FFF516
FFF416
6
7
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
Timer 1
Timer 2
8
STP release timer underflow
Timer 3
9
Timer 4
10
11
12
13
14
(Note 3)
Timer 5
Timer 6
Serial I/O2 receive
INT3
External interrupt (active edge selectable) (Note 4)
Serial I/O2 transmit
INT4
15
FFE116
External interrupt (active edge selectable)
Valid when INT4 interrupt is selected
Valid when A-D conversion is selected
Valid when FLD blanking interrupt is selected
Valid when FLD digit interrupt is selected
Non-maskable software interrupt
FFE016
A-D conversion
FLD blanking
FLD digit
16
17
FFDF16
FFDD16
FFDE16
FFDC16
BRK instruction
Notes 1 : Vector addresses contain interrupt jump destination addresses.
2 : Reset function in the same way as an interrupt with the highest priority.
3 : In the mask option type P, timer 4 interrupt whose count source is CNTR1 input cannot be used.
4 : In the mask option type P, INT3 interrupt cannot be used.
38B5 Group User’s Manual
1-69
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Timing After Interrupt
The interrupt processing routine begins with the machine cycle fol-
lowing the completion of the instruction that is currently in execution.
Figure 78 shows a timing chart after an interrupt occurs, and Figure
79 shows the time up to execution of the interrupt processing routine.
φ
SYNC
RD
WR
Address bus
S, SPS S-1, SPS S-2, SPS
BL
BH AL, AH
AL AH
PC
Data bus
Not used
PCH PCL PS
SYNC
: CPU operation code fetch cycle
(This is an internal signal which cannot be observed from the external unit.)
: Vector address of each interrupt
: Jump destination address of each interrupt
: “0016” or “0116”
BL, BH
AL, AH
SPS
Fig. 78 Timing chart after interrupt occurs
Interrupt request occurs
Main routine
Interrupt operation starts
Push onto
stack vector
fetch
Waiting time for
pipeline post-
processing
Interrupt processing routine
0 to 16 cycles
2 cycles
5 cycles
7 to 23 cycles (4 MHz, 1.75 µs to 5.75 µs)
Fig. 79 Time up to execution of interrupt processing routine
38B5 Group User’s Manual
1-70
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
A-D Converter
By repeating the above operations up to the lowest-order bit of the
A-D conversion register, an analog value converts into a digital value.
A-D conversion completes at 61 clock cycles (15.25 µs at f(XIN) = 8
MHz) after it is started, and the result of the conversion is stored into
the A-D conversion register.
A-D conversion is started by setting AD conversion completion bit to
“0.” During A-D conversion, internal operations are performed as fol-
lows.
1. After the start of A-D conversion, A-D conversion register goes to
“0016.”
Concurrently with the completion of A-D conversion, A-D conversion
interrupt request occurs, so that the AD conversion interrupt request
bit is set to “1.”
2. The highest-order bit of A-D conversion register is set to “1,” and
the comparison voltage Vref is input to the comparator. Then, Vref
is compared with analog input voltage VIN.
3. As a result of comparison, when Vref < VIN, the highest-order bit of
A-D conversion register becomes “1.” When Vref > VIN, the high-
est-order bit becomes “0.”
Table 14 Relative formula for a reference voltage VREF of A-D
converter and Vref
When n = 0
Vref = 0
VREF
1024
When n = 1 to 1023
Vref =
✕ n
n:Value of A-D converter (decimal numeral)
Table 15 Change of A-D conversion register during A-D conversion
Change of A-D conversion register
Value of comparison voltage (Vref)
At start of conversion
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VREF
2
First comparison
Second comparison
Third comparison
VREF
2
VREF
±
✽1
0
0
4
VREF
2
VREF
8
VREF
4
±
±
±
✽1 ✽2
0
0
0
1
After completion of tenth
comparison
A result of A-D conversion
✽1 ✽2 ✽3 ✽4 ✽5 ✽6 ✽7 ✽8
VREF
2
VREF
1024
VREF
4
±
±
• • • •
✽9 ✽10
✽1–✽10: A result of the first comparison to the tenth comparison
38B5 Group User’s Manual
1-71
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Figures 80 shows the A-D conversion equivalent circuit, and Figure
81 shows the A-D conversion timing chart.
V
CC
V
SS
V
CC
VSS
About 2 kΩ
V
IN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
7
8
9
Sampling
clock
C
Chopper
amplifier
A-D conversion register (high-order)
A-D conversion register
(low-order)
AD conversion interrupt request
AN10
AN11
b3 b2 b1 b0
A-D control
register
V
ref
V
REF
Built-in
Reference
D-A converter clock
V
SS
Fig. 80 A-D conversion equivalent circuit
φ
Write signal for A-D
control register
61 cycles
AD conversion
completion bit
Sampling clock
Fig. 81 A-D conversion timing chart
38B5 Group User’s Manual
1-72
CHAPTER 2
APPLICATION
2.1 I/O port
2.2 Timer
2.3 Serial I/O
2.4 FLD controller
2.5 A-D converter
2.6 PWM
2.7 Interrupt interval determination
function
2.8 Watchdog timer
2.9 Buzzer output circuit
2.10 Reset circuit
2.11 Clock generating circuit
APPLICATION
2.1 I/O port
2.1 I/O port
This paragraph describes the setting method of I/O port relevant registers, notes etc.
2.1.1 Memory assignment
Address
000016 Port P0 (P0)
000116 Port P0 direction register (P0D)
000216 Port P1 (P1)
000316
000416 Port P2 (P2)
000516 Port P2 direction register (P2D)
000616 Port P3 (P3)
000716
000816 Port P4 (P4)
000916 Port P4 direction register (P4D)
000A16 Port P5 (P5)
000B16 Port P5 direction register (P5D)
000C16 Port P6 (P6)
000D16 Port P6 direction register (P6D)
000E16 Port P7 (P7)
000F16 Port P7 direction register (P7D)
001016 Port P8 (P8)
001116 Port P8 direction register (P8D)
001216 Port P9 (P9)
001316
Port P9 direction register (P9D)
0EF016 Pull-up control register 1 (PULL1)
Pull-up control register 2 (PULL2)
0EF116
Fig. 2.1.1 Memory assignment of I/O port relevant registers
38B5 Group User’s Manual
2-2
APPLICATION
2.1 I/O port
2.1.2 Relevant registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (i = 0, 1, 2, 3, 4, 5, 7, 8)
(Pi: addresses 0016, 0216, 0416, 0616, 0816, 0A16, 0E16, 1016)
b
Name
Functions
At reset R W
0
1
2
3
4
5
6
7
Port Pi0
0
0
0
0
0
0
0
0
●In output mode
Port Pi1
Port Pi2
Port Pi3
Port Pi4
Port Pi5
Port Pi6
Port Pi7
Write •••••••• Port latch
Read •••••••• Port latch
●In input mode
Write •••••••• Port latch
Read •••••••• Value of pin
Fig. 2.1.2 Structure of port Pi (i = 0, 1, 2, 3, 4, 5, 7, 8)
Port P6
b7 b6 b5 b4 b3 b2 b1 b0
Port P6
(P6: address 0C16)
b
Name
Functions
At reset R W
0
1
2
3
4
5
6
7
Port P60
0
0
0
0
0
0
●In output mode
Port P61
Port P62
Port P63
Port P64
Port P65
Write •••••••• Port latch
Read •••••••• Port latch
●In input mode
Write •••••••• Port latch
Read •••••••• Value of pin
Nothing is arranged for these bits. When these
bits are read out, the contents are undefined.
0
0
✕ ✕
✕ ✕
Fig. 2.1.3 Structure of port P6
Port P9
b7 b6 b5 b4 b3 b2 b1 b0
Port P9
(P9: address 1216)
b
0
Name
Port P90
Functions
●In output mode
Write •••••••• Port latch
Read •••••••• Port latch
●In input mode
Write •••••••• Port latch
Read •••••••• Value of pin
At reset R W
0
1
Port P91
0
0
0
0
0
0
0
✕ ✕
✕ ✕
✕ ✕
✕ ✕
✕ ✕
✕ ✕
2
3
4
5
6
7
Nothing is arranged for these bits. When these
bits are read out, the contents are undefined.
Fig. 2.1.4 Structure of port P9
38B5 Group User’s Manual
2-3
APPLICATION
2.1 I/O port
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (i = 0, 2, 4, 5, 7, 8)
(PiD: addresses 0116, 0516, 0916, 0B16, 0F16, 1116)
b
0
Name
Port Pi direction
register
Functions
0 : Port Pi0 input mode
1 : Port Pi0 output mode
At reset R W
0
0 : Port Pi1 input mode
1 : Port Pi1 output mode
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0 : Port Pi3 input mode
1 : Port Pi3 output mode
0 : Port Pi4 input mode
1 : Port Pi4 output mode
0 : Port Pi5 input mode
1 : Port Pi5 output mode
0 : Port Pi6 input mode
1 : Port Pi6 output mode
0 : Port Pi7 input mode
1 : Port Pi7 output mode
(Note)
Note: Bit 7 of the port P4 direction register (address 0916) does not have
direction register function because P47 is input port. When writing to bit 7
of the port P4 direction register, write “0” to the bit.
Fig. 2.1.5 Structure of port Pi (i = 0, 2, 4, 5, 7, 8) direction register
Port P6 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P6 direction register
(P6D: address 0D16)
b
0
Name
Port P6 direction
register
Functions
0 : Port P60 input mode
1 : Port P60 output mode
At reset R W
0
0 : Port P61 input mode
1 : Port P61 output mode
0
0
0
0
0
1
2
3
4
5
0 : Port P62 input mode
1 : Port P62 output mode
0 : Port P63 input mode
1 : Port P63 output mode
0 : Port P64 input mode
1 : Port P64 output mode
0 : Port P65 input mode
1 : Port P65 output mode
Nothing is arranged for these bits. When these
bits are read out, the contents are undefined.
6
7
0
0
✕ ✕
✕ ✕
Fig. 2.1.6 Structure of port P6 direction register
38B5 Group User’s Manual
2-4
APPLICATION
2.1 I/O port
Port P9 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P9 direction register
(P9D: address 1316)
b
0
Name
Port P9 direction
register
Functions
0 : Port P90 input mode
1 : Port P90 output mode
At reset R W
0
0 : Port P91 input mode
1 : Port P91 output mode
0
1
Nothing is arranged for these bits. When these
bits are read out, the contents are undefined.
0
0
2
3
4
5
6
7
✕ ✕
✕ ✕
0
✕ ✕
✕ ✕
✕ ✕
✕ ✕
0
0
0
Fig. 2.1.7 Structure of port P9 direction register
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register 1
(PULL1: address 0EF016)
b
0
Name
Ports P50, P51 pull-
up control
Functions
0: No pull-up
1: Pull-up
At reset R W
0
0: No pull-up
1: Pull-up
Ports P52, P53 pull-
up control
0
0
0
0
0
0
0
1
2
3
4
5
6
7
Ports P54, P55 pull- 0: No pull-up
up control
1: Pull-up
Ports P56, P57 pull-
up control
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
Port P61 pull-up
control
Ports P62, P63 pull-
up control
Ports P64, P65 pull-
up control
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
Note: The pin set to output port is cut off from pull-up control.
Fig. 2.1.8 Structure of pull-up control register 1
38B5 Group User’s Manual
2-5
APPLICATION
2.1 I/O port
Pull-up control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register 2
(PULL2: address 0EF116)
b
0
Name
Ports P70, P71 pull-
up control
Functions
0: No pull-up
1: Pull-up
At reset R W
0
0: No pull-up
1: Pull-up
Ports P72, P73 pull-
up control
0
0
0
0
0
0
0
1
2
3
4
5
6
7
Ports P74, P75 pull- 0: No pull-up
up control
1: Pull-up
Ports P76, P77 pull-
up control
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
Ports P84, P85 pull-
up control
Ports P86, P87 pull-
up control
Ports P90, P91 pull-
up control
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
Note: The pin set to output port is cut off from pull-up control.
Fig. 2.1.9 Structure of pull-up control register 2
2.1.3 Terminate unused pins
Table 2.1.1 Termination of unused pins
Pins
Termination
P1, P3
P5, P6
Open at “H” output state.
1–P6
5
, P7, • Set to the input mode and connect each to VCC or VSS through a resistor of 1 kΩ to
P8
4
–P8
7
, P9
10 kΩ.
• Set to the output mode and open at “L” or “H” output state.
P4
0
–P4
6
, P6
0
• Set to the input mode and connect each to VCC or VSS through a resistor of 1 kΩ to
10 kΩ.
• Set to the output mode and open at “L” output state.
• Set to the input mode and connect each to VCC or VSS through a resistor of 1 kΩ to
10 kΩ.
P0, P2, P8
0
–P8
3
• Set to the output mode and open at “H” output state.
P4
7
Disable INT
Open
2
interrupt and connect to VCC or VSS through a resistor of 1 KΩ to 10 kΩ.
V
X
REF
OUT
Open (only when using external clock)
Connect to VSS (GND).
AVSS, VEE
38B5 Group User’s Manual
2-6
APPLICATION
2.1 I/O port
2.1.4 Notes on use
(1) Notes in standby state
In standby state✽1 for low-power dissipation, do not make input levels of an input port and an I/O port
“undefined”, especially for I/O ports of the P-channel open-drain and the N-channel open-drain.
Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using built-in pull-up resistor, note on varied current values:
• When setting as an input port : Fix its input level
• When setting as an output port : Prevent current from flowing out to external
● Reason
Even when setting as an output port with its direction register, in the following state :
• P-channel......when the content of the port latch is “0”
• N-channel......when the content of the port latch is “1”
the transistor becomes the OFF state, which causes the ports to be the high-impedance state.
Note that the level becomes “undefined” depending on external circuits.
Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the
state that input levels of a input port and an I/O port are “undefined”. This may cause power source
current.
✽1 standby state: stop mode by executing STP instruction
wait mode by executing WIT instruction
(2) N-channel open-drain port
P4
0–P4
2
, P4
5
, P4
6
, P6 of N-channel open-drain output ports have the built-in hysteresis circuit for
0
input. In standby state for low-power dissipation, do not make these pins floating state.
● Reason
When power sources for pull-up of these pins are cut off in standby state, these ports become
floating. Accordingly, a current may flow from Vcc to Vss through the built-in hysteresis circuit.
38B5 Group User’s Manual
2-7
APPLICATION
2.1 I/O port
(3) Modifying port latch of I/O port with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction✽2, the value of the
unspecified bit may be changed.
● Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
•As for bit which is set for input port:
The pin state is read in the CPU, and is written to this bit after bit managing.
•As for bit which is set for output port:
The bit value is read in the CPU, and is written to this bit after bit managing.
Note the following:
•Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
•As for a bit of which is set for an input port, its value may be changed even when not specified
with a bit managing instruction in case where the pin state differs from its port latch contents.
✽2 Bit managing instructions: SEB and CLB instructions
(4) Pull-up control
When each port which has built-in pull-up resistor (P5, P6
1
–P6
5
, P7, P8
4
–P8 , P9) is set to output
7
port, pull-up control of corresponding port become invalid. (Pull-up cannot be set.)
● Reason
Pull-up control is valid only when each direction register is set to the input mode.
2.1.5 Termination of unused pins
(1) Terminate unused pins
➀ Output ports : Open
➁ Input ports :
Connect each pin to VCC or VSS through each resistor of 1 kΩ to 10 kΩ.
As for pins whose potential affects to operation modes such as pin INT or others, select the VCC
pin or the VSS pin according to their operation mode.
➂ I/O ports :
• Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of
1 kΩ to 10 kΩ.
Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the
I/O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the
mode of the ports is switched over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source current may increase in the input
mode. With regard to an effects on the system, thoroughly perform system evaluation on the user
side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
38B5 Group User’s Manual
2-8
APPLICATION
2.1 I/O port
(2) Termination remarks
➀ Input ports and I/O ports :
Do not open in the input mode.
● Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➁ and
➂ shown on the above.
➁ I/O ports :
When setting for the input mode, do not connect to VCC or VSS directly.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and VCC (or VSS).
➂ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to VCC or VSS through
a resistor.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
38B5 Group User’s Manual
2-9
APPLICATION
2.2 Timer
2.2 Timer
This paragraph explains the registers setting method and the notes relevant to the timers.
2.2.1 Memory map
Timer 1 (T1)
Timer 2 (T2)
Timer 3 (T3)
Timer 4 (T4)
Timer 5 (T5)
Timer 6 (T6)
002016
002116
002216
002316
002416
002516
Timer 6 PWM register (T6PWM)
Timer 12 mode register (T12M)
Timer 34 mode register (T34M)
Timer 56 mode register (T56M)
002716
002816
002916
002A16
Timer X (low-order) (TXL)
002C16
002D16
002E16
002F16
Timer X (high-order) (TXH)
Timer X mode register 1 (TXM1)
Timer X mode register 2 (TXM2)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
003C16
003D16
003E16
003F16
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Fig. 2.2.1 Memory map of registers relevant to timers
38B5 Group User’s Manual
2-10
APPLICATION
2.2 Timer
2.2.2 Relevant registers
(1) 8-bit timer
Timer i
b7 b6 b5 b4 b3 b2 b1 b0
Timer i (i = 1, 3, 4, 5, 6)
(Ti: addresses 2016, 2216, 2316, 2416, 2516)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
1
1
1
1
1
1
1
1
• Set timer i count value.
• The value set in this register is written to both
the timer i and the timer i latch at one time.
• When the timer i is read out, the count value
of the timer i is read out.
Fig. 2.2.2 Structure of Timer i (i=1, 3, 4, 5, 6)
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2
(T2: address 2116)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
1
0
0
0
0
0
0
0
• Set timer 2 count value.
• The value set in this register is written to both
the timer 2 and the timer 2 latch at one time.
• When the timer 2 is read out, the count value
of the timer 2 is read out.
Fig. 2.2.3 Structure of Timer 2
Timer 6 PWM register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 6 PWM register
(T6PWM: address 2716)
b
Functions
At reset R W
• In timer 6 PWM1 mode
Undefined
0
1
2
3
4
“L” level width of PWM rectangular waveform is set.
• Duty of PWM rectangular waveform: n/(n + m)
Period: (n + m) × ts
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
n = timer 6 set value
m = timer 6 PWM register set value
ts = timer 6 count source period
At n = 0, all PWM output “L”.
At m = 0, all PWM output “H”.
(However, n = 0 has priority.)
5
6
• Selection of timer 6 PWM1 mode
Set “1” to the timer 6 operation mode selection bit.
7
Fig. 2.2.4 Structure of Timer 6 PWM register
38B5 Group User’s Manual
2-11
APPLICATION
2.2 Timer
Timer 12 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 12 mode register
(T12M: address 2816)
b
0
Name
Timer 1 count stop
bit
Functions
0: Count operation
1: Count stop
At reset R W
0
Timer 2 count stop
bit
Timer 1 count
source selection
bits
0: Count operation
1: Count stop
0
0
1
2
3
4
b3 b2
0 0: f(XIN)/8 or f(XCIN)/16
0 1: f(XCIN)
1 0: f(XIN)/16 or f(XCIN)/32
1 1: f(XIN)/64 or f(XCIN)/128
b5 b4
0 0: Timer 1 underflow
0 1: f(XCIN)
Timer 2 count
source selection
bits
0
0
1 0: External count input
CNTR0
5
1 1: Not available
0: I/O port
1: Timer 1 output
Timer 1 output
selection bit (P45)
0
0
6
7
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
Fig. 2.2.5 Structure of Timer 12 mode register
Timer 34 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 34 mode register
(T34M: address 2916)
b
0
Name
Timer 3 count stop
bit
Functions
0: Count operation
1: Count stop
At reset R W
0
Timer 4 count stop
bit
Timer 3 count
source selection
bits
0: Count operation
1: Count stop
0
0
1
2
3
4
b3 b2
0 0: f(XIN)/8 or f(XCIN)/16
0 1: Timer 2 underflow
1 0: f(XIN)/16 or f(XCIN)/32
1 1: f(XIN)/64 or f(XCIN)/128
b5 b4
0 0: f(XIN)/8 or f(XCIN)/16
0 1: Timer 3 underflow
1 0: External count input
CNTR1 (Note)
Timer 4 count
source selection
bits
0
0
5
1 1: Not available
0: I/O port
1: Timer 3 output
Timer 3 output
selection bit (P46)
0
0
6
7
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
Note: In the mask option type P, CNTR1 function cannot be used.
Fig. 2.2.6 Structure of Timer 34 mode register
38B5 Group User’s Manual
2-12
APPLICATION
2.2 Timer
Timer 56 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 56 mode register
(T56M: address 2A16)
b
0
Name
Timer 5 count stop
Functions
0: Count operation
1: Count stop
At reset R W
0
bit
Timer 6 count stop
bit
Timer 5 count
0: Count operation
1: Count stop
0
0
0
0
0
0
1
2
3
4
0: f(XIN)/8 or f(XCIN)/16
1: Timer 4 underflow
source selection bit
Timer 6 operation
mode selection bit
0: Timer mode
1: PWM mode
b5 b4
Timer 6 count
source selection
bits
0 0: f(XIN)/8 or f(XCIN)/16
0 1: Timer 5 underflow
1 0: Timer 4 underflow
1 1: Not available
0: I/O port
1: Timer 6 output
5
6
Timer 6 (PWM)
output selection bit
(P44)
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
7
Fig. 2.2.7 Structure of Timer 56 mode register
(2) 16-bit timer
Timer X (low-order, high-order)
b7 b6 b5 b4 b3 b2 b1 b0
Timer X (low-order, high-order)
(TXL, TXH: addresses 2C16, 2D16)
b
Functions
At reset R W
• Set timer X count value.
1
1
1
1
1
1
1
1
0
1
2
3
• When the timer X write control bit of the timer
X mode register 1 is “0”, the value is written to
timer X and the latch at one time.
When the timer X write control bit of the timer
X mode register 1 is “1”, the value is written
only to the latch.
4
5
6
7
• The timer X count value is read out by reading
this register.
Notes 1: When reading and writing, perform them to both the high-
order and low-order bytes.
2: Read both registers in order of TXH and TXL following.
3: Write both registers in order of TXL and TXH following.
4: Do not read both registers during a write, and do not write to
both registers during a read.
Fig. 2.2.8 Structure of Timer X (low-order, high-order)
38B5 Group User’s Manual
2-13
APPLICATION
2.2 Timer
Timer X mode register 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register 1
(TXM1: address 2E16)
b
0
Name
Timer X write
control bit
Functions
At reset R W
0
0 : Write value in latch and
counter
1 : Write value in latch only
b2 b1
Timer X count
source selection bits
0
0
0
1
2
3
0 0: f(XIN)/2 or f(XCIN)/4
0 1: f(XIN)/8 or f(XCIN)/16
1 0: f(XIN)/64 or f(XCIN)/128
1 1: Not available
Nothing is arranged for this bit. This is write
disabled bit. When this bit is read out, the
contents are “0”.
b5 b4
0
0
0
Timer X operating
mode bits
4
5
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width
measurement mode
0 : •Count at rising edge in
event counter mode
•Start from “H” output in
pulse output mode
CNTR2 active edge
switch bit
6
•Measure “H” pulse
width in pulse width
measurement mode
1 : •Count at falling edge in
event counter mode
•Start from “L” output in
pulse output mode
•Measure “L” pulse
width in pulse width
measurement mode
0
Timer X stop
control bit
0 : Count operating
1 : Count stop
7
Fig. 2.2.9 Structure of Timer X mode register 1
38B5 Group User’s Manual
2-14
APPLICATION
2.2 Timer
Timer X mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register 2
(TXM2: address 2F16
)
b
0
Name
Functions
At reset R W
0
Real time port control
bit (P8
0: Real time port function is
invalid
5
)
1: Real time port function is
valid
Real time port control
bit (P86)
1
0: Real time port function is
invalid
0
1: Real time port function is
valid
0
P8
5
data for real time
data for real time
2
3
0: “L” output
1: “H” output
port
P8
port
6
0: “L” output
1: “H” output
0
4
5
6
7
0
0
0
0
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
Fig. 2.2.10 Structure of Timer X mode register 2
38B5 Group User’s Manual
2-15
APPLICATION
2.2 Timer
(3) 8-bit timer, 16-bit timer
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16)
b
0
Name
Functions
At reset R W
✽
✽
✽
0
0
0
INT0 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
1
0 : No interrupt request
issued
1 : Interrupt request issued
INT1 interrupt
request bit
2 INT2 interrupt
request bit
0 : No interrupt request
issued
Remote controller
/counter overflow
interrupt request bit
1 : Interrupt request issued
✽
0
3
0 : No interrupt request
issued
1 : Interrupt request issued
Serial I/O1 interrupt
request bit
Serial I/O automatic
transfer interrupt
request bit
Timer X interrupt
4
✽
✽
✽
✽
0
0
0
0
0 : No interrupt request
issued
1 : Interrupt request issued
request bit
Timer 1 interrupt
request bit
5
6
7
0 : No interrupt request
issued
1 : Interrupt request issued
Timer 2 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
Timer 3 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.2.11 Structure of Interrupt request register 1
38B5 Group User’s Manual
2-16
APPLICATION
2.2 Timer
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16
)
b
0
Name
Functions
At reset R W
Timer 4 interrupt
request bit (Note)
Timer 5 interrupt
request bit
Timer 6 interrupt
request bit
Serial I/O2 receive
interrupt request bit
INT3/Serial I/O2
✽
✽
✽
✽
✽
0
0
0
0
0
0 : No interrupt request issued
1 : Interrupt request issued
1
2
3
4
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
transmit interrupt
request bit (Note)
✽
✽
0 : No interrupt request issued
1 : Interrupt request issued
0
0
0
INT4 interrupt
request bit
5
6
7
A-D converter
interrupt request bit
FLD blanking
interrupt request bit
FLD digit interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
✽: “0” can be set by software, but “1” cannot be set.
Note: In the mask option type P, if timer 4 interrupt whose count source is
CNTR input and INT interrupt are selected, these bits do not
1
3
become “1”.
Fig. 2.2.12 Structure of Interrupt request register 2
38B5 Group User’s Manual
2-17
APPLICATION
2.2 Timer
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 3E16)
b
0
Name
Functions
At reset R W
0
INT0 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
1 INT1 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
2 INT2 interrupt
enable bit
Remote controller
/counter overflow
interrupt enable bit
0
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O1 interrupt
enable bit
3
Serial I/O automatic
transfer interrupt
enable bit
Timer X interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
4
5
6
7
Timer 1 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Timer 2 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
Timer 3 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 2.2.13 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2
0
(ICON2 : address 3F16
)
b
0
Name
Functions
At reset R W
0
Timer 4 interrupt
enable bit (Note)
Timer 5 interrupt
enable bit
Timer 6 interrupt
enable bit
Serial I/O2 receive
interrupt enable bit
INT3/Serial I/O2
0 : interrupt disabled
1 : Interrupt enabled
0
0
0
0
1
2
3
4
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
transmit interrupt
enable bit (Note)
0
0
0
INT4 interrupt
enable bit
5
6
7
0 : interrupt disabled
1 : Interrupt enabled
A-D converter
interrupt enable bit
FLD blanking
interrupt enable bit
FLD digit interrupt
enable bit
0 : interrupt disabled
1 : Interrupt enabled
Fix “0” to this bit.
Note: In the mask option type P, timer 4 interrupt whose count source
is CNTR input and INT interrupt are not available.
1
3
Fig. 2.2.14 Structure of Interrupt control register 2
38B5 Group User’s Manual
2-18
APPLICATION
2.2 Timer
2.2.3 Timer application examples
(1) Basic functions and uses
[Function 1] Control of event interval (Timer 1 to Timer 6, Timer X: timer mode)
When a certain time, by setting a count value to each timer, has passed, the timer interrupt request occurs.
<Use>
•Generating of an output signal timing
•Generating of a wait time
[Function 2] Control of cyclic operation (Timer 1 to Timer 6, Timer X: timer mode)
The value of the timer latch is automatically written to the corresponding timer each time the timer
underflows, and each timer interrupt request occurs in cycles.
<Use>
•Generating of cyclic interrupts
•Clock function (measurement of 1 s); see “(2) Timer application example 1”
•Control of a main routine cycle
[Function 3] Output of rectangular waveform
(Timer 1, Timer 3, Timer 6, Timer X: pulse output mode)
The output level of the T1OUT pin, T3OUT pin, PWM
1
pin or CNTR pin is inverted each time the timer
2
underflows.
<Use>
•Piezoelectric buzzer output; see “(3) Timer application example 2”
•Generating of the remote control carrier waveforms
[Function 4] Count of external pulses (Timer 2, Timer 4, Timer X: event counter mode)
External pulses input to the CNTR
0
pin, CNTR pin, CNTR2 pin are counted as the timer count
1
source (in the event counter mode).
<Use>
•Frequency measurement; see “(4) Timer application example 3”
•Division of external pulses
•Generating of interrupts due to a cycle using external pulses as the count source; count of a reel pulse
[Function 5] Output of PWM signal (Timer 6)
“H” interval and “L” interval are specified, respectively, and the output of pulses from P44/PWM1
pin is repeated.
<Use>
•Control of electric volume
[Function 6] Measurement of external pulse width (Timer X: pulse width measurement mode)
The “H” or “L” level width of external pulses input to CNTR2 pin is measured.
<Use>
•Measurement of external pulse frequency (measurement of pulse width of FG pulse✽ for a motor);
see “(5) Timer application example 4”
•Measurement of external pulse duty (when the frequency is fixed)
FG pulse✽: Pulse used for detecting the motor speed to control the motor speed.
[Function 7] Control of real time port (Timer X: real time port function)
The data for real time is output from the P85 pin or P86 pin each time the timer underflows.
<Use>
•Stepping motor control; see “(6) Timer application example 5”
38B5 Group User’s Manual
2-19
APPLICATION
2.2 Timer
(2) Timer application example 1: Clock function (measurement of 1 s)
Outline: The input clock is divided by the timer so that the clock can count up at 1 s intervals.
Specifications: •The clock f(XIN) = 4.19 MHz (222 Hz) is divided by the timer.
•The timer 3 interrupt request bit is checked in main routine, and if the interrupt
request is issued, the clock is counted up.
• The timer 1 interrupt occurs every 244 µs to execute processing of other interrupts.
Figure 2.2.15 shows the timers connection and setting of division ratios; Figure 2.2.16 shows the
relevant registers setting; Figure 2.2.17 shows the control procedure.
Timer 3 interrupt request bit
Timer 1
1/64
Timer 2
1/256
Timer 3
1/16
f(XIN)
4.19 MHz
0/1
1/16
1 second
0/1
244 µs
0 : No interrupt request issued
1 : Interrupt request issued
Timer 1 interrupt
request bit
Fig. 2.2.15 Timers connection and setting of division ratios
38B5 Group User’s Manual
2-20
APPLICATION
2.2 Timer
Timer 12 mode register (address 2816
)
b7
b0
0
0
0 0 1 0 0
1
T12M
Timer 1 count: Stop; Clear to “0” when starting count.
Timer 2 count: In progress
Timer 1 count source: f(XIN)/16
Timer 2 count source: Timer 1’s underflow
Timer 1 output selection: I/O port
Timer 34 mode register (address 2916
)
b7
b0
T34M
0
0
0 1
0
Timer 3 count: In progress
Timer 3 count source: Timer 2’s underflow
Timer 3 output selection: I/O port
Timer 1 (address 2016
)
b7
b0
T1
T2
T3
3F16
Timer 2 (address 2116
)
b0
b7
Set “division ratio – 1”.
[ T1 = 63 (3F16), T2 = 255 (FF16), T3 = 15 (0F16) ]
FF16
Timer 3 (address 2216
)
b0
b7
0F16
Interrupt control register 1 (address 3E16
)
b7
b0
ICON1
0
0
1
Timer 1 interrupt: Enabled
Timer 2 interrupt: Disabled
Timer 3 interrupt: Disabled
Interrupt request register 1 (address 3C16
)
b7
b0
IREQ1
Timer 1 interrupt request (becomes “1” at 244 µs intervals)
Timer 2 interrupt request
Timer 3 interrupt request (becomes “1” at 1 s intervals)
Fig. 2.2.16 Relevant registers setting
38B5 Group User’s Manual
2-21
APPLICATION
2.2 Timer
RESET
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SEI
•All interrupts disabled
T12M
T34M
(address 2816
(address 2916
)
)
00001001
00XX01X0
2
•Connection of Timers 1 to 3
2
•Setting of Interrupt request bits of Timers 1 to 3 to “0”
•Timer 1 interrupt enabled, Timers 2 and 3 interrupts disabled
IREQ1 (address 3C16
)
000XXXXX
001XXXXX
2
2
ICON1 (address 3E16
)
(address 2016
(address 2116
(address 2216
)
)
)
3F16
FF16
0F16
T1
T2
T3
•Setting “Division ratio – 1” to Timers 1 to 3
(address 2816), bit0
0
T12M
CLI
•Timer count start
•Interrupts enabled
Y
0
Clock is stopped ?
N
•Judgment whether time is not set or time is being set
•Confirmation that 1 sec. has passed
(Check of Timer 3 interrupt request bit)
IREQ1 (address 3C16), bit7 ?
1
•Interrupt request bit cleared
(Clear it by software when not using the interrupt.)
0
IREQ1 (address 3C16), bit7
✽
Clock count up
Second to Year
•Clock count up
Main processing
•Adjust the main processing so that all processing in the loop ✽ will
be processed within 1 second interval.
<Procedure for end of clock setting> (Note)
T2
T3
IREQ1
(address 2116
(address 2216
(address 3C16), bit7
)
)
FF16
0F16
0
•Set Timers again when starting clock from 0 second after
end of clcok setting.
The procedure is Timer 2 setting followed by Timer 3 setting.
•Do not set Timer 1 again because Timer 1 is used to
generate the interrupt at 244 µs intervals.
Note : Perform procedure for end of clock setting only when end of
clock setting.
Fig. 2.2.17 Control procedure
38B5 Group User’s Manual
2-22
APPLICATION
2.2 Timer
(3) Timer application example 2: Piezoelectric buzzer output
Outline: The rectangular waveform output function of the timer is applied for a piezoelectric buzzer
output.
Specifications: •The rectangular waveform, dividing the clock f(XIN) = 4.19 MHz (222 Hz) into about
2 kHz (2048 Hz), is output from the P4 /T3OUT pin.
6
•The level of the P4
stops.
6
/T3OUT pin is fixed to “H” while a piezoelectric buzzer output
Figure 2.2.18 shows a peripheral circuit example, and Figure 2.2.19 shows the timers connection and
setting of division ratios. Figures 2.2.20 shows the relevant registers setting, and Figure 2.2.21
shows the control procedure.
The “H” level is output while a piezoelectric buzzer output stops.
T
3OUT output
T
3OUT
PiPiPi.....
244 µs 244 µs
Set a division ratio so that the underflow
output period of the timer 3 can be 244 µs.
38B5 Group
Fig. 2.2.18 Peripheral circuit example
Timer 3
1/64
Fixed
1/2
f(XIN)
4.19 MHz
T3OUT
1/16
Fig. 2.2.19 Timers connection and setting of division ratios
38B5 Group User’s Manual
2-23
APPLICATION
2.2 Timer
Timer 34 mode register (address 2916)
b7
b0
T34M
0
1
1 0
0
Timer 3 count: In progress
Timer 3 count source: f(XIN)/16
Timer 3 output selection: Buzzer output in progress = “1”
Buzzer output stopped = “0”
Timer 3 (address 2216)
b7
b0
Set “division ratio – 1”; 63 (3F16).
3F16
T3
Interrupt control register 1 (address 3E16)
b7
b0
ICON1
0
Timer 3 interrupt: Disabled
Fig. 2.2.20 Relevant registers setting
RESET
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SEI
•All interrupts disabled
•Port state setting at buzzer output stopped; “H” level output
P4D
P4
(address 0916), bit6
(address 0816), bit6
1
1
ICON1 (address 3E16), bit7
0
•Timer 3 interrupt disabled
•T3OUT output stopped; Buzzer output stopped
T34M (address 2916
)
)
00XX10X0
3F16
2
T3
(address 2216
•Interrupts enabled
CLI
Main processing
•Processing buzzer request, generated during main
processing, in output unit
Output unit
Yes
Piezoelectric buzzer request ?
No
T34M
T3
(address 2916), bit6
(address 2216
0
3F16
T34M (address 2916), bit6
1
)
Start of piezoelectric buzzer output
Stop of piezoelectric buzzer
output
Fig. 2.2.21 Control procedure
38B5 Group User’s Manual
2-24
APPLICATION
2.2 Timer
(4) Timer application example 3: Frequency measurement
Outline: The following two values are compared to judge whether the frequency is within a valid
range.
•A value by counting pulses input to P6
•A reference value
0
/CNTR
1
pin with the timer.
Specifications: •The pulse is input to the P6
0
/CNTR
1
pin and counted by the timer 4. (Note 1)
•A count value of timer 4 is read out at about 2 ms intervals, the timer 1 interrupt
interval. When the count value is 28 to 40, it is judged that the input pulse is valid.
•Because the timer is a down-counter, the count value is compared with 227 to 215
(Note 2).
Notes 1: In the mask option type P, use the CNTR pin and timer 2.
0
2: 227 to 215 = {255 (initial value of counter) – 28} to {255 – 40}; 28 to 40 means the number
of valid value.
Figure 2.2.22 shows the judgment method of valid/invalid of input pulses; Figure 2.2.23 shows the
relevant registers setting; Figure 2.2.24 shows the control procedure.
@
@
@
@
@
@
@
@
@
@
@
@
Input pulse
71.4 µs or more
71.4 µs
50 µs
50 µs or less
(14 kHz or less)
(14 kHz)
(20 kHz)
(20 kHz or more)
Valid
Invalid
Invalid
2 ms
71.4 µs
2 ms
50 µs
= 28 counts
= 40 counts
Fig. 2.2.22 Judgment method of valid/invalid of input pulses
38B5 Group User’s Manual
2-25
APPLICATION
2.2 Timer
Timer 12 mode register (address 2816)
b7
b0
0
0
1 0
1
T12M
Timer 1 count: Stop; Clear to “0” when starting count.
Timer 1 count source: f(XIN)/16
Timer 1 output selection: I/O port
Timer 34 mode register (address 2916)
b7
b0
0
1
0
0
T34M
Timer 4 count: In progress
Timer 4 count source: External count input CNTR1
Timer 1 (address 2016)
b7
b0
Set “division ratio – 1”; 63 (3F16).
T1
T4
3F16
Timer 4 (address 2316)
b7
b0
Set 255 (FF16) just before counting pulses.
(After a certain time has passed, the number of
input pulses is decreased from this value.)
FF16
Interrupt control register 1 (address 3E16)
b7
b0
ICON1
1
Timer 1 interrupt: Enabled
Interrupt control register 2 (address 3F16)
b7
b0
0
ICON2
Timer 4 interrupt: Disabled
Interrupt request register 2 (address 3D16)
b7
b0
IREQ2
0
Timer 4 interrupt request
( “1” of this bit when reading the count value
indicates the 256 or more pulses input in the
condition of Timer 4 = 255)
Fig. 2.2.23 Relevant registers setting
38B5 Group User’s Manual
2-26
APPLICATION
2.2 Timer
● X: This bit is not used here. Set it to “0” or “1” arbitrary.
RESET
Initialization
SEI
•All interrupts disabled
00XX10X12
3F16
•Set division ratio so that Timer 1 interrupt will occur at 244 µs intervals.
(address 2816)
(address 2016)
T12M
T1
0X10XX0X2
FF16
•External pulses input from CNTR1 pin selected as Timer 4’s count source
•Setting Timer 4 count value
(address 2916)
(address 2316)
T34M
T4
1
0
•Timer 1 interrupt enabled
•Timer 4 interrupt disabled
(address 3E16),bit5
(address 3F16),bit0
ICON1
ICON2
T12M (address 2816), bit0
CLI
0
•Timer 1 count start
•Interrupts enabled
Timer 1 interrupt process routine
1/8
•Set so that pulse judgment process will be performed once each time
Timer 1 interrupt occurs 8 times, at 2 ms intervals.
CLT (Note 1)
CLD (Note 2)
Push registers to stack
Note 1: When using Index X mode flag (T)
Note 2: When using Decimal mode flag (D)
•Pushing registers used in interrupt process routine
1
•Processing as out of range when the count value is 256 or more
IREQ2 (address 3D16), bit0 ?
•Count value read
•Storing count value into Accumulator (A)
(A)
T4 (address 2316)
In range
214 < (A) < 228
•Compare the read value with
reference value.
•Store the comparison result to flag Fpulse.
Out of range
0
1
Fpulse
Fpulse
•Initialization of counter value
•Timer 4 interrupt request bit cleared
T4
(address 2316)
FF16
0
IREQ2 (address 3D16), bit0
Process judgment result
Pop registers
•Popping registers pushed to stack
RTI
Fig. 2.2.24 Control procedure
38B5 Group User’s Manual
2-27
APPLICATION
2.2 Timer
(5) Timer application example 4: Measurement of FG pulse width for motor
Outline: The timer X counts the “H” level width of the pulses input to the P6
1/CNTR
0
/CNTR
2
pin. An
underflow is detected by the timer X interrupt and an end of the input pulse “H” level is
detected by the timer 2 interrupt of which count source is the input to P6
1
/CNTR
0
/CNTR
2
pin.
Specifications: •The timer X counts the “H” level width of the FG pulse input to the P6
CNTR pin.
1/CNTR
0
/
2
<Example>
When f(XIN) = 4.19 MHz, the count source is 15.2 µs, which is obtained by dividing the clock
frequency by 64. Measurement can be made up to 1 s in the range of FFFF16 to 000016
.
Figure 2.2.25 shows the timers connection and setting of division ratio; Figure 2.2.26 shows the
relevant registers setting; Figure 2.2.27 shows the control procedure.
Timer X count source
selection bit
Timer X
1/65536
Timer X interrupt
request bit
1/64
0/1
f(XIN) = 4.19 MHz
1 second
Fig. 2.2.25 Timers connection and setting of division ratios
38B5 Group User’s Manual
2-28
APPLICATION
2.2 Timer
Port P6 direction register (address 0D16
)
b7
b0
P6D
0
P6
1
/CNTR
0
/CNTR : Input mode
2
Timer X mode register 1 (address 2E16
)
b7
b0
TXM1
1
0
1
1
1 0
0
Write value in latch and counter
Timer X count source: f(XIN)/64
Timer X operating mode: Pulse width measurement mode
CNTR active edge: Measuring “H” pulse width in pulse width measurement mode
Timer X count: Stop; Clear to “0” when starting count.
2
Timer X mode register 2 (address 2F16
)
b7
b0
TXM2
0
0
Real time port function (P8
Real time port function (P8
5
6
): Invalid
): Invalid
Timer X (low-order) (address 2C16
)
b7
b0
FF16
TXL
TXH
Set “65535 (FFFF16)” before stat of pulse width
measurement.
Timer X (high-order) (address 2D16
)
b7
b0
FF16
Interrupt edge selection register (address 3A16
)
b7
b0
INTEDGE
T12M
1
CNTR
0
pin edge: Falling edge count
)
Timer 12 mode register (address 2816
b7
b0
0
1
0
0
Timer 2 count: Stop
Timer 2 count source: External count input CNTR
0
Timer 2 (address 2116
)
b7
b0
Set “0”.
T2
0
Timer 2 interrupt request occurs due to falling edge input to CNTR pin.
0
Interrupt control register 1 (address 3E16
)
b7
b0
ICON1
1
1
Timer X interrupt: Enabled
Timer 2 interrupt: Enabled
Interrupt request register 1 (address 3C16
)
b7
b0
IREQ1
Timer X interrupt request (becomes “1” when Timer X underflows)
Timer 2 interrupt request (becomes “1” when “H” level input ends)
Fig. 2.2.26 Relevant registers setting
38B5 Group User’s Manual
2-29
APPLICATION
2.2 Timer
RESET
● X: This bit is not used here. Set it to “0” or “1” arbitrary.
Initialization
SEI
•All interrupts disabled
•Setting P61/CNTR0/CNTR2 pin to input mode
•Timer X: Pulse width measurement mode
(Measuring “H” pulse width of input pulses from CNTR2 pin)
•Setting Timer X count value
P6D
(address 0D16),bit1
(address 2E16)
(address 2F16)
(address 2C16)
(address 2D16)
0
TXM1
TXM2
TXL
1011X1002
XXXXXX002
FF16
TXH
FF16
•CNTR0 pin edge: Falling edge count
INTEDGE(address 3A16),bit6
1
•External pulses input from CNTR0 pin selected as Timer 2’s count source
•Setting “0” to Timer 2
•Timers X and 2 interrupts: Enabled
T12M
T2
ICON1
(address 2816)
(address 2116)
(address 3E16)
0X10XX1X2
0
XXXX1X1X2
•Timers X and 2 count start
•Interrupts enabled
(address 2E16),bit7
(address 2816),bit1
0
0
TXM1
T12M
CLI
Notes 1: Timer X interrupt also occurs owing to factors other than
measurement level.(CNTR2 input = “L” in this application)
Process it by software as error proccesing is performed for
measurement level as necessary . CNTR2 input level can be
checked by reading the contents of sharing port P61 register.
2: When using Index X mode flag (T)
Timer X interrupt process routine (Note 1)
CLT (Note 2)
CLD (Note 3)
Push registers to stack
3: When using Decimal m
•Pushing registers used in interrupt process routine
ode flag (D)
Error processing
Pop registers
•Popping registers pushed to stack
RTI
Fig. 2.2.27 Control procedure
38B5 Group User’s Manual
2-30
APPLICATION
2.2 Timer
Timer 2 interrupt process routine (Note 1)
Notes 2: When using Index X mode flag (T)
3: When using Decimal m
•Pushing registers used in interrupt process routine
CLT (Note 2)
CLD (Note 3)
Push registers to stack
ode flag (D)
•Count value read and storing it to RAM
(A)
TXH
( )
TXL
Measurement result (high-order 8 bits)
(A)
Measurement result (low-order 8 bits)
A
( )
A
TXL
TXH
(address 2C16)
(address 2D16)
FF16
FF16
Pop registers
•Popping registers pushed to stack
RTI
Note 1: The first value becomes invalid depending on start timing of Time X count
shown by the following figure.
Process it by software as necessary.
[ Example 1] • Start Timer X count when CNTR2 input level is “L”.
(CNTR2 input level can be checked by reading the contents of sharing port P61 register.
FFFF16
T1
T2
000016
T1 value: Valid
T2 value: Valid
CNTR2
Count start of
Timer X
Timer 2 interrupt
Timer 2 interrupt
[ Example 2] • Start Timer X count when CNTR2 input level is “H”.
Invalidate the first Timer 2 interrupt after start of Timer X count.
FFFF16
T1
T2
000016
CNTR2
T1 value: Invalid
T2 value: Valid
Count start of
Timer X
Timer 2 interrupt
Timer 2 interrupt
38B5 Group User’s Manual
2-31
APPLICATION
2.2 Timer
(6) Timer application example 5: Control of stepping motor
Outline: The rotating of stepping motor is controlled by using real time output ports.
Specifications: •The motor is controlled by using 2 real time output ports.
•The count source is f(XIN) = 4.19 MHz divided by 8.
•Values of Timer X and real time output are updated in the timer X interrupt routine
Figure 2.2.28 shows the timers connection and the table example of timer X/RTP setting values;
Figure 29 shows the RTP output example; Figure 2.2.30 shows the relevant registers setting; Figure
2.2.31 shows the control procedure.
RTP P85
RTP P86
TXL
TXH
TXM2
Motor
Timer X
table
RTP
table
38B5 group
Timer X setting table example
RTP setting table example
RTP
RTP output
pattern
RTP value
Timer X value
output time
TXM2,b2 TXM2,b3
()
1
T1
T2
0
0
1
1
0
1
0
1
2FD016
2B7116
()
2
()
3
T3
T4
T5
T6
T7
T8
208116
186916
13C916
13A916
122116
11C116
()
4
RTP: Real Time Port
Fig. 2.2.28 Timers connection and table example of timer X/RTP setting values
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T8
RTP output time
RTP P8
RTP P8
5
6
(1)
(2)
(3)
(4)
RTP
output
pattern
(1)
RTP
output
pattern
(2)
RTP
output
pattern
(3)
RTP
output
pattern
(4)
RTP: Real Time Port
Fig. 2.2.29 RTP output example
38B5 Group User’s Manual
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APPLICATION
2.2 Timer
Timer X mode register 1 (address 2E16)
b7
b0
1
0
0
0 1 0
TXM1
Write value in latch and counter
Timer X count source: f(XIN)/8
Timer X operating mode: Timer mode
Timer X count: Stop; Clear to “0” when starting count.
Timer X mode register 2 (address 2F16)
b7
b0
TXM2
1
1
Real time port function (P85): Valid
Real time port function (P86): Valid
P85 data for real time port
P86 data for real time port
Timer X (low-order) (address 2C16)
b7
b0
TXL
TXH
Update the value from the table each time Timer X underflows.
(When accelerating or reducing speed.)
Timer X (high-order) (address 2D16)
b7
b0
Interrupt control register 1 (address 3E16)
b7
b0
ICON1
1
Timer X interrupt: Enabled
Fig. 2.2.30 Relevant registers setting
38B5 Group User’s Manual
2-33
APPLICATION
2.2 Timer
● X: This bit is not used here. Set it to “0” or “1” arbitrary.
RESET
Initialization
SEI
•All interrupts disabled
•Setting Timer X
•Setting RTP function, “002” data from table
•Setting Timer X initial value, “2FD02” data from table
(address 2E16)
(address 2F16)
(address 2C16)
(address 2D16)
(address 3C16),bit4
(address 3E16),bit4
TXM1
TXM2
TXL
TXH
IREQ1
ICON1
1X00X0102
XXXX00112
D016
2F16
0
•Timer X interrupt request cleared
•Timer X interrupt enabled
1
(address 2E16), bit7
0
•Timer X count start
•Interrupts enabled
TXM1
CLI
Main processing
RTP: Real Time Port
Timer X interrupt process routine
Notes 1: When using Index X mode flag (T)
CLT (Note 1)
2: When using Decimal m
•Pushing registers used in interrupt process routine
CLD (Note 2)
Push registers to stack
ode flag (D)
Transfer the next underflow time of Timer X
from internal ROM table and store it to TXL
(address 2C16) and TXH (address 2D16)
Transfer RTP output data from internal
ROM table next underflow of Timer X and
store it to bits 2 and 3 of TXM2 (address
2F16) and TXH (address 2D16)
Pop registers
RTI
•Popping registers pushed to stack
Fig. 2.2.31 Control procedure
38B5 Group User’s Manual
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APPLICATION
2.3 Serial I/O
2.3 Serial I/O
This paragraph explains the registers setting method and the notes relevant to the serial I/O.
2.3.1 Memory map
Baud rate generator (BRG)
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
UART control register (UARTCON)
Serial I/O1 automatic transfer data pointer (SIO1DP)
Serial I/O1 control register 1 (SIO1CON1,SC11)
Serial I/O1 control register 2 (SIO1CON2,SC12)
Serial I/O1 register/Transfer counter (SIO1)
Serial I/O1 control register 3 (SIO1CON3,SC13)
Serial I/O2 control register (SIO2CON)
Serial I/O2 status register (SIO2STS)
Serial I/O2 transmit/receive buffer register (TB/RB)
Interrupt source switch register (IFR)
003916
003C16 Interrupt request register 1 (IREQ1)
003D16 Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
003E16
003F16
Fig. 2.3.1 Memory map of registers relevant to Serial I/O
38B5 Group User’s Manual
2-35
APPLICATION
2.3 Serial I/O
2.3.2 Relevant registers
(1) Serial I/O1
Serial I/O1 automatic transfer data pointer
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 automatic transfer data pointer
(SIO1DP: address 1816)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
• Indicates the low-order 8 bits of the address
storing the start data on the serial I/O.
automatic transfer RAM.
• Data is written into the latch and read from the
decrement counter.
Fig. 2.3.2 Structure of Serial I/O1 automatic transfer data pointer
38B5 Group User’s Manual
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APPLICATION
2.3 Serial I/O
Serial I/O1 control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 1
(SIO1CON1•SC11: address 1916)
b
0
Name
Serial transfer
selection bits
Functions
At reset R W
0
b1b0
0 0: Serial I/O disabled
(Pins P6 , P6 , P6
P5 –P5 pins are I/O
ports.)
2
4
5,
0
3
0
0
1
2
0 1: 8-bit serial I/O
1 0: Not available
1 1: Automatic transfer
serial I/O (8 bits)
b3b2
Serial I/O1
synchronous clock
selection bits
(P65/SSTB1 pin
control bits)
0 0: Internal synchronous
clock (P6
5 pin is I/O
port.)
0 1: External synchronous
clock (P6
5 pin is I/O
port.)
1 0: Internal synchronous
clock (P6 pin is
STB1 output.)
1 1: Internal synchronous
clock (P6 pin is
STB1 output.)
0
3
5
S
5
S
0
0
Serial I/O
initialization bit
Transfer mode
selection bit
0: Serial I/O initialization
1: Serial I/O enabled
4
5
0: Full-duplex
(transmit/receive) mode
(P5
1: Transmit-only mode
(P5 pin is I/O port.)
0 pin is SIN1 input.)
0
Transfer direction
selection bit
0
0
0: LSB first
1: MSB first
6
7
Serial I/O1 clock pin
selection bit
0: SCLK11 (P5
is I/O port.)
1: SCLK12 (P5
is I/O port.)
3
/SCLK12 pin
/SCLK11 pin
2
Fig. 2.3.3 Structure of Serial I/O1 control register 1
38B5 Group User’s Manual
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APPLICATION
2.3 Serial I/O
Serial I/O1 control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 2
(SIO1CON2 • SC12: address 1A16
)
b
0
Name
Functions
At reset R W
0
P6
2
/SRDY1
•
P64
/SBUSY1 pin
control bits
b3b2b1b0
0 0 0 0: P6
0 0 0 1: Not used
0 0 1 0: P6 pin is SRDY1 output; P6
I/O port.
2, P64 pins are I/O ports.
2
4
pin is
pin is
0 0 1 1: P6
2
pin is SRDY1 output; P6
4
0
0
0
1
2
3
I/O port.
0 1 0 0: P6
2
pin is I/O port; P6
4
pin is
pin is
pin is
pin is
S
BUSY1 input.
2 pin is I/O port; P64
0 1 0 1: P6
BUSY1 input.
0 1 1 0: P6 pin is I/O port; P6
BUSY1 output.
0 1 1 1: P6 pin is I/O port; P6
BUSY1 output.
S
2
4
4
S
2
S
1 0 0 0: P6
2
pin is SRDY1 input; P6
4
4
4
4
pin is
pin is
pin is
pin is
S
BUSY1 output.
1 0 0 1: P6 pin is SRDY1 input; P6
BUSY1 output.
1 0 1 0: P6 pin is SRDY1 input; P6
BUSY1 output.
1 0 1 1: P6 pin is SRDY1 input; P6
BUSY1 output.
2
S
2
S
2
S
1 1 0 0: P6
2
pin is SRDY1 output; P6
4
4
4
4
pin is
S
BUSY1 input.
1 1 0 1: P6 pin is SRDY1 output; P6
BUSY1 input.
1 1 1 0: P6 pin is SRDY1 output; P6
BUSY1 input.
1 1 1 1: P6 pin is SRDY1 output; P6
BUSY1 input.
2
pin is
pin is
pin is
S
2
S
2
S
S
S
BUSY1 output •
STB1 output
4
5
0
0
0: Functions as signal for
each 1-byte
1: Functions as signal for
each transfer data set
function selection bit
(Valid in serial I/O1
automatic transfer
mode)
Serial transfer
status flag
0: Serial transfer
completed
1: Serial transfer in-
progress
6
7
S
OUT1 pin control
0
0
0: Output active
1: Output high-impedance
bit (when serial data
is not transferred)
P5
1/SOUT1 P-channel
0: CMOS 3 state (P-
channel output is valid.)
1: N-channel open-drain
output (P-channel output
is invalid.)
output disable bit
Fig. 2.3.4 Structure of Serial I/O1 control register 2
38B5 Group User’s Manual
2-38
APPLICATION
2.3 Serial I/O
Serial I/O1 register/Transfer counter
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 register/Transfer counter
(SIO1: address 1B16)
b
0
Name
Functions
•At function as serial I/O1
register:
At reset R W
•In 8-bit serial I/O
mode:
Undefined
This register becomes the
shift register to perform
serial transmit/reception.
Set transmit data to this
register.
Serial I/O1 register
1
2
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
•In automatic transfer
serial I/O mode:
Transfer counter
The serial transfer is started
by writing the transmit data.
3
4
5
•At function as transfer
counter:
Set (transfer byte number –
1) to this register.
When selecting an internal
clock, the automatic
transfer is started by writing
the transmit data.
(When selecting an external
clock, after writing a value
to this register, wait for 5 or
more cycles of the internal
system clock before
6
7
inputting the transfer clock
to the SCLK1 pin.)
Fig. 2.3.5 Structure of Serial I/O1 register/Transfer counter
38B5 Group User’s Manual
2-39
APPLICATION
2.3 Serial I/O
Serial I/O1 control register 3
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 3
(SIO1CON3 • SC13: address 1C16
)
b
0
Name
Functions
At reset R W
b4b3b2b1b0
0
Automatic transfer
interval set bits
(valid only when
selecting internal
synchronous clock)
0 0 0 0 0: 2 cycles of
transfer clock
0 0 0 0 1: 3 cycles of
transfer clock
0
0
0
0
0
1
2
3
4
to
1 1 1 1 0: 32 cycles of
transfer clock
1 1 1 1 1: 33 cycles of
transfer clock
Data is written into the
latch and read from the
decrement counter.
b7b6b5
5
Internal
synchronous clock
selection bits
0 0 0 : f(XIN)/4 or f(XCIN)/8
0 0 1 : f(XIN)/8 or
f(XCIN)/16
0 1 0 : f(XIN)/16 or
f(XCIN)/32
0 1 1 : f(XIN)/32 or
f(XCIN)/64
1 0 0 : f(XIN)/64 or
f(XCIN)/128
1 0 1 : f(XIN)/128 or
f(XCIN)/256
0
0
6
7
1 1 0 : f(XIN)/256 or
f(XCIN)/512
1 1 1 : Not used
Fig. 2.3.6 Structure of Serial I/O1 control register 3
38B5 Group User’s Manual
2-40
APPLICATION
2.3 Serial I/O
(2) Serial I/O2
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator
(BRG: address 1616)
b
Functions
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
• Bit rate of the serial transfer is determined.
• This is the 8-bit counter and has the reload
register.
The count source is divided by n+1 owing to
specifying a value n.
0
1
2
3
4
5
6
7
Fig. 2.3.7 Structure of Baud rate generator
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register
(UARTCON: address 1716)
b
0
Name
Functions
At reset R W
0
Character length
selection bit (CHAS)
Parity enable bit
(PARE)
0: 8 bits
1: 7 bits
0: Parity checking disabled
1: Parity checking enabled
0
0
0
0
1
0: Even parity
1: Odd parity
2 Parity selection bit
(PARS)
3
0: 1 stop bit
1: 2 stop bits
Stop bit length
selection bit (STPS)
4 P5
5/TxD P-channel
0: CMOS output (in output
mode)
1: N-channel open-drain
output (in output mode)
output disable bit
(POFF)
0
0
5
6
0: XIN or XCIN/2 (depending
on internal system clock)
1: XCIN
BRG clock switch bit
Serial I/O2 clock
0: SCLK21 (P5 /SCLK22 pin is
7
used as I/O port or SRDY2
output pin.)
I/O pin selection bit
1: SCLK22 (P56/SCLK21 pin is
used as I/O port.)
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “1”.
1
7
Fig. 2.3.8 Structure of UART control register
38B5 Group User’s Manual
2-41
APPLICATION
2.3 Serial I/O
Serial I/O2 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register
(SIO2CON: address 1D16
)
b
0
Name
Functions
At reset R W
0
0: f(XIN) or f(XCIN)/2 or
BRG count source
selection bit (CSS)
f(XCIN
)
1: f(XIN)/4 or f(XCIN)/8 or
f(XCIN)/4
0
1
Serial I/O2
•In clock synchronous
mode
0: BRG output/4
1: External clock input
•In UART mode
synchronous clock
selection bit
(SCS)
0: BRG output/16
1: External clock input/16
0: P5
normal I/O pin
7
pin operates as
0
0
2
3
S
RDY2 output
enable bit (SRDY)
1: P5
7
pin operates as
S
RDY2 output pin
Transmit interrupt
source selection bit
(TIC)
0: When transmit buffer
has emptied
1: When transmit shift
operation is completed
0
0
0
4 Transmit enable bit
(TE)
0: Transmit disabled
1: Transmit enabled
0: Receive disabled
1: Receive enabled
5
Receive enable bit
(RE)
Serial I/O2 mode
6
0: Clock asynchronous
serial I/O (UART) mode
1: Clock synchronous
serial I/O mode
selection bit (SIOM)
0
Serial I/O2 enable
bit (SIOE)
0: Serial I/O2 disabled
7
(pins P54–P57 operate
as normal I/O pins)
1: Serial I/O2 enabled
(pins P54–P57 operate
as serial I/O pins)
Fig. 2.3.9 Structure of Serial I/O2 control register
38B5 Group User’s Manual
2-42
APPLICATION
2.3 Serial I/O
Serial I/O2 status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 status register
(SIO2STS: address 1E16)
b
0
Name
Transmit buffer
empty flag (TBE)
Functions
0: Buffer full
1: Buffer empty
At reset R W
0
Receive buffer full
flag (RBF)
Transmit shift
register shift
completion flag
(TSC)
0: Buffer empty
1: Buffer full
0
0
1
2
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag
(OE)
0: No error
1: Overrun error
0
0
0
0
1
3
4
5
6
7
Parity error flag
(PE)
0: No error
1: Parity error
0: No error
1: Framing error
Framing error flag
(FE)
Summing error flag
(SE)
0: (OE) U (PE) U (FE) = 0
1: (OE) U (PE) U (FE) = 1
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “1”.
Fig. 2.3.10 Structure of Serial I/O2 status register
Serial I/O2 transmit/receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 transmit/receive buffer register
(TB/RB: address 1F16)
b
0
1
Functions
At reset R W
This is the buffer register which is used to write
transmit data or to read receive data.
• At write : The value is written to the transmit
buffer register. The value cannot be
written to the receive buffer register.
• At read : The contents of the receive buffer
register is read out. When a
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
2
3
4
5
6
7
character bit length is 7 bits, the
MSB of data stored in the receive
buffer is “0”. The contents of the
transmit buffer register cannot be
read out.
Fig. 2.3.11 Structure of Serial I/O2 transmit/receive buffer register
38B5 Group User’s Manual
2-43
APPLICATION
2.3 Serial I/O
(3) Serial I/O1 and Serial I/O2
Interrupt source switch register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt source switch register
(IFR: address 3916
)
b
0
Name
3/serial I/O2
transmit interrupt
Functions
3 intrrupt
1: Serial I/O2 transmit
interrupt
At reset R W
0
INT
0: INT
switch bit (Note)
0: INT
4
interrupt
0
1 INT
4/A-D
1: A-D conversion intrerrupt
conversion interrupt
switch bit
0
0
0
0
0
0
2
3
4
5
6
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
7
Note: In the mask option type P, this bit is not available because INT
3
funciton is not used.
Fig. 2.3.12 Structure of Interrupt source switch register
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16
)
b
0
Name
Functions
At reset R W
✽
✽
✽
0
0
0
INT
0
interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
1 INT
request bit
1 interrupt
0 : No interrupt request
issued
1 : Interrupt request issued
2 INT
2
interrupt
request bit
0 : No interrupt request
issued
Remote controller
/counter overflow
interrupt request bit
1 : Interrupt request issued
✽
0
3
Serial I/O1 interrupt 0 : No interrupt request
request bit
issued
Serial I/O automatic 1 : Interrupt request issued
transfer interrupt
request bit
✽
✽
✽
✽
0
0
0
0
Timer X interrupt
request bit
4
5
6
7
0 : No interrupt request
issued
1 : Interrupt request issued
Timer 1 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
Timer 2 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
Timer 3 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.3.13 Structure of Interrupt request register 1
38B5 Group User’s Manual
2-44
APPLICATION
2.3 Serial I/O
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16
)
b
0
Name
Functions
0 : No interrupt request issued
1 : Interrupt request issued
At reset R W
Timer 4 interrupt
request bit (Note)
Timer 5 interrupt
request bit
Timer 6 interrupt
request bit
Serial I/O2 receive
interrupt request bit
INT3/Serial I/O2
✽
✽
✽
✽
✽
0
0
0
0
0
0 : No interrupt request issued
1 : Interrupt request issued
1
2
3
4
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
transmit interrupt
request bit (Note)
✽
✽
0 : No interrupt request issued
1 : Interrupt request issued
0
0
0
INT4 interrupt
request bit
5
6
7
A-D converter
interrupt request bit
FLD blanking
interrupt request bit
FLD digit interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
✽: “0” can be set by software, but “1” cannot be set.
Note: In the mask option type P, if timer 4 interrupt whose count source is
CNTR1 input and INT3 interrupt are selected, these bits do not
become “1”.
Fig. 2.3.14 Structure of Interrupt request register 2
38B5 Group User’s Manual
2-45
APPLICATION
2.3 Serial I/O
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 3E16)
b
0
Name
Functions
At reset R W
0
INT0 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
1 INT1 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
2 INT2 interrupt
enable bit
Remote controller
/counter overflow
interrupt enable bit
0
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O1 interrupt
enable bit
3
Serial I/O automatic
transfer interrupt
enable bit
Timer X interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
4
5
6
7
Timer 1 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Timer 2 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
Timer 3 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 2.3.15 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2
0
(ICON2 : address 3F16
)
b
0
Name
Functions
At reset R W
0
Timer 4 interrupt
enable bit (Note)
Timer 5 interrupt
enable bit
Timer 6 interrupt
enable bit
Serial I/O2 receive
interrupt enable bit
INT3/Serial I/O2
0 : interrupt disabled
1 : Interrupt enabled
0
0
0
0
1
2
3
4
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
transmit interrupt
enable bit (Note)
0
0
0
INT4 interrupt
enable bit
5
6
7
0 : interrupt disabled
1 : Interrupt enabled
A-D converter
interrupt enable bit
FLD blanking
interrupt enable bit
FLD digit interrupt
enable bit
0 : interrupt disabled
1 : Interrupt enabled
Fix “0” to this bit.
Note: In the mask option type P, timer 4 interrupt whose count source
is CNTR input and INT interrupt are not available.
1
3
Fig. 2.3.16 Structure of Interrupt control register 2
38B5 Group User’s Manual
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APPLICATION
2.3 Serial I/O
2.3.3 Serial I/O1 connection examples
(1) Control of peripheral IC equipped with CS pin
Figure 2.3.17 shows connection examples with peripheral ICs equipped with the CS pin.
All examples can use the automatic transfer function.
(1) Only transmission
(2) Transmission and reception
(Using SIN1 pin as I/O port)
SBUSY1
SCLK11
SOUT1
CS
SBUSY1
SCLK11
SOUT1
SIN1
CS
CLK
DATA
CLK
IN
OUT
Peripheral IC
(OSD controller etc.)
38B5 group
38B5 group
Peripheral IC
(EEPROM etc.)
(3) Transmission and reception
(When connecting SIN1 with SOUT1)
(When connecting IN with OUT in
peripheral IC)
(4) Connection of plural IC
SBUSY1
SCLK11
SOUT1
SIN1
Port
SCLK11
SOUT1
SIN1
CS
CS
CLK
IN
CLK
IN
OUT
OUT
Port
✽2
✽1
Peripheral IC 1
Peripheral IC
38B5 group
(EEPROM etc.)
38B5 group
CS
✽1: Select an N-channel open-drain output for SOUT1 pin
output control.
✽2: Use the OUT pin of peripheral IC which is an N-
channel open-drain output and becomes high impe-
dance during receiving data.
CLK
IN
OUT
Peripheral IC 2
Note: “Port” means an output port controlled by software.
Fig. 2.3.17 Serial I/O1 connection examples (1)
38B5 Group User’s Manual
2-47
APPLICATION
2.3 Serial I/O
(2) Connection with microcomputer
Figure 2.3.18 shows connection examples with another microcomputer.
(1) Selecting internal clock
(2) Selecting external clock
SCLK11
SOUT1
SIN1
CLK
SCLK11
SOUT1
SIN1
CLK
IN
IN
OUT
OUT
38B5 group
Microcomputer
38B5 group
Microcomputer
(3) Using SRDY1 signal output function
(Selecting external clock)
(4) Using switch function of CLK signal output
pins, SCLK12 (Selecting internal clock)
SCLK11
SOUT1
SIN1
SRDY1
SCLK11
SOUT1
SIN1
RDY
CLK
IN
CLK
IN
OUT
SCLK12
Port
OUT
Microcomputer
38B5 group
Microcomputer
38B5 group
CLK
IN
OUT
CS
Peripheral IC
Fig. 2.3.18 Serial I/O1 connection examples (2)
38B5 Group User’s Manual
2-48
APPLICATION
2.3 Serial I/O
2.3.4 Serial I/O1’s modes
Figure 2.3.19 shows the serial I/O1’s modes.
✽
Output SRDY1 signal
✽
Input SRDY1 signal (Note)
Used
handshake
signal
✽
Output SBUSY1 signal
✽
Input SBUSY1 signal
Internal
clock
✽
Output SSTB1 signal
Not used
handshake
signal
Full duplex
mode
8-bit serial
I/O
Serial I/O1
✽
Output SRDY1 signal
Automatic
transfer
serial I/O
Transmit
only mode
✽
Input SRDY1 signal (Note)
Used
handshake
signal
✽
Output SBUSY1 signal
External
clock
✽
Input SBUSY1 signal
Not used
handshake
signal
Note: This is only valid when outputting the SBUSY1 signal.
✽ Active logic can apply to each signal of SRDY1, SBUSY1, SSTB1.
Fig. 2.3.19 Serial I/O1’s modes
38B5 Group User’s Manual
2-49
APPLICATION
2.3 Serial I/O
2.3.5 Serial I/O1 application examples
(1) Output of serial data (control of peripheral IC)
Outline : Serial communication is performed, connecting ports with the CS pin of a peripheral IC.
Figure 2.3.20 shows a connection diagram, and Figure 2.3.21 shows a timing chart.
CS
P62
P52/SCLK11
P51/SOUT1
CS
CLK
CLK
DATA
DATA
38B5 group
Peripheral IC
Fig. 2.3.20 Connection diagram
Specifications : • Use of serial I/O1 (Not using automatic transfer function)
• Synchronous clock frequency : 131 kHz (f(XIN) = 4.19 MHz is divided by 32)
• Transfer direction : LSB first
• Not use of serial I/O1 interrupt
• Port P6
2
is connected to the CS pin (“L” active) of the peripheral IC for transmission
control; the output level of port P6
2
is controlled by software.
CS
CLK
DO0
DO1
DO2
DO3
DATA
Fig. 2.3.21 Timing chart
38B5 Group User’s Manual
2-50
APPLICATION
2.3 Serial I/O
Figure 2.3.22 shows the registers setting relevant to the transmission side, and Figure 2.3.23 shows
the setting of transmission data.
Serial I/O1 control register 1 (address 001916
)
SIO1CON1
(SC11)
0
0 1 0 0 0 0 1
8-bit serial I/O
Internal synchronous clock (P6 pin is an I/O port.)
5
Serial I/O initialization
Transmit-only mode
LSB first
Serial I/O1 clock pin: SCLK11
Serial I/O1 control register 2 (address 001A16
)
SIO1CON2
(SC12)
0
0
0 0 0 0
Pins P6
2
and P6
4
of I/O ports
S
OUT1 pin: Output active
P5 /SOUT1: CMOS 3-state (P-channel output is valid.)
1
Serial I/O1 control register 3 (address 001C16
)
SIO1CON3 0 1
(SC13)
1
Internal synchronous clock: f(XIN)/32
Port P6 (address 000C16
1
)
P6
Set P6 output level to “H”
2
Port P6 direction register (address 000D16
1
)
P6D
Set P6 to output mode
2
Fig. 2.3.22 Registers setting relevant to transmission side
Serial I/O1 register (001B16
)
Set a transmission data.
SIO1
Confirm that transmission of the previous
data is completed, where bit 5, the serial
transfer status flag of the serial I/O1 control
register 2, is “0”; before writing data.
Fig. 2.3.23 Setting of transmission data
38B5 Group User’s Manual
2-51
APPLICATION
2.3 Serial I/O
Control procedure: When the registers are set as shown in Figure 2.3.22, the serial I/O1 can transmit
1-byte data by writing data to the serial I/O1 register.
Thus, after setting the CS signal to “L”, write the transmission data to the serial
I/O1 register by each 1 byte; and return the CS signal to “H” when the target
number of bytes has been transmitted.
Figure 2.3.24 shows a control procedure.
RESET
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SC11 (address 001916
SC12 (address 001A16
SC13 (address 001C16
)
)
)
00100001
00XX0000
011XXXXX
2
Serial I/O1 setting
2
2
P6 (address 000C16), bit2
P6D (address 000D16), bit2
SC11 (address 001916), bit4
1
1
1
CS signal output level to “H” setting
CS signal output port setting
Enabled serial I/O1
P6 (address 000C16), bit2
0
CS signal output level to “L” setting
Transmission data write
(Start of 1-byte data transmission)
SIO1 (address 001B16
)
Transmission data
1
Judgment of completion of transmitting 1-byte
data
SIO1CON2 (address 001A16), bit5 ?
0
Use any of RAM area as a counter for counting
the number of transmitted bytes.
Judgment of completion of transmitting the target
number of bytes
N
All data have been transmitted ?
Y
Returning CS signal output level to “H” when
transmission of the target number of bytes is
completed
P6 (address 000C16), bit2
1
Fig. 2.3.24 Control procedure
38B5 Group User’s Manual
2-52
APPLICATION
2.3 Serial I/O
(2) Transmission/Reception using automatic transfer
Outline: Serial transmission/reception control is performed, using the serial automatic transfer function.
Figure 2.3.25 shows a connection diagram, and Figure 2.3.26 shows a timing chart of serial data
transmission/reception.
P52/SCLK11
P51/SOUT1
P50/SIN1
CLK
IN
OUT
Sub microcomputer
38B5 group
Fig. 2.3.25 Connection diagram
Specifications: • Use of serial I/O1 using automatic transfer function
• Synchronous clock frequency: 131 kHz (f(XIN) = 4.19 MHz is divided by 32.)
• Transfer direction: LSB first
• Transmission/reception byte number: 8 bytes/block each
• Transfer interval for 1-byte: 244 µs (32 cycles of transfer clock)
• Not use of serial I/O1 automatic transfer interrupt
Figure 2.3.27 shows the relevant registers setting, and Figure 2.3.28 shows the control procedure.
1 block
CLK
DO0
DI0
DO1
DI1
DO2
DI2
DO7
DI7
DO0
DI0
DO1
DI1
OUT
IN
Block period is controlled by software.
(Synchronize it with the main routine.)
Fig. 2.3.26 Timing chart of serial data transmission/reception
38B5 Group User’s Manual
2-53
APPLICATION
2.3 Serial I/O
Serial I/O1 control register 1 (address 001916
)
0
0 0 0 0 1 1
0
SIO1CON1
(SC11)
Automatic transfer serial I/O (8 bits)
Internal synchronous clock (P65 pin is an I/O port.)
Serial I/O initialization
Full duplex mode
LSB first
Serial I/O1 clock pin: SCLK11
Serial I/O1 control register 2 (address 001A16
)
SIO1CON2
(SC12)
0
0
0 0 0 0
Pins P6
2
and P6
4
of I/O ports
S
OUT1 pin: Output active
P5 /SOUT1: CMOS 3-state
1
Serial I/O1 control register 3 (address 001C16
)
SIO1CON3
(SC13)
1
1 1 1 0
0
1
1
Automatic transfer interval set bits: 32 cycles of transfer clock
Internal synchronous clock: f(XIN)/32
Serial I/O1 automatic transfer data pointer (address 001816
)
SIO1DP
SIO1
0716
Set low-order 8 bits of address 0F0716 (=0716
)
Transfer counter (address 001B16
)
Set the number of transfer bytes – 1 = 7
(Automatic transfer stars by writing to this register
when selecting an internal synchronous clock.)
0716
Automatic transfer RAM of serial I/O (addresses 0F0016 to 0FFF16, its addresses 0F6016 to 0FFF16
shared by FLD automatic display RAM
SIORAM
DI
7
0F0016
0F0116
DO
7
0F0016
0F0116
DO
6
DI
6
Transfer counter
0716
Serial I/O1
automatic transfer
data pointer
0F0616
0F0716
DO
DO
1
0
0F0616
0F0716
DI
DI
1
0
Automatic transfer executed
0716
The area of addresses 0F0816 to 0FFF16, which is not used as automatic transfer,
can be used as normal RAM; the area of addresses 0F6016 to 0FFF16 can be
used as FLD automatic display RAM.
Fig. 2.3.27 Relevant registers setting
38B5 Group User’s Manual
2-54
APPLICATION
2.3 Serial I/O
RESET
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SC11 (address 001916
SC12 (address 001A16
SC13 (address 001C16
SIO1DP (address 001816
SC11 (address 001916), bit4
)
)
)
00000011
00XX0000
01111110
0716
1
2
Serial I/O1 initial setting
Setting of automatic transfer function
2
2
)
Enabled serial I/O1
Generating certain period timing using timer’s functions
(Control so that main routine will be executed at certain
period.)
N
The time to control main routine
period has passed ?
Y
Automatic transfer RAM of
serial I/O (addresses 0F0016
Transmitted
data RAM
1-block data, 8 bytes, to be transmitted set in RAM
to 0F0716
)
Number of transferred count set causing automatic
transfer start
(Set the number of transfer bytes – 1.)
SIO1 (address 001B16
)
8 – 1
Possible to process others during automatic transfer
(Perform part of main processing.)
1
Judgment of completion of automatic transfer
Taking received data into RAM for processing
SIO1CON2 (address 001A16), bit5 ?
0
Automatic transfer RAM of
serial I/O (addresses 0F0016
Received data
RAM
to 0F0716
)
Main processing
Processing data taken into received data
RAM and preparing next transmission data in
main routine
Fig. 2.3.28 Control procedure
38B5 Group User’s Manual
2-55
APPLICATION
2.3 Serial I/O
2.3.6 Serial I/O2 connection examples
(1) Control of peripheral IC equipped with CS pin
Figure 2.3.29 shows connection examples with peripheral ICs equipped with the CS pin.
(1) Only transmission
(2) Transmission and reception
(Using RxD pin as I/O port)
Port
SCLK21
TxD
CS
Port
SCLK21
TxD
CS
CLK
DATA
CLK
IN
RxD
OUT
Peripheral IC
(OSD controller etc.)
38B5 group
38B5 group
Peripheral IC
(EEPROM etc.)
(3) Transmission and reception
(When connecting RxD with TxD)
(When connecting IN with OUT in
peripheral IC)
(4) Connection of plural IC
Port
SCLK21
TxD
CS
Port
SCLK21
TxD
CS
CLK
IN
CLK
IN
RxD
OUT
RxD
OUT
Port
✽1
✽2
Peripheral IC 1
38B5 group
Peripheral IC
(EEPROM etc.)
38B5 group
CS
✽1: Select an N-channel open-drain output for TxD pin
output control.
✽2: Use the OUT pin of peripheral IC which is an N-
channel open-drain output and becomes high impe-
dance during receiving data.
CLK
IN
OUT
Peripheral IC 2
Note: “Port” means an output port controlled by software.
Fig. 2.3.29 Serial I/O2 connection examples (1)
38B5 Group User’s Manual
2-56
APPLICATION
2.3 Serial I/O
(2) Connection with microcomputer
Figure 2.3.30 shows connection examples with another microcomputer.
(1) Selecting internal clock
(2) Selecting external clock
SCLK21
TxD
CLK
SCLK21
TxD
CLK
IN
IN
RxD
OUT
RxD
OUT
38B5 group
Microcomputer
38B5 group
Microcomputer
(3) Using SRDY2 signal output function
(Selecting external clock)
(4) Using switch function of CLK signal output
pins, SCLK22, (Selecting internal clock)
SCLK21
TxD
SRDY2
SCLK21
TxD
RDY
CLK
IN
CLK
IN
RxD
OUT
SCLK22
Port
RxD
OUT
Microcomputer
38B5 group
Microcomputer
38B5 group
CLK
IN
OUT
CS
(5) In UART
Peripheral IC
TxD
RxD
RxD
TxD
38B5 group
Microcomputer
Fig. 2.3.30 Serial I/O2 connection examples (2)
38B5 Group User’s Manual
2-57
APPLICATION
2.3 Serial I/O
2.3.7 Serial I/O2’s modes
A clock synchronous or clock asynchronous (UART) can be selected for the serial I/O2.
Figure 2.3.31 shows the serial I/O2’s modes, and Figure 2.3.32 shows the serial I/O2 transfer data format.
Internal clock
Output SRDY2 signal
Clock synchronous serial I/O
External clock
Serial I/O2
Not output SRDY2 signal
Clock asynchronous serial I/O
(UART)
Fig. 2.3.31 Serial I/O2’s modes
Clock synchronous serial I/O
1ST-8DATA-1SP
ST LSB
MSB SP
1ST-7DATA-1SP
ST LSB
Serial I/O2
MSB SP
1ST-8DATA-1PAR-1SP
ST LSB
MSB PAR SP
MSB PAR SP
MSB 2SP
1ST-7DATA-1PAR-1SP
ST LSB
UART
1ST-8DATA-2SP
ST LSB
1ST-7DATA-2SP
ST LSB
MSB 2SP
1ST-8DATA-1PAR-2SP
ST LSB
MSB PAR 2SP
1ST-7DATA-1PAR-2SP
ST LSB
MSB PAR 2SP
Fig. 2.3.32 Serial I/O2 transfer data format
38B5 Group User’s Manual
2-58
APPLICATION
2.3 Serial I/O
2.3.8 Serial I/O2 application examples
(1) Communication (transmission/reception) using clock synchronous serial I/O
Outline : 2-byte data is transmitted and received, using the clock synchronous serial I/O.
The SRDY2 signal is used for communication control.
Figure 2.3.33 shows a connection diagram, and Figure 2.3.34 shows a timing chart.
P40/INT0
SCLK21
TxD
SRDY2
SCLK21
RxD
38B5 group
38B5 group
Fig. 2.3.33 Connection diagram
Specifications : • Use of serial I/O2 in clock synchronous serial I/O
• Synchronous clock frequency : 125 kHz (f(XIN) = 4 MHz is divided by 32)
• Use of SRDY2 (receivable signal)
• The reception side outputs the SRDY2 signal at intervals of 2 ms (generated by the
timer), and 2-byte data is transferred from the transmission side to the reception
side.
S
RDY2
...
...
S
CLK21
...
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
TxD
2 ms
Fig. 2.3.34 Timing chart
38B5 Group User’s Manual
2-59
APPLICATION
2.3 Serial I/O
Figure 2.3.35 shows the registers setting relevant to the transmission side, and Figure 2.3.36 shows
the registers setting relevant to the reception side.
Transmission side
Serial I/O2 status register (address 001E16)
SIO2STS
Transmit buffer empty flag
• Confirm that the data has been transferred from Transmit buffer
register to Transmit shift register.
• When this flag is “1”, it is possible to write the next transmission
data in to Transmit buffer register.
Transmit shift register shift completion flag
Confirm completion of transmitting 1-byte data with this flag.
“1” : Transmit shift completed
Serial I/O2 control register (address 001D16)
1 1 0 0
SIO2CON
0
1
0
BRG count source: f(XIN)
Synchronous clock: BRG/4
SRDY2 output not used
Transmit enabled
Receive disabled
Clock synchronous serial I/O
Serial I/O2 enabled
UART control register (address 001716)
UARTCON
0
0 0
P55/TxD pin: CMOS output
BRG clock: f(XIN)
Serial I/O2 clock: SCLK21
Baud rate generator (address 001616)
BRG
Set “division ratio – 1”
0716
Interrupt edge selection register (address 003A16)
0
INTEDGE
INT0 falling edge active
Fig. 2.3.35 Registers setting relevant to transmission side
38B5 Group User’s Manual
2-60
APPLICATION
2.3 Serial I/O
Reception side
Serial I/O2 status register (address 001E16
)
SIO2STS
SIO2CON
UARTCON
Receive buffer full flag
Confirm completion of receiving 1-byte data with this flag.
“1” : at completing reception
“0” : at reading out contents of Receive buffer register
Overrun error flag
“1” : When data is ready in Receive shift register while Receive buffer
register contains the data.
Serial I/O2 control register (address 001D16
)
1
1
1
1
1 1
Synchronous clock: External clock input
S
RDY2 output enabled
Transmit enabled
When using SRDY2 output, set this bit to “1”.
Receive disabled
Clock synchronous serial I/O
Serial I/O2 enabled
UART control register (address 001716
0
)
Serial I/O2 clock: SCLK21
Fig. 2.3.36 Registers setting relevant to reception side
38B5 Group User’s Manual
2-61
APPLICATION
2.3 Serial I/O
Figure 2.3.37 shows a control procedure of the transmission side, and Figure 2.3.38 shows a control
procedure of the reception side.
RESET
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SIO2CON (address 001D16
UARTCON (address 001716
BRG (address 001616
INTEDGE (address 003A16), bit0
)
)
1101X000
X000XXXX
8 – 1
0
2
• Serial I/O2 setting
2
)
0
IREQ1 (address 003C16), bit0 ?
• Detection of INT0 falling edge
1
IREQ1 (address 003C16), bit0
0
• Transmission data write
Transmit buffer empty flag is set to “0” by this writing.
The first byte of a
transmission data
TB/RB (address 001F16
)
• Judgment of transferring from Transmit buffer
register to Transmit shift register
(Transmit buffer empty flag)
0
SIO2STS (address 001E16), bit0 ?
1
• Transmission data write
Transmit buffer empty flag is set to “0” by this writing.
The second byte of
a transmission data
TB/RB (address 001F16
)
• Judgment of transferring from Transmit buffer
register to Transmit shift register
(Transmit buffer empty flag)
0
0
SIO2STS (address 001E16), bit0 ?
1
• Judgment of shift completion of Transmit shift register
(Transmit shift register shift completion flag)
SIO2STS (address 001E16), bit2 ?
1
Fig. 2.3.37 Control procedure of transmission side
38B5 Group User’s Manual
2-62
APPLICATION
2.3 Serial I/O
RESET
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SIO2CON (address 001D16
UARTCON (address 001716), bit6
)
1111X11X
0
2
• Serial I/O2 setting
0
• An interval of 2 ms generated by Timer.
• SRDY2 output
2ms has passed ?
1
S
RDY2 signal is output by writing data to
TB/RB (address 001F16
)
Dummy data
the TB/RB.
When using SRDY2, set Transmit enable
bit (bit4) of SIO2CON to “1.”
0
• Judgment of completion of receiving
(Receive buffer full flag)
SIO2STS (address 001E16), bit1 ?
1
• Reception of the first byte data.
Receive buffer full flag is set to “0” by reading
data.
Read out reception data from
TB/RB (address 001F16
)
0
• Judgment of completion of receiving
(Receive buffer full flag)
SIO2STS (address 001E16), bit1 ?
1
• Reception of the second byte data.
Receive buffer full flag is set to “0” by reading data.
Read out reception data from
TB/RB (address 001F16
)
Fig. 2.3.38 Control procedure of reception side
38B5 Group User’s Manual
2-63
APPLICATION
2.3 Serial I/O
(2) Output of serial data (control of peripheral IC)
Outline : Serial communication is performed, connecting port P5 with the CS pin of a peripheral IC.
7
Figure 2.3.39 shows a connection diagram, and Figure 2.3.40 shows a timing chart.
CS
P57
CS
CLK
S
CLK21
CLK
DATA
DATA
TxD
38B5 group
Peripheral IC
Fig. 2.3.39 Connection diagram
Specifications : • Use of serial I/O2 in clock synchronous serial I/O
• Synchronous clock frequency : 125 kHz (f(XIN) = 4 MHz is divided by 32)
• Transfer direction : LSB first
• Not use of receive/transmit interrupts of serial I/O2
• Port P5
7
is connected with the CS pin (“L” active) of the peripheral IC for transmission
control; the output level of port P5
7
is controlled by software.
CS
CLK
DATA
DO0
DO1
DO2
DO3
Fig. 2.3.40 Timing chart
38B5 Group User’s Manual
2-64
APPLICATION
2.3 Serial I/O
Figure 2.3.41 shows the relevant registers setting and Figure 2.3.42 shows the setting of transmission
data.
Serial I/O2 control register (address 001D16
)
1
1 0 1 1 0 0 0
SIO2CON
BRG count source: f(XIN
)
Synchronous clock: BRG/4
RDY2 output not used
S
Transmit interrupt source: When transmit shift operation is completed
Transmit enabled
Receive disabled
Clock synchronous serial I/O
Serial I/O2 enabled
UART control register (address 001716
)
UARTCON
0
0 0
P55
/TxD pin: CMOS output
BRG clock: f(XIN
)
Serial I/O2 clock: SCLK21
Baud rate generator (address 001616
)
Set “division ratio – 1”
BRG
0716
Interrupt control register 2 (address 003F16
)
0
0
ICON2
INT
3
/Serial I/O2 transmit interrupt: Disabled
Interrupt request register 2 (address 003D16
0
)
IREQ2
INT
3/serial I/O2 transmit interrupt request cleared
Confirm transmission completion of 1-byte unit.
Fig. 2.3.41 Relevant registers setting
Serial I/O2 transmit/receive buffer register (001F16
)
Set a transmission data.
Confirm that transmission of the previous data is
TB/RB
completed, where bit 4, the INT /serial I/O2
3
transmit interrupt request bit of the interrupt
request register 2, is “1”; before writing data.
Fig. 2.3.42 Setting of transmission data
38B5 Group User’s Manual
2-65
APPLICATION
2.3 Serial I/O
Figure 2.3.43 shows a control procedure.
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
Serial I/O2 setting
SIO2CON (address 001D16
)
11011000
2
UARTCON (address 001716
BRG (address 00161)
)
X000XXXX
8 – 1
2
INT3/Serial I/O2 transmit interrupt: Disabled
CS signal output level to “H” setting
CS signal output port setting
ICON2 (address 003F16), bit4
P5 (address 000A16), bit7
P5D (address 000B16), bit7
0
1
1
CS signal output level to “L” setting
P5 (address 000A16), bit7
0
IREQ2 (address 003D16), bit4
0
INT3/Serial I/O2 transmit interrupt request bit to “0” setting
Transmission data write
(Start of 1-byte data transmission)
Transmission data
TB/RB (address 001F16
)
0
Judgment of completion of transmitting 1-byte
data
IREQ2 (address 003D16), bit4 ?
1
Use any of RAM area as a counter for counting
the number of transmitted bytes.
Judgment of completion of transmitting the target
number of bytes
N
All data has been transmitted ?
Y
Returning CS signal output level to “H” when
transmission of the target number of bytes is
completed
P5 (address000A16), bit7
1
Fig. 2.3.43 Control procedure
38B5 Group User’s Manual
2-66
APPLICATION
2.3 Serial I/O
(3) Cyclic transmission or reception of block data (data of specified number of bytes) between
two microcomputers
Outline : When the clock synchronous serial I/O is used for communication, synchronization of the
clock and the data between the transmitting and receiving sides may be lost because of
noise included in the synchronous clock. It is necessary to correct that constantly, using
“heading adjustment”.
This “heading adjustment” is carried out by using the interval between blocks in this
example.
Figure 2.3.44 shows a connection diagram.
S
CLK21
S
CLK21
R
T
X
D
D
T
X
D
D
X
R
X
38B5 group
Master unit
38B5 group
Slave unit
Fig. 2.3.44 Connection diagram
Specifications: • Use of serial I/O2 in clock synchronous serial I/O
• Synchronous clock frequency : 131 kHz (f(XIN) = 4.19 MHz is divided by 32.)
• Byte cycle: 488 µs
• Number of bytes for transmission or reception : 8 bytes/block each
• Block transfer cycle : 16 ms
• Block transfer term : 3.5 ms
• Interval between blocks : 12.5 ms
• Heading adjustment time : 8 ms
• Transfer direction : LSB first
Limitations of the specifications:
• Reading of the reception data and setting of the next transmission data must be
completed within the time obtained from “byte cycle – time for transferring 1-byte
data” (in this example, the time taken from generating of the serial I/O2 receive
interrupt request to input of the next synchronous clock is 431 µs).
• “Heading adjustment time < interval between blocks” must be satisfied.
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APPLICATION
2.3 Serial I/O
The communication is performed according to the timing shown in Figure 2.3.45. In the slave unit,
when a synchronous clock is not input within a certain time (heading adjusment time), the next clock
input is processed as the beginning (heading) of a block.
When a clock is input again after one block (8 bytes) is received, the clock is ignored.
Figure 2.3.46 shows the relevant registers setting in the master unit and Figure 2.3.47 shows the
relevant registers setting in the slave unit.
D0
D1
D2
D7
D0
Byte cycle
Interval between blocks
Block transfer term
Block transfer cycle
Heading adjustment time
Processing for heading adjustment
Fig. 2.3.45 Timing chart
Master unit
Serial I/O2 control register (address 001D16
)
SIO2CON
1 1
1 1 1 0 0 0
BRG count source : f(XIN
)
Synchronous clock : BRG/4
RDY2 output disabled
S
Transmit interrupt source : Transmit shift operating completion
Transmit enabled
Receive enabled
Clock synchronous serial I/O
Serial I/O2 enabled
UART control register (address 001716
)
UARTCON
0
0 0
P55/TxD pin: CMOS output
BRG clock: f(XIN
)
Serial I/O2 clock: SCLK21
Baud rate generator (address 001616
0716
)
BRG
Set “division ratio – 1”
Fig. 2.3.46 Relevant registers setting in master unit
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APPLICATION
2.3 Serial I/O
Slave unit
Serial I/O2 control register (address 001D16
)
1 1 1 1 0 1
SIO2CON
Synchronous clock : External clock
RDY2 output disabled
S
Transmit enabled
Receive enabled
Clock synchronous serial I/O
Serial I/O2 enabled
UART control register (address 001716
)
UARTCON
0
0
P55/TxD pin: CMOS output
Serial I/O2 clock: SCLK21
Fig. 2.3.47 Relevant registers setting in slave unit
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2.3 Serial I/O
Control procedure by software:
● Control in the master unit
After setting the relevant registers shown in Figure 2.3.46, the master unit starts transmission or
reception of 1-byte data by writing transmission data to the serial I/O2 transmit buffer register.
To perform the communication in the timing shown in Figure 2.3.45, take the timing into account
and write transmission data. Additionally, read out the reception data when the serial I/O2 transmit
interrupt request bit is set to “1,” or before the next transmission data is written to the serial I/O2
transmit buffer register.
Figure 2.3.48 shows a control procedure of the master unit using timer interrupts.
Interrupt processing routine
executed every 500µs
CLT (Note 1)
CLD (Note 2)
Push register to stack
Note 1: When using the Index X mode flag (T).
Note 2: When using the Decimal mode flag (D).
Pushing the register used in the interrupt
processing routine into the stack
●
●
Generating a certain block interval by
using a timer or other functions
N
Within a block transfer
period?
Y
●
Check of the block interval counter and
determination to start a block transfer
Count a block interval counter
Read a reception data
Y
N
Complete to transfer
a block?
Start a block transfer?
Y
N
Write the first transmission data
(first byte) in a block
Write a transmission data
●
Pop registers
RTI
Popping registers which is pushed to stack
Fig. 2.3.48 Control procedure of master unit
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2.3 Serial I/O
● Control in the slave unit
After setting the relevant registers as shown in Figure 2.3.47, the slave unit becomes the state
where a synchronous clock can be received at any time, and the serial I/O2 receive interrupt
request bit is set to “1” each time an 8-bit synchronous clock is received.
In the serial I/O2 receive interrupt processing routine, the data to be transmitted next is written to
the transmit buffer register after the received data is read out.
However, if no serial I/O2 receive interrupt occurs for a certain time (heading adjustment time or
more), the following processing will be performed.
1. The first 1-byte data of the transmission data in the block is written into the transmit buffer register.
2. The data to be received next is processed as the first 1 byte of the received data in the block.
Figure 2.3.49 shows a control procedure of the slave unit using the serial I/O2 receive interrupt
and any timer interrupt (for heading adjustment).
Serial I/O2 receive interrupt
processing routine
Timer interrupt processing
routine
CLT (Note 1)
CLD (Note 2)
Push register to stack
CLT (Note 1)
CLD (Note 2)
Push register to stack
●
●
Pushing the register used in
the interrupt processing
routine into the stack
Pushing the register used
in the interrupt processing
routine into the stack.
●
Confirmation of the received
byte counter to judge the
block transfer term
Heading adjustment
counter – 1
N
Within a block transfer
term?
Y
N
Heading adjustment
counter = 0?
Read a reception data
Y
Write the first transmission
data (first byte) in a block
A received byte counter +1
A received byte counter
0
N
A received byte
counter ≥ 8?
Y
●
Pop registers
RTI
Popping registers which is
pushed to stack
Write a transmission data
Write dummy data (FF16)
Initial
value
(Note 3)
Heading
adjustment
counter
●
Popping registers which is
pushed to stack
Pop registers
Notes 1: When using the Index X mode flag (T).
2: When using the Decimal mode flag (D).
RTI
3: In this example, set the value which is equal to the
heading adjustment time divided by the timer interrupt
cycle as the initial value of the heading adjustment
counter.
For example: When the heading adjustment time is 8 ms
and the timer interrupt cycle is 1 ms, set
8 as the initial value.
Fig. 2.3.49 Control procedure of slave unit
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2.3 Serial I/O
(4) Communication (transmission/reception) using asynchronous serial I/O (UART)
Outline : 2-byte data is transmitted and received, using the asynchronous serial I/O.
Port P5
6
is used for communication control.
Figure 2.3.50 shows a connection diagram, and Figure 2.3.51 shows a timing chart.
Transmission side
Reception side
P5
6
P5
6
TX
D
RX
D
38B5 group
38B5 group
Fig. 2.3.50 Connection diagram
Specifications : • Use of serial I/O2 in UART
• Transfer bit rate : 9600 bps (f(XIN) = 3.6864 MHz is divided by 384)
• Data format : 1ST-8DADA-2ST
• Communication control using port P5
6
(The output level of port P5 is controlled by softoware.)
6
• 2-byte data is transferred from the transmission side to the receiption side at
intervals of 10 ms generated by the timer.
P5
6
....
....
TXD
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D0
ST
ST
ST
SP(2)
SP(2)
10 ms
Fig. 2.3.51 Timing chart
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APPLICATION
2.3 Serial I/O
Table 2.3.1 shows setting examples of the baud rate generator (BRG) values and transfer bit rate
values.
Table 2.3.1 Setting examples of baud rate generator values and transfer bit rate values
f(XIN) = 3.6864 MHz
f(XIN) = 4 MHz
Transfer bit rate
BRG count BRG setting
BRG count
BRG setting
value
(Note 1)
Actual rate
Actual rate
source (Note 2)
value
source (Note 2)
600
f(XIN)/4
95(5F16)
600.00
1200.00
2400.00
4800.00
9600.00
19200.00
38400.00
76800.00
—
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)
103(6716)
51(3316)
25(1916)
12(0C16)
25(1916)
12(0C16)
5(0516)
600.96
1201.92
2403.85
4807.69
9615.38
19230.77
41666.67
83333.33
31250.00
62500.00
1200
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)
f(XIN)
—
47(2F16)
23(1716)
11(0B16)
5(0516)
2(0216)
5(0516)
2(0216)
—
2400
4800
9600
19200
38400
76800
31250
62500
f(XIN)
f(XIN)
f(XIN)
2(0216)
f(XIN)
7(0716)
—
—
—
f(XIN)
3(0316)
Notes 1: Equation of transfer bit rate:
f(XIN)
Transfer bit rate (bps) =
(BRG setting value + 1) ✕ 16 ✕ m✽
✽m: When bit 0 of the serial I/O2 control register (address 001D16) is set to “0”, a value of m
is 1.
When bit 0 of the serial I/O2 control register is set to “1”, a value of m is 4.
2: Select the BRG count source with bit 0 of the serial I/O2 control register (address 001D16).
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APPLICATION
2.3 Serial I/O
Figure 2.3.52 shows the registers setting relevant to the transmission side; Figure 2.3.53 shows the
registers setting relevant to the reception side.
Transmission side
Serial I/O2 status register (address 001E 16)
b7
b0
SIO2STS
Transmit buffer empty flag
• Confirm that tha data has been transferred from Transmit buffer
register to Transmit shift register.
• When this flag is “1”, it is possible to write the next transmission
data in to Transmit buffer register.
Transmit shift register shift completion flag
Confirm completion of transmitting 1-byte data with this flag.
“1” : Transmit shift completed
Serial I/O2 control register (address 001D 16)
b7
b0
1
0 0
1
0
0 1
SIO2CON
BRG count source : f(XIN)/4
Serial I/O2 synchronous clock : BRG/16
SRDY2 output disabled
Transmit enabled
Receive disabled
Asynchronous serial I/O (UART)
Serial I/O2 enabled
UART control register (address 0017 16)
b7
b0
UARTCON
0 0
1
0
0
Character length : 8 bits
Parity checking disabled
Stop bit length : 2 stop bits
P55/TXD pin : CMOS output
BRG clock : f(XIN)
Baud rate generator (address 0016 16)
b7
b0
f(XIN)
–
1
Set
0516
BRG
Transfer bit rate ✕ 16 ✕ m ✽
When bit 0 of SIO2CON (address 001D 16) is set to “0”,
✽
a value of m is 1.
When bit 0 of SIO2CON is set to “1”, a value of m is 4.
Fig. 2.3.52 Registers setting relevant to transmission side
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APPLICATION
2.3 Serial I/O
Reception side
Serial I/O2 status register (address 001E 16
)
b7
b0
SIO2STS
Receive buffer full flag
Confirm completion of receiving 1-byte data with this flag.
“1” : at completing reception
“0” : at reading out contents of Receive buffer register
Overrun error flag
“1” : When data is ready in Receive shift register while Receive buffer
register contains the data.
Parity error flag
“1” : When a parity error occurs in enabled parity.
Framing error flag
“1” : When stop bits cannot be detected at the specified timing
Summing error flag
“1” : when any one of the following errors occurs.
• Overrun error
• Parity error
• Framing error
Serial I/O2 control register (address 001D 16
)
b7
b0
1
0 1 0
0
0
1
SIO2CON
BRG count source : f(XIN)/4
Serial I/O synchronous clock : BRG/16
SRDY output disabled
Transmit disabled
Receive enabled
Asynchronous serial I/O (UART)
Serial I/O2 enabled
UART control register (address 0017 16
)
b7
b0
UARTCON
0
1
0 0
Character length : 8 bits
Parity checking disabled
Stop bit length : 2 stop bits
BRG clock: f(XIN
)
Baud rate generator (address 0016 16
)
b7
b0
f(XIN
)
–
1
Set
BRG
0516
Transfer bit rate
✕ 16 ✕
m ✽
When bit 0 of SIO2CON (address 001D 16) is set to “0”,
a value of m is 1.
✽
When bit 0 of SIO2CON is set to “1”, a value of m is 4.
Fig. 2.3.53 Registers setting relevant to reception side
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APPLICATION
2.3 Serial I/O
Figure 2.3.54 shows a control procedure of the transmission side, and Figure 2.3.55 shows a control
procedure of the reception side.
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
• Serial I/O2 setting
1001X001
XX001X00
6 – 1
2
(address 001D16
)
SIO2CON
UARTCON
BRG
2
(address 001716
(address 001616
)
)
(address 000A16), bit6
(address 000B16), bit6
0
1
P5
P5D
• Port P5 set for communication control
6
N
10 ms has passed ?
Y
• An interval of 10 ms generated by Timer
• Communication start
P5 (address 000A16), bit6
1
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
The first byte of a
transmission data
TB/RB (address 001F16
)
• Judgment of transferring data from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
0
SIO2STS (address 001E16), bit0?
1
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
The second byte of
)
a transmission data
TB/RB (address 001F16
• Judgment of transferring data from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
0
SIO2STS (address 001E16), bit0?
1
0
• Judgment of shift completion of Transmit shift register
(Transmit shift register shift completion flag)
SIO2STS (address 001E16), bit2?
1
P5 (address 000A16), bit6
0
• Communication completion
Fig. 2.3.54 Control procedure of transmission side
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APPLICATION
2.3 Serial I/O
RESET
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SIO2CON (address 001D16
1010X001
XX0X1X00
6 – 1
2
)
• Serial I/O2 setting
2
UARTCON
BRG
(address 001716
(address 001616
)
)
0
P5D
(address 000B16), bit6
• Port P56 setting for communication control
0
SIO2STS (address 001E16), bit1?
• Judgment of completion of receiving
(Receive buffer full flag)
1
• Reception of the first byte data
Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from TB/RB (address 001F16
)
• Judgment of an error flag
1
0
SIO2STS (address 001E16), bit6?
0
• Judgment of completion of
receiving
SIO2STS (address 001E16), bit1?
(Receive buffer full flag)
1
• Reception of the second byte data
Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from TB/RB (address 001F16
)
• Judgment of an error flag
Processing for error
1
SIO2STS (address 001E16), bit0?
0
1
P5 (address 000A16), bit0?
0
SIO2CON (address 001D16
SIO2CON (address 001D16
)
)
0000X001
1010X001
2
• Countermeasure for a bit slippage
2
Fig. 2.3.55 Control procedure of reception side
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APPLICATION
2.3 Serial I/O
2.3.9 Notes on serial I/O1
(1) Clock
■ Using internal clock
After setting the synchronous clock to an internal clock, clear the serial I/O interrupt request bit
before perform the normal serial I/O transfer or the serial I/O automatic transfer.
■ Using external clock
After inputting “H” level to the external clock input pin, clear the serial I/O interrupt request bit
before performing the normal serial I/O transfer or the serial I/O automatic transfer.
(2) Using serial I/O1 interrupt
Clear bit 3 of the interrupt request register 1 to “0” by software.
(3) State of SOUT1 pin
The SOUT1 pin control bit of the serial I/O1 control register 2 can be used to select the state of the
S
OUT1 pin when serial data is not transferred; either output active or high-impedance. However, when
selecting an external synchronous clock; the SOUT1 pin can become the high-impedance state by
setting the SOUT1 pin control bit to “1” when the serial I/O1 clock input is at “H” after transfer completion.
(4) Serial I/O initialization bit
● Set “0” to the serial I/O initialization bit of the serial I/O1 control register 1 when terminating a
serial transfer during transferring.
● When writing “1” to the serial I/O initialization bit, the serial I/O1 is enabled, but each register is
not initialized. Set the value of each register by program.
(5) Handshake signal
■ SBUSY1 input signal
Input an “H” level to the SBUSY1 input and an “L” level signal to the SBUSY1 input in the initial state.
When the external synchronous clock is selected, switch the input level to the SBUSY1 input and
the SBUSY1 input while the serial I/O1 clock input is in “H” state.
■ SRDY1 input•output signal
When selecting the internal synchronous clock, input an “L” level to the SRDY1 input and an “H”
level signal to the SRDY1 input in the initial state.
(6) 8-bit serial I/O mode
■ When selecting external synchronous clock
When an external synchronous clock is selected, the contents of the serial I/O1 register are being
shifted continually while the transfer clock is input to the serial I/O1 clock pin. In this case, control
the clock externally.
(7) In automatic transfer serial I/O mode
■ Set of automatic transfer interval
● When the SBUSY1 output is used, and the SBUSY1 output and the SSTB1 output function as signals
for each transfer data set by the SBUSY1 output•SSTB1 output function selection bit of serial I/O1
control register 2; the transfer interval is inserted before the first data is transmitted/received,
and after the last data is transmitted/received. Accordingly, regardless of the contents of the
SBUSY1 output•SSTB1 output function selection bit, this transfer interval for each 1-byte data becomes
2 cycles longer than the value set by the automatic transfer interval set bits of serial I/O1 control
register 3.
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APPLICATION
2.3 Serial I/O
● When using the SSTB1 output, regardless of the contents of the SBUSY1 output•SSTB1 output function
selection bit, this transfer interval for each 1-byte data becomes 2 cycles longer than the value
set by the automatic transfer interval set bits of serial I/O1 control register 3.
● When using the combined output of SBUSY1 and SSTB1 as the signal for each of all transfer data
set, the transfer interval after completion of transmission/reception of the last data becomes 2
cycles longer than the value set by the automatic transfer interval set bits.
● Set the transfer interval of each 1-byte data transfer to 5 or more cycles of the internal clock
φ after the rising edge of the last bit of a 1-byte data.
● When selecting an external clock, the set of automatic transfer interval becomes invalid.
■ Set of serial I/O1 transfer counter
● Write the value decreased by 1 from the number of transfer data bytes to the serial I/O1 transfer
counter.
● When selecting an external clock, after writing a value to the serial I/O1 register/transfer counter,
wait for 5 or more cycles of internal clock φ before inputting the transfer clock to the serial I/
O1 clock pin.
■ Serial I/O initialization bit
A serial I/O1 automatic transfer interrupt request occurs when “0” is written to the serial I/O
initialization bit during an operation. Disable it with the interrupt enable bit as necessary by program.
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APPLICATION
2.3 Serial I/O
2.3.10 Notes on serial I/O2
(1) Notes when selecting clock synchronous serial I/O
➀ Stop of transmission operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O2 enable bit is cleared to “0” (serial I/O2 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK21, SCLK22 and SRDY2 function as I/O ports, the transmission
data is not output). When data is written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O2 enable bit is set to “1” at this time,
the data during internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the receive enable bit to “0” (receive disabled), or clear the serial I/O2 enable bit
to “0” (serial I/O2 disabled).
➂ Stop of transmit/receive operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, simultaneously clear both the transmit enable bit and receive enable bit to “0” (transmit
and receive disabled).
(when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
● Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.
If any one of transmission and reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,
the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clearing the serial I/O2 enable bit to
“0” (serial I/O2 disabled) (refer to (1), ➀).
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2.3 Serial I/O
(2) Notes when selecting clock asynchronous serial I/O
➀ Stop of transmission operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O2 enable bit is cleared to “0” (serial I/O2 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK21, SCLK22 and SRDY2 function as I/O ports, the transmission
data is not output). When data is written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O2 enable bit is set to “1” at this time,
the data during internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the receive enable bit to “0” (receive disabled).
➂ Stop of transmit/receive operation
Only transmission operation is stopped.
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O2 enable bit is cleared to “0” (serial I/O2 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK21, SCLK22 and SRDY2 function as I/O ports, the transmission
data is not output). When data is written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O2 enable bit is set to “1” at this time,
the data during internally shifting is output to the TxD pin and an operation failure occurs.
Only receive operation is stopped.
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the receive enable bit to “0” (receive disabled).
(3)
SRDY2 output of reception side
When signals are output from the SRDY2 pin on the reception side by using an external clock in the
clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY2 output enable bit, and
the transmit enable bit to “1” (transmit enabled).
(4) Setting serial I/O2 control register again
Set the serial I/O2 control register again after the transmission and the reception circuits are reset
by clearing both the transmit enable bit and the receive enable bit to “0.”
Clear both the transmit enable
bit (TE) and the receive enable
bit (RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O2 control register
Can be set with the
LDM instruction at
↓
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to “1”
the same time
Fig. 2.3.56 Sequence of setting serial I/O2 control register again
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APPLICATION
2.3 Serial I/O
(5) Data transmission control with referring to transmit shift register completion flag
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks. When data transmission is controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(6) Transmission control when external clock is selected
When an external clock is used as the synchronous clock for data transmission, set the transmit
enable bit to “1” at “H” of the serial I/O2 clock input level. Also, write the transmit data to the transmit
buffer register (serial I/O shift register) at “H” of the serial I/O2 clock input level.
(7) Transmit interrupt request when transmit enable bit is set
The transmission interrupt request bit is set and the interruption request is generated even when
selecting timing that either of the following flags is set to “1” as timing where the transmission
interruption is generated.
• Transmit buffer empty flag is set to “1”
• Transmit shift register completion flag is set to “1”
Therefore, when the transmit interrupt is used, set the transmit interrupt enable bit to transmit
enabled as the following sequence.
➀ Transmit enable bit is set to “1”
➁ Transmit interrupt request bit is set to “0”
● Reason
When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift
register completion flag are set to “1”.
(8) Using TxD pin
The P5 /TxD P-channel output disable bit of UART control register is valid in both cases: using as
5
a normal I/O port and as the TxD pin. Do not supply Vcc + 0.3 V or more even when using the P5
TxD pin as an N-channel open-drain output.
5
/
Additionally, in the serial I/O2, the TxD pin latches the last bit and continues to output it after
completing transmission.
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APPLICATION
2.4 FLD controller
2.4 FLD controller
This paragraph describes the setting method of FLD controller relevant registers, notes etc.
2.4.1 Memory assignment
Address
003D16
Interrupt request register 2 (IREQ2)
Interrupt control register 2 (ICON2)
003F16
P1FLDRAM write disable register (P1FLDRAM)
P3FLDRAM write disable register (P3FLDRAM)
FLDC mode register (FLDM)
0EF216
0EF316
0EF416
0EF516
0EF616
Tdisp time set register (TDISP)
Toff1 time set register (TOFF1)
0EF716
0EF816
0EF916
0EFA16
0EFB16
0EFC16
Toff2 time set register (TOFF2)
FLD data pointer (FLDDP)
Port P0FLD/port switch register (P0FPR)
Port P2FLD/port switch register (P2FPR)
Port P8FLD/port switch register (P8FPR)
Port P8FLD output control register (P8FLDCON)
Fig. 2.4.1 Memory assignment of FLD controller relevant registers
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APPLICATION
2.4 FLD controller
2.4.2 Relevant registers
P1FLDRAM write disable register
b7 b6 b5 b4 b3 b2 b1 b0
P1FLDRAM write disable register
(P1FLDRAM: address 0EF216)
b
0
Name
Functions
At reset R W
0
FLDRAM corre-
sponding to port
P10 write disable bit
0: Operating normally
1: Write disabled
0
0
0
0
0
0
0
1
2
3
4
5
6
7
FLDRAM corre-
sponding to port
P11 write disable bit
0: Operating normally
1: Write disabled
FLDRAM corre-
sponding to port
P12 write disable bit
0: Operating normally
1: Write disabled
FLDRAM corre-
sponding to port
P13 write disable bit
0: Operating normally
1: Write disabled
FLDRAM corre-
sponding to port
P14 write disable bit
0: Operating normally
1: Write disabled
FLDRAM corre-
sponding to port
P15 write disable bit
0: Operating normally
1: Write disabled
0: Operating normally
1: Write disabled
FLDRAM corre-
sponding to port
P16 write disable bit
FLDRAM corre-
sponding to port
P17 write disable bit
0: Operating normally
1: Write disabled
Fig. 2.4.2 Structure of P1FLDRAM write disable register
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APPLICATION
2.4 FLD controller
P3FLDRAM write disable register
b7 b6 b5 b4 b3 b2 b1 b0
P3FLDRAM write disable register
(P3FLDRAM: address 0EF316
)
b
Name
Functions
At reset R W
0
0
1
2
3
4
5
6
7
FLDRAM corre-
sponding to port
P30 write disable bit
0: Operating normally
1: Write disabled
0
0
0
0
0
0
0
FLDRAM corre-
sponding to port
P31 write disable bit
0: Operating normally
1: Write disabled
FLDRAM corre-
sponding to port
P32 write disable bit
0: Operating normally
1: Write disabled
FLDRAM corre-
sponding to port
P33 write disable bit
0: Operating normally
1: Write disabled
FLDRAM corre-
sponding to port
P34 write disable bit
0: Operating normally
1: Write disabled
FLDRAM corre-
sponding to port
P35 write disable bit
0: Operating normally
1: Write disabled
FLDRAM corre-
sponding to port
P36 write disable bit
0: Operating normally
1: Write disabled
FLDRAM corre-
sponding to port
0: Operating normally
1: Write disabled
P37 write disable bit
Fig. 2.4.3 Structure of P3FLDRAM write disable register
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APPLICATION
2.4 FLD controller
FLDC mode register
b7 b6 b5 b4 b3 b2 b1 b0
FLDC mode register
(FLDM: address 0EF416)
b
0
Name
Functions
At reset R W
0
Automatic display
control bit (P0, P1,
P2, P3, P8)
0 : General-purpose mode
1 : Automatic display
mode
Display start bit
0
0
1
2
0 : Display stopped
1 : Display in progress (display
starts by writing “1”)
Tscan control bits
b3 b2
0 0 : 0 FLD digit interrupt
(at rising edge of each
digit)
0 1 : 1 ✕ Tdisp
1 0 : 2 ✕ Tdisp
3
0
1 1 : 3 ✕ Tdisp
FLD blanking interrupt (at
falling edge of last digit)
4
5
Timing number
control bit
0 : 16 timing mode
1 : 32 timing mode (Note 2)
0
0
Gradation display
mode selection
control bit
0 : Not selected
1 : Selected (Notes 1, 2)
6
7
Tdisp counter count 0 : f(XIN)/16 or f(XCIN)/32
source selection bit 1 : f(XIN)/64 or f(XCIN)/128
0
0
High-breakdown
voltage port driv-
ability selection bit
0 : Drivability strong
1 : Drivability weak
Notes 1: When the gradation display mode is selected, the number of
timing is max. 16 timing. (Set “0” to the timing number control
bit (b4).)
2: When switching the timing number control bit (b4) or the
gradation display mode selection control bit (b5), set “0” to
the display start bit (b1) (display stop state) before that.
Fig. 2.4.4 Structure of FLD mode register
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APPLICATION
2.4 FLD controller
Tdisp time set register
b7 b6 b5 b4 b3 b2 b1 b0
Tdisp time set register
(TDISP: address 0EF516
)
b
Functions
At reset R W
0
0
1
2
3
4
5
6
7
•Set the Tdisp time.
•When a value n is written to this register, Tdisp
time is expressed as Tdisp = (n + 1) ✕ count
source.
•When reading this register, the value in the
counter is read out.
0
0
0
0
0
0
0
(Example)
When the following condition is satisfied, Tdisp
becomes 804 µs {(200 + 1) ✕ 4 µs};
•f(XIN) = 4 MHz
•bit 6 of FLDC mode register = 0
(f(XIN)/16 is selected as Tdisp counter count
source. )
•Tdisp time set register = 200 (C816).
Fig. 2.4.5 Structure of Tdisp time set register
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APPLICATION
2.4 FLD controller
Toff1 time set register
b7 b6 b5 b4 b3 b2 b1 b0
Toff1 time set register
(TOFF1: address 0EF616)
b
0
Functions
At reset R W
1
•Set the Toff1 time.
•When a value n1 is written to this register,
Toff1 time is expressed as Toff1 = n1 ✕ count
source.
1
1
1
1
1
1
1
1
2
3
4
5
6
7
(Example)
When the following condition is satisfied, Toff1
becomes 120 µs (= 30 ✕ 4 µs);
•f(XIN) = 4 MHz
•bit 6 of FLDC mode register = 0
(f(XIN)/16 is selected as Tdisp counter count
source.)
•Toff1 time set register = 30 (1E16).
Note: Set value of 0316 or more.
Fig. 2.4.6 Structure of Toff1 time set register
Toff2 time set register
b7 b6 b5 b4 b3 b2 b1 b0
Toff2 time set register
(TOFF2: address 0EF716)
b
0
Functions
At reset R W
1
•Set the Toff2 time.
•When a value n2 is written to this register,
Toff2 time is expressed as Toff2 = n2 ✕ count
source.
However, setting of Toff2 time is valid only for
the FLD port which is satisfied the following;
•gradation display mode
1
1
1
1
1
1
1
1
2
3
4
5
6
7
•value of FLD automatic display RAM (in
gradation display mode) = “1” (dark display).
(Example)
When the following condition is satisfied, Toff2
becomes 720 µs (= 180 ✕ 4 µs);
•f(XIN) = 4 MHz
•bit 6 of FLDC mode register = 0
(f(XIN)/16 is selected as Tdisp counter count
source.)
•Toff2 time set register = 180 (B416).
Note: When the Toff2 control bit (b7) of the port P8FLD output control
register (address 0EFC16) is set to “1”, set value of 0316 or
more to the Toff2 control register.
Fig. 2.4.7 Structure of Toff2 time set register
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APPLICATION
2.4 FLD controller
FLD data pointer/FLD data pointer reload register
b7 b6 b5 b4 b3 b2 b1 b0
FLD data pointer/FLD data pointer reload register
(FLDDP: address 0EF816)
b
0
Functions
At reset R W
Undefined
The start address of each data of FLD ports P0,
P1, P2, P3, and P8, which is transferred from
FLD automatic display RAM, is set to this
register.
The start address becomes the address adding
the value set to this register into the last data
address of each FLD port.
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
1
2
3
4
5
6
7
Set a value of (timing number – 1) to this
register.
The value which is set to this address is written
to the FLD data pointer reload register.
When reading data from this address, the value
in the FLD data pointer is read.
When bits 5 to 7 of this register is read, “0” is
always read.
Fig. 2.4.8 Structure of FLD data pointer/FLD data pointer reload register
Port P0FLD/port switch register
b7 b6 b5 b4 b3 b2 b1 b0
Port P0FLD/port switch register
(P0FPR: address 0EF916)
b
0
Name
Port P00FLD/port
switch bit
Functions
At reset R W
0
0 : General-purpose port
1 : FLD port
Port P01FLD/port
switch bit
Port P02FLD/port
switch bit
Port P03FLD/port
switch bit
Port P04FLD/port
switch bit
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
Port P05FLD/port
switch bit
Port P06FLD/port
switch bit
Port P07FLD/port
switch bit
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
Fig. 2.4.9 Structure of port P0FLD/port switch register
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APPLICATION
2.4 FLD controller
Port P2FLD/port switch register
b7 b6 b5 b4 b3 b2 b1 b0
Port P2FLD/port switch register
(P2FPR: address 0EFA16)
b
0
Name
Port P20FLD/port
switch bit
Functions
At reset R W
0
0 : General-purpose port
1 : FLD port
Port P21FLD/port
switch bit
Port P22FLD/port
switch bit
Port P23FLD/port
switch bit
Port P24FLD/port
switch bit
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
Port P25FLD/port
switch bit
Port P26FLD/port
switch bit
Port P27FLD/port
switch bit
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
Fig. 2.4.10 Structure of port P2FLD/port switch register
Port P8FLD/port switch register
b7 b6 b5 b4 b3 b2 b1 b0
Port P8FLD/port switch register
(P8FPR: address 0EFB16)
b
0
Name
Port P80FLD/port
switch bit
Functions
At reset R W
0
0 : General-purpose port
1 : FLD port
Port P81FLD/port
switch bit
Port P82FLD/port
switch bit
Port P83FLD/port
switch bit
Port P84FLD/port
switch bit
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
Port P85FLD/port
switch bit
Port P86FLD/port
switch bit
Port P87FLD/port
switch bit
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
Fig. 2.4.11 Structure of port P8FLD/port switch register
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APPLICATION
2.4 FLD controller
Port P8FLD output control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P8FLD output control register
(P8FLDCON : address 0EFC16)
b
0
Name
P84–P87 FLD
output reverse bit
Functions
0 : Output normally
1 : Reverse output
At reset R W
0
P84–P87/FLDRAM 0 : Operating normally
0
0
0
0
1
2
3
4
1 : Write disabled
write disable bit
P84–P87 Toff
invalid bit
0 : Operating normally
1 : Toff invalid
P84–P87 delay
control bit (Note)
P63/AN9 dimmer
output control bit
0 : No delay
1 : Delay
0 : Ordinary port
1 : Dimmer output
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
5
6
7
0
0
0 : Operating normally
Toff2 control bit
0
(falling operation)
1 : Rising operation
Note: Valid only when selecting FLD port and P84–P87 Toff invalid function
Fig. 2.4.12 Structure of port P8FLD output control register
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16)
b
0
Name
Functions
0 : No interrupt request issued
1 : Interrupt request issued
At reset R W
Timer 4 interrupt
request bit (Note)
Timer 5 interrupt
request bit
Timer 6 interrupt
request bit
Serial I/O2 receive 0 : No interrupt request issued
interrupt request bit
INT3/serial I/O2
✽
✽
✽
✽
✽
0
0
0
0
0
0 : No interrupt request issued
1 : Interrupt request issued
1
2
3
4
0 : No interrupt request issued
1 : Interrupt request issued
1 : Interrupt request issued
0 :
No interrupt request issued
1 : Interrupt request issued
transmit interrupt
request bit (Note)
✽
✽
0 : No interrupt request issued
1 : Interrupt request issued
0
0
0
INT4 interrupt
request bit
A-D converter
interrupt request bit
FLD blanking
interrupt request bit
FLD digit interrupt
request bit
5
6
7
0 : No interrupt request issued
1 : Interrupt request issued
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
✽: “0” can be set by software, but “1” cannot be set.
Note: In the mask option type P, if timer 4 interrupt whose count source is
CNTR1 input and INT3 interrupt are selected, these bits do not
become “1”.
Fig. 2.4.13 Structure of interrupt request register 2
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APPLICATION
2.4 FLD controller
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2
(ICON2 : address 3F16
)
b
0
Name
Functions
At reset R W
0
Timer 4 interrupt
enable bit (Note)
Timer 5 interrupt
enable bit
Timer 6 interrupt
enable bit
Serial I/O2 receive
interrupt enable bit
INT3/serial I/O2
0 : interrupt disabled
1 : Interrupt enabled
0
0
0
0
1
2
3
4
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
transmit interrupt
enable bit (Note)
0
0
0
INT4 interrupt
enable bit
5
6
7
0 : interrupt disabled
1 : Interrupt enabled
A-D converter
interrupt enable bit
FLD blanking
interrupt enable bit
FLD digit interrupt
enable bit
0 : interrupt disabled
1 : Interrupt enabled
Fix “0” to this bit.
Note: In the mask option type P, timer 4 interrupt whose count source
is CNTR input and INT interrupt are not available.
1
3
Fig. 2.4.14 Structure of interrupt control register 2
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APPLICATION
2.4 FLD controller
2.4.3 FLD controller application examples
(1) Key-scan using FLD automatic display and segments
Outline: Key read-in with segment pins is performed by software using the FLD automatic display
mode.
SUN MON TUE WED THU FRI SAT
P10–P17
Digit
SP EP
REC
P3
0
, P3
1
●
●
AM
PM
●
●
Segment
Segment
■
CH
P00
, P0
1
L
R
P2
P0 –P0
38B5 Group
0
–P2
7
LEVEL
4
7
Panel with fluorescent display (FLD)
Key-matrix
Fig. 2.4.15 Connection diagram
Specifications: •Use of total 20 FLD ports (10 digits; 10 segments (8 key-scan included))
•Use of FLD automatic display mode
•Display in gradation display mode and 16 timing mode
•Toff1 = 40 µs, Toff2 = 64 µs, Tdisp = 204 µs, Tscan = 3 ✕ Tdisp = 720 µs,
f(XIN) = 4 MHz
•Use of FLD blanking interrupt
Figure 2.4.16 shows the timing chart of key-scan, and Figure 2.4.17 shows the enlarged view of
Tscan. After switching the segment pin to an output port, generate the waveform shown Figure 2.4.17
by software and perform key-scan.
Tdisp
Tscan
FLD16 (P1
0)
Toff1
Toff2
FLD17 (P1
1
)
)
FLD18 (P1
2
FLD25 (P3
1)
FLD blanking interrupt request occur
Key-scan
FLD
(P2
P0
0–FLD9
• • •
0
–P2
7
,
0
, P0
1
)
Fig. 2.4.16 Timing chart of key-scan using FLD automatic display mode and segments
FLD
0
1
(P2
0
)
)
FLD
(P2
1
2
FLD
2
7
(P2
)
)
FLD
(P2
7
Fig. 2.4.17 Enlarged view of FLD0 (P20) to FLD
7
(P2 ) Tscan
7
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APPLICATION
2.4 FLD controller
Figure 2.4.18 shows the setting of relevant registers.
Port P0 direction register (address 000116
)
P0D
P2D
0
0 0 0
Set P0
4
to P07 to input ports for key-scan input
Port P2 direction register (address 000516
)
1
1 1 1 1 1
1
1
Set P2
0
to P2 to output ports for key-scan output
7
Port P0FLD/port switch register (address 0EF916
)
P0FPR
0 0 0 0 0 0 1 1
Set P0
0
, P0
–P0
1
7
to FLD ports (FLD
8
, FLD )
9
Set P0
2
to general-purpose I/O ports
Port P2FLD/port switch register (address 0EFA16
)
P2FPR
1
1 1 1 1 1 1 1
Set P20–P2
7
to FLD ports (FLD
0
–FLD )
7
FLDC mode register (address 0EF416
1 0
)
FLDM
1
0
1 1 0 1
Automatic display mode
Display stopped
Tscan = 3 ✕ Tdisp FLD blanking interrupt
16 timing mode
Gradation display mode selected
Tdisp counter count source : f(XIN)/16
High-breakdown voltage port drivability weak
Fig. 2.4.18 Setting of relevant registers
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APPLICATION
2.4 FLD controller
Tdisp time set register (address 0EF516
)
50 (3216) set; (50 + 1) ✕ count source = 204 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
TDISP
TOFF1
TOFF2
3216
Toff1 time set register (address 0EF616
)
10 (A16) set; 10 ✕ count source = 40 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
A
16
Toff2 time set register (address 0EF716
)
16 (1016) set; 16 ✕ count source = 64 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
1016
Note: Perform this setting when the gradation display mode is selected.
FLD data pointer (address 0EF816
)
0
0 0 0 1 0 0 1
FLDDP
Set {(digit number) – 1} = 9
P1FLDRAM write disable register (address 0EF216
)
P1FLDRAM
1 1
1
1 1 1 1 1
Disable writing to FLDRAM corresponding to P10 to P17
P3FLDRAM write disable register (address 0EF316
)
P3FLDRAM
1 1
Disable writing to FLDRAM corresponding to P30, P31
Interrupt request register 2 (address 003D16
0
)
IREQ2
Clear FLD blanking interrupt request bit
Interrupt control register 2 (address 003F16
)
ICON2
0
1
FLD blanking interrupt: Enabled
FLDC mode register (address 0EF416
)
FLDM
1
0 1 0 1 1 1 1
Display start
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APPLICATION
2.4 FLD controller
Setting of FLD automatic display RAM:
Table 2.4.1 FLD automatic display RAM map
1 to 16 timing display data stored area
Gradation display control data stored area
Corresponding
digit pin
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0FB016 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0FB116 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0FB216 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0FB316 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0FB416 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0F6016 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0F6116 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0F6216 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0F6316 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0F6416 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
→ FLD25 (P31)
→ FLD24 (P30)
→ FLD23 (P17)
→ FLD22 (P16)
→ FLD21 (P15)
→ FLD20 (P14)
→ FLD19 (P13)
→ FLD18 (P12)
→ FLD17 (P11)
→ FLD16 (P10)
FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0FB516
0FB616
0FB716
0FB816
0F6516
0F6616
0F6716
0F6816
0FB916 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0F6916 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0F6A16
0F6B16
0F6C16
0F6D16
0F6E16
0F6F16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
0F7016
0F7116
0F7216
0F7316
0F7416
0F7516
0F7616
0F7716
0F7816
0F7916
0F7A16
0F7B16
0F7C16
0F7D16
0F7E16
0F7F16
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
→ FLD25 (P31)
→ FLD24 (P30)
→ FLD23 (P17)
→ FLD22 (P16)
→ FLD21 (P15)
→ FLD20 (P14)
→ FLD19 (P13)
→ FLD18 (P12)
→ FLD17 (P11)
→ FLD16 (P10)
0FD016 FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
0FD116 FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
0FD216 FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
0FD316 FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
0FD416 FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
0F8016 FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
0F8116 FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
0F8216 FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
0F8316 FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
0F8416 FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
0F8516
0F8616
0F8716
0F8816
0F8916
0F8A16
0F8B16
0F8C16
0F8D16
0F8E16
0F8F16
0F9016
0F9116
0F9216
0F9316
0F9416
0F9516
0F9616
0F9716
0F9816
0F9916
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
: Area which is used to set segment data
: Area which is used to set digit data
: Area which is available as ordinary RAM
38B5 Group User’s Manual
2-96
APPLICATION
2.4 FLD controller
FLD18
FLD19
FLD20
FLD21
FLD22 FLD23
FLD24
FLD25
a
SUN MON
TUE WED THU FRI SAT
f
b
c
g
•
•
•
SP EP
AM
PM
REC
e
•
CH
■
d
FLD17
FLD16
L
LEVEL
R
Fig. 2.4.19 FLD digit allocation example
Table 2.4.2 FLD automatic display RAM map example
Gradation display control data stored area
1 to 16 timing display data stored area
Corresponding
digit pin
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
g
g
g
g
g
g
g
g
g
g
g
g
g
g
0FB016
0FB116
0FB216 FRI
0FB316 WED
0FB416 MON
0FB516 SUN
f
f
f
f
f
f
f
e
e
e
e
e
e
e
d
d
d
d
d
d
d
c
c
c
c
c
c
c
b
b
b
b
b
b
b
a
a
a
a
a
a
a
EP
0F6016
0F6116
0F6216 FRI
0F6316 WED
0F6416 MON
0F6516 SUN
f
f
f
f
f
f
f
e
e
e
e
e
e
e
d
d
d
d
d
d
d
c
c
c
c
c
c
c
b
b
b
b
b
b
b
a
a
a
a
a
a
a
EP
CH
SAT
CH
SAT
→ FLD25 (P31)
→ FLD24 (P30)
→ FLD23 (P17)
→ FLD22 (P16)
→ FLD21 (P15)
→ FLD20 (P14)
→ FLD19 (P13)
→ FLD18 (P12)
→ FLD17 (P11)
→ FLD16 (P10)
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
–
■
0F6616
0F6716
0F6816
0F6916
0F6A16
0F6B16
0F6C16
0F6D16
0F6E16
0F6F16
0F7016
0F7116
0F7216
0F7316
0F7416
0F7516
0F7616
0F7716
0F7816
0F7916
–
■
REC SP
REC SP
→ FLD25 (P31)
→ FLD24 (P30)
→ FLD23 (P17)
→ FLD22 (P16)
→ FLD21 (P15)
→ FLD20 (P14)
→ FLD19 (P13)
→ FLD18 (P12)
→ FLD17 (P11)
→ FLD16 (P10)
PM AM
THU
PM AM
THU
TUE
TUE
•
•
•
•
•
•
•
•
L
R
L
R
LEVEL
LEVEL
: Unused
38B5 Group User’s Manual
2-97
APPLICATION
2.4 FLD controller
Control procedure:
RESET
Initialization
Port direction registers setting
P0D (address 000116), bit 4–bit 7
P2D (address 000516)
00002
111111112
000000112
111111112
101011012
3216
FLD port setting
P0FPR (address 0EF916)
P2FPR (address 0EFA16)
FLDM (address 0EF416)
TDISP (address 0EF516)
TOFF1 (address 0EF616)
TOFF2 (address 0EF716)
FLDDP (address 0EF816)
FLD automatic display function setting
A16
1016 (Note 1)
000010012
Digit data and segment data setting
FLD automatic display RAM
(addresses 0FB016–0FE916)
Data to be
display
Gradation display control
RAM
(addresses 0F6016–0F9916)
Gradation display control data setting
Set “1” for dark display
Gradation display
control data (Note 1)
Set “0” for bright display (Note 2)
P1FLDRAM (address 0EF216)
P3FLDRAM (address 0EF316)
111111112
000000112
(Note 3)
Writing data to digit pin disabled
FLD blanking interrupt request bit cleared
IREQ2 (address 003D16), bit 6
1 cycle or more wait
0
Wait until writing to FLD blanking interrupt request
bit is completed
1
1
FLD blanking interrupt enabled
FLD automatic display start
I ON2 (address 003F16), bit 6
C
FLDM (address 0EF416), bit 1
Main processing
Notes 1: When selecting the gradation display, set these
registers, too.
2: The display data can be rewritten at arbitrary
timing.
3: Set these registers according to necessity.
Fig. 2.4.20 Control procedure
38B5 Group User’s Manual
2-98
APPLICATION
2.4 FLD controller
FLD blanking interrupt routine
Push registers to stack, etc.
Segment key-scan
FLDM (address 0EF416), bit 0
P1 (address 000216)
P3 (address 000616), bit 0, bit 1
P2FPR (address 0EFA16)
P2 (address 000416)
0
0016
002
000000002
0016
Switching from automatic display mode to general-purpose mode
Setting of “L” level to port corresponding to digit
Setting of port to be used for key-scan to general-purpose port
Output of “L” level from all ports for key-scan
Set data table for key-scan to P2 (address
000416)
Wait for key-scan
Wait until “H” level output of P2 is stabilized
Keys read-in
(Set the port P0 direction register (P0D) (address
000116) to the input mode in the initialization, etc.)
Transfer the contents of P04 to P07 (address
000016) to RAM
Data table reference pointer for the next key-scan updated
Update the data table pointer for key-scan
N
Key-scan is completed ? (Note)
Y
Setting of flag which judge whether key-scan is completed or not
Set key-scan completion flag
Initialize data table pointer for key-scan
Output of “L” level from all key-scan ports
Setting of general-purpose ports to FLD ports
Switching from general-purpose mode to the automatic
display mode
P2 (address 000416)
P2FPR (address 0EFA16)
FLDM (address 0EF416), bit 0
0016
111111112
1
Note: If key-scan is not completed within Tscan set
RTI
time, perform key-scan separately.
38B5 Group User’s Manual
2-99
APPLICATION
2.4 FLD controller
(2) Key-scan using FLD automatic display and digits
Outline: Key read-in with digit output waveforms is performed by software using the FLD automatic
display mode.
SUN MON TUE WED THU FRI SAT
P00, P01
P20–P27
Segment
SP EP
REC
●
●
AM
PM
●
●
Digit
Digit
■
CH
P30, P31
P10–P17
L
R
LEVEL
P04–P07
Panel with fluorescent display (FLD)
38B5 Group
Key-matrix
Fig. 2.4.21 Connection diagram
Specifications: •Use of total 20 FLD ports (10 digits, 8 key-scan included; 10 segments)
•Use of FLD automatic display mode
•Display in gradation display mode and 16 timing mode
•Toff1 = 40 ms, Toff2 = 64 ms, Tdisp = 204 ms, Tscan = 0 ms, f(XIN) = 4 MHz
•Use of FLD digit interrupt
38B5 Group User’s Manual
2-100
APPLICATION
2.4 FLD controller
Figure 2.4.22 shows the timing chart of key-scan.
Tscan = 0 µs
Tdisp
Toff1
FLD16 (P10)
FLD digit interrupt request occur
Toff2
FLD17 (P11)
FLD digit interrupt request occur
FLD18 (P12)
•
FLD digit interrupt request occur
•
•
•
•
FLD25 (P31)
FLD digit interrupt request occur
FLD0–FLD9
(P20–P27,
P00, P01)
Fig. 2.4.22 Timing chart of key-scan using FLD automatic display mode and digits
38B5 Group User’s Manual
2-101
APPLICATION
2.4 FLD controller
Figure 2.4.23 shows the setting of relevant registers.
Port P0 direction register (address 000116
)
P0D
0
0 0 0
Set P0
4
to P0
7
to input ports for key-scan input
)
Port P0FLD/port switch register (address 0EF916
P0FPR
1 1
0
0 0 0 0 0
Set P0
0
, P0
–P0
1
7
to FLD ports (FLD
8
, FLD
9
)
Set P0
2
to general-purpose I/O ports
Port P2FLD/port switch register (address 0EFA16
)
P2FPR
1
1 1 1 1 1 1 1
Set P20–P2
7
to FLD ports (FLD
0
–FLD )
7
FLDC mode register (address 0EF416
1 0
)
FLDM
1
0
0 0 0 1
Automatic display mode
Display stopped
0 FLD digit interrupt
16 timing mode
Gradation display mode selected
Tdisp counter count source : f(XIN)/16
High-breakdown voltage port drivability weak
Fig. 2.4.23 Setting of relevant registers
38B5 Group User’s Manual
2-102
APPLICATION
2.4 FLD controller
Tdisp time set register (address 0EF516
)
50 (3216) set; (50 + 1) ✕ count source = 204 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
TDISP
TOFF1
TOFF2
3216
Toff1 time set register (address 0EF616
)
10 (A16) set; 10 ✕ count source = 40 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
A
16
Toff2 time set register (address 0EF716
)
16 (1016) set; 16 ✕ count source = 64 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
1016
Note: Perform this setting when the gradation display mode is selected.
FLD data pointer (address 0EF816
)
0
0 0 0 1 0 0 1
FLDDP
Set {(digit number) – 1} = 9
P1FLDRAM write disable register (address 0EF216
)
P1FLDRAM
1 1
1
1 1 1 1 1
Disable writing to FLDRAM corresponding to P10 to P17.
P3FLDRAM write disable register (address 0EF316
)
P3FLDRAM
1 1
Disable writing to FLDRAM corresponding to P30, P31.
Interrupt request register 2 (address 003D16
0
)
IREQ2
Clear FLD digit interrupt request bit
Interrupt control register 2 (address 003F16
)
ICON2
0
1
FLD digit interrupt: Enabled
FLDC mode register (address 0EF416
)
FLDM
1
0 1 0 0 0 1 1
Display start
38B5 Group User’s Manual
2-103
APPLICATION
2.4 FLD controller
Setting of FLD automatic display RAM:
Table 2.4.3 FLD automatic display RAM map
1 to 16 timing display data stored area
Gradation display control data stored area
Corresponding
digit pin
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0FB016 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0FB116 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0FB216 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0FB316 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0FB416 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0F6016 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0F6116 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0F6216 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0F6316 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0F6416 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
→ FLD25 (P31)
→ FLD24 (P30)
→ FLD23 (P17)
→ FLD22 (P16)
→ FLD21 (P15)
→ FLD20 (P14)
→ FLD19 (P13)
→ FLD18 (P12)
→ FLD17 (P11)
→ FLD16 (P10)
FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0FB516
0FB616
0FB716
0FB816
0F6516
0F6616
0F6716
0F6816
0FB916 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0F6916 FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0F6A16
0F6B16
0F6C16
0F6D16
0F6E16
0F6F16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
0F7016
0F7116
0F7216
0F7316
0F7416
0F7516
0F7616
0F7716
0F7816
0F7916
0F7A16
0F7B16
0F7C16
0F7D16
0F7E16
0F7F16
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
FLD9 FLD8
→ FLD25 (P31)
→ FLD24 (P30)
→ FLD23 (P17)
→ FLD22 (P16)
→ FLD21 (P15)
→ FLD20 (P14)
→ FLD19 (P13)
→ FLD18 (P12)
→ FLD17 (P11)
→ FLD16 (P10)
0FD016 FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
0FD116 FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
0FD216 FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
0FD316 FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
0FD416 FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
0F8016 FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
0F8116 FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
0F8216 FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
0F8316 FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
0F8416 FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
0F8516
0F8616
0F8716
0F8816
0F8916
0F8A16
0F8B16
0F8C16
0F8D16
0F8E16
0F8F16
0F9016
0F9116
0F9216
0F9316
0F9416
0F9516
0F9616
0F9716
0F9816
0F9916
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
FLD25FLD24
: Area which is used to set segment data
: Area which is used to set digit data
: Area which is available as ordinary RAM
38B5 Group User’s Manual
2-104
APPLICATION
2.4 FLD controller
FLD18
FLD19
FLD20
FLD21
FLD22 FLD23
FLD24
FLD25
a
SUN MON
TUE WED THU FRI SAT
f
b
c
g
•
•
•
SP EP
AM
PM
REC
e
•
CH
■
d
FLD17
FLD16
L
LEVEL
R
Fig. 2.4.24 FLD digit allocation example
Table 2.4.4 FLD automatic display RAM map example
Gradation display control data stored area
1 to 16 timing display data stored area
Corresponding
digit pin
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
g
g
g
g
g
g
g
g
g
g
g
g
g
g
0FB016
0FB116
0FB216 FRI
0FB316 WED
0FB416 MON
0FB516 SUN
f
f
f
f
f
f
f
e
e
e
e
e
e
e
d
d
d
d
d
d
d
c
c
c
c
c
c
c
b
b
b
b
b
b
b
a
a
a
a
a
a
a
EP
0F6016
0F6116
0F6216 FRI
0F6316 WED
0F6416 MON
0F6516 SUN
f
f
f
f
f
f
f
e
e
e
e
e
e
e
d
d
d
d
d
d
d
c
c
c
c
c
c
c
b
b
b
b
b
b
b
a
a
a
a
a
a
a
EP
CH
SAT
CH
SAT
→ FLD25 (P31)
→ FLD24 (P30)
→ FLD23 (P17)
→ FLD22 (P16)
→ FLD21 (P15)
→ FLD20 (P14)
→ FLD19 (P13)
→ FLD18 (P12)
→ FLD17 (P11)
→ FLD16 (P10)
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
–
■
0F6616
0F6716
0F6816
0F6916
0F6A16
0F6B16
0F6C16
0F6D16
0F6E16
0F6F16
0F7016
0F7116
0F7216
0F7316
0F7416
0F7516
0F7616
0F7716
0F7816
0F7916
–
■
REC SP
REC SP
→ FLD25 (P31)
→ FLD24 (P30)
→ FLD23 (P17)
→ FLD22 (P16)
→ FLD21 (P15)
→ FLD20 (P14)
→ FLD19 (P13)
→ FLD18 (P12)
→ FLD17 (P11)
→ FLD16 (P10)
PM AM
THU
PM AM
THU
TUE
TUE
•
•
•
•
•
•
•
•
L
R
L
R
LEVEL
LEVEL
: Unused
38B5 Group User’s Manual
2-105
APPLICATION
2.4 FLD controller
Control procedure:
RESET
Initialization
Port direction register setting
00002
P0D (address 000116), bit 4–bit 7
P0FPR (address 0EF916)
P2FPR (address 0EFA16)
FLDM (address 0EF416)
TDISP (address 0EF516)
TOFF1 (address 0EF616)
TOFF2 (address 0EF716)
FLDDP (address 0EF816)
000000112
111111112
101000012
3216
A16
1016 (Note 1)
000010012
FLD port setting
FLD automatic display function setting
FLD automatic display RAM
(addresses 0FB016–0FE916)
Data to be
display
Digit data and segment data setting (Note 2)
Gradation display control
RAM
(addresses 0F6016–0F9916)
Setting of gradation display control data
Set “1” for dark display
Gradation display
control data (Note 1)
Set “0” for bright display (Note 2)
P1FLDRAM (address 0EF216)
P3FLDRAM (address 0EF316)
111111112
000000112
(Note 3)
Writing data to digit pin disabled
FLD digit interrupt request bit cleared
IREQ2 (address 003D16), bit 6
1 cycle or more wait
0
Wait until writing to the FLD digit interrupt request
bit is completed
1
1
ICON2 (address 003F16), bit 6
FLDM (address 0EF416), bit 1
FLD digit interrupt enabled
FLD automatic display start
Main processing
Notes 1: When selecting the gradation display, set these
registers, too.
2: The display data can be rewritten at arbitrary
timing.
3: Set these registers according to necessity.
Fig. 2.4.25 Control procedure
38B5 Group User’s Manual
2-106
APPLICATION
2.4 FLD controller
FLD digit interrupt routine
Push registers to stack, etc.
Digit key-scan
Wait until the digit output is stabilized since the digit
output waveform may become dull depending on the
PCB pattern wiring length etc.
Wait for key-scan
Keys read-in
(Set the port P0 direction register (P0D) (address
000116) to the input mode in the initialization, etc.)
Transfer the contents of P04 to P07
(address 000016) to RAM
Store the contents of RAM to the buffer
RTI
38B5 Group User’s Manual
2-107
APPLICATION
2.4 FLD controller
(3) FLD display by software (example of not used FLD controller)
Outline: FLD display and key read-in is performed, using a timer interrupt.
SUN MON TUE WED THU FRI SAT
P10–P17
Digit
SP EP
REC
P3
0
, P3
1
●
●
AM
PM
●
●
Segment
Segment
■
CH
P00
, P0
1
L
R
P2
P0 –P0
38B5 Group
0
–P2
7
LEVEL
4
7
Panel with fluorescent display (FLD)
Key-matrix
Fig. 2.4.26 Connection diagram
Specifications: •Use of 10 digits and 10 segments (8 key-scan included)
•Display controlled by software
•Use of timer 1 interrupt
Figure 2.4.27 shows the timing chart of FLD display by software, and Figure 2.4.28 shows the
enlarged view of P2
perform key-scan.
0
to P2
7
key-scan. Generate the waveform shown Figure 2.4.28 by software and
P1
0
1
P1
P1
2
1
P3
Key-scan
P2
0
–P2
7
1
,
• • •
P00
, P0
Fig. 2.4.27 Timing chart of FLD display by software
P20
P21
P22
P27
Fig. 2.4.28 Enlarged view of P2
0
to P2
7
key-scan
38B5 Group User’s Manual
2-108
APPLICATION
2.4 FLD controller
Figure 2.4.29 shows the setting of relevant registers.
Port P0 direction register (address 000116)
P0D
0 0 0 0
Set P04 to P07 to input ports for key scan input
Port P2 direction register (address 000516)
1 1
P2D 1 1 1 1 1 1
Set P20 to P27 to output ports for key scan output
FLDC mode register (address 0EF416)
0 0
1
FLDM
General-purpose mode
Display stopped
High-breakdown voltage port drivability weak
Interrupt request register 1 (address 003C16)
0
IREQ1
Clear timer 1 interrupt request bit
Interrupt control register 1 (address 003E16)
1
ICON1
T12M
Timer 1 interrupt: Enabled
Timer 12 mode register (address 002816)
0
Timer 1 count start
Fig. 2.4.29 Setting of relevant registers
38B5 Group User’s Manual
2-109
APPLICATION
2.4 FLD controller
P12
P13
P14
P15
P16
P17
P30
P31
a
g
SUN MON
TUE WEDTHU FRI SAT
f
b
c
SP EP
REC
•
•
•
•
AM
PM
e
CH
■
d
P11
P10
L
R
LEVEL
Fig. 2.4.30 FLD digit allocation example
Table 2.4.5 FLD automatic display RAM map example
Corresponding
digit pin
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
g
g
g
g
g
g
g
0FB016
0FB116
0FB216 FRI
0FB316 WED
0FB416 MON
0FB516 SUN
f
f
f
f
f
f
f
e
e
e
e
e
e
e
d
d
d
d
d
d
d
c
c
c
c
c
c
c
b
b
b
b
b
b
b
a
a
a
a
a
a
a
EP
CH
SAT
→ P31
→ P30
→ P17
→ P16
→ P15
→ P14
→ P13
→ P12
→ P11
→ P10
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
–
■
REC SP
→ P31
→ P30
→ P17
→ P16
→ P15
→ P14
→ P13
→ P12
→ P11
→ P10
PM AM
THU
TUE
•
•
•
•
L
R
LEVEL
: Unused
(The automatic display is not performed because FLD controller is not used.)
38B5 Group User’s Manual
2-110
APPLICATION
2.4 FLD controller
Control procedure:
●X: This bit is not used for this application.
RESET
Set “0” or “1” to this bit arbitrarily.
Initialization
Port direction registers setting
P0D (address 000116), bit 4–bit 7
P2D (address 000516
FLDM (address 0EF416
0000
11111111
1XXXXX00
2
)
2
)
2
IREQ1 (address 003C16), bit 5
0
Timer 1 interrupt request bit cleared
Wait until completion of writing to timer 1 interrupt request bit
Timer 1 interrupt: Enabled
Timer 1 count start
ICON1 (address 003E16), bit 5
T12M (address 002816), bit 0
1
0
Timer 1 interrupt routine
Segment key-scan
Push registers to stack, etc.
FLD display turned off
P0 (address 000016), bit 0, bit 1
002
P1 (address 000216
P2 (address 000416
)
)
0016
0016
P3 (address 000616), bit 0, bit 1
002
N
All column display is completed ?
Y
Segment
data
P0 (address 000016), bit 0, bit 1
P2 (address 000416
)
P1 (address 000216
)
Digit data
P3 (address 000616), bit 0, bit 1
Set data table for key-scan to P2 (address 000416
)
Wait until “H” level output of P2
is stabilized.
Wait for key-scan
Keys read-in
(Set the port P0 direction register (P0D) (address
000116) to the input mode on initialization, etc.)
Transfer the contents of P0
4 to P07
(address 000016) to RAM
Update the data table pointer for key-scan
N
Key-scan is completed ?
Y
RTI
Fig. 2.4.31 Control procedure
38B5 Group User’s Manual
2-111
APPLICATION
2.4 FLD controller
(4) Display by combination with digit expander (M35501FP*) (basic combination example)
* For M35501FP, refer to section “3.12 M35501FP”.
Outline: The fluorescent display which has many display numbers (36 segments ✕ 16 digits) is
displayed by using the digit expander (M35501FP).
38B5 Group
M35501FP
P5
P5
P8
0
RESET
SEL
1
7
CLK
P2
P0
P1
P3
P8
0
0
0
0
0
–P2
7
7
7
7
3
OVFIN
–P0
–P1
–P3
–P8
DIG
0
–DIG15
Digit (16)
Fluorescent display (FLD)
REC
DISC
TRACK
DATE
Y
M
D
SLEEP
CLOCK
Segment (36)
1
2
3
4
5
6
7
8
9
s
h
m
10 11 12 13 14 15 16 17 18
19 20 21 22 23 24 25 26 27
28 29 30 31 32 33 34 35 36
REC
Fig. 2.4.32 Connection diagram
Specifications: •Use of M35501FP (M35501FP: 16 digits, 38B5 Group: 3_6___s__e__g__m___ents)
Ports P5 and P5 of 38B5 Group supply signals to the RESET and SEL pins of
M35501FP respectively.
The P8 pin (FLD port vacant pin) supply signals to the CLK pin of M35501FP.
0
1
7
•Use of FLD automatic display mode of 38B5 Group
•Display in gradation display mode and 16 timing mode
•Toff1 = 40 µs, Toff2 = 64 µs, Tdisp = 204 µs, f(XIN) = 4 MHz
Figure 2.4.33 shows the timing chart of 38B5 Group and M35501FP, and Figure 2.4.34 shows the
timing chart (enlarged view) of digit and segment output.
38B5 Group User’s Manual
2-112
APPLICATION
2.4 FLD controller
M35501FP
RESET
SEL
OVFIN
OVFOUT
CLK
DIG0
DIG1
DIG2
DIG3
DIG12
DIG13
DIG14
DIG15
38B5 Group
FLD0–FLD35
(P2
P1
0
0
–P2
7
, P0
0
–P0
7
,
,
–P1
7
, P3
0
–P3
7
P80–P83)
Fig. 2.4.33 Timing chart of 38B5 Group and M35501FP
M35501FP
CLK
Tdisp
DIG0
Toff1
DIG1
DIG2
Toff2
DIG15
38B5 Group
FLD0–FLD35
(P2
P1
0
0
–P2
7
, P0
0
–P0
7
,
,
• • •
–P1
7, P3
0
–P3
7
P80–P83)
Fig. 2.4.34 Timing chart (enlarged view) of digit and segment output
38B5 Group User’s Manual
2-113
APPLICATION
2.4 FLD controller
Figure 2.4.35 shows the setting of relevant registers.
Port P0FLD/port switch register (address 0EF916
)
P0FPR
P2FPR
P8FPR
1 1 1 1 1 1 1 1
Set P0
0
–P0
7
to FLD output ports (FLD –FLD15)
8
Port P2FLD/port switch register (address 0EFA16
1 1 1 1 1 1 1 1
)
Set P2
0
–P2
7
to FLD output ports (FLD
0
–FLD )
7
Port P8FLD/port switch register (address 0EFB16
1 0 0 0 1 1 1 1
)
Set P8
0
–P8
–P8
3
6
to FLD output ports (FLD32–FLD35
to general-purpose I/O ports
)
Set P8
4
Set P8
7
to FLD output port (FLD39
)
Port P5 direction register (address 000B16
0 0 0 0 0 0 1 1
)
P5D
Set P5
0
1
to output port (for M35501 RESET signal)
to output port (for M35501 SEL signal)
Set P5
Port P5 (address 000A16
)
P5 0 0 0 0 0 0 0 0
M35501 RESET signal output (Note 1)
M35501 SEL signal “L” output
Note 1: After retain RESET signal output “L” for 2 µs or more, release reset by outputting “H” level
from RESET signal output at CLK signal = “L” .
Fig. 2.4.35 Setting of relevant registers
38B5 Group User’s Manual
2-114
APPLICATION
2.4 FLD controller
FLDC mode register (address 0EF416
1 0 1 0 0 0 0 1
)
FLDM
Automatic display mode
Display stopped
Tscan = 0 FLD digit interrupt
16 timing mode
Gradation display mode selected
Tdisp counter count source : f(XIN)/16
High-breakdown voltage port drivability weak
Tdisp time set register (address 0EF516
)
50 (3216) set; (50 + 1) ✕ count source = 204 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
TDISP
TOFF1
TOFF2
3216
Toff1 time set register (address 0EF616
)
10 (A16) set; 10 ✕ count source = 40 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
A
16
Toff2 time set register (address 0EF716) (Note 2)
16 (1016) set; 16 ✕ count source = 64 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
1016
Note 2: Perform this setting when the gradation display mode is selected.
FLD data pointer (address 0EF816
FLDDP 0 0 0 0 1 1 1 1
)
Set {(digit number) – 1} = 15
FLDC mode register (address 0EF416
FLDM 1 0 1 0 0 0 1 1
)
Display start
38B5 Group User’s Manual
2-115
APPLICATION
2.4 FLD controller
Setting of FLD automatic display RAM:
Table 2.4.6 FLD automatic display RAM map
Corresponding
digit pin of
M35501FP
1 to 16 timing display data stored area
Gradation display control data stored area
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FLD
7
FLD
6
FLD
5
FLD
4
FLD
3
FLD
2
FLD
1
FLD
0
FLD FLD FLD FLD FLD FLD FLD FLD0
7
6
5
4
3
2
1
0FB016
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
0FEA16
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FF016
0FF116
0F6016
0F6116
0F6216
0F6316
0F6416
0F6516
0F6616
0F6716
0F6816
0F6916
0F6A16
0F6B16
0F6C16
0F6D16
0F6E16
0F6F16
0F7016
0F7116
0F7216
0F7316
0F7416
0F7516
0F7616
0F7716
0F7816
0F7916
0F7A16
0F7B16
0F7C16
0F7D16
0F7E16
0F7F16
0F8016
0F8116
0F8216
0F8316
0F8416
0F8516
0F8616
0F8716
0F8816
0F8916
0F8A16
0F8B16
0F8C16
0F8D16
0F8E16
0F8F16
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
DIG15
DIG14
DIG13
DIG12
DIG11
DIG10
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
9
8
7
6
5
4
3
2
1
0
FLD15FLD14FLD13FLD12FLD11FLD10 FLD
9
FLD
8
FLD15
FLD14FLD13FLD12FLD11FLD10 FLD
9 FLD8
DIG15
DIG14
DIG13
DIG12
DIG11
DIG10
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
9
8
7
6
5
4
3
2
1
0
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
FLD23FLD22FLD21FLD20FLD19FLD18FLD17FLD16
DIG15
DIG14
DIG13
DIG12
DIG11
DIG10
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
9
8
7
6
5
4
3
2
1
0
FLD31FLD30FLD29FLD28FLD27FLD26FLD25FLD24
0F9016 FLD31FLD30FLD29 FLD28FLD27FLD26FLD25FLD24
DIG15
DIG14
DIG13
DIG12
DIG11
DIG10
0F9116
0F9216
0F9316
0F9416
0F9516
0F9616
0F9716
0F9816
0F9916
0F9A16
0F9B16
0F9C16
0F9D16
0F9E16
0F9F16
0FA016
0FA116
0FA216
0FA316
0FA416
0FA516
0FA616
0FA716
0FA816
0FA916
0FAA16
0FAB16
0FAC16
0FAD16
0FAE16
0FAF16
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
9
8
7
6
5
4
3
2
1
0
FLD35FLD34FLD33FLD32
FLD35FLD34FLD33FLD32
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DIG15
DIG14
DIG13
DIG12
DIG11
DIG10
0FF2
0FF31166
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
0FFA16
0FFB16
0FFC16
0FFD16
0FFE16
0FFF16
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
9
8
7
6
5
4
3
2
1
0
: CLK signal set area to M35501FP
: Unused
38B5 Group User’s Manual
2-116
APPLICATION
2.4 FLD controller
DIG
0
DIG
1
DIG
2
DIG
3
DIG
4
DIG
5
DIG
6
DIG
7
DIG
8
DIG9 DIG10 DIG11
FLD26
FLD27
FLD28
19
FLD
0
5
FLD
1
6
FLD
2
7
FLD
3
FLD
4
9
FLD20 FLD22 FLD
FLD24
FLD21 FLD23 FLD
FLD25
18
FLD
FLD
FLD
FLD8
FLD
FLD16
FLD17
FLD12 FLD14
FLD13 FLD15
FLD10 FLD11FLD12FLD13FLD14
FLD15 FLD16FLD17FLD18FLD19
FLD10
FLD11
FLD2
FLD6
FLD3 FLD7
DISC
TRACK
REC
SLEEP
DATE
CLOCK
FLD8
FLD9
FLD4
FLD5
FLD29
Y
h
M
D
FLD20 FLD21FLD22 FLD23FLD24
FLD25 FLD26FLD27FLD28FLD29
FLD
0
FLD
1
1
2
3
4
5
6
7
8
9
m
s
FLD30 FLD31FLD32FLD33 FLD34
FLD35
REC
FLD35
FLD30
FLD31 FLD32
FLD33 FLD34
10 11 12 13 14 15 16 17 18
19 20 21 22 23 24 25 26 27
28 29 30 31 32 33 34 35 36
DIG13
DIG14
REC
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
DIG12
DIG15
10 11 12 13 14 15 16 17 18
9
15 16 17
10 11 12 13 14
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
19 20 21 22 23 24 25 26 27
18 19 20 21 22 23 24 25 26
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
28 29 30 31 32 33 34 35 36
27 28 29 30 31 32 33 34 35
Fig. 2.4.36 FLD digit allocation example
Control procedure:
Figure 2.4.37 shows the control procedure.
RESET
Initialization
FLD port setting
P0FPR (address 0EF916
P2FPR (address 0EFA16
P8FPR (address 0EFB16
)
)
)
11111111
11111111
10001111
10100001
3216
2
2
2
2
FLDM (address 0EF416
TDISP (address 0EF516
)
)
FLD automatic display function setting
TOFF1 (address 0EF616
TOFF2 (address 0EF716
)
)
)
A16
1016 (Note 1)
FLDDP (address 0EF816
P5D (address 000B16
00001111
00000011
00000000
2
2
2
Port direction registers setting
)
RESET to M35501FP =“L
SEL = “L
”,
P5 (address 000A16
)
”
signal output set
P5 (address 000A16
)
00000001
2
RESET of M35501FP released (Note 2)
Setting of CLK data to M35501FP and
segment data (Note 3)
Data to be
display
FLD automatic display RAM
(address 0FB016–0FFF16
)
Gradation display control data setting
Set “1” for dark display
Gradation
display control
data (Note 1)
Gradation display control
RAM
(addresses 0F6016–0FAF16
Set “0” for bright display (Note 3)
)
FLD automatic display start
FLDM (address 0EF416), bit 1
1
Main processing
Notes 1: When selecting the gradation display, set these registers,
too.
2: After retaining RESET signal output “L” for 2 µs or more,
release reset while CLK signal is “L”.
3: The display data can be rewritten at arbitrary timing.
Fig. 2.4.37 Control procedure
38B5 Group User’s Manual
2-117
APPLICATION
2.4 FLD controller
(5) Display by combination with digit expander (M35501FP*) (example considering column discrepancy
prevention)
* For M35501FP, refer to section “3.12 M35501FP”.
Outline: In the case of (4), which is displayed by using the digit expander (M35501FP), if a noise
enters signals between 38B5 Group and M35501FP, a column discrepancy of display may
occur. Prevent the column discrepancy by using the OVFOUT output of M35501FP.
The OVFOUT pin of M35501FP outputs an overflow signal. The overflow signal is the
signal which outputs “H” synchronizing to the last digit output signal of M35501FP, and
the signal is output at definite intervals in the correct state. Incorrect state is detected by
measuring the output period of this signal, and a column discrepancy is prevented.
38B5 Group
M35501FP
P5
0
1
7
1
RESET
SEL
P5
CLK
P8
CNTR
OVFOUT
P20
P00
P10
P30
P80
–P2
–P0
–P1
–P3
–P8
7
7
7
7
3
OVFIN
DIG
0
–DIG15
Digit (16)
Fluorescent display (FLD)
REC
DISC
TRACK
DATE
Y
M
D
s
SLEEP
CLOCK
Segment (36)
1
2
3
4
5
6
7
8
9
h
m
10 11 12 13 14 15 16 17 18
19 20 21 22 23 24 25 26 27
28 29 30 31 32 33 34 35 36
REC
Fig. 2.4.38 Connection diagram
Specifications: •Use of M35501FP (M35501: 16 digits, 38B5 Group: 36 segments)
_____________
Ports P5
M35501FP respectively.
The P8 pin (FLD port vacant pin) supply signals to the CLK pin of M35501FP.
0
and P5 of 38B5 Group supply signal to the RESET and SEL pins of
1
7
•Use of FLD automatic display mode of 38B5 Group
•Display in gradation display mode and 16 timing mode
•Toff1 = 40 µs, Toff2 = 64 µs, Tdisp = 204 µs, f(XIN) = 4 MHz
Countermeasures against
column discrepancycolumn
discrepancy
→ •OVFOUT output of M35501FP input to CNTR
1
pin of 38B5 Group
Input signal to CNTR
4 of 38B5 Group
1
pin is counted as a count source by timer
The timer 6 interrupt is generated each time FLD display period
(Tdisp (204 µs) ✕ 16 column = 3.264 ms), and a value of timer
4 is confirmed. M35501FP is reset at incorrect state.
Figure 2.4.39 shows the timing chart (at correct state) of 38B5 Group and M35501FP, and Figure
2.4.40 shows the timing chart (at incorrect state) of 38B5 Group and M35501FP.
38B5 Group User’s Manual
2-118
APPLICATION
2.4 FLD controller
M35501FP
RESET
SEL
OVFIN
OVFOUT
CLK
DIG0
DIG1
DIG14
DIG15
38B5 Group
FLD –FLD35
0
(P2
P1
0
0
–P2
7
, P0
0
–P0
7
,
,
–P1
7, P3
0
–P3
7
P80
–P8 )
3
Fig. 2.4.39 Timing chart (at correct state) of 38B5 Group and M35501FP
M35501FP
RESET
SEL
OVFIN
Noise
OVFOUT
CLK
DIG0
DIG1
DIG14
DIG15
38B5 Group
FLD –FLD35
0
(P2
P1
0
0
–P2
7
, P0
0
–P0
7
,
,
–P1
7, P3
0
–P3
7
P80
–P8 )
3
Column discrepancy occur
Fig. 2.4.40 Timing chart (at incorrect state) of 38B5 Group and M35501FP
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APPLICATION
2.4 FLD controller
Figure 2.4.41 shows the setting of relevant registers.
P0FPR
P2FPR
1 1 1 1 1 1 1 1
Set P00–P0
7
to FLD output ports (FLD –FLD15)
8
Port P2FLD/port switch register (address 0EFA16
)
1
1 1 1 1 1 1 1
Set P20–P2
7
to FLD output ports (FLD
0
–FLD )
7
Port P8FLD/port switch register (address 0EFB16
)
1
0 0 0 1 1 1 1
P8FPR
Set P8
0
–P8
–P8
3
6
to FLD output ports (FLD32–FLD35
to general-purpose I/O ports
)
Set P8
4
Set P8
7
to FLD output port (FLD39
)
Port P5 direction register (address 000B16
)
P5D
1
1
Set P5
0
1
to general-purpose output port (for M35501 RESET signal)
to general-purpose output port (for M35501 SEL signal)
Set P5
Port P5 (address 000A16
)
P5
0 0
M35501 RESET signal output (Note 1)
M35501 SEL signal “L” output
Note 1: After retain RESET signal output “L” for 2 µs or more, release reset by
outputting “H” level from RESET signal output at CLK signal = “L” .
FLDC mode register (address 0EF416
)
FLDM
1
0
1 0
0 0 0 1
Automatic display mode
Display stopped
Tscan = 0 FLD digit interrupt
16 timing mode
Gradation display mode selected
Tdisp counter count source : f(XIN)/16
High-breakdown voltage port drivability weak
Tdisp time set register (address 0EF516
)
50 (3216) set; (50 + 1) ✕ count source = 204 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
TDISP
TOFF1
TOFF2
3216
Toff1 time set register (address 0EF616
)
10 (A16) set; 10 ✕ count source = 40 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
0A16
Toff2 time set register (address 0EF716) (Note 2)
16 (1016) set; 16 ✕ count source = 64 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
1016
Note 2: Perform this setting when the gradation display mode is selected.
Fig. 2.4.41 Setting of relevant registers
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APPLICATION
2.4 FLD controller
FLD data pointer (address 0EF816
)
FLDDP
0 0 0 0 1 1 1 1
Set {(digit number) – 1} = 15
Interrupt edge selection register (address 003A16
)
0
INTEDGE
T34M
CNTR
1
pin rising edge active
)
Timer 34 mode register (address 002916
0
1
0
1
Timer 4 count stop, count start at FLD display started
Timer 4 count source: External count input CNTR
1
Timer 4 (address 002316
)
Check value of T4 each time timer 6 interrupt occurrence
When the value is FE16, it is judged as correct state
T4
FF16
Timer 56 mode register (address 002A16
)
T56M
0 0 0 1 0 0 1 1
Timer 5 count stop, count start at FLD display started
Timer 6 count stop, count start at FLD display started
Timer 5 count source: f(XIN)/8
Timer 6: Timer mode
Timer 6 count source: Timer 5 underflow
P44 I/O port
Timer 5 (address 002416
)
)
T5
T6
0716
Timer 6 interrupt occurs at 3.264 ms intervals
Timer 6 (address 002516
CB16
Interrupt request register 2 (address 003D16
0
)
IREQ2
Clear timer 6 interrupt request
Interrupt control register 2 (address 003F16
)
ICON2
FLDM
0
1
Timer 6 interrupt enabled
FLDC mode register (address 0EF416
)
1
0 1 0 0 0 1 1
Display start
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APPLICATION
2.4 FLD controller
Control procedure:
Figure 2.4.42 shows the control procedure.
●X: This bit is not used for this application.
RESET
Set “0” or “1” to this bit arbitrarily.
Initialization
P0FPR (address 0EF916)
P2FPR (address 0EFA16)
P8FPR (address 0EFB16)
FLDM (address 0EF416)
TDISP (address 0EF516)
TOFF1 (address 0EF616)
TOFF2 (address 0EF716)
FLDDP (address 0EF816)
P5D (address 000B16)
P5 (address 000A16)
111111112
111111112
1XXX11112
101000012
3216
FLD port setting
FLD automatic display function setting
A16
1016 (Note 1)
XXXX11112
XXXXXX112
XXXXXX002
0X10XX1X2
0
Port direction register setting
RESET to M35501FP = “L”, SEL =“L” signal output setting
Timer 4 setting
T34M (address 002916)
INTEDGE (address 003A16), bit 7
T4 (address 002316)
FF16
T56M (address 002A16)
T5 (address 002416)
T6 (address 002516)
000100112
716
CB16
Timer 5, timer 6 setting
P5 (address 000A16)
XXXXXX012
RESET of M35501FP released (Note 2)
Setting of CLK data to M35501FP and
segment data (Note 3)
FLD automatic display RAM
(addresses 0FB016–0FFF16)
Data to be
display
Setting of gradation display control data
Set “1” for dark display
Gradation
display control
data (Note 1)
Gradation display control
RAM
(addresses 0F6016–0FAF16)
Set “0” for bright display (Note 3)
Timer 6 interrupt enabled
0
1
0
002
1
IREQ2 (address 003D16), bit 2
ICON2 (address 003F16), bit 2
T34M (address 002916), bit 0
T56M (address 002A16), bit 0, 1
FLDM (address 0EF416), bit 1
Timer 4, timer 5, timer 6 count start (Note 4)
FLD automatic display start (Note 4)
Main processing
Fig. 2.4.42 Control procedure
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APPLICATION
2.4 FLD controller
Interrupt occurs each time FLD display cycle = 3.264 ms
Timer 6 interrupt routine
Push registers to stack, etc.
Correct
data (FE16)
Check of OVFOUT output number during FLD display cycle
Only 1 time (=FE16) is correct.
Check timer 4 data ?
Incorrect data (except FE16)
Error processing
FLDM (address 0EF416), bit 1
FLD turned off
0
Transfer present display contents to work RAM
Display data is retained as backup.
Setting of RESET to M35501FP = “L”,
SEL = “L” signal output
P5 (address 000A16)
P5 (address 000A16)
XXXXXX002
XXXXXX012
Releasing RESET of M35501FP (Note 2)
Setting of CLK data to M35501FP
Setting of segment data by display data
of backup
FLD automatic display RAM
(addresses 0FB016–0FFF16)
Data to be
display
(Note 5)
Setting of gradation display control data
Set “1” for dark display
Gradation
display control
data (Note 1)
Gradation display control
RAM
(addresses 0F6016–0FAF16)
Set “0” for bright display
Timer 5, timer 6 count start (Note 4)
FLD turned on, automatic display start (Note 4)
002
1
T56M (address 002A16), bit 0, 1
FLDM (address 0EF416), bit 1
Setting of timer 4 again
T4 (address 002316)
Pop registers
FF16
Notes 1: When selecting the gradation display, set these registers,
too.
2: After retaining RESET signal output “L” for 2 µs or more,
release reset while CLK signal is “L”.
RTI
3: The display data can be rewritten at arbitrary timing.
4: Synchronize count start timing of timer 5 and timer 6 with
FLD automatic display start timing as possible.
5: Set segment data of M35501FP at reset and others
according to necessity.
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APPLICATION
2.4 FLD controller
2.4.4 Notes on use
● Set a value of 0316 or more to the Toff1 time set register.
● When displaying in the gradation display mode, select the 16 timing mode by the timing number control
bit (bit 4 of FLDC mode register (address 0EF416) = “0”).
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APPLICATION
2.5 A-D converter
2.5 A-D converter
This paragraph describes the setting method of A-D converter relevant registers, notes etc.
2.5.1 Memory assignment
Address
003216
003316
A-D control register (ADCON)
A-D conversion register (low-order) (ADL)
003416 A-D conversion register (high-order) (ADH)
003D16
003F16
Interrupt request register 2 (IREQ2)
Interrupt control register 2 (ICON2)
Fig. 2.5.1 Memory assignment of A-D converter relevant registers
2.5.2 Relevant registers
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register
(ADCON: address 3216
)
b
0
Name
Analog input pin
selection bits
Functions
At reset R W
0
b3 b2 b1 b0
0 0 0 0: P7
0 0 0 1: P7
0 0 1 0: P7
0 0 1 1: P7
0 1 0 0: P7
0 1 0 1: P7
0 1 1 0: P7
0 1 1 1: P7
0
1
2
3
4
5
6
7
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
1
0
0
2
3
4
1 0 0 0: P6
2
/SRDY1/AN
8
3
/AN
9
0
1
/INT
4/SBUSY1/AN10
1 0 1 1: P65/SSTB1/AN11
0: Conversion in progress
1: Conversion completed
AD conversion
completion bit
0
0
0
5
6
7
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
Fig. 2.5.2 Structure of A-D control register
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APPLICATION
2.5 A-D converter
A-D conversion register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (low-order)
(ADL: address 3316)
b
Functions
At reset R W
Undefined
Nothing is arranged for these bits. These are write
disabled bits. When these bits are read out, the
contents are “0”.
0
1
2
3
4
5
6
7
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
These are A-D conversion result (low-order 2 bits)
stored bits. This is read exclusive register.
Undefined
Note: Do not read this register during A-D conversion.
Fig. 2.5.3 Structure of A-D conversion register (low-order)
A-D conversion register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (high-order)
(ADH: address 3416)
b
Functions
At reset R W
Undefined
0
1
2
3
4
5
6
7
This is A-D conversion result (high-order 8 bits) stored
bits. This is read exclusive register.
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Note: Do not read this register during A-D conversion.
Fig. 2.5.4 Structure of A-D conversion register (high-order)
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APPLICATION
2.5 A-D converter
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16)
b
0
Name
Functions
0 : No interrupt request issued
1 : Interrupt request issued
At reset R W
Timer 4 interrupt
request bit (Note)
Timer 5 interrupt
request bit
Timer 6 interrupt
request bit
Serial I/O2 receive
interrupt request bit
INT3/Serial I/O2
transmit interrupt
request bit (Note)
✽
✽
✽
✽
✽
0
0
0
0
0
0 : No interrupt request issued
1 : Interrupt request issued
1
2
3
4
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
✽
✽
0 : No interrupt request issued
1 : Interrupt request issued
0
0
0
INT4 interrupt
request bit
A-D converter
interrupt request bit
FLD blanking
interrupt request bit
FLD digit interrupt
request bit
5
6
7
0 : No interrupt request issued
1 : Interrupt request issued
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
✽: “0” can be set by software, but “1” cannot be set.
Note: In the mask option type P, if timer 4 interrupt whose count source is
CNTR1 input and INT3 interrupt are selected, these bits do not
become “1”.
Fig. 2.5.5 Structure of interrupt request register 2
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APPLICATION
2.5 A-D converter
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2
(ICON2 : address 3F16)
b
0
Name
Functions
At reset R W
0
Timer 4 interrupt
enable bit (Note)
Timer 5 interrupt
enable bit
Timer 6 interrupt
enable bit
Serial I/O2 receive
interrupt enable bit
INT3/Serial I/O2
transmit interrupt
enable bit (Note)
0 : interrupt disabled
1 : Interrupt enabled
0
0
0
0
1
2
3
4
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0
0
0
INT4 interrupt
enable bit
5
6
7
0 : interrupt disabled
1 : Interrupt enabled
A-D converter
interrupt enable bit
FLD blanking
interrupt enable bit
FLD digit interrupt
enable bit
0 : interrupt disabled
1 : Interrupt enabled
Fix “0” to this bit.
Note: In the mask option type P, timer 4 interrupt whose count source
is CNTR1 input and INT3 interrupt are not available.
Fig. 2.5.6 Structure of interrupt control register 2
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APPLICATION
2.5 A-D converter
2.5.3 A-D converter application examples
(1) Read-in of analog signal
Outline: The analog input voltage input from a sensor is converted to digital values.
Figure 2.5.7 shows a connection diagram, and Figure 2.5.8 shows the setting of relevant registers.
P70/AN0
Sensor
38B5 Group
Fig. 2.5.7 Connection diagram
Specifications: •Conversion of analog input voltage input from sensor to digital values
•Use of P7 /AN pin as analog input pin
0
0
A-D control register (address 003216)
0 0 0 0 0
ADCON
Analog input pin : P70/AN0 selected
A-D conversion start
A-D conversion register (high-order) (address 003416)
(Read-only)
ADH
ADL
A result of A-D conversion is stored (Note).
A-D conversion register (low-order) (address 003316)
(Read-only)
A result of A-D conversion is stored (Note).
Note: After bit 4 of ADCON is set to “1”, read out both registers in order of ADH (address
003416) and ADL (address 003316) following.
Fig. 2.5.8 Setting of relevant registers
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APPLICATION
2.5 A-D converter
Control procedure: A-D converter is started by performing register setting shown Figure 2.5.8.
Figure 2.5.9 shows the control procedure.
• P70/AN0 pin selected as analog input pin
• A-D conversion start
← 0000
← 0
2
ADCON (address 003216), bit 0–bit 3
ADCON (address 003216), bit 4
0
• Judgment of A-D conversion completion
ADCON (address 003216), bit 4 ?
1
Read out ADH (address 003416
)
• Read out of high-order (b9–b2) conversion result
• Read out of low-order (b1, b0) conversion result
Read out ADL (address 003316
)
Fig. 2.5.9 Control procedure
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APPLICATION
2.5 A-D converter
2.5.4 Notes on use
(1) Analog input pin
■ Make the signal source impedance for analog input low, or equip an analog input pin with an
external capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application
products on the user side.
● Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A-D conversion precision to be worse.
■ When the P6
4
/INT
4
/SBUSY1/AN10 pin is selected as analog input pin, external interrupt function (INT )
4
becomes invalid.
(2) A-D converter power source pin
The AVSS pin is A-D converter power source pin. Regardless of using the A-D conversion function
or not, connect it as following :
• AVSS : Connect to the VSS line
● Reason
If the AVSS pin is opened, the microcomputer may have a failure because of noise or others.
(3) Clock frequency during A-D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A-D conversion.
• f(XIN) is 250 kHz or more
• Use clock divided by main clock (f(XIN)) as internal system clock.
• Do not execute the STP instruction and WIT instruction
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APPLICATION
2.6 PWM
2.6 PWM
This paragraph describes the setting method of PWM relevant registers, notes etc.
2.6.1 Memory assignment
Address
001416
001516
PWM register (high-order) (PWMH)
PWM register (low-order) (PWML)
002616
PWM control register (PWMCON)
Fig. 2.6.1 Memory assignment of PWM relevant registers
2.6.2 Relevant registers
PWM register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
PWM register (high-order)
(PWMH: address 1416)
b
0
1
2
3
4
5
6
7
Functions
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
• High-order 8 bits of PWM0 output data is set.
• The values set in this register is transferred to
the PWM latch each sub-period cycle (64 µs).
(At f(XIN) = 4 MHz)
• When this register is read out, the value of the
PWM register (high-order) is read out.
Fig. 2.6.2 Structure of PWM register (high-order)
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APPLICATION
2.6 PWM
PWM register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
PWM register (low-order)
(PWML: address 1516)
b
Functions
At reset R W
Undefined
• Low-order 6 bits of PWM0 output data is set.
• The values set in this register is transferred to
the PWM latch at each PWM cycle period
(4096 µs).
(At f(XIN) = 4 MHz)
• When this register is read out, the value of the
PWM latch (low-order 6 bits) is read out.
0
1
2
3
4
5
6
Undefined
Undefined
Undefined
Undefined
Undefined
Nothing is arranged for this bit. This bit is a
write disabled bit. When this bit is read out, the
contents are “0”.
Undefined
✕
✕
• This bit indicates whether the transfer to the
PWM latch is completed.
Undefined
7
0: Transfer is completed
1: Transfer is not completed
• This bit is set to “1” at writing.
Fig. 2.6.3 Structure of PWM register (low-order)
PWM control register
b7 b6 b5 b4 b3 b2 b1 b0
PWM control register
(PWMCON: address 2616)
Name
b
0
Functions
At reset R W
P87/PWM output
selection bit
0: I/O port
1: PWM output
0
1 Nothing is arranged for these bits. These are
0
0
0
0
0
0
0
write disabled bits. When these bits are read out,
2
3
4
5
6
7
the contents are “0”.
Fig. 2.6.4 Structure of PWM control register
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APPLICATION
2.6 PWM
2.6.3 PWM application example
(1) Control of VS tuner
Figure 2.6.5 shows a connection diagram, and Figure 2.6.6 shows the setting of relevant registers.
VS tuner
ANT
VT
Filter
P87/PWM0/FLD39
38B5 Group
0–32 V
Fig. 2.6.5 Connection diagram
Outline: • Control of VS tuner by using the 14-bit resolution PWM output function
0
• f(XIN) = 4 MHz
PWM control register (address 002616
)
PWMCON
1
Select PWM output
Note: The PWM output function has priority even when the
bit corresponded to the P8 pin of the port P8 direction
register is set to the input mode.
7
PWM register (high-order) (address 001416
)
PWMH
Set high-order 8 bits (N) of a 14-bit data to be output
Note: Depending on data (N) of the high-order 8 bits, the period (250
✕ N) of the “H” level during the sub period (64 µs) is
determined.
PWM register (low-order) (address 001516
)
PWML
Set low-order 6 bits (m) of a 14-bit data to be output
Note: Depending on data (m) of the low-order 6 bits, the number of
sub period to which the ADD bit is to be added within the
repetitive cycle consisting of 64 sub periods is determined.
When output data is written to the PWM register (low-order),
bit 7 of this register becomes “1”. When completing to transfer
data from the PWM register (low-order) to the PWM latch, bit 7
becomes “0”.
Fig. 2.6.6 Setting of relevant registers
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APPLICATION
2.6 PWM
Control procedure: PWM waveform is output to the external by setting relevant registers shown
Figure 2.6.6. This PWM output is integrated through the low pass filter and
0
converted into DC signals for control of the VS tuner.
Figure 2.6.7 shows the control procedure.
The P87/PWM0/FLD39 pin is set to the PWM
output pin.
1
PWMCON (address 002616), bit 0
After setting data, PWM waveform
corresponding to the new data is output from
the next repetitive cycle.
Data to be
output
PWMH (address 001416)
PWML (address 001516)
Fig. 2.6.7 Control procedure
2.6.4 Notes on use
● For PWM output, “L” level is output first.
0
● After data is set to the PWM register (low-order) and the PWM register (high-order), PWM waveform
corresponding to new data is output from next repetitive cycle.
PWM0 output data
change
Modified data is output from next
repetitive cycle.
Fig. 2.6.8 PWM output
0
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APPLICATION
2.7 Interrupt interval determination function
2.7 Interrupt interval determination function
This paragraph describes the setting method of interrupt interval determination function relevant registers,
notes etc.
2.7.1 Memory assignment
Address
003016
Interrupt interval determination register (IID)
003116 Interrupt interval determination control register (IIDCON)
003A16
003C16
003E16
Interrupt edge selection register (INTEDGE)
Interrupt request register 1 (IREQ1)
Interrupt control register 1 (ICON1)
Fig. 2.7.1 Memory assignment of interrupt interval determination function relevant registers
2.7.2 Relevant registers
Interrupt interval determination register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt interval determination register
(IID: address 3016)
b
Functions
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
• This register stores a value which is obtained
by counting a following interval with the
counter sampling clock.
Rising interval
Falling interval
Both edges interval (Note)
(Selected by interrupt edge selection register)
• Read exclusive register
0
1
2
3
4
5
6
7
Note: When the noise filter sampling clock selection bits (bits 2, 3) of
the interrupt interval determination control register is “00”, the
both-sided edge detection function cannot be used.
Fig. 2.7.2 Structure of interrupt interval determination register
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APPLICATION
2.7 Interrupt interval determination function
Interrupt interval determination control register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt interval determination control register
(IIDCON: address 3116)
b
0
Name
Functions
At reset R W
0
Interrupt interval
determination circuit 1: Operating
0: Stopped
operating selection
bit
0
0
0
0
Counter sampling
clock selection bit
Noise filter
sampling clock
selection bits (INT2)
0: f(XIN)/128
1: f(XIN)/256
1
2
3
4
b3 b2
0 0: Filter is not used.
0 1: f(XIN)/32
1 0: f(XIN)/64
1 1: f(XIN)/128
0: One-sided edge
detection
One-sided/both-
sided edge
detection selection
bit
1: Both-sided edge
detection (Note)
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
5
6
7
0
0
0
Note: When the noise filter sampling clock selection bits (bits 2, 3) is
“00”, the both-sided edge detection function cannot be used.
Fig. 2.7.3 Structure of interrupt interval determination control register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register
(INTEDGE : address 3A16)
b
0
Name
INT0 interrupt edge
selection bit
Functions
At reset R W
0
0 : Falling edge active
1 : Rising edge active
INT1 interrupt edge
selection bit
INT2 interrupt edge
selection bit
INT3 interrupt edge
selection bit (Note) 1 : Rising edge active
0
0
0
0
0
1
2
3
4
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
INT4 interrupt edge
selection bit
0 : Falling edge active
1 : Rising edge active
5 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
CNTR0 pin edge
switch bit
CNTR1 pin edge
switch bit (Note)
0
0
0 : Rising edge count
1 : Falling edge count
6
0 : Rising edge count
1 : Falling edge count
7
Note: In the mask option type P, these bits are not available because
CNTR1 function and INT3 function cannot be used.
Fig. 2.7.4 Structure of interrupt edge selection register
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APPLICATION
2.7 Interrupt interval determination function
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16)
b
0
Name
INT0 interrupt
request bit
Functions
At reset R W
✽
✽
✽
0
0
0
0 : No interrupt request
issued
1 : Interrupt request issued
INT1 interrupt
request bit
1
0 : No interrupt request
issued
1 : Interrupt request issued
2 INT2 interrupt
request bit
0 : No interrupt request
issued
Remote controller
/counter overflow
interrupt request bit
1 : Interrupt request issued
✽
0
3
0 : No interrupt request
issued
1 : Interrupt request issued
Serial I/O1 interrupt
request bit
Serial I/O automatic
transfer interrupt
request bit
Timer X interrupt
4
✽
✽
✽
✽
0
0
0
0
0 : No interrupt request
issued
1 : Interrupt request issued
request bit
Timer 1 interrupt
request bit
5
6
7
0 : No interrupt request
issued
1 : Interrupt request issued
Timer 2 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
Timer 3 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.7.5 Structure of interrupt request register 1
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APPLICATION
2.7 Interrupt interval determination function
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 3E16)
b
0
Name
Functions
At reset R W
0
INT0 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
1 INT1 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
2 INT2 interrupt
enable bit
Remote controller
/counter overflow
interrupt enable bit
0
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O1 interrupt
enable bit
3
Serial I/O automatic
transfer interrupt
enable bit
Timer X interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
4
5
6
7
Timer 1 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Timer 2 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
Timer 3 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 2.7.6 Structure of interrupt control register 1
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APPLICATION
2.7 Interrupt interval determination function
2.7.3 Interrupt interval determination function application examples
(1) Reception of remote-control signal
Outline: Remote-control signal is read in by both of the interrupt interval determination function using
a noise filter and a timer interrupt.
Receiver
P47/INT2
unit
Remote controller
38B5 Group
Fig. 2.7.7 Connection diagram
Specifications: • Measurement of one-sided edge interval
• Use of noise filter
• Check of remote control interrupt request within the timer 2 interrupt (488 µs
period) processing routine
• Operation at f(XIN) = 4 MHz in high-speed mode
Figure 2.7.8 shows the function block diagram, and Figure 2.7.9 shows a timing chart of data
determination.
Microcomputer hardware
Microcomputer software
Interrupt interval
determination
register
Determination
of header or
0/1
Receiver
unit
Data
check
1-byte
reception
Noise filter
• Noise elimination
• One-sided edge
detection
• One-sided edge
interval
judgment
• Read out register
• Comparison of
read out value with
reference value
• Recognition bit
number of each
code
Fig. 2.7.8 Function block diagram
Input (INT2)
(Overflow)
Interrupt request
Timer 2 interrupt
(488 µs)
Interrupt interval
determination
register read-in
Data determination
Ignore
Header
0
1
• • •
1
Ignore Ignore
Check of excess bit
1-byte reception
Fig. 2.7.9 Timing chart of data determination
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APPLICATION
2.7 Interrupt interval determination function
Figure 2.7.10 shows the setting of relevant registers.
CPU mode register (address 003B16
0
)
CPUM
INTEDGE
IIDCON
High-speed (f(XIN)) mode operation (Note)
Interrupt edge selection register (address 003A16
)
0
INT
2
pin: Falling edge active
Interrupt interval determination control register (address 003116
)
1 1
0
1 0
Interrupt interval determination circuit: Operating
Counter sampling clock: f(XIN)/256
Noise filter sampling clock: f(XIN)/64
One-sided edge detection
Interrupt request register 1 (address 003C16
)
IREQ1
ICON1
IID
Determination of remote controller/counter overflow interrupt request bit
Interrupt control register 1 (address 003E16
)
0
Remote controller/counter overflow interrupt: Disabled
Interrupt interval determination register (address 003016
)
Determination of header/data (0/1) with this value
Note: The interrupt interval determination
function cannot be used in the low-
speed mode.
Fig. 2.7.10 Setting of relevant registers
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APPLICATION
2.7 Interrupt interval determination function
Control procedure: When the registers are set as shown Figure 2.7.10, remote-control signals are
receivable. Figure 2.7.11 shows the control procedure, and Figure 2.7.12 shows
the reception of remote-control data (timer 2 interrupt).
●X: This bit is not used here. Set it to “0” or “1”
RESET
arbitrarily.
Initialization
SEI
CPUM (address 003B16), bit 6
0
INTEDGE (address 003A16), bit 2
IIDCON (address 003116)
IREQ1 (address 003C16)
NOP
0
XXX101112
0
ICON1 (address 003E16)
0
CLI
Fig. 2.7.11 Control procedure
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APPLICATION
2.7 Interrupt interval determination function
Timer 2 interrupt
Push registers to stack etc.
Input edge ?
(IREQ1, bit 2 = ?)
N
Y
N
N
During checking excess
bit ?
Clear edge (IREQ1, bit 2 = 0)
Y
Excess bit
determined counter
Y
Y
During checking
excess bit ?
over ?
Y
Number of bits error
(Excess bit is found)
N
Read IID (address 003016
)
Fixed data
RTI
RTI
IID (address 003016
)
= FF16
?
Time error
RTI
N
Y
In range of header ?
N
Start receiving data etc.
RTI
In range of 0
Out of range of 0 or 1
In range of data, 0 or 1 ?
In range of 1
CY ← 1
Time error
RTI
CY ← 0
Shift reception data
N
Complete to
receive ?
Y
Start checking excess bit
RTI
Fig. 2.7.12 Reception of remote-control data (timer 2 interrupt)
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APPLICATION
2.8 Watchdog timer
2.8 Watchdog timer
The watchdog timer is a 20-bit down-count counter consisting of a low-order 8 bits and a high-order 12 bits.
“1” is subtracted from the watchdog timer each time a count source inputs.
This paragraph describes the setting method of watchdog timer relevant register, notes etc.
2.8.1 Memory assignment
Address
002B16
Watchdog timer contort register (WDTCON)
Fig. 2.8.1 Memory assignment of watchdog timer relevant register
2.8.2 Relevant register
The watchdog timer starts counting by writing an arbitrary value to the watchdog timer control register.
Figure 2.8.2 shows the structure of the watchdog timer control register.
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Watchdog timer control register
(WDTCON: address 2B16)
b
Name
Functions
At reset R W
0
1
2
3
4
5
6
1
1
1
1
1
1
0
Watchdog timer H
(high-order 6 bits of reading exclusive)
STP instruction
disable bit
0: STP instruction enabled
1: STP instruction disabled
7
0
Watchdog timer H
count source
0: Watchdog timer L
underflow
selection bit
1: f(XIN)/16 or f(XCIN)/16
Fig. 2.8.2 Structure of watchdog timer control register
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APPLICATION
2.8 Watchdog timer
2.8.3 Watchdog timer application examples
Outline: When a program runs away, the watchdog timer makes the microcomputer return to the
reset state.
Specifications: •When the watchdog timer H underflows, it is judged as incorrect program, and the
microcomputer is returned to the reset state.
•Bit 7 of the watchdog timer control register is set to “0” at 1-cycle intervals in the
main routine before underflow of the watchdog timer H. (Initialization of watchdog
timer value)
•Use of watchdog timer L underflow as count source of watchdog timer H
•Setting of main clock division ratio to f(XIN) (high-speed mode)
Figure 2.8.3 shows the connection of watchdog timer and the setting of the division ratio.
Figure 2.8.4 shows the setting of relevant registers.
Watchdog timer H
1/4096
Watchdog timer L
1/256
Fixed
1/8
Reset
circuit
f(XIN) = 4 MHz
Internal reset
RESET
STP instruction disable bit
STP instruction
Fig. 2.8.3 Connection of watchdog timer and setting of division ratio
CPU mode register (address 003B16)
CPUM
0 0 0
0 0
Single-chip mode
Main clock (XIN-XOUT): Oscillating
High-speed (f(XIN)) mode operation
Internal system clock: XIN-XOUT
Watchdog timer control register (address 002B16)
0 0
WDTCON
STP instruction: Enabled
Watchdog timer H count source:
Underflow of watchdog timer L
Fig. 2.8.4 Setting of relevant registers
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APPLICATION
2.8 Watchdog timer
Figure 2.8.5 shows the control procedure.
RESET
●X: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SEI
CLT
CLD
CPU mode register setting
(single-chip mode, main clock oscillating, high-speed mode)
CPUM (address 003B16)
CLI
000XXX002
Count of watchdog timer start
(STP instruction enabled, WDTH count source)
WDTCON (address 002B16)
Main processing
00XXXXXX2
Fig. 2.8.5 Control procedure
2.8.4 Notes on use
● The watchdog timer continues to count even while waiting for stop release. Accordingly, make sure that
watchdog timer does not underflow during this term by writing to the watchdog timer control register
(address 002B16) once before executing the STP instruction, etc.
● Once a “1” is written to the STP instruction disable bit (bit 6) of the watchdog timer control register
(address 002B16), it cannot be programmed to “0” again. This bit becomes “0” after reset.
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APPLICATION
2.9 Buzzer output circuit
2.9 Buzzer output circuit
The output frequency can be selected from 1 kHz, 2 kHz, or 4 kHz (at f(XIN) = 4.19 MHz), and the output
port can be selected between either the BUZ01 pin or the BUZ02 pin.
This paragraph describes the setting method of buzzer output circuit relevant register, notes etc.
2.9.1 Memory assignment
Address
0EFD16
Buzzer output control register (BUZCON)
Fig. 2.9.1 Memory assignment of buzzer output circuit relevant register
2.9.2 Relevant register
The buzzer output circuit starts outputting a buzzer by setting the buzzer output ON/OFF bit (bit 4) of the
buzzer output control register.
Figure 2.9.2 shows the structure of the buzzer output control register.
Buzzer output control register
b7 b6 b5 b4 b3 b2 b1 b0
Buzzer output control register
(BUZCON: address 0EFD16)
b
0
Name
Output frequency
selection bits
Functions
At reset R W
0
b1b0
0 0: 1 kHz (f(XIN)/4096)
0 1: 2 kHz (f(XIN)/2048)
1 0: 4 kHz (f(XIN)/1024)
1 1: Not available
b3b2
0
0
1
2
Output port
selection bits
0 0: P20 and P43 function
as ordinary ports.
0 1: P43/BUZ01 functions as
a buzzer output.
0
0
3
4
1 0: P20/BUZ02/FLD0
functions as a buzzer
output.
1 1: Not available
Buzzer output
ON/OFF bit
0: Buzzer output OFF (“0”
output)
1: Buzzer output ON
5
6
7
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
0
0
0
Fig. 2.9.2 Structure of buzzer output control register
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APPLICATION
2.9 Buzzer output circuit
2.9.3 Buzzer output circuit application examples
Outline: A buzzer output is performed by using the buzzer output circuit.
Specifications: •f(XIN) = 4.19 MHz, buzzer output frequency = 4 kHz
•Buzzer output from BUZ01 pin
Figure 2.9.3 shows the connection of buzzer output circuit and the setting of the division ratio.
Figure 2.9.4 shows the setting of relevant register. Figure 2.9.5 shows the control procedure.
Port latch
f(XIN) = 4.19 MHz
1/1024
Buzzer output
(4 kHz)
Buzzer output ON/OFF bit
Output port control signal
Port direction register
Fig. 2.9.3 Connection of buzzer output circuit and setting of division ratio
Buzzer output control register (address 0EFD16)
BUZCON
0 0 1 1 0
Output frequency: 4 kHz (f(XIN)/1024)
P43/Buz01: Buzzer output
Buzzer output: OFF
Fig. 2.9.4 Setting of relevant register
●X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
SEI
CLT
CLD
Buzzer output control register setting
(output frequency = 4 kHz, Buz01 output,
buzzer output OFF)
BUZCON (address 0EFD16
CLI
)
XXX001102
Buzzer output ON
1
BUZCON (address 0EFD16), bit 4
Fig. 2.9.5 Control procedure
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APPLICATION
2.10 Reset circuit
2.10 Reset circuit
____________
The reset state is caused by applying an “L” level to the RESET pin. After that, the reset state is released
____________
by applying an “H” level to the RESET pin, so that the program is executed in the middle-speed mode from
the contents of the reset vector address.
2.10.1 Connection example of reset IC
Figure 2.10.1 shows the example of power-on reset circuit. Figure 2.10.2 shows the system example which
switches to the RAM backup mode by detecting a drop of the system power source voltage with the INT
interrupt.
VCC
Power source
Output
M62022L
GND
RESET
Delay capacity
0.1µF
VSS
38B5 Group
Fig. 2.10.1 Example of power-on reset circuit
System power
source voltage
VCC
+
5V
VCC1
RESET
RESET
INT
Cd
INT
VCC2
VSS
V1
GND
38B5 Group
M62009L, M62009P, M62009FP
Fig. 2.10.2 RAM backup system example
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APPLICATION
2.10 Reset circuit
2.10.2 Notes on use
(1) Reset input voltage control
Make sure that the reset input voltage is 0.5 V or less for Vcc of 2.7 V.
Perform switch to the high-speed mode when power source voltage is within 4.0 to 5.5 V.
(2) Countermeasure when RESET signal rise time is long
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the VSS pin. And use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
● Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
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APPLICATION
2.11 Clock generating circuit
2.11 Clock generating circuit
2.11.1 Relevant register
Figure 2.11.1 shows the structure of the CPU mode register.
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register
(CPUM, CM: address 3B16)
b
0
Name
Functions
At reset R W
0
b1 b0
Processor mode
bits
00 : Single-chip mode
01 :
0
0
1
0
1
2
3
4
10 :
11 :
0 : Page 0
1 : Page 1
Not available
Stack page
selection bit
XCOUT drivability
selection bit
Port Xc switch bit
0: Low drive
1: High drive
0: I/O port function
1: XCIN-XCOUT oscillation
function
Main clock (XIN-
XOUT) stop bit
0: Oscillating
1: Stopped
0
1
5
6
Main clock division
ratio selection bit
0: f(XIN) (high-speed mode)
1: f(XIN)/4 (middle-speed
mode)
0: XIN–XOUT selection
(middle-/high-speed
mode)
0
7
Internal system
clock selection bit
1: XCIN–XCOUT selection
(low-speed mode)
Fig. 2.11.1 Structure of CPU mode register
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APPLICATION
2.11 Clock generating circuit
2.11.2 Clock generating circuit application examples
(1) Status transition during power failure
Outline: The clock is counted up every one second by using the timer interrupt during a power
failure.
Input port
Power failure detection signal
(Note)
38B5 Group
Note: Signal is detected by inputting to each input port,
interrupt input pin, and analog input pin.
Fig. 2.11.2 Connection diagram
Specifications: •Reducing power dissipation as low as possible while maintaining clock function
•Clock: f(XIN) = 4.19 MHz, f(XCIN) = 32.768 kHz
•Port processing
Input port: Fixed to “H” or “L” level on the external
Output port: Fixed to output level that does not cause current flow to the external
(Example) When a circuit turns on LED at “L” output level, fix the
output level to “H”.
I/O port: Input port → Fixed to “H” or “L” level on the external
Output port → Output of data that does not consume current
V
REF: Stop to supply to reference voltage input pin by external circuit
Figure 2.11.3 shows the status transition diagram during power failure and Figure 2.11.4 shows the
setting of relevant registers.
Reset released
Power failure detected
X
IN
X
CIN
Internal
system clock
Middle-speed
mode
High-speed mode
Low-speed mode
After detecting, change internal system clock to
low-speed mode and stop oscillating XIN-XOUT
Change internal system
clock to high-speed
mode
X
CIN-XCOUT oscillation function selected
Fig. 2.11.3 Status transition diagram during power failure
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APPLICATION
2.11 Clock generating circuit
CPU mode register (address 003B16
)
CPUM
0 0 0 0
0 0
Main clock: High-speed mode (f(XIN)) (Note 1)
CPU mode register (address 003B16
)
CPUM
CPUM
0 0 0 1
0 0
(Note 2)
Port X : XCIN-XCOUT oscillation function
C
CPU mode register (address 003B16
)
1 0 0 1
0 0
(Note 2)
Internal system clock: Low-speed mode (f(XCIN))
CPU mode register (address 003B16
)
CPUM
1 0 1 1
(Note 2)
0 0
Main clock f(XIN): Stopped
Notes 1: This setting is necessary only when selecting the high-
speed mode.
2: When selecting the middle-speed mode, bit 6 is “1”.
Fig. 2.11.4 Setting of relevant registers
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APPLICATION
2.11 Clock generating circuit
Control procedure: Set the relevant registers in the order shown below to prepare for a power
failure.
●X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
CPUM (address 003B16), bit 6
CPUM (address 003B16), bit 4
0
1
When selecting main clock f(XIN) (high-speed mode)
Port XC: XCIN-XCOUT oscillation function
N
Detect power failure ?
≈
Y
Internal system clock: f(XCIN) (low-speed mode)
Main clock f(XIN) oscillation stopped
1 (Note)
1 (Note)
CPUM (address 003B16), bit 7
CPUM (address 003B16), bit 5
Set so that timer interrupt occurs every one
second
Execute WIT instruction
At a power failure, clock count is performed during
timer interrupt processing (every second).
N
Return condition from power failure
concluded ?
Y
Return processing from power failure
Note: Do not switch at one time.
≈
Fig. 2.11.5 Control procedure
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APPLICATION
2.11 Clock generating circuit
(2) Counting without clock error during power failure
Outline: It keeps counting without clock error during a power failure.
Specifications: •Reducing power consumption as low as possible while maintaining clock function
•Clock: f(XIN) = 4.19 MHz
•Sub clock: f(XCIN) = 32.768 kHz
•Use of Timer 3 interrupt
For the peripheral circuit and the status transition during a power failure, refer to “Figures 2.11.2
and 2.11.3”.
Figure 2.11.6 shows the structure of clock counter, Figures 2.11.7 and 2.11.8 show the setting of
relevant registers.
Timer 1 interrupt
Timer 3 interrupt
1 minute counter
Timer 1
1/64
Base counter
244 µs
1 second counter
1/16
1 second
f(XIN) = 4.19 MHz
1/16
1/256
1/60
Minute/Time/Day/
Month/Year
When the system returns from a
power failure, add the time taken
for the switching processing for the
return.
Timer 1
1/8
Timer 2
1/256
Timer 3
1/16
<At power failure>
244 µs
f(XCIN) = 32.768 kHz
: Software timer
: Hardware timer
Fig. 2.11.6 Structure of clock counter
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APPLICATION
2.11 Clock generating circuit
CPU mode register (address 003B16
)
CPUM
CPUM
0
0
0
1
0 0
Port XC: XCIN-XCOUT oscillation function
CPU mode register (address 003B16
0 0
)
1
1
0 0
Internal system clock: f(XIN) (high-speed mode)
Timer 1 (address 002016
3F16
)
Set (Division ratio -1); 63 (3F16
)
T1
Timer 12 mode register (address 002816
)
T12M
0
0
0 0
1 0 0 0
Timer 1 count: Operating
Timer 2 count: Operating
Timer 1 count source: f(XIN)/16
Timer 2 count source: Timer 1 underflow
P45 I/O port
Timer 34 mode register (address 002916
)
T34M
0
0
0
1
0
Timer 3 count: Operating
Timer 3 count source: Timer 2 underflow
P46 I/O port
Interrupt request register 1 (address 003C16
)
IREQ1
0
0
Set “0” to timer 1 interrupt request bit
Set “0” to timer 3 interrupt request bit
Interrupt control register 1 (address 003E16
)
ICON1
1
Timer 1 interrupt: Enabled
Fig. 2.11.7 Initial setting of relevant registers
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APPLICATION
2.11 Clock generating circuit
Timer 12 mode register (address 002816
)
T12M
CPUM
CPUM
ICON1
0
1
Timer 1 count source: f(XCIN
)
CPU mode register (address 003B16
)
1
0
0
1
0 0
Internal system clock: f(XCIN) (low-speed mode)
CPU mode register (address 003B16
0 1
)
1
1
0 0
Main clock f(XIN): Stopped
Interrupt control register 1 (address 003E16
)
1
0
Timer 1 interrupt: Disabled
Timer 3 interrupt: Enabled
Timer 1 (address 002016
0716
)
)
)
T1
T2
T3
Timer 2 (address 002116
FF16
Set (Division ratio – 1)
(T1 = 7 (0716), T2 = 255 (FF16), T3 = 15 (0F16))
Timer 3 (address 002216
0F16
Fig. 2.11.8 Setting of relevant registers after detecting power failure
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APPLICATION
2.11 Clock generating circuit
Control procedure: Set the relevant registers in the order shown below to prepare for a power
failure.
●X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
Port XC: XCIN-XCOUT oscillation function
CPUM (address 003B16), bit 4
CPUM (address 003B16), bit 6
1
0
When selecting main clock f(XIN) (high-speed mode)
Setting for making base and one second counters activate during
timer 1 interrupt
In the normal power state, these software counters generate one
second.
T1 (address 002016
)
3F16
000010002
00XX01X0
0,0
FF16
0F16
1
T12M (address 002816
T34M (address 002916
)
)
2
IREQ1 (address 003C16), bit 7, bit 5
Base counter (internal RAM)
1 second counter (internal RAM)
ICON1 (address 003E16), bit 5
N
Detect power failure ?
Y
≈
T12M (address 002816), bit 3, bit 2
ICON1 (address 003E16), bit 5
CPUM (address 003B16), bit 7
CPUM (address 003B16), bit 5
IREQ1 (address 003C16), bit 7, bit 5
0, 1
0
1 (Note)
1 (Note)
0, 0
0716
3F16
0F16
Timer 1 count source: f(XCIN
)
Timer 1 interrupt: Disabled
Internal system clock: f(XCIN) (low-speed mode)
Main clock f(XIN): Oscillation stopped
Setting for generating timer 3 interrupt every second
Generation of one second by hardware timer during
power failure
T1 (address 002016
T2 (address 002116
T3 (address 002216
)
)
)
Timer 3 interrupt: Enabled
1
ICON1 (address 003E16), bit 7
Execute WIT instruction
Timer 3 interrupt occurs every second
(return from wait mode)
N
Return condition for power failure is
satisfied ?
Y
Return processing from power failure
Note: Do not switch at one time.
≈
Fig. 2.11.9 Control procedure
38B5 Group User’s Manual
2-158
APPLICATION
2.11 Clock generating circuit
Timer 3 interrupt routine
Push registers to stack etc.
Count 1 minute (internal RAM) counter
1 minute counter overflow ?
N
Y
Modify time, day, month, year
≈
RTI
38B5 Group User’s Manual
2-159
APPLICATION
2.11 Clock generating circuit
MEMORANDUM
38B5 Group User’s Manual
2-160
CHAPTER 3
APPENDIX
3.1 Electrical characteristics
3.2 Standard characteristics
3.3 Notes on use
3.4 Countermeasures against noise
3.5 Control registers
3.6 Mask ROM confirmation form
3.7 ROM programming confirmation form
3.8 Mark specification form
3.9 Package outline
3.10 List of instruction code
3.11 Machine instructions
3.12 M35501FP
3.13 SFR memory map
3.14 Pin configuration
APPENDIX
3.1 Electrical characteristics
3.1 Electrical characteristics
3.1.1 Absolute maximum ratings
Table 3.1.1 Absolute maximum ratings
Parameter
Unit
V
Symbol
Conditions
Ratings
–0.3 to 7.0
VCC
Power source voltage
Pull-down power source voltage
VEE
VI
VCC – 45 to VCC +0.3
–0.3 to VCC +0.3
V
V
Input voltage
P47, P50–P57, P61–P65, P70–
P77, P84–P87, P90, P91
VI
VI
VI
VI
VO
–0.3 to 13
V
V
V
V
V
Input voltage
Input voltage
Input voltage
Input voltage
Output voltage
P40–P46, P60
VCC – 45 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VCC +0.3
VCC – 45 to VCC +0.3
P00–P07, P20–P27, P80–P83
RESET, XIN
All voltages are
based on VSS.
Output transistors
are cut off.
XCIN
P00–P07, P10–P17, P20–P27,
P30–P37, P80–P83
VO
Output voltage
P50–P57, P61–P65, P70–P77,
P84–P87, P90, P91, XOUT,
XCOUT
–0.3 to VCC +0.3
V
VO
Pd
–0.3 to 13
800
V
Output voltage
P40–P46, P60
mW
mW
°C
Power dissipation
Ta = –20 to 65 °C
Ta = 65 to 85 °C
800 – 12.5 ✕ (Ta – 65)
–20 to 85
Topr
Tstg
Operating temperature
Storage temperature
–40 to 125
°C
38B5 Group User’s Manual
3-2
APPENDIX
3.1 Electrical characteristics
3.1.2 Recommended operating conditions
Table 3.1.2 Recommended operating conditions (1)
(Vcc = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Min.
4.0
Typ.
5.0
5.0
0
Max.
5.5
VCC
Power source voltage
In high-speed mode
V
V
V
V
V
V
V
V
In middle-/low-speed mode
2.7
5.5
VSS
VEE
VREF
AVSS
VIA
Power source voltage
Pull-down power source voltage
VCC–43
2.0
VCC
VCC
Analog reference voltage (when A-D converter is used)
Analog power source voltage
0
Analog input voltage
“H” input voltage
AN0–AN11
0
VCC
VCC
VIH
P40–P47, P50–P57, P60–P65, P70–P77,
P90, P91
0.75VCC
VIH
VIH
VIH
VIH
VIH
VIL
“H” input voltage
“H” input voltage
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
P84–P87
0.4VCC
0.8VCC
0.52VCC
0.8VCC
0.8VCC
0
VCC
VCC
V
V
V
V
V
V
P00–P07
P20–P27, P80–P83
RESET
VCC
VCC
XIN, XCIN
VCC
P40–P47, P50–P57, P60–P65, P70–P77,
P90, P91
0.25VCC
VIL
“L” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
P84–P87
0
0
0
0
0.16VCC
0.2VCC
0.2VCC
0.2VCC
–240
V
V
VIL
P00–P07, P20–P27, P80–P83
RESET
VIL
V
VIL
XIN, XCIN
V
ΣIOH(peak)
H” total peak output current (Note 1)
mA
P00–P07, P10–P17, P20–P27, P30–P37, P80–P83
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
“H” total peak output current (Note 1)
P50–P57, P61–P65, P70–P77, P90, P91
–60
100
60
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
“L” total peak output current (Note 1)
P50–P57, P60–P65, P70–P77, P90, P91
“L” total peak output current (Note 1)
P40–P46, P84–P87
“H” total average output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37, P80–P87
–120
–30
50
“H” total average output current (Note 1)
P50–P57, P61–P65, P70–P77, P90, P91
“L” total average output current (Note 1)
P50–P57, P60–P65, P70–P77, P90, P91
“L” total average output current (Note 1)
P40–P46, P84–P87
30
“H” peak output current (Note 2)
P00–P07, P10–P17, P20–P27, P30–P37, P80–P83
–40
–10
10
“H” peak output current (Note 2)
P50–P57, P61–P65, P70–P77, P84–P87, P90, P91
“L” peak output current (Note 2)
P50–P57, P61–P65, P70–P77, P84–P87, P90, P91
“L” peak output current (Note 2)
P40–P46, P60
30
“H” average output current (Note 3)
P00–P07, P10–P17, P20–P27, P30–P37, P80–P83
–18
–5
IOH(avg)
“H” average output current (Note 3)
P50–P57, P60–P65, P70–P77, P84–P87, P90, P91
IOL(avg)
“L” average output current (Note 3)
P50–P57, P61–P65, P70–P77, P84–P87, P90, P91
5
IOL(avg)
“L” average output current (Note 3)
15
P40–P46, P60
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an
average value measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current IOL (avg), IOH(avg) in an average value measured over 100 ms.
38B5 Group User’s Manual
3-3
APPENDIX
3.1 Electrical characteristics
Table 3.1.3 Recommended operating conditions (2)
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
kHz
Min.
Max.
250
f(CNTR0)
f(CNTR1)
Clock input frequency for timers 2, 4, and X (duty cycle 50 %)
f(XIN)
Main clock input oscillation frequency (Note 1)
Sub-clock input oscillation frequency (Notes 1, 2)
4.2
50
MHz
kHz
f(XCIN)
32.768
Notes 1: When the oscillation frequency has a duty cycle of 50%.
2: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
3.1.3 Electrical characteristics
Table 3.1.4 Electrical characteristics (1)
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
IOH = –18 mA
Unit
V
Min.
Typ.
Max.
VOH
VCC–2.0
“H” output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P80–P83
IOH = –10 mA
IOL = 10 mA
VCC–2.0
V
V
VOH
VOL
“H” output voltage P50–P57, P60–P65, P70–P77,
P84–P87, P90, P91
2.0
2.0
“L” output voltage P50–P57, P61–P65, P84–P87,
P90, P91
V
V
VOL
“L” output voltage P40–P46, P60
IOL = 15 mA
0.6
0.4
VT+–VT–
Hysteresis
P40–P42, P45–P47, P5, P60,
P61, P64 (Note 1)
V
V
VT+–VT–
VT+–VT–
IIH
Hysteresis
Hysteresis
RESET, XIN
XCIN
0.5
0.5
µA
VI = VCC
“H” input current P47, P50–P57, P61–P65,
P70–P77, P84–P87
5.0
µA
µA
µA
µA
µA
µA
IIH
IIH
IIH
IIH
IIL
IIL
VI = 12 V
VI = VCC
VI = VCC
VI = VCC
VI = VSS
“H” input current P40–P46, P60
10.0
5.0
“H” input current P00–P07, P20–P27, P80–P83 (Note 2)
“H” input current RESET, XCIN
“H” input current XIN
5.0
4.0
“L” input current P40–P47, P60
–5.0
–5.0
VI = VSS
Pull-up “off”
“L” input current P50–P57, P61–P65, P70–P77,
P84–P87, P90, P91
–30
–70
–25
–140
–45
µA
µA
VCC = 5 V, VI = VSS
Pull-up “on”
–6.0
VCC = 3 V, VI = VSS
Pull-up “on”
–5.0
–5.0
µA
µA
µA
µA
IIL
VI = VSS
VI = VSS
VI = VSS
“L” input current P0
“L” input current RESET, XCIN
“L” input current XIN
0–P07, P20–P27, P80–P83 (Note 2)
IIL
IIL
–4.0
600
900
–10
ILOAD
VEE = VCC–43 V,
VOL =VCC
Output transistors “off”
300
Output load current P00–P07, P10–P17, P30–P37
µA
ILEAK
VEE = VCC–43 V,
VOL =VCC–43 V
Output leak current P00–P07, P10–P17, P20–P27,
P30–P37, P80–P83
Output transistors “off”
µA
IREADH
VRAM
VI = 5 V
“H” read current P00–P07, P20–P27, P80–P83
1
V
When clock is stopped
2
5.5
Notes 1: P42, P45, P46, and P60 of the mask option type P do not have hysteresis characteristics.
2: Except when reading ports P0, P2, or P8.
38B5 Group User’s Manual
3-4
APPENDIX
3.1 Electrical characteristics
Table 3.1.5 Electrical characteristics (2)
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Test conditions
Min.
Typ.
7.5
Max.
15
ICC
Power source current
High-speed mode
f(XIN) = 4.2 MHz
f(XCIN) = 32 kHz
mA
mA
mA
Output transistors “off”
High-speed mode
1
3
f(XIN) = 4.2 MHz (in WIT state)
f(XCIN) = 32 kHz
Output transistors “off”
Middle-speed mode
f(XIN) = 4.2 MHz
f(XCIN) = stopped
Output transistors “off”
Middle-speed mode
f(XIN) = 4.2 MHz (in WIT state)
f(XCIN) = stopped
1
mA
Output transistors “off”
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32 kHz
Low-power dissipation mode (CM3 = 0)
Output transistors “off”
60
200
40
µA
Low-speed mode
20
µA
f(XIN) = stopped
f(XCIN) = 32 kHz (in WIT state)
Low-power dissipation mode (CM3 = 0)
Output transistors “off”
Increment when A-D conversion is executed
0.6
0.1
mA
µA
µA
All oscillation stopped (in STP state) Ta = 25 °C
1
Output transistors “off”
Ta = 85 °C
10
3.1.4 A-D converter characteristics
Table 3.1.6 A-D converter characteristics
(VCC = 4.0 to 5.5V, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 250 kHz to 4.2 MHz in high-speed mode, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
10
—
—
Bits
LSB
tc(φ)
µA
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
VCC = VREF = 5.12 V
VREF = 5.0 V
±1
±2.5
62
TCONV
61
50
IVREF
IIA
Reference input current
Analog port input current
Ladder resistor
150
0.5
35
200
5.0
µA
RLADDER
kΩ
38B5 Group User’s Manual
3-5
APPENDIX
3.1 Electrical characteristics
3.1.5 Timing requirements and switching characteristics
Table 3.1.7 Timing requirements
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
2.0
238
60
Max.
____________
tW(RESET)
tC(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time (XCIN input)
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “H” pulse width
INT0 to INT4 input “L” pulse width
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input set up time
tWH(XIN)
tWL(XIN)
60
tC(XCIN)
20
tWH(XCIN)
tWL(XCIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
5.0
5.0
4.0
1.6
1.6
80
tWL(INT)
80
tC(SCLK)
0.95
400
400
200
200
tWH(SCLK)
tWL(SCLK)
tsu(SCLK–SIN)
th(SCLK–SIN)
Serial I/O input hold time
Table 3.1.8 Switching characteristics
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
tWH(SCLK)
Parameter
Test conditions
Unit
Min.
Typ.
Max.
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
CL = 100 pF
CL = 100 pF
tC(SCLK)/2–160
tC(SCLK)/2–160
ns
ns
ns
ns
ns
ns
ns
tWL(SCLK)
td(SCLK–SOUT)
tv(SCLK–SOUT)
tr(SCLK)
0.2 tc
Serial I/O output valid time
0
Serial I/O clock output rising time
Serial I/O clock output falling time
CL = 100 pF
CL = 100 pF
40
40
tf(SCLK)
tr(Pch–strg)
P-channel high-breakdown voltage
CL = 100 pF
55
output rising time (Note 1)
VEE = VCC–43 V
1.8
µs
tr(Pch–weak)
P-channel high-breakdown voltage
CL = 100 pF
output rising time (Note 2)
VEE = VCC–43 V
Notes 1: When bit 7 of the FLDC mode register (address 0EF416) is at “0”.
2: When bit 7 of the FLDC mode register (address 0EF416) is at “1”.
P0,P1,P2,
P3,P80–P8
3
P5
P5
P5
2
3
6
/SCLK11
/SCLK12
/SCLK21
/SCLK22
,
,
,
High-breakdown
P-channel open-
drain output port
Serial I/O clock
output port
P5
7
CL
CL
(Note)
V
EE
Note: Ports P2 and P8 need external resistors.
Fig. 3.1.1 Circuit for measuring output switching characteristics
38B5 Group User’s Manual
3-6
APPENDIX
3.1 Electrical characteristics
Timing Diagram
tC(CNTR)
tWL(CNTR)
t
WH(CNTR)
CNTR0,CNTR1
0.8VCC
0.2VCC
0.2VCC
t
WL(INT)
t
WH(INT)
INT0–INT
4
0.8VCC
t
W(RESET)
0.8VCC
RESET
0.2VCC
tC(XIN)
tWL(XIN)
t
WH(XIN)
0.8VCC
XIN
0.2VCC
t
C(XCIN)
tWL(XCIN)
t
WH(XCIN)
0.8VCC
XCIN
0.2VCC
t
C(SCLK)
t
f(SCLK
)
tr
t
WL(SCLK
)
tWH(SCLK)
0.8VCC
S
CLK
IN
0.2VCC
t
su(SIN-SCLK
)
th(SCLK-SIN)
0.8VCC
0.2VCC
S
t
d(SCLK-SOUT
)
tv(SCLK-SOUT)
S
OUT
Fig. 3.1.2 Timing diagram
38B5 Group User’s Manual
3-7
APPENDIX
3.2 Standard characteristics
3.2 Standard characteristics
3.2.1 Power source current standard characteristics
At 5.5 V
9
8
Power source current
(mA)
7
6
5
4
3
2
1
At 4.0 V
4.2
0
0
1
2
3
4
5
6
Frequency f(XIN) (MHz)
Fig. 3.2.1 Power source current standard characteristics
At 5.5 V
Power source current
1000
900
800
700
600
500
400
300
200
100
(µA)
At 4.0 V
4.2
0
0
1
2
3
4
5
6
Frequency f(XIN) (MHz)
Fig. 3.2.2 Power source current standard characteristics (in wait mode)
38B5 Group User's Manual
3-8
APPENDIX
3.2 Standard characteristics
3.2.2 Port standard characteristics
Port P30 IOH-VOH characteristics (25 °C)
(Same characteristics pins: P0, P1, P2, P3, P8
0–P83)
I
OH
(mA)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
V
CC = 5.5 V
V
CC = 5.0 V
V
CC = 3.0 V
0
0
1.200
2.400
3.600
4.800
6.000
VOH (V)
Fig. 3.2.3 High-breakdown P-channel open-drain output port characteristics (25 °C)
Port P30 IOH–VOH characteristics (90 °C)
(Same characteristics pins: P0, P1, P2, P3, P80–P83)
IOH
(mA)
-100
VCC = 5.5 V
-90
-80
VCC = 5.0 V
-70
-60
-50
VCC = 3.0 V
-40
-30
-20
-10
0
0
1.200
2.400
3.600
4.800
6.000
VOH (V)
Fig. 3.2.4 High-breakdown P-channel open-drain output port characteristics (90 °C)
38B5 Group User's Manual
3-9
APPENDIX
3.2 Standard characteristics
Port P8
7
I
OH-VOH characteristics (25 °C)
–P65, P7, P84–P87, P9)
(Same characteristics pins: P5, P6
1
I
OH
(mA)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
V
CC = 5.5 V
V
CC = 5.0 V
V
CC = 3.0 V
0
0
1.200
2.400
3.600
4.800
6.000
VOH (V)
Fig. 3.2.5 CMOS output port P-channel side characteristics (25 °C)
Port P8
7
I
OH–VOH characteristics (90 °C)
–P65, P7, P84–P87, P9)
(Same characteristics pins: P5, P6
1
I
OH
(mA)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
VCC =5.5 V
V
CC =5.0 V
V
CC =3.0 V
0
0
1.200
2.400
3.600
4.800
6.000
VOH (V)
Fig. 3.2.6 CMOS output port P-channel side characteristics (90 °C)
38B5 Group User's Manual
3-10
APPENDIX
3.2 Standard characteristics
Port P8
7
I
OL–VOL characteristics (25 °C)
–P6
(Same characteristics pins: P5, P6
1
5
, P7, P8
4
–P8
7
, P9)
I
OL
(mA)
100
90
80
70
60
50
40
30
20
10
V
CC = 5.5 V
V
CC = 5.0 V
V
CC = 3.0 V
0
0
1.200
2.400
3.600
4.800
6.000
VOL (V)
Fig. 3.2.7 CMOS output port N-channel side characteristics (25 °C)
Port P8
7
I
OL–VOL characteristics (90 °C)
–P65, P7, P84–P87, P9)
(Same characteristics pins: P5, P6
1
IOL
(mA)
100
90
80
70
60
50
40
30
20
10
V
CC = 5.5 V
V
CC = 5.0 V
V
CC = 3.0 V
3.600
0
0
1.200
2.400
4.800
6.000
V
OL (V)
Fig. 3.2.8 CMOS output port N-channel side characteristics (90 °C)
38B5 Group User's Manual
3-11
APPENDIX
3.2 Standard characteristics
Port P4
0
I
OL-VOL characteristics (25 °C)
–P4 , P60)
(Same characteristics pins: P4
0
6
I
OL
(mA)
100
90
80
70
60
50
40
30
20
10
V
CC = 5.5 V
VCC = 5.0 V
V
CC = 3.0 V
0
0
1.200
2.400
3.600
4.800
6.000
OL (V)
V
Fig. 3.2.9 N-channel open-drain output port characteristics (25 °C)
Port P4
0
, IOL-VOL characteristics (90 °C)
–P4 , P60)
(Same characteristics pins: P4
0
6
I
OL
(mA)
100
90
80
70
60
50
40
30
20
10
V
CC =5.5 V
VCC =5.0 V
V
CC =3.0 V
0
0
1.200
2.400
3.600
4.800
6.000
OL (V)
V
Fig. 3.2.10 N-channel open-drain output port characteristics (90 °C)
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APPENDIX
3.2 Standard characteristics
3.2.3 A-D conversion standard characteristics
Figure 3.2.11 shows the A-D conversion standard characteristics.
The lower line on the graph indicates the absolute precision error. It expresses the deviation from the ideal
value. For example, the conversion of output code from 0016 to 0116 occurs ideally at the point of AN
0
=
2.5 mV, but the measured value is –2 mV. Accordingly, the measured point of conversion is defined as “2.5
– 2 = 0.5 mV”.
The upper line on the graph indicates the width of input voltages equivalent to output codes. For example,
the measured width of the input voltage for output code 6016 is 6 mV, so that the differential nonlinear error
is defined as “6 – 5 = 1 mV (0.2 LSB)”.
38B5 GROUP A-D CONVERTER ERROR & STEP WIDTH MEASUREMENT
VCC = 5.12 [V], VREF = 5.12 [V], AN0
XIN = 4 [MHz], Temp = 25 [deg.]
1 LSB WIDTH
15
10
5
15.0
10.0
5.0
0
0.0
-5
-10
-15
0
16
272
528
784
32
48
64
80
96
112
368
624
880
128
STEP No.
144
160
416
672
928
176
432
688
944
192
448
704
960
208
464
720
976
224
480
736
992
240
256
ERROR (Absolute precision error)
15
10
5
15.0
10.0
5.0
0
0.0
-5
-10
-15
256
288
544
800
304
560
816
320
576
832
336
592
848
352
606
864
384
STEP No.
400
496
512
15
15.0
10.0
5.0
10
5
0
0.0
-5
-10
-15
512
640
STEP No.
656
752
768
15
10
5
15.0
10.0
5.0
0
0.0
-5
-10
-15
768
896
912
1008
1024
STEP No.
Fig. 3.2.11 A-D conversion standard characteristics
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APPENDIX
3.3 Notes on use
3.3 Notes on use
3.3.1 Notes on interrupts
(1) Switching external interrupt detection edge
For the products able to switch the external interrupt detection edge, switch it as the following
sequence.
Clear an interrupt enable bit to “0” (interrupt disabled)
↓
Switch the detection edge
↓
Clear an interrupt request bit to “0”
(no interrupt request issued)
↓
Set the interrupt enable bit to “1” (interrupt enabled)
Fig. 3.3.1 Sequence of switch detection edge
■ Reason
The interrupt circuit recognizes the switching of the detection edge as the change of external input
signals. This may cause an unnecessary interrupt.
(2) Check of interrupt request bit
● When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request
register immediately after this bit is set to “0” by using a data transfer instruction, execute one or
more instructions before executing the BBC or BBS instruction.
■ Reason
If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt
request register is cleared to “0”, the value of the interrupt request bit before being cleared to “0”
is read.
Clear the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Data transfer instruction:
LDM, LDA, STA, STX, and STY instructions
Fig. 3.3.2 Sequence of check of interrupt request bit
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APPENDIX
3.3 Notes on use
(3) Structure of interrupt control register 2
Fix the bit 7 of the interrupt control register 2
to “0”. Figure 3.3.3 shows the structure of the
interrupt control register 2.
b7
b0
Interrupt control register
Address 003F16
0
Interrupt enable bits
Not used
Fix this bit to “0”.
Fig. 3.3.3 Structure of interrupt control register 2
3.3.2 Notes on serial I/O1
(1) Clock
■ Using internal clock
After setting the synchronous clock to an internal clock, clear the serial I/O interrupt request bit
before perform the normal serial I/O transfer or the serial I/O automatic transfer.
■ Using external clock
After inputting “H” level to the external clock input pin, clear the serial I/O interrupt request bit
before performing the normal serial I/O transfer or the serial I/O automatic transfer.
(2) Using serial I/O1 interrupt
Clear bit 3 of the interrupt request register 1 to “0” by software.
(3) State of SOUT1 pin
The SOUT1 pin control bit of the serial I/O1 control register 2 can be used to select the state of the
S
OUT1 pin when serial data is not transferred; either output active or high-impedance. However, when
selecting an external synchronous clock; the SOUT1 pin can become the high-impedance state by
setting the SOUT1 pin control bit to “1” when the serial I/O1 clock input is at “H” after transfer completion.
(4) Serial I/O initialization bit
● Set “0” to the serial I/O initialization bit of the serial I/O1 control register 1 when terminating a
serial transfer during transferring.
● When writing “1” to the serial I/O initialization bit, the serial I/O1 is enabled, but each register is
not initialized. Set the value of each register by program.
(5) Handshake signal
■ SBUSY1 input signal
Input an “H” level to the SBUSY1 input and an “L” level signal to the SBUSY1 input in the initial state.
When the external synchronous clock is selected, switch the input level to the SBUSY1 input and
the SBUSY1 input while the serial I/O1 clock input is in “H” state.
■ SRDY1 input•output signal
When selecting the internal synchronous clock, input an “L” level to the SRDY1 input and an “H”
level signal to the SRDY1 input in the initial state.
(6) 8-bit serial I/O mode
■ When selecting external synchronous clock
When an external synchronous clock is selected, the contents of the serial I/O1 register are being
shifted continually while the transfer clock is input to the serial I/O1 clock pin. In this case, control
the clock externally.
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APPENDIX
3.3 Notes on use
(7) In automatic transfer serial I/O mode
■ Set of automatic transfer interval
● When the SBUSY1 output is used, and the SBUSY1 output and the SSTB1 output function as signals
for each transfer data set by the SBUSY1 output•SSTB1 output function selection bit of serial I/O1
control register 2; the transfer interval is inserted before the first data is transmitted/received,
and after the last data is transmitted/received. Accordingly, regardless of the contents of the
SBUSY1 output•SSTB1 output function selection bit, this transfer interval for each 1-byte data becomes
2 cycles longer than the value set by the automatic transfer interval set bits of serial I/O1 control
register 3.
● When using the SSTB1 output, regardless of the contents of the SBUSY1 output•SSTB1 output function
selection bit, this transfer interval for each 1-byte data becomes 2 cycles longer than the value
set by the automatic transfer interval set bits of serial I/O1 control register 3.
● When using the combined output of SBUSY1 and SSTB1 as the signal for each of all transfer data
set, the transfer interval after completion of transmission/reception of the last data becomes 2
cycles longer than the value set by the automatic transfer interval set bits.
● Set the transfer interval of each 1-byte data transfer to 5 or more cycles of the internal clock
φ after the rising edge of the last bit of a 1-byte data.
● When selecting an external clock, the set of automatic transfer interval becomes invalid.
■ Set of serial I/O1 transfer counter
● Write the value decreased by 1 from the number of transfer data bytes to the serial I/O1 transfer
counter.
● When selecting an external clock, after writing a value to the serial I/O1 register/transfer counter,
wait for 5 or more cycles of internal clock φ before inputting the transfer clock to the serial I/
O1 clock pin.
■ Serial I/O initialization bit
A serial I/O1 automatic transfer interrupt request occurs when “0” is written to the serial I/O
initialization bit during an operation. Disable it with the interrupt enable bit as necessary by program.
3.3.3 Notes on serial I/O2
(1) Notes when selecting clock synchronous serial I/O
➀ Stop of transmission operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O2 enable bit is cleared to “0” (serial I/O2 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK21, SCLK22 and SRDY2 function as I/O ports, the transmission
data is not output). When data is written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O2 enable bit is set to “1” at this time,
the data during internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the receive enable bit to “0” (receive disabled), or clear the serial I/O2 enable bit
to “0” (serial I/O2 disabled).
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APPENDIX
3.3 Notes on use
➂ Stop of transmit/receive operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, simultaneously clear both the transmit enable bit and receive enable bit to “0” (transmit
and receive disabled).
(when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
● Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.
If any one of transmission and reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,
the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clearing the serial I/O2 enable bit to
“0” (serial I/O2 disabled) (refer to (1), ➀).
(2) Notes when selecting clock asynchronous serial I/O
➀ Stop of transmission operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O2 enable bit is cleared to “0” (serial I/O2 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK21, SCLK22 and SRDY2 function as I/O ports, the transmission
data is not output). When data is written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O2 enable bit is set to “1” at this time,
the data during internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the receive enable bit to “0” (receive disabled).
➂ Stop of transmit/receive operation
Only transmission operation is stopped.
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O2 enable bit is cleared to “0” (serial I/O2 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK21, SCLK22 and SRDY2 function as I/O ports, the transmission
data is not output). When data is written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O2 enable bit is set to “1” at this time,
the data during internally shifting is output to the TxD pin and an operation failure occurs.
Only receive operation is stopped.
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the receive enable bit to “0” (receive disabled).
(3) SRDY2 output of reception side
When signals are output from the SRDY2 pin on the reception side by using an external clock in the
clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY2 output enable bit, and
the transmit enable bit to “1” (transmit enabled).
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APPENDIX
3.3 Notes on use
(4) Setting serial I/O2 control register again
Set the serial I/O2 control register again after the transmission and the reception circuits are reset
by clearing both the transmit enable bit and the receive enable bit to “0.”
Clear both the transmit enable
bit (TE) and the receive enable
bit (RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O2 control register
Can be set with the
LDM instruction at
↓
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to “1”
the same time
Fig. 3.3.4 Sequence of setting serial I/O2 control register again
(5) Data transmission control with referring to transmit shift register completion flag
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks. When data transmission is controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(6) Transmission control when external clock is selected
When an external clock is used as the synchronous clock for data transmission, set the transmit
enable bit to “1” at “H” of the serial I/O2 clock input level. Also, write the transmit data to the transmit
buffer register (serial I/O shift register) at “H” of the serial I/O2 clock input level.
(7) Transmit interrupt request when transmit enable bit is set
The transmission interrupt request bit is set and the interruption request is generated even when
selecting timing that either of the following flags is set to “1” as timing where the transmission
interruption is generated.
• Transmit buffer empty flag is set to “1”
• Transmit shift register completion flag is set to “1”
Therefore, when the transmit interrupt is used, set the transmit interrupt enable bit to transmit
enabled as the following sequence.
➀ Transmit enable bit is set to “1”
➁ Transmit interrupt request bit is set to “0”
● Reason
When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift
register completion flag are set to “1”.
(8) Using TxD pin
The P5 /TxD P-channel output disable bit of UART control register is valid in both cases: using as
5
a normal I/O port and as the TxD pin. Do not supply Vcc + 0.3 V or more even when using the P5
TxD pin as an N-channel open-drain output.
5/
Additionally, in the serial I/O2, the TxD pin latches the last bit and continues to output it after
completing transmission.
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APPENDIX
3.3 Notes on use
3.3.4 Notes on FLD controller
● Set a value of 0316 or more to the Toff1 time set register.
● When displaying in the gradation display mode, select the 16 timing mode by the timing number control
bit (bit 4 of FLDC mode register (address 0EF416) = “0”).
3.3.5 Notes on A-D converter
(1) Analog input pin
■ Make the signal source impedance for analog input low, or equip an analog input pin with an
external capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application
products on the user side.
● Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A-D conversion precision to be worse.
■ When the P6
4
/INT
4
/SBUSY1/AN10 pin is selected as analog input pin, external interrupt function (INT )
4
becomes invalid.
(2) A-D converter power source pin
The AVSS pin is A-D converter power source pin. Regardless of using the A-D conversion function
or not, connect it as following :
• AVSS : Connect to the VSS line
● Reason
If the AVSS pin is opened, the microcomputer may have a failure because of noise or others.
(3) Clock frequency during A-D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A-D conversion.
• f(XIN) is 250 kHz or more
• Use clock divided by main clock (f(XIN)) as internal system clock.
• Do not execute the STP instruction and WIT instruction
3.3.6 Notes on PWM
● For PWM output, “L” level is output first.
0
● After data is set to the PWM register (low-order) and the PWM register (high-order), PWM waveform
corresponding to new data is output from next repetitive cycle.
PWM0 output data
change
Modified data is output from next
repetitive cycle.
Fig. 3.3.5 PWM output
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APPENDIX
3.3 Notes on use
3.3.7 Notes on watchdog timer
● The watchdog timer continues to count even while waiting for stop release. Accordingly, make sure that
watchdog timer does not underflow during this term by writing to the watchdog timer control register
(address 002B16) once before executing the STP instruction, etc.
● Once a “1” is written to the STP instruction disable bit (bit 6) of the watchdog timer control register
(address 002B16), it cannot be programmed to “0” again. This bit becomes “0” after reset.
3.3.8 Notes on reset circuit
(1) Reset input voltage control
Make sure that the reset input voltage is 0.5 V or less for Vcc of 2.7 V.
Perform switch to the high-speed mode when power source voltage is within 4.0 to 5.5 V.
(2) Countermeasure when RESET signal rise time is long
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the VSS pin. And use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
● Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
3.3.9 Notes on input and output pins
(1) Notes in stand-by state
In stand-by state*1 for low-power dissipation, do not make input levels of an input port and an I/O
port “undefined”, especially for I/O ports of the N-channel open-drain.
Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using built-in pull-up resistor, note on varied current values:
• When setting as an input port : Fix its input level
• When setting as an output port : Prevent current from flowing out to external
● Reason
Even when setting as an output port with its direction register, in the following state :
• P-channel......when the content of the port latch is “0”
• N-channel......when the content of the port latch is “1”
the transistor becomes the OFF state, which causes the ports to be the high-impedance state.
Note that the level becomes “undefined” depending on external circuits.
Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the
state that input levels of a input port and an I/O port are “undefined”. This may cause power
source current.
*1 stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
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APPENDIX
3.3 Notes on use
(2) N-channel open-drain port
P4 –P4 , P4 , P4 , P6 of N-channel open-drain output ports have built-in hysteresis circuit for input.
0
2
5
6
0
In standby state for low-power dissipation, do not make these pins floating state.
● Reason
When power sources for pull-up of these pins are cut off in standby state, these ports become
floating. Accordingly, a current may flow from Vcc to Vss through built-in hysteresis circuit.
(3) Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction*2, the value of the
unspecified bit may be changed.
● Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
• As for a bit which is set for an input port :
The pin state is read in the CPU, and is written to this bit after bit managing.
• As for a bit which is set for an output port :
The bit value of the port latch is read in the CPU, and is written to this bit after bit managing.
Note the following :
• Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
• As for a bit of the port latch which is set for an input port, its value may be changed even when
not specified with a bit managing instruction in case where the pin state differs from its port latch
contents.
*2 bit managing instructions : SEB, and CLB instructions
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APPENDIX
3.3 Notes on use
3.3.10 Notes on programming
(1) Processor status register
➀ Initializing of processor status register
Flags which affect program execution must be initialized after a reset.
In particular, it is essential to initialize the T and D flags because they have an important effect
on calculations.
● Reason
After a reset, the contents of the processor status register (PS) are undefined except for the I
flag which is “1”.
Reset
↓
Initializing of flags
↓
Main program
Fig. 3.3.6 Initialization of processor status register
➁ How to reference the processor status register
To reference the contents of the processor status register (PS), execute the PHP instruction once
then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its
original status.
A NOP instruction should be executed after every PLP instruction.
PLP instruction execution
(S)
↓
(S)+1
Stored PS
NOP
Fig. 3.3.7 Sequence of PLP instruction execution
Fig. 3.3.8 Stack memory contents after PHP
instruction execution
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APPENDIX
3.3 Notes on use
(2) Decimal calculations
➀ Execution of decimal calculations
The ADC and SBC are the only instructions which will yield proper decimal notation, set the
decimal mode flag (D) to “1” with the SED instruction. After executing the ADC or SBC instruction,
execute another instruction before executing the SEC, CLC, or CLD instruction.
➁ Notes on status flag in decimal mode
When decimal mode is selected, the values of three of the flags in the status register (the N, V,
and Z flags) are invalid after a ADC or SBC instruction is executed.
The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared
to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C
flag must be initialized to “0” before each calculation. To check for a borrow, the C flag must be
initialized to “1” before each calculation.
Set D flag to “1”
↓
ADC or SBC instruction
↓
NOP instruction
↓
SEC, CLC, or CLD instruction
Fig. 3.3.9 Status flag at decimal calculations
(3) JMP instruction
When using the JMP instruction in indirect addressing mode, do not specify the last address on a
page as an indirect address.
3.3.11 Programming and test of built-in PROM version
As for in the One Time PROM version (shipped in blank) and the built-in EPROM version, their built-in
PROM can be read or programmed with a general-purpose PROM programmer using a special programming
adapter.
The built-in EPROM version is available only for program development and on-chip program evaluation.
The programming test and screening for PROM of the One Time PROM version (shipped in blank) are not
performed in the assembly process and the following processes. To ensure reliability after programming,
performing programming and test according to the Figure 3.3.10 before actual use are recommended.
Programming with PROM programmer
Screening (Caution)
(Leave at 150 °C for 40 hours)
Verification with PROM programmer
Caution: The screening temperature is far higher than the
storage temperature. Never expose to 150 °C
exceeding 100 hours.
Functional check in target device
Fig. 3.3.10 Programming and testing of One Time PROM version
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APPENDIX
3.3 Notes on use
3.3.12 Notes on built-in PROM version
(1) Programming adapter
Use a special programming adapter shown in Table 3.3.1 and a general-purpose PROM programmer
when reading from or programming to the built-in PROM in the built-in PROM version.
Table 3.3.1 Programming adapter
Microcomputer
M38B59EFFP (One Time PROM version shipped in blank)
M38B59EFFS
Programming adapter
PCA4738F-80A
PCA4738L-80A
(2) Programming/reading
In PROM mode, operation is the same as that of the M5M27C101K, but programming conditions of
PROM programmer are not set automatically because there are no internal device ID codes.
Accurately set the following conditions for data programming/reading. Take care not to apply 21 V
to the VPP pin (is also used as port P4 ), or the product may be permanently damaged.
7
➀ Programming voltage: 12.5 V
➁ Setting of PROM programmer address: Refer to “Table 3.3.2”
Table 3.3.2 PROM programmer address setting
Microcomputer
M38B59EFFP
M38B59EFFS
PROM programmer start address
PROM programmer end address
Address FFFD16
Address 108016
(3) Erasing
Contents of the windowed EPROM are erased through an ultraviolet light source with the wavelength
2537 Angstrom. At least 15 W•sec/cm2 are required to erase EPROM contents.
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APPENDIX
3.3 Notes on use
3.3.13 Termination of unused pins
(1) Terminate unused pins
➀ Output ports : Open
➁ Input ports :
Connect each pin to VSS through each resistor of 1 kΩ to 10 kΩ.
As for pins whose potential affects to operation modes such as pins INT or others, select the VCC
pin or the VSS pin according to their operation mode.
➂ I/O ports :
• Set the I/O ports for the input mode and connect them to VSS through each resistor of 1 kΩ to
10 kΩ.
Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the I/
O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the
mode of the ports is switched over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source current may increase in the input
mode. With regard to an effects on the system, thoroughly perform system evaluation on the user
side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
(2) Termination remarks
➀ Input ports and I/O ports :
Do not open in the input mode.
● Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➁ and
➂ shown on the above.
➁ I/O ports :
When setting for the input mode, do not connect to VCC or VSS directly.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and VCC (or VSS).
➂ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to VCC or VSS through
a resistor.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
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APPENDIX
3.4 Countermeasures against noise
3.4 Countermeasures against noise
Countermeasures against noise are described below. The following countermeasures are effective against
noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use.
3.4.1 Shortest wiring length
The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer.
The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer.
(1) Package
Select the smallest possible package to make the total wiring length short.
● Reason
The wiring length depends on a microcomputer package. Use of a small package, for example
QFP and not DIP, makes the total wiring length short to reduce influence of noise.
DIP
SDIP
SOP
QFP
Fig. 3.4.1 Selection of packages
(2) Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin as short as possible. Especially,
connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within
20mm).
● Reason
The width of a pulse input into the RESET pin is determined by the timing necessary conditions.
If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is completely initialized. This may cause
a program runaway.
Noise
Reset
RESET
circuit
VSS
VSS
N.G.
Reset
circuit
RESET
VSS
VSS
O.K.
Fig. 3.4.2 Wiring for the RESET pin
38B5 Group User’s Manual
3-26
APPENDIX
3.4 Countermeasures against noise
(3) Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is
connected to an oscillator and the VSS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS patterns.
● Reason
If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program
failure or program runaway. Also, if a potential difference is caused by the noise between the VSS
level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in
the microcomputer.
Noise
XIN
XIN
XOUT
VSS
XOUT
VSS
O.K.
N.G.
Fig. 3.4.3 Wiring for clock I/O pins
38B5 Group User’s Manual
3-27
APPENDIX
3.4 Countermeasures against noise
(4) Wiring to VPP pin of One Time PROM version and EPROM version
Connect an approximately 5 kΩ resistor to the VPP pin the shortest possible in series. When not
connecting the resistor, make the length of wiring between the VPP pin and the VSS pin the shortest
possible.
Note: Even when a circuit which included an approximately 5 kΩ resistor is used in the Mask ROM
version, the microcomputer operates correctly.
● Reason
The VPP pin of the One Time PROM and the EPROM version is the power source input pin for
the built-in PROM. When programming in the built-in PROM, the impedance of the VPP pin is low
to allow the electric current for writing flow into the PROM. Because of this, noise can enter easily.
If noise enters the VPP pin, abnormal instruction codes or data are read from the built-in PROM,
which may cause a program runaway.
Approximately
5 kΩ
P47/VPP
RESET
Fig. 3.4.4 Wiring for the VPP pin of the One Time PROM and the EPROM version
3.4.2 Connection of bypass capacitor across VSS line and VCC line
Connect an approximately 0.1 µF bypass capacitor across the VSS line and the VCC line as follows:
• Connect a bypass capacitor across the VSS pin and the VCC pin at equal length.
• Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS line and VCC line.
• Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin.
VCC
VCC
VSS
VSS
N.G.
O.K.
Fig. 3.4.5 Bypass capacitor across the VSS line and the VCC line
38B5 Group User’s Manual
3-28
APPENDIX
3.4 Countermeasures against noise
3.4.3 Wiring to analog input pins
• Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog
input pin in series. Besides, connect the resistor to the microcomputer as close as possible.
• Connect an approximately 1000 pF capacitor across the VSS pin and the analog input pin. Besides,
connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog
input pin and the VSS pin at equal length.
● Reason
Signals which is input in an analog input pin (such as an A-D converter/comparator input pin) are
usually output signals from sensor. The sensor which detects a change of event is installed far
from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer
necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer,
which causes noise to an analog input pin.
If a capacitor between an analog input pin and the VSS pin is grounded at a position far away from
the VSS pin, noise on the GND line may enter a microcomputer through the capacitor.
Noise
(Note)
Microcomputer
Analog
input pin
Thermistor
N.G.
O.K.
VSS
Note : The resistor is used for dividing
resistance with a thermistor.
Fig. 3.4.6 Analog signal line and a resistor and a capacitor
3.4.4 Oscillator concerns
Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected
by other signals.
(1) Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a
current larger than the tolerance of current value flows.
● Reason
In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and
thermal heads or others. When a large current flows through those signal lines, strong noise
occurs because of mutual inductance.
Microcomputer
Mutual inductance
M
XIN
XOUT
Large
current
VSS
GND
Fig. 3.4.7 Wiring for a large current signal line
38B5 Group User’s Manual
3-29
APPENDIX
3.4 Countermeasures against noise
(2) Installing oscillator away from signal lines where potential levels change frequently
Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential
levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines
which are sensitive to noise.
● Reason
Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect
other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms
may be deformed, which causes a microcomputer failure or a program runaway.
N.G.
CNTR
Do not cross
XIN
XOUT
VSS
Fig. 3.4.8 Wiring of signal lines where potential levels change frequently
(3) Oscillator protection using VSS pattern
As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the
position (on the component side) where an oscillator is mounted.
Connect the VSS pattern to the microcomputer VSS pin with the shortest possible wiring. Besides,
separate this VSS pattern from other VSS patterns.
An example of VSS patterns on the
underside of a printed circuit board
Oscillator wiring
pattern example
XIN
XOUT
VSS
Separate the VSS line for oscillation from other VSS lines
Fig. 3.4.9 VSS pattern on the underside of an oscillator
38B5 Group User’s Manual
3-30
APPENDIX
3.4 Countermeasures against noise
3.4.5 Setup for I/O ports
Setup I/O ports using hardware and software as follows:
<Hardware>
• Connect a resistor of 100 Ω or more to an I/O port in series.
<Software>
• As for an input port, read data several times by a program for checking whether input levels are
equal or not.
• As for an output port, since the output data may reverse because of noise, rewrite data to its port
latch at fixed periods.
• Rewrite data to direction registers and pull-up control registers at fixed periods.
Note: When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse
may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise
pulse.
Noise
O.K.
Data bus
Noise
Direction register
N.G.
Port latch
I/O port
pins
Fig. 3.4.10 Setup for I/O ports
38B5 Group User’s Manual
3-31
APPENDIX
3.4 Countermeasures against noise
3.4.6 Providing of watchdog timer function by software
If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer
and the microcomputer can be reset to normal operation. This is equal to or more effective than program
runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer
provided by software.
In the following example, to reset a microcomputer to normal operation, the main routine detects errors of
the interrupt processing routine and the interrupt processing routine detects errors of the main routine.
This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
<The main routine>
• Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value
N in the SWDT once at each execution of the main routine. The initial value N should satisfy the
following condition:
N+1 ≥ ( Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others,
the initial value N should have a margin.
• Watches the operation of the interrupt processing routine by comparing the SWDT contents with
counts of interrupt processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and determines to branch to the program
initialization routine for recovery processing in the following case:
If the SWDT contents do not change after interrupt processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt processing.
• Determines that the main routine operates normally when the SWDT contents are reset to the
initial value N at almost fixed cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch to the program initialization
routine for recovery processing in the following case:
If the SWDT contents are not initialized to the initial value N but continued to decrement and if
they reach 0 or less.
Interrupt processing routine
Main routine
(SWDT) ← (SWDT)—1
(SWDT)← N
CLI
Interrupt processing
Main processing
>0
(SWDT)
≤0?
RTI
≠N
≤0
(SWDT)
=N?
Return
N
Interrupt processing
routine errors
Main routine
errors
Fig. 3.4.11 Watchdog timer by software
38B5 Group User’s Manual
3-32
APPENDIX
3.5 Control registers
3.5 Control registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (i = 0, 1, 2, 3, 4, 5, 7, 8)
(Pi: addresses 0016, 0216, 0416, 0616, 0816, 0A16, 0E16, 1016)
b
Name
Functions
At reset R W
0
1
2
3
4
5
6
7
Port Pi0
0
0
0
0
0
0
0
0
●In output mode
Port Pi1
Port Pi2
Port Pi3
Port Pi4
Port Pi5
Port Pi6
Port Pi7
Write •••••••• Port latch
Read •••••••• Port latch
●In input mode
Write •••••••• Port latch
Read •••••••• Value of pin
Fig. 3.5.1 Structure of port Pi
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (i = 0, 2, 4, 5, 7, 8)
(PiD: addresses 0116, 0516, 0916, 0B16, 0F16, 1116
)
b
0
Name
Port Pi direction
register
Functions
At reset R W
0
0 : Port Pi
0
0
input mode
output mode
1 : Port Pi
0 : Port Pi
1 : Port Pi
1
1
input mode
output mode
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0 : Port Pi
1 : Port Pi
2
2
input mode
output mode
0 : Port Pi
1 : Port Pi
3
3
input mode
output mode
0 : Port Pi
1 : Port Pi
4
4
input mode
output mode
0 : Port Pi
1 : Port Pi
5
5
input mode
output mode
0 : Port Pi
1 : Port Pi
6
6
input mode
output mode
0 : Port Pi
1 : Port Pi
(Note)
7
input mode
output mode
7
Note: Bit 7 of the port P4 direction register (address 0916) does not have
direction register function because P4 is input port. When writing to bit 7
of the port P4 direction register, write “0” to the bit.
7
Fig. 3.5.2 Structure of port Pi direction register
38B5 Group User’s Manual
3-33
APPENDIX
3.5 Control registers
Port P6
b7 b6 b5 b4 b3 b2 b1 b0
Port P6
(P6: address 0C16)
b
Name
Functions
At reset R W
0
1
2
3
4
5
6
7
Port P60
0
0
0
0
0
0
●In output mode
Port P61
Port P62
Port P63
Port P64
Port P65
Write •••••••• Port latch
Read •••••••• Port latch
●In input mode
Write •••••••• Port latch
Read •••••••• Value of pin
Nothing is arranged for these bits. When these
bits are read out, the contents are undefined.
0
0
✕ ✕
✕ ✕
Fig. 3.5.3 Structure of port P6
Port P6 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P6 direction register
(P6D: address 0D16)
b
0
Name
Port P6 direction
register
Functions
0 : Port P60 input mode
1 : Port P60 output mode
At reset R W
0
0 : Port P61 input mode
1 : Port P61 output mode
0
0
0
0
0
1
2
3
4
5
0 : Port P62 input mode
1 : Port P62 output mode
0 : Port P63 input mode
1 : Port P63 output mode
0 : Port P64 input mode
1 : Port P64 output mode
0 : Port P65 input mode
1 : Port P65 output mode
Nothing is arranged for these bits. When these
bits are read out, the contents are undefined.
6
7
0
0
✕ ✕
✕ ✕
Fig. 3.5.4 Structure of port P6 direction register
38B5 Group User’s Manual
3-34
APPENDIX
3.5 Control registers
Port P9
b7 b6 b5 b4 b3 b2 b1 b0
Port P9
(P9: address 1216)
b
0
Name
Port P90
Functions
●In output mode
Write •••••••• Port latch
Read •••••••• Port latch
●In input mode
Write •••••••• Port latch
Read •••••••• Value of pin
At reset R W
0
1
Port P91
0
0
0
0
0
0
0
✕ ✕
✕ ✕
✕ ✕
✕ ✕
✕ ✕
✕ ✕
2
3
4
5
6
7
Nothing is arranged for these bits. When these
bits are read out, the contents are undefined.
Fig. 3.5.5 Structure of port P9
Port P9 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P9 direction register
(P9D: address 1316)
b
0
Name
Port P9 direction
register
Functions
0 : Port P90 input mode
1 : Port P90 output mode
At reset R W
0
0 : Port P91 input mode
1 : Port P91 output mode
0
1
Nothing is arranged for these bits. When these
bits are read out, the contents are undefined.
0
0
2
3
4
5
6
7
✕ ✕
✕ ✕
0
✕ ✕
✕ ✕
✕ ✕
✕ ✕
0
0
0
Fig. 3.5.6 Structure of port P9 direction register
38B5 Group User’s Manual
3-35
APPENDIX
3.5 Control registers
PWM register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
PWM register (high-order)
(PWMH: address 1416)
b
0
1
2
3
4
5
6
7
Functions
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
• High-order 8 bits of PWM0 output data is set.
• The values set in this register is transferred to
the PWM latch each sub-period cycle (64 µs).
(At f(XIN) = 4 MHz)
• When this register is read out, the value of the
PWM register (high-order) is read out.
Fig. 3.5.7 Structure of PWM register (high-order)
PWM register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
PWM register (low-order)
(PWML: address 1516)
b
Functions
At reset R W
Undefined
• Low-order 6 bits of PWM0 output data is set.
• The values set in this register is transferred to
the PWM latch at each PWM cycle period
(4096 µs).
(At f(XIN) = 4 MHz)
• When this register is read out, the value of the
PWM latch (low-order 6 bits) is read out.
0
1
2
3
4
5
6
Undefined
Undefined
Undefined
Undefined
Undefined
Nothing is arranged for this bit. This bit is a
write disabled bit. When this bit is read out, the
contents are “0”.
Undefined
✕
✕
• This bit indicates whether the transfer to the
PWM latch is completed.
Undefined
7
0: Transfer is completed
1: Transfer is not completed
• This bit is set to “1” at writing.
Fig. 3.5.8 Structure of PWM register (low-order)
38B5 Group User’s Manual
3-36
APPENDIX
3.5 Control registers
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator
(BRG: address 1616)
b
Functions
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
• Bit rate of the serial transfer is determined.
• This is the 8-bit counter and has the reload
register.
The count source is divided by n+1 owing to
specifying a value n.
0
1
2
3
4
5
6
7
Fig. 3.5.9 Structure of baud rate generator
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register
(UARTCON: address 1716)
b
0
Name
Functions
At reset R W
0
Character length
selection bit (CHAS)
Parity enable bit
(PARE)
0: 8 bits
1: 7 bits
0: Parity checking disabled
1: Parity checking enabled
0
0
0
0
1
0: Even parity
1: Odd parity
2 Parity selection bit
(PARS)
3
0: 1 stop bit
1: 2 stop bits
Stop bit length
selection bit (STPS)
4 P55/TxD P-channel
output disable bit
(POFF)
0: CMOS output (in output
mode)
1: N-channel open-drain
output (in output mode)
0
0
5
0: XIN or XCIN/2 (depending
on internal system clock)
1: XCIN
BRG clock switch bit
6
7
Serial I/O2 clock
I/O pin selection bit
0: SCLK21 (P57/SCLK22 pin is
used as I/O port or SRDY2
output pin.)
1: SCLK22 (P56/SCLK21 pin is
used as I/O port.)
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “1”.
1
Fig. 3.5.10 Structure of UART control register
38B5 Group User’s Manual
3-37
APPENDIX
3.5 Control registers
Serial I/O1 automatic transfer data pointer
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 automatic transfer data pointer
(SIO1DP: address 1816)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
• Indicates the low-order 8 bits of the address
storing the start data on the serial I/O.
automatic transfer RAM.
• Data is written into the latch and read from the
decrement counter.
Fig. 3.5.11 Structure of serial I/O1 automatic transfer data pointer
Serial I/O1 control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 1
(SIO1CON1•SC11: address 1916)
b
0
Name
Serial transfer
selection bits
Functions
At reset R W
0
b1b0
0 0: Serial I/O disabled
(Pins P62, P64, P65,
P50–P53 pins are I/O
ports.)
0
0
1
2
0 1: 8-bit serial I/O
1 0: Not available
1 1: Automatic transfer
serial I/O (8 bits)
b3b2
Serial I/O1
0 0: Internal synchronous
synchronous clock
selection bits
(P65/SSTB1 pin
control bits)
clock (P65 pin is I/O
port.)
0 1: External synchronous
clock (P65 pin is I/O
port.)
1 0: Internal synchronous
clock (P65 pin is
SSTB1 output.)
0
3
1 1: Internal synchronous
clock (P65 pin is
SSTB1 output.)
0
0
Serial I/O
initialization bit
Transfer mode
selection bit
0: Serial I/O initialization
1: Serial I/O enabled
4
5
0: Full-duplex
(transmit/receive) mode
(P50 pin is SIN1 input.)
1: Transmit-only mode
(P50 pin is I/O port.)
Transfer direction
selection bit
0
0
0: LSB first
1: MSB first
6
7
Serial I/O1 clock pin
selection bit
0: SCLK11 (P53/SCLK12 pin
is I/O port.)
1: SCLK12 (P52/SCLK11 pin
is I/O port.)
Fig. 3.5.12 Structure of serial I/O1 control register 1
38B5 Group User’s Manual
3-38
APPENDIX
3.5 Control registers
Serial I/O1 control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 2
(SIO1CON2 • SC12: address 1A16)
b
0
Name
Functions
At reset R W
0
P62/SRDY1 •
P64/SBUSY1 pin
control bits
b3b2b1b0
0 0 0 0: P62, P64 pins are I/O ports.
0 0 0 1: Not used
0 0 1 0: P62 pin is SRDY1 output; P64 pin is
I/O port.
0 0 1 1: P62 pin is SRDY1 output; P64 pin is
I/O port.
0 1 0 0: P62 pin is I/O port; P64 pin is
SBUSY1 input.
0 1 0 1: P62 pin is I/O port; P64 pin is
SBUSY1 input.
0 1 1 0: P62 pin is I/O port; P64 pin is
SBUSY1 output.
0 1 1 1: P62 pin is I/O port; P64 pin is
SBUSY1 output.
1 0 0 0: P62 pin is SRDY1 input; P64 pin is
SBUSY1 output.
1 0 0 1: P62 pin is SRDY1 input; P64 pin is
SBUSY1 output.
1 0 1 0: P62 pin is SRDY1 input; P64 pin is
SBUSY1 output.
0
0
0
1
2
3
1 0 1 1: P62 pin is SRDY1 input; P64 pin is
SBUSY1 output.
1 1 0 0: P62 pin is SRDY1 output; P64 pin is
SBUSY1 input.
1 1 0 1: P62 pin is SRDY1 output; P64 pin is
SBUSY1 input.
1 1 1 0: P62 pin is SRDY1 output; P64 pin is
SBUSY1 input.
1 1 1 1: P62 pin is SRDY1 output; P64 pin is
SBUSY1 input.
S
BUSY1 output •
4
5
0
0
0: Functions as signal for
each 1-byte
1: Functions as signal for
each transfer data set
SSTB1 output
function selection bit
(Valid in serial I/O1
automatic transfer
mode)
Serial transfer
status flag
0: Serial transfer
completed
1: Serial transfer in-
progress
6
7
SOUT1 pin control
bit (when serial data
is not transferred)
0
0
0: Output active
1: Output high-impedance
P51/SOUT1 P-channel
output disable bit
0: CMOS 3 state (P-
channel output is valid.)
1: N-channel open-drain
output (P-channel output
is invalid.)
Fig. 3.5.13 Structure of serial I/O1 control register 2
38B5 Group User’s Manual
3-39
APPENDIX
3.5 Control registers
Serial I/O1 register/Transfer counter
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 register/Transfer counter
(SIO1: address 1B16)
b
0
Name
Functions
•At function as serial I/O1
register:
At reset R W
•In 8-bit serial I/O
mode:
Undefined
This register becomes the
shift register to perform
serial transmit/reception.
Set transmit data to this
register.
Serial I/O1 register
1
2
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
•In automatic transfer
serial I/O mode:
Transfer counter
The serial transfer is started
by writing the transmit data.
3
4
5
•At function as transfer
counter:
Set (transfer byte number –
1) to this register.
When selecting an internal
clock, the automatic
transfer is started by writing
the transmit data.
(When selecting an external
clock, after writing a value
to this register, wait for 5 or
more cycles of the internal
system clock before
6
7
inputting the transfer clock
to the SCLK1 pin.)
Fig. 3.5.14 Structure of serial I/O1 register/Transfer counter
38B5 Group User’s Manual
3-40
APPENDIX
3.5 Control registers
Serial I/O1 control register 3
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 3
(SIO1CON3 • SC13: address 1C16)
b
0
Name
Functions
At reset R W
b4b3b2b1b0
0
Automatic transfer
interval set bits
(valid only when
selecting internal
synchronous clock)
0 0 0 0 0: 2 cycles of
transfer clock
0 0 0 0 1: 3 cycles of
transfer clock
0
0
0
0
0
1
2
3
4
to
1 1 1 1 0: 32 cycles of
transfer clock
1 1 1 1 1: 33 cycles of
transfer clock
Data is written into the
latch and read from the
decrement counter.
b7b6b5
5
Internal
synchronous clock
selection bits
0 0 0 : f(XIN)/4 or f(XCIN)/8
0 0 1 : f(XIN)/8 or
f(XCIN)/16
0 1 0 : f(XIN)/16 or
f(XCIN)/32
0 1 1 : f(XIN)/32 or
f(XCIN)/64
1 0 0 : f(XIN)/64 or
f(XCIN)/128
1 0 1 : f(XIN)/128 or
f(XCIN)/256
0
0
6
7
1 1 0 : f(XIN)/256 or
f(XCIN)/512
1 1 1 : Not used
Fig. 3.5.15 Structure of serial I/O1 control register 3
38B5 Group User’s Manual
3-41
APPENDIX
3.5 Control registers
Serial I/O2 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register
(SIO2CON: address 1D16)
b
0
Name
Functions
At reset R W
0
0: f(XIN) or f(XCIN)/2 or
f(XCIN)
BRG count source
selection bit (CSS)
1: f(XIN)/4 or f(XCIN)/8 or
f(XCIN)/4
0
1
Serial I/O2
•In clock synchronous
mode
0: BRG output/4
1: External clock input
•In UART mode
synchronous clock
selection bit
(SCS)
0: BRG output/16
1: External clock input/16
0: P57 pin operates as
normal I/O pin
1: P57 pin operates as
SRDY2 output pin
0
0
2
3
SRDY2 output
enable bit (SRDY)
Transmit interrupt
source selection bit
(TIC)
0: When transmit buffer
has emptied
1: When transmit shift
operation is completed
0
0
0
4 Transmit enable bit
(TE)
0: Transmit disabled
1: Transmit enabled
0: Receive disabled
1: Receive enabled
5
Receive enable bit
(RE)
Serial I/O2 mode
6
0: Clock asynchronous
serial I/O (UART) mode
1: Clock synchronous
serial I/O mode
selection bit (SIOM)
0
Serial I/O2 enable
bit (SIOE)
0: Serial I/O2 disabled
(pins P54–P57 operate
as normal I/O pins)
7
1: Serial I/O2 enabled
(pins P54–P57 operate
as serial I/O pins)
Fig. 3.5.16 Structure of serial I/O2 control register
38B5 Group User’s Manual
3-42
APPENDIX
3.5 Control registers
Serial I/O2 status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 status register
(SIO2STS: address 1E16)
b
0
Name
Transmit buffer
empty flag (TBE)
Functions
0: Buffer full
1: Buffer empty
At reset R W
0
Receive buffer full
flag (RBF)
Transmit shift
register shift
completion flag
(TSC)
0: Buffer empty
1: Buffer full
0
0
1
2
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag
(OE)
0: No error
1: Overrun error
0
0
0
0
1
3
4
5
6
7
Parity error flag
(PE)
0: No error
1: Parity error
0: No error
1: Framing error
Framing error flag
(FE)
Summing error flag
(SE)
0: (OE) U (PE) U (FE) = 0
1: (OE) U (PE) U (FE) = 1
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “1”.
Fig. 3.5.17 Structure of serial I/O2 status register
Serial I/O2 transmit/receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 transmit/receive buffer register
(TB/RB: address 1F16)
b
0
1
Functions
At reset R W
This is the buffer register which is used to write
transmit data or to read receive data.
• At write : The value is written to the transmit
buffer register. The value cannot be
written to the receive buffer register.
• At read : The contents of the receive buffer
register is read out. When a
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
2
3
4
5
6
7
character bit length is 7 bits, the
MSB of data stored in the receive
buffer is “0”. The contents of the
transmit buffer register cannot be
read out.
Fig. 3.5.18 Structure of serial I/O2 transmit/receive buffer register
38B5 Group User’s Manual
3-43
APPENDIX
3.5 Control registers
Timer i
b7 b6 b5 b4 b3 b2 b1 b0
Timer i (i = 1, 3, 4, 5, 6)
(Ti: addresses 2016, 2216, 2316, 2416, 2516)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
1
1
1
1
1
1
1
1
• Set timer i count value.
• The value set in this register is written to both
the timer i and the timer i latch at one time.
• When the timer i is read out, the count value
of the timer i is read out.
Fig. 3.5.19 Structure of timer i
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2
(T2: address 2116)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
1
0
0
0
0
0
0
0
• Set timer 2 count value.
• The value set in this register is written to both
the timer 2 and the timer 2 latch at one time.
• When the timer 2 is read out, the count value
of the timer 2 is read out.
Fig. 3.5.20 Structure of timer 2
PWM control register
b7 b6 b5 b4 b3 b2 b1 b0
PWM control register
(PWMCON: address 2616)
Name
b
Functions
At reset R W
P87/PWM output
selection bit
0: I/O port
1: PWM output
0
0
1 Nothing is arranged for these bits. These are
0
0
0
0
0
0
0
write disabled bits. When these bits are read out,
2
3
4
5
6
7
the contents are “0”.
Fig. 3.5.21 Structure of PWM control register
38B5 Group User’s Manual
3-44
APPENDIX
3.5 Control registers
Timer 6 PWM register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 6 PWM register
(T6PWM: address 2716)
b
Functions
At reset R W
• In timer 6 PWM1 mode
Undefined
0
1
2
3
4
“L” level width of PWM rectangular waveform is set.
• Duty of PWM rectangular waveform: n/(n + m)
Period: (n + m) × ts
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
n = timer 6 set value
m = timer 6 PWM register set value
ts = timer 6 count source period
At n = 0, all PWM output “L”.
At m = 0, all PWM output “H”.
(However, n = 0 has priority.)
5
6
• Selection of timer 6 PWM1 mode
Set “1” to the timer 6 operation mode selection bit.
7
Fig. 3.5.22 Structure of timer 6 PWM register
Timer 12 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 12 mode register
(T12M: address 2816)
b
0
Name
Timer 1 count stop
bit
Functions
0: Count operation
1: Count stop
At reset R W
0
Timer 2 count stop
bit
Timer 1 count
source selection
bits
0: Count operation
1: Count stop
0
0
1
2
3
4
b3 b2
0 0: f(XIN)/8 or f(XCIN)/16
0 1: f(XCIN)
1 0: f(XIN)/16 or f(XCIN)/32
1 1: f(XIN)/64 or f(XCIN)/128
b5 b4
0 0: Timer 1 underflow
0 1: f(XCIN)
Timer 2 count
source selection
bits
0
0
1 0: External count input
CNTR0
5
1 1: Not available
0: I/O port
1: Timer 1 output
Timer 1 output
selection bit (P45)
0
0
6
7
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
Fig. 3.5.23 Structure of timer 12 mode register
38B5 Group User’s Manual
3-45
APPENDIX
3.5 Control registers
Timer 34 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 34 mode register
(T34M: address 2916)
b
0
Name
Timer 3 count stop
bit
Functions
0: Count operation
1: Count stop
At reset R W
0
Timer 4 count stop
bit
Timer 3 count
source selection
bits
0: Count operation
1: Count stop
0
0
1
2
3
4
b3 b2
0 0: f(XIN)/8 or f(XCIN)/16
0 1: Timer 2 underflow
1 0: f(XIN)/16 or f(XCIN)/32
1 1: f(XIN)/64 or f(XCIN)/128
b5 b4
0 0: f(XIN)/8 or f(XCIN)/16
0 1: Timer 3 underflow
1 0: External count input
CNTR1 (Note)
Timer 4 count
source selection
bits
0
0
5
1 1: Not available
0: I/O port
1: Timer 3 output
Timer 3 output
selection bit (P46)
0
0
6
7
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
Note: In the mask option type P, CNTR1 function cannot be used.
Fig. 3.5.24 Structure of timer 34 mode register
Timer 56 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 56 mode register
(T56M: address 2A16)
b
0
Name
Timer 5 count stop
Functions
0: Count operation
1: Count stop
At reset R W
0
bit
Timer 6 count stop
bit
Timer 5 count
0: Count operation
1: Count stop
0
0
0
0
0
0
1
2
3
4
0: f(XIN)/8 or f(XCIN)/16
1: Timer 4 underflow
source selection bit
Timer 6 operation
mode selection bit
0: Timer mode
1: PWM mode
b5 b4
Timer 6 count
source selection
bits
0 0: f(XIN)/8 or f(XCIN)/16
0 1: Timer 5 underflow
1 0: Timer 4 underflow
1 1: Not available
0: I/O port
1: Timer 6 output
5
6
Timer 6 (PWM)
output selection bit
(P44)
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
7
Fig. 3.5.25 Structure of timer 56 mode register
38B5 Group User’s Manual
3-46
APPENDIX
3.5 Control registers
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Watchdog timer control register
(WDTCON: address 2B16)
b
Name
Functions
At reset R W
0
1
2
3
4
5
6
1
1
1
1
1
1
0
Watchdog timer H
(high-order 6 bits of reading exclusive)
STP instruction
disable bit
0: STP instruction enabled
1: STP instruction disabled
7
0
Watchdog timer H
count source
0: Watchdog timer L
underflow
selection bit
1: f(XIN)/16 or f(XCIN)/16
Fig. 3.5.26 Structure of watchdog timer control register
Timer X (low-order, high-order)
b7 b6 b5 b4 b3 b2 b1 b0
Timer X (low-order, high-order)
(TXL, TXH: addresses 2C16, 2D16)
b
Functions
At reset R W
• Set timer X count value.
1
1
1
1
1
1
1
1
0
1
2
3
• When the timer X write control bit of the timer
X mode register 1 is “0”, the value is written to
timer X and the latch at one time.
When the timer X write control bit of the timer
X mode register 1 is “1”, the value is written
only to the latch.
4
5
6
7
• The timer X count value is read out by reading
this register.
Notes 1: When reading and writing, perform them to both the high-
order and low-order bytes.
2: Read both registers in order of TXH and TXL following.
3: Write both registers in order of TXL and TXH following.
4: Do not read both registers during a write, and do not write to
both registers during a read.
Fig. 3.5.27 Structure of timer X (low-order, high-order)
38B5 Group User’s Manual
3-47
APPENDIX
3.5 Control registers
Timer X mode register 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register 1
(TXM1: address 2E16)
b
0
Name
Timer X write
control bit
Functions
At reset R W
0
0 : Write value in latch and
counter
1 : Write value in latch only
b2 b1
Timer X count
source selection bits
0
0
0
1
2
3
0 0: f(XIN)/2 or f(XCIN)/4
0 1: f(XIN)/8 or f(XCIN)/16
1 0: f(XIN)/64 or f(XCIN)/128
1 1: Not available
Nothing is arranged for this bit. This is write
disabled bit. When this bit is read out, the
contents are “0”.
b5 b4
0
0
0
Timer X operating
mode bits
4
5
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width
measurement mode
0 : •Count at rising edge in
event counter mode
•Start from “H” output in
pulse output mode
CNTR2 active edge
switch bit
6
•Measure “H” pulse
width in pulse width
measurement mode
1 : •Count at falling edge in
event counter mode
•Start from “L” output in
pulse output mode
•Measure “L” pulse
width in pulse width
measurement mode
0
Timer X stop
control bit
0 : Count operating
1 : Count stop
7
Fig. 3.5.28 Structure of timer X mode register 1
38B5 Group User’s Manual
3-48
APPENDIX
3.5 Control registers
Timer X mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register 2
(TXM2: address 2F16)
b
0
Name
Functions
At reset R W
0
Real time port control
bit (P85)
0: Real time port function is
invalid
1: Real time port function is
valid
Real time port control
bit (P86)
1
0: Real time port function is
invalid
0
1: Real time port function is
valid
0
P85 data for real time
port
2
3
0: “L” output
1: “H” output
P86 data for real time
port
0: “L” output
1: “H” output
0
4
5
6
7
0
0
0
0
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
Fig. 3.5.29 Structure of timer X mode register 2
Interrupt interval determination register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt interval determination register
(IID: address 3016)
b
Functions
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
• This register stores a value which is obtained
by counting a following interval with the
counter sampling clock.
Rising interval
Falling interval
Both edges interval (Note)
(Selected by interrupt edge selection register)
• Read exclusive register
0
1
2
3
4
5
6
7
Note: When the noise filter sampling clock selection bits (bits 2, 3) of
the interrupt interval determination control register is “00”, the
both-sided edge detection function cannot be used.
Fig. 3.5.30 Structure of interrupt interval determination register
38B5 Group User’s Manual
3-49
APPENDIX
3.5 Control registers
Interrupt interval determination control register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt interval determination control register
(IIDCON: address 3116)
b
0
Name
Functions
At reset R W
0
Interrupt interval
determination circuit 1: Operating
0: Stopped
operating selection
bit
0
0
0
0
Counter sampling
clock selection bit
Noise filter
sampling clock
selection bits (INT2)
0: f(XIN)/128
1: f(XIN)/256
1
2
3
4
b3 b2
0 0: Filter is not used.
0 1: f(XIN)/32
1 0: f(XIN)/64
1 1: f(XIN)/128
0: One-sided edge
detection
One-sided/both-
sided edge
detection selection
bit
1: Both-sided edge
detection (Note)
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
5
6
7
0
0
0
Note: When the noise filter sampling clock selection bits (bits 2, 3) is
“00”, the both-sided edge detection function cannot be used.
Fig. 3.5.31 Structure of interrupt interval determination control register
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register
(ADCON: address 3216)
b
0
Name
Analog input pin
selection bits
Functions
At reset R W
0
b3 b2 b1 b0
0 0 0 0: P70/AN0
0 0 0 1: P71/AN1
0 0 1 0: P72/AN2
0 0 1 1: P73/AN3
0 1 0 0: P74/AN4
0 1 0 1: P75/AN5
0 1 1 0: P76/AN6
0 1 1 1: P77/AN7
1 0 0 0: P62/SRDY1/AN8
1 0 0 1: P63/AN9
1 0 1 0: P64/INT4/SBUSY1/AN10
1 0 1 1: P65/SSTB1/AN11
1
0
0
2
3
4
0
1
0: Conversion in progress
1: Conversion completed
AD conversion
completion bit
0
0
0
5
6
7
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
Fig. 3.5.32 Structure of A-D control register
38B5 Group User’s Manual
3-50
APPENDIX
3.5 Control registers
A-D conversion register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (low-order)
(ADL: address 3316)
b
Functions
At reset R W
Undefined
Nothing is arranged for these bits. These are write
disabled bits. When these bits are read out, the
contents are “0”.
0
1
2
3
4
5
6
7
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
These are A-D conversion result (low-order 2 bits)
stored bits. This is read exclusive register.
Undefined
Note: Do not read this register during A-D conversion.
Fig. 3.5.33 Structure of A-D conversion register (low-order)
A-D conversion register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (high-order)
(ADH: address 3416)
b
Functions
At reset R W
Undefined
0
1
2
3
4
5
6
7
This is A-D conversion result (high-order 8 bits) stored
bits. This is read exclusive register.
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Note: Do not read this register during A-D conversion.
Fig. 3.5.34 Structure of A-D conversion register (high-order)
38B5 Group User’s Manual
3-51
APPENDIX
3.5 Control registers
Interrupt source switch register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt source switch register
(IFR: address 3916
)
b
0
Name
INT3/serial I/O2
transmit interrupt
switch bit (Note)
Functions
3 intrrupt
1: Serial I/O2 transmit
interrupt
At reset R W
0
0: INT
0: INT
4
interrupt
0
1 INT
4/A-D
1: A-D conversion intrerrupt
conversion interrupt
switch bit
0
0
0
0
0
0
2
3
4
5
6
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
7
Note: In the mask option type P, this bit is not available because INT
3
function cannot be used.
Fig. 3.5.35 Structure of interrupt source switch register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register
(INTEDGE : address 3A16)
b
0
Name
INT0 interrupt edge
selection bit
INT1 interrupt edge
selection bit
INT2 interrupt edge
selection bit
INT3 interrupt edge
selection bit (Note) 1 : Rising edge active
INT4 interrupt edge
selection bit
Functions
At reset R W
0
0
0
0
0
0
0 : Falling edge active
1 : Rising edge active
1
2
3
4
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
0 : Falling edge active
1 : Rising edge active
5 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
CNTR0 pin edge
switch bit
CNTR1 pin edge
switch bit (Note)
0
0
0 : Rising edge count
1 : Falling edge count
6
0 : Rising edge count
1 : Falling edge count
7
Note: In the mask option type P, these bits are not available because
CNTR1 function and INT3 function cannot be used.
Fig. 3.5.36 Structure of interrupt edge selection register
38B5 Group User’s Manual
3-52
APPENDIX
3.5 Control registers
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register
(CPUM, CM: address 3B16)
b
0
Name
Functions
At reset R W
0
b1 b0
Processor mode
bits
00 : Single-chip mode
01 :
0
0
1
0
1
2
3
4
10 :
11 :
0 : Page 0
1 : Page 1
Not available
Stack page
selection bit
XCOUT drivability
selection bit
Port Xc switch bit
0: Low drive
1: High drive
0: I/O port function
1: XCIN-XCOUT oscillation
function
Main clock (XIN-
XOUT) stop bit
0: Oscillating
1: Stopped
0
1
5
6
Main clock division
ratio selection bit
0: f(XIN) (high-speed mode)
1: f(XIN)/4 (middle-speed
mode)
0: XIN–XOUT selection
(middle-/high-speed
mode)
0
7
Internal system
clock selection bit
1: XCIN–XCOUT selection
(low-speed mode)
Fig. 3.5.37 Structure of CPU mode register
38B5 Group User’s Manual
3-53
APPENDIX
3.5 Control registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16)
b
0
Name
INT0 interrupt
request bit
Functions
At reset R W
✽
✽
✽
0
0
0
0 : No interrupt request
issued
1 : Interrupt request issued
INT1 interrupt
request bit
1
0 : No interrupt request
issued
1 : Interrupt request issued
2 INT2 interrupt
request bit
0 : No interrupt request
issued
Remote controller
/counter overflow
interrupt request bit
1 : Interrupt request issued
✽
0
3
0 : No interrupt request
issued
1 : Interrupt request issued
Serial I/O1 interrupt
request bit
Serial I/O automatic
transfer interrupt
request bit
Timer X interrupt
4
✽
✽
✽
✽
0
0
0
0
0 : No interrupt request
issued
1 : Interrupt request issued
request bit
Timer 1 interrupt
request bit
5
6
7
0 : No interrupt request
issued
1 : Interrupt request issued
Timer 2 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
Timer 3 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
✽: “0” can be set by software, but “1” cannot be set.
Fig. 3.5.38 Structure of interrupt request register 1
38B5 Group User’s Manual
3-54
APPENDIX
3.5 Control registers
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16)
b
0
Name
Functions
0 : No interrupt request issued
1 : Interrupt request issued
At reset R W
Timer 4 interrupt
request bit (Note)
Timer 5 interrupt
request bit
Timer 6 interrupt
request bit
Serial I/O2 receive
interrupt request bit
INT3/Serial I/O2
transmit interrupt
request bit (Note)
✽
✽
✽
✽
✽
0
0
0
0
0
0 : No interrupt request issued
1 : Interrupt request issued
1
2
3
4
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
✽
✽
0
0
0
INT4 interrupt
request bit
A-D converter
interrupt request bit
FLD blanking
interrupt request bit
FLD digit interrupt
request bit
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
0 : No interrupt request issued
1 : Interrupt request issued
5
6
7
0 : No interrupt request issued
1 : Interrupt request issued
✽: “0” can be set by software, but “1” cannot be set.
Note: In the mask option type P, if timer 4 interrupt whose count source is
CNTR1 input and INT3 interrupt are selected, these bits do not
become “1”.
Fig. 3.5.39 Structure of interrupt request register 2
38B5 Group User’s Manual
3-55
APPENDIX
3.5 Control registers
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 3E16)
b
0
Name
Functions
At reset R W
0
INT0 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
1 INT1 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
2 INT2 interrupt
enable bit
Remote controller
/counter overflow
interrupt enable bit
0
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O1 interrupt
enable bit
3
Serial I/O automatic
transfer interrupt
enable bit
Timer X interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
4
5
6
7
Timer 1 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Timer 2 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
Timer 3 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 3.5.40 Structure of interrupt control register 1
38B5 Group User’s Manual
3-56
APPENDIX
3.5 Control registers
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2
(ICON2 : address 3F16
0
)
b
0
Name
Functions
At reset R W
0
Timer 4 interrupt
enable bit (Note)
Timer 5 interrupt
enable bit
Timer 6 interrupt
enable bit
Serial I/O2 receive
interrupt enable bit
INT3/Serial I/O2
0 : interrupt disabled
1 : Interrupt enabled
0
0
0
0
1
2
3
4
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
transmit interrupt
enable bit (Note)
0
0
0
INT4 interrupt
enable bit
5
6
7
0 : interrupt disabled
1 : Interrupt enabled
A-D converter
interrupt enable bit
FLD blanking
interrupt enable bit
FLD digit interrupt
enable bit
0 : interrupt disabled
1 : Interrupt enabled
Fix “0” to this bit.
Note: In the mask option type P, timer 4 interrupt whose count source
is CNTR input and INT interrupt are not available.
1
3
Fig. 3.5.41 Structure of interrupt control register 2
38B5 Group User’s Manual
3-57
APPENDIX
3.5 Control registers
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register 1
(PULL1: address 0EF016)
b
0
Name
Ports P50, P51 pull-
up control
Functions
0: No pull-up
1: Pull-up
At reset R W
0
0: No pull-up
1: Pull-up
Ports P52, P53 pull-
up control
0
0
0
0
0
0
0
1
2
3
4
5
6
7
Ports P54, P55 pull- 0: No pull-up
up control
1: Pull-up
Ports P56, P57 pull-
up control
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
Port P61 pull-up
control
Ports P62, P63 pull-
up control
Ports P64, P65 pull-
up control
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
Note: The pin set to output port is cut off from pull-up control.
Fig. 3.5.42 Structure of pull-up control register 1
Pull-up control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register 2
(PULL2: address 0EF116)
b
0
Name
Ports P70, P71 pull-
up control
Functions
0: No pull-up
1: Pull-up
At reset R W
0
0: No pull-up
1: Pull-up
Ports P72, P73 pull-
up control
0
0
0
0
0
0
0
1
2
3
4
5
6
7
Ports P74, P75 pull- 0: No pull-up
up control
1: Pull-up
Ports P76, P77 pull-
up control
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
Ports P84, P85 pull-
up control
Ports P86, P87 pull-
up control
Ports P90, P91 pull-
up control
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
Note: The pin set to output port is cut off from pull-up control.
Fig. 3.5.43 Structure of pull-up control register 2
38B5 Group User’s Manual
3-58
APPENDIX
3.5 Control registers
P1FLDRAM write disable register
b7 b6 b5 b4 b3 b2 b1 b0
P1FLDRAM write disable register
(P1FLDRAM: address 0EF216)
b
0
Name
Functions
At reset R W
0
FLDRAM corre-
sponding to port
P10 write disable bit
0: Operating normally
1: Write disabled
0
0
0
0
0
0
0
1
2
3
4
5
6
7
FLDRAM corre-
sponding to port
P11 write disable bit
0: Operating normally
1: Write disabled
FLDRAM corre-
sponding to port
P12 write disable bit
0: Operating normally
1: Write disabled
FLDRAM corre-
sponding to port
P13 write disable bit
0: Operating normally
1: Write disabled
FLDRAM corre-
sponding to port
P14 write disable bit
0: Operating normally
1: Write disabled
FLDRAM corre-
sponding to port
P15 write disable bit
0: Operating normally
1: Write disabled
0: Operating normally
1: Write disabled
FLDRAM corre-
sponding to port
P16 write disable bit
FLDRAM corre-
sponding to port
P17 write disable bit
0: Operating normally
1: Write disabled
Fig. 3.5.44 Structure of P1FLDRAM write disable register
38B5 Group User’s Manual
3-59
APPENDIX
3.5 Control registers
P3FLDRAM write disable register
b7 b6 b5 b4 b3 b2 b1 b0
P3FLDRAM write disable register
(P3FLDRAM: address 0EF316)
b
0
Name
Functions
At reset R W
0
FLDRAM corre-
sponding to port
P30 write disable bit
0: Operating normally
1: Write disabled
0
0
0
0
0
0
0
1
2
3
4
5
6
7
FLDRAM corre-
sponding to port
P31 write disable bit
0: Operating normally
1: Write disabled
FLDRAM corre-
sponding to port
P32 write disable bit
0: Operating normally
1: Write disabled
FLDRAM corre-
sponding to port
P33 write disable bit
0: Operating normally
1: Write disabled
FLDRAM corre-
sponding to port
P34 write disable bit
0: Operating normally
1: Write disabled
FLDRAM corre-
sponding to port
P35 write disable bit
0: Operating normally
1: Write disabled
0: Operating normally
1: Write disabled
FLDRAM corre-
sponding to port
P36 write disable bit
FLDRAM corre-
sponding to port
P37 write disable bit
0: Operating normally
1: Write disabled
Fig. 3.5.45 Structure of P3FLDRAM write disable register
38B5 Group User’s Manual
3-60
APPENDIX
3.5 Control registers
FLDC mode register
b7 b6 b5 b4 b3 b2 b1 b0
FLDC mode register
(FLDM: address 0EF416)
b
0
Name
Functions
At reset R W
0
Automatic display
control bit (P0, P1,
P2, P3, P8)
0 : General-purpose mode
1 : Automatic display
mode
Display start bit
0
0
1
2
0 : Display stopped
1 : Display in progress (display
starts by writing “1”)
Tscan control bits
b3 b2
0 0 : 0 FLD digit interrupt
(at rising edge of each
digit)
0 1 : 1 ✕ Tdisp
1 0 : 2 ✕ Tdisp
3
0
1 1 : 3 ✕ Tdisp
FLD blanking interrupt (at
falling edge of last digit)
4
5
Timing number
control bit
0 : 16 timing mode
1 : 32 timing mode (Note 2)
0
0
Gradation display
mode selection
control bit
0 : Not selected
1 : Selected (Notes 1, 2)
6
7
Tdisp counter count 0 : f(XIN)/16 or f(XCIN)/32
source selection bit 1 : f(XIN)/64 or f(XCIN)/128
0
0
High-breakdown
voltage port driv-
ability selection bit
0 : Drivability strong
1 : Drivability weak
Notes 1: When the gradation display mode is selected, the number of
timing is max. 16 timing. (Set “0” to the timing number control
bit (b4).)
2: When switching the timing number control bit (b4) or the
gradation display mode selection control bit (b5), set “0” to
the display start bit (b1) (display stop state) before that.
Fig. 3.5.46 Structure of FLDC mode register
38B5 Group User’s Manual
3-61
APPENDIX
3.5 Control registers
Tdisp time set register
b7 b6 b5 b4 b3 b2 b1 b0
Tdisp time set register
(TDISP: address 0EF516)
b
Functions
At reset R W
0
0
1
2
3
4
5
6
7
•Set the Tdisp time.
•When a value n is written to this register, Tdisp
time is expressed as Tdisp = (n + 1) ✕ count
source.
•When reading this register, the value in the
counter is read out.
0
0
0
0
0
0
0
(Example)
When the following condition is satisfied, Tdisp
becomes 804 µs {(200 + 1) ✕ 4 µs};
•f(XIN) = 4 MHz
•bit 6 of FLDC mode register = 0
(f(XIN)/16 is selected as Tdisp counter count
source. )
•Tdisp time set register = 200 (C816).
Fig. 3.5.47 Structure of Tdisp time set register
38B5 Group User’s Manual
3-62
APPENDIX
3.5 Control registers
Toff1 time set register
b7 b6 b5 b4 b3 b2 b1 b0
Toff1 time set register
(TOFF1: address 0EF616)
b
0
Functions
At reset R W
1
•Set the Toff1 time.
•When a value n1 is written to this register,
Toff1 time is expressed as Toff1 = n1 ✕ count
source.
1
1
1
1
1
1
1
1
2
3
4
5
6
7
(Example)
When the following condition is satisfied, Toff1
becomes 120 µs (= 30 ✕ 4 µs);
•f(XIN) = 4 MHz
•bit 6 of FLDC mode register = 0
(f(XIN)/16 is selected as Tdisp counter count
source.)
•Toff1 time set register = 30 (1E16).
Note: Set value of 0316 or more.
Fig. 3.5.48 Structure of Toff1 time set register
Toff2 time set register
b7 b6 b5 b4 b3 b2 b1 b0
Toff2 time set register
(TOFF2: address 0EF716)
b
0
Functions
At reset R W
1
•Set the Toff2 time.
•When a value n2 is written to this register,
Toff2 time is expressed as Toff2 = n2 ✕ count
source.
However, setting of Toff2 time is valid only for
the FLD port which is satisfied the following;
•gradation display mode
1
1
1
1
1
1
1
1
2
3
4
5
6
7
•value of FLD automatic display RAM (in
gradation display mode) = “1” (dark display).
(Example)
When the following condition is satisfied, Toff2
becomes 720 µs (= 180 ✕ 4 µs);
•f(XIN) = 4 MHz
•bit 6 of FLDC mode register = 0
(f(XIN)/16 is selected as Tdisp counter count
source.)
•Toff2 time set register = 180 (B416).
Note: When the Toff2 control bit (b7) of the port P8FLD output control
register (address 0EFC16) is set to “1”, set value of 0316 or
more to the Toff2 control register.
Fig. 3.5.49 Structure of Toff2 time set register
38B5 Group User’s Manual
3-63
APPENDIX
3.5 Control registers
FLD data pointer/FLD data pointer reload register
b7 b6 b5 b4 b3 b2 b1 b0
FLD data pointer/FLD data pointer reload register
(FLDDP: address 0EF816)
b
0
Functions
At reset R W
Undefined
The start address of each data of FLD ports P0,
P1, P2, P3, and P8, which is transferred from
FLD automatic display RAM, is set to this
register.
The start address becomes the address adding
the value set to this register into the last data
address of each FLD port.
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
1
2
3
4
5
6
7
Set a value of (timing number – 1) to this
register.
The value which is set to this address is written
to the FLD data pointer reload register.
When reading data from this address, the value
in the FLD data pointer is read.
When bits 5 to 7 of this register is read, “0” is
always read.
Fig. 3.5.50 Structure of FLD data pointer/FLD data pointer reload register
Port P0FLD/port switch register
b7 b6 b5 b4 b3 b2 b1 b0
Port P0FLD/port switch register
(P0FPR: address 0EF916)
b
0
Name
Port P00FLD/port
switch bit
Functions
At reset R W
0
0 : General-purpose port
1 : FLD port
Port P01FLD/port
switch bit
Port P02FLD/port
switch bit
Port P03FLD/port
switch bit
Port P04FLD/port
switch bit
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
Port P05FLD/port
switch bit
Port P06FLD/port
switch bit
Port P07FLD/port
switch bit
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
Fig. 3.5.51 Structure of port P0FLD/Port switch register
38B5 Group User’s Manual
3-64
APPENDIX
3.5 Control registers
Port P2FLD/port switch register
b7 b6 b5 b4 b3 b2 b1 b0
Port P2FLD/port switch register
(P2FPR: address 0EFA16)
b
0
Name
Port P20FLD/port
switch bit
Functions
At reset R W
0
0 : General-purpose port
1 : FLD port
Port P21FLD/port
switch bit
Port P22FLD/port
switch bit
Port P23FLD/port
switch bit
Port P24FLD/port
switch bit
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
Port P25FLD/port
switch bit
Port P26FLD/port
switch bit
Port P27FLD/port
switch bit
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
Fig. 3.5.52 Structure of port P2FLD/port switch register
Port P8FLD/port switch register
b7 b6 b5 b4 b3 b2 b1 b0
Port P8FLD/port switch register
(P8FPR: address 0EFB16)
b
0
Name
Port P80FLD/port
switch bit
Functions
At reset R W
0
0 : General-purpose port
1 : FLD port
Port P81FLD/port
switch bit
Port P82FLD/port
switch bit
Port P83FLD/port
switch bit
Port P84FLD/port
switch bit
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
Port P85FLD/port
switch bit
Port P86FLD/port
switch bit
Port P87FLD/port
switch bit
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
Fig. 3.5.53 Structure of port P8FLD/port switch register
38B5 Group User’s Manual
3-65
APPENDIX
3.5 Control registers
Port P8FLD output control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P8FLD output control register
(P8FLDCON : address 0EFC16)
b
0
Name
P84–P87 FLD
output reverse bit
Functions
0 : Output normally
1 : Reverse output
At reset R W
0
P84–P87/FLDRAM 0 : Operating normally
0
0
0
0
1
2
3
4
1 : Write disabled
write disable bit
P84–P87 Toff
invalid bit
0 : Operating normally
1 : Toff invalid
P84–P87 delay
control bit (Note)
P63/AN9 dimmer
output control bit
0 : No delay
1 : Delay
0 : Ordinary port
1 : Dimmer output
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
5
6
7
0
0
0 : Operating normally
Toff2 control bit
0
(falling operation)
1 : Rising operation
Note: Valid only when selecting FLD port and P84–P87 Toff invalid function
Fig. 3.5.54 Structure of port P8FLD output control register
Buzzer output control register
b7 b6 b5 b4 b3 b2 b1 b0
Buzzer output control register
(BUZCON: address 0EFD16)
b
0
Name
Output frequency
selection bits
Functions
At reset R W
0
b1b0
0 0: 1 kHz (f(XIN)/4096)
0 1: 2 kHz (f(XIN)/2048)
1 0: 4 kHz (f(XIN)/1024)
1 1: Not available
b3b2
0
0
1
2
Output port
selection bits
0 0: P20 and P43 function
as ordinary ports.
0 1: P43/BUZ01 functions as
a buzzer output.
0
0
3
4
1 0: P20/BUZ02/FLD0
functions as a buzzer
output.
1 1: Not available
Buzzer output
ON/OFF bit
0: Buzzer output OFF (“0”
output)
1: Buzzer output ON
5
6
7
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
0
0
0
Fig. 3.5.55 Structure of buzzer output control register
38B5 Group User’s Manual
3-66
APPENDIX
3.6 Mask ROM confirmation form
3.6 Mask ROM confirmation form
GZZ-SH54-19B<88A1>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38B57M6-XXXFP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Supervisor
Submitted by
TEL
(
Company
name
)
❈ Customer
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data.
We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type
27512
EPROM address
000016
Product name
ASCII code :
‘M38B57M6-’
In the address space of the microcomputer, the internal
ROM area is from address A08016 to FFFD16. The reset
vector is stored in addresses FFFC16 and FFFD16.
000F16
001016
A07F16
A08016
Data
ROM (24K-130) bytes
FFFD16
FFFE16
FFFF16
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
(1) Set the data in the unused area (the shaded area of the
diagram) to “FF16”.
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘B’ = 4216
‘5’ = 3516
‘7’ = 3716
‘M’ = 4D16
‘6’ = 3616
‘–’ = 2D16
FF16
(2) The ASCII codes of the product name “M38B57M6–”
must be entered in addresses 000016 to 000816. And set
the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right in
hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
38B5 Group User’s Manual
3-67
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH54-19B<88A1>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38B57M6-XXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program be-
cause ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
27512
*= $0000
.BYTE ‘M38B57M6–’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM
will not be processed.
❈2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate
mark specification form (80P6N) and attach it to the mask ROM confirmation form.
❈3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
External clock input
Quartz crystal
Other (
)
At what frequency?
f(XIN) =
MHz
(2) How will you use the XCIN-XCOUT oscillator?
Ceramic resonator
Quartz crystal
Other (
External clock input
)
At what frequency?
f(XCIN) =
kHz
❈4. Comments
(2/2)
38B5 Group User’s Manual
3-68
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH54-20B<88A1>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38B57MCH-
MITSUBISHI ELECTRIC
XXXFP
signature
signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
❈ Customer
Date
Date:
issued
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data.
We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type
27512
EPROM address
000016
Product name
ASCII code :
‘M38B57MCH-’
In the address space of the microcomputer, the internal
ROM area is from address 408016 to FFFD16. The reset
vector is stored in addresses FFFC16 and FFFD16.
000F16
001016
001116
Mask option
407F16
408016
Data
ROM (48K-130) bytes
FFFD16
FFFE16
FFFF16
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
(1) Set the data in the unused area (the shaded area of the
diagram) to “FF16”.
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘B’ = 4216
‘5’ = 3516
‘7’ = 3716
‘M’ = 4D16
‘C’ = 4316
‘H’ = 4816
‘–’ = 2D16
FF16
(2) The ASCII codes of the product name “M38B57MCH–”
must be entered in addresses 000016 to 000916. And set
the data “FF16” in addresses 000A16 to 000F16.
The ASCII codes and addresses are listed to the right in
hexadecimal notation.
FF16
FF16
FF16
FF16
The option data must be entered in address 001016.
FF16
(1/3)
38B5 Group User’s Manual
3-69
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH54-20B<88A1>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
✽
SINGLE-CHIP MICROCOMPUTER M38B57MCH-
MITSUBISHI ELECTRIC
XXXFP
We recommend the use of the following pseudo-command to set the start address of the assembler source program be-
cause ASCII codes of the product name are written to addresses 000016 to 000916 of EPROM.
EPROM type
27512
*= $0000
.BYTE ‘M38B57MCH–’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM
will not be processed.
❈2. Mask option specification
High-breakdown voltage ports P20 to P27 and P80 to P83 can be selected whether pull-down resistors are built-in or not
from among the following 8 types by the mask option.
Select built-in type of pull-down resistors from among the following A to G, P, and fill out the following certainly.
(Fill out the upper part of page 1/3 also.)
Set the data of the same option type name in EPROM specified address. (Set the ASCII code of A to G, P; 4116 to 4716,
5016.)
Set the following pseudo-command to the assembler source program.
EPROM type
27512
*= $0010
.BYTE $XX
The pseudo-command
Connective port of pull-down resistor
(connected at “1” writing)
Option type
P2
0
P2
1
P2
2
P2
3
P2
4
P2
5
P2
6
P2
7
P8
0
P8
1
P8
2
P8
3
A ($41)
B ($42)
C ($43)
D ($44)
E ($45)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
F ($46)
G ($47)
P ($50)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
M38B57MCH-
XXXFP
Option type
Fill out with any one of A to G, P.
(2/3)
38B5 Group User’s Manual
3-70
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH54-20B<88A1>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
✽
SINGLE-CHIP MICROCOMPUTER M38B57MCH-
MITSUBISHI ELECTRIC
XXXFP
❈ 3. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate
mark specification form (80P6N) and attach it to the mask ROM confirmation form.
❈ 4. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
External clock input
Quartz crystal
Other (
)
At what frequency?
f(XIN) =
MHz
(2) How will you use the XCIN-XCOUT oscillator?
Ceramic resonator
Quartz crystal
Other (
External clock input
)
At what frequency?
f(XCIN) =
kHz
❈ 5. Comments
(3/3)
38B5 Group User’s Manual
3-71
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH54-21B<88A1>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
Section head Supervisor
signature signature
SINGLE-CHIP MICROCOMPUTER M38B59MFH-
MITSUBISHI ELECTRIC
XXXFP
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
❈ Customer
Date
Date:
issued
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data.
We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type
27512
EPROM address
000016
Product name
ASCII code :
‘M38B59MFH-’
In the address space of the microcomputer, the internal
ROM area is from address 108016 to FFFD16. The reset
vector is stored in addresses FFFC16 and FFFD16.
000F16
001016
001116
Mask option
107F16
108016
Data
ROM (60K-130) bytes
FFFD16
FFFE16
FFFF16
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
(1) Set the data in the unused area (the shaded area of the
diagram) to “FF16”.
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘B’ = 4216
‘5’ = 3516
‘9’ = 3916
‘M’ = 4D16
‘F’ = 4616
‘H’ = 4816
‘–’ = 2D16
FF16
(2) The ASCII codes of the product name “M38B59MFH–”
must be entered in addresses 000016 to 000916. And set
the data “FF16” in addresses 000A16 to 000F16.
The ASCII codes and addresses are listed to the right in
hexadecimal notation.
FF16
FF16
FF16
FF16
The option data must be entered in address 001016.
FF16
(1/3)
38B5 Group User’s Manual
3-72
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH54-21B<88A1>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
✽
SINGLE-CHIP MICROCOMPUTER M38B59MFH-
MITSUBISHI ELECTRIC
XXXFP
We recommend the use of the following pseudo-command to set the start address of the assembler source program be-
cause ASCII codes of the product name are written to addresses 000016 to 000916 of EPROM.
EPROM type
27512
*= $0000
.BYTE ‘M38B59MFH–’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM
will not be processed.
❈ 2. Mask option specification
High-breakdown voltage ports P20 to P27 and P80 to P83 can be selected whether pull-down resistors are built-in or not
from among the following 8 types by the mask option.
Select built-in type of pull-down resistors from among the following A to G, P, and fill out the following certainly.
(Fill out the upper part of page 1/3 also.)
Set the data of the same option type name in EPROM specified address. (Set the ASCII code of A to G, P; 4116 to 4716,
5016.)
Set the following pseudo-command to the assembler source program.
EPROM type
27512
*= $0010
.BYTE $XX
The pseudo-command
Connective port of pull-down resistor
(connected at “1” writing)
Option type
P2
0
P2
1
P2
2
P2
3
P2
4
P2
5
P2
6
P2
7
P8
0
P8
1
P8
2
P8
3
A ($41)
B ($42)
C ($43)
D ($44)
E ($45)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
F ($46)
G ($47)
P ($50)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
M38B59MFH-
XXXFP
Option type
Fill out with any one of A to G, P.
(2/3)
38B5 Group User’s Manual
3-73
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH54-21B<88A1>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
✽
SINGLE-CHIP MICROCOMPUTER M38B59MFH-
MITSUBISHI ELECTRIC
XXXFP
❈ 3. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate
mark specification form (80P6N) and attach it to the mask ROM confirmation form.
❈ 4. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
External clock input
Quartz crystal
Other (
)
At what frequency?
f(XIN) =
MHz
(2) How will you use the XCIN-XCOUT oscillator?
Ceramic resonator
Quartz crystal
Other (
External clock input
)
f(XCIN) =
At what frequency?
kHz
❈ 5. Comments
(3/3)
38B5 Group User’s Manual
3-74
APPENDIX
3.7 ROM programming confirmation form
3.7 ROM programming confirmation form
GZZ-SH54-22B<88A0>
ROM number
Date:
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38B59EF-XXXFP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
❈ Customer
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based
on this data. We shall assume the responsibility for errors only if the ROM programming data on the products we
produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type
27512
EPROM address
000016
Product name
ASCII code :
‘M38B59EF-’
In the address space of the microcomputer, the internal
ROM area is from address 108016 to FFFD16. The reset
vector is stored in addresses FFFC16 and FFFD16.
000F16
001016
107F16
108016
Data
ROM (60K-130) bytes
FFFD16
FFFE16
FFFF16
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
(1) Set the data in the unused area (the shaded area of the
diagram) to “FF16”.
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘B’ = 4216
‘5’ = 3516
‘9’ = 3916
‘E’ = 4516
‘F’ = 4616
‘–’ = 2D16
FF16
(2) The ASCII codes of the product name “M38B59EF–”
must be entered in addresses 000016 to 000816. And set
the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right in
hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
38B5 Group User’s Manual
3-75
APPENDIX
3.7 ROM programming confirmation form
GZZ-SH54-22B<88A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38B59EF-XXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program be-
cause ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
27512
*= $0000
.BYTE ‘M38B59EF–’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation
form, the ROM will not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate
mark specification form (80P6N) and attach it to the ROM programming confirmation form.
❈3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
External clock input
Quartz crystal
Other (
)
At what frequency?
f(XIN) =
MHz
(2) How will you use the XCIN-XCOUT oscillator?
Ceramic resonator
Quartz crystal
Other (
External clock input
)
At what frequency?
kHz
f(XCIN) =
❈ 4. Comments
(2/2)
38B5 Group User’s Manual
3-76
APPENDIX
3.8 Mark specification form
3.8 Mark specification form
80P6N (80-PIN QFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
64
41
40
65
Mitsubishi IC catalog name
Mitsubishi product number
(6-digit, or 7-digit)
80
25
1
24
B. Customer’s Parts Number + Mitsubishi IC Catalog Name
64
41
40
65
Customer’s Parts Number
Note : The fonts and size of characters are standard Mitsubishi type.
Mitsubishi IC catalog name
Notes 1 :The mark field should be written right aligned.
2 :The fonts and size of characters are standard Mitsubishi type.
3 : Customer’s parts number can be up to 14 alphanumeric char-
acters for capital letters, hyphens, commas, periods and so on.
80
25
1
24
4 : If the Mitsubishi logo
is not required, check the box below.
Mitsubishi logo is not required
C. Special Mark Required
Notes1 :If special mark is to be printed, indicate the desired lay-
out of the mark in the left figure. The layout will be
duplicated technically as close as possible.
Mitsubishi product number (6-digit, or 7-digit) and Mask
ROM number (3-digit) are always marked for sorting the
products.
64
41
40
65
2 : If special character fonts (e,g., customer’s trade mark
logo) must be used in Special Mark, check the box be-
low.
80
25
For the new special character fonts, a clean font original
(ideally logo drawing) must be submitted.
1
24
Special character fonts required
38B5 Group User’s Manual
3-77
APPENDIX
3.9 Package outline
3.9 Package outline
80P6N-A
Plastic 80pin 14✕20mm body QFP
EIAJ Package Code
QFP80-P-1420-0.80
JEDEC Code
–
Weight(g)
1.58
Lead Material
Alloy 42
MD
HD
D
80
65
1
64
I2
Recommended Mount Pad
Dimension in Millimeters
Symbol
A
Min
–
0
–
0.3
0.13
13.8
19.8
–
16.5
22.5
0.4
–
Nom
–
Max
3.05
0.2
–
0.45
0.2
14.2
20.2
–
17.1
23.1
0.8
–
0.1
10°
–
A1
0.1
2.8
0.35
0.15
14.0
20.0
0.8
16.8
22.8
0.6
1.4
–
–
0.5
–
14.6
20.6
A
2
b
c
D
E
e
24
41
25
40
A
L1
H
H
D
E
L
L1
y
–
0°
–
1.3
–
F
e
b
L
b2
Detail F
I
2
–
–
y
M
M
D
E
–
–
38B5 Group User’s Manual
3-78
APPENDIX
3.10 List of instruction code
3.10 List of instruction code
D3 – D0
0000
0001
0010
0011
0100
0101
5
0110
6
0111
7
1000
8
1001
9
1010
A
1011
B
1100
C
1101
D
1110
E
1111
F
Hexadecimal
notation
0
1
2
3
4
D7 – D4
0000
ORA
JSR
BBS
ORA
ZP
ASL
ZP
BBS
0, ZP
ORA
IMM
ASL
A
SEB
0, A
ORA
ABS
ASL
ABS
SEB
0, ZP
BRK
—
PHP
CLC
PLP
SEC
PHA
CLI
—
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
IND, X ZP, IND 0, A
ORA
IND, Y
BBC
0, A
ORA
ASL
BBC
ORA
ABS, Y
DEC
A
CLB
0, A
ORA
ASL
CLB
BPL
JSR
CLT
—
—
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ZP, X ZP, X 0, ZP
ABS, X ABS, X 0, ZP
AND
ABS IND, X
JSR
SP
BBS
1, A
BIT
ZP
AND
ZP
ROL
ZP
BBS
1, ZP
AND
IMM
ROL
A
SEB
1, A
BIT
ABS
AND
ABS
ROL
ABS
SEB
1, ZP
AND
BMI
BBC
1, A
AND
ROL
BBC
AND
ABS, Y
INC
A
CLB
1, A
LDM
AND
ROL
CLB
SET
STP
—
IND, Y
ZP, X ZP, X 1, ZP
ZP ABS, X ABS, X 1, ZP
EOR
RTI
BBS
2, A
COM
ZP
EOR
ZP
LSR
ZP
BBS
2, ZP
EOR
IMM
LSR
A
SEB
2, A
JMP
ABS
EOR
ABS
LSR
ABS
SEB
2, ZP
IND, X
EOR
BVC
BBC
2, A
EOR
LSR
BBC
EOR
ABS, Y
CLB
2, A
EOR
LSR
CLB
—
—
—
—
IND, Y
ZP, X ZP, X 2, ZP
ABS, X ABS, X 2, ZP
ADC
RTS
MUL
BBS
3, A
TST
ZP
ADC
ZP
ROR
ZP
BBS
3, ZP
ADC
IMM
ROR
A
SEB
3, A
JMP
IND
ADC
ABS
ROR
ABS
SEB
3, ZP
PLA
SEI
IND, X ZP, X
ADC
—
BBC
3, A
ADC
ROR
BBC
ADC
ABS, Y
CLB
3, A
ADC
ROR
CLB
BVS
BRA
—
—
—
IND, Y
ZP, X ZP, X 3, ZP
ABS, X ABS, X 3, ZP
STA
IND, X
RRF
ZP
BBS
4, A
STY
ZP
STA
ZP
STX
ZP
BBS
4, ZP
SEB
4, A
STY
ABS
STA
ABS
STX
ABS
SEB
4, ZP
DEY
TYA
TAY
CLV
INY
—
TXA
TXS
TAX
TSX
DEX
—
STA
IND, Y
BBC
4, A
STY
STA
STX
BBC
STA
ABS, Y
CLB
4, A
STA
ABS, X
CLB
4, ZP
BCC
LDY
—
—
—
ZP, X ZP, X ZP, Y 4, ZP
LDA
LDX
BBS
5, A
LDY
ZP
LDA
ZP
LDX
ZP
BBS
5, ZP
LDA
IMM
SEB
5, A
LDY
ABS
LDA
ABS
LDX
ABS
SEB
5, ZP
IMM IND, X IMM
LDA
JMP
BBC
LDY
LDA
LDX
BBC
LDA
ABS, Y
CLB
LDY
LDA
LDX
CLB
BCS
IND, Y ZP, IND 5, A
ZP, X ZP, X ZP, Y 5, ZP
5, A ABS, X ABS, X ABS, Y 5, ZP
CPY
CMP
IMM IND, X
BBS
6, A
CPY
ZP
CMP
ZP
DEC
ZP
BBS
6, ZP
CMP
IMM
SEB
6, A
CPY
ABS
CMP
ABS
DEC
ABS
SEB
6, ZP
WIT
CMP
BNE
BBC
6, A
CMP
DEC
BBC
CMP
ABS, Y
CLB
6, A
CMP
DEC
CLB
—
—
CLD
INX
—
IND, Y
ZP, X ZP, X 6, ZP
ABS, X ABS, X 6, ZP
CPX
SBC
DIV
BBS
7, A
CPX
ZP
SBC
ZP
INC
ZP
BBS
7, ZP
SBC
IMM
SEB
7, A
CPX
ABS
SBC
ABS
INC
ABS
SEB
7, ZP
NOP
—
IMM IND, X ZP, X
SBC
IND, Y
BBC
7, A
SBC
INC
BBC
SBC
ABS, Y
CLB
7, A
SBC
INC
CLB
BEQ
—
—
SED
—
ZP, X ZP, X 7, ZP
ABS, X ABS, X 7, ZP
: 3-byte instruction
: 2-byte instruction
: 1-byte instruction
38B5 Group User’s Manual
3-79
APPENDIX
3.11 Machine instructions
3.11 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
n
IMM
n
A
n
BIT,A,R
ZP
n
BIT,ZP, R
OP
#
OP
69
# OP
2
#
OP
n
# OP
65
#
2
OP
n
#
ADC
(Note 1)
(Note 5)
When T = 0
When T = 0, this instruction adds the contents
M, C, and A; and stores the results in A and C.
When T = 1, this instruction adds the contents
of M(X), M and C; and stores the results in
M(X) and C. When T=1, the contents of A re-
main unchanged, but the contents of status
flags are changed.
2
3
←
A
A + M + C
When T = 1
←
M(X)
M(X) + M + C
M(X) represents the contents of memory
where is indicated by X.
AND
(Note 1)
When T = 0
When T = 0, this instruction transfers the con-
tents of A and M to the ALU which performs a
bit-wise AND operation and stores the result
back in A.
When T = 1, this instruction transfers the con-
tents M(X) and M to the ALU which performs a
bit-wise AND operation and stores the results
back in M(X). When T = 1, the contents of A
remain unchanged, but status flags are
changed.
29
2
2
25
3
2
V
←
A
A
M
When T = 1
V
←
M(X)
M(X)
M
M(X) represents the contents of memory
where is indicated by X.
7
0
ASL
This instruction shifts the content of A or M by
one bit to the left, with bit 0 always being set to
0 and bit 7 of A or M always being contained in
C.
0A
2
1
06
5
2
←
C
←
0
BBC
(Note 4)
Ai or Mi = 0?
Ai or Mi = 1?
This instruction tests the designated bit i of M
or A and takes a branch if the bit is 0. The
branch address is specified by a relative ad-
dress. If the bit is 1, next instruction is
executed.
13
+
4
2
17
+
5
5
3
3
20i
20i
BBS
(Note 4)
This instruction tests the designated bit i of the
M or A and takes a branch if the bit is 1. The
branch address is specified by a relative ad-
dress. If the bit is 0, next instruction is
executed.
03
+
4
2
07
+
20i
20i
C = 0?
C = 1?
BCC
(Note 4)
This instruction takes a branch to the ap-
pointed address if C is 0. The branch address
is specified by a relative address. If C is 1, the
next instruction is executed.
BCS
(Note 4)
This instruction takes a branch to the ap-
pointed address if C is 1. The branch address
is specified by a relative address. If C is 0, the
next instruction is executed.
Z = 1?
BEQ
(Note 4)
This instruction takes a branch to the ap-
pointed address when Z is 1. The branch
address is specified by a relative address.
If Z is 0, the next instruction is executed.
V
A
M
BIT
This instruction takes a bit-wise logical AND of
A and M contents; however, the contents of A
and M are not modified.
24
3
2
The contents of N, V, Z are changed, but the
contents of A, M remain unchanged.
N = 1?
Z = 0?
BMI
(Note 4)
This instruction takes a branch to the ap-
pointed address when N is 1. The branch
address is specified by a relative address.
If N is 0, the next instruction is executed.
BNE
(Note 4)
This instruction takes a branch to the ap-
pointed address if Z is 0. The branch address
is specified by a relative address. If Z is 1, the
next instruction is executed.
38B5 Group User’s Manual
3-80
APPENDIX
3.11 Machine instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
OP
ABS
ABS, X
OP
7D
ABS, Y
IND
n
ZP, IND
OP
IND, X
IND, Y
REL
n
SP
n
7
6
5
T
•
4
B
•
3
D
•
2
I
1
Z
Z
0
C
C
OP
75
n
4
#
2
n
#
OP
6D
n
4
#
3
n
#
OP
79
n
#
3
OP
#
n
#
OP
61
n
6
#
2
OP
71
n
6
#
2
OP
#
OP
#
N
N
V
V
5
3
5
•
35
4
2
2D
4
3
3D
5
3
39
5
3
21
6
2
31
6
2
N
•
•
•
•
•
Z
•
16
6
2
0E
6
3
1E
7
3
N
•
•
•
•
•
•
•
•
•
•
•
Z
•
C
•
•
•
•
•
•
•
•
•
2
2
2
2
2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
90
B0
F0
•
M7 M6
Z
2C
4
3
30
2
2
2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
D0
38B5 Group User’s Manual
3-81
APPENDIX
3.11 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
n
IMM
n
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP n #
OP
#
OP
# OP
#
n
# OP
#
BPL
(Note 4)
N = 0?
This instruction takes a branch to the ap-
pointed address if N is 0. The branch address
is specified by a relative address. If N is 1, the
next instruction is executed.
←
BRA
BRK
PC
PC ± offset
This instruction branches to the appointed ad-
dress. The branch address is specified by a
relative address.
←
B
1
When the BRK instruction is executed, the
CPU pushes the current PC contents onto the
stack. The BADRS designated in the interrupt
vector table is stored into the PC.
00
7
1
←
←
(PC)
M(S)
(PC) + 2
PCH
←
S
S – 1
←
PCL
S – 1
M(S)
←
S
←
PS
S – 1
M(S)
←
S
←
I
1
←
←
PCL
PCH
ADL
ADH
BVC
(Note 4)
V = 0?
V = 1?
Ai or Mi
This instruction takes a branch to the ap-
pointed address if V is 0. The branch address
is specified by a relative address. If V is 1, the
next instruction is executed.
BVS
(Note 4)
This instruction takes a branch to the ap-
pointed address when V is 1. The branch
address is specified by a relative address.
When V is 0, the next instruction is executed.
1B
+
2
1
1F
+
5
2
←
CLB
CLC
CLD
CLI
0
This instruction clears the designated bit i of A
or M.
20i
20i
18
D8
58
12
B8
2
2
2
2
2
1
1
1
1
1
←
←
C
D
0
0
This instruction clears C.
This instruction clears D.
This instruction clears I.
This instruction clears T.
This instruction clears V.
←
I
0
←
←
CLT
CLV
T
V
0
0
C9
2
2
C5
3
2
CMP
(Note 3)
When T = 0
A – M
When T = 1
M(X) – M
When T = 0, this instruction subtracts the con-
tents of M from the contents of A. The result is
not stored and the contents of A or M are not
modified.
When T = 1, the CMP subtracts the contents
of M from the contents of M(X). The result is
not stored and the contents of X, M, and A are
not modified.
M(X) represents the contents of memory
where is indicated by X.
__
44
E4
5
3
2
2
←
COM
CPX
M
M
This instruction takes the one’s complement of
the contents of M and stores the result in M.
E0
C0
2
2
2
X – M
Y – M
This instruction subtracts the contents of M
from the contents of X. The result is not stored
and the contents of X and M are not modified.
2
C4
C6
3
5
2
2
CPY
DEC
This instruction subtracts the contents of M
from the contents of Y. The result is not stored
and the contents of Y and M are not modified.
1A
2
1
←
←
A
M
A – 1 or
M – 1
This instruction subtracts 1 from the contents
of A or M.
38B5 Group User’s Manual
3-82
APPENDIX
3.11 Machine instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
OP
ABS
n
ABS, X
OP
ABS, Y
OP #
IND
n
ZP, IND
OP
IND, X
OP n #
IND, Y
OP n #
REL
n
SP
n
7
N
•
6
V
•
5
T
•
4
B
•
3
D
•
2
I
1
Z
•
0
C
•
OP
n
#
n
#
OP
#
n
#
n
OP
#
n
#
OP
10
#
2
OP
#
2
•
80
4
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
50
70
2
2
2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
0
•
•
•
•
•
•
0
•
•
•
•
•
0
•
•
•
•
•
0
•
•
•
•
•
D5
4
2
CD
4
3
DD
5
3
D9
5
3
C1
6
2
D1
6
2
N
•
•
•
Z
C
N
N
•
•
•
•
•
•
•
•
•
•
Z
Z
•
EC
CC
CE
4
4
6
3
3
3
C
N
N
•
•
•
•
•
•
•
•
•
•
Z
Z
C
•
D6
6
2
DE
7
3
38B5 Group User’s Manual
3-83
APPENDIX
3.11 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
IMM
n
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP #
OP
CA
n
2
#
1
OP
# OP
#
n
# OP
#
n
←
←
←
DEX
DEY
DIV
X
Y
A
X – 1
This instruction subtracts one from the current
contents of X.
88
2
1
Y – 1
This instruction subtracts one from the current
contents of Y.
(M(zz + X + 1),
M(zz + X )) / A
This instruction divides the 16-bit data in
M(zz+(X)) (low-order byte) and M(zz+(X)+1)
(high-order byte) by the contents of A. The
quotient is stored in A and the one's comple-
ment of the remainder is pushed onto the stack.
←
M(S)
one's comple-
ment of Remainder
←
S
S – 1
49
2
2
45
3
2
EOR
(Note 1)
When T = 0
When T = 0, this instruction transfers the con-
tents of the M and A to the ALU which
performs a bit-wise Exclusive OR, and stores
the result in A.
When T = 1, the contents of M(X) and M are
transferred to the ALU, which performs a bit-
wise Exclusive OR and stores the results in
M(X). The contents of A remain unchanged,
but status flags are changed.
–
←
A
A V M
When T = 1
–
←
M(X)
M(X) V M
M(X) represents the contents of memory
where is indicated by X.
E6
5
2
←
←
3A
INC
INX
A
M
A + 1 or
M + 1
This instruction adds one to the contents of A
or M.
2
1
←
←
E8
C8
2
2
1
1
X
Y
X + 1
Y + 1
This instruction adds one to the contents of X.
This instruction adds one to the contents of Y.
INY
JMP
If addressing mode is ABS
This instruction jumps to the address desig-
nated by the following three addressing
modes:
←
←
PCL
PCH
ADL
ADH
If addressing mode is IND
Absolute
←
←
PCL
PC
M (ADH, ADL)
M (AD , AD + 1)
Indirect Absolute
Zero Page Indirect Absolute
H
H
L
If addressing mode is ZP, IND
←
←
PCL
PCH
M(00, ADL)
M(00, ADL + 1)
←
JSR
M(S)
PCH
S – 1
This instruction stores the contents of the PC
in the stack, then jumps to the address desig-
nated by the following addressing modes:
Absolute
←
S
←
PCL
S – 1
M(S)
←
S
After executing the above,
if addressing mode is ABS,
Special Page
Zero Page Indirect Absolute
←
←
PCL
PCH
ADL
ADH
if addressing mode is SP,
←
←
PCL
PCH
ADL
FF
If addressing mode is ZP, IND,
←
←
PCL
PCH
M(00, ADL)
M(00, ADL + 1)
A9
2
2
A5
3C
3
4
2
3
LDA
(Note 2)
When T = 0
When T = 0, this instruction transfers the con-
tents of M to A.
←
A
M
When T = 1
When T = 1, this instruction transfers the con-
tents of M to (M(X)). The contents of A remain
unchanged, but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
←
M(X)
M
←
LDM
M
nn
This instruction loads the immediate value in
M.
←
←
A2
A0
2
2
2
2
A6
A4
3
3
2
2
LDX
LDY
X
Y
M
This instruction loads the contents of M in X.
This instruction loads the contents of M in Y.
M
38B5 Group User’s Manual
3-84
APPENDIX
3.11 Machine instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
OP n
ABS
n
ABS, X
OP
ABS, Y
OP n #
IND
n
ZP, IND
IND, X
OP n #
IND, Y
OP n #
REL
n
SP
n
7
6
5
4
3
2
1
0
OP
n
#
#
OP
#
n
#
OP
#
OP
n
#
OP
#
OP
#
N
N
V
•
T
•
B
•
D
•
I
Z
Z
C
•
•
N
•
•
•
•
•
•
•
•
•
•
•
Z
•
•
•
E2 16
2
2
55
4
4D
4
3
5D
5
3
59
5
3
41
6
2
51
6
2
N
•
•
•
•
•
Z
•
F6
6
2
EE
4C
6
3
3
FE
7
3
N
N
•
•
•
•
•
•
•
•
•
•
Z
Z
•
•
N
•
•
•
•
•
•
•
•
•
•
•
Z
•
•
•
3
6C
5
3
B2
4
2
20
6
3
02
7
2
22
5
2
•
•
•
•
•
•
•
•
B5
4
2
AD
4
3
BD
5
3
B9
5
3
A1
6
2
B1
6
2
N
•
•
•
•
•
•
•
•
•
•
Z
•
•
•
•
B6
4
2
AE
AC
4
4
3
3
BE
5
3
N
N
•
•
•
•
•
•
•
•
•
•
Z
Z
•
•
B4
4
2
BC
5
3
38B5 Group User’s Manual
3-85
APPENDIX
3.11 Machine instructions
Addressing mode
Symbol
LSR
Function
Details
IMP
n
IMM
n
A
n
2
BIT, A
OP
ZP
n
BIT, ZP
OP #
OP
#
OP
# OP
4A
#
1
n
# OP
46
#
n
This instruction shifts either A or M one bit to
the right such that bit 7 of the result always is
set to 0, and the bit 0 is stored in C.
5
2
7
0
→
C
→
0
←
M(S) • A A ✽M(zz + X) This instruction multiply Accumulator with the
MUL
←
S
S – 1
memory specified by the Zero Page X address
mode and stores the high-order byte of the re-
sult on the Stack and the low-order byte in A.
←
NOP
PC
PC + 1
This instruction adds one to the PC but does EA
no otheroperation.
2
1
09
2
2
ORA
(Note 1)
When T = 0
When T = 0, this instruction transfers the con-
tents of A and M to the ALU which performs a
bit-wise “OR”, and stores the result in A.
When T = 1, this instruction transfers the con-
tents of M(X) and the M to the ALU which
performs a bit-wise OR, and stores the result
in M(X). The contents of A remain unchanged,
but status flags are changed.
05
3
2
←
A
A V M
When T = 1
←
M(X)
M(X) V M
M(X) represents the contents of memory
where is indicated by X.
←
S – 1
PHA
PHP
PLA
PLP
ROL
M(S)
A
This instruction pushes the contents of A to
the memory location designated by S, and
decrements the contents of S by one.
48
3
3
4
4
1
1
1
1
←
S
←
S – 1
M(S)
PS
This instruction pushes the contents of PS to
the memory location designated by S and dec-
rements the contents of S by one.
08
←
S
←
←
S
A
S + 1
M(S)
This instruction increments S by one and
stores the contents of the memory designated
by S in A.
68
←
S
S + 1
This instruction increments S by one and
stores the contents of the memory location
designated by S in PS.
←
28
PS
M(S)
This instruction shifts either A or M one bit left
through C. C is stored in bit 0 and bit 7 is
stored in C.
2A
6A
2
2
1
1
26
66
82
5
5
8
2
2
2
7
←
0
←
←
C
ROR
This instruction shifts either A or M one bit
right through C. C is stored in bit 7 and bit 0 is
stored in C.
7
→
0
→
C
RRF
RTI
This instruction rotates 4 bits of the M content
to the right.
7
0
→
→
←
S
S + 1
This instruction increments S by one, and
stores the contents of the memory location
designated by S in PS. S is again incremented
by one and stores the contents of the memory
location designated by S in PCL. S is again
incremented by one and stores the contents of
memory location designated by S in PCH.
←
40
60
6
6
1
1
PS
M(S)
S + 1
M(S)
S + 1
←
PCL
←
PCH
S
←
S
←
M(S)
←
PCL
←
RTS
S
S + 1
←
This instruction increments S by one and
stores the contents of the memory location
designated by S in PCL. S is again
M(S)
S + 1
S
←
←
PCH
(PC)
M(S)
(PC) + 1
incremented by one and the contents of the
memory location is stored in PCH. PC is
incremented by 1.
38B5 Group User’s Manual
3-86
APPENDIX
3.11 Machine instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
OP
ABS
ABS, X
OP
5E
ABS, Y
OP #
IND
n
ZP, IND
OP
IND, X
OP n #
IND, Y
OP n #
REL
n
SP
n
7
N
0
6
V
•
5
T
•
4
B
•
3
D
•
2
I
1
Z
Z
0
C
C
OP
56
n
6
#
2
n
#
OP
4E
n
6
#
3
n
#
n
OP
#
n
#
OP
#
OP
#
7
3
•
62 15
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
01
6
2
11
6
2
15
4
2
0D
4
3
1D
5
3
5
3
N
Z
19
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
Z
(Value saved in stack)
N
N
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Z
Z
•
C
C
•
36
76
6
6
2
2
2E
6E
6
6
3
3
3E
7E
7
7
3
3
(Value saved in stack)
•
•
•
•
•
•
•
•
38B5 Group User’s Manual
3-87
APPENDIX
3.11 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
n
IMM
n
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP n #
OP
#
OP
E9
# OP
2
#
n
# OP
E5
#
2
SBC
(Note 1)
(Note 5)
When T = 0
When T = 0, this instruction subtracts the
value of M and the complement of C from A,
and stores the results in A and C.
When T = 1, the instruction subtracts the con-
tents of M and the complement of C from the
contents of M(X), and stores the results in
M(X) and C.
2
3
_
←
A
A – M – C
When T = 1
_
←
M(X)
M(X) – M – C
A remain unchanged, but status flag are
changed.
M(X) represents the contents of memory
where is indicated by X.
←
SEB
SEC
SED
SEI
Ai or Mi
1
This instruction sets the designated bit i of A
or M.
0B
+
2
1
0F
+
5
2
20i
20i
←
←
C
D
1
1
This instruction sets C.
This instruction set D.
This instruction set I.
This instruction set T.
38
F8
78
32
2
2
2
2
1
1
1
1
←
I
1
←
←
SET
STA
STP
T
M
1
A
This instruction stores the contents of A in M.
The contents of A does not change.
85
4
2
This instruction resets the oscillation control F/ 42
F and the oscillation stops. Reset or interrupt
input is needed to wake up from this mode.
2
1
←
←
←
←
STX
STY
TAX
TAY
TST
TSX
TXA
TXS
TYA
WIT
M
M
X
X
Y
This instruction stores the contents of X in M.
The contents of X does not change.
86
84
4
4
2
2
This instruction stores the contents of Y in M.
The contents of Y does not change.
A
This instruction stores the contents of A in X. AA
The contents of A does not change.
2
2
1
1
Y
A
This instruction stores the contents of A in Y. A8
The contents of A does not change.
M = 0?
This instruction tests whether the contents of
M are “0” or not and modifies the N and Z.
64
3
2
←
←
←
←
X
A
S
A
S
X
X
Y
This instruction transfers the contents of S in BA
X.
2
2
2
2
2
1
1
1
1
1
This instruction stores the contents of X in A.
This instruction stores the contents of X in S.
This instruction stores the contents of Y in A.
8A
9A
98
The WIT instruction stops the internal clock C2
but not the oscillation of the oscillation circuit
is not stopped.
CPU starts its function after the Timer X over
flows (comes to the terminal count). All regis-
ters or internal memory contents except Timer
X will not change during this mode. (Of course
needs VDD).
Notes 1 : The number of cycles “n” is increased by 3 when T is 1.
2 : The number of cycles “n” is increased by 2 when T is 1.
3 : The number of cycles “n” is increased by 1 when T is 1.
4 : The number of cycles “n” is increased by 2 when branching has occurred.
5 : N, V, and Z flags are invalid in decimal operation mode.
38B5 Group User’s Manual
3-88
APPENDIX
3.11 Machine instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
OP n
ABS
ABS, X
OP
FD
ABS, Y
IND
n
ZP, IND
OP
IND, X
IND, Y
REL
n
SP
n
7
6
5
T
•
4
B
•
3
D
•
2
I
1
Z
Z
0
C
C
OP
n
4
#
2
#
OP
ED
n
4
#
3
n
#
OP
F9
n
#
3
OP
#
n
#
OP
E1
n
6
#
2
OP
F1
n
6
#
2
OP
#
OP
#
N
N
V
V
F5
5
3
5
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
•
•
1
•
•
•
1
•
•
1
•
•
•
95
5
2
8D
5
3
9D
6
3
99
6
3
81
7
2
91
7
2
•
•
•
•
•
•
•
96
5
2
8E
8C
5
5
3
3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
94
5
2
•
•
N
N
N
N
N
•
Z
Z
Z
Z
Z
•
N
•
Z
•
38B5 Group User’s Manual
3-89
APPENDIX
3.11 Machine instructions
Symbol
Contents
Symbol
Contents
IMP
IMM
A
BIT, A
BIT, A, R
ZP
BIT, ZP
BIT, ZP, R
ZP, X
Implied addressing mode
Immediate addressing mode
+
–
✽
Addition
Subtraction
Multiplication
Division
Logical OR
Logical AND
Logical exclusive OR
Negation
Shows direction of data flow
Index register X
Index register Y
Accumulator or Accumulator addressing mode
Accumulator bit addressing mode
Accumulator bit relative addressing mode
Zero page addressing mode
Zero page bit addressing mode
Zero page bit relative addressing mode
Zero page X addressing mode
Zero page Y addressing mode
Absolute addressing mode
/
V
V
–
V
–
←
X
Y
ZP, Y
ABS
ABS, X
ABS, Y
IND
Absolute X addressing mode
Absolute Y addressing mode
Indirect absolute addressing mode
S
Stack pointer
Program counter
PC
PS
PCH
PCL
ADH
ADL
FF
nn
Processor status register
8 high-order bits of program counter
8 low-order bits of program counter
8 high-order bits of address
8 low-order bits of address
FF in Hexadecimal notation
Immediate value
Zero page address
Memory specified by address designation of any ad-
dressing mode
ZP, IND
Zero page indirect absolute addressing mode
IND, X
IND, Y
REL
SP
C
Indirect X addressing mode
Indirect Y addressing mode
Relative addressing mode
Special page addressing mode
Carry flag
zz
M
Z
Zero flag
I
D
B
T
V
N
Interrupt disable flag
Decimal mode flag
Break flag
X-modified arithmetic mode flag
Overflow flag
M(X)
M(S)
Memory of address indicated by contents of index
register X
Memory of address indicated by contents of stack
pointer
Contents of memory at address indicated by ADH and
ADL, in ADH is 8 high-order bits and ADL is 8 low-or-
der bits.
M(ADH, ADL)
Negative flag
M(00, ADL)
Contents of address indicated by zero page ADL
Bit i (i = 0 to 7) of accumulator
Bit i (i = 0 to 7) of memory
Opcode
Ai
Mi
OP
n
Number of cycles
#
Number of bytes
38B5 Group User's Manual
3-90
APPENDIX
3.12 M35501FP
3.12 M35501FP
DESCRIPTION
FEATURES
The M35501FP generates digit signals for fluorescent display
when connected to the output port of a microcomputer. There are
up to 16 digit pins available, and more can be added by connect-
ing additional M35501FPs. The number of fluorescent displays
can be increased easily by connecting the M35501FP to the
CMOS FLD output pins of an 8-bit microcomputer in
MITSUBISHI’s 38B5 Group. The M35501FP is suitable for fluores-
cent display control on household electric appliances, audio
products, etc.
●Digit output............................................................. 16 (maximum)
•Up to 16 pins can be selected
•More digits available by connecting additional M35501FPs
•Output structure: high-breakdown voltage, P-channel open-
drain; built-in pull-down resistor between digit output pins and
VEE pin
●Power-on reset circuit........................................................ Built-in
●Power source voltage ................................................ 4.0 to 5.5 V
●Pull-down power source voltage ................................ Vcc – 43 V
●Operating temperature range ...................................–20 to 85 °C
●Package ............................................................................. 24P2E
●Power dissipation ..............250 µW (at 100 kHz operation clock)
PIN CONFIGURATION (TOP VIEW)
14
24 23 22 21 20 19 18 17 16 15
13
M35501FP
1
2
3
4
5
6
7
8
9
10 11 12
Outline: 24P2E-A
24-pin plastic-molded SSOP
Fig. 3.12.1 Pin configuration of M35501FP
38B5 Group User’s Manual
3-91
APPENDIX
3.12 M35501FP
FUNCTIONAL BLOCK
DIG15 DIG14 DIG13 DIG12 DIG11 DIG10 DIG
9
DIG
15
8
DIG
16
7
DIG
17
6
DIG
5
DIG
4
DIG
20
3
DIG
21
2
DIG
1 DIG0
8
14
10
9
13
18 19
11
22 23
12
V
EE
24
OVFOUT
OVFIN
7
6
Shift register
3
V
CC
V
SS
1
4
Optional digit
counter
Power-on
reset
RESET
5
2
CLK SEL
Fig. 3.12.2 Functional block diagram
PIN DESCRIPTION
Table 3.12.1 Pin description
Function
Apply 4.0–5.5 V to Vcc, and 0V to Vss.
Output Structure
–
Fig. No.
Pin
Name
Power source input
Reset input
–
3
VCC, VSS
RESET
Reset internal shift register (built-in power-on reset CMOS input level
circuit). Built-in pull-up resistor
Digit output varies according to rising edge of clock CMOS input level
2
2
4
CLK
Clock input
input.
Built-in pull-down resistor
Use when specifying the number of digits.
CMOS input level
Built-in pull-down resistor
SEL
Select input
Input “H” when using one M35501FP. Connect to
OVFOUT pin of additional M35501FPs when using
multiple M35501FPs (to use 17 digits or more).
CMOS input level
OVFIN
Overflow signal input
Leave open when using one M35501FP. Connect to
OVFIN pin of additional M35501FPs when using multiple
M35501FPs (to use 17 digits or more).
CMOS output
5
1
–
OVFOUT
Overflow signal output
Digit output
Output the digit output waveform of fluorescent
display. Leave open when not in use (VEE level
output).
High-breakdown-voltage
P-channel open-drain output
Built-in pull-down resistor
DIG15–
DIG0
Apply voltage to DIG0–DIG15 pull-down resistors.
–
VEE
Pull-down power source input
38B5 Group User’s Manual
3-92
APPENDIX
3.12 M35501FP
PORT BLOCK
(1) DIG0–DIG15
(2) SEL, CLK
Shift register
Pull-down transistor
VEE
(3) RESET
(4) OVFIN
Pull-up transistor
(5) OVFOUT
Shift register
Fig. 3.12.3 Port block diagram
38B5 Group User’s Manual
3-93
APPENDIX
3.12 M35501FP
USAGE
Three usages of the M35501FP are described below.
(1) 16-Digit Mode: 16 digits selected
The number of digits is set to 16 by fixing the OVFIN pin to “H” and
the SEL pin to “L.” Figure 3.12.5 shows the output waveform.
(2) Optional Digit Mode: 1-16 digits selectable
When the number of CLK pin rising edges during an “H” period of
the SEL pin is n and the OVFIN pin is fixed to “H,” the number of
digits set is n. If n is 16 or more, all 16 digits are set. Figure 3.12.6
shows the output waveform.
SEL pin
n
CLK pin
Fig. 3.12.4 Digit setting
(3) Cascade Mode: 17 digits or more selectable
17 digits or more can be used by connecting two M35501FPs or
more. Figure 3.12.7 shows an example using three M35501FPs, of-
fering 33 to 48 digit outputs.
Cascade mode will not operate if all M35501FPs are in 16-digit
mode (SEL = “L”). Use the most significant M35501FP in the optional
digit mode for DIG output. Figure 3.12.8 shows the output waveform.
38B5 Group User’s Manual
3-94
APPENDIX
3.12 M35501FP
DIGIT OUTPUT WAVEFORM
SEL
“L”
CLK
DIG0
DIG1
DIG2
DIG13
DIG14
DIG15
OVFOUT
Fig. 3.12.5 16-digit mode output waveform
RESET
SEL
CLK
DIG0
DIG1
DIG2
DIG3
“L”
DIG4
DIG15
“L”
OVFOUT
Fig. 3.12.6 Optional digit mode output waveform
38B5 Group User’s Manual
3-95
APPENDIX
3.12 M35501FP
OVFIN(1)
RESET
DIG0
DIG1
RESET
CLK
SEL
CLK
DIG14
DIG15
Select signal
OVFOUT(1)
OVFIN(2)
DIG16
DIG17
RESET
CLK
DIG30
DIG31
SEL
OVFOUT(2)
OVFIN(3)
RESET
DIG32
DIG33
CLK
SEL
DIG46
DIG47
OVFOUT(3)
Fig. 3.12.7 Cascade mode connection example: 17 digits or more selected
CLK
RESET
DIG0
DIG1
DIG2
DIG15
OVFOUT(1)
DIG16
DIG17
DIG31
OVFOUT(2)
Fig. 3.12.8 Cascade mode output waveform
38B5 Group User’s Manual
3-96
APPENDIX
3.12 M35501FP
The number of fluorescent displays can be increased by connecting
the M35501FP to the CMOS FLD output pins on a 38B5 Group mi-
crocomputer.
Segment (high-breakdown-voltage: 36 pins + CMOS: 4 pins)
(1 pin used as CLK.)
P27–P20
P07–P00
P17–P10
P37–P30
P83–P80
Fluorescent Display (FLD)
Fluorescent Display (FLD)
M38B5X
P84
SEL
Digits
DIG0–DIG15
M35501
CLK
Fig. 3.12.9 Connection example with 38B5 Group microcomputer (1 to 16 digits)
This FLD controller can control up to 32 digits using the 32 timing
mode of the 38B5 Group microcomputer.
Segment (high-breakdown-voltage: 36 pins + CMOS: 4 pins)
(1 pin is used as CLK.)
P27–P20
P07–P00
M38B5X
Fluorescent Display (FLD)
Fluorescent Display (FLD)
P17–P10
P37–P30
P83–P80
P84
SELM35501
CLK
Digits
DIG0–DIG15
OVFOUT
OVFIN
OVFIN
SEL
OVFOUT
Digits
DIG16–DIG31
M35501
CLK
Fig. 3.12.10 Connection example with 38B5 Group microcomputer (17 to 32 digits)
38B5 Group User’s Manual
3-97
APPENDIX
3.12 M35501FP
Notes1: Perform the reset release when CLK input signal is “L.”
2: When setting the number of digits by SEL signal, optional digit
counter is set to “0” by reset.
RESET CIRCUIT
To reset the controller, the RESET pin should be held at “L” for 2
µs or more. Reset is released when the RESET pin is returned to
“H” and the power source voltage is between 4.0 V and 5.5 V.
RESET
CLK
DIG0
DIG1
DIG2
DIG3
Fig. 3.12.11 Digit output waveform when reset signal is input
38B5 Group User’s Manual
3-98
APPENDIX
3.12 M35501FP
POWER-ON RESET
If the rising time exceeds 100 µs, connect the capacitor between
the RESET pin and VSS at the shortest distance. Consequently,
the RESET pin should be held at “L” until the minimum operation
guaranteed voltage is reached.
Reset can be performed automatically during power on (power-on
reset) by the built-in power-on reset circuit. When using this cir-
cuit, set 100 µs or less for the period in which it takes to reach
minimum operation guaranteed voltage from reset.
VDD
Pull-up transistor
Power-on reset circuit
output voltage
RESET
pin
Power-on reset
circuit
Reset state
(Note)
Internal reset signal
Note:
This symbol represents a parasitic diode.
Applied voltage to the RESET pin must be VDD or less.
Reset released
Power-on
Fig. 3.12.12 Power-on reset circuit
38B5 Group User’s Manual
3-99
APPENDIX
3.12 M35501FP
Table 3.12.2 Absolute maximum ratings
Symbol
Parameter
Ratings
Unit
Conditions
VCC
Power source voltage
•All voltages are based on VSS.
•Output transistors are off.
–0.3 to 7.0
VCC –45 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VCC +0.3
VCC –45 to VCC +0.3
–0.3 to VCC +0.3
250
V
V
VEE
VI
Pull-down power source voltage
Input voltage CLK, SEL, OVFIN
Input voltage RESET
V
VI
V
VO
VO
Pd
Output voltage DIG0–DIG15
Output voltage OVFOUT
Power dissipation
V
V
mW
°C
°C
Ta = 25 °C
Topr
Tstg
Operating temperature
Storage temperature
–20 to 85
–40 to 125
Table 3.12.3 Recommended operating conditions (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
4.0
Typ.
5.0
0
Max.
5.5
VCC
Power source voltage
V
V
V
V
V
V
V
VSS
VEE
VIH
VIH
VIL
Power source voltage
Pull-down power source voltage
VCC –43
0.8VCC
0.8VCC
0
VSS
VCC
“H” input voltage CLK, SEL, OVFIN
“H” input voltage RESET
VCC
“L” input voltage CLK, SEL, OVFIN
“L” input voltage RESET
0.2VCC
0.2VCC
VIL
0
Table 3.12.4 Recommended operating conditions (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Max.
–36
–10
10
Typ.
IOH(peak)
IOH(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
CLK
“H” peak output current DIG0 – DIG15 (Note 1)
“H” peak output current OVFOUT (Note 1)
“L” peak output current OVFOUT (Note 1)
“H” average current DIG0 – DIG15 (Note 2)
“H” average current OVFOUT (Note 2)
“L” average current OVFOUT (Note 2)
Clock input frequency
mA
mA
mA
mA
mA
mA
MHz
–18
–5.0
5.0
2
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current is an average value measured over 100 ms.
38B5 Group User’s Manual
3-100
APPENDIX
3.12 M35501FP
Table 3.12.5 Electrical characteristics (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
DIG output
Test conditions
IOH = –18 mA
Unit
V
Min.
Typ.
Max.
2.0
VOH
“H” output voltage
VCC –2.0
DIG0–DIG15
OVFOUT
OVFOUT
CLK, OVFIN
RESET
VOH
“H” output voltage
“L” output voltage
Hysteresis
IOH = –10 mA
IOL = 10 mA
VCC = 5.0 V
VCC –2.0
V
V
V
VOL
VT+ — VT–
0.4
70
IIH
“H” input current
“H” input current
“L” input current
“L” input current
Output load current
OVFIN
VI = VCC
5.0
140
µA
µA
µA
µA
µA
RESET
IIH
CLK, SEL
VI = VCC
30
VCC = 5.0 V
VI = VSS
IIL
OVFIN
–5.0
–185
800
CLK, SEL
RESET
IIL
VI = VSS
–60
500
–130
650
VCC = 5.0 V
ILOAD
DIG0 – DIG15
DIG0–DIG15
VEE = VCC –43 V
VOL = VCC
Output transistors are off.
VEE = VCC –43 V
VOL = VCC –43 V
Output transistors are off.
ILEAK
ICC
Output leakage current
Power source
–10
µA
µA
50
VCC = 5.0 V, CLK = 100 kHz
Output transistors are off.
38B5 Group User’s Manual
3-101
APPENDIX
3.12 M35501FP
Table 3.12.6 Timing requirements (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Max.
Min.
2
tw(RESET)
tc(CLK)
Reset input “L” pulse width
Clock input cycle time
µs
ns
ns
ns
ns
ns
ns
500
200
200
500
500
500
twH(CLK)
twL(CLK)
tsu(SEL)
th(SEL)
Clock input “H” pulse width
Clock input “L” pulse width
Select input setup time
Select input hold time
th(CLK)
Clock input setup time
tw(RESET)
tc(CLK)
vcc
0.8VCC
RESET
vss
0.2VCC
twL(CLK)
twH(CLK)
vcc
vss
0.8VCC
CLK
0.2VCC
vcc
vss
vcc
vss
SEL
CLK
tsu(SEL)
th(SEL)
th(CLK)
Fig. 3.12.13 Timing diagram
38B5 Group User’s Manual
3-102
APPENDIX
3.13 SFR memory map
3.13 SFR memory map
000016 Port P0 (P0)
002016 Timer 1 (T1)
Port P0 direction register (P0D)
Port P1 (P1)
Timer 2 (T2)
Timer 3 (T3)
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
002116
002216
002316 Timer 4 (T4)
002416 Timer 5 (T5)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Timer 6 (T6)
002516
002616 PWM control register (PWMCON)
002716 Timer 6 PWM register (T6PWM)
002816 Timer 12 mode register (T12M)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Timer 34 mode register (T34M)
Timer 56 mode register (T56M)
002916
002A16
Port P5 direction register (P5D)
Port P6 (P6)
002B16 Watchdog timer control register (WDTCON)
002C16 Timer X (low-order) (TXL)
Port P6 direction register (P6D)
Port P7 (P7)
002D16 Timer X (high-order) (TXH)
002E16 Timer X mode register 1 (TXM1)
002F16 Timer X mode register 2 (TXM2)
003016 Interrupt interval determination register (IID)
Port P7 direction register (P7D)
Port P8 (P8)
Port P8 direction register (P8D)
Interrupt interval determination control register (IIDCON)
003116
001216 Port P9 (P9)
003216 A-D control register (ADCON)
001316 Port P9 direction register (P9D)
003316 A-D conversion register (low-order) (ADL)
PWM register (high-order) (PWMH)
PWM register (low-order) (PWM L)
Baud rate generator (BRG)
001416
001516
001616
001716
001816
001916
003416 A-D conversion register (high-order) (ADH)
003516
003616
003716
003816
UART control register (UARTCON)
Serial I/O1 automatic transfer data pointer (SIO1DP)
Serial I/O1 control register 1 (SIO1CON1)
Interrupt source switch register (IFR)
003916
001A16 Serial I/O1 control register 2 (SIO1CON2)
001B16 Serial I/O1 register/Transfer counter (SIO1)
003A16 Interrupt edge selection register (INTEDGE)
003B16 CPU mode register (CPUM)
Serial I/O1 control register 3 (SIO1CON3)
Serial I/O2 control register (SIO2CON)
Interrupt request register 1(IREQ1)
Interrupt request register 2(IREQ2)
001C16
001D16
003C16
003D16
001E16 Serial I/O2 status register (SIO2STS)
003E16 Interrupt control register 1(ICON1)
003F16 Interrupt control register 2(ICON2)
Serial I/O2 transmit/receive buffer register (TB/RB)
001F16
Pull-up control register 1 (PULL1)
Pull-up control register 2 (PULL2)
P1FLDRAM write disable register (P1FLDRAM)
P3FLDRAM write disable register (P3FLDRAM)
FLDC mode register (FLDM)
FLD data pointer (FLDDP)
0EF016
0EF116
0EF216
0EF316
0EF416
0EF816
0EF916
Port P0FLD/port switch register (P0FPR)
0EFA16 Port P2FLD/port switch register (P2FPR)
0EFB16 Port P8FLD/port switch register (P8FPR)
Port P8FLD output control register (P8FLDCON)
0EFC16
0EF516 Tdisp time set register (TDISP)
0EF616 Toff1 time set register (TOFF1)
0EF716 Toff2 time set register (TOFF2)
0EFD16 Buzzer output control register (BUZCON)
0EFE16
0EFF16
38B5 Group User’s Manual
3-103
APPENDIX
3.14 Pin configuration
3.14 Pin configuration
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P3
P3
P3
P3
P3
P3
P3
P3
P8
P8
P8
P8
0
1
2
3
4
5
6
7
0
1
2
3
/FLD24
/FLD25
/FLD26
/FLD27
/FLD28
/FLD29
/FLD30
/FLD31
/FLD32
/FLD33
/FLD34
/FLD35
P5
7
/SRDY2/
SCLK22
P5
P5
P5
6
/SCLK21
5
/TxD
4
/RxD
P5
3
/SCLK12
/SCLK11
P52
P51
/SOUT1
/SIN1
AVSS
REF
/SSTB1/AN11
/SBUSY1/AN10
P5
0
M38B5xMxH-XXXXFP
V
P6
/INT
5
P64
4
VEE
P6
3
/AN
9
8
7
6
P84
P85
P86
/FLD36
P6
2/SRDY1/AN
/RTP
/RTP
0
/FLD37
/FLD38
P7
P7
7
6
/AN
/AN
1
Note: In the mask option type P, INT3 and CNTR1 cannot be used.
(Top view)
Package type: 80P6N-A
80-pin plastic molded QFP
38B5 Group User’s Manual
3-104
MITSUBISHI SEMICONDUCTORS
USER’S MANUAL
38B5 Group
Nov. First Edition 1998
Editioned by
Committee of editing of Mitsubishi Semiconductor USER’S MANUAL
Published by
Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission
of Mitsubishi Electric Corporation.
©1998 MITSUBISHI ELECTRIC CORPORATION
User’s Manual
38B5 Group
New publication, effective Nov. 1998.
© 1998 MITSUBISHI ELECTRIC CORPORATION.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
38B5 Group User’s Manual
Rev.
Rev.
date
Revision Description
No.
1.0 First Edition
981202
(1/1)
相关型号：
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