M38B53M5XXXFS [RENESAS]
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER; 单片8位CMOS微机
| 型号： | M38B53M5XXXFS |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 文件： | 总70页 (文件大小：905K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PWM .............................................................................14-bit ✕ 1
8-bit ✕ 1 (also functions as timer 6)
DESCRIPTION
The 38B5 group is the 8-bit microcomputer based on the 740 family
•
core technology.
A-D converter .............................................. 10-bit ✕ 12 channels
Fluorescent display function ........................ Total 40 control pins
Interrupt interval determination function ..................................... 1
Watchdog timer ............................................................. 20-bit ✕ 1
Buzzer output ............................................................................. 1
2 Clock generating circuit
•
•
•
•
•
•
The 38B5 group has six 8-bit timers, a 16-bit timer, a fluorescent
display automatic display circuit, 12-channel 10-bit A-D converter, a
serial I/O with automatic transfer function, which are available for
controlling musical instruments and household appliances.
The 38B5 group has variations of internal memory size and packag-
ing. For details, refer to the section on part numbering.
For details on availability of microcomputers in the 38B5 group, refer
to the section on group expansion.
Main clock (XIN–XOUT) ......................... Internal feedback resistor
Sub-clock (XCIN–XCOUT) ......... Without internal feedback resistor
(connect to external ceramic resonator or quartz-crystal oscillator)
Power source voltage
•
In high-speed mode ................................................... 4.0 to 5.5 V
(at 4.19 MHz oscillation frequency and high-speed selected)
In middle-speed mode ............................................... 2.7 to 5.5 V
(at 4.19 MHz oscillation frequency and middle-speed selected)
In low-speed mode .................................................... 2.7 to 5.5 V
(at 32 kHz oscillation frequency and low-speed selected)
Power dissipation
FEATURES
Basic machine-language instructions ....................................... 71
•
•
The minimum instruction execution time .......................... 0.48 µs
(at 4.19 MHz oscillation frequency)
Memory size
•
ROM............................................. 24K to 60K bytes
RAM ............................................ 512 to 2048 bytes
•
•
In high-speed mode .......................................................... 35 mW
(at 4.19 MHz oscillation frequency)
Programmable input/output ports ............................................. 55
•
In low-speed mode ............................................................ 60 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
Operating temperature range ................................... –20 to 85 °C
High-breakdown-voltage output ports....................................... 36
•
Software pull-up resistors ...... (Ports P5, P61 to P65, P7, P84 to P87, P9)
•
Interrupts .................................................. 21 sources, 16 vectors
•
Timers ........................................................... 8-bit ✕ 6, 16-bit ✕ 1
•
APPLICATION
Musical instruments, VCR, household appliances, etc.
Serial I/O1 (Clock-synchronized) .................................... 8-bit ✕ 1
•
...................... (max. 256-byte automatic transfer function)
Serial I/O2 (UART or Clock-synchronized) ..................... 8-bit ✕ 1
•
PIN CONFIGURATION (TOP VIEW)
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P3
P3
P3
P3
P3
P3
P3
P3
P8
P8
P8
P8
0
1
2
3
4
5
6
7
0
1
2
3
/FLD24
/FLD25
/FLD26
/FLD27
/FLD28
/FLD29
/FLD30
/FLD31
/FLD32
/FLD33
/FLD34
/FLD35
P5
7
/SRDY2/
SCLK22
P5
P5
P5
6/SCLK21
5/TxD
4/RxD
P5
3
/SCLK12
/SCLK11
P52
P51
/SOUT1
/SIN1
AVSS
REF
/SSTB1/AN11
/SBUSY1/AN10
P6 /AN
/SRDY1/AN
P5
0
M38B57MC-XXXFP
V
P6
/INT
5
P64
4
V
EE
3
9
P8
P8
P8
4
5
6
/FLD36
P6
2
8
/RTP
0
/FLD37
/FLD38
P7
P7
7
/AN
7
6
/RTP
1
6/AN
Package type : 80P6N-A
80-pin plastic-molded QFP
Fig. 1 Pin Configuration of M38B57MC-XXXFP
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL BLOCK
Fig. 2 Functional Block Diagram
2
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1 Pin Description (1)
Pin
Name
Function
Function except a port function
VCC, VSS
VEE
Power source
Pull-down
power source
Reference
voltage
• Apply voltage of 4.0–5.5 V to VCC, and 0 V to VSS.
• Apply voltage supplied to pull-down resistors of ports P0, P1, and P3.
VREF
AVSS
• Reference voltage input pin for A-D converter.
Analog power
source
• Analog power source input pin for A-D converter.
• Connect to VSS.
______
RESET
Reset input
Clock input
• Reset input pin for active “L.”
XIN
• Input and output pins for the main clock generating circuit.
• Feedback resistor is built in between XIN pin and XOUT pin.
•
Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency.
XOUT
Clock output
• When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• The clock is used as the oscillating source of system clock.
P00/FLD8– I/O port P0
P07/FLD15
• 8-bit I/O port.
• FLD automatic display
• I/O direction register allows each pin to be individually programmed as either pins
input or output.
• At reset, this port is set to input mode.
• A pull-down resistor is built in between port P0 and the VEE pin.
• CMOS compatible input level.
• High-breakdown-voltage P-channel open-drain output structure.
• At reset, this port is set to VEE level.
P10/FLD16– Output port P1
P17/FLD23
• 8-bit output port.
• FLD automatic display
• A pull-down resistor is built in between port P1 and the VEE pin.
• High-breakdown-voltage P-channel open-drain output structure.
• At reset, this port is set to VEE level.
pins
P20/BUZ02/ I/O port P2
FLD0–
• 8-bit I/O port with the same function as port P0.
• Low-voltage input level.
• FLD automatic display
pins
P27/FLD7
• High-breakdown-voltage P-channel open-drain output structure.
• 8-bit output port.
• Buzzer output pin (P20)
• FLD automatic display
pins
P30/FLD24– Output port P3
P37/FLD31
• A pull-down resistor is built in between port P3 and the VEE pin.
• High-breakdown-voltage P-channel open-drain output structure.
• At reset, this port is set to VEE level.
P40/INT0,
P41/INT1,
P42/INT3
P43/BUZ01
P44/PWM1
I/O port P4
• 7-bit I/O port with the same function as port P0.
• CMOS compatible input level.
• Interrupt input pins
• N-channel open-drain output structure.
• Buzzer output pin
• PWM output pin
(Timer output pin)
• Timer output pin
P45/T1OUT,
P46/T3OUT
P47/INT2
Input port P4
• 1-bit input port.
• Interrupt input pin
• CMOS compatible input level.
3
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 2 Pin Description (2)
Pin
Name
Function
Function except a port function
P50/SIN1,
I/O port P5
• 8-bit CMOS I/O port with the same function as port P0.
• CMOS compatible input level.
• Serial I/O1 function pins
P51/SOUT1,
P52/SCLK11,
P53/SCLK12
P54/RXD,
P55/TXD,
• CMOS 3-state output structure.
• Serial I/O2 function pins
P56/SCLK21,
________
P57/SRDY2/
SCLK22
P60/CNTR1 I/O port P6
• 1-bit I/O port with the same function as port P0.
• CMOS compatible input level.
• Timer input pin
• Timer I/O pin
• N-channel open-drain output structure.
• 5-bit CMOS I/O port with the same function as port P0.
• CMOS compatible input level.
P61/CNTR0/
CNTR2
________
P62/SRDY1/
AN8
• CMOS 3-state output structure.
• Serial I/O1 function pin
• A-D conversion input pin
• A-D conversion input pin
• Serial I/O1 function pin
• A-D conversion input pin
• Interrupt input pin (P64)
P63/AN9
P64/INT4/
SBUSY1/AN10,
P65/SSTB1/
AN11
P70/AN0–
P77/AN7
I/O port P7
• 8-bit CMOS I/O port with the same function as port P0.
• CMOS compatible input level.
• A-D conversion input pin
• CMOS 3-state output structure.
P80/FLD32– I/O port P8
P83/FLD35
• 4-bit I/O port with the same function as port P0.
• Low-voltage input level.
•
•
•
FLD automatic display pins
FLD automatic display pins
FLD automatic display pins
• High-breakdown-voltage P-channel open-drain output structure.
• 4-bit CMOS I/O port with the same function as port P0.
• Low-voltage input level.
P84/FLD36
P85/RTP0/
FLD37,
P86/RTP1/
FLD38
P87/PWM0/
FLD39
• 14-bit PWM output
P90/XCIN,
I/O port P9
• 2-bit CMOS I/O port with the same function as port P0.
• CMOS compatible input level.
•
I/O pins for sub-clock generating
circuit (connect a ceramic resona-
tor or a quarts-crystal oscillator)
P91/XCOUT
• CMOS 3-state output structure.
4
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product
M38B5 7 M C - XXX FP
Package type
FP : 80P6N-A package
FS : 80D0 package
ROM number
Omitted in some types.
ROM/PROM size
: 4096 bytes
: 8192 bytes
: 12288 bytes
: 16384 bytes
: 20480 bytes
: 24576 bytes
: 28672 bytes
: 32768 bytes
: 36864 bytes
: 40960 bytes
: 45056 bytes
: 49152 bytes
: 53248 bytes
: 57344 bytes
: 61440 bytes
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used for
users.
Memory type
M : Mask ROM version
E : EPROM or One Time PROM version
RAM size
: 192 bytes
: 256 bytes
: 384 bytes
: 512 bytes
: 640 bytes
: 768 bytes
: 896 bytes
: 1024 bytes
: 1536 bytes
: 2048 bytes
0
1
2
3
4
5
6
7
8
9
Fig. 3 Part Numbering
5
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Mitsubishi plans to expand the 38B5 group as follows:
Memory Type
Support for Mask ROM, One Time PROM and EPROM versions.
Memory Size
ROM/PROM size .................................................. 24K to 60K bytes
RAM size ........................................................... 1024 to 2048 bytes
Package
80P6N-A ..................................... 0.8 mm-pitch plastic molded QFP
80D0 ........................ 0.8 mm-pitch ceramic LCC (EPROM version)
Under development
M38B59EF
ROM size (bytes)
60K
56K
52K
48K
44K
40K
36K
32K
28K
24K
20K
16K
12K
8K
New product
M38B57MC
Planning
M38B57M6
4K
256
512
768
1,024
1,536
2,048
RAM size (bytes)
Note : Products under development or planning : the development schedule and specifications may be revised without notice.
Fig. 4 Memory Expansion Plan
Currently supported products are listed below.
Table 3 List of Supported Products
As of Jan. 1998
(P) ROM size (bytes)
Product
RAM size (bytes)
1024
Package
80P6N-A
Remarks
ROM size for User ( )
49152
Mask ROM version
M38B57MC-XXXFP
(49022)
6
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
[CPU Mode Register] CPUM
The CPU mode register contains the stack page selection bit and
internal system clock control bits. The CPU mode register is allo-
cated at address 003B16.
Central Processing Unit (CPU)
The 38B5 group uses the standard 740 family instruction set. Refer
to the table of 740 family addressing modes and machine instruc-
tions or the 740 Family Software Manual for details on the instruction
set.
Machine-resident 740 Family instructions are as follows:
•The FST and SLW instructions cannot be used.
•The MUL, DIV, WIT and STP instructions can be used.
b7
b0
CPU mode register
(
CPUM (CM) : address 003B16)
Processor mode bits
b1 b0
0
0
1
1
0 : Single-chip mode
1
0
1
Not available
Stack page selection bit
0 : 0 page
1 : 1 page
X
COUT drivability selection bit
0 : Low drive
1 : High drive
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN-XCOUT oscillating function
Main clock (XIN-XOUT) stop bit
0 : oscillating
1 : stopped
Main clock division ratio selection bit
0 : f(XIN
)
(high-speed mode)
1 : f(XIN)/4 (middle-speed mode)
Internal system clock selection bit
0 : XIN–XOUT selection (middle-/high-speed mode)
1 : XCIN–XCOUT selection (low-speed mode)
Fig. 5 Structure of CPU Mode Register
7
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Memory
Special function register (SFR) area
The special function register (SFR) area in the zero page contains
control registers such as I/O ports and timers.
Zero page
The 256 bytes from addresses 000016 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
ROM
Special page
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing, and the other areas are user areas for storing pro-
grams.
The 256 bytes from addresses FF0016 to FFFF16 are called the spe-
cial page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM size
(byte)
Address
XXXX16
000016
SFR area 1
RAM
192
256
384
512
640
768
896
1024
1536
2048
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
Zero page
004016
010016
XXXX16
Reserved area
044016
Not used (Note)
0EF0
0EFF1166
ROM area
SFR area 2
0F0016
ROM size
(byte)
Address
YYYY16
Address
ZZZZ16
RAM area for Serial I/O automatic
transfer
RAM area for FLD automatic display
ROM
0FFF16
YYYY16
4096
8192
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
Reserved ROM area
(common ROM area,128 byte)
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
ZZZZ16
FF0016
Special page
FFDC16
Interrupt vector area
Reserved ROM area
FFFE16
FFFF16
Note: When 1024 bytes or more are used as RAM area, this area can be used.
Fig. 6 Memory Map Diagram
8
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016 Port P0 (P0)
Port P0 direction register (P0D)
002016 Timer 1 (T1)
Timer 2 (T2)
Timer 3 (T3)
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
002116
002216
Port P1 (P1)
002316 Timer 4 (T4)
002416 Timer 5 (T5)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Timer 6 (T6)
002516
002616 PWM control register (PWMCON)
002716 Timer 6 PWM register (T6PWM)
002816 Timer 12 mode register (T12M)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Timer 34 mode register (T34M)
Timer 56 mode register (T56M)
002916
002A16
Port P5 direction register (P5D)
Port P6 (P6)
002B16 Watchdog timer control register (WDTCON)
002C16 Timer X (low-order) (TXL)
Port P6 direction register (P6D)
Port P7 (P7)
002D16 Timer X (high-order) (TXH)
002E16 Timer X mode register 1 (TXM1)
002F16 Timer X mode register 2 (TXM2)
003016 Interrupt interval determination register (IID)
Port P7 direction register (P7D)
Port P8 (P8)
Port P8 direction register (P8D)
Interrupt interval determination control register (IIDCON)
003116
001216 Port P9 (P9)
003216 A-D control register (ADCON)
001316 Port P9 direction register (P9D)
003316 A-D conversion register (low-order) (ADL)
PWM register (high-order) (PWMH)
PWM register (low-order) (PWM L)
Baud rate generator (BRG)
001416
001516
001616
001716
001816
001916
003416 A-D conversion register (high-order) (ADH)
003516
003616
003716
003816
UART control register (UARTCON)
Serial I/O1 automatic transfer data pointer (SIO1DP)
Serial I/O1 control register 1 (SIO1CON1)
Interrupt source switch register (IFR)
003916
001A16 Serial I/O1 control register 2 (SIO1CON2)
001B16 Serial I/O1 register/Transfer counter (SIO1)
003A16 Interrupt edge selection register (INTEDGE)
003B16 CPU mode register (CPUM)
Serial I/O1 control register 3 (SIO1CON3)
Serial I/O2 control register (SIO2CON)
Interrupt request register 1(IREQ1)
Interrupt request register 2(IREQ2)
001C16
001D16
003C16
003D16
001E16 Serial I/O2 status register (SIO2STS)
003E16 Interrupt control register 1(ICON1)
003F16 Interrupt control register 2(ICON2)
Serial I/O2 transmit/receive buffer register (TB/RB)
001F16
Pull-up control register 1 (PULL1)
Pull-up control register 2 (PULL2)
P1FLDRAM write disable register (P1FLDRAM)
P3FLDRAM write disable register (P3FLDRAM)
FLDC mode register (FLDM)
FLD data pointer (FLDDP)
0EF016
0EF116
0EF216
0EF316
0EF416
0EF816
0EF916
Port P0FLD/port switch register (P0FPR)
0EFA16 Port P2FLD/port switch register (P2FPR)
0EFB16 Port P8FLD/port switch register (P8FPR)
Port P8FLD output control register (P8FLDCON)
0EFC16
0EF516 Tdisp time set register (TDISP)
0EF616 Toff1 time set register (TOFF1)
0EF716 Toff2 time set register (TOFF2)
0EFD16 Buzzer output control register (BUZCON)
0EFE16
0EFF16
Fig. 7 Memory Map of Special Function Register (SFR)
9
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O Ports
[Direction Registers] PiD
The 38B5 group has 55 programmable I/O pins arranged in eight
individual I/O ports (P0, P2, P40–P46, and P5–P9). The I/O ports
have direction registers which determine the input/output direction of
each individual pin. Each bit in a direction register corresponds to
one pin, and each pin can be set to be input port or output port. When
“0” is written to the bit corresponding to a pin, that pin becomes an
input pin. When “1” is written to that pin, that pin becomes an output
pin. If data is read from a pin set to output, the value of the port
output latch is read, not the value of the pin itself. Pins set to input
(the bit corresponding to that pin must be set to “0”) are floating and
the value of that pin can be read. If a pin set to input is written to, only
the port output latch is written to and the pin remains floating.
b7
b0
Pull-up control register 1
(PULL1 : address 0EF0 16
)
P5
P5
P5
P5
0
2
4
6
, P5
, P5
, P5
, P5
1
3
5
7
pull-up control bit
pull-up control bit
pull-up control bit
pull-up control bit
0: No pull-up
1: Pull-up
P6
P6
P6
1
2
pull-up control bit
, P6
, P6
3
5
pull-up control bit
pull-up control bit
4
Not used
(returns “0” when read)
[High-Breakdown-Voltage Output Ports]
The 38B5 group microprocessors have 5 ports with high-breakdown-
voltage pins (ports P0–P3 and P80–P83). The high-breakdown-volt-
age ports have P-channel open-drain output with Vcc- 45 V of break-
down voltage. Each pin in ports P0, P1, and P3 has an internal pull-
down resistor connected to VEE. At reset, the P-channel output tran-
sistor of each port latch is turned off, so that it goes to VEE level (“L”)
by the pull-down resistor.
b7
b0
Pull-up control register 2
(PULL2 : address 0EF1 16
)
P7
P7
P7
P7
0
2
4
6
, P7
, P7
, P7
, P7
1
3
5
7
pull-up control bit
pull-up control bit
pull-up control bit
pull-up control bit
pull-up control bit
pull-up control bit
pull-up control bit
Writing “1” (weak drivability) to bit 7 of the FLDC mode register (ad-
dress 0EF416) shows the rising transition of the output transistors for
reducing transient noise. At reset, bit 7 of the FLDC mode register is
set to “0” (strong drivability).
0: No pull-up
1: Pull-up
P8
P8
P9
4
6
0
, P8
, P8
, P9
5
7
1
[Pull-up Control Register] PULL
Not used
(returns “0” when read)
Ports P5, P61–P65, P7, P84–P87 and P9 have built-in programmable
pull-up resistors. The pull-up resistors are valid only in the case that
the each control bit is set to “1” and the corresponding port direction
registers are set to input mode.
Fig. 8 Structure of Pull-up Control Registers (PULL1 and PULL2)
10
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 4 List of I/O Port Functions (1)
Pin Name Input/Output
P00/FLD8– Port P0 Input/output,
I/O Format
Non-Port Function
Related SFRs
Ref.No.
(1)
CMOS compatible input level FLD automatic display function FLDC mode register
P07/FLD15
individual bits High-breakdown voltage P-
Port P0FLD/port switch register
channel open-drain output
with pull-down resistor
P10/FLD16– Port P1 Output
P17/FLD23
High-breakdown voltage P-
channel open-drain output
with pull-down resistor
FLDC mode register
(2)
P20/BUZ02/ Port P2 Input/output,
Low-voltage input level
Buzzer output (P20)
FLDC mode register
(3)
(1)
(2)
FLD0
individual bits High-breakdown voltage P-
channel open-drain output
Port P2FLD/port switch register
Buzzer output control register
P21/FLD1–
P27/FLD7
P30/FLD24– Port P3 Output
P37/FLD31
High-breakdown voltage P-
channel open-drain output
with pull-down resistor
FLDC mode register
P40/INT0,
P41/INT1,
P42/INT3
P43/BUZ01
P44/PWM1
P45/T1OUT
P46/T3OUT
P47/INT2
Port P4 Input/output,
CMOS compatible input level External interrupt input
Interrupt edge selection register
(4)
individual bits N-channel open-drain output
Buzzer output
Buzzer output control register
Timer 56 mode register
Timer 12 mode register
Timer 34 mode register
(5)
(6)
(7)
(7)
(8)
PWM output
Timer output
Timer output
Input
CMOS compatible input level External interrput input
Interrupt edge selection register
Interrupt interval determination
control register
P50/SIN1
P51/SOUT1,
P52/SCLK11,
P53/SCLK12
P54/RXD,
Port P5 Input/output,
CMOS compatible input level Serial I/O1 function I/O
Serial I/O1 control register 1, 2
(9)
individual bits CMOS 3-state output
(10)
Serial I/O2 function I/O
Serial I/O2 control register
UART control register
(9)
P55/TXD,
(10)
P56/SCLK21
________
P57/SRDY2/
SCLK22
(11)
(4)
P60/CNTR1 Port P6
CMOS compatible input level External count I/O
N-channel open-drain output
CMOS compatible input level
CMOS 3-state output
Interrupt edge selection register
P61/CNTR0/
(12)
(13)
CNTR2
________
P62/SRDY1/
AN8
Serial I/O1 function I/O
A-D conversion input
Serial I/O1 control register 1, 2
A-D control register
P63/AN9
P64/INT4/
A-D conversion input
A-D control register
(14)
(15)
Serial I/O1 function I/O
A-D conversion input
Serial I/O1 control register 1, 2
A-D control register
S
BUSY1/AN10
External interrupt input
Serial I/O1 function I/O
A-D conversion input
Interrupt edge selection register
Serial I/O1 control register 1, 2
A-D control register
P65/SSTB1/
AN11
(16)
(14)
P70/AN0–
P77/AN7
Port P7
A-D conversion input
A-D control register
11
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 5 List of I/O Port Functions (2)
Pin Name Input/Output
P80/FLD32– Port P8 Input/output,
I/O Format
Non-Port Function
Related SFRs
Ref.No.
(1)
Low-voltage input level
FLD automatic display function FLDC mode register
P83/FLD35
individual bits High-breakdown voltage P-
channel open-drain output
Low-voltage input level
Port P8FLD/port switch register
P84/FLD36
P85/RTP0/
FLD37,
(17)
(18)
CMOS 3-state output
FLD automatic display function FLDC mode register
Real time port output
Port P8FLD/port switch register
P86/RTP1/
FLD38
Timer X mode register 2
P87/PWM0/
FLD39
FLD automatic display function FLDC mode register
(19)
PWM output
Port P8FLD/port switch register
PWM control register
P90/XCIN
Port P9
CMOS compatible input level Sub-clock generating circuit I/O CPU mode register
CMOS 3-state output
(20)
(21)
P91/XCOUT
Notes 1 : How to use double-function ports as function I/O ports, refer to the applicable sections.
2 : Make sure that the input level at each pin is either 0 V or Vcc during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from Vcc to Vss through the input-stage gate.
12
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Ports P1, P3
(1) Ports P0, P21–P27, P80–P83
FLD/Port
switch register
Dimmer signal (Note 1)
Direction register
Dimmer signal (Note 1)
Port latch
Local data
bus
Local data
bus
*
*
Data bus
Port latch
Data bus
read
VEE
(Note 2)
VEE
(4) Ports P40–P42, P60
(3) Port P2
0
FLD/Port
switch register
Buzzer control signal
Buzzer signal output
Direction register
Port latch
Dimmer signal (Note 1)
Direction register
Local data
bus
Data bus
Port latch
*
Data bus
read
INT0,INT1,INT3 interrupt input
CNTR1 input
Timer 4 external clock input
(Note 2)
VEE
(5) Port P4
3
(6) Port P44
Buzzer control signal
Buzzer signal output
Timer 6 output selection bit
Direction register
Direction register
Port latch
Data bus
Port latch
Data bus
Timer 6 output
(7) Ports P4
5
, P4
6
(8) Port P47
Timer 1 output bit
Timer 3 output bit
Direction register
Data bus
Port latch
Data bus
INT2 interrupt
input
Timer 1 output
Timer 3 output
* High-breakdown-voltage P-channel transistor
Notes 1: The dimmer signal sets the Toff timing.
2: A pull-down resistor is not built in to ports P2 and P8.
Fig. 9 Port Block Diagram (1)
13
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(9) Ports P50, P54
(10) Ports P51–P53, P55, P56
Pull-up control
,P5
P-channel output disable signal (P5
Output OFF control signal
1
5)
Pull-up control
Serial I/O2 mode selection bit
Direction register
Direction register
Port latch
Data bus
Port latch
Data bus
T
XD, SOUT or SCLK
Serial clock input
P5 ,P5 ,P5
Serial I/O input
2
3
6
(11) Port P57
(12) Port P61
Pull-up control
Pull-up control
Timer X operating mode bit
S
RDY2 output enable bit
Direction register
Direction register
Port latch
Data bus
Data bus
Port latch
Timer X output
Serial ready output
Serial clock input
CNTR
0,CNTR2 input
Timer2, TimerX external clock input
(13) Port P62
(14) Ports P63, P7
Pull-up control
P6
2/SRDY1•P64/SBUSY1
Pull-up control
pin control bit
Direction register
Port latch
Direction register
Data bus
Port latch
Data bus
Serial ready output
Serial ready input
A-D conversion input
Analog input pin selection bit
A-D conversion input
Analog input pin selection bit
Fig. 10 Port Block Diagram (2)
14
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(15) Port P6
4
(16) Port P6
5
Pull-up control
Pull-up control
P6
2/SRDY1•P64/SBUSY1
P6
5/SSTB1 pin control bit
pin control bit
Direction register
Direction register
Port latch
Port latch
Data bus
Data bus
Analog input
pin selection
bit
S
STB1 output
S
BUSY1 output
INT
4 interrupt input, SBUSY1 input
A-D conversion input
A-D conversion input
(17) Port P8
4
(18) Ports P85, P86
Dimmer signal
(Note)
Pull-up control
Dimmer signal
(Note)
Pull-up control
FLD/Port
FLD/Port
switch register
switch register
Real time port
control bit
Direction register
Port latch
Direction register
Port latch
Local data
bus
Local data
bus
Data bus
Data bus
RTP output
(19) Port P8
7
(20) Port P90
Dimmer signal
(Note)
Pull-up control
Pull-up control
Port Xc switch bit
FLD/Port
P87/PWM
output enable bit
switch register
Direction register
Direction register
Port latch
Local data
bus
Port latch
Data bus
Data bus
PWM0 output
Sub-clock generating circuit input
(21) Port P9
1
Pull-up control
Port Xc switch bit
Direction register
Port latch
Data bus
Oscillator
Port P9
0
* High-breakdown-voltage P-channel transistor
Note: The dimmer signal sets the Toff timing.
Port Xc switch bit
Fig. 11 Port Block Diagram (3)
15
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupts
Interrupts occur by twenty one sources: five external, fifteen internal,
and one software.
(1) Interrupt Control
Each interrupt except the BRK instruction interrupt have both an
interrupt request bit and an interrupt enable bit, and is controlled by
the interrupt disable flag. An interrupt occurs if the corresponding
interrupt request and enable bits are “1” and the interrupt disable flag
is “0.” Interrupt enable bits can be set or cleared by software. Inter-
rupt request bits can be cleared by software, but cannot be set by
software. The BRK instruction interrupt and reset cannot be disabled
with any flag or bit. The I flag disables all interrupts except the BRK
instruction interrupt and reset. If several interrupts requests occurs
at the same time the interrupt with highest priority is accepted first.
(2) Interrupt Operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
1. The contents of the program counter and processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding
interrupt request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
■Notes on Use
When the active edge of an external interrupt (INT0–INT4) is set or
when switching interrupt sources in the same vector address, the
corresponding interrupt request bit may also be set. Therefore, please
take following sequence:
(1) Disable the external interrupt which is selected.
(2) Change the active edge in interrupt edge selection register
(3) Clear the set interrupt request bit to “0.”
(4) Enable the external interrupt which is selected.
16
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 6 Interrupt Vector Addresses and Priority
Vector Addresses (Note 1)
Interrupt Request
Generating Conditions
Interrupt Source Priority
Remarks
High
Low
Reset (Note 2)
1
2
FFFD16
FFFB16
FFFC16
FFFA16
At reset
Non-maskable
INT0
At detection of either rising or falling edge of
INT0 input
External interrupt
(active edge selectable)
External interrupt
INT1
INT2
3
4
FFF916
FFF716
FFF816
FFF616
At detection of either rising or falling edge of
INT1 input
(active edge selectable)
External interrupt
At detection of either rising or falling edge of
INT2 input
(active edge selectable)
Valid when interrupt interval
determination is operating
Valid when serial I/O1 ordinary
mode is selected
Remort control/
counter overflow
Serial I/O1
At 8-bit counter overflow
5
FFF516
FFF416
At completion of data transfer
Serial I/O1 auto-
matic transfer
Timer X
At completion of the last data transfer
Valid when serial I/O1 automatic
transfer mode is selected
6
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
At timer X underflow
Timer 1
7
At timer 1 underflow
Timer 2
8
At timer 2 underflow
STP release timer underflow
Timer 3
9
At timer 3 underflow
Timer 4
10
11
12
13
14
At timer 4 underflow
Timer 5
At timer 5 underflow
Timer 6
At timer 6 underflow
Serial I/O2 receive
INT3
At completion of serial I/O2 data receive
At detection of either rising or falling edge of
INT3 input
External interrupt
(active edge selectable)
Serial I/O2 transmit
INT4
At completion of data transmit
At detection of either rising or falling edge of
INT4 input
15
FFE116
FFE016
External interrupt
(active edge selectable)
Valid when INT4 interrupt is selected
A-D conversion
FLD blanking
At completion of A-D conversion
At falling edge of the last timing immediately
before blanking period starts
Valid when A-D conversion is selected
Valid when FLD blanking
16
17
FFDF16
FFDD16
FFDE16
FFDC16
interrupt is selected
FLD digit
At rising edge of each digit
Valid when FLD digit interrupt is selected
Non-maskable software interrupt
BRK instruction
At BRK instruction execution
Notes 1 : Vector addresses contain interrupt jump destination addresses.
2 : Reset function in the same way as an interrupt with the highest priority.
17
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset
Interrupt request
Fig. 12 Interrupt Control
b7
b0
Interrupt source switch register
(IFR : address 003916
)
INT
0 : INT
1 : Serial I/O2 transmit interrupt
INT /AD conversion interrupt switch bit
0 : INT interrupt
3
/serial I/O2 transmit interrupt switch bit
3
interrupt
4
4
1 : A-D conversion interrupt
Not used (return “0” when read)
(Do not write “1” to these bits.)
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16
)
INT
INT
INT
INT
INT
0
interrupt edge selection bit
interrupt edge selection bit
interrupt edge selection bit
interrupt edge selection bit
interrupt edge selection bit
1
2
3
4
0 : Falling edge active
1 : Rising edge active
Not used (return "0" when read)
0 : Rising edge count
1 : Falling edge count
CNTR
CNTR
0
pin edge switch bit
pin edge switch bit
1
b7
b0
b7
b0
Interrupt request register 2
(IREQ2 : address 003D16
Interrupt request register 1
(IREQ1 : address 003C16
)
)
INT
INT
INT
0
interrupt request bit
interrupt request bit
interrupt request bit
Timer 4 interrupt request bit
Timer 5 interrupt request bit
Timer 6 interrupt request bit
Serial I/O2 receive interrupt request bit
1
2
Remote controller/counter overflow interrupt
request bit
INT
INT
3
/serial I/O2 transmit interrupt request bit
interrupt request bit
Serial I/O1 interrupt request bit
Serial I/O automatic transfer interrupt request bit
Timer X interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
4
AD conversion interrupt request bit
FLD blanking interrupt request bit
FLD digit interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0 Interrupt control register 1
(ICON1 : address 003E16
b7
b0
Interrupt control register 2
(ICON2 : address 003F16
)
)
INT
INT
INT
0
interrupt enable bit
interrupt enable bit
interrupt enable bit
Timer 4 interrupt enable bit
Timer 5 interrupt enable bit
Timer 6 interrupt enable bit
1
2
Remote controller/counter overflow interrupt
enable bit
Serial I/O2 receive interrupt enable bit
INT
INT
3
4
/serial I/O2 transmit interrupt enable bit
interrupt enable bit
Serial I/O1 interrupt enable bit
Serial I/O automatic transfer interrupt enable bit
Timer X interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
AD conversion interrupt enable bit
FLD blanking interrupt enable bit
FLD digit interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 13 Structure of Interrupt Related Registers
18
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timers
8-Bit Timer
The 38B5 group has six built-in timers : Timer 1, Timer 2, Timer 3,
Timer 4, Timer 5, and Timer 6.
b7
b7
b7
b0
Timer 12 mode register
(T12M: address 002816)
Each timer has the 8-bit timer latch. All timers are down-counters.
When the timer reaches “0016,” an underflow occurs with the next
count pulse. Then the contents of the timer latch is reloaded into the
timer and the timer continues down-counting. When a timer
underflows, the interrupt request bit corresponding to that timer is
set to “1.”
Timer 1 count stop bit
0 : Count operation
1 : Count stop
Timer 2 count stop bit
0 : Count operation
1 : Count stop
Timer 1 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : f(XCIN)
10 : f(XIN)/16 or f(XCIN)/32
11 : f(XIN)/64 or f(XCIN)/128
Timer 2 count source selection bits
00 : Underflow of Timer 1
01 : f(XCIN)
10 : External count input CNTR0
11 : Not available
Timer 1 output selection bit (P45)
0 : I/O port
The count can be stopped by setting the stop bit of each timer to “1.”
The internal system clock can be set to either the high-speed mode
or low-speed mode with the CPU mode register. At the same time,
timer internal count source is switched to either f(XIN) or f(XCIN).
1 : Timer 1 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
●Timer 1, Timer 2
The count sources of timer 1 and timer 2 can be selected by setting
the timer 12 mode register. A rectangular waveform of timer 1
underflow signal divided by 2 is output from the P45/T1OUT pin. The
waveform polarity changes each time timer 1 overflows. The active
edge of the external clock CNTR0 can be switched with the bit 6 of
the interrupt edge selection register.
b0
Timer 34 mode register
(T34M: address 002916)
Timer 3 count stop bit
0 : Count operation
1 : Count stop
Timer 4 count stop bit
0 : Count operation
1 : Count stop
Timer 3 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : Underflow of Timer 2
10 : f(XIN)/16 or f(XCIN)/32
11 : f(XIN)/64 or f(XCIN)/128
Timer 4 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : Underflow of Timer 3
10 : External count input CNTR1
11 : Not available
Timer 3 output selection bit (P46)
0 : I/O port
1 : Timer 3 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
At reset or when executing the STP instruction, all bits of the timer 12
mode register are cleared to “0,” timer 1 is set to “FF16,” and timer 2
is set to “0116.”
●Timer 3, Timer 4
The count sources of timer 3 and timer 4 can be selected by setting
the timer 34 mode register. A rectangular waveform of timer 3
underflow signal divided by 2 is output from the P46/T3OUT pin. The
waveform polarity changes each time timer 3 overflows. The active
edge of the external clock CNTR1 can be switched with the bit 7 of
the interrupt edge selection register.
b0
Timer 56 mode register
(T56M: address 002A16)
●Timer 5, Timer 6
Timer 5 count stop bit
0 : Count operation
1 : Count stop
Timer 6 count stop bit
0 : Count operation
1 : Count stop
Timer 5 count source selection bit
0 : f(XIN)/8 or f(XCIN)/16
1 : Underflow of Timer 4
Timer 6 operation mode selection bit
0 : Timer mode
The count sources of timer 5 and timer 6 can be selected by setting
the timer 56 mode register. A rectangular waveform of timer 6
underflow signal divided by 2 is output from the P44/PWM1 pin. The
waveform polarity changes each time timer 6 overflows.
●Timer 6 PWM1 Mode
1 : PWM mode
Timer 6 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : Underflow of Timer 5
10 : Underflow of Timer 4
11 : Not available
Timer 6 (PWM) output selection bit (P44)
0 : I/O port
1 : Timer 6 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
Timer 6 can output a rectangular waveform with “H” duty cycle n/
(n+m) from the P44/PWM1 pin by setting the timer 56 mode register
(refer to Figure 16). The n is the value set in timer 6 latch (address
002516) and m is the value in the timer 6 PWM register (address
002716). If n is “0,” the PWM output is “L,” if m is “0,” the PWM output
is “H” (n = 0 is prior than m = 0). In the PWM mode, interrupts occur
at the rising edge of the PWM output.
Fig. 14 Structure of Timer Related Register
19
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
XCIN
RESET
Timer 1 latch (8)
Timer 1 count source
selection bit
1/2
“01”
FF16
Internal system clock
selection bit
STP instruction
Timer 1 interrupt request
“1”
Timer 1 (8)
1/8
XIN
“00”
“10”
“11”
Timer 1 count
stop bit
“0”
1/16
1/64
P45 latch
P45/T1OUT
1/2
Timer 1 output selection bit
P45 direction register
Timer 2 latch (8)
Timer 2 count source
selection bit
“00”
“01”
0116
Timer 2 interrupt request
Timer 2 (8)
Timer 2 count
stop bit
“10”
Rising/Falling
active edge switch
P61/CNTR0/CNTR2
Timer 3 latch (8)
Timer 3 count source
selection bit
“01”
“00”
Timer 3 interrupt request
Timer 3 (8)
Timer 3 count
stop bit
P46 latch
“10”
“11”
P46/T3OUT
1/2
Timer 3 output selection bit
Timer 4 latch (8)
Timer 4 count source
selection bit
“01”
Timer 4 (8)
Timer 4 interrupt request
P46 direction register
“00”
“10”
Timer 4 count
stop bit
Rising/Falling
active edge switch
P60/CNTR1
Timer 5 latch (8)
Timer 5 count source
“1” selection bit
Timer 5 interrupt request
Timer 5 (8)
“0”
Timer 5 count
stop bit
Timer 6 latch (8)
Timer 6 count source
“01”
selection bit
Timer 6 (8)
Timer 6 interrupt request
“00”
“10”
Timer 6 count
stop bit
Timer 6 PWM register (8)
P44 latch
P44/PWM1
PWM
1/2
“1”
“0”
Timer 6 output selection bit
P44 direction register
Timer 6 operation
mode selection bit
Fig. 15 Block Diagram of Timer
20
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ts
Timer 6
count source
Timer 6 PWM
mode
n
✕
ts
m
ts
✕ ts
(n+m)
✕
Timer 6 interrupt request
Timer 6 interrupt request
Note: PWM waveform (duty : n/(n + m) and period: (n + m)
n : setting value of Timer 6
✕ ts) is output.
m: setting value of Timer 6 PWM register
ts: period of Timer 6 count source
Fig. 16 Timing Chart of Timer 6 PWM1 Mode
21
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
16-Bit Timer
■ Note
Timer X is a 16-bit timer that can be selected in one of four modes by
the Timer X mode register 1, 2 and can be controlled the timer X
write and the real time port by setting the timer X mode registers.
Read and write operation on 16-bit timer must be performed for both
high- and low-order bytes. When reading a 16-bit timer, read from
the high-order byte first. When writing to 16-bit timer, write to the low-
order byte first. The 16-bit timer cannot perform the correct operation
when reading during write operation, or when writing during read
operation.
•Timer X Write Control
If the timer X write control bit is “0,” when the value is written in the
address of timer X, the value is loaded in the timer X and the latch at
the same time.
If the timer X write control bit is “1,” when the value is written in the
address of timer X, the value is loaded only in the latch. The value in
the latch is loaded in timer X after timer X underflows.
When the value is written in latch only, unexpected value may be set
in the high-order counter if the writing in high-order latch and the
underflow of timer X are performed at the same timing.
●Timer X
Timer X is a down-counter. When the timer reaches “000016,” an
underflow occurs with the next count pulse. Then the contents of the
timer latch is reloaded into the timer and the timer continues down-
counting. When a timer underflows, the interrupt request bit corre-
sponding to that timer is set to “1.”
•Real Time Port Control
While the real time port function is valid, data for the real time port
are output from ports P85 and P86 each time the timer X underflows.
(However, if the real time port control bit is changed from “0” to “1,”
data are output without the timer X.) When the data for the real time
port is changed while the real time port function is valid, the changed
data are output at the next underflow of timer X.
(1) Timer mode
A count source can be selected by setting the Timer X count source
selection bits (bits 1 and 2) of the Timer X mode register 1.
Before using this function, set the corresponding port direction regis-
ters to output mode.
(2) Pulse output mode
Each time the timer underflows, a signal output from the CNTR2 pin
is inverted. Except for this, the operation in pulse output mode is the
same as in timer mode. When using a timer in this mode, set the port
shared with the CNTR2 pin to output.
(3) Event counter mode
The timer counts signals input through the CNTR2 pin. Except for
this, the operation in event counter mode is the same as in timer
mode. When using a timer in this mode, set the port shared with the
CNTR2 pin to input.
(4) Pulse width measurement mode
A count source can be selected by setting the Timer X count source
selection bits (bits 1 and 2) of the Timer X mode register 1. When
CNTR2 active edge switch bit is “0,” the timer counts while the input
signal of the CNTR2 pin is at “H.” When it is “1,” the timer counts
while the input signal of the CNTR2 pin is at “L.” When using a timer
in this mode, set the port shared with the CNTR2 pin to input.
22
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Real time port
Data bus
control bit
“1”
Q D
P85 data for real time port
P85
Real time port
control bit (P8
“0”
Latch
“0”
“1”
5
)
P8
register
5
direction
Timer X mode register
write signal
P85
latch
latch
Real time port
“1”
control bit
Q D
P86 data for real time port
P86
“0”
P8
Real time port
control bit (P86)
Latch
P8
register
6
direction
“0”
“1”
Timer X mode register
write signal
6
XCIN
1/2
Internal system clock
selection bit
1/2
“1”
XIN
Count source selection bit
1/8
“0”
1/64
Timer X stop
control bit
Timer X write
control bit
Timer X operating
mode bit
CNTR
edge switch bit
2 active
Timer X latch (high-order) (8)
Timer X latch (low-order) (8)
“00”,“01”,“11”
“0”
“1”
Timer X
interrupt request
P61
/CNTR
0/CNTR2
Timer X (low-order) (8)
Timer X (high-order) (8)
“10”
Pulse width
measurement mode
Pulse output mode
CNTR
2 active
“0”
“1”
edge switch bit
Q
Q
T
P6
1 direction
register
P61 latch
Pulse output mode
CNTR
0
Fig. 17 Block Diagram of Timer X
b7
b0
b7
b0
Timer X mode register 2
(TXM2 : address 002F16
Timer X mode register 1
(TXM1 : address 002E16
)
)
Timer X write control bit
Real time port control bit (P85)
0 : Real time port function is invalid
1 : Real time port function is valid
Real time port control bit (P86)
0 : Real time port function is invalid
1 : Real time port function is valid
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer X count source selection bits
b2 b1
0
0
1
1
0 : f(XIN)/2 or f(XCIN)/4
1 : f(XIN)/8 or f(XCIN)/16
0 : f(XIN)/64 or f(XCIN)/128
1 : Not available
P8
5
data for real time port
data for real time port
P86
Not used (returns "0" when read)
Not used (returns "0" when read)
Timer X operating mode bits
b5 b4
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement mode
CNTR
2 active edge switch bit
0 : • Event counter mode ; counts rising edges
• Pulse output mode ; output starts with “H” level
• Pulse width measurement mode ; measures “H” periods
1 : • Event counter mode ; counts falling edges
• Pulse output mode ; output starts with “L” level
• Pulse width measurement mode ; measures “L” periods
Timer X stop control bit
0 : Count operating
1 : Count stop
Fig. 18 Structure of Timer X Related Registers
23
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FLD automatic display RAM).
Serial I/O
________
The P62/SRDY1/AN8, P64/INT4/SBUSY1/AN10, and P65/SSTB1/AN11
●Serial I/O1
Serial I/O1 is used as the clock synchronous serial I/O and has an
pins each have a handshake I/O signal function and can select
either “H” active or “L” active for active logic.
ordinary mode and an automatic transfer mode. In the automatic
transfer mode, serial transfer is performed through the serial I/O
automatic transfer RAM which has up to 256 bytes (addresses
0F0016 to 0FFF16: addresses 0F6016 to 0FFF16 are also used as
Main address
bus
Local address
bus
Main
data bus
Local
data bus
Serial I/O automatic
transfer RAM
(0F0016—0FFF16)
Serial I/O1
automatic transfer
data pointer
Address decoder
Serial I/O1
automatic transfer
controller
XCIN
1/2
Serial I/O1
control register 3
Internal system
clock selection bit
“1”
“0”
1/4
1/8
XIN
P65 latch
“0”
1/16
1/32
1/64
1/128
1/256
(P65/SSTB1 pin control bit)
P65/SSTB1
“1”
P62/SRDY1•P64/SBUSY1
pin control bit
P64 latch
Internal synchronous
clock selection bits
“0”
Serial I/O1
synchronous clock
P64/SBUSY1
“1”
selection bit
“0”
P62/SRDY1•P64/SBUSY1
pin control bit
Synchronous
circuit
P62 latch
“0”
“1”
Serial I/O1 clock
P62/SRDY1
pin selection bit
“1”
“0”
“1”
Serial transfer
status flag
Serial I/O1
interrupt request
P52 latch
“0”
P52/SCLK11
P53/SCLK12
“0”
“1”
“1”
“1”
Serial I/O1 counter
Serial I/O1 clock
pin selection bits
“0”
P53 latch
“0”
P51 latch
P51/SOUT1
P50/SIN1
“1”
Serial transfer selection bits
Serial I/O1 register (8)
Fig. 19 Block Diagram of Serial I/O1
24
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Serial I/O1 control register 1
(SIO1CON1 (SC11):address 001916
)
Serial transfer selection bits
00: Serial I/O disabled (pins P6
01: 8-bits serial I/O
2,P64,P65,and P50—P53 are I/O ports)
10: Not available
11: Automatic transfer serial I/O (8-bits)
Serial I/O1 synchronous clock selection bits (P6
00: Internal synchronous clock (P6 pin is an I/O port.)
01: External synchronous clock (P6
5/SSTB1 pin control bit)
5
5
pin is an I/O port.)
10: Internal synchronous clock (P6
11: Internal synchronous clock (P6
5
5
pin is an SSTB1 output.)
pin is an SSTB1 output.)
Serial I/O initialization bit
0: Serial I/O initialization
1: Serial I/O enabled
Transfer mode selection bit
0: Full duplex (transmit and receive) mode (P5
1: Transmit-only mode (P5 pin is an I/O port.)
0 pin is an SIN1 input.)
0
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O1 clock pin selection bit
0:SCLK11 (P53/
1:SCLK12 (P52/
S
S
CLK12 pin is an I/O port.)
CLK11 pin is an I/O port.)
b7
b0
Serial I/O1 control register 2
(SIO1CON2 (SC12): address 001A16
)
P6
0000: Pins P6
0001: Not used
2
/SRDY1 • P6
4
/SBUSY1 pin control bits
and P6 are I/O ports
2
4
0010: P6
0011: P6
0100: P6
0101: P6
0110: P6
0111: P6
1000: P6
1001: P6
1010: P6
1011: P6
1100: P6
1101: P6
1110: P6
1111: P6
2
2
2
2
2
2
2
2
2
2
2
2
2
2
pin is an SRDY1output, P6
pin is an SRDY1output, P6
4
4
pin is an I/O port.
pin is an I/O port.
pin is an I/O port, P6
pin is an I/O port, P6
pin is an I/O port, P6
pin is an I/O port, P6
4
4
4
4
pin is an SBUSY1 input.
pin is an SBUSY1 input.
pin is an SBUSY1 output.
pin is an SBUSY1 output.
pin is an SRDY1 input, P6
pin is an SRDY1 input, P6
pin is an SRDY1 input, P6
pin is an SRDY1 input, P6
4
4
4
4
pin is an SBUSY1 output.
pin is an SBUSY1 output.
pin is an SBUSY1 output.
pin is an SBUSY1 output.
pin is an SRDY1 output, P6
pin is an SRDY1 output, P6
pin is an SRDY1 output, P6
pin is an SRDY1 output, P6
4
pin is an SBUSY1 input.
pin is an SBUSY1 input.
pin is an SBUSY1 input.
pin is an SBUSY1 input.
4
4
4
S
BUSY1 output • SSTB1 output function selection bit
(Valid in automatic transfer mode)
0: Functions as each 1-byte signal
1: Functions as signal for all transfer data
Serial transfer status flag
0: Serial transfer completion
1: Serial transferring
S
OUT1 pin control bit (at no-transfer serial data)
0: Output active
1: Output high-impedance
P51/SOUT1 P-channel output disable bit
0: CMOS 3-state (P-channel output is valid.)
1: N-channel open-drain (P-channel output is invalid.)
Fig. 20 Structure of Serial I/O1 Control Registers 1, 2
25
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Serial I/O1 Operation
When the SCLK1 input is “H” after completion of transfer, set the
SOUT1 pin control bit to “1.”
Either the internal synchronous clock or external synchronous clock
can be selected by the serial I/O1 synchronous clock selection bits
(b2 and b3 of address 001916) of serial I/O1 control register 1 as
synchronous clock for serial transfer.
When the SCLK1 input goes to “L” after the start of the next serial
transfer, the SOUT1 pin control bit is automatically reset to “0” and
put into an output active state.
The internal synchronous clock has a built-in dedicated divider where
7 different clocks are selected by the internal synchronous clock
selection bits (b5, b6 and b7 of address 001C16) of serial I/O1
Regardless of whether the internal synchronous clock or external
synchronous clock is selected, the full duplex mode and the trans-
mit-only mode are available for serial transfer, one of which is se-
lected by the transfer mode selection bit (b5 of address 001916) of
serial I/O1 control register 1.
control register 3.
________
The P62/SRDY1/AN8, P64/INT4/SBUSY1/AN10, and P65/SSTB1/AN11
pins each select either I/O port or handshake I/O signal by the
Either LSB first or MSB first is selected for the I/O sequence of the
serial transfer bit strings by the transfer direction selection bit (b6 of
address 001916) of serial I/O1 control register 1.
serial I/O1 synchronous clock selection bits (b2 and b3 of address
________
001916) of serial I/O1 control register 1 as well as the P62/SRDY1 •
P64/SBUSY1 pin control bits (b0 to b3 of address 001A16) of serial
I/O1 control register 2.
When using serial I/O1, first select either 8-bit serial I/O or auto-
matic transfer serial I/O by the serial transfer selection bits (b0 and
b1 of address 001916) of serial I/O1 control register 1, after comple-
tion of the above bit setup. Next, set the serial I/O initialization bit
(b4 of address 001916) of serial I/O1 control register 1 to “1” (Serial
I/O enable) .
For the SOUT1 being used as an output pin, either CMOS output or
N-channel open-drain output is selected by the P51/SOUT1 P-chan-
nel output disable bit (b7 of address 001A16) of serial I/O1 control
register 2.
Either output active or high-impedance can be selected as a SOUT1
pin state at serial non-transfer by the SOUT1 pin control bit (b6 of
address 001A16) of serial I/O1 control register 2. However, when
the external synchronous clock is selected, perform the following
setup to put the SOUT1 pin into a high-impedance state.
When stopping serial transfer while data is being transferred, re-
gardless of whether the internal or external synchronous clock is
selected, reset the serial I/O initialization bit (b4) to “0.”
b7
b0
Serial I/O1 control register 3
(SIO1CON3 (SC13): address 001C16
)
Automatic transfer interval set bits
00000:2cycles of transfer clocks
00001:3cycles of transfer clocks
:
11110:32cycles of transfer clocks
11111:33cycles of transfer clocks
Data is written to a latch and read from a decrement counter.
Internal synchronous clock selection bits
000:f(XIN)/4 or f(XCIN)/8
001:f(XIN)/8 or f(XCIN)/16
010:f(XIN)/16 or f(XCIN)/32
011:f(XIN)/32 or f(XCIN)/64
100:f(XIN)/64 or f(XCIN)/128
101:f(XIN)/128 or f(XCIN)/256
110:f(XIN)/256 or f(XCIN)/512
Fig. 21 Structure of Serial I/O1 Control Register 3
26
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) 8-bit Serial I/O Mode
that the automatic transfer interval setting is valid, a transfer inter-
val is placed before the start of transmission/reception of the first
data and after the end of transmission/reception of the last data.
For SSTB1 output, regardless of the contents of the SBUSY1 output •
SSTB1 output function selection bit (b4), the transfer interval for each
1-byte data is longer than the set value by 2 cycles.
Address 001B16 is assigned to the serial I/O1 register.
When the internal synchronous clock is selected, a serial transfer
of the 8-bit serial I/O is started by a write signal to the serial I/O1
register (address 001B16).
The serial transfer status flag (b5 of address 001A16) of serial I/O1
control register 2 indicates the shift register status of serial I/O1,
and is set to “1” by writing into the serial I/O1 register, which be-
comes a transfer start trigger and reset to “0” after completion of 8-
bit transfer. At the same time, a serial I/O1 interrupt request occurs.
When the external synchronous clock is selected, the contents of
the serial I/O1 register are continuously shifted while transfer clocks
are input to SCLK1. Therefore, the clock needs to be controlled ex-
ternally.
Furthermore, when using a combination of SBUSY1 output and SSTB1
output as a signal for all transfer data, the transfer interval after the
end of transmission/reception of the last data is longer than the set
value by 2 cycles.
When the external synchronous clock is selected, automatic trans-
fer interval setting is disabled.
After completion of the above bit setup, if the internal synchronous
clock is selected, automatic serial transfer is started by writing the
value of “number of transfer bytes - 1” into the transfer counter
(address 001B16).
(3) Automatic Transfer Serial I/O Mode
The serial I/O1 automatic transfer controller controls the write and
read operations of the serial I/O1 register, so the function of ad-
dress 001B16 is used as a transfer counter (1-byte units).
When performing serial transfer through the serial I/O automatic
transfer RAM (addresses 0F0016 to 0FFF16), it is necessary to set
the serial I/O1 automatic transfer data pointer (address 001816)
beforehand.
When the external synchronous clock is selected, write the value of
“number of transfer bytes - 1” into the transfer counter and input an
internal system clock interval of 5 cycles or more. After that, input
transfer clock to SCLK1.
As a transfer interval for each 1-byte data transfer, input an internal
system clock interval of 5 cycles or more from the clock rise time of
the last bit.
Input the low-order 8 bits of the first data store address to be seri-
ally transferred to the automatic transfer data pointer set bits.
When the internal synchronous clock is selected, the transfer inter-
val for each 1-byte data can be set by the automatic transfer inter-
val set bits (b0 to b4 of address 001C16) of serial I/O1 control regis-
ter 3 in the following cases:
Regardless of whether the internal or external synchronous clock
is selected, the automatic transfer data pointer and the transfer
counter are decremented after each 1-byte data is received and
then written into the automatic transfer RAM. The serial transfer
status flag (b5 of address 001A16) is set to “1” by writing data into
the transfer counter. Writing data becomes a transfer start trigger,
and the serial transfer status flag is reset to “0” after the last data is
written into the automatic transfer RAM. At the same time, a serial
I/O1 interrupt request occurs.
1. When using no handshake signal
2. When using the SRDY1 output, SBUSY1 output, and SSTB1 output
of the handshake signal independently
3. When using a combination of SRDY1 output and SSTB1 output or a
combination of SBUSY1 output and SSTB1 output of the handshake
signal
The values written in the automatic transfer data pointer set bits
(b0 to b7 of address 001816) and the automatic transfer interval set
bits (b0 to b4 of address 001C16) are held in the latch.
When data is written into the transfer counter, the values latched in
the automatic transfer data pointer set bits (b0 to b7) and the auto-
matic transfer interval set bits (b0 to b4) are transferred to the
decrement counter.
It is possible to select one of 32 different values, namely 2 to 33
cycles of the transfer clock, as a setting value.
When using the SBUSY1 output and selecting the SBUSY1 output •
SSTB1 output function selection bit (b4 of address 001A16) of serial
I/O1 control register 2 as the signal for all transfer data, provided
b7
b0
Serial I/O1 automatic transfer data pointer
(SIO1DP: address 001816
)
Automatic transfer data pointer set bits
Specify the low-order 8 bits of the first data store address on the serial I/O automatic
transfer RAM. Data is written into the latch and read from the decrement counter.
Fig. 22 Structure of Serial I/O1 Automatic Transfer Data Pointer
27
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Automatic transfer RAM
FFF16
Automatic transfer
data pointer
5216
F5216
F5116
F5016
F4F16
F4E16
Transfer counter
0416
F0016
S
IN1
S
OUT1
Serial I/O1 register
Fig. 23 Automatic Transfer Serial I/O Operation
28
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(4) Handshake Signal
1. SSTB1 output signal
The SSTB1 output is a signal to inform an end of transmission/re-
ception to the serial transfer destination . The SSTB1 output signal
can be used only when the internal synchronous clock is selected.
In the initial status, namely, in the status in which the serial I/O
initialization bit (b4) is reset to “0,” the SSTB1 output goes to “L,” or
the _S__S_T__B_1_ output goes to “H.”
S
BUSY1
SCLK1
At the end of transmit/receive operation, when the data of the serial
I/O1 register is all output from SOUT1, pulses are output in the pe-
riod of 1 cycle of the transfer clock so as to cause the SSTB1 output
to go “H” or the _S__S_T__B_1_ output to go “L.” After that, each pulse is
SOUT1
Fig. 25 SBUSY1 Input Operation (internal synchronous clock)
returned to the initial status in which SSTB1 output goes to “L” or the
________
SSTB1 output goes to “H.”
Furthermore, after 1 cycle, the serial transfer status flag (b5) is re-
set to “0.”
When the external synchronous clock is selected, input an “H” level
_________
signal into the SBUSY1 input and an “L” level signal into the SBUSY1
input in the initial status in which transfer is stopped. At this time,
the transfer clocks to be input in SCLK1 become invalid.
During serial transfer, the transfer clocks to be input in SCLK1 be-
come valid, enabling a transmit/receive operation, while an “L” level
signal is input into the SBUSY1 input and an “H” level signal is input
into the _S__B_U__S_Y__1_ input.
In the automatic transfer serial I/O mode, whether the SSTB1 output
is to be active at an end of each 1-byte data or after completion of
transfer of all data can be selected by the SBUSY1 output • SSTB1
output function selection bit (b4 of address 001A16) of serial I/O1
control register 2.
When changing the input values in the SBUSY1 input and the_S__B_U__S_Y__1_
input at these operations, change them when the SCLK1 input is in a
high state.
SSTB1
When the high impedance of the SOUT1 output is selected by the
SOUT1 pin control bit (b6), the SOUT1 output becomes active, en-
abling serial transfer by inputting a transfer clock to SCLK1, while an
“L” level signal is input into the SBUSY1 input and an “H” level signal
is input into the _S__B_U__S_Y__1_ input.
Serial transfer
status flag
SCLK1
SOUT1
S
BUSY1
Fig. 24 SSTB1 Output Operation
2. SBUSY1 input signal
S
CLK1
The SBUSY1 input is a signal which receives a request for a stop of
transmission/reception from the serial transfer destination.
When the internal synchronous clock is selected, input an “H” level
signal into the SBUSY1 input and an “L” level signal into the _S__B_U__S_Y__1_
input in the initial status in which transfer is stopped.
Invalid
SOUT1
(Output high-impedance)
When starting a transmit/receive operation, input an “L” level signal
into the SBUSY1 input and an “H” level signal into the_S__B_U__S_Y__1_ input in
the period of 1.5 cycles or more of the transfer clock. Then, transfer
clocks are output from the SCLK1 output.
Fig. 26 SBUSY1 Input Operation (external synchronous clock)
3. SBUSY1 output signal
When an “H” level signal is input into the SBUSY1 input and an “L”
level signal into the_S__B_U__S_Y__1_ input after a transmit/receive operation
is started, this transmit/receive operation are not stopped immedi-
ately and the transfer clocks from the SCLK1 output is not stopped
until the specified number of bits are transmitted and received.
The handshake unit of the 8-bit serial I/O is 8 bits and that of the
automatic transfer serial I/O is 8 bits.
The SBUSY1 output is a signal which requests a stop of transmis-
sion/reception to the serial transfer destination. In the automatic
transfer serial I/O mode, regardless of the internal or external syn-
chronous clock, whether the SBUSY1 output is to be active at trans-
fer of each 1-byte data or during transfer of all data can be selected
by the SBUSY1 output • SSTB1 output function selection bit (b4).
In the initial status, the status in which the serial I/O initialization bit
_________
(b4) is reset to “0,” the SBUSY1 output goes to “H” and the SBUSY1
output goes to “L.”
29
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
When the internal synchronous clock is selected, in the 8-bit serial
I/O mode and the automatic transfer serial I/O mode (SBUSY1 out-
data is written into the serial I/O1 register to start a transmit opera-
tion, regardless of the serial I/O transfer mode.
put function outputs in 1-byte units), the SBUSY1 output goes to “L”
At termination of transmit/receive operation, the SBUSY1 output re-
turns to “H” and the _S__B_U__S_Y__1_ output returns to “L”, the initial status,
when the serial transfer status flag is set to "0", regardless of whether
the internal or external synchronous clock is selected.
_________
and the SBUSY1 output goes to “H” before 0.5 cycle (transfer clock)
of the timing at which the transfer clock from the SCLK1 output goes
to “L” at a start of transmit/receive operation.
In the automatic transfer serial I/O mode (the SBUSY1 output func-
Furthermore, in the automatic transfer serial I/O mode (SBUSY1 out-
put function outputs in 1-byte units), the SBUSY1 output goes to “H”
and the_S__B_U__S_Y__1_ output goes to “L” each time 1-byte of receive data
is written into the automatic transfer RAM.
tion outputs all transfer data), the SBUSY1 output goes to “L” and the
_________
SBUSY1 output goes to “H” when the first transmit data is written into
the serial I/O1 register (address 001B16).
When the external synchronous clock is selected, the SBUSY1 out-
put goes to “L” and the _S__B_U__S_Y__1_ output goes to “H” when transmit
S
BUSY1
SBUSY1
Serial transfer
status flag
Serial transfer
status flag
S
CLK1
SCLK1
Write to Serial
I/O1 register
SOUT1
Fig. 27 SBUSY1 Output Operation
(internal synchronous clock, 8-bits serial I/O)
Fig. 28 SBUSY1 Output Operation
(external synchronous clock, 8-bits serial I/O)
Automatic transfer
interval
S
CLK1
Serial I/O1 register
→Automatic transfer RAM
Automatic transfer RAM
→Serial I/O1 register
SBUSY1
Serial transfer
status flag
SOUT1
Fig. 29 SBUSY1 Output Operation in Automatic Transfer Serial I/O Mode
(internal synchronous clock, SBUSY1 output function outputs each 1-byte)
30
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
4. SRDY1 output signal
The SRDY1 output is a transmit/receive enable signal which informs
the serial transfer destination that transmit/receive is ready. In the
initial status, when the serial I/O initialization bit (b4) is reset to “0,”
the SRDY1 output goes to “L” and the _S_R__D__Y_1_ output goes to “H”. After
transmitted data is stored in the serial I/O1 register (address 001B16)
S
RDY1
S
CLK1
and a transmit/receive operation becomes ready, the SRDY1 output
________
goes to “H” and the SRDY1 output goes to “L”. When a transmit/
receive operation is started and the transfer clock goes to “L”, the
SRDY1 output goes to “L” and the _S__R_D__Y_1_ output goes to “H”.
Write to serial
I/O1 register
5. SRDY1 input signal
Fig. 30 SRDY1 Output Operation
The SRDY1 input signal becomes valid only when the SRDY1 input
and the SBUSY1 output are used. The SRDY1 input is a signal for
receiving a transmit/receive ready completion signal from the serial
transfer destination.
When the internal synchronous clock is selected, input a low level
signal into the SRDY1 input and a high level signal into the_S__R__D_Y__1_
input in the initial status in which the transfer is stopped.
When an “H” level signal is input into the SRDY1 input and an “L”
level signal is input into the_S__R__D_Y__1_input for a period of 1.5 cycles or
more of transfer clock, transfer clocks are output from the SCLK1
output and a transmit/receive operation is started.
S
RDY1
S
CLK1
S
OUT1
After the transmit/receive operation is started and an “L” level sig-
nal is input into the SRDY1 input and an “H” level signal into the
_________
SRDY1 input, this operation cannot be immediately stopped.
After the specified number of bits are transmitted and received, the
transfer clocks from the SCLK1 output is stopped. The handshake
unit of the 8-bit serial I/O and that of the automatic transfer serial
I/O are of 8 bits.
Fig. 31 SRDY1 Input Operation (internal synchronous clock)
When the external synchronous clock is selected, the SRDY1 input
becomes one of the triggers to output the SBUSY1 signal.
_________
To start a transmit/receive operation (SBUSY1 output: “L,” SBUSY1
output: “H”), input an “H” level signal into the SRDY1 input and an “L”
level signal into the_S__R__D_Y__1_ input, and also write transmit data into
the serial I/O1 register.
31
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Write to serial
I/O1 register
A:
S
CLK1
SCLK1
S
RDY1
S
RDY1
S
RDY1
S
BUSY1
S
BUSY1
S
BUSY1
SCLK1
A:
B:
Internal synchronous
clock selection
External synchronous
clock selection
Write to serial
I/O1 register
B:
Fig. 32 Handshake Operation at Serial I/O1 Mutual Connecting (1)
Write to serial
I/O1 register
A:
S
CLK1
SCLK1
S
RDY1
S
RDY1
S
RDY1
S
BUSY1
S
BUSY1
S
BUSY1
S
CLK1
A:
B:
Internal synchronous
clock selection
External synchronous
clock selection
Write to serial
I/O1 register
B:
Fig. 33 Handshake Operation at Serial I/O1 Mutual Connecting (2)
32
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ister (address 001D16) to “1.” For clock synchronous serial I/O, the
transmitter and the receiver must use the same clock for serial I/O2
operation. If an internal clock is used, transmit/receive is started by
a write signal to the serial I/O2 transmit/receive buffer register (TB/
RB) (address 001F16).
●Serial I/O2
Serial I/O2 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation during serial I/O2 operation.
(1) Clock Synchronous Serial I/O Mode
When P57 (SCLK22) is selected as a clock I/O pin, _S__R__D_Y__2_ output
function is invalid, and P56 (SCLK21) is used as an I/O port.
The clock synchronous serial I/O mode can be selected by setting
the serial I/O2 mode selection bit (b6) of the serial I/O2 control reg-
Data bus
Serial I/O2 control register
Address 001D16
Address 001F16
Receive buffer register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive shift register
P5
P5
4/RXD
Shift clock
“0”
Clock control circuit
6
/SCLK21
/SRDY2/ CLK22
IN
Serial I/O2 clock I/O pin selection bit
P5
7
S
“1”
“0”
“1”
Internal system clock selection bit
Serial I/O2 synchronous clock selection bit
X
“0”
BRG count source selection bit
Division ratio 1/(n+1)
Baud rate generator
Address 001616
1/4
X
CIN
“1”
1/2
BRG clock
switch bit
1/4
Falling edge detector
Clock control circuit
F/F
P57/SRDY2/SCLK22
Transmit shift register shift
completion flag (TSC)
Serial I/O2
clock I/O pin
selection bit
Shift clock
Transmit interrupt source selection bit
Transmit shift register
Transmit buffer register
P55/TXD
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Serial I/O2 status register
Address 001E16
Address 001F16
Data bus
Fig. 34 Block Diagram of Clock Synchronous Serial I/O2
Transmit/Receive shift clock
(1/2—1/2048 of internal
clock or external clock)
Serial I/O2 output TxD
Serial I/O2 input RxD
D
D
0
0
D
D
1
1
D
D
2
2
D
D
3
3
D
D
4
4
D
D
5
5
D
D
6
6
D
D
7
7
Receive enable signal SRDY2
Write-in signal to serial I/O2 transmit/receive
buffer register (address 001F16
)
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Overrun error (OE)
detection
Notes
1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting transmit interrupt source selection bit (TIC) of the serial I/O2
control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1.”
Fig. 35 Operation of Clock Synchronous Serial I/O2 Function
33
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Asynchronous Serial I/O (UART) Mode
The transmit and receive shift registers each have a buffer (the two
buffers have the same address in memory). Since the shift register
cannot be written to or read from directly, transmit data is written to
the transmit buffer, and receive data is read from the receive buffer.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer can receive 2-byte data continuously.
The asynchronous serial I/O (UART) mode can be selected by clear-
ing the serial I/O2 mode selection bit (b6) of the serial I/O2 control
register (address 001D16) to “0.” Eight serial data transfer formats
can be selected and the transfer formats used by the transmitter
and receiver must be identical.
Data bus
Serial I/O2 control register
Address 001D16
Address 001F16
Receive buffer full flag (RBF)
Receive interrupt request (RI)
OE
Receive buffer register
Character length selection bit
7 bit
ST detector
P54/RXD
Receive shift register
1/16
8 bit
UART control register
SP detector
PE FE
Address 001716
Clock control circuit
Serial I/O2 synchronous
clock selection bit
“0”
“1”
Serial I/O2 clock I/O pin
selection bit
P56/SCLK21
P5
7
/SRDY2/SCLK22
X
IN
Internal system clock selection bit
“0”
BRG count source
“1”
1/2
selection bit
“1”
Division ratio 1/(n+1)
Baud rate generator
X
CIN
Address 001616
BRG clock
1/4
switch bit
ST/SP/PA generator
Transmit shift register shift
completion flag (TSC)
1/16
Transmit interrupt source selection bit
Transmit shift register
P55/TXD
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
Transmit buffer register
Serial I/O2 status register
Address 001E16
Address 001F16
Data bus
Fig. 36 Block Diagram of UART Serial I/O2
Transmit or receive clock
Write-in signal to
transmit buffer register
TBE=0
TSC=0
TBE=1
TBE=0
TBE=1
TSC=1*
SP
D
0
D
1
D1
Serial I/O2 output T
X
D
ST
D0
SP
ST
* Generated at 2nd bit in 2-stop
bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit
Read-out signal from receive
buffer register
RBF=0
RBF=1
SP
RBF=1
SP
D0
D1
D1
ST
D0
ST
Serial I/O2 input RXD
Fig. 37 Operation of UART Serial I/O2 Function
34
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Serial I/O2 Control Register] SIO2CON (001D16
)
Writing “0” to the serial I/O2 enable bit (SIOE : b7 of the serial I/O2
control register) also clears all the status flags, including the error
flags.
The serial I/O2 control register contains eight control bits for serial
I/O2 functions.
All bits of the serial I/O2 status register are initialized to “0” at reset,
but if the transmit enable bit (b4) of the serial I/O2 control register
has been set to “1,” the transmit shift register shift completion flag
(b2) and the transmit buffer empty flag (b0) become “1.”
[UART Control Register] UARTCON (001716)
This is a 5 bit register containing four control bits (b0 to b3), which
are valid when UART is selected and set the data format of data
receive/transfer, and one control bit (b4), which is always valid and
sets the output structure of the P55/TxD pin.
[Serial I/O2 Transmit Buffer Register/Receive
Buffer Register] TB/RB (001F16)
[Serial I/O2 Status Register] SIO2STS (001E16)
The read-only serial I/O2 status register consists of seven flags (b0
to b6) which indicate the operating status of the serial I/O2 function
and various errors. Three of the flags (b4 to b6) are only valid in the
UART mode. The receive buffer full flag (b1) is cleared to “0” when
the receive buffer is read.
The transmit buffer and the receive buffer are located in the same
address. The transmit buffer is write-only and the receive buffer is
read-only. If a character bit length is 7 bits, the MSB of data stored in
the receive buffer is "0".
[Baud Rate Generator] BRG (001616)
The error detection is performed at the same time data is transferred
from the receive shift register to the receive buffer register, and the
receive buffer full flag is set. A writing to the serial I/O2 status regis-
ter clears error flags OE, PE, FE, and SE (b3 to b6, respectively).
The baud rate generator determines the baud rate for serial transfer.
With the 8-bit counter having a reload register, the baud rate genera-
tor divides the frequency of the count source by 1/(n+1), where n is
the value written to the baud rate generator.
b7
b0
b7
b0
Serial I/O2 control register
(SIO2CON : address 001D16)
Serial I/O2 status register
(SIO2STS : address 001E16)
BRG count source selection bit (CSS)
0: f(XIN) or f(XCIN)/2 or f(XCIN)
1: f(XIN)/4 or f(XCIN)/8 or f(XCIN)/4
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Serial I/O2 synchronous clock selection bit (SCS)
0: BRG/ 4
(when clock synchronous serial I/O is selected)
BRG/16 (UART is selected)
1: External clock input
(when clock synchronous serial I/O is selected)
External clock input/16 (UART is selected)
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
SRDY2 output enable bit (SRDY)
0: P57 pin operates as ordinary I/O pin
1: P57 pin operates as SRDY2 output pin
Overrun error flag (OE)
0: No error
1: Overrun error
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Serial I/O2 mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Not used (returns "1" when read)
Serial I/O2 enable bit (SIOE)
0: Serial I/O2 disabled
b7
b0
(pins P54 to P57 operate as ordinary I/O pins)
1: Serial I/O2 enabled
UART control register
(UARTCON : address 001716)
(pins P54 to P57 operate as serial I/O pins)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P55/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
BRG clock switch bit
0: XIN or XCIN (depends on internal system clock)
1: XCIN
Serial I/O2 clock I/O pin selection bit
0: SCLK21 (P57/SCLK22 pin is used as I/O port or SRDY2 output pin.)
1: SCLK22 (P56/SCLK21 pin is used as I/O port.)
Not used (return "1" when read)
Fig. 38 Structure of Serial I/O2 Related Register
35
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FLD Controller
The 38B5 group has fluorescent display (FLD) drive and control cir-
•Toff1 time set register
•Toff2 time set register
cuits.
•Port P0FLD/port switch register
The FLD controller consists of the following components:
•40 pins for FLD control pins
•FLDC mode register
•Port P2FLD/port switch register
•Port P8FLD/port switch register
•Port P8 FLD output control register
•FLD automatic display RAM (max. 160 bytes)
A gradation display mode can be used for bright/dark display as a
display function.
•FLD data pointer
•FLD data pointer reload register
•Tdisp time set register
Main
Local
Main address bus
data bus data bus
FLD/P P2
FLD/P P2
0
1
2
3
4
5
6
7
/FLD
/FLD
/FLD
/FLD
/FLD
/FLD
/FLD
/FLD
0
1
2
3
4
5
6
7
P2
FLD/P
FLD/P P2
P2
0F6016
8
8
8
8
8
FLD/P
FLD/P P2
P2
FLD/P
FLD/P P2
0EFA16
Local address bus
000416
FLD/P P0
FLD/P P0
0
1
2
3
4
5
6
7
/FLD
/FLD
8
9
P0
/FLD10
/FLD11
/FLD12
/FLD13
/FLD14
/FLD15
000016
FLD/P
FLD/P P0
P0
FLD/P
FLD/P P0
P0
0FFF16
FLD/P
FLD/P P0
0EF916
P1
P1
P1
P1
P1
P1
P1
P1
0
1
2
3
4
5
6
7
/FLD16
/FLD17
/FLD18
/FLD19
/FLD20
/FLD21
/FLD22
/FLD23
000216
P3
P3
P3
P3
P3
P3
P3
P3
0
1
2
3
4
5
6
7
/FLD24
/FLD25
/FLD26
/FLD27
/FLD28
/FLD29
/FLD30
FLDC mode register
(0EF416
)
FLD data pointer
reload register
/FLD31
000616
(0EF816
)
P8
0
1
2
3
4
5
6
7
/FLD32
/FLD33
/FLD34
/FLD35
/FLD36
/FLD37
/FLD38
FLD/P
FLD/P P8
FLD/P P8
FLD/P P8
Address
decoder
FLD data pointer
(0EF816
)
P8
P8
FLD/P
FLD/P
FLD/P P8
FLD/P P8
0EFB16
/FLD39
001016
FLD blanking interrupt
FLD digit interrupt
Timing generator
Fig. 39 Block Diagram for FLD Control Circuit
36
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[FLDC Mode Register] FLDM
The FLDC mode register is a 8-bit register respectively which is used
to control the FLD automatic display and to set the blanking time
Tscan for key-scan.
b7
b0
FLDC mode register
(FLDM: address 0EF416)
Automatic display control bit (P0, P1, P2, P3, P8)
0 : General-purpose mode
1 : Automatic display mode
Display start bit
0 : Stop display
1 : Display
(start to display by switching “0” to “1”)
Tscan control bits
00 : FLD digit interrupt (at rising edge of each digit)
01 : 1 ✕ Tdisp
FLD blanking interrupt
10 : 2 ✕ Tdisp
(at falling edge of the last digit)
11 : 3 ✕ Tdisp
Timing number control bit
0 : 16 timing mode
1 : 32 timing mode
Gradation display mode selection control bit
0 : Not selecting
1 : Selecting (Note)
Tdisp counter count source selection bit
0 : f(XIN)/16 or f(XCIN)/32
1 : f(XIN)/64 or f(XCIN)/128
High-breakdown voltage port drivability selection bit
0 : Drivability strong
1 : Drivability weak
Note: When a gradation display mode is selected, a number of timing is max. 16 timing.
(Set the timing number control bit to “0.”)
Fig. 40 Structure of FLDC Mode Register
37
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FLD automatic display pins
This setting is performed by writing a value into the FLD/port switch
register (addresses 0EF916 to 0EFB16) of each port.
When the automatic display control bits of the FLDC mode register
(address 0EF416) are set to “1,” the ports of P0, P1, P2, P3 and P8
are used as FLD automatic display pins.
This setting can be performed in units of bit. When “0” is set, the port
is set to the general-purpose port. When “1” is set, the port is set to
the FLD pin. There is no restriction on whether the FLD pin is to be
used as a segment pin or a digit pin.
When using the FLD automatic display mode, set each port to the
FLD pin or the general-purpose port using the respective switch reg-
ister in accordance with the number of segments and the number of
digits.
Table 7 Pins in FLD Automatic Display Mode
Port Name
Automatic Display Pins
Setting Method
P0, P2,
P80–P83
P1, P3
FLD0–FLD15
FLD32–FLD35
FLD16–FLD31
FLD36–FLD39
The individual bits of the FLD/port switch register (addresses 0EF916–0EFB16) can be set each pin
either FLD port (“1”) or general-purpose port (“0”).
None (FLD only)
P84–P87
The individual bits of the FLD/port switch register (address 0EFB16) can be set each pin to either
FLD port (“1”) or general-purpose port (“0”).
The output can be reversed by the port P8 FLD output control register (address 0EFC16).
The port output format is the CMOS output format. When using the port as a display pin, a driver
must be installed externally.
Setting example 2
Setting example 3
Setting example 4
Setting example 1
18
20
16
10
Number of segments
Number of digits
15
8
25
15
0
1
1
1
1
1
1
1
1
FLD
FLD
FLD
FLD
FLD
FLD
FLD
FLD
0
1
2
3
4
5
6
7
(SEG
(SEG
(SEG
(SEG
(SEG
(SEG
(SEG
(SEG
1)
2)
3)
4)
5)
6)
7)
8)
P2
P2
P2
P2
P2
P2
P2
P2
0
1
2
3
4
5
6
7
0
0
1
1
1
1
1
1
P2
0
1
0
0
0
0
0
0
1
1
0
1
2
3
4
5
P2
P2
P2
P2
P2
P2
Port P2
0
0
0
0
0
0
0
P2
FLD
FLD
FLD
FLD
FLD
FLD
2(SEG
3(SEG
4(SEG
5(SEG
6(SEG
7(SEG
1)
2)
3)
4)
5)
6)
FLD
FLD
4
(SEG
1
)
)
5(SEG
2
1
1
1
1
1
1
1
1
FLD
FLD
8
(DIG
1
)
1
FLD
8
(SEG
1
)
FLD
8
(SEG
(SEG10
FLD10(SEG11
9
)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FLD
FLD
6
(SEG
3
)
)
Port P0
9(DIG
2)
0
0
0
0
0
1
1
P01
P02
P03
P04
P05
FLD
9
)
7(SEG
4
FLD10(DIG
FLD11(DIG
FLD12(DIG
FLD13(DIG
FLD14(DIG
FLD15(DIG
3
)
)
)
FLD
FLD
8
(SEG
5)
4
FLD11(SEG12
FLD12(SEG13
)
)
9
(SEG
6)
5
6
7
8
)
)
)
)
FLD10(SEG
FLD11(SEG
FLD12(SEG
7
8
9
)
)
)
FLD13(SEG14
FLD14(SEG15
FLD15(SEG16
)
)
FLD14(SEG
FLD15(SEG
2
)
)
)
FLD13(SEG10)
3
FLD16(DIG
FLD17(DIG
FLD18(DIG
FLD19(DIG
FLD20(DIG
FLD21(DIG
FLD22(DIG
FLD23(DIG
1)
2)
3)
4)
5)
6)
7)
8)
1
1
1
1
1
1
1
1
FLD16(DIG
9
)
Port P1
FLD16(DIG
FLD17(DIG
FLD18(DIG
FLD19(DIG
1
2
3
4
)
1
1
1
1
0
0
0
0
FLD16(DIG
FLD17(DIG
FLD18(DIG
FLD19(DIG
FLD20(DIG
FLD21(DIG
FLD22(DIG
FLD23(DIG
1
2
3
4
5
6
7
8
)
)
)
)
)
)
)
)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FLD17(DIG10
FLD18(DIG11
FLD19(DIG12
FLD20(DIG13
FLD21(DIG14
FLD22(DIG15
FLD23(DIG16
)
)
)
)
)
)
)
)
)
)
FLD20(SEG
FLD21(SEG
FLD22(SEG
FLD23(SEG
4
5
6
7
)
)
)
)
FLD24(DIG17
FLD25(DIG18
FLD26(DIG19
FLD27(DIG20
)
)
)
)
Port P3
FLD24(DIG
9
)
1
1
1
1
0
0
0
0
FLD24(SEG
8
9
)
)
1
1
1
1
0
0
0
0
FLD24(DIG9)
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
FLD25(DIG10
FLD26(DIG11
FLD27(DIG12
FLD28(DIG13
FLD29(DIG14
FLD30(DIG15
)
)
)
)
)
)
FLD25(SEG
FLD25(DIG10
)
FLD14(SEG11
)
FLD26(SEG10
FLD27(SEG11
)
)
FLD15(SEG12
)
FLD28(SEG
FLD29(SEG
7
)
FLD26(SEG13
FLD27(SEG14
FLD28(SEG15
FLD29(SEG16
)
)
)
)
FLD28(DIG
FLD29(DIG
FLD30(DIG
FLD31(DIG
5
6
7
8
)
)
)
)
8)
FLD30(SEG
9)
FLD31(SEG10
)
FLD31(SEG17
)
FLD32(SEG11
FLD33(SEG12
FLD34(SEG13
FLD35(SEG14
FLD36(SEG15
FLD37(SEG16
FLD38(SEG17
FLD39(SEG18
)
1
1
1
1
1
1
1
1
1
FLD32(SEG18
FLD33(SEG19
FLD34(SEG20
FLD35(SEG21
FLD36(SEG22
FLD37(SEG23
FLD38(SEG24
FLD39(SEG25
)
)
)
)
)
)
)
)
FLD32(SEG12
FLD33(SEG13
FLD34(SEG14
FLD35(SEG15
)
)
)
)
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
P80
P81
P82
P83
P84
P85
P86
P87
Port P8
)
1
1
1
0
0
0
0
)
)
)
)
)
)
P84
P85
P86
P87
Fig. 41 Segment/Digit Setting Example
38
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FLD automatic display RAM
[FLD Data Pointer and FLD Data Pointer Reload Register]
FLDDP (0EF816)
Both the FLD data pointer and FLD data pointer reload register are
8-bit registers assigned at address 0EF816. When writing data to this
address, the data is written to the FLD data pointer reload register;
when reading data from this address, the value in the FLD data pointer
is read.
The FLD automatic display RAM uses the 160 bytes of addresses
0F6016 to 0FFF16. For FLD, the 3 modes of 16-timing ordinary mode,
16-timing•gradation display mode and 32-timing mode are available
depending on the number of timings and the presence/absence of
gradation display.
The automatic display RAM in each mode is as follows:
(1) 16-timing•Ordinary Mode
The 80 bytes of addresses 0FB016 to 0FFF16 are used as a FLD
display data store area. Because addresses 0F6016 to 0FAF16
are not used as the automatic display RAM, they can be the ordi-
nary RAM or serial I/O automatic reverse RAM.
(2) 16-timing•Gradation Display Mode
The 160 bytes of addresses 0F6016 to 0FFF16 are used. The 80
bytes of addresses 0FB016 to 0FFF16 are used as an FLD dis-
play data store area, while the 80 bytes of addresses 0F6016 to
0FAF16 are used as a gradation display control data store area.
(3) 32-timing Mode
The 160 bytes of addresses 0F6016 to 0FFF16 are used as an
FLD display data store area.
16-timing•ordinary mode
Not used
16-timing•gradation display mode
32-timing mode
0F6016
0F6016
0F6016
Gradation display
control data stored
area
1 to 32 timing display
data stored area
0FB016
0FB016
0FFF16
1 to 16 timing display
data stored area
1 to 16 timing display
data stored area
0FFF16
0FFF16
Fig. 42 FLD Automatic Display RAM Assignment
39
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data setup
(1) 16-timing•Ordinary Mode
Number of FLD segments: 15
Number of timing: 8
(FLD data pointer reload register = 7)
The area of addresses 0FB016 to 0FFF16 are used as a
FLD automatic display RAM.
Bit
Address
7
6
5
4
3
2
1
0
0FB016
The last timing
(The last data of FLDP2)
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
0FEA16
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
0FFA16
0FFB16
0FFC16
0FFD16
0FFE16
0FFF16
Note:
When data is stored in the FLD automatic display RAM,
the last data of FLD port P2 is stored at address 0FB016,
the last data of FLD port P0 is stored at address 0FC016,
the last data of FLD port P1 is stored at address 0FD016,
the last data of FLD port P3 is stored at address 0FE016,
and the last data of FLD port P8 is stored at address 0FF016,
to assign in sequence from the last data respectively.
The first data of the FLD port P2, P0, P1, P3, and P8 is stored at
an address which adds the value of (the timing number – 1) to the
corresponding address 0FB016, 0FC016, 0FD016, 0FE016, and
0FF016.
Timing for start
(The first data of FLDP2)
FLDP2 data area
The last timing
(The last data of FLDP0)
Set the FLD data pointer reload register to the value given by the
number of digits – 1. “1” is always written to bit 6, and “0” is
always written to bit 5. Note that “0” is always read from bits 6
and 5 when reading.
Timing for start
(The first data of FLDP0)
(2) 16-timing•Gradation Display Mode
FLDP0 data area
Display data setting is performed in the same way as that of the
16-timing•ordinary mode. Gradation display control data is
arranged at an address resulting from subtracting 005016 from
the display data store address of each timing and pin. Bright dis-
play is performed by setting “0,” and dark display is performed by
setting “1.”
The last timing
(The last data of FLDP1)
(3) 32-timing Mode
The area of addresses 0F6016 to 0FFF16 are used as a
FLD automatic display RAM.
Timing for start
(The first data of FLDP1)
FLDP1 data area
When data is stored in the FLD automatic display RAM,
the last data of FLD port P2 is stored at address 0F6016,
the last data of FLD port P0 is stored at address 0F8016,
the last data of FLD port P1 is stored at address 0FA016,
the last data of FLD port P3 is stored at address 0FC016,
and the last data of FLD port P8 is stored at address 0FE016,
to assign in sequence from the last data respectively.
The first data of the FLD port P2, P0, P1, P3, and P8 is stored at
an address which adds the value of (the timing number – 1) to the
corresponding address 0F6016, 0F8016, 0FA016, 0FC016, and
0FE016.
The last timing
(The last data of FLDP3)
Timing for start
(The first data of FLDP3)
FLDP3 data area
Set the FLD data pointer reload register to the value given by the
number of digits–1. “1” is always written to bit 6, and “0” is always
written to bit 5. Note that “0” is always read from bits 6 and 5
when reading.
The last timing
(The last data of FLDP8)
Timing for start
(The first data of FLDP8)
FLDP8 data area
shaded area is used for segment.
shaded area is used for digit.
Fig. 43 Example of Using the FLD Automatic Display RAM in
16-timing•Ordinary Mode
40
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Number of FLD segments: 25
Number of timing: 15
(FLD data pointer reload register = 14)
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Address
Address
0FB016
0F6016
0F6116
0F6216
0F6316
0F6416
0F6516
0F6616
0F6716
0F6816
0F6916
0F6A16
0F6B16
0F6C16
0F6D16
0F6E16
0F6F16
0F7016
0F7116
0F7216
0F7316
0F7416
0F7516
0F7616
0F7716
0F7816
0F7916
0F7A16
0F7B16
0F7C16
0F7D16
0F7E16
0F7F16
0F8016
0F8116
0F8216
0F8316
0F8416
0F8516
0F8616
0F8716
0F8816
0F8916
0F8A16
0F8B16
0F8C16
0F8D16
0F8E16
0F8F16
0F9016
0F9116
0F9216
0F9316
0F9416
0F9516
0F9616
0F9716
0F9816
0F9916
0F9A16
0F9B16
0F9C16
0F9D16
0F9E16
0F9F16
0FA016
0FA116
0FA216
0FA316
0FA416
0FA516
0FA616
0FA716
0FA816
0FA916
0FAA16
0FAB16
0FAC16
0FAD16
0FAE16
0FAF16
The last timing
The last timing
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
0FEA16
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
0FFA16
0FFB16
0FFC16
0FFD16
0FFE16
0FFF16
Note:
(The last data of FLDP2)
(The last data of FLDP2)
FLDP2 gradation
display data area
FLDP2 data area
Timing for start
(The first data of FLDP2)
The last timing
Timing for start
(The first data of FLDP2)
The last timing
(The last data of FLDP0)
(The last data of FLDP0)
FLDP0 gradation
display data area
FLDP0 data area
Timing for start
(The first data of FLDP0)
The last timing
Timing for start
(The first data of FLDP0)
The last timing
(The last data of FLDP1)
(The last data of FLDP1)
FLDP1 gradation
display data area
FLDP1 data area
Timing for start
(The first data of FLDP1)
The last timing
Timing for start
(The first data of FLDP1)
The last timing
(The last data of FLDP3)
(The last data of FLDP3)
FLDP3 gradation
display data area
FLDP3 data area
Timing for start
(The first data of FLDP3)
The last timing
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP8)
(The last data of FLDP8)
FLDP8 gradation
display data area
FLDP8 data area
Timing for start
(The first data of FLDP8)
Timing for start
(The first data of FLDP8)
shaded area is used for segment.
shaded area is used for digit.
Note:
shaded area is used for gradation display data.
Fig. 44 Example of Using the FLD Automatic Display RAM in 16-timing•Gradation Display Mode
41
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Number of FLD segments: 18
Number of timing: 20
(FLD data pointer reload register = 19)
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Address
Address
The last timing
0FB016
0F6016
0F6116
0F6216
0F6316
0F6416
0F6516
0F6616
0F6716
0F6816
0F6916
0F6A16
0F6B16
0F6C16
0F6D16
0F6E16
0F6F16
0F7016
0F7116
0F7216
0F7316
0F7416
0F7516
0F7616
0F7716
0F7816
0F7916
0F7A16
0F7B16
0F7C16
0F7D16
0F7E16
0F7F16
0F8016
0F8116
0F8216
0F8316
0F8416
0F8516
0F8616
0F8716
0F8816
0F8916
0F8A16
0F8B16
0F8C16
0F8D16
0F8E16
0F8F16
0F9016
0F9116
0F9216
0F9316
0F9416
0F9516
0F9616
0F9716
0F9816
0F9916
0F9A16
0F9B16
0F9C16
0F9D16
0F9E16
0F9F16
0FA016
0FA116
0FA216
0FA316
0FA416
0FA516
0FA616
0FA716
0FA816
0FA916
0FAA16
0FAB16
0FAC16
0FAD16
0FAE16
0FAF16
(The last data of FLDP2)
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
0FEA16
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
0FFA16
0FFB16
0FFC16
0FFD16
0FFE16
0FFF16
Note:
Timing for start
(The first data of FLDP1)
FLDP2 data area
The last timing
(The last data of FLDP3)
Timing for start
(The first data of FLDP2)
FLDP3 data area
The last timing
(The last data of FLDP0)
Timing for start
(The first data of FLDP3)
FLDP0 data area
The last timing
(The last data of FLDP8)
Timing for start
(The first data of FLDP0)
FLDP8 data area
The last timing
(The last data of FLDP1)
Timing for start
(The first data of FLDP8)
FLDP1 data area
shaded area is used for segment.
shaded area is used for digit.
Fig. 45 Example of Using the FLD Automatic Display RAM in 32-timing Mode
42
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Digit data protect function
The FLD automatic display RAM is provided with a data protect
function that disables the RAM area data to be rewritten as digit
data.
This function can disable data from being written in optional bits in
the RAM area corresponding to P1 to P3. A programming load can
be reduced by protecting an area that requires no change after
data such as digit data is written.
Write digit data beforehand; then set “1” in the corresponding bits.
With this, the setting is completed.
The data protect area becomes the maximum RAM area of P1 and
P3. For example, when bit 0 of P1 is protected in the 16-
timing•ordinary mode, bits 0 of RAM addresses 0FD016 to 0FDF16
can be protected. Likewise, in the 16-timing•gradation display mode,
bits 0 of addresses 0FD016 to 0FDF16 and 0F8016 to 0F8F16 can be
protected. In the 32-timing mode, bits 0 of addresses 0FA016 to
0FBF16 can be protected.
b7
b7
b0
b0
P1FLDRAM write disable register
(P1FLDRAM : address 0EF216
P3FLDRAM write disable register
)
(P3FLDRAM : address 0EF316
FLDRAM corresponding to P3
FLDRAM corresponding to P3
)
FLDRAM corresponding to P1
FLDRAM corresponding to P1
0
0
1
1
FLDRAM corresponding to P1
FLDRAM corresponding to P1
2
3
FLDRAM corresponding to P3
FLDRAM corresponding to P3
2
3
FLDRAM corresponding to P1
FLDRAM corresponding to P1
FLDRAM corresponding to P1
FLDRAM corresponding to P1
4
5
6
7
FLDRAM corresponding to P3
FLDRAM corresponding to P3
FLDRAM corresponding to P3
FLDRAM corresponding to P3
4
5
6
7
0: Operating normally
1: Write disabled
0: Operating normally
1: Write disabled
Fig. 46 Structure of FLDRAM Write Disable Register
43
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Setting method when using the grid scan type FLD
When using the grid scan type FLD, set “1” in the RAM area corre-
sponding to the digit ports that output “1” at each timing. Set “0” in
the RAM area corresponding to the other digit ports.
Number of FLD segments: 16
Number of timing: 10
(FLD data pointer reload register = 9)
Bit
7
6
5
4
3
2
1
0
Address
0FB016
0FB116
0FB216
The last timing
(The last data of FLDP2)
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
Number of timing: 10
FLDP2 data area
The first second third.......................9th
10th
Timing for start
(The first data of FLDP2)
DIG10 (P3
1
)
)
)
DIG9 (P3
0
7
The last timing
(The last data of FLDP0)
DIG8 (P1
FLDP0 data area
Timing for start
(The first data of FLDP0)
DIG2 (P1
1
)
)
The last timing
(The last data of FLDP1)
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
DIG1 (P1
0
Segment output
FLDP1 data area
Timing for start
(The first data of FLDP1)
Fig. 47 Example of Digit Timing Using Grid Scan Type
The last timing
(The last data of FLDP3)
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
FLDP3 data area
0FE816
0FE916
0FEA16
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
0FFA16
0FFB16
0FFC16
0FFD16
0FFE16
0FFF16
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP8)
FLDP8 data area
Timing for start
(The first data of FLDP8)
Note:
shaded area is used for segment.
shaded area is used for digit.
Fig. 48 Example of Using the FLD Automatic Display RAM
Using Grid Scan Type
44
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing setting
Key-scan
Each timing is set by the FLDC mode register, Tdisp time set regis-
ter, Toff1 time set register, and Toff2 time set register.
•Tdisp time setting
When a key-scan is performed with the segment during key-scan
blanking period Tscan, take the following sequence:
1. Write “0” to bit 0 of the FLDC mode register (address 0EF416).
2. Set the port corresponding to the segment for key-scan to the
output port.
Set the Tdisp time by the Tdisp counter count source selection bit of
the FLDC mode register and the Tdisp time set register.
Supposing that the value of the Tdisp time set register is n, the
Tdisp time is represented as Tdisp = (n+1) ✕ t (t: count source
synchronization).
3. Perform the key-scan.
4. After the key-scan is performed, write “1” to bit 0 of FLDC mode
register (address 0EF416).
When the Tdisp counter count source selection bit of the FLDC mode
register is “0” and the value of the Tdisp time set register is 200
(C816), the Tdisp time is: Tdisp = (200+1) ✕ 4 (at XIN= 4 MHz) = 804
µs. When reading the Tdisp time set register, the value in the
counter is read out.
■ Note
When performing a key-scan according to the above steps 1 to 4,
take the following points into consideration.
1. Do not set “0” in bit 1 of the FLDC mode register (address 0EF416).
2. Do not set “1” in the ports corresponding to digits.
•Toff1 time setting
Set the Toff1 time by the Toff1 time set register.
Supposing that the value of the Toff1 time set register is n1, the
Toff1 time is represented as Toff1 = n1 ✕ t.
P84 to P87 FLD Output Reverse Function
P84 to P87 are provided with a function to reverse the polarity of the
FLD output. This function is useful in adjusting the polarity when
using an externally installed driver.
When the Tdisp counter count source selection bit of the FLDC mode
register is “0” and the value of the Toff1 time set register is 30
(1E16), Toff1 = 30 ✕ 4 (at XIN = 4 MHz) = 120 µs.
•Toff2 time setting
The output polarity can be reversed by setting bit 0 of the port P8
FLD output control register to “1.”
Set the Toff2 time by the Toff2 time set register.
Supposing that the value of the Toff2 time set register is n2, the
Toff2 time is represented as Toff2 = n2 ✕ t.
When the Tdisp counter count source selection bit of the FLDC mode
register is “0” and the value of the Toff2 time set register is 180
(B416), Toff2 = 180 ✕ 4 (at XIN = 4 MHz) = 720 µs.
This Toff2 time setting is valid only for FLD ports which are in the
gradation display mode and whose gradation display control RAM
value is “1.”
FLD automatic display start
To perform FLD automatic display, set the following registers.
•Port P0FLD/port switch register
•Port P2FLD/port switch register
•Port P8FLD/port switch register
•FLDC mode register
•Tdisp time set register
•Toff1 time set register
•Toff2 time set register
•FLD data pointer
FLD automatic display mode is selected by writing “1” to the bit 0 of
the FLDC mode register (address 0EF416), and the automatic dis-
play is started by writing “1” to bit 1. During FLD automatic display,
bit 1 of the FLDC mode register (address 0EF416) always keeps “1,”
and FLD automatic display can be interrupted by writing “0” to bit 1.
45
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Repeat synchronous
Tdisp
Tn Tn-1 Tn-2
Tscan
T4
T3
T2
T1
Segment
Digit output
Segment setting by software
FLD digit interrupt request occurs at the rising
edge of digit (each timing).
FLD blanking interrupt request occurs
at the falling edge of the last timing.
Segment
Digit
Toff1
Tdisp
Segment
Digit
When a gradation display mode is selected
Pin under the condition that bit 5 of the
FLDC mode register is “1,” and the
corresponding gradation display control
data value is “1.”
Toff1
Toff2
Tdisp
n: Number of timing
Fig. 49 FLDC Timing
b7
b0
P8FLD output control register
(P8FLDCON: address 0EFC16)
P84–P87 FLD output reverse bits
0: Output normally
1: Reverse output
Not available (returns “0” when read)
Fig. 50 Structure of P8FLD Output Control Register
46
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D Converter
conversion interrupt request bit to “1.”
The 38B5 group has a 10-bit A-D converter. The A-D converter per-
Note that the comparator is constructed linked to a capacitor, so set
f(XIN) to at least 250 kHz during A-D conversion. Use a CPU system
clock dividing the main clock XIN as the internal system clock.
forms successive approximation conversion.
[A-D Conversion Register] AD
One of these registers is a high-order register, and the other is a low-
order register. The high-order 8 bits of a conversion result is stored
in the A-D conversion register (high-order) (address 003416), and
the low-order 2 bits of the same result are stored in bit 7 and bit 6 of
the A-D conversion register (low-order) (address 003316).
During A-D conversion, do not read these registers.
b7
b0
A-D control register
(ADCON: address 003216
)
Analog input pin selection bits
0000: P7 /AN
0001: P7 /AN
0
0
1
1
0010: P7
0011: P7
0100: P7
0101: P7
0110: P7
0111: P7
1000: P6
1001: P6
1010: P6
1011: P6
2
3
4
5
6
7
2
3
4
5
/AN
/AN
/AN
/AN
/AN
/AN
/SRDY1/AN
/AN
/INT
2
3
4
5
6
7
[A-D Control Register] ADCON
This register controls A-D converter. Bits 3 to 0 are analog input pin
selection bits. Bit 4 is an AD conversion completion bit and “0” during
A-D conversion. This bit is set to “1” upon completion of A-D conver-
sion.
8
9
4
/SBUSY1/AN10
/SSTB1/AN11
A-D conversion is started by setting “0” in this bit.
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between AVSS
Not used (returns “0” when read)
and VREF, and outputs the divided voltages.
b7
b0
[Channel Selector]
A-D conversion register (high-order)
(ADH: address 003416
)
The channel selector selects one of the input ports P77/AN7–P70/
________
AN0, and P65/SSTB1/AN11–P62/SRDY1/AN8 and inputs it to the com-
parator.
AD conversion result stored bits
When port P64 is selected as an analog input pin, an external inter-
rupt function (INT4) is invalid.
b7
b0
A-D conversion register (low-order)
(ADL: address 003316
)
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input
voltage with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
Not used (returns “0” when read)
AD conversion result stored bits
Fig. 51 Structure of A-D Control Register
Data bus
b7
b0
A-D control register
4
P70
P71
P72
P73
P74
P75
P76
P77
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
A-D control circuit
A-D interrupt request
Comparator
A-D conversion register (H) A-D conversion register (L)
(Address 003416
)
(Address 003316)
Resistor ladder
P6
2
/SRDY1/AN
P6 /AN
/SBUSY1/AN10
P6 /SSTB1/AN11
8
3
9
P64/INT4
AVSS
VREF
5
Fig. 52 Block Diagram of A-D Converter
47
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Pulse Width Modulation (PWM)
The 38B5 group has a PWM function with a 14-bit resolution. When
the oscillation frequency XIN is 4 MHz, the minimum resolution bit
width is 250 ns and the cycle period is 4096 µs. The PWM timing
generator supplies a PWM control signal based on a signal that is
the frequency of the XIN clock.
The explanation in the rest of this data sheet assumes XIN = 4 MHz.
Data bus
PWM register (low-order)
It is set to “1”
when write.
(address 001516
)
bit7
bit5
bit0
bit0
bit7
PWM register (high-order)
(address 001416
)
PWM latch (14-bit)
MSB
LSB
14
P87 latch
P87/PWM0
PWM
14-bit PWM circuit
P8
7/PWM output
selection bit
When an internal
X
CIN
1/2
system clock
selection bit is set
to “0”
P87
/PWM output
selection bit
(64 µs cycle)
Timing
“1”
“0”
generating
unit for PWM
P8 direction
7
X
IN
(4096 µs cycle)
register
(4MHz)
Fig. 53 PWM Block Diagram
48
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1. Data setup
The PWM output pin also function as port P87. Set port P87 to be the
PWM output pin by setting bit 0 of the PWM control register (address
002616) to “1.” The high-order 8 bits of output data are set in the
high-order PWM register PWMH (address 001416) and the low-order
6 bits are set in the low-order PWM register PWML (address 001516).
3. Transfer from register to latch
Data written to the PWML register is transferred to the PWM latch
once in each PWM period (every 4096 µs), and data written to the
PWMH register is transferred to the PWM latch once in each sub-
period (every 64 µs). When the PWML register is read, the contents
of the latch are read. However, bit 7 of the PWML register indicates
whether the transfer to the PWM latch is completed; the transfer is
completed when bit 7 is “0.”
2. PWM operation
The timing of the 14-bit PWM function is shown in Figure 56.
The 14-bit PWM data is divided into the low-order 6 bits and the
high-order 8 bits in the PWM latch.
Table 8 Relationship between Low-order 6-bit Data and Setting
Period of ADD Bit
Low-order
The high-order 8 bits of data determine how long an “H” level signal
is output during each sub-period. There are 64 sub-periods in each
period, and each sub-period t is 256 ✕✕ τ (= 64 µs) long. The signal’s
“H” has a length equal to N times τ, and its minimum resolution = 250
ns.
6-bit data
Sub-periods tm lengthened (m = 0 to 63)
LSB
0 0 0 0 0 0 None
0 0 0 0 0 1 m = 32
0 0 0 0 1 0 m = 16, 48
The last bit of the sub-period becomes the ADD bit which is specified
either “H” or “L,” by the contents of PWML. As shown in Table 8, the
ADD bit is decided either “H” or “L.”
0 0 0 1 0 0 m = 8, 24, 40, 56
0 0 1 0 0 0 m = 4, 12, 20, 28, 36, 44, 52, 60
0 1 0 0 0 0 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62
1 0 0 0 0 0 m = 1, 3, 5, 7, .................................................., 57, 59, 61, 63
That is, only in the sub-period tm shown in Table 8 in the PWM cycle
period T = 64t, the “H” duration is lengthened during the minimum
resolution width τ period in comparison with the other period.
For example, if the high-order eight bits of the 14-bit data are “0316”
and the low-order six bits are “0516,” the length of the “H” level output
in sub-periods t8, t24, t32, t40 and t56 is 4 τ, andits length 3 τ in all other
sub-periods.
Time at the “H” level of each sub-period almost becomes equal be-
cause the time becomes length set in the high-order 8 bits or be-
comes the value plus τ, and this sub-period t (= 64 µs, approximate
15.6 kHz) becomes cycle period approximately.
4096 µs
64 µs
64 µs
m = 7
64 µs
64 µs
64 µs
m = 0
m = 8
m = 9
m = 63
15.75 µs
15.75 µs
15.75 µs
16.0 µs
15.75 µs
15.75 µs
15.75 µs
Pulse width modulation register H: 00111111
Pulse width modulation register L: 000101
Sub-periods where “H” pulse width is 16.0 µs: m = 8, 24, 32, 40, 56
Sub-periods where “H” pulse width is 15.75 µs: m = all other values
Fig. 54 PWM Timing
49
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
PWM control register
(PWMCON: address 002616
)
P87/PWM output selection bit
0: I/O port
1: PWM output
Not used (return “0” when read)
Fig. 55 Structure of PWM Control Register
Data 6A16 stored at address 001416
5916 6A16
Data 2416 stored at address 001516
1316 A416
Data 7B16 stored at address 001416
PWM register
(high-order)
7B16
Bit 7 cleared after transfer
2416
Data 3516 stored at address 001516
3516
PWM register
(low-order)
Transfer from register to latch
1AA416
Transfer from register to latch
1EF516
B516
1EE416
PWM latch
(14-bit)
165316
1A9316
1AA416
When bit 7 of PWML is “0,” transfer
from register to latch is disabled.
T = 4096 µs
(64 ✕ 64 µs)
t = 64 µs
6A 6B 6A 6B 6A 6B 6A 6B 6A 6B 6B 6B 6A 6B 6A 6B 6A 6B 6A
6B 6A 6B 6A 6B 6A 6B 6A
(Example 1)
PWM output
1
Low-order 6-bits
output
5
5
5
5
5
2
5
5
5
5
5
5
5
5
5
H = 6A16
L = 2416
6B16............36 times
(107)
6A16............28 times
(106)
106 ✕ 64 +36
6A 6A 6A 6A 6B 6A 6B 6A 6B 6A 6A 6A 6B 6A 6B 6A 6B 6A 6A
6A 6B 6A 6B 6A 6B 6A 6A
(Example 2)
PWM output
Low-order 6 bits
output
4
3
4
4
3
4
4
3
4
H = 6A16
6B16............24 times
6A16............40 times
106 ✕ 64 +24
L = 1816
t = 64 µs
(256 ✕ 0.25 µs)
Minimum bit width
τ
= 0.25 µs
………
………
PWM output
2
………
………
6B 6A 69 68 67
ADD
02 01 00 FF FE FD FC
02 01
6A 69 68 67
02 01
ADD
02 01 00 FF FE FD FC
.............
………
8-bit counter
97 96 95
97 96 95
The ADD portions with
additional are determined
either “H” or “L” by low-order
6-bit data.
τ
“H” period length specified by PWMH
256 (64 µs), fixed
τ
Fig. 56 14-bit PWM Timing
50
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt Interval Determination Function
The 38B5 group has an interrupt interval determination circuit.
This interrupt interval determination circuit has an 8-bit binary up
counter. Using this counter, it determines a duration of time from the
rising edge (falling edge) of an input signal pulse on the P47/INT2 pin
to the rising edge (falling edge) of the signal pulse that is input next.
How to determine the interrupt interval is described below.
1. Enable the INT2 interrupt by setting bit 2 of the interrupt control
register 1 (address 003E16). Select the rising interval or falling
interval by setting bit 2 of the interrupt edge selection register
(address 003A16).
Noise filter
The P47/INT2 pin builds in the noise filter.
The noise filter operation is described below.
1. Select the sampling clock of the input signal with bits 2 and 3 of
the interrupt interval determination control register. When not
using the noise filter, set “00.”
2. The P47/INT2 input signal is sampled in synchronization with the
selected clock. When sampling the same level signal in a series
of three sampling, the signal is recognized as the interrupt
signal, and the interrupt request occurs.
When setting bit 4 of interrupt interval determination control
register to “1,” the interrupt request can occur at both rising and
falling edges.
2. Set bit 0 of the interrupt interval determination control register
(address 003116) to “1” (interrupt interval determination operat-
ing).
When using the noise filter, set the minimum pulse width of the
INT2 input signal to 3 cycles or more of the sample clock.
3. Select the sampling clock of 8-bit binary up counter by setting bit
1 of the interrupt interval determination control register. When
writing “0,” f(XIN)/128 is selected (the sampling interval: 32 µs at
f(XIN) = 4.19 MHz); when “1,” f(XIN)/256 is selected (the sampling
interval: 64 µs at f(XIN) = 4.19 MHz).
Note: In the low-speed mode (CM7 = 1), the interrupt interval deter-
mination function cannot operate.
4. When the signal of polarity which is set on the INT2 pin (rising or
falling edge) is input, the 8-bit binary up counter starts count-
ing up of the selected counter sampling clock.
5. When the signal of polarity above 4 is input again, the value of the
8-bit binary up counter is transferred to the interrupt interval
determination register (address 003016), and the remote control
interrupt request occurs. Immediately after that, the 8-bit binary
up counter continues to count up again from “0016.”
6. When count value reaches “FF16,” the 8-bit binary up counter stops
counting up. Then, simultaneously when the next counter sam-
pling clock is input, the counter sets value “FF16” to the interrupt
interval determination register to generate the counter overflow
interrupt request.
f(XIN)/128
f(XIN)/256
Counter sampling
clock selection bit
8-bit binary up
counter
Counter overflow
interrupt request
or remote control
interrupt request
INT2 interrupt input
Noise filter
Interrupt interval
determination register
address 003016
One-sided/both-sided
detection selection bit
Noise filter sampling
clock selection bit
1/128
1/64
Data bus
1/32
Divider
f(XIN
)
Fig. 57 Interrupt Interval Determination Circuit Block Diagram
51
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Interrupt interval determination control register
(IIDCON: address 003116
)
Interrupt interval determination circuit operating selection bit
0 : Stopped
1 : Operating
Counter sampling clock selection bit
0 : f(XIN)/128
1 : f(XIN)/256
Noise filter sampling clock selection bits (INT
2)
00 : Filter stop
01 : f(XIN)/32
10 : f(XIN)/64
11 : f(XIN)/128
One-sided/both-sided edge detection selection bit
0 : One-sided edge detection
1 : Both-sided edge detection (can be used when using a noise filter)
Not used (return “0” when read)
Fig. 58 Structure of Interrupt Interval Determination Control Register
(When IIDCON4 = “0”)
Noise filter
sampling clock
INT pin
2
Acceptance of
interrupt
Counter sampling
clock
FF
N
FE
6
5
4
~
3
8-bit binary up
counter value
~
3
2
2
1
1
1
0
0
0
FF
6
N
Interrupt interval
determination
register value
N
FF
6
Remote control
interrupt request
Counter overflow
interrupt request
Remote control
interrupt request
Fig. 59 Interrupt Interval Determination Operation Example (at rising edge active)
(When IIDCON
Noise filter
4 = “1”)
sampling clock
INT2 pin
Acceptance of
interrupt
Counter sampling
clock
FF
FE
N
3
2
2
2
2
1
1
1
3
1
1
8-bit binary up
counter value
0
0
0
0
0
N
2
3
2
FF
Interrupt interval
determination
register value
N
2
FF
2
Counter overflow
interrupt request
Remote control
interrupt request
Remote control
interrupt request
Remote control
interrupt request
Remote control
interrupt request
Fig. 60 Interrupt Interval Determination Operation Example (at both-sided edge active)
52
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Watchdog Timer
“0,” the underflow signal of watchdog timer L becomes the count
source. The detection time is set then to f(XIN) = 2.1 s at 4 MHz
frequency and f(XCIN) = 512 s at 32 kHz frequency.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because
of a software runaway). The watchdog timer consists of an 8-bit watch-
dog timer L and a 12-bit watchdog timer H.
When this bit is set to “1,” the count source becomes the signal
divided by 8 for f(XIN) (or divided by 16 for f(XCIN)). The detection
time in this case is set to f(XIN) = 8.2 ms at 4 MHz frequency and
f(XCIN) = 2 s at 32 KHz frequency. This bit is cleared to “0” after
resetting.
●Standard operation of watchdog timer
When any data is not written into the watchdog timer control register
(address 002B16) after resetting, the watchdog timer is in the stop
state. The watchdog timer starts to count down by writing an optional
value into the watchdog timer control register (address 002B16) and
an internal reset occurs at an underflow of the watchdog timer H.
Accordingly, programming is usually performed so that writing to the
watchdog timer control register (address 002B16) may be started
before an underflow. When the watchdog timer control register
(address 002B16) is read, the values of the 6 high-order bits of the
watchdog timer H, STP instruction disable bit, and watchdog timer H
count source selection bit are read.
(3) Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 002B16) permits
disabling the STP instruction when the watchdog timer is in opera-
tion.
When this bit is “0,” the STP instruction is enabled.
When this bit is “1,” the STP instruction is disabled.
Once the STP instruction is executed, an internal resetting occurs.
When this bit is set to “1,” it cannot be rewritten to “0” by program.
This bit is cleared to “0” after resetting.
(1) Initial value of watchdog timer
■ Note
At reset or writing to the watchdog timer control register (address
002B16), a watchdog timer H is set to “FFF16” and a watchdog timer
L to “FF16.”
When releasing the stop mode, the watchdog timer performs its count
operation even in the stop release waiting time. Be careful not to
cause the watchdog timer H to underflow in the stop release waiting
time, for example, by writing data in the watchdog timer control reg-
ister (address 002B16) before executing the STP instruction.
(2) Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 002B16) permits
selecting a watchdog timer H count source. When this bit is set to
“FF16” is set when
watchdog timer
control register is
written to.
Data bus
“FFF16” is set
when watchdog
timer control
register is written
to.
X
CIN
1/2
“0”
“1”
“0”
Watchdog timer L (8)
Internal system clock
selection bit
(Note)
Watchdog timer H (12)
1/8
“1”
Watchdog timer H count
source selection bit
X
IN
STP instruction disable bit
STP instruction
Reset
circuit
Internal reset
RESET
Note: Either high-speed, middle-speed or low-speed mode is selected by bit 7 of CPU mode register.
Fig. 61 Block Diagram of Watchdog Timer
b0
b7
Watchdog timer control register
(WDTCON : address 002B16
)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/8 or f(XCIN)/16
Fig. 62 Structure of Watchdog Timer Control Register
53
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Buzzer Output Circuit
The 38B5 group has a buzzer output circuit. One of 1 kHz, 2 kHz and
4 kHz (at XIN = 4.19 MHz) frequencies can be selected by the buzzer
output control register (address 0EFD16). Either P43/BUZ01 or P20/
BUZ02/FLD0 can be selected as a buzzer output port by the output
port selection bits (b2 and b3 of address 0EFD16).
The buzzer output is controlled by the buzzer output ON/OFF bit
(b4).
Port latch
1/1024
1/2048
1/4096
f(XIN
)
Buzzer output
Divider
Buzzer output ON/OFF bit
Output port control signal
Port direction register
Fig. 63 Block Diagram of Buzzer Output Circuit
b7
b0
Buzzer output control register
(BUZCON: address 0EFD16)
Output frequency selection bits (XIN = 4.19 MHz)
00 : 1 kHz (f(XIN)/4096)
01 : 2 kHz (f(XIN)/2048)
10 : 4 kHz (f(XIN)/1024)
11 : Not available
Output port selection bits
00 : P20 and P43 function as ordinary ports.
01 : P43/BUZ01 functions as a buzzer output.
10 : P20/BUZ02/FLD0 functions as a buzzer output.
11 : Not available
Buzzer output ON/OFF bit
0 : Buzzer output OFF (“0” output)
1 : Buzzer output ON
Not used (return “0” when read)
Fig. 64 Structure of Buzzer Output Control Register
54
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset Circuit
______
Poweron
To reset the microcomputer, RESET pin should be held at an “L”
______
level for 2 µs or more. Then the RESET pin is returned to an “H” level
(the power source voltage should be between 2.7 V and 5.5 V, and
the oscillation should be stable), reset is released. After the reset is
completed, the program starts from the address contained in address
FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make
sure that the reset input voltage is less than 0.5 V for VCC of 2.7 V
(switching to the high-speed mode, a power source voltage must be
between 4.0 V and 5.5 V).
(Note)
Power source
voltage
0V
RESET
VCC
Reset input
voltage
0V
0.2VCC
Note : Reset release voltage ; Vcc=2.7 V
RESET
V
CC
Power source
voltage detection
circuit
Fig. 65 Reset Circuit Example
X
IN
φ
RESET
Internal
reset
ADH, ADL
Address
?
?
?
?
FFFC
FFFD
ADH
Data
ADL
SYNC
X
IN: about 4000 cycles
Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN)=4
• f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 66 Reset Sequence
55
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address Register contents
Address Register contents
000016
000116
000216
000416
000516
000616
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001716
001916
001A16
001C16
001D16
001E16
002016
002116
002216
002316
002416
002516
002616
002816
(1)
(2)
(3)
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
8016
0016
0016
0016
0016
8016
FF16
(33)
Timer 34 mode register
002916
002A16
Port P0
0016
0016
3F16
FF16
Port P0 direction register
Port P1
(34)
(35)
(36)
(37)
(38)
(39)
(40)
(41)
Timer 56 mode register
Watchdog timer control register
Timer X (low-order)
002B16
002C16
002D16
002E16
002F16
(4) Port P2
(5) Port P2 direction register
(6) Port P3
FF16
0016
Timer X (high-order)
Timer X mode register 1
Timer X mode register 2
0016
0016
1016
(7)
(8)
(9)
Port P4
Port P4 direction register
Port P5
Interrupt interval determination
control register
A-D control register
003116
003216
003916
003A16
003B16
003C16
003D16
003E16
003F16
0EF016
0EF116
0EF216
0EF316
0EF416
0EF516
0EF616
0EF716
0EF916
0EFA16
0EFB16
0EFC16
0EFD16
(10) Port P5 direction register
(11) Port P6
(42)
(43)
(44)
(45)
(46)
(47)
(48)
(49)
(50)
(51)
(52)
(53)
(54)
(55)
(56)
(57)
(58)
(59)
(60)
(61)
(62)
(63)
Interrupt source switch register
Interrupt edge selection register
CPU mode register
0016
0016
(12) Port P6 direction register
(13) Port P7
0 1 0 0 1 0 0 0
Interrupt request register 1
Interrupt request register 2
Interrupt control register 1
Interrupt control register 2
Pull-up control register 1
Pull-up control register 2
P1FLDRAM write disable register
P3FLDRAM write disable register
FLDC mode register
0016
0016
0016
0016
0016
0016
0016
(14)
(15)
Port P7 direction register
Port P8
(16) Port P8 direction register
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
Port P9
Port P9 direction register
UART control register
Serial I/O1 control register 1
Serial I/O1 control register 2
Serial I/O1 control register 3
Serial I/O2 control register
Serial I/O2 status register
Timer 1
0016
0016
0016
FF16
FF16
0016
0016
0016
0016
0016
Tdisp time set register
Toff1 time set register
Toff2 time set register
Port P0FLD/port switch register
Timer 2
Port P2FLD/port switch register
Port P8FLD/port switch register
Port P8FLD output control register
0116
FF16
FF16
Timer 3
Timer 4
Timer 5
FF16
FF16
0016
0016
Buzzer output control register
Processor status register
Program counter
Timer 6
(PS) ✕ ✕ ✕ ✕ ✕
✕ ✕
1
PWM control register
Timer 12 mode register
(PC
H
)
)
FFFD16 contents
FFFC16 contents
(PC
L
X: Not fixed
Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.
Fig. 67 Internal Status at Reset
56
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
●Oscillation control
The 38B5 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance with
the resonator manufacturer's recommended values. No
external resistor is needed between XIN and XOUT since a feedback
resistor exists on-chip. However, an external feedback resistor is
needed between XCIN and XCOUT.
(1) Stop mode
If the STP instruction is executed, the internal system clock stops at
an “H” level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16”
and timer 2 is set to “0116.”
Either XIN divided by 8 or XCIN divided by 16 is input to timer 1 as
count source, and the output of timer 1 is connected to timer 2. The
bits of the timer 12 mode register are cleared to “0.” Set the interrupt
enable bits of the timer 1 and timer 2 to disabled (“0”) before execut-
ing the STP instruction. Oscillator restarts when an external interrupt
is received, but the internal system clock is not supplied to the CPU
until timer 1 underflows. This allows time for the clock circuit oscilla-
tion to stabilize.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
●Frequency control
(1) Middle-speed mode
The internal system clock is the frequency of XIN divided by 4. After
reset, this mode is selected.
(2) Wait mode
If the WIT instruction is executed, the internal system clock stops at
an “H” level. The states of XIN and XCIN are the same as the state
before executing the WIT instruction. The internal system clock re-
starts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after the
clock is restarted.
(2) High-speed mode
The internal system clock is the frequency of XIN.
(3) Low-speed mode
The internal system clock is the frequency of XCIN divided by 2.
■Note
If you switch the mode between middle/high-speed and low-speed,
stabilize both XIN and XCIN oscillations. The sufficient time is required
for the sub clock to stabilize, especially immediately after power on
and at returning from stop mode. When switching the mode between
middle/high-speed and low-speed, set the frequency on condition
that f(XIN) > 3f(XCIN).
X
CIN
XCOUT
X
IN
XOUT
(4) Low power consumption mode
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set bit
5 of the CPU mode register to “1.” When the main clock XIN is re-
started (by setting the main clock stop bit to “0”), set enough time for
oscillation to stabilize.
Rf
Rd
C
COUT
CIN
COUT
CCIN
By clearing furthermore the XCOUT drivability selection bit (b3) of CPU
mode register to “0,” low power consumption operation of less than
200 µA (f(XCIN) = 32 kHz) can be realized by reducing the drivability
between XCIN and XCOUT. At reset or during STP instruction execu-
tion this bit is set to “1” and a strong drivability that has an easy
oscillation start is set.
Fig. 68 Ceramic Resonator Circuit
XCIN
XCOUT
XIN
XOUT
open
open
External oscillation circuit
External oscillation circuit
or external pulse
CC
V
V
CC
SS
VSS
V
Fig. 69 External Clock Input Circuit
57
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XCOUT
XCIN
“0”
“1”
Port XC
switch bit (Note 3)
1/2
Timer 2 count source
selection bit (Note 2)
Timer 1 count source
selection bit (Note 2)
Internal system clock
XOUT
XIN
selection bit (Notes 1, 3)
“1”
“0”
Low-speed mode
“1”
Timer 1
Timer 2
“0”
1/4
1/2
“0”
“1”
High-speed or
middle-speed
mode
Main clock division ratio
selection bits (Note 3)
Middle-speed mode
“1”
Timing φ (internal clock)
“0”
High-speed or
low-speed mode
Main clock stop bit
(Note 3)
Q
S
R
S
R
Q
Q
S
R
STP instruction
STP instruction
WIT instruction
Reset
Interrupt disable flag l
Interrupt request
Notes 1: When low-speed mode is selected, set the port Xc switch bit (b4) to “1.”
2: Refer to the structure of the timer 12 mode register.
3: Refer to the structure of the CPU mode register.
Fig. 70 Clock Generating Circuit Block Diagram
58
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
High-speed mode
=4 MHz)
Middle-speed mode
(φ
(
φ
=1 MHz)
CM
“1”
6
CM
CM
CM
CM
7
6
5
4
=0(4 MHz selected)
=0(high-speed)
=0(XIN oscillating)
“0”
CM7
CM6
CM5
CM4
=0(4 MHz selected)
=1(middle-speed)
=0(XIN oscillating)
=0(32 kHz stopped)
=0(32 kHz stopped)
4
4
6
6
CM
Middle-speed mode
=1 MHz)
High-speed mode
=4 MHz)
CM
6
(
φ
(
φ
“1”
“1”
“1”
“0”
“0”
“0”
CM
CM
CM
CM
7
6
5
4
=0(4 MHz selected)
=1(middle-speed)
=0(XIN oscillating)
=1(32 kHz oscillating)
CM
CM
CM
CM
7
6
5
4
=0(4 MHz selected)
=0(high-speed)
=0(XIN oscillating)
=1(32 kHz oscillating)
Low-speed mode
Low-speed mode
(φ =16 kHz)
(
φ
=16 kHz)
CM
6
CM
CM
CM
CM
7
6
5
4
=1(32 kHz selected)
=1(middle-speed)
=0(XIN oscillating)
=1(32 kHz oscillating)
CM
CM
CM
CM
7
6
5
4
=1(32 kHz selected)
=0(high-speed)
=0(XIN oscillating)
=1(32 kHz oscillating)
b7
b4
CPU mode register
(CPUM : address 003B16
)
CM4 : Port Xc switch bit
CM
0: I/O port function
1: XCIN-XCOUT oscillating function
CM5 : Main clock (XIN- XOUT) stop bit
0: Oscillating
1: Stopped
CM6: Main clock division ratio selection bit
0: f(XIN) (High-speed mode)
CM
CM
CM
Low-power dissipation mode
=16 kHz)
Low-power dissipation mode
=16 kHz)
(
φ
(
φ
1: f(XIN)/4 (Middle-speed mode)
CM
6
CM7: Internal system clock selection bit
0: XIN–XOUT selected (Middle-/High-speed mode)
1: XCIN–XCOUT selected (Low-speed mode)
CM
CM
CM
7
6
5
=1(32 kHz selected)
=1(middle-speed)
=1(XIN stopped)
CM7
CM6
CM5
CM4
=1(32 kHz selected)
=0(high-speed)
=1(XIN stopped)
=1(32 kHz oscillating)
CM
4
=1(32 kHz oscillating)
Notes 1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2: The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait
mode is ended.
3: Timer operates in the wait mode.
4: When the stop mode is ended, a delay of approximately 1 ms occurs by Timer 1 in middle-/high-speed mode.
5: When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 in low-speed mode.
6: The example assumes that 4 MHz is being applied to the X IN pin and 32 kHz to the X CIN pin. φ indicates the internal system clock.
Fig. 71 State Transitions of System Clock
59
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING
A-D Converter
Processor Status Register
The comparator uses internal capacitors whose charge will be lost if
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” After a
reset, initialize flags which affect program execution. In particular, it
is essential to initialize the index X mode (T) and the decimal mode
(D) flags because of their effect on calculations.
the clock frequency is too low.
Therefore, make sure that f(XIN) is at least on 250 kHz during an A-D
conversion.
Do not execute the STP or WIT instruction during an A-D conver-
sion.
Interrupts
Instruction Execution Time
The contents of the interrupt request bits do not change immediately
after they have been written. After writing to an interrupt request reg-
ister, execute at least one instruction before performing a BBC or
BBS instruction.
The instruction execution time is obtained by multiplying the frequency
of the internal system clock by the number of cycles needed to ex-
ecute an instruction.
The number of cycles required to execute an instruction is shown in
the list of machine instructions.
Decimal Calculations
The frequency of the internal system clock is the same of the XIN
frequency in high-speed mode.
•To calculate in decimal notation, set the decimal mode flag (D) to
“1,” then execute an ADC or SBC instruction. Only the ADC and
SBC instructions yield proper decimal results. After executing an
ADC or SBC instruction, execute at least one instruction before ex-
ecuting a SEC, CLC, or CLD instruction.
At STP Instruction Release
At the STP instruction release, all bits of the timer 12 mode register
are cleared.
•In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
The XCOUT drivability selection bit (the CPU mode register) is set to
“1” (high drive) in order to start oscillating.
Timers
NOTES ON USE
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n+1).
Notes on Built-in EPROM Version
The P47 pin of the One Time PROM version or the EPROM version
functions as the power source input pin of the internal EPROM.
Therefore, this pin is set at low input impedance, thereby being af-
fected easily by noise.
Multiplication and Division Instructions
•The index X mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
•The execution of these instructions does not change the contents of
the processor status register.
To prevent a malfunction due to noise, insert a resistor (approx. 5
kΩ) in series with the P47 pin.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
•The data transfer instruction (LDA, etc.)
•The operation instruction when the index X mode flag (T) is “1”
•The addressing mode which uses the value of a direction register
as an index
•The bit-test instruction (BBC or BBS, etc.) to a direction register
•The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a
direction register.
Use instructions such as LDM and STA, etc., to set the port direction
registers.
Serial I/O
•Using an external clock
When using an external clock, input “H” to the external clock input
pin and clear the serial I/O interrupt request bit before executing
serial I/O transfer and serial I/O automatic transfer.
•Using an internal clock
When using an internal clock, set the synchronous clock to the in-
ternal clock, then clear the serial I/O interrupt request bit before ex-
ecuting a serial I/O transfer and serial I/O automatic transfer.
60
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
ROM PROGRAMMING METHOD
The following are necessary when ordering a mask ROM produc-
The built-in PROM of the blank One Time PROM version and the
EPROM version can be read or programmed with a general purpose
PROM programmer using a special programming adapter. Set the
address of PROM programmer in the user ROM area.
tion:
(1) Mask ROM Order Confirmation Form
(2) Mark Specification Form
(3) Data to be written to ROM, in EPROM form (three identical cop-
ies)
Table 9 Special Programming Adapter
Package
80P6N-A
80D0
Name of Programming Adapter
PCA7438F-80A
PCA7438L-80A
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 72 is recommended to verify programming.
Programming with PROM
programmer
Screening (Note)
(150°C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Note:
Fig. 72 Programming and Testing of One Time PROM Version
61
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Table 10 Absolute Maximum Ratings
Parameter
Unit
V
Symbol
Conditions
Ratings
–0.3 to 7.0
VCC
Power source voltage
Pull-down power source voltage
VEE
VI
VCC – 45 to VCC +0.3
–0.3 to VCC +0.3
V
Input voltage
P47, P50–P57, P61–P65, P70–
V
P77, P84–P87, P90, P91
VI
VI
VI
VI
VO
Input voltage
Input voltage
Input voltage
Input voltage
Output voltage
P40–P46, P60
–0.3 to 13
V
V
V
V
V
P00–P07, P20–P27, P80–P83
RESET, XIN
VCC – 45 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VCC +0.3
VCC – 45 to VCC +0.3
All voltages are
based on VSS.
Output transistors
are cut off.
XCIN
P00–P07, P10–P17, P20–P27,
P30–P37, P80–P83
VO
Output voltage
P50–P57, P61–P65, P70–P77,
P84–P87, P90, P91, XOUT,
XCOUT
–0.3 to VCC +0.3
V
VO
Output voltage
P40–P46, P60
–0.3 to 13
600
V
mW
°C
Pd
Power dissipation
Operating temperature
Storage temperature
Ta = 25°C
Topr
Tstg
–20 to 85
–40 to 125
°C
62
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RECOMMENDED OPERATING CONDITIONS
Table 11 Recommended Operating Conditions (1) (VCC = 4.0 to 5.5V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
5.0
Symbol
Parameter
Unit
Min.
4.0
Max.
5.5
VCC
Power source voltage
in high-speed mode
V
V
V
V
V
V
V
V
in middle-/low-speed mode
2.7
5.0
5.5
VSS
VEE
VREF
AVSS
VIA
Power source voltage
0
Pull-down power source voltage
VCC – 43
2.0
VCC
VCC
Analog reference voltage (when A-D converter is used)
Analog power source voltage
0
Analog input voltage
“H” input voltage
AN0–AN11
0
VCC
VCC
VIH
P40–P47, P50–P57, P60–P65,
P70–P77, P90, P91
0.75VCC
VIH
VIH
VIH
VIH
VIH
VIL
“H” input voltage
“H” input voltage
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
P84–P87
P00–P07
0.4VCC
0.8VCC
0.52VCC
0.8VCC
0.8VCC
0
VCC
VCC
V
V
V
V
V
V
P20–P27, P80–P83
VCC
____________
RESET
VCC
XIN, XCIN
VCC
P40–P47, P50–P57, P60–P65,
P70–P77, P90, P91
0.25VCC
VIL
“L” input voltage
P84–P87
0
0
0
0
0.16VCC
0.2VCC
0.2VCC
0.2VCC
–240
V
V
VIL
“L” input voltage
P00–P07, P20–P27, P80–P83
____________
VIL
“L” input voltage
V
RESET
VIL
“L” input voltage
XIN, XCIN
V
IOH(peak)
“H” total peak output current (Note 1)
P00–P07, P10–P17, P20–P27,
P30–P37, P80–P83
mA
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
“H” total peak output current (Note 1)
“L” total peak output current (Note 1)
“L” total peak output current (Note 1)
P50–P57, P61–P65, P70–P77, P90, P91
P50–P57, P60–P65, P70–P77, P90, P91
P40–P46, P84–P87
–60
100
60
mA
mA
mA
mA
“H” total average output current (Note 1) P00–P07, P10–P17, P20–P27,
P30–P37, P80–P87
–120
IOH(avg)
IOL(avg)
IOL(avg)
IOH(peak)
“H” total average output current (Note 1) P50–P57, P61–P65, P70–P77, P90, P91
“L” total average output current (Note 1) P50–P57, P60–P65, P70–P77, P90, P91
“L” total average output current (Note 1) P40–P46, P84–P87
–30
50
mA
mA
mA
mA
30
“H” peak output current (Note 2)
“H” peak output current (Note 2)
“L” peak output current (Note 2)
P00–P07, P10–P17, P20–P27,
P30–P37, P80–P83
–40
IOH(peak)
IOL(peak)
P50–P57, P61–P65, P70–P77,
P84–P87, P90, P91
–10
10
mA
mA
P50–P57, P61–P65, P70–P77,
P84–P87, P90, P91
IOL(peak)
IOH(avg)
“L” peak output current (Note 2)
P40–P46, P60
30
mA
mA
“H” average output current (Note 3)
P00–P07, P10–P17, P20–P27,
P30–P37, P80–P83
–18
IOH(avg)
IOL(avg)
IOL(avg)
“H” average output current (Note 3)
“L” average output current (Note 3)
“L” average output current (Note 3)
P50–P57, P60–P65, P70–P77,
P84–P87, P90, P91
–5
5
mA
mA
mA
P50–P57, P61–P65, P70–P77,
P84–P87, P90, P91
P40–P46, P60
15
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an
average value measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms.
63
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 12 Recommended Operating Conditions (2) (VCC = 4.0 to 5.5V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
kHz
Min.
Max.
250
f(CNTR0)
f(CNTR1)
Clock input frequency for timers 2, 4, and X (duty cycle 50 %)
f(XIN)
Main clock input oscillation frequency (Note 1)
Sub-clock input oscillation frequency (Note 1, 2)
4.2
50
MHz
kHz
f(XCIN)
32.768
Notes 1: When the oscillation frequency has a duty cycle of 50%.
2: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
ELECTRICAL CHARACTERISTICS
Table 13 Electrical Characteristics (1) (VCC = 4.0 to 5.5V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
IOH = –18 mA
Unit
V
Min.
Typ.
Max.
VOH
“H” output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P80–P83
VCC–2.0
IOH = –10 mA
IOL = 10 mA
VCC–2.0
V
V
VOH
VOL
“H” output voltage P50–P57, P60–P65, P70–P77,
P84–P87, P90, P91
2.0
2.0
“L” output voltage P50–P57, P61–P65, P84–P87,
P90, P91
V
V
VOL
“L” output voltage P40–P46, P60
IOL = 15 mA
0.6
0.4
VT+–VT–
Hysteresis
P40–P42, P44–P47, P5, P60,
P61, P64
V
V
VT+–VT–
VT+–VT–
IIH
Hysteresis
Hysteresis
RESET, XIN
XCIN
0.5
0.5
µA
“H” input current P47, P50–P57, P61–P65,
P70–P77, P84–P87
VI = VCC
5.0
µA
µA
µA
µA
µA
µA
IIH
IIH
IIH
IIH
IIL
IIL
“H” input current P40–P46, P60
“H” input current P20–P27, P80–P83 (Note)
“H” input current RESET, XCIN
“H” input current XIN
VI = 12 V
VI = VCC
VI = VCC
VI = VCC
VI = VSS
10.0
5.0
5.0
4.0
“L” input current P40–P47, P60
–5.0
–5.0
“L” input current P50–P57, P61–P65, P70–P77,
P84–P87, P90, P91
VI = VSS
Pull-up “off”
–30
–70
–25
–140
–45
µA
µA
VCC = 5 V, VI = VSS
Pull-up “on”
–6.0
VCC = 3 V, VI = VSS
Pull-up “on”
–5.0
–5.0
µA
µA
µA
µA
IIL
“L” input current P20–P27, P80–P83 (Note)
“L” input current RESET, XCIN
VI = VSS
VI = VSS
VI = VSS
IIL
IIL
“L” input current
XIN
–4.0
600
900
–10
ILOAD
Output load current P00–P07, P10–P17, P30–P37
VEE = VCC–43 V, VOL = VCC
Output transistors “off”
300
µA
ILEAK
Output leak current P00–P07, P10–P17, P20–P27,
P30–P37, P80–P83
VEE = VCC–43 V, VOL = VCC
–43 V Output transistors “off”
µA
V
IREADH
VRAM
“H” read current
VI = 5 V
1
5.5
RAM hold voltage
When clock is stopped
2
Note: Except when reading ports P2 or P8.
64
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 14 Electrical Characteristics (2) (VCC = 4.0 to 5.5V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
7.5
Symbol
Parameter
Test conditions
Unit
mA
Min.
Max.
15
Power source current
High-speed mode
f(XIN) = 4.2 MHz
f(XCIN) = 32 kHz
ICC
Output transistors “off”
High-speed mode
f(XIN) = 4.2 MHz (in WIT state)
f(XCIN) = 32 kHz
1
3
mA
mA
Output transistors “off”
Middle-speed mode
f(XIN) = 4.2 MHz
f(XCIN) = stopped
Output transistors “off”
Middle-speed mode
f(XIN) = 4.2 MHz (in WIT state)
f(XCIN) = stopped
1
mA
µA
Output transistors “off”
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32 kHz
Low-power dissipation mode (CM3 = 0)
Output transistors “off”
60
200
40
Low-speed mode
20
µA
f(XIN) = stopped
f(XCIN) = 32 kHz (in WIT state)
Low-power dissipation mode (CM3 = 0)
Output transistors “off”
Increment when A-D conversion is executed
0.6
0.1
mA
µA
µA
All oscillation stopped (in STP state) Ta = 25°C
1
Output transistors “off”
Ta = 85°C
10
A-D CONVERTER CHARACTERISTICS
Table 15 A-D Converter Characteristics
(VCC = 4.0 to 5.5V, VSS = 0V, Ta = –20 to 85°C, f(XIN) = 250 kHz to 4.2 MHz in high-speed mode, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
±1
Max.
10
Bits
LSB
tc(φ)
µA
—
—
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
VCC = VREF = 5.12 V
VREF = 5.0 V
±2.5
62
TCONV
61
50
IVREF
IIA
Reference input current
Analog port input current
Ladder resistor
150
0.5
35
200
5.0
µA
kΩ
RLADDER
65
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS
Table 16 Timing Requirements (VCC = 4.0 to 5.5V, VSS = 0V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
2.0
238
60
Max.
____________
Reset input “L” pulse width
µs
ns
ns
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
ns
ns
ns
tW(RESET)
tC(XIN)
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time (XCIN input)
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “H” pulse width
INT0 to INT4 input “L” pulse width
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input set up time
tWH(XIN)
tWL(XIN)
60
tC(XCIN)
20
tWH(XCIN)
tWL(XCIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
5.0
5.0
4.0
1.6
1.6
80
tWL(INT)
80
tC(SCLK)
0.95
400
400
200
200
tWH(SCLK)
tWL(SCLK)
tsu(SCLK–SIN)
th(SCLK–SIN)
Serial I/O input hold time
SWITCHING CHARACTERISTICS
Table 17 Switching Characteristics (VCC = 4.0 to 5.5V, VSS = 0V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
tWH(SCLK)
Parameter
Test conditions
Unit
Min.
Typ.
Max.
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
CL = 100 pF
CL = 100 pF
tC(SCLK)/2–160
tC(SCLK)/2–160
ns
ns
ns
ns
ns
ns
ns
tWL(SCLK)
td(SCLK–SOUT)
tv(SCLK–SOUT)
tr(SCLK)
0.2 tc
Serial I/O output valid time
0
Serial I/O clock output rising time
Serial I/O clock output falling time
CL = 100 pF
CL = 100 pF
40
40
tf(SCLK)
tr(Pch–strg)
P-channel high-breakdown voltage
output rising time (Note 1)
CL = 100 pF
VEE = VCC–43 V
55
1.8
µs
tr(Pch–weak)
P-channel high-breakdown voltage
output rising time (Note 2)
CL = 100 pF
VEE = VCC–43 V
Notes 1: When bit 7 of the FLDC mode register (address 0EF416) is at “0”.
2: When bit 7 of the FLDC mode register (address 0EF416) is at “1”.
P0,P1,P2,
P3,P80–P8
3
P5
P5
P5
2
3
6
/SCLK11
/SCLK12
/SCLK21
/SCLK22
,
,
,
High-breakdown
P-channel open-
drain output port
Serial I/O clock
output port
P57
CL
CL
(Note)
VEE
Note: Ports P2 and P8 need external resistors.
Fig. 73 Circuit for Measuring Output Switching Characteristics
66
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing Diagram
tC(CNTR)
tWL(CNTR)
0.2VCC
tWH(CNTR)
CNTR0,CNTR1
0.8VCC
tWL(INT)
0.2VCC
tWH(INT)
INT0–INT4
RESET
0.8VCC
tW(RESET)
0.8VCC
0.2VCC
tC(XIN)
tC(XCIN)
tC(SCLK)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
0.2VCC
tWL(XCIN)
tWH(XCIN)
0.8VCC
XCIN
0.2VCC
tf(SCLK)
tr
tWL(SCLK)
tWH(SCLK)
0.8VCC
SCLK
SIN
0.2VCC
tsu(SIN-SCLK)
th(SCLK-SIN)
0.8VCC
0.2VCC
td(SCLK-SOUT)
tv(SCLK-SOUT)
SOUT
Fig. 74 Timing Diagram
67
Keep safety first in your circuit designs!
¡ Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
¡ These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
¡ Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.
¡ All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
¡ Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
¡ The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
¡ If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
¡ Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
© 1998 MITSUBISHI ELECTRIC CORP.
\KI-9802 Printed in Japan (ROD) 2
New publication, effective Feb. 1998.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
38B5 GROUP DATA SHEET
Rev.
Rev.
date
Revision Description
No.
1.0 First Edition
980202
(1/1)
相关型号：
©2020 ICPDF网 联系我们和版权申明