M38853FB-HP_技术文档

To all our customers

Regarding the change of names mentioned in the document, such as Mitsubishi

Electric and Mitsubishi XX, to Renesas Technology Corp.

The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas

Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)

Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi

Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names

have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.

Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been

made to the contents of the document, and these changes do not constitute any alteration to the

contents of the document itself.

Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices

and power devices.

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

GENERAL DESCRIPTION

The 3885 group is the 8-bit microcomputer based on the 740 fam-

ily core technology.

ꢀComparator circuit ...................................................... 8 channels

ꢀClock generating circuit..................................... Built-in 2 circuits

(connect to external ceramic resonator or quartz-crystal oscillator)

ꢀPower source voltage................................................ 3.0 to 3.6 V

ꢀPower dissipation

The 3885 group is designed for Keyboard Controller for the note

book PC.

2

The multi-master I C-bus interface can be added by option.

In high-speed mode ..........................................................20 mW

(at 8 MHz oscillation frequency, at 3.3 V power source voltage)

In low-speed mode ......................................................... 330 mW

(at 32 kHz oscillation frequency, at 3.3 V power source voltage)

ꢀOperating temperature range....................................–20 to 85°C

FEATURES

ꢀBasic machine-language instructions ...................................... 71

ꢀMinimum instruction execution time .................................. 0.5 µs

(at 8 MHz oscillation frequency)

ꢀMemory size

ꢀSupply voltage ................................................. VCC = 3.3 ± 0.3V

ꢀProgram/Erase voltage .................................VPP = 5.0 V ± 10 %

ꢀProgramming method...................... Programming in unit of byte

ꢀErasing method

ROM ................................................................. 32K to 60K bytes

RAM ............................................................... 1024 to 2048 bytes

ꢀProgrammable input/output ports ............................................ 72

ꢀSoftware pull-up transistors ....................................................... 8

ꢀInterrupts ................................................. 22 sources, 16 vectors

ꢀTimers ............................................................................. 8-bit ꢀ 4

ꢀWatchdog timer ............................................................ 16-bit ꢀ 1

ꢀPWM output .................................................................. 14-bit ꢀ 2

ꢀSerial I/O....................... 8-bit ꢀ 1(UART or Clock-synchronized)

Parallel I/O mode

CPU reprogramming mode

ꢀProgram/Erase control by software command

ꢀNumber of times for programming/erasing ............................ 100

ꢀOperating temperature range (at programming/erasing)

........................................................................Room temperature

2

ꢀMulti-master I C bus interface (option) ........................ 1 channel

ꢀLPC interface.............................................................. 2 channels

ꢀSerialized IRQ .................................................................. 3 factor

ꢀA-D converter ............................................... 10-bit ꢀ 8 channels

ꢀD-A converter ................................................. 8-bit ꢀ 2 channels

APPLICATION

Note book PC

PIN CONFIGURATION (TOP VIEW)

40

61

P1

6

7

P3

1

0

/PWM10

/PWM00

39

38

37

36

35

34

33

62

63

64

65

66

67

68

69

70

71

72

73

74

75

P20/CMPREF

P2

P8

7

/SERIRQ

P8 /LCLK

/LRESET

/LFRAME

1

6

2

P85

P2

3

P84

P2

4(LED0)

P8

3

2

1

0

/LAD

3

2

1

0

5

6

7

(LED

1

2

3

)

M38857M8-XXXHP

M38858MC-XXXHP

M38859M8-XXXHP

M38859FFHP

32

31

30

29

28

V

X

SS

OUT

IN

V

CC

REF

AVSS

V

27

26

25

24

23

P6

7

/AN

7

P4

RESET

CNVSS

P4

0

/XCOUT

/XCIN

6

1

76

77

78

79

80

5

4

3

/AN

5

4

3

V

PP

2

/INT

/R

0

22

21

P4

3

4

1

P6

2

/AN

2

1

X

D

1/AN

: Flash memory version

Package type : 80P6Q-A

Fig. 1 Pin configuration

1

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Fig. 2 Functional block diagram

2

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PIN DESCRIPTION

Table 1 Pin description (1)

Functions

Name

Power source

CNVSS input

Function except a port function

VCC, VSS

CNVSS

VREF

•Apply voltage of 3.0 V ±10 % to Vcc, and 0 V to Vss.

•Connected to VSS.

•In the flash memory version, this pin functions as the VPP power source input pin.

•Reference voltage input pin for A-D and D-A converters.

•Analog power source input pin for A-D and D-A converters.

•Connect to VSS.

Reference voltage

Analog power source

Reset input

AVSS

•Reset input pin for active “L”.

RESET

XIN

•Input and output pins for the clock generating circuit.

Clock input

•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set

the oscillation frequency.

•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT

pin open.

XOUT

Clock output

•8-bit I/O port.

•I/O direction register allows each pin to be individually programmed as either input or output.

•CMOS compatible input level.

P00–P07

P10–P17

I/O port P0

I/O port P1

•CMOS 3-state output structure or N-channel open-drain output structure.

•8-bit I/O port.

•I/O direction register allows each pin to be individually programmed as either input or output.

•CMOS compatible input level.

•CMOS 3-state output structure or N-channel open-drain output structure.

•8-bit I/O port.

•Comparator reference power source

input pin

P20/CMPREF

•I/O direction register allows each pin to be individually

programmed as either input or output.

I/O port P2

•CMOS compatible input level.

•CMOS 3-state output structure.

P21–P27

•P24 to P27 (4 bits) are enabled to output large current for LED drive.

•8-bit I/O port.

•Key-on wake-up input pins

•Comparator input pins

•PWM output pins

P30/PWM00

P31/PWM10

•I/O direction register allows each pin to be individually

programmed as either input or output.

I/O port P3

•CMOS compatible input level.

•CMOS 3-state output structure.

•Key-on wake-up input pins

•Comparator input pins

P32–P37

•These pins function as key-on wake-up and compara-

tor input.

•These pins are enabled to control pull-up.

3

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Table 2 Pin description (2)

Functions

Name

Function except a port function

•8-bit I/O port with the same function as port P0

P40/XCOUT

P41/XCIN

•Sub-clock generating circuit I/O

pins (Connect a resonator.)

CMOS compatible input level

P42/INT0

P43/INT1

•Interrupt input pins

P40, P41 : CMOS 3-state output structure

I/O port P4

P44/RxD

P45/TxD

P46/SCLK

P42-P47 : CMOS 3-state output structure or N-

channel open-drain output structure

•Serial I/O function pins

•Each pin level of P42 to P46 can be read even in

output port mode.

•Serial I/O function pins

P47/SRDY

/CLKRUN

•Serialized IRQ function pin

P50/INT5

•8-bit I/O port with the same function as port P0

•CMOS compatible input level

P51/INT20

P52/INT30

P53/INT40

P54/CNTR0

P55/CNTR1

•Interrupt input pins

•CMOS 3-state output structure

I/O port P5

•Timer X, timer Y function pins

•D-A converter output pins

•PWM output pins

P56/DA1/PWM01

P57/DA2/PWM11

•8-bit I/O port with the same function as port P0

•CMOS compatible input level.

P60

/AN

0

–P6

7

/AN

7

I/O port P6

•A-D converter output pins

•CMOS 3-state output structure.

•8-bit CMOS I/O port with the same function as port P0

P70

P71

P72

P70–P75 : CMOS compatible input level or

TTL compatible input level

P73/INT21

P74/INT31

P75/INT41

P76, P77 : CMOS compatible input level or

•Interrupt input pins

2

I/O port P7

SMBUS input level in the I C-BUS

interface function,

P76/SDA

P77/SCL

N-channel open-drain output structure

2

•I C-BUS interface function pins

•Each pin level of P70 to P75 can be read evev in

output port mode.

•8-bit CMOS I/O port with the same function as port

P0

P80/LAD0

P81/LAD1

P82/LAD2

P83/LAD3

•CMOS compatible input level.

•CMOS 3-state output structure.

•LPC interface function pins

•Serialized IRQ function pin

I/O port P8

P84/LFRAME

P85/LRESET

P86/LCLK

P87/SERIRQ

4

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PART NUMBERING

Product name

M3885

8

M

C

-XXX HP

Package type

HP : 80P6Q-A

ROM number

Omitted in the flash memory version.

ROM/Flash memory size

1: 4096 bytes

2: 8192 bytes

3: 12288 bytes

4: 16384 bytes

5: 20480 bytes

6: 24576 bytes

7: 28672 bytes

8: 32768 bytes

9: 36864 bytes

A: 40960 bytes

B: 45056 bytes

C: 49152 bytes

D: 53248 bytes

E: 57344 bytes

F: 61440 bytes

The first 128 bytes and the last 2 bytes of ROM are reserved

areas ; user cannot use those bytes.

However, they can be programmed or erased in the flash

memory version, so that the users can use them.

Memory type

M : Mask ROM version

F : Flash memory version

RAM size

0: 192 bytes

1: 256 bytes

2: 384 bytes

3: 512 bytes

4: 640 bytes

5: 768 bytes

6: 896 bytes

7: 1024 bytes

8: 1536 bytes

9: 2048 bytes

Fig. 3 Part numbering

5

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

GROUP EXPANSION

Mitsubishi plans to expand the 3885 group as follows.

Packages

80P6Q-A .................................. 0.5 mm-pitch plastic molded LQFP

Memory Type

Support for mask ROM, flash memory version.

Memory Size

ROM size ........................................................... 32 K to 60 K bytes

RAM size .......................................................... 1024 to 2048 bytes

Memory Expansion

ROM size (bytes)

ROM

external

M38859FF

60K

56K

48K

40K

M38858MC

32K

24K

M38857M8

M38859M8

16K

8K

256

512

768

1024

1280

1536

1792

2048

RAM size (bytes)

Fig. 4 Memory expansion plan

Table 3 Products plan list

As of May 2002

(P) ROM size (bytes)

Product name

RAM size (bytes)

Package

80P6Q-A

Remarks

ROM size for User in (

)

M38857M8-XXXHP

M38858MC-XXXHP

M38859M8-XXXHP

M38859FFHP

32768 (32638)

49152 (19022)

32768 (32638)

61440

1024

1536

2048

Mask ROM version

Flash memory version

6

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FUNCTIONAL DESCRIPTION

[Stack Pointer (S)]

CENTRAL PROCESSING UNIT (CPU)

The 3885 group uses the standard 740 Family instruction set. Re-

fer to the table of 740 Family addressing modes and machine

instructions or the 740 Family Software Manual for details on the

instruction set.

The stack pointer is an 8-bit register used during subroutine calls

and interrupts. This register indicates start address of stored area

(stack) for storing registers during subroutine calls and interrupts.

The low-order 8 bits of the stack address are determined by the

contents of the stack pointer. The high-order 8 bits of the stack ad-

dress are determined by the stack page selection bit. If the stack

page selection bit is “0” , the high-order 8 bits becomes “0016”. If

the stack page selection bit is “1”, the high-order 8 bits becomes

“0116”.

Machine-resident 740 Family instructions are as follows:

The FST and SLW instructions cannot be used.

The STP, WIT, MUL, and DIV instructions can be used.

[Accumulator (A)]

The operations of pushing register contents onto the stack and

popping them from the stack are shown in Figure 7.

Store registers other than those described in Figure 7 with pro-

gram when the user needs them during interrupts or subroutine

calls.

The accumulator is an 8-bit register. Data operations such as data

transfer, etc., are executed mainly through the accumulator.

[Index Register X (X)]

The index register X is an 8-bit register. In the index addressing

modes, the value of the OPERAND is added to the contents of

register X and specifies the real address.

[Program Counter (PC)]

The program counter is a 16-bit counter consisting of two 8-bit

registers PCH and PCL. It is used to indicate the address of the

next instruction to be executed.

[Index Register Y (Y)]

The index register Y is an 8-bit register. In partial instruction, the

value of the OPERAND is added to the contents of register Y and

specifies the real address.

b0

b7

A

Accumulator

b0

b7

X

Index register X

Index register Y

b7

Y

b7

S

Stack pointer

b15

b7

PCH

PC

L

Program counter

b7

N V T B D I Z C

Processor status register (PS)

Carry flag

Zero flag

Interrupt disable flag

Decimal mode flag

Break flag

Index X mode flag

Overflow flag

Negative flag

Fig. 5 740 Family CPU register structure

7

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

On-going Routine

Execute JSR

Interrupt request

(Note)

M (S) (PC

(S) (S) – 1

M (S) (PC

H

)

Push return address

on stack

M (S) (PC

(S) (S) – 1

M (S) (PC

H)

L

)

(S) (S) – 1

M (S) (PS)

(S) (S) – 1

Push return address

on stack

Push contents of processor

status register on stack

L

)

(S) (S)– 1

Subroutine

Interrupt

Service Routine

I Flag is set from “0” to “1”

Execute RTS

(S) (S) + 1

Fetch the jump vector

Execute RTI

(S) (S) + 1

POP return

address from stack

POP contents of

processor status

register from stack

(PC

(S) (S) + 1

(PC M (S)

L)

M (S)

(PS)

(S) (S) + 1

(PC M (S)

(S) (S) + 1

(PC M (S)

M (S)

H)

L)

POP return

address

from stack

H)

Note: Condition for acceptance of an interrupt

Interrupt enable flag is “1”

Interrupt disable flag is “0”

Fig. 6 Register push and pop at interrupt generation and subroutine call

Table 4 Push and pop instructions of accumulator or processor status register

Push instruction to stack

Pop instruction from stack

Accumulator

PHA

PHP

PLA

PLP

Processor status register

8

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

•Bit 4: Break flag (B)

[Processor status register (PS)]

The B flag is used to indicate that the current interrupt was

generated by the BRK instruction. The BRK flag in the processor

status register is always “0”. When the BRK instruction is used to

generate an interrupt, the processor status register is pushed

onto the stack with the break flag set to “1”.

The processor status register is an 8-bit register consisting of 5

flags which indicate the status of the processor after an arithmetic

operation and 3 flags which decide MCU operation. Branch opera-

tions can be performed by testing the Carry (C) flag , Zero (Z) flag,

Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,

V, N flags are not valid.

•Bit 5: Index X mode flag (T)

When the T flag is “0”, arithmetic operations are performed

between accumulator and memory. When the T flag is “1”, direct

arithmetic operations and direct data transfers are enabled

between memory locations.

•Bit 0: Carry flag (C)

The C flag contains a carry or borrow generated by the arithmetic

logic unit (ALU) immediately after an arithmetic operation. It can

also be changed by a shift or rotate instruction.

•Bit 1: Zero flag (Z)

•Bit 6: Overflow flag (V)

The V flag is used during the addition or subtraction of one byte

of signed data. It is set if the result exceeds +127 to -128. When

the BIT instruction is executed, bit 6 of the memory location

operated on by the BIT instruction is stored in the overflow flag.

•Bit 7: Negative flag (N)

The Z flag is set if the result of an immediate arithmetic operation

or a data transfer is “0”, and cleared if the result is anything other

than “0”.

•Bit 2: Interrupt disable flag (I)

The N flag is set if the result of an arithmetic operation or data

transfer is negative. When the BIT instruction is executed, bit 7 of

the memory location operated on by the BIT instruction is stored

in the negative flag.

The I flag disables all interrupts except for the interrupt

generated by the BRK instruction.

Interrupts are disabled when the I flag is “1”.

•Bit 3: Decimal mode flag (D)

The D flag determines whether additions and subtractions are

executed in binary or decimal. Binary arithmetic is executed when

this flag is “0”; decimal arithmetic is executed when it is “1”.

Decimal correction is automatic in decimal mode. Only the ADC

Table 5 Set and clear instructions of each bit of processor status register

N flag

C flag

SEC

CLC

Z flag

I flag

SEI

D flag

SED

CLD

B flag

T flag

SET

CLT

V flag

–

Set instruction

CLI

CLV

Clear instruction

9

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

[CPU Mode Register (CPUM)] 003B16

The CPU mode register contains the stack page selection bit, etc.

The CPU mode register is allocated at address 003B16.

b7

b0

CPU mode register

1

(

CPUM : address 003B16)

Processor mode bits

b1 b0

0

1

0

1

0

1

: Single-chip mode

: Not available

Stack page selection bit

0

1

: 0 page

: 1 page

Fix this bit to “1”.

Port P4 /P4 switch bit

0

1

0 : I/O port function (stop oscillating)

1 : XCIN–XCOUT oscillating function

Main clock (XIN–XOUT) stop bit

0 : Oscillating

1 : Stopped

Main clock division ratio selection bits

b7 b6

0

1

0

1

0

1

: φ = f(XIN)/2 (high-speed mode)

: φ = f(XIN)/8 (middle-speed mode)

: φ = f(XCIN)/2 (low-speed mode)

: Not available

Fig. 7 Structure of CPU mode register

10

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MEMORY

Zero Page

Access to this area with only 2 bytes is possible in the zero page

RAM

addressing mode.

RAM is used for data storage and for stack area of subroutine

calls and interrupts.

Special Page

Access to this area with only 2 bytes is possible in the special

ROM

page addressing mode.

ROM is used for program code and data table storage.

The first 128 bytes and the last 2 bytes of ROM are reserved for

device testing code and the rest is user area. Programming/Eras-

ing of the reserved ROM area is possible in the flash memory

version.

Interrupt Vector Area

The interrupt vector area contains reset and interrupt vectors.

Special Function Register (SFR) Area

The special function register area contains the control registers

such as I/O ports, timers, serial I/O, etc.

000016

SFR area

RAM area

Zero page

004016

Address

XXXX16

RAM size

(bytes)

010016

RAM

1024

1536

2048

043F16

063F16

083F16

XXXX16

Not used

0FF016

SFR area

0FFF16

YYYY16

Reserved ROM area

(Note) (128 bytes)

ZZZZ16

ROM area

ROM size

(bytes)

Address

YYYY16

Address

ZZZZ16

ROM

32768

49152

61440

800016

400016

100016

808016

408016

108016

FF0016

FFDC16

Special page

Interrupt vector area

FFFE16

FFFF16

Reserved ROM area

(Note)

Notes: This area is reserved in the mask ROM version.

This area is usable in flash memory version.

Fig. 8 Memory map diagram

11

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Port P0 (P0)

Prescaler 12 (PRE12)

000016

000116

000216

000316

000416

000516

000616

000716

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

001016

001116

001216

001316

001416

001516

001616

001716

001816

001916

001A16

001B16

001C16

001D16

002016

002116

002216

002316

002416

002516

002616

002716

Port P0 direction register (P0D)

Port P1 (P1)

Timer 1 (T1)

Timer 2 (T2)

Port P1 direction register (P1D)

Port P2 (P2)

Timer XY mode register (TM)

Prescaler X (PREX)

Timer X (TX)

Port P2 direction register (P2D)

Port P3 (P3)

Prescaler Y (PREY)

Timer Y (TY)

Port P3 direction register (P3D)

Port P4 (P4)

002816 Data bas buffer register 0 (DBB0)

002916 Data bas buffer status register 0 (DBBSTS0)

002A16 LPC control register (LPCCON)

002B16 Data bas buffer register 1 (DBB1)

002C16 Data bas buffer status register 1 (DBBSTS1)

002D16 Comparator data register (CMPD)

002E16 Port control register 1 (PCTL1)

002F16 Port control register 2 (PCTL2)

003016 PWM0H register (PWM0H)

Port P4 direction register (P4D)

Port P5 (P5)

Port P5 direction register (P5D)

Port P6 (P6)

Port P6 direction register (P6D)

Port P7 (P7)

Port P7 direction register (P7D)

Port P8 (P8)/Port P4 input register (P4I)

003116 PWM0L register (PWM0L)

Port P8 direction register (P8D)/Port P7 input register (P7I)

2

003216 PWM1H register (PWM1H)

I C data shift register (S0)

2

003316 PWM1L register (PWM1L)

I C address register (S0D)

2

AD/DA control register (ADCON)

A-D conversion register 1 (AD1)

D-A1 conversion register (DA1)

D-A2 conversion register (DA2)

A-D conversion register 2 (AD2)

003416

003516

003616

003716

003816

I C status register (S1)

2

I C control register (S1D)

2

I C clock control register (S2)

2

I C start/stop condition control register (S2D)

Transmit/Receive buffer register (TB/RB)

Serial I/O status register (SIOSTS)

Serial I/O control register (SIOCON)

UART control register (UARTCON)

Baud rate generator (BRG)

003916 Interrupt source selection register (INTSEL)

Interrupt edge selection register (INTEDGE)

CPU mode register (CPUM)

003A16

003B16

003C16

003D16

003E16

003F16

Interrupt request register 1 (IREQ1)

Interrupt request register 2 (IREQ2)

Interrupt control register 1 (ICON1)

Interrupt control register 2 (ICON2)

Serialized IRQ control register (SERCON)

001E16 Watchdog timer control register (WDTCON)

Serialized IRQ request register (SERIRQ)

001F16

LPC0 address register L (LPC0ADL)

0FF016

0FF116 LPC0 address register H (LPC0ADH)

0FF216 LPC1 address register L (LPC1ADL)

0FF316 LPC1 address register H (LPC1ADH)

0FF816 Port P5 input register (P5I)

0FF916 Port control register 3 (PCTL3)

0FFE16 Flash memory control register (FMCR)

0FFF16 Reserved

(Note)

Note: This applies to only flash memory version.

Fig. 9 Memory map of special function register (SFR)

12

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

I/O PORTS

comes floating. In input port mode, writing the port register

changes only the data of the port latch and the pin remains high

impedance state.

All I/O pins are programmable as input or output. All I/O ports

have direction registers which specify the data direction of each

pin like input/output. One bit in a direction register corresponds to

one pin. Each pin can be set to be input or output port.

Writing “0” to the bit corresponding to the pin, that pin becomes an

input mode. Writing “1” to the bit, that pin becomes an output

mode.

When the P8 function selection bit of the port control register 2 is

set to “1”, reading from address 001016 reads the port P4 register,

and reading from address 001116 reads the port P7 register.

Especially, the input level of P42 to P46 pins and P70 to P75 pins

can be read regardless of the data of the direction registers in this

case.

When the data is read from the bit of the port register correspond-

ing to the pin which is set to output, the value shows the port latch

data, not the input level of the pin. When a pin set to input, the pin

Table 6 I/O port function (1)

Name

Input/Output

Related SFRs

Ref.No.

(1)

I/O Structure

Non-Port Function

CMOS compatible

input level

P00-P07

Port P0

Port control register 1

CMOS 3-state output

or N-channel open-

drain output

P10–P17

Port P1

Port P2

Analog comparator

power source input pin

Port control register 1

Port control register 2

P20/CMPREF

(2)

(3)

P21–P27

CMOS compatible

input level

CMOS 3-state output

PWM output

Key-on wake up input

Comparator input

(4)

(5)

P30/PWM00

P31/PWM10

Port control register 1

AD/DA control register

Port P3

Key-on wake up input

Comparator input

P32–P37

(6)

Port control register 1

CPU mode register

(7)

(8)

P40/XCOUT

P41/XCIN

Sub-clock generating

circuit

Input/output,

individual bits

Interrupt edge selection

register

Port control register 2

P42/INT0

P43/INT1

(9)

(10)

External interrupt input

Serial I/O function input

Serial I/O control register

Port control register 2

(11)

P44/RXD

P45/TXD

P46/SCLK

CMOS compatible

input level

CMOS 3-state output

or N-channel open-

drain output

Port P4

Serial I/O control register

UART control register

Port control register 2

Serial I/O function output

Serial I/O function I/O

(12)

(13)

(14)

Serial I/O control register

Port control register 2

Serial I/O function output Serial I/O control register

Serialized IRQ control

register

output

P47/SRDY

/CLKRUN

Serialized IRQ function

13

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Table 7 I/O port function (2)

Name

Related SFRs

Input/Output

I/O Format

Non-Port Function

Ref.No.

CMOS compatible

input level

CMOS 3-state output

or N-channel

P50/INT5

P51/INT20

(15)

(16)

Interrupt edge selection

register

External interrupt input

P52/INT30

P53/INT40

opendrain output

P54/CNTR0

P55/CNTR1

Timer X, timer Y func-

tion I/O

Timer XY mode register

(17)

Port P5

P56/DA1/

PWM01

CMOS compatible

input level

CMOS 3-state output

D-A converter output

PWM output

AD/DA control register

UART control register

(18)

(19)

P57/DA2/

PWM11

P60/AN0–

P67/AN7

Port P6

A-D converter input

AD/DA control register

Port control register 2

(20)

P70

P71

P72

(21)

(22)

(23)

(24)

CMOS compatible

input level or

TTL input level

Input/output,

individual bits

P73/INT21

P74/INT31

P75/INT41

Interrupt edge selection

register

Port control register 2

Pure N-channel

open-drain output

External interrupt input

(25)

(26)

Port P7

CMOS compatible

input level or SMBUS

input level

2

P76/SDA

P77/SCL

I C-BUS interface func-

2

I C control register

tion I/O

Pure N-channel

open-drain output

P80/LAD0

P81/LAD1

P82/LAD2

P83/LAD3

LPC interface function

I/O

CMOS compatible

input level

CMOS 3-state output

P84/

LFRAME

(27)

(28)

Data bus buffer control

register

Port P8

P85/

LRESET

P86/LCLK

P87/

SERIRQ

Serialized IRQ function

I/O

Notes1: For details usage of double-function ports as function I/O ports, refer to the applicable sections.

2: Make sure that the input level of each pin should be either 0 V or VCC in STP mode.

When an input level is at an intermediate voltage level, the ICC current will become large because of the input buffer gate.

14

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(1) Ports P0, P1

(2) Port P20

P00

P04

P10

P14

–P0

–P1

3

7

3

7

,

Direction

register

output structure

selection bits

Direction

register

Data bus

Port latch

Data bus

Port latch

Comparator reference power source input

Comparator reference input

pin select bit

(4) Ports P3

0

, P3

1

(3) Port P2

1

–P2

7

P30–P33 pull-up control bit

PWM

0

(PWM

1

) output pin selection bit

(PWM ) enable bit

PWM

0

1

Direction

register

Direction

register

Data bus

Port latch

Data bus

Port latch

PWM⁰⁰(PWM10) output

Comparator input

Key-on wake-up input

(5) Ports P3

2

–P3

7

(6) Port P4

0

P3

0

4

–P3

3

7

,

Port X

C

switch bit

pull-up control bit

Direction

register

Direction

register

Data bus

Port latch

Data bus

Port latch

Sub-clock oscillation circuit

Port P4

1

Port XC switch bit

Comparator input

Key-on wake-up input

(7) Port P4

1

(8) Ports P42 , P43

Port X

C

switch bit

P4 output structure selection bit

Direction

register

Direction

register

Data bus

Port latch

Data bus

Port latch

Interrupt input

Sub-clock oscillation circuit

✻1

✻1. Reading the port P8 register (address 001016) is switched to port P4 pin input level by the P8 function selection bit of the port control

register 2 (PCTL2).

Fig. 10 Port block diagram (1)

15

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(9) Port P4

4

(10) Port P45

P4 output structure selection bit

P45/TXD P-channel output disable bit

Serial I/O enable bit

Transmit enable bit

Serial I/O enable bit

Receive enable bit

Direction

register

Direction

register

Data bus

Port latch

Data bus

✻1

Serial I/O output

Serial I/O input

(11) Port P4

6

(12) Port P4

7

P4 output structure selection bit

Serialized IRQ enable bit

Serial I/O mode selection bit

Serial I/O enable bit

Serial I/O mode selection bit

Serial I/O enable bit

Serial I/O

synchronous clock selection bit

Serial I/O enable bit

SRDY output enable bit

Direction

register

Direction

register

Data bus

Port latch

Data bus

Serial I/O ready output

CLKRUN output

✻1

Serial I/O clock output

Serial I/O external clock input

(14) Ports P54, P55

(13) Ports P50 to P53

P5i open drain selection bit

Direction

register

Direction

register

Data bus

Port latch

Data bus

Pulse output mode

Timer output

Interrupt input

CNTR0, CNTR1 interrupt input

(15) Ports P5

6

, P5

7

(16) Port P6

PWM

0

(PWM1) output pin selection bit

PWM

0

(PWM1) enable bit

Direction

register

Direction

register

Port latch

Data bus

A-D converter input

Analog input pin selection bit

PWM⁰¹(PWM11) output

D-A converter output

D-A

1

(D-A2) output enable bit

✻1. Reading the port P8 register (address 001016) is switched to port P4 pin input level by the P8 function selection bit of the port control

register 2 (PCTL2).

Fig. 11 Port block diagram (2)

16

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(17) Ports P7

0

to P7

2

(18) Ports P73 to P75

Direction

register

Direction

register

Port latch

Data bus

Port latch

✻2

Interrupt input

✻2

(20) Port P7

7

(19) Port P7

6

2

I C-BUS interface

enable bit

2

I C-BUS interface

enable bit

Direction

register

Direction

register

Data bus

Port latch

Data bus

Port latch

S

CL output

S

DA output

✻3

S

CL input

S

DA input

(21) Ports P8

0

to P8

3

(22) Ports P84 to P86

LPC enable bit

Direction

register

Direction

register

Data bus

Port latch

LRESET

LCLK

LAD [3 : 0]

LFRAME

(23) Port P8

7

SIRQ enable bit

Direction

register

Data bus

Port latch

IRQSER

✻2. The input level can be switched between CMOS compatible input level and TTL level by the P7 input level selection bit of the port

control register 2 (PCTL2).

Reading the port P8 direction register is switched to port P7 pin input level by the P8 function selection bit of the port control register 2

(PCTL2).

2

✻3. The input level can be switched between CMOS compatible input level and SMBUS level by the I C-BUS interface pin input selection

2

bit of the I C control register (SID).

Fig. 12 Port block diagram (3)

17

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

b7

b0

Port control register 1

(PCTL1: address 002E16

)

P00–P03 output structure selection bit

0: CMOS

1: N-channel open-drain

P04–P07 output structure selection bit

0: CMOS

1: N-channel open-drain

P10–P13 output structure selection bit

0: CMOS

1: N-channel open-drain

P14–P17 output structure selection bit

0: CMOS

1: N-channel open-drain

P30–P33 pull-up control bit

0: No pull-up

1: Pull-up

P34–P37 pull-up control bit

0: No pull-up

1: Pull-up

PWM0 enable bit

0: PWM

1: PWM

0

output disabled

output enabled

0

PWM1 enable bit

0: PWM

1: PWM

1

output disabled

output enabled

1

b7

b0

Port control register 2

(PCTL2: address 002F16

)

Not used (returns “0” when read)

P7 input level selection bit (P7

0

-P75)

0: CMOS input level

1: TTL input level

P4 output structure selection bit (P4

2

, P43, P44, P46)

0: CMOS

1: N-channel open-drain

P8 function selection bit

0: Port P8/Port P8 direction register

1: Port P4 input register/Port P7 input register

INT , INT , INT interrupt switch bit

2

3

4

0: INT20, INT30, INT40 interrupt

1: INT21, INT31, INT41 interrupt

Timer Y count source selection bit

0: f(XIN)/16 (f(XCIN)/16 in low-speed mode)

1: f(XCIN

)

Oscillation stabilizing time set after STP instruction released bit

0: Automatic set “0116” to timer 1 and “FF16” to prescaler 12

1: No automatic set

Comparator reference input selection bit

0: P20/CMPREF input

1: Reference input fixed

Fig. 13 Structure of port I/O related registers (1)

18

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

b7

b0

Port P5 input register

(P5I: address 0FF816

)

P50

P51

P52

P53

input level bit

These bits directly show the pin input levels.

0: “L” level input

1: “H” level input

Not used (returns “0” when read)

b7

b0

Port control register 3

(PCTL3: address 0FF916

)

P50

P51

P52

P53

open drain selection bit

0: CMOS

1: N-channel open drain

Not used (returns “0” when read)

Fig. 14 Structure of port I/O related registers (2)

19

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

INTERRUPTS

Interrupt Source Selection

Interrupts occur by 16 sources among 22 sources: thirteen exter-

Any of the following interrupt sources can be selected by the inter-

rupt source selection register (INTSEL).

1. INT0 or Input buffer full

nal, nine internal, and one software.

Interrupt Control

2. INT1 or Output buffer empty

3. Serial I/O receive or LRESET

4. Serial I/O transmission or SCLSDA

5. Timer 2 or INT5

Each interrupt is controlled by an interrupt request bit, an interrupt

enable bit, and the interrupt disable flag except for the software in-

terrupt caused by the BRK instruction. An interrupt occurs when

both the corresponding interrupt request bit and interrupt enable

bit are “1” and the interrupt disable flag is “0”.

6. CNTR0 or INT0

7. CNTR1 or INT1

Interrupt enable bits can be set or cleared by software.

Interrupt request bits can be cleared by software, but cannot be

set by software.

8. A-D conversion or Key-on wake-up

External Interrupt Pin Selection

The BRK instruction interrupt cannot be disabled with any flag or

bit. The I (interrupt disable) flag disables all interrupts except the

BRK instruction interrupt.

The external interrupt sources of INT2, INT3, and INT4 can be se-

lected from either input pin from INT20, INT30, INT40 or input pin

from INT21, INT31, INT41 by the INT2, INT3, INT4 interrupt switch

bit (bit 4 of PCTL2).

When several interrupts occur at the same time, the interrupts are

serviced according to the priority.

■■Notes

Interrupt Operation

By acceptance of an interrupt, the following operations are auto-

When setting the followings, the interrupt request bit may be set to

“1”.

matically performed:

•When setting external interrupt active edge

Related register: Interrupt edge selection register (address

003A16); Timer XY mode register (address

002316)

1. The contents of the program counter and the processor status

register are automatically pushed onto the stack.

2. The interrupt disable flag is set and the corresponding interrupt

request bit is cleared.

•When switching interrupt sources of an interrupt vector address

where two or more interrupt sources are allocated

Related register: Interrupt source selection register (address

003916)

3. The interrupt jump destination address is read from the vector

table and stored into the program counter.

•When setting input pin of external interrupts INT2, INT3 and INT4

Related register: INT2, INT3, INT4 interrupt switch bit of Port con-

trol register 2 (bit 4 of address 002F16)

When not requiring the interrupt occurrence synchronized with

these setting, take the following sequence.

■ Set the corresponding interrupt enable bit to “0” (disabled).

■ Set the active edge selection bit or the interrupt source selec-

tion bit to “1”.

■ Set the corresponding interrupt request bit to “0” after 1 or more

instructions have been executed.

■ Set the corresponding interrupt enable bit to “1” (enabled).

20

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Table 8 Interrupt vector addresses and priority

Vector Addresses (Note 1)

Interrupt Request

Generating Conditions

Remarks

Non-maskable

Interrupt Source

Reset (Note 2)

INT0

Priority

1

High

Low

FFFC16

At reset

FFFD16

External interrupt

(active edge selectable)

At detection of either rising or

falling edge of INT0 input

2

FFFB16

FFF916

FFFA16

FFF816

Input buffer full

(IBF)

At input data bus buffer writing

At detection of either rising or External interrupt

falling edge of INT1 input

INT1

(active edge selectable)

3

Output buffer

empty (OBE)

At output data bus buffer read-

ing

At completion of serial I/O data

reception

Serial I/O

reception

Valid when serial I/O is selected

External interrupt

4

5

FFF716

FFF516

FFF616

FFF416

LRESET

At falling edge of LRESET input

At completion of serial I/

Otransfer shift or when trans-

mission buffer is empty

Serial I/O

transmission

Valid when serial I/O is selected

External interrupt

(active edge selectable)

At detection of either rising or

falling edge of SCL or SDA

SCL, SDA

Timer X

Timer Y

Timer 1

Timer 2

At timer X underflow

At timer Y underflow

At timer 1 underflow

At timer 2 underflow

6

7

8

FFF316

FFF116

FFEF16

FFF216

FFF016

FFEE16

STP release timer underflow

9

FFED16

FFEB16

FFE916

FFEC16

FFEA16

FFE816

At detection of either rising or External interrupt

INT5

falling edge of INT5 input

(active edge selectable)

At detection of either rising or

falling edge of CNTR0 input

External interrupt

(active edge selectable)

CNTR0

INT0

10

11

External interrupt

(active edge selectable)

At detection of either rising or

falling edge of INT0 input

At detection of either rising or

falling edge of CNTR1 input

External interrupt

(active edge selectable)

CNTR1

INT1

At detection of either rising or

falling edge of INT1 input

External interrupt (falling valid)

2

I C

12

13

FFE716

FFE516

FFE616

FFE416

At completion of data transfer

At detection of either rising or External interrupt

falling edge of INT2 input

INT2

(active edge selectable)

At detection of either rising or External interrupt

INT3

14

15

FFE316

FFE116

FFE216

FFE016

falling edge of INT3 input

(active edge selectable)

At detection of either rising or External interrupt

INT4

falling edge of INT4 input

(active edge selectable)

At completion of A-D conversion

A-D converter

16

17

FFDF16

FFDD16

FFDE16

FFDC16

At falling of port P3 (at input) in-

put logical level AND

External interrupt (falling valid)

Non-maskable software interrupt

Key-on wake-up

BRK instruction

At BRK instruction execution

Notes 1: Vector addresses contain interrupt jump destination addresses.

2: Reset functions in the same way as an interrupt with the highest priority.

21

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Interrupt request bit

Interrupt enable bit

Interrupt disable flag (I)

BRK instruction

Reset

Interrupt request

Fig. 15 Interrupt control

b7

b0

Interrupt edge selection register

(INTEDGE : address 003A¹⁶

)

INT

0

active edge selection bit

INT1

Not used (returns “0” when read)

INT

2

3

4

5

active edge selection bit

0 : Falling edge active

1 : Rising edge active

Not used (returns “0” when read)

b7

b0

b7

b0

Interrupt request register 2

(IREQ2 : address 003D¹⁶

Interrupt request register 1

)

(IREQ1 : address 003C¹⁶

)

INT

bit

INT

0

/input buffer full interrupt request

CNTR

0

/INT

0

interrupt request bit

CNTR

1

1 interrupt request bit

2

1

/output buffer empty interrupt

I C interrupt request bit

request bit

Serial I/O receive interrupt/LRESET

request bit

INT

2

3

4

interrupt request bit

Serial I/O transmit/S^CL, SDA interrupt

request bit

AD converter/key-on wake-up interrupt

request bit

Timer X interrupt request bit

Timer Y interrupt request bit

Timer 1 interrupt request bit

Not used (returns “0” when read)

0 : No interrupt request issued

1 : Interrupt request issued

Timer 2/INT5 interrupt request bit

b7

b0

b7

0

b0

Interrupt control register 2

Interrupt control register 1

(ICON1 : address 003E¹⁶

(ICON2 : address 003F¹⁶

)

CNTR

0

/INT

0

interrupt enable bit

INT

bit

0

/input buffer full interrupt enable bit

/output buffer empty interrupt enable

CNTR

1

2

I C interrupt enable bit

INT

2

3

4

interrupt enable bit

Serial I/O receive interrupt/LRESET

enable bit

Serial I/O transmit/S^CL, SDA interrupt

enable bit

Timer X interrupt enable bit

Timer Y interrupt enable bit

Timer 1 interrupt enable bit

AD converter/key-on wake-up interrupt

enable bit

Not used (returns “0” when read)

(Do not write “1” to this bit)

Timer 2/INT5 interrupt enable bit

0 : Interrupts disabled

1 : Interrupts enabled

Fig. 16 Structure of interrupt-related registers (1)

22

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

b7

b0

Interrupt source selection register

(INTSEL: address 003916

)

INT0/input buffer full interrupt source selection bit

0 : INT interrupt

0

1 : Input buffer full interrupt

INT

0 : INT

1 : Output buffer empty interrupt

1

/output buffer empty interrupt source selection bit

1

interrupt

Serial I/O receive/LRESET interrupt source selection bit

0 : Serial I/O receive

1 : LRESET interrupt

Serial I/O transmit/SCL, SDA interrupt source selection bit

0 : Serial I/O transmit interrupt

1 : SCL, SDA interrupt

Timer 2/INT

0 : Timer 2 interrupt

1 : INT interrupt

5 interrupt source selection bit

5

CNTR

0 : CNTR

1 : INT interrupt

0

/INT

0

interrupt source selection bit

0

interrupt

0

CNTR

0 : CNTR

1 : INT interrupt

1

/INT

1

interrupt source selection bit

1

interrupt

1

AD converter/key-on wake-up interrupt source selection bit

0 : A-D converter interrupt

1 : Key-on wake-up interrupt

Fig. 17 Structure of interrupt-related registers (2)

23

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Key Input Interrupt (Key-on Wake Up)

goes from “1” to “0”. An example of using a key input interrupt is

shown in Figure 18, where an interrupt request is generated by

pressing one of the keys consisted as an active-low key matrix

which inputs to ports P30–P33.

A Key input interrupt request is generated by applying “L” level to

any pin of port P3 that have been set to input mode. In other

words, it is generated when the logical AND of all port P3 input

Port PXx

“L” level output

Port control register 1

Bit 5 = “0”

Port P3

7

Key input interrupt request

direction register = “1”

■

■■

Port P3

latch

7

6

5

4

P3

7

output

Port P3

direction register = “1”

6

Port P3

latch

P3

6

5

4

Port P3

direction register = “1”

5

■

Port P3

latch

Port P3

direction register = “1”

4

Port P3

latch

output

Port control register 1

Bit 4 = “1”

Port P3

direction register = “0”

3

Port P3 input circuit

Comparator circuit

■

■■

Port P3

3

latch

P3

3

input

Port P3

direction register = “0”

2

■■

Port P3

latch

2

P3

2

Port P3

direction register = “0”

1

■

Port P3

latch

1

P3

1

Port P3

direction register = “0”

0

■

Port P3

latch

0

■ P-channel transistor for pull-up

■■ CMOS output buffer

Fig. 18 Connection example when using key input interrupt and port P3 block diagram

24

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

TIMERS

Timer 1 and Timer 2

The 3885 group has four timers: timer X, timer Y, timer 1, and

The count source of prescaler 12 is the oscillation frequency di-

vided by 16. The output of prescaler 12 is counted by timer 1 and

timer 2, and a timer underflow sets the interrupt request bit.

timer 2.

The division ratio of each timer or prescaler is given by 1/(n + 1),

where n is the value in the corresponding timer or prescaler latch.

All timers are count down structure. When the timer reaches

“0016”, an underflow occurs at the next count pulse and the corre-

sponding timer latch is reloaded into the timer and the count is

continued. When a timer underflows, the interrupt request bit cor-

responding to that timer is set to “1”.

Timer X and Timer Y

Timer X and Timer Y can each select one of four operating modes

by setting the timer XY mode register.

(1) Timer Mode

The timer counts f(XIN)/16.

(2) Pulse Output Mode

b0

b7

Timer X (or timer Y) counts f(XIN)/16. Whenever the contents of

the timer reach “0016”, the signal output from the CNTR0 (or

CNTR1) pin is inverted. If the CNTR0 (or CNTR1) active edge se-

lection bit is “0”, output begins at “ H”.

Timer XY mode register

(TM : address 002316

)

Timer X operating mode bit

b1b0

0 0 : Timer mode

0 1 : Pulse output mode

1 0 : Event counter mode

1 1 : Pulse width measurement mode

If it is “1”, output starts at “L”. When using a timer in this mode, set

the corresponding port P54 ( or port P55) direction register to out-

put mode.

CNTR0 active edge selection bit

0: Interrupt at falling edge

Count at rising edge in event

counter mode

1: Interrupt at rising edge

Count at falling edge in event

counter mode

(3) Event Counter Mode

Operation in event counter mode is the same as in timer mode,

except that the timer counts signals input through the CNTR0 or

CNTR1 pin.

Timer X count stop bit

0: Count start

1: Count stop

When the CNTR0 (or CNTR1) active edge selection bit is “0”, the

rising edge of the CNTR0 (or CNTR1) pin is counted.

When the CNTR0 (or CNTR1) active edge selection bit is “1”, the

falling edge of the CNTR0 (or CNTR1) pin is counted.

Timer Y operating mode bit

b5b4

0 0 : Timer mode

0 1 : Pulse output mode

1 0 : Event counter mode

1 1 : Pulse width measurement mode

(4) Pulse Width Measurement Mode

CNTR1 active edge selection bit

If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer

counts f(XIN)/16 while the CNTR0 (or CNTR1) pin is at “H”. If the

CNTR0 (or CNTR1) active edge selection bit is “1”, the timer

counts while the CNTR0 (or CNTR1) pin is at “L”.

0: Interrupt at falling edge

Count at rising edge in event

counter mode

1: Interrupt at rising edge

Count at falling edge in event

counter mode

Timer Y count stop bit

0: Count start

1: Count stop

The count can be stopped by setting “1” to the timer X (or timer Y)

count stop bit in any mode. The corresponding interrupt request

bit is set each time a timer overflows.

Fig. 19 Structure of timer XY mode register

The count source for timer Y in the timer mode or the pulse output

mode can be selected from either f(XIN)/16 or f(XCIN) by the timer

Y count source selection bit of the port control register 2 (bit 5 of

PCTL2).

25

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Data bus

Divider

1/16

Oscillator

f(XIN

Prescaler X latch (8)

Timer X latch (8)

)

Pulse width

measurement

mode

Timer mode

Pulse output mode

(f(XCIN) in low-speed mode)

To timer X interrupt

Timer X (8)

Prescaler X (8)

Timer X count stop bit

request bit

CNTR0 active

edge selection

Event

counter

mode

P54/CNTR0

bit

“0”

To CNTR

0 interrupt

request bit

“1”

CNTR0 active

“1”

“0”

edge selection

bit

Q

T

Toggle flip-flop

R

Timer X latch write pulse

Pulse output mode

Port P5

latch

4

Port P5

direction register

4

Pulse output mode

Data bus

Oscillator

Divider

Timer Y count source

selection bit

f(XIN

)

1/16

“0”

(f(XCIN) in low-speed mode)

Oscillator

Prescaler Y latch (8)

Timer Y latch (8)

Timer Y (8)

Pulse width

measure-

“1”

Timer mode

f(XCIN

)

ment mode Pulse output mode

To timer Y interrupt

request bit

Prescaler Y (8)

CNTR

edge selection

1 active

Event

counter

mode

Timer Y count stop bit

P55/CNTR1

bit

“0”

“1”

To CNTR

1 interrupt

request bit

CNTR1 active

“1”

“0”

edge selection

bit

Q

T

Toggle flip-flop

R

Port P55

latch

Timer Y latch write pulse

Pulse output mode

Port P5

5

direction register

Pulse output mode

Data bus

Prescaler 12 latch (8)

Prescaler 12 (8)

Timer 1 latch (8)

Timer 1 (8)

Timer 2 latch (8)

Timer 2 (8)

Oscillator

f(XIN

(f(XCIN) in low-speed mode)

Divider

1/16

)

To timer 2 interrupt

request bit

To timer 1 interrupt

request bit

Fig. 20 Block diagram of timer X, timer Y, timer 1, and timer 2

26

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

WATCHDOG TIMER

The watchdog timer gives a mean of returning to the reset status

when a program cannot run on a normal loop (for example, be-

cause of a software run-away). The watchdog timer consists of an

8-bit watchdog timer L and an 8-bit watchdog timer H.

ꢀWatchdog timer H count source selection bit operation

Bit 7 of WDTCON permits selecting a watchdog timer H count

source. When this bit is set to “0”, the count source becomes the

underflow signal of watchdog timer L. The detection time is set to

131.072 ms at f(XIN)=8 MHz and 32.768 s at f(XCIN)=32 kHz .

When this bit is set to “1”, the count source becomes the signal

divided by 16 for f(XIN) (or f(XCIN) in low speed mode). The detec-

tion time in this case is set to 512 µs at f(XIN)=8 MHz and 128 ms

at f(XCIN)=32 kHz . This bit is cleared to “0” after resetting.

Basic Operation of Watchdog Timer

When any data is not written into the watchdog timer control reg-

ister (WDTCON) after resetting, the watchdog timer is in the stop

state. The watchdog timer starts to count down by writing an op-

tional value into the watchdog timer control register (WDTCON) and

an internal reset occurs at an underflow of the watchdog timer H.

Accordingly, programming is usually performed so that writing to

the watchdog timer control register (WDTCON) may be started be-

fore an underflow. When the watchdog timer control register

(WDTCON) is read, the values of the high-order 6 bits of the

watchdog timer H, STP instruction disable bit, and watchdog timer

H count source selection bit are read.

ꢀSTP instruction disable bit

Bit 6 of WDTCON permits disabling the STP instruction when the

watchdog timer is in operation.

When this bit is “0”, the STP instruction is enabled.

When this bit is “1”, the STP instruction is disabled.

When this bit is “1”, the STP instruction execution cause an inter-

nal reset. When this bit is set to “1”, it cannot be rewritten to “0” by

program. This bit is cleared to “0” after resetting.

Initial Value of Watchdog Timer

At reset or writing to the watchdog timer control register

(WDTCON), each watchdog timer H and L is set to “FF16”.

“FF16” is set when

Data bus

watchdog timer

control register is

written to.

“FF16” is set when

watchdog timer

control register is

written to.

XCIN

“0”

“1”

“10”

Watchdog timer L (8)

Main clock division

ratio selection bits

Watchdog timer H (8)

1/16

(Note)

“00”

“01”

Watchdog timer H count

source selection bit

XIN

STP instruction disable bit

STP instruction

Reset

circuit

Internal reset

RESET

Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.

Fig. 21 Block diagram of Watchdog timer

b0

b7

Watchdog timer control register

(WDTCON : address 001E¹⁶

)

Watchdog timer H (for read-out of high-order 6 bit)

STP instruction disable bit

0: STP instruction enabled

1: STP instruction disabled

Watchdog timer H count source selection bit

0: Watchdog timer L underflow

1: f(X^IN)/16 or f(XCIN)/16

Fig. 22 Structure of Watchdog timer control register

27

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PULSE WIDTH MODULATION (PWM)

OUTPUT CIRCUIT

The 3885 group has two PWM output circuits, PWM0 and PWM1,

with 14-bit resolution respectively. These can operate indepen-

dently. When the oscillation frequency XIN is 8 MHz, the minimum

resolution bit width is 250 ns and the cycle period is 4096 µs. The

PWM timing generator supplies a PWM control signal based on a

signal that is the frequency of the XIN clock.

The following explanation assumes f(XIN) = 8 MHz.

Data Bus

Set to “1”

PWM0L register (Address 003116)

at write

bit 5

bit 7

bit 0

bit 7

PWM0H register (Address 003016)

PWM0 latch (14 bits)

LSB

MSB

14

P30 latch

P30/PWM00

PWM0

14-bit PWM0 circuit

PWM0 enable bit

PWM0 output selection bit

PWM0 enable bit

(64 µs period)

PWM0

timing

generator

f(XIN)

(8MHz)

1/2

(4MHz)

P30 direction register

(4096 µs period)

P56 latch

P56/DA1/PWM01

PWM0 enable bit

PWM0 output selection bit

PWM0 enable bit

P56 direction register

Fig. 23 PWM block diagram (PWM0)

28

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

this “H” duration by the contents of the low-order 6-bit data ac-

cording to the rule in Table 9.

Data Setup (PWM0)

The PWM0 output pin also functions as port P30 or P56. The

PWM0 output pin is selected from either P30/PWM00 or

P56/PWM01 by PWM0 output pin selection bit (bit 4 of ADCON).

The PWM0 output becomes enabled state by setting PWM0 en-

able bit (bit 6 of PCTL1). The high-order eight bits of output data

are set in the PWM0H register and the low-order six bits are set in

the PWM0L register.

That is, only in the sub-period tm shown by Table 9 in the PWM

cycle period T = 64t, its “H” duration is lengthened to the minimum

resolution τ added to the length of other periods.

For example, if the high-order eight bits of the 14-bit data are 0316

and the low-order six bits are 0516, the length of the “H”-level out-

put in sub-periods t8, t24, t32, t40, and t56 is 4 τ, and its length is 3

τ in all other sub-periods.

PWM1 is set as the same way.

Time at the “H” level of each sub-period almost becomes equal,

because the time becomes length set in the high-order 8 bits or

becomes the value plus τ, and this sub-period t (= 64 µs, approxi-

mate 15.6 kHz) becomes cycle period approximately.

PWM Operation

The 14-bit PWM data is divided into the low-order six bits and the

high-order eight bits in the PWM latch.

The high-order eight bits of data determine how long an “H”-level

signal is output during each sub-period. There are 64 sub-periods

in each period, and each sub-period is 256 ꢀ τ (64 µs) long. The

signal is “H” for a length equal to N times τ, where τ is the mini-

mum resolution (250 ns).

Transfer From Register to Latch

Data written to the PWML register is transferred to the PWM latch

at each PWM period (every 4096 µs), and data written to the

PWMH register is transferred to the PWM latch at each sub-period

(every 64 µs). The signal which is output to the PWM output pin is

corresponding to the contents of this latch. When the PWML reg-

ister is read, the latch contents are read. However, bit 7 of the

PWML register indicates whether the transfer to the PWM latch is

completed; the transfer is completed when bit 7 is “0” and it is not

done when bit 7 is “1”.

“H” or “L” of the bit in the ADD part shown in Figure 24 is added to

Table 9 Relationship between low-order 6 bits of data and

period set by the ADD bit

Low-order 6 bits of data (PWML)

Sub-periods tm Lengthened (m=0 to 63)

0 0 0 0 0 ^L0^SB

0 0 0 0 0 1

0 0 0 0 1 0

0 0 0 1 0 0

0 0 1 0 0 0

0 1 0 0 0 0

1 0 0 0 0 0

None

m=32

m=16, 48

m=8, 24, 40, 56

m=4, 12, 20, 28, 36, 44, 52, 60

m=2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62

m=1, 3, 5, 7, ................................................ ,57, 59, 61, 63

4096 µs

64 µs

m=0

64 µs

m=63

64 µs

m=9

m=7

m=8

15.75 µs

16.0 µs

15.75 µs

Pulse width modulation register H :

Pulse width modulation register L :

00111111

000101

Sub-periods where “H” pulse width is 16.0 µs :

Sub-periods where “H” pulse width is 15.75 µs :

m = 8, 24, 32, 40, 56

m = all other values

Fig. 24 PWM timing

29

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Data 6A16 stored at address 003016

6A16

Data 7B16 stored at address 003016

7B16

PWM0H

register

5916

Data 2416 stored at address 003116

1316 A416

Bit 7 cleared after transfer

2416

Data 3516 stored at address 003116

3516

PWM0L

register

Transfer from register to latch

1AA416

Transfer from register to latch

1EF516

B516

1EE416

PWM0 latch

(14bits)

165316

1A9316

1AA416

When bit 7 of PWM0L is 0, transfer

from register to latch is disabled.

T = 4096 µs

(64 ꢀ 64 µs)

t = 64 µs

Example 1

6A 6B 6A 6B 6A 6B 6A 6B 6A 6B 6B 6B 6A 6B 6A 6B 6A 6B 6A

6B 6A 6B 6A 6B 6A 6B 6A

PWM

0

output

1

low-order

H

5

2

5

6-bit output:

L

6A¹⁶, 2416

6B16 ·············· 36 times

(107)

6A16 ············· 28 times

106 ꢀ 64 + 36

(106)

Example 2

6A 6A 6A 6A 6B 6A 6B 6A 6B 6A 6A 6A 6B 6A 6B 6A 6B 6A 6A

6A 6B 6A 6B 6A 6B 6A 6A

PWM0 output

low-order

6-bit output:

4

3

4

3

4

3

4

H

L

ꢀ

6A^{16 ·······}40 times

6A¹⁶, 1816

6B16 ·············· 24 times

106 ꢀꢀ64 + 24

t = 64 µs

(256 ꢀ 0.25 µs)

Minimum resolution bit width τ = 0.25 µs

·······

PWM output

6B 6A 69 68 67

02 01

6A 69 68 67

02 01

2

ADD

02 01 00 FF FE FD FC

8-bit

counter

·······

02 01 00 FF FE FD FC

97 96 95

The ADD

H duration length specified by PWM0H

portions with

additional τ are

determined by

PWML.

256 τ (64 µs), fixed

Fig. 25 14-bit PWM timing (PWM0)

30

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(1) Clock Synchronous Serial I/O Mode

Clock synchronous serial I/O mode can be selected by setting the

serial I/O mode selection bit of the serial I/O control register (bit 6

of SIOCON) to “1”.

SERIAL I/O

Serial I/O

Serial I/O works as either clock synchronous serial I/O mode or

universal asynchronous receiver transmitter (UART) serial I/O

mode. A dedicated timer is also provided for baud rate generation.

For clock synchronous serial I/O, the transmitter and the receiver

must use the same clock. When an internal clock is used, the

transfer starts by writing to the TB.

Data bus

Address 001A16

Serial I/O control register

Address 0018¹⁶

Receive buffer register

Receive buffer full flag (RBF)

Receive interrupt request (RI)

Receive shift register

P44/RXD

Shift clock

Clock control circuit

P46/SCLK

Serial I/O synchronous

clock selection bit

BRG count source selection bit

Address 001C16

f(X^IN

)

Baud rate generator

1/4

(f(XCIN) in low-speed

mode)

Frequency division ratio 1/(n+1)

1/4

Clock control circuit

Falling-edge detector

P47/SRDY/CLKRUN

F/F

Transmit shift completion flag (TSC)

Transmit interrupt source selection bit

Shift clock

P45/TXD

Transmit shift register

Transmit buffer register

Transmit interrupt request (TI)

Transmit buffer empty flag (TBE)

Address 001816

Serial I/O status register

Data bus

Fig. 26 Block diagram of clock synchronous serial I/O

Transfer shift clock

(1/2 to 1/2048 of the internal

clock, or an external clock)

TxD pin

RxD pin

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

D1

D

SRDY pin

Write pulse to transmit buffer

register (TB)

RBF = 1

TSC = 1

Overrun error (OE)

detection

TBE = 0

TSC = 1

TBE = 1

TSC = 0

1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the

transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O

control register.

Notes

2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and the next

serial data is output continuously from the TxD pin.

3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .

Fig. 27 Operation of clock synchronous serial I/O function

31

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(2) Asynchronous Serial I/O (UART) Mode

Universal asynchronous transmitter receiver (UART) serial I/O

mode can be selected by clearing the serial I/O mode selection bit

of the serial I/O control register to “0”.

two buffers assigned the same address. Since the shift register

cannot be written to or read from directly, transmit data is written

to the transmit buffer register, and receive data is read from the re-

ceive buffer register.

Eight serial data transfer formats can be selected, and the transfer

formats used by a transmitter and receiver must be identical.

Both the transmit and receive shift registers have a buffer, but the

The transmit buffer register can also hold the next data to be

transmitted, and the receive buffer register can hold a character

while the next character is being received.

Data bus

Address

001A¹⁶

Address

0018¹⁶

Serial I/O control register

Receive buffer register

Receive buffer full flag (RBF)

Receive interrupt request (RI)

OE

Character length selection bit

P4

4/RX

D

ST detector

7 bits

8 bits

Receive shift register

1/16

UART control register

PE FE SP detector

Address 001B16

Clock control circuit

Serial I/O synchronous clock selection bit

P46/SCLK

Frequency division ratio 1/(n+1)

Baud rate generator

BRG count source selection bit

1/4

f(XIN

)

(f(X^CIN) in low-speed mode)

ST/SP/PA generator

1/16

Transmit shift completion flag (TSC)

Transmit interrupt source selection bit

P45/TXD

Transmit shift register

Transmit interrupt request (TI)

Character length selection bit

Transmit buffer register

Data bus

Transmit buffer empty flag (TBE)

Serial I/O status register

Address 001916

Fig. 28 Block diagram of UART mode

32

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Transmit or receive clock

Transmit buffer write

signal

TBE=0

TSC=0

TBE=1

TBE=0

TSC=1^ꢀ

TBE=1

Serial output TXD pin

ST

SP

D0

D1

ST

D0

D1

SP

^ꢀGenerated at 2nd bit in 2-stop-bit mode

1 start bit

7 or 8 data bit

1 or 0 parity bit

1 or 2 stop bit (s)

Receive buffer read

signal

RBF=0

RBF=1

SP

RBF=1

SP

ST

Serial input R

X

D pin

D0

D1

ST

D0

D1

Notes

1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).

2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting of the transmit

interrupt source selection bit (TIC) of the serial I/O control register.

3: The receive interrupt (RI) is set when the RBF flag becomes “1”.

4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.

Fig. 29 Operation of UART mode function

[Serial I/O Control Register (SIOCON)] 001A16

The serial I/O control register consists of eight control bits for the

serial I/O function.

[Transmit Buffer Register/Receive Buffer

Register (TB/RB)] 001816

The transmit buffer register and the receive buffer register are lo-

cated at the same address. The transmit buffer is write-only and

the receive buffer is read-only. If a character length is 7 bits, the

MSB data stored in the receive buffer is “0”.

[UART Control Register (UARTCON)] 001B16

The UART control register consists of four control bits (bits 0 to 3)

which are valid in UART mode and set the data format of an data

transfer. The POFF bit (bit4) is always valid and define the output

structure of the P45/TXD pin.

[Baud Rate Generator (BRG)] 001C16

The baud rate generator determines the baud rate for serial transfer.

The baud rate generator divides the frequency of the count source

by 1/(n + 1), where n is the value written to the baud rate generator.

[Serial I/O Status Register (SIOSTS)] 001916

The read-only serial I/O status register consists of seven flags

(bits 0 to 6) which indicate the operating status of the serial I/O

function and various errors.

ꢀꢀNotes

When setting the transmit enable bit to “1”, the serial I/O transmit

interrupt request bit is automatically set to “1”. When not requiring

the interrupt occurrence synchronized with the transmission en-

abled, take the following sequence.

Three of the flags (bits 4 to 6) are valid only in UART mode.

The receive buffer full flag (bit 1) is cleared to “0” when the receive

buffer register is read.

If there is an error, it is detected at the same time that data is

transferred from the receive shift register to the receive buffer reg-

ister, and the receive buffer full flag is set. A write to the serial I/O

status register clears all the error flags OE, PE, FE, and SE (bit 3

to bit 6, respectively). Writing “0” to the serial I/O enable bit (SIOE,

bit 7 of SIDCON) also clears all the status flags, including the er-

ror flags.

ꢀ Set the serial I/O transmit interrupt enable bit to “0” (disabled).

ꢀ Set the transmit enable bit to “1”.

ꢀ Set the serial I/O transmit interrupt request bit to “0” after 1 or

more instructions have been executed.

ꢀ Set the serial I/O transmit interrupt enable bit to “1” (enabled).

Bits 0 to 6 of the serial I/O status register are initialized to “0” at re-

set, but if the transmit enable bit (TE, bit 4 of SIOCON) has been

set to “1”, the transmit shift completion flag (TSC, bit 2) and the

transmit buffer empty flag (TBE, bit 0) become “1”.

33

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

b7

b0

b7

Serial I/O status register

(SIOSTS : address 001916

Serial I/O control register

(SIOCON : address 001A16

)

BRG count source selection bit (CSS)

0: f(XIN) (f(XCIN) in low-speed mode)

1: f(XIN)/4 (f(XCIN)/4 in low-speed mode)

Transmit buffer empty flag (TBE)

0: Buffer full

1: Buffer empty

Serial I/O synchronous clock selection bit (SCS)

0: BRG output divided by 4 when clock synchronous

serial I/O is selected, BRG output divided by 16

when UART is selected.

Receive buffer full flag (RBF)

0: Buffer empty

1: Buffer full

1: External clock input when clock synchronous serial

I/O is selected, external clock input divided by 16

when UART is selected.

Transmit shift completion flag (TSC)

0: Transmit shift in progress

1: Transmit shift completed

S

0: P4

1: P4

RDY output enable bit (SRDY)

Overrun error flag (OE)

0: No error

1: Overrun error

7

pin operates as ordinary I/O pin

pin operates as SRDY output pin

7

Transmit interrupt source selection bit (TIC)

0: Interrupt when transmit buffer has emptied

1: Interrupt when transmit shift operation is completed

Parity error flag (PE)

0: No error

1: Parity error

Transmit enable bit (TE)

0: Transmit disabled

1: Transmit enabled

Framing error flag (FE)

0: No error

1: Framing error

Receive enable bit (RE)

0: Receive disabled

1: Receive enabled

Summing error flag (SE)

0: (OE) U (PE) U (FE)=0

1: (OE) U (PE) U (FE)=1

Serial I/O mode selection bit (SIOM)

0: Clock asynchronous (UART) serial I/O

1: Clock synchronous serial I/O

Not used (returns “1” when read)

Serial I/O enable bit (SIOE)

0: Serial I/O disabled

(pins P4

1: Serial I/O enabled

(pins P4 to P4 operate as serial I/O pins)

4 to P47 operate as ordinary I/O pins)

b0

b7

UART control register

(UARTCON : address 001B16

)

4

7

Character length selection bit (CHAS)

0: 8 bits

1: 7 bits

Parity enable bit (PARE)

0: Parity checking disabled

1: Parity checking enabled

Parity selection bit (PARS)

0: Even parity

1: Odd parity

Stop bit length selection bit (STPS)

0: 1 stop bit

1: 2 stop bits

P45/TXD P-channel output disable bit (POFF)

0: CMOS output (in output mode)

1: N-channel open drain output (in output mode)

Not used (return “1” when read)

Fig. 30 Structure of serial I/O control registers

34

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

2

Table 10 Multi-master I C-BUS interface functions

MULTI-MASTER I C-BUS INTERFACE

2

The multi-master I C-BUS interface is a serial communications cir-

Item

Function

2

cuit, conforming to the Philips I C-BUS data transfer format. This

2

In conformity with Philips I C-BUS

standard:

interface, offering both arbitration lost detection and a synchronous

functions, is useful for the multi-master serial communications.

10-bit addressing format

7-bit addressing format

High-speed clock mode

Standard clock mode

Format

2

Figure 31 shows a block diagram of the multi-master I C-BUS in-

2

terface and Table 10 lists the multi-master I C-BUS interface

functions.

2

In conformity with Philips I C-BUS

standard:

Master transmission

Master reception

Slave transmission

Slave reception

2

This multi-master I C-BUS interface consists of the I C address

2

register, the I C data shift register, the I C clock control register,

Communication mode

SCL clock frequency

2

the I C control register, the I C status register, the I C start/stop

condition control register and other control circuits.

2

When using the multi-master I C-BUS interface, set 1 MHz or

16.1 kHz to 400 kHz (at φ = 4 MHz)

more to system clock φ.

System clock φ = f(XIN)/2 (high-speed mode)

φ = f(XIN)/8 (middle-speed mode)

I²C address register

b7

b0

SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB

Interrupt

generating

circuit

Interrupt

generating

circuit

Interrupt request signal

(I²CIRQ)

Interrupt request signal

(S^CLDAIRQ)

S

S0D

Address comparator

I²C data shift register

Serial data

Noise

elimination

circuit

Data

control

circuit

b7

b0

(SDA

)

b7

b0

S

0

AL AAS AD0 LRB

MST TRX BB PIN

S1

S2D

AL

circuit

STSP

SEL

SIS SIP

SSC4SSC3 SSC2 SSC1 SSC0

I²C status register

2

I C start/stop condition

control register

Internal data bus

BB

circuit

Serial

clock

I²C clock control register

Noise

elimination

circuit

S1D

Clock

control

circuit

b7

b0

b7

b0

(SCL

)

CLK 10BIT

STP SAD ALS

FAST

MODE

ACK

BIT

CCR4 CCR3 CCR2 CCR1 CCR0

TISS

ACK

ES0 BC2 BC1 BC0

Bit counter

S2

I²C clock control register

System clock (φ)

Stop selection

Clock division

2

Fig. 31 Block diagram of multi-master I C-BUS interface

✽✽: Purchase of MITSUBISHI ELECTRIC CORPORATIONS I²C components conveys a license under the Philips I²C Patent Rights to use these components

an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

35

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

2

[I C Data Shift Register (S0)] 001216

2

The I C data shift register (S0) is an 8-bit shift register to store re-

b7

b0

I²C address register

ceive data and write transmit data.

SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB

(S0D: address 001316

)

When transmit data is written into this register, it is transferred to

the outside from bit 7 in synchronization with the SCL clock, and

each time one-bit data is output, the data of this register are

shifted by one bit to the left. When data is received, it is input to

this register from bit 0 in synchronization with the SCL clock, and

each time one-bit data is input, the data of this register are shifted

by one bit to the left. The minimum 2 cycles of φ are required from

the rising of the SCL clock until input to this register.

Read/write bit

Slave address

2

Fig. 32 Structure of I C address register

2

The I C data shift register is in a write enable status only when the

2

I C-BUS interface enable bit (ES0 bit : bit 3 S1D) of the I C con-

trol register is “1”. The bit counter is reset by a write instruction to

2

the I C data shift register. When both the ES0 bit and the MST bit

2

of the I C status register (S1) are “1”, the SCL is output by a write

2

instruction to the I C data shift register. Reading data from the I C

data shift register is always enabled regardless of the ES0 bit

value.

2

[I C Address Register (S0D)] 001316

2

The I C address register (S0D) consists of a 7-bit slave address and

_______

a read/write bit. In the addressing mode, the slave address written in

this register is compared with the address data to be received imme-

diately after the START condition is detected.

•Bit 0: Read/^_w^___r^_i^_t^_e^__bit (RWB)

This is not used in the 7-bit addressing mode. In the 10-bit ad-

dressing mode, the first address data to be received is compared

2

with the contents (SAD6 to SAD0 + RWB) of the I C address reg-

ister.

The RWB bit is cleared to “0” automatically when the stop condi-

tion is detected.

•Bits 1 to 7: Slave address (SAD0–SAD6)

These bits store slave addresses. Regardless of the 7-bit address-

ing mode and the 10-bit addressing mode, the address data

transmitted from the master is compared these bits.

36

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

2

[I C Clock Control Register (S2)] 001616

2

b7

b0

The I C clock control register (S2) is used to set ACK control, SCL

I²C clock control register

(S2 : address 001616

ACK FAST

BIT MODE

ACK

CCR4 CCR3 CCR2 CCR1 CCR0

mode and SCL frequency.

)

•Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)

These bits control the SCL frequency. Refer to Table 11.

•Bit 5: SCL mode specification bit (FAST MODE)

This bit specifies the SCL mode. When this bit is set to “0”, the

standard clock mode is selected. When the bit is set to “1”, the

high-speed clock mode is selected.

SCL frequency control

bits

Refer to Table 11.

SCL mode specification bit

0 : Standard clock mode

1 : High-speed clock

mode

2

When connecting the bus of the high-speed mode I C bus stan-

ACK bit

0 : ACK is returned.

1 : ACK is not

returned.

dard (maximum 400 kbits/s), use 8 MHz or more oscillation

frequency f(XIN) and high-speed mode (2 division main clock).

•Bit 6: ACK bit (ACK BIT)

ACK clock bit

0 : No ACK clock

1 : ACK clock

ꢀ

This bit sets the SDA status when an ACK clock is generated.

When this bit is set to “0”, the ACK return mode is selected and

SDA goes to “L” at the occurrence of an ACK clock. When the bit is

set to “1”, the ACK non-return mode is selected. The SDA is held in

the “H” status at the occurrence of an ACK clock.

2

Fig. 33 Structure of I C clock control register

2

Table 11 Set values of I C clock control register and SCL

However, when the slave address matches with the address data

in the reception of address data at ACK BIT = “0”, the SDA is au-

tomatically made “L” (ACK is returned). If there is a unmatch

between the slave address and the address data, the SDA is auto-

matically made “H” (ACK is not returned).

frequency

Setting value of

CCR4–CCR0

SCL frequency

(at φ = 4 MHz, unit : kHz) (Note 1)

Standard clock

mode

High-speed clock

mode

CCR4 CCR3 CCR2 CCR1 CCR0

Setting disabled Setting disabled

0

1

0

1

0

1

0

1

0

1

0

1

0

ꢀACK clock: Clock for acknowledgment

Setting disabled

333

Setting disabled

– (Note 2)

100

•Bit 7: ACK clock bit (ACK)

This bit specifies the mode of acknowledgment which is an ac-

knowledgment response of data transfer. When this bit is set to

“0”, the no ACK clock mode is selected. In this case, no ACK clock

occurs after data transmission. When the bit is set to “1”, the ACK

clock mode is selected and the master generates an ACK clock

each completion of each 1-byte data transfer. The device for

transmitting address data and control data releases the SDA at the

occurrence of an ACK clock (makes SDA “H”) and receives the

ACK bit generated by the data receiving device.

250

400 (Note 3)

166

83.3

1000/CCR value

500/CCR value

(Note 3)

1

0

1

0

1

34.5

33.3

32.3

17.2

16.6

16.1

Note: Do not write data into the I²C clock control register during transfer. If

data is written during transfer, the I²C clock generator is reset, so

that data cannot be transferred normally.

Notes 1: Duty of SCL clock output is 50 %. The duty becomes 35 to 45 %

only when the high-speed clock mode is selected and CCR value

= 5 (400 kHz, at φ = 4 MHz). “H” duration of the clock fluctuates

from –4 to +2 cycles of φ in the standard clock mode, and fluctu-

ates from –2 to +2 cycles of φ in the high-speed clock mode. In

the case of negative fluctuation, the frequency does not increase

because “L” duration is extended instead of “H” duration reduc-

tion.

These are value when SCL clock synchronization by the synchro-

nous function is not performed. CCR value is the decimal

notation value of the SCL frequency control bits CCR4 to CCR0.

2: Each value of SCL frequency exceeds the limit at φ = 4 MHz or

more. When using these setting value, use φ of 4 MHz or less.

3: The data formula of SCL frequency is described below:

φ/(8 ꢀ CCR value) Standard clock mode

φ/(4 ꢀ CCR value) High-speed clock mode (CCR value ≠ 5)

φ/(2 ꢀ CCR value) High-speed clock mode (CCR value = 5)

Do not set 0 to 2 as CCR value regardless of φ frequency.

Set 100 kHz (max.) in the standard clock mode and 400 kHz

(max.) in the high-speed clock mode to the SCL frequency by set-

ting the SCL frequency control bits CCR4 to CCR0.

37

MITSUBISHI MICROCOMPUTERS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

2

[I C Control Register (S1D)] 001516

2

b7

b0

The I C control register (S1D) controls data communication for-

I²C control register

CLK 10 BIT

STP SAD

TISS

ALS ES0 BC2 BC1 BC0

mat.

(S1D : address 001516)

•Bits 0 to 2: Bit counter (BC0–BC2)

These bits decide the number of bits for the next 1-byte data to be

Bit counter (Number of

transmit/receive bits)

b2 b1 b0

2

transmitted. The I C interrupt request signal occurs immediately

after the number of count specified with these bits (ACK clock is

added to the number of count when ACK clock is selected by ACK

bit (bit 7 of S2)) have been transferred, and BC0 to BC2 are re-

turned to “0002”.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

: 8

: 7

: 6

: 5

: 4

: 3

: 2

: 1

Also when a START condition is received, these bits become

“0002” and the address data is always transmitted and received in

8 bits.

I²C-BUS interface

enable bit

0 : Disabled

1 : Enabled

2

•Bit 3: I C interface enable bit (ES0)

2

This bit enables to use the multi-master I C BUS interface. When

this bit is set to “0”, the use disable status is provided, so that the

SDA and the SCL become high-impedance. When the bit is set to

“1”, use of the interface is enabled.

Data format selection bit

0 : Addressing format

1 : Free data format

When ES0 = “0”, the following is performed.

Addressing format selection bit

0 : 7-bit addressing format

1 : 10-bit addressing format

2

• PIN = “1”, BB = “0” and AL = “0” are set (which are bits of the I C

status register at S1 ).

2

• Writing data to the I C data shift register (S0) is disabled.

System clock stop selection bit

0 : System clock stop

when executing WIT

or STP instruction

1 : Not system clock

stop when executing

WIT instruction

•Bit 4: Data format selection bit (ALS)

This bit decides whether or not to recognize slave addresses.

When this bit is set to “0”, the addressing format is selected, so

that address data is recognized. When a match is found between

a slave address and address data as a result of comparison or

(Do not use the STP

instruction.)

2

when a general call (refer to “I C Status Register”, bit 1) is re-

ceived, transfer processing can be performed. When this bit is set

to “1”, the free data format is selected, so that slave addresses are

not recognized.

I²C-BUS interface pin input

level selection bit

0 : CMOS input

1 : SMBUS input

•Bit 5: Addressing format selection bit (10BIT SAD)

This bit selects a slave address specification format. When this bit

is set to “0”, the 7-bit addressing format is selected. In this case,

2

only the high-order 7 bits (slave address) of the I C address regis-

2

Fig. 34 Structure of I C control register

ter (S0D) are compared with address data. When this bit is set to

“1”, the 10-bit addressing format is selected, and all the bits of the

2

I C address register are compared with address data.

•Bit 6: System clock stop selection bit (CLKSTP)

When executing the WIT or STP instruction, this bit selects the

2

condition of system clock provided to the multi-master I C-BUS in-

terface. When this bit is set to “0”, system clock and operation of

2

the multi-master I C-BUS interface stop by executing the WIT or

STP instruction.

When this bit is set to “1”, system clock and operation of the multi-

2

master I C-BUS interface do not stop even when the WIT

instruction is executed.

When the system clock stop selection bit is “1”, do not execute the

STP instruction.

2

•Bit 7: I C-BUS interface pin input level selection bit

This bit selects the input level of the SCL and SDA pins of the multi-

2

master I C-BUS interface.

38

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

2

[I C Status Register (S1)] 001416

•Bit 4: SCL pin low hold bit (PIN)

2

The I C status register (S1) controls the I C-BUS interface status.

The low-order 4 bits are read-only bits and the high-order 4 bits

can be read out and written to.

This bit generates an interrupt request signal. Each time 1-byte

data is transmitted, the PIN bit changes from “1” to “0”. At the

same time, an interrupt request signal occurs to the CPU. The PIN

bit is set to “0” in synchronization with a falling of the last clock (in-

cluding the ACK clock) of an internal clock and an interrupt

request signal occurs in synchronization with a falling of the PIN

bit. When the PIN bit is “0”, the SCL is kept in the “0” state and

clock generation is disabled. Figure 42 shows an interrupt request

signal generating timing chart.

Set “00002” to the low-order 4 bits, because these bits become the

reserved bits at writing.

•Bit 0: Last receive bit (LRB)

This bit stores the last bit value of received data and can also be

used for ACK receive confirmation. If ACK is returned when an

ACK clock occurs, the LRB bit is set to “0”. If ACK is not returned,

this bit is set to “1”. Except in the ACK mode, the last bit value of

received data is input. The state of this bit is changed from “1” to

The PIN bit is set to “1” in one of the following conditions:

2

• Executing a write instruction to the I C data shift register (S0).

2

“0” by executing a write instruction to the I C data shift register

(This is the only condition which the prohibition of the internal

clock is released and data can be communicated except for the

start condition detection.)

(S0).

•Bit 1: General call detecting flag (AD0)

ꢀ

When the ALS bit is “0”, this bit is set to “1” when a general call

whose address data is all “0” is received in the slave mode. By a

general call of the master device, every slave device receives con-

trol data after the general call. The AD0 bit is set to “0” by

detecting the STOP condition or START condition, or reset.

• When the ES0 bit is “0”

• At reset

• When writing “1” to the PIN bit by software

The conditions in which the PIN bit is set to “0” are shown below:

• Immediately after completion of 1-byte data transmission (includ-

ing when arbitration lost is detected)

ꢀGeneral call: The master transmits the general call address “0016” to all

• Immediately after completion of 1-byte data reception

• In the slave reception mode, with ALS = “0” and immediately af-

ter completion of slave address agreement or general call

address reception

slaves.

•Bit 2: Slave address comparison flag (AAS)

This flag indicates a comparison result of address data when the

ALS bit is “0”.

• In the slave reception mode, with ALS = “1” and immediately af-

ter completion of address data reception

ꢀ In the slave receive mode, when the 7-bit addressing format is

selected, this bit is set to “1” in one of the following conditions:

• The address data immediately after occurrence of a START

condition agrees with the slave address stored in the high-or-

•Bit 5: Bus busy flag (BB)

This bit indicates the status of use of the bus system. When this

bit is set to “0”, this bus system is not busy and a START condition

can be generated. The BB flag is set/reset by the SCL, SDA pins in-

put signal regardless of master/slave. This flag is set to “1” by

detecting the start condition, and is set to “0” by detecting the stop

condition. The condition of these detecting is set by the start/stop

condition setting bits (SSC4–SSC0) of S2D. When the ES0 bit (bit

3 of S1D) is “0” or reset, the BB flag is set to “0”.

For the writing function to the BB flag, refer to the sections

“START Condition Generating Method” and “STOP Condition Gen-

erating Method” described later.

2

der 7 bits of the I C address register (S0D).

• A general call is received.

ꢀ In the slave reception mode, when the 10-bit addressing format

is selected, this bit is set to “1” with the following condition:

2

• When the address data is compared with the I C address reg-

ister (8 bits consisting of slave address and RWB bit), the first

bytes agree.

2

ꢀꢀThis bit is set to “0” by executing a write instruction to the I C

data shift register (S0) when ES0 is set to “1” or reset.

ꢀ

•Bit 3: Arbitration lost detecting flag (AL)

In the master transmission mode, when the SDA is made “L” by

any other device, arbitration is judged to have been lost, so that

this bit is set to “1”. At the same time, the TRX bit is set to “0”, so

that immediately after transmission of the byte whose arbitration

was lost is completed, the MST bit is set to “0”. The arbitration lost

can be detected only in the master transmission mode. When ar-

bitration is lost during slave address transmission, the TRX bit is

set to “0” and the reception mode is set. Consequently, it becomes

possible to detect the agreement of its own slave address and ad-

dress data transmitted by another master device.

ꢀArbitration lost :The status in which communication as a master is dis-

abled.

39

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

•Bit 6: Communication mode specification bit

(transfer direction specification bit: TRX)

b7

b0

I²C status register

MST TRX BB

AL AAS AD0 LRB

This bit decides a direction of transfer for data communication.

When this bit is “0”, the reception mode is selected and the data of

a transmitting device is received. When the bit is “1”, the transmis-

sion mode is selected and address data and control data are

output onto the SDA in synchronization with the clock generated on

the SCL.

(S1 : address 001416

)

Last receive bit (Note)

0 : Last bit = “0”

1 : Last bit = “1”

General call detecting flag

(Note)

0 : No general call detected

1 : General call detected

This bit is set/reset by software and hardware. About set/reset by

hardware is described below. This bit is set to “1” by hardware

when all the following conditions are satisfied:

• When ALS is “0”

Slave address comparison flag

(Note)

0 : Address disagreement

1 : Address agreement

• In the slave reception mode or the slave transmission mode

___

• When the R/W bit reception is “1”

This bit is set to “0” in one of the following conditions:

• When arbitration lost is detected.

Arbitration lost detecting flag

(Note)

• When a STOP condition is detected.

• When writing “1” to this bit by software is invalid by the START

condition duplication preventing function (Note).

• With MST = “0” and when a START condition is detected.

• With MST = “0” and when ACK non-return is detected.

• At reset

0 : Not detected

1 : Detected

SCL pin low hold bit

0 : low hold

1 : release

•Bit 7: Communication mode specification bit

(master/slave specification bit: MST)

Bus busy flag

0 : Bus free

1 : Bus busy

This bit is used for master/slave specification for data communica-

tion. When this bit is “0”, the slave is specified, so that a START

condition and a STOP condition generated by the master are re-

ceived, and data communication is performed in synchronization

with the clock generated by the master. When this bit is “1”, the

master is specified and a START condition and a STOP condition

are generated. Additionally, the clocks required for data communi-

cation are generated on the SCL.

Communication mode

specification bits

00 : Slave receive mode

01 : Slave transmit mode

10 : Master receive mode

11 : Master transmit mode

This bit is set to “0” in one of the following conditions.

• Immediately after completion of 1-byte data transfer when arbi-

tration lost is detected

Note: These bit and flags can be read out but cannot

be written.

Write “0” to these bits at writing.

• When a STOP condition is detected.

2

Fig. 35 Structure of I C status register

• Writing “1” to this bit by software is invalid by the START condi-

tion duplication preventing function (Note).

• At reset

Note: START condition duplication preventing function

SCL

The MST, TRX, and BB bits is set to “1” at the same time after con-

firming that the BB flag is “0” in the procedure of a START condition

occurrence. However, when a START condition by another master

device occurs and the BB flag is set to “1” immediately after the con-

tents of the BB flag is confirmed, the START condition duplication

preventing function makes the writing to the MST and TRX bits in-

valid. The duplication preventing function becomes valid from the

rising of the BB flag to reception completion of slave address.

I²CIRQ

Fig. 36 Interrupt request signal generating timing

40

MITSUBISHI MICROCOMPUTERS

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START Condition Generating Method

START/STOP Condition Detecting Operation

The START/STOP condition detection operations are shown in

Figures 39, 40, and Table 14. The START/STOP condition is set

by the START/STOP condition set bit.

The START/STOP condition can be detected only when the input

signal of the SCL and SDA pins satisfy three conditions: SCL re-

lease time, setup time, and hold time (see Table 14).

The BB flag is set to “1” by detecting the START condition and is

reset to “0” by detecting the STOP condition.

2

When writing “1” to the MST, TRX, and BB bits of the I C status

register (S1) at the same time after writing the slave address to

2

the I C data shift register (S0) with the condition in which the ES0

2

bit of the I C control register (S1D) and the BB flag are “0”, a

START condition occurs. After that, the bit counter becomes

“0002” and an SCL for 1 byte is output. The START condition gen-

erating timing is different in the standard clock mode and the

high-speed clock mode. Refer to Figure 37, the START condition

generating timing diagram, and Table 12, the START condition

generating timing table.

The BB flag set/reset timing is different in the standard clock mode

and the high-speed clock mode. Refer to Table 14, the BB flag set/

reset time.

Note: When a STOP condition is detected in the slave mode (MST = 0), an

interrupt request signal “I²CIRQ” occurs to the CPU.

I²C status register

write signal

S

CL

DA

Setup

time

SCL release time

Hold time

SCL

Setup

Hold time

time

SDA

Fig. 37 START condition generating timing diagram

BB flag

reset

time

BB flag

Table 12 START condition generating timing table

START/STOP condition

generating selection bit clock mode

Standard

High-speed

clock mode

Fig. 39 START condition detecting timing diagram

Item

5.0 µs (20 cycles) 2.5 µs (10 cycles)

13.0 µs (52 cycles) 6.5 µs (26 cycles)

5.0 µs (20 cycles) 2.5 µs (10 cycles)

13.0 µs (52 cycles) 6.5 µs (26 cycles)

“0”

“1”

“0”

“1”

Setup

time

SCL release time

SCL

Hold

time

Setup

Hold time

time

SDA

BB flag

Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the

number of φ cycles.

reset

time

BB flag

STOP Condition Generating Method

Fig. 40 STOP condition detecting timing diagram

2

When the ES0 bit of the I C control register (S1D) is “1”, write “1”

2

to the MST and TRX bits, and write “0” to the BB bit of the I C sta-

Table 14 START condition/STOP condition detecting conditions

tus register (S1) simultaneously. Then a STOP condition occurs.

The STOP condition generating timing is different in the standard

clock mode and the high-speed clock mode. Refer to Figure 38,

the STOP condition generating timing diagram, and Table 13, the

STOP condition generating timing table.

Standard clock mode

High-speed clock mode

SCL release time

SSC value + 1 cycle (6.25 µs)

4 cycles (1.0 µs)

SSC value

Setup time

Hold time

+ 1 cycle < 4.0 µs (3.25 µs)

2 cycles (1.0 µs)

2 cycles (0.5 µs)

2

SSC value

cycle < 4.0 µs (3.0 µs)

2

BB flag set/

reset time

SSC value –1

3.5 cycles (0.875 µs)

+ 2 cycles (3.375 µs)

I²C status register

write signal

2

Note: Unit : Cycle number of system clock φ

SSC value is the decimal notation value of the START/STOP condi-

tion set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC

value. The value in parentheses is an example when the I²C START/

STOP condition control register is set to “1816” at φ = 4 MHz.

SCL

Setup

time

Hold time

SDA

Fig. 38 STOP condition generating timing diagram

Table 13 STOP condition generating timing table

START/STOP condition

generating selection bit clock mode

Standard

High-speed

clock mode

Item

“0”

“1”

“0”

“1”

5.5 µs (22 cycles) 3.0 µs (12 cycles)

13.5 µs (54 cycles) 7.0 µs (28 cycles)

5.5 µs (22 cycles) 3.0 µs (12 cycles)

13.5 µs (54 cycles) 7.0 µs (28 cycles)

Setup

time

Hold

time

Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the

number of φ cycles.

41

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

2

[I C START/STOP Condition Control Register

ꢀ 10-bit addressing format

(S2D)] 001716

The I C START/STOP condition control register (S2D) controls

To adapt the 10-bit addressing format, set the 10BIT SAD bit of

2

the I C control register (S1D) to “1”. An address comparison is

START/STOP condition detection.

performed between the first-byte address data transmitted from

2

•Bits 0 to 4: START/STOP condition set bits (SSC4–SSC0)

SCL release time, setup time, and hold time change the detection

condition by value of the main clock divide ratio selection bit and

the oscillation frequency f(XIN) because these time are measured

by the internal system clock. Accordingly, set the proper value to

the START/STOP condition set bits (SSC4 to SSC0) in considered

of the system clock frequency. Refer to Table 14.

the master and the 8-bit slave address stored in the I C ad-

dress register (S0). At the time of this comparison, an address

2

comparison between the RWB bit of the I C address register

(S0) and the R/W bit which is the last bit of the address data

transmitted from the master is made. In the 10-bit addressing

mode, the RWB bit which is the last bit of the address data not

only specifies the direction of communication for control data,

but also is processed as an address data bit.

Do not set “000002” or an odd number to the START/STOP condi-

tion set bits (SSC4 to SSC0).

When the first-byte address data agree with the slave address,

2

Refer to Table 15, the recommended set value to START/STOP

condition set bits (SSC4–SSC0) for each oscillation frequency.

•Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP)

An interrupt can occur when detecting the falling or rising edge of

the SCL or SDA pin. This bit selects the polarity of the SCL or SDA

pin interrupt pin.

the AAS bit of the I C status register (S1) is set to “1”. After the

2

second-byte address data is stored into the I C data shift reg-

ister (S0), perform an address comparison between the

second-byte data and the slave address by software. When the

address data of the 2 bytes agree with the slave address, set

2

the RWB bit of the I C address register (S0D) to “1” by soft-

•Bit 6: SCL/SDA interrupt pin selection bit (SIS)

ware. This processing can make the 7-bit slave address and R/

___

This bit selects the pin of which interrupt becomes valid between

W data agree, which are received after a RESTART condition

2

the SCL pin and the SDA pin.

is detected, with the value of the I C address register (S0D).

Note: When changing the setting of the SCL/SDA interrupt pin polarity se-

lection bit, the SCL/SDA interrupt pin selection bit, or the I²C-BUS

interface enable bit ES0, the SCL/SDA interrupt request bit may be

set. When selecting the SCL/SDA interrupt source, disable the inter-

rupt before the SCL/SDA interrupt pin polarity selection bit, the SCL/

SDA interrupt pin selection bit, or the I²C-BUS interface enable bit

ES0 is set. Reset the request bit to “0” after setting these bits, and

enable the interrupt.

For the data transmission format when the 10-bit addressing

format is selected, refer to Figure 42, (3) and (4).

•Bit 7: START/STOP condition generating selection bit

(STSPSEL)

Setup/Hold time when the START/STOP condition is generated

can be selected.

Cycle number of system clock becomes standard for setup/hold

time. Additionally, setup/hold time is different between the START

condition and the STP condition. (Refer to Tables 12 and 13.) Set

“1” to this bit when the system clock frequency is 4 MHz or more.

Address Data Communication

There are two address data communication formats, namely, 7-bit

addressing format and 10-bit addressing format. The respective

address communication formats are described below.

ꢀ 7-bit addressing format

To adapt the 7-bit addressing format, set the 10BIT SAD bit of

2

the I C control register (S1D) to “0”. The first 7-bit address data

transmitted from the master is compared with the high-order 7-

2

bit slave address stored in the I C address register (S0D). At

the time of this comparison, address comparison of the RWB bit

2

of the I C address register (S0D) is not performed. For the data

transmission format when the 7-bit addressing format is se-

lected, refer to Figure 42, (1) and (2).

42

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

b7

STSP

SEL SIS SIP

b0

I²C START/STOP condition

control register

SSC4SSC3 SSC2 SSC1SSC0

(S2D : address 001716

)

START/STOP condition set bits

S

CL/SDA interrupt pin polarity

selection bit

0 : Falling edge active

1 : Rising edge active

S

CL/SDA interrupt pin selection bit

0 : SDA valid

1 : SCL valid

START/STOP condition generating

selection bit

0 : Setup/Hold time short mode

1 : Setup/Hold time long mode

2

Fig. 41 Structure of I C START/STOP condition control register

Table 15 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency

Oscillation

frequency

f(XIN) (MHz)

START/STOP

condition

control register

System

clock φ

(MHz)

Main clock

divide ratio

SCL release time

Setup time

Hold time

(µs)

8

4

2

XXX11010

XXX11000

XXX00100

XXX01100

XXX01010

XXX00100

6.75 µs (27 cycles)

6.25 µs (25 cycles)

5.0 µs (5 cycles)

6.5 µs (13 cycles)

5.5 µs (11 cycles)

5.0 µs (5 cycles)

3.5 µs (14 cycles)

3.25 µs (13 cycles)

3.0 µs (3 cycles)

3.5 µs (7 cycles)

3.0 µs (6 cycles)

3.0 µs (3 cycles)

3.25 µs (13 cycles)

3.0 µs (12 cycles)

2.0 µs (2 cycles)

3.0 µs (6 cycles)

2.5 µs (5 cycles)

2.0 µs (2 cycles)

2

8

2

4

1

2

1

Note: Do not set “000002” or an odd number to the START/STOP condition set bits (SSC4 to SSC0).

A

Data

A

Data

S

Slave address R/W

7 bits “0”

A/A

P

1 to 8 bits

(1) A master-transmitter transnmits data to a slave-receiver

A

Data

A

Data

Slave address

7 bits

S

R/W

“1”

P

A

1 to 8 bits

(2) A master-receiver receives data from a slave-transmitter

Slave address

1st 7 bits

Slave address

2nd bytes

A

Data

1 to 8 bits

A

Data

S

R/W

“0”

A/A

P

7 bits

8 bits

1 to 8 bits

(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address

Slave address

1st 7 bits

Slave address

2nd bytes

Slave address

1st 7 bits

Data

1 to 8 bits

P

A

Data

S

R/W

“0”

Sr

R/W

“1”

A

1 to 8 bits

7 bits

8 bits

7 bits

(4) A master-receiver receives data from a slave-transmitter with a 10-bit address

S : START condition

A : ACK bit

P : STOP condition

R/W : Read/Write bit

Sr : Restart condition

Fig. 42 Address data communication format

43

MITSUBISHI MICROCOMPUTERS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

2

Example of Master Transmission

An example of master transmission in the standard clock mode, at

the SCL frequency of 100 kHz and in the ACK return mode is

shown below.

ꢀPrecautions when using multi-master I C-

BUS interface

(1) Read-modify-write instruction

The precautions when the read-modify-write instruction such as

SEB, CLB etc. is executed for each register of the multi-master

2

(1) Set a slave address in the high-order 7 bits of the I C address

2

register (S0D) and “0” into the RWB bit.

I C-BUS interface are described below.

2

(2) Set the ACK return mode and SCL = 100 kHz by setting “8516”

• I C data shift register (S0: address 001216)

2

in the I C clock control register (S2).

When executing the read-modify-write instruction for this regis-

ter during transfer, data may become a value not intended.

2

(3) Set “0016” in the I C status register (S1) so that transmission/

2

reception mode can become initializing condition.

• I C address register (S0D: address 001316)

2

(4) Set a communication enable status by setting “0816” in the I C

When the read-modify-write instruction is executed for this regis-

ter at detecting the STOP condition, data may become a value

not intended. It is because H/W changes the read/write bit

(RWB) at the above timing.

control register (S1D).

2

(5) Confirm the bus free condition by the BB flag of the I C status

register (S1).

2

(6) Set the address data of the destination of transmission in the

• I C status register (S1: address 001416)

2

high-order 7 bits of the I C data shift register (S0) and set “0”

Do not execute the read-modify-write instruction for this register

in the least significant bit.

because all bits of this register are changed by H/W.

2

(7) Set “F016” in the I C status register (S1) to generate a START

• I C control register (S1D: address 001516)

condition. At this time, an SCL for 1 byte and an ACK clock au-

tomatically occur.

When the read-modify-write instruction is executed for this regis-

ter at detecting the START condition or at completing the byte

transfer, data may become a value not intended. Because H/W

changes the bit counter (BC0-BC2) at the above timing.

2

(8) Set transmit data in the I C data shift register (S0). At this time,

an SCL and an ACK clock automatically occur.

2

(9) When transmitting control data of more than 1 byte, repeat step

(8).

• I C clock control register (S2: address 001616)

The read-modify-write instruction can be executed for this register.

2

(10) Set “D016” in the I C status register (S1) to generate a STOP

• I C START/STOP condition control register (S2D: address

condition if ACK is not returned from slave reception side or

transmission ends.

001716)

The read-modify-write instruction can be executed for this register.

Example of Slave Reception

An example of slave reception in the high-speed clock mode, at

the SCL frequency of 400 kHz, in the ACK non-return mode and

using the addressing format is shown below.

2

(1) Set a slave address in the high-order 7 bits of the I C address

register (S0D) and “0” in the RWB bit.

(2) Set the no ACK clock mode and SCL = 400 kHz by setting

2

“2516” in the I C clock control register (S2).

2

(3) Set “0016” in the I C status register (S1) so that transmission/

reception mode can become initializing condition.

2

(4) Set a communication enable status by setting “0816” in the I C

control register (S1D).

(5) When a START condition is received, an address comparison

is performed.

(6)•When all transmitted addresses are “0” (general call):

2

AD0 of the I C status register (S1) is set to “1” and an interrupt

request signal occurs.

• When the transmitted address matches with the address set

in (1):

2

ASS of the I C status register (S1) is set to “1” and an interrupt

request signal occurs.

2

• In the cases other than the above AD0 and AAS of the I C

status register (S1) are set to “0” and no interrupt request sig-

nal occurs.

2

(7) Set dummy data in the I C data shift register (S0).

(8) When receiving control data of more than 1 byte, repeat step (7).

(9) When a STOP condition is detected, the communication ends.

44

MITSUBISHI MICROCOMPUTERS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

2

(2) START condition generating procedure using multi-master

1. Procedure example (The necessary conditions of the generat-

ing procedure are described as the following 2 to 5.

(4) Writing to I C status register

Do not execute an instruction to set the PIN bit to “1” from “0” and

an instruction to set the MST and TRX bits to “0” from “1” simulta-

neously. It is because it may enter the state that the SCL pin is

released and the SDA pin is released after about one machine

cycle. Do not execute an instruction to set the MST and TRX bits

to “0” from “1” simultaneously when the PIN bit is “1”. It is because

it may become the same as above.

LDA —

(Taking out of slave address value)

(Interrupt disabled)

SEI

BBS 5, S1, BUSBUSY (BB flag confirming and branch pro

cess)

BUSFREE:

STA S0

(Writing of slave address value)

(Trigger of START condition generating)

(Interrupt enabled)

(5) Process of after STOP condition generating

2

LDM #$F0, S1

CLI

Do not write data in the I C data shift register S0 and the I C sta-

tus register S1 until the bus busy flag BB becomes “0” after

generating the STOP condition in the master mode. It is because

the STOP condition waveform might not be normally generated.

Reading to the above registers do not have the problem.

BUSBUSY:

CLI

(Interrupt enabled)

2. Use “Branch on Bit Set” of “BBS 5, $0014, –” for the BB flag

confirming and branch process.

(6) ES0 bit switch

In standard clock mode when SSC = “000102” or in high-speed

clock mode, flag BB may switch to “1” if ES0 bit is set to “1” when

SDA is “L”.

3. Use “STA $12, STX $12” or “STY $12” of the zero page ad-

dressing instruction for writing the slave address value to the

2

I C data shift register.

Countermeasure:

4. Execute the branch instruction of above 2 and the store instruc-

tion of above 3 continuously shown the above procedure

example.

Set ES0 to “1” when SDA is “H”.

5. Disable interrupts during the following three process steps:

• BB flag confirming

• Writing of slave address value

• Trigger of START condition generating

When the condition of the BB flag is bus busy, enable interrupts

immediately.

(3) RESTART condition generating procedure

1. Procedure example (The necessary conditions of the generat-

ing procedure are described as the following 2 to 4.)

Execute the following procedure when the PIN bit is “0”.

LDM #$00, S1

LDA —

(Select slave receive mode)

(Taking out of slave address value)

(Interrupt disabled)

SEI

STAS0

(Writing of slave address value)

LDM #$F0, S1

CLI

(

Trigger of RESTART condition generating

)

(Interrupt enabled)

2. Select the slave receive mode when the PIN bit is “0”. Do not

write “1” to the PIN bit. Neither “0” nor “1” is specified for the

writing to the BB bit.

The TRX bit becomes “0” and the SDA pin is released.

3. The SCL pin is released by writing the slave address value to

2

the I C data shift register.

4. Disable interrupts during the following two process steps:

• Writing of slave address value

• Trigger of RESTART condition generating

45

MITSUBISHI MICROCOMPUTERS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

LPC INTERFACE

LPC interface function is base on Low Pin Count (LPC) Interface

Specification, Revision 1.0. The 3885 supports only I/O read cycle

and

I/O write cycle. There are two channels of bus buffers to the host.

The functions of Input Data Bus Buffer, Output Data Bus Buffer

and Data Bus Buffer Status Register are the same as that of the

8042, 3880 group, 3881 group and 3886 group. It can be written in

or read out from the host controller through LPC interface. LPC in-

terface function block diagram is shown in Figure 43.

Functional input or output pins of LPC interface are shared with

Port 8 (P80–P86). Setting the LPC interface enable bit (bit3 of

LPCCON) to “1” enables LPC interface. Enabling channel i (i = 0,

1) of the data bus buffer is controlled by the data bus buffer i (i =

0, 1) enable bits (bit 4 or bit 5 of LPCCON).

The slave addresses of the data bus buffer channel i (i = 0, 1) are

definable by setting LPCi (i = 0, 1) address register H/L

(LPC0ADL, LPC0ADH, LPC1ADL, LPC1ADH). The bit 2 value of

LPCi address register L is not decoded. This bit returns “0” when

the internal CPU read. The bit 2 of slave address is latched to

XA2i flag when the host controller writes the data.

The input buffer full (IBF) interrupt occurs when the host controller

writes the data. The output buffer empty (OBE) interrupt is gener-

ated when the host controller reads out the data. The 3885

merges two input buffer full (IBF) interrupt requests and two output

buffer empty (OBE) interrupt requests as shown in Figure 44.

Table 16 Function explanation of the control pin in LPC interface

Input/

Output

Function

Pin name

P8

0

1

2

3

/LAD

0

1

2

3

I/O

I

These pins communicate address, control and data

information between the host and the data bus buffer of

the 3885.

Input the signal to indicate the start of new cycle and

termination of abnormal communication cycles.

P8

4

/LFRAME

/LRESET

/LCLK

Input the signal to reset the LPC interface function.

P8

5

I

Input the LPC synchronous clock signal.

P8

6

I

46

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

P8

4

/

LFRAME

LRESET

P8 LCLK

P8

5

/

6/

P8

0/LAD0

P8

1/LAD1

Input Control Circuit

P8

2/LAD2

Input Data

Bus Buffer [7:4]

Bus Buffer [3:0]

Output Data

Bus Buffer [7:4]

Bus Buffer [3:0]

P8

3/LAD3

Data bus buffer status register

4i XA2i

U

7i

U

6i

U

5i

U

2i

IBFi OBFi

Output Control Circuit

Interrupt signal

IBF, OBE

Interrupt Generate

Circuit

0

b6

b5

b4

b3

b2

b1

b0

LPC control register (LPCCON)

Fig. 43 Block diagram of LPC interface function (1ch)

47

MITSUBISHI MICROCOMPUTERS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

One-shot pulse

generating circuit

Input buffer

full flag 0 IBF

Rising edge

detection circuit

0

1

Input buffer full interrupt

request signal IBF

One-shot pulse

generating circuit

Rising edge

detection circuit

Input buffer

full flag 1 IBF

Output buffer

full flag 0

One-shot pulse

generating circuit

Rising edge

detection circuit

OBF

0

1

OBE

0

Output buffer empty interrupt

request signal OBE

Output buffer

full flag 1

One-shot pulse

generating circuit

Rising edge

detection circuit

OBE

1

IBF

0

1

IBF

Interrupt request is set at this rising edge

OBF

OBE0)

0

(

OBF

OBE1)

1

(

OBE

Interrupt request is set at this rising edge

Fig. 44 Interrupt request circuit of data bus buffer

48

MITSUBISHI MICROCOMPUTERS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

[LPC Control Register (LPCCON)] 002A16

• SYNC output select bit (SYNCSEL)

“00”: OK

[Output Data Bus Buffer i (i = 0, 1)

(DBBOUT0, DBBOUT1)] 002816, 002B16

Writing data to data bus buffer registers (DBB0 , DBB1) address

from the internal CPU means writing to DBBOUTi (i = 0, 1). The

data of DBBOUTi (i = 1, 0) is read out from the host controller

when bit 2 of slave address (A2) is “0”.

“01”: LONG & OK

“10”: Err

“11”: LONG & Err

• LPC interface software reset bit (LPCSR)

“0”: Reset release (automatic)

“1”: Reset

[LPCi address register H/L

(LPC0ADL, LPC1ADL / LPC0ADH, LPC1ADH)]

0FF016 to 0FF316

• LPC interface enable bit (LPCBEN)

“0”: P80–P86 works as port

“1”: P80–P86 works as LPC interface

• Data bus buffer 0 enable bit (DBBEN0)

“0”: Data bus buffer 0 disable

“1”: Data bus buffer 0 enable

• Data bus buffer 1 enable bit (DBBEN1)

“0”: Data bus buffer 1 disable

“1”: Data bus buffer 1 enable

The slave addresses of data bus buffer channel i(i=0,1) are defin-

able by setting LPCi address registers H/L (LPC0ADL, LPC0ADH,

LPC1ADL, LPC1ADH ). These registers can be set and cleared

any time. When the internal CPU reads LPCi address register L,

the bit 2 (A2) is fixed to “0”. The bit 2 of slave address (A2) is

latched to XA2i flag when the host controller writes the data. The

slave addresses, set in these registers, is used for comparing with

the addresses from the host controller.

Bits 0 and 1 of the LPC control register (LPCCON) specify the

SYNC code output.

Bit 2 of the LPC control register (LPCCON) enables the LPC inter-

face to enter the reset state by software. When LPCSR is set to

“1”, LPC interface is initialized in the same manner as the external

“L” input to LRESET pin (See Figure 50). Writing “0” to LPCSR the

reset state will be released after 1.5 cycle of φ and this bit is

cleared to “0”.

[Data Bus Buffer Status Register i (i = 0, 1)

(DBBSTS0, DBBSTS1)] 002916, 002C16

Bits 0, 1 and 3 are read-only bits and indicate the status of the

data bus buffer. Bits 2, 4, 5, 6 and 7 are user definable flags which

can be read and written by software. The data bus buffer status

register can be read out by the host controller when bit 2 of the

slave address (A2) is “1”.

•Bit 0: Output buffer full flag i (OBFi)

This bit is set to “1” when a data is written into the output data bus

buffer i and cleared to “0” when the host controller reads out the

data from the output data bus buffer i.

•Bit 1: Input buffer full flag i (IBFi)

This bit is set to “1” when a data is written into the input data bus

buffer i by the host controller, and cleared to “0” when the data is

read out from the input data bus buffer i by the internal CPU.

•Bit 3: XA2 flag (XA2i)

The bit 2 of slave address is latched while a data is written into the

input data bus buffer i.

[Input Data Bus Buffer i(i=0,1)

(DBBIN0, DBBIN1)] 002816, 002B16

In I/O write cycle from the host controller, the data byte of the data

phase is latched to DBBINi (i=0,1). The data of DBBINi can be

read out form the data bus buffer registers (DBB0, DBB1) address

in SFR area.

49

MITSUBISHI MICROCOMPUTERS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

LPC control register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

LPCCON

Address

002A16

When reset

00000000

2

R

W

Bit symbol

SYNCSEL SYNC output select bit

Bit name

Function

00 : OK

01 : Long & OK

10 : Err

11 : Long & Err

0 : Reset release(automatic)

1 : Reset

LPC interface software reset bit

LPCSR

LPCEN

0 : P80 to P86 as port

1 : LPC interface enable

LPC interface enable bit

0 : Data bus buffer 0 disable

1 : Data bus buffer 0 enable

Data bus buffer 0 enable bit

DBBEN0

DBBEN1

0 : Data bus buffer 1 disable

1 : Data bus buffer 1 enable

Data bus buffer 1 enable bit

Cannot write to this bit.

Returns “0” when read.

Fig. 45 LPC control register

Data bus buffer status register i (i = 0, 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

DBBSTS0

DBBSTS1

Address

002916

002C16

When reset

00000000

2

00000000

2

R

W

Bit symbol

Bit name

Function

OBFi

IBFi

U2i

Output buffer full flag

Input buffer full flag

User definable flag

XA2i flag

0 : Buffer empty

1 : Buffer full

0 : Buffer empty

1 : Buffer full

This flag can be freely defined

by user.

This flag indicates the A2

status when IBFi flag is set.

XA2i

This flag can be freely defined

by user.

U4i

U5i

U6i

U7i

User definable flag

Fig. 46 Data bus buffer control register

50

MITSUBISHI MICROCOMPUTERS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

LPCi address register L (i=0,1) (Note2)

Symbol

LPC0ADL

LPC1ADL

Address

0FF02

0FF22

When reset

000000002

b7 b6 b5 b4 b3 b2 b1 b0

R

W

Bit symbol

LPCSAD0

Bit name

Slave address bit 0

LPCSAD1

LPCSAD2

LPCSAD3

LPCSAD4

LPCSAD5

LPCSAD6

LPCSAD7

Slave address bit 1

Slave address bit 2 (Note 1)

Slave address bit 3

Slave address bit 4

Slave address bit 5

Slave address bit 6

Slave address bit 7

Notes 1: Always returnes “0” when read , even if writing “1” to this bit.

2: Do not set the same 16-bit slave address to both channel 0 and channel 1.

LPCi address register H (i=0,1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

LPC0ADH

LPC1ADH

Address

0FF12

0FF32

When reset

000000002

R

W

Bit symbol

Bit name

Slave address bit 8

Slave address bit 9

Slave address bit 10

Slave address bit 11

Slave address bit 12

Slave address bit 13

Slave address bit 14

LPCSAD8

LPCSAD9

LPCSAD10

LPCSAD11

LPCSAD12

LPCSAD13

LPCSAD14

LPCSAD15

Slave address bit 15

Fig. 47 LPC related registers

51

MITSUBISHI MICROCOMPUTERS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Basic Operation of LPC Interface

Set up steps for LPC interface is as below.

(2) Example for I/O read cycle

The I/O read cycle timing is shown in Figure 49. The standard

transfer cycle number of I/O read cycle is 13. The data on LAD

[3:0] is monitored at every rising edge of LCLK. The communica-

tion starts from the falling edge of LFRAME.

•Set the LPC interface enable bit (bit3 of LPCCON) to “1”.

•Choose which data bus buffer channel use.

•Set the data bus buffer i enable bit (i = 0, 1) (bit 4 or 5 of

LPCCON) to “1”.

st

•1 clock: The last clock when LFRAME is “Low”. The host sends

•Set the slave address to LPCi address register L and H (i = 0, 1)

(LPC0ADL, LPC0ADH, LPC1ADL, LPC1ADH).

“00002” on LAD [3:0] for communication start.

nd

•2 clock: LFRAME is “High”. The host sends “000X2” on LAD

[3:0] to inform the cycle type as I/O read.

rd

(1) Example of I/O write cycle

• From 3 clock to 6th clock: In these four cycles , the host sends

The I/O write cycle timing is shown in Figure 48. The standard

transfer cycle number of I/O write cycle is 13. The communication

starts from the falling edge of LFRAME.

16-bit slave address. The 3885 compares it with the LPCi ad-

dress register H or L (i = 0, 1).

rd

3

4

5

6

clock: The slave address bit [15:12].

clock: The slave address bit [11:8].

clock: The slave address bit [7:4].

th

The data on LAD [3:0] is monitored at every rising edge of LCLK.

st

• 1 clock: The last clock when LFRAME is “Low”. The host send

“00002” on LAD [3:0] for communication start.

clock: The slave address bit [3:0].

nd

th

• 2 clock: LFRAME is “High”. The host send “001X2” on LAD

• 7 clock and 8 clock are used for turning the communication di-

[3:0] to inform the cycle type as I/O write.

rection from the host→the peripheral to the peripheral→the host.

rd

th

• From 3 clock to 6 clock : In these four cycles , the host sends

7

8

clock: The host outputs “11112” on LAD [3:0].

clock: The LAD [3:0] is set to tri-state by the host to

turn the communication direction.

th

16-bit slave address. The 3885 compares it with the LPCi ad-

dress register H and L (i = 0, 1).

rd

th

3

4

5

6

clock: The slave address bit [15:12].

clock: The slave address bit [11:8].

clock: The slave address bit [7:4].

• 9 clock: The 3885 outputs “00002” (SYNC OK) to LAD [3:0] for

th

acknowledgment.

th

• 10 clock and 11 clock are used for one data byte transfer from

the output data bus buffer i (DBBOUTi) or data bus buffer status

register i (DBBSTSi).

clock: The slave address bit [3:0].

th

• 7 clock and 8 clock are used for one data byte transfer. The

th

data is written to the input data bus buffer (DBBINi, i = 0, 1)

10 clock: The 3885 sends the data bit [3:0].

th

7

8

clock: The host sends the data bit [3:0].

11 clock: The 3885 sends the data bit [7:4].

th

clock: The host sends the data bit [7:4].

• 12 clock: The 3885 outputs “11112” to LAD [3:0]. In this timing

th

• 9 clock and 10 clock are for turning the communication direc-

OBFi (bit 2 of DBBSTSi) is cleared to “0” and OBE

tion from the host→the peripheral to the slave→the host.

interrupt signal is generated.

th

9

clock: The host outputs “11112” on LAD [3:0].

• 13 clock: The LAD [3:0] is set to tri-state by the host to turn the

th

10 clock: The LAD [3:0] is set to tri-state by the host to

turn the communication direction.

communication direction.

th

• 11 clock: The 3885 outputs “00002” (SYNC OK) to LAD [3:0] for

acknowledgment.

th

• 12 clock: The 3885 outputs “11112” to LAD [3:0]. In this timing

the address bit 2 is latched to XA2i (bit3 of DBBSTSi),

IBFi (bit 1 of DBBSTSi) is set to “1” and IBF interrupt

signal is generated.

th

• 13 clock: The LAD [3:0] is set to tri-state by the host to turn the

communication direction.

52

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

●

Data write (I/O write cycle)

CYCTYPE

+

START

ADDRESS

DATA

TAR

SYNC

TAR

DIR

LCLK

LFRAME

LAD [3:0]

(Note)

Input data bus buffer i

XA2i flag

IBFi flag

driven by the host

driven by the 3885

●

Command write (I/O write cycle)

CYCTYPE

START

ADDRESS

DATA

TAR

SYNC

TAR

+

DIR

LCLK

LFRAME

LAD [3:0]

(Note)

Input data bus buffer i

XA2i flag

IBFi flag

driven by the 3885

to LAD3 pins remain tri-state after transfer completion.

driven by the host

Note: LAD

0

Fig. 48 Data and command write timing

53

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

●

Data Read (I/O read cycle)

CYCTYPE

+

START

ADDRESS

TAR

SYNC

DATA

TAR

DIR

LCLK

LFRAME

LAD [3:0]

(Note 1)

Output data bus buffer i

OBFi flag

driven by the host

driven by the 3885

●

Status Read (I/O read cycle)

CYCTYPE

+

START

ADDRESS

TAR

SYNC

DATA

TAR

DIR

LCLK

LFRAME

LAD [3:0]

OBFi flag

(Note 1)

(Note 2)

driven by the host

driven by the the 3885

Notes 1: LAD

0 to LAD3 pins remain tri-state after transfer completion.

2: OBFi flag does not change.

Fig. 49 Data and status read timing

54

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

LPCSR write signal

LPCSR bit

(LPC interface software reset signal)

1.5 cycle of φ

LRESET

LPC interface reset signal

D

Q

CPU Data bus bit 2

LPCSR write signal

Q

D

Q

CK

R

CK

R

CPU RESET

φ

CPU RESET

Fig. 50 Reset timing and block

Table 17 Reset conditions of LPC interface function

Pin name / Internal register

P80/LAD0

LRESET = “L”

Tri-state

Note

P81/LAD1

P82/LAD2

P83/LAD3

P84/LFRAME

Input

P85/LRESET

LPC bus interface function

Input

P86/LCLK

Input data bus buffer registeri

Output data bus buffer registeri

Uxi flag 7, 6, 5, 4, 2

Keep same value before

LRESET goes “L”.

XA2i flag

IBFi flag

Initialization to “0”.

There is possibility to generate

IBF interrupt request.

OBFi flag

Initialization to “0”.

There is possibility to generate

OBE interrupt request.

LPCi address register

LPCCON

Keep same value before

LRESET goes “L”.

55

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

SERIALIZED INTERRUPT

The serialized IRQ circuit communicates the interrupt status to the

host controller based on the Serialized IRQ Support for PCI System,

Version 6.0.

Table 18 shows the summary of serialized interrupt of 3885.

Table 18 Smmary of serialized IRQ function

Item

Function

The factors of serialized IRQ

The numbers of serialized IRQ factor that can output simultaneously are 3.

• Channel 0 (IRQ1,IRQ2)

➀ Setting Software IRQi (i = 1, 12) request bit (bits 0, 1 of SERIRQ) to “1”.

➀ The “1” of OBF0 and Hardware IRQi ( i=1, 12) request bit (bits 3, 4 of SERCON) to “1”.

• Channel 1 (IRQx ; user selectable)

➀ Setting the IRQx request bit (bit 7 of SERIRQ) to “1”.

➀ The “1” of OBF1 and Hardware IRQx request bit to “1”.

• Channel 0 (IRQ1, IRQ12)

The number of frame

➀ Setting Software IRQ1 request bit (bit 0 of SERIRQ) to “1” or detecting “1” of OBF0 with

“1” of Hardware IRQ1 request bit (bit 4 of SERCON) selects IRQ1 Frame .

➀ Setting IRQ12 Software request bit (bit 1 of SERIRQ) to “1” or detecting “1” of OBF0 with

“1” of Hardware IRQ1 request bit (bit 4 of SERCON) selects IRQ12 Frame.

• Channel 1 (IRQx ; user selectable)

Setting IRQx frame select bit (bit 2-6 of SERIRQ) selects IRQ 1–15 frame or extend

frame 0–10.

Operation clock

Clock restart

Synchronized with LCLK (Max. 33 MHz).

LPC clock restart enable bit (bit 1 of SERCON) enables restart owing to “L” output of CLKRUN

with the interrupt when the LPC clock has stopped or slowed down.

Clock stop inhibition

LPC clock stop inhibition bit (bit 2 of SERCON) enables the inhibition of clock stop control

during the IRQSER cycle when the clock tends to stop or slow down.

56

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Internal data bus

Serialized IRQ control register

Serialized IRQ request register

b7 b6 b5 b4 b3 b2 b1 b0

Clock stop inhibition enable

and clock restart enable

Software Serialized IRQ request

OBF interrupt control

Serialized IRQ enable

Serialized interrupt request

control circuit

IRQx frame number

OBF0 – OBF1

Serialized

IRQ request

Frame number

SERIRQ

Serialized interrupt

control circuit

Clock restart request

and start frame

Clock operation

activate request

status and finish

acknowledgement

Clock monitor

control circuit

*

CLKRUN#

LCLK

LRESET#

CPU clock φ

Open Drain

*

Fig. 51 Block diagram of serialized interrupt

57

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Register Explanation

Bit 3 : Hardware IRQ1 request bit (SEIR1)

The serialized IRQ function is configured and controlled by the se-

rialized IRQ request register (SERIRQ) and the serialized IRQ

control register (SERCON).

When this bit is “1”, OBF0 status is directly connected to the IRQ1

frame.

Bit 4 : Hardware IRQ12 request bit (SEIR12 )

When this bit is “1”, OBF0 status is directly connected to IRQ12

frame.

[Serialized IRQ control register (SERCON)] 001D16

Bit 0 : Serialized IRQ enable bit (SIRQEN )

This bit enables/disables the serialized IRQ interface. When this

bit is “1”, use of serialized IRQ is enabled. Then P87 functions as

IRQ/Data line (SERIRQ) and P47 functions as CLKRUN.

Output structure of CLKRUN pin becomes N-channel open drain.

Bit 5 : Hardware IRQx request bit (SEIRx )

When this bit is “1”, OBF1 status is directly connected to the IRQx

frame.

Bit 1 : LPC clock restart enable bit (RUNEN )

Setting this bit to “1” enables clock restart with “L” output of

CLKRUN.

Bit 6 : IRQ1/IRQ12 disable bit (SCH0EN )

This bit controls whether the serialized IRQ channel 0 transfers

the IRQ1 and IRQ12 frame to the host or not.

Bit 2 : LPC clock stop inhibition bit (SUPEN )

Setting this bit to “1” makes CLKRUN output change to “L” for in-

hibiting the clock stop.

Bit 7 : IRQx output polarity bit (SCH1POL)

This bit selects IRx frame output level.

Serialized IRQ control register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

SERCON

Address

001D¹⁶

When reset

00000000

2

R

Bit symbol

SIRQEN

Bit name

Function

W

0 : Serialized IRQ disable

1 : Serialized IRQ enable

Serialized IRQ enable bit

LPC clock restart enable bit

LPC clock stop inhibition bit

0 : Clock restart disable

1 : Clock restart enable

RUNEN

SUPEN

0 : Stop inhibition control disable

1 : Stop inhibition control enable

0 : No IRQ1 request

Hardware IRQ1 request bit

SEIR1

1 : OBF

0 synchronized IRQ1 request

0 : No IRQ12 request

Hardware IRQ12 request bit

Hardware IRQx request bit

IRQ1/IRQ12 disable bit

IRQx output polarity bit

SEIR12

SEIRx

1 : OBF

0 : No IRQx request

1 : OBF synchronized IRQx request

0 synchronized IRQ12 request

1

0 : IRQ1/IRQ12 output enable

1 : IRQ1/IRQ12 output disable

SCH0EN

0 : -Request Hiz-Hiz-Hiz

-No request L-H-Hiz

SCH1POL

1 : -Request L-H-Hiz

-No request Hiz-Hiz-Hiz

Fig. 52 Configuration of serialized IRQ control register

58

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

[Serialized IRQ request register (SERIRQ)] 001F16

The interrupt source is definable by this register.

Bits 2-6 : IRQx frame select bits (ISi, i = 0–4)

These bits select the active IRQ frame of serial IRQ channel 1.

When these bit are “000002”, the serial IRQ channel 1 is disabled.

Bit 0 : Software IRQ1 request bit (IR1)

SERIRQ line shows IR1 value at the sample phase of IRQ1 frame,

when the SCH0EN is “1”.

Bit 7 : Software IRQx request bit (IRx)

SERIRQ line shows IRx value at the sample phase of IRQx frame

which is selected by bits 2 to 6 of SERIRQ. Output level is select-

able by the IRQx output polarity bit (SCH1POL).

Bit 1 : Software IRQ12 request bit (IR12)

SERIRQ line shows IR12 value at the sample phase of IRQ12

frame, when the SCH0EN is “1”.

Serialized IRQ request register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

SERIRQ

Address

001F16

When reset

000000002

R

W

Bit symbol

IR1

Bit name

Function

Software IRQ1

request bit

0: No IRQ1 request

1: IRQ1 request

Software IRQ12

request bit

0: No IRQ12 request

1: IRQ12 request

IR12

IS0

IRQx frame select bit

b6b5b4b3b2

0 0 0 0 0 : Disable serial IRQ channel 1

0 0 0 0 1 : IRQ1 Frame

0 0 0 1 0 : IRQ2 Frame

0 0 0 1 1 : IRQ3 Frame

0 0 1 0 0 : IRQ4 Frame

0 0 1 0 1 : IRQ5 Frame

0 0 1 1 0 : IRQ6 Frame

0 0 1 1 1 : IRQ7 Frame

0 1 0 0 0 : IRQ8 Frame

0 1 0 0 1 : IRQ9 Frame

0 1 0 1 0 : IRQ10 Frame

0 1 0 1 1 : IRQ11 Frame

0 1 1 0 0 : IRQ12 Frame

0 1 1 0 1 : IRQ13 Frame

0 1 1 1 0 : IRQ14 Frame

0 1 1 1 1 : IRQ15 Frame

1 0 0 0 0 : Do not select

1 0 0 0 1 : Do not select

1 0 0 1 0 : Do not select

1 0 0 1 1 : Do not select

1 0 1 0 0 : Do not select

1 0 1 0 1 : Extend Frame 0

1 0 1 1 0 : Extend Frame 1

1 0 1 1 1 : Extend Frame 2

1 1 0 0 0 : Extend Frame 3

1 1 0 0 1 : Extend Frame 4

1 1 0 1 0 : Extend Frame 5

1 1 0 1 1 : Extend Frame 6

1 1 1 0 0 : Extend Frame 7

1 1 1 0 1 : Extend Frame 8

1 1 1 1 0 : Extend Frame 9

1 1 1 1 1 : Extend Frame 10

IS1

IS2

IS3

IS4

IRx

0: No IRQx request

1: IRQx request

Software IRQx

request bit

Fig. 53 Structure of serialized IRQ request register

59

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Operation of Serialized IRQ

(2) IRQ/Data Frame

A cycle operation of serialized IRQ starts with Start Frame and fin-

ishes with Stop Frame. There are two modes of operation :

Continuous (Idle) mode and Quiet (Active) mode. The next opera-

tion mode is determined by monitoring the stop frame pulse width.

Each IRQ/Data Frame is three clocks. When the IRQi (i = 0, 1, x)

request is “0”, then the SERIRQ line is driven to “L” during the

st

Sample phase (1 clock) of the corresponding IRQ/Data frame,

nd

to “H” during the Recovery phase (2 clock), to tri-state during

rd

the Turn-around phase (3 clock). When the IRQi request is “1”,

➀Timing of serialized IRQ cycle

then the SERIRQ line is tri-state in all phases (3 clocks period).

Figure 54 shows the timing diagram of serialized IRQ cycle.

(3) Stop Frame

(1) Start Frame

The Stop Frame is detected when the SERIRQ line remains “L” in

2 or 3 clocks. The next operation mode is Quiet mode when the

pulse width of “L” is 2 clocks. The next operation mode is the

Continuous mode when the pulse width is 3 clocks.

The Start Frame is detected when the SERIRQ line remains “L” in

4 to 8 clocks.

Start frame

IRQ0 frame

IRQ1 frame

IRQ15 frame

IOCHK frame

Stop frame

Host control

To the next cycle

Clock

SERIRQ

Driver source

IRQ1

device

control

IRQ15

device

control

Host control

Fig. 54 Timing diagram of serialized IRQ cycle

60

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Operation Mode

Figure 55 shows the timing of continuous mode; Figure 56 shows

After receiving the start frame; the IRQ1 Frame, IRQ12 Frame or

IRQx frame is asserted.

that of Quiet mode.

Note : If the pulse width of “L” is less than 4 clocks, or 9 clocks or

more; the start frame is not detected and the next start (the

falling edge of SERIRQ) is waited.

(1) Continuous mode

Serialized IRQ cycles starts in Continuous mode after CPU reset

in the case of LRESET = “L” and the previous stop frame being 3

clocks.

Start frame (Note)

IRQ0 frame

IRQ1 frame

IRQ2 frame

IRQ3 frame

LCLK

SERIRQ line

Host SERIRQ output

3885 SERIRQ output

Drive source

Host

3885

Note: The start frame count is 4 clocks as exemple.

Fig. 55 Timing diagram of Continuous mode

(2) Quiet mode

Note: When the sum of pulse width of “L” driven by the 3885 in

st

At clock stop, clock slow down or the pulse width of the last stop

frame being 2 clocks, it is the Quiet mode.

the 1 clock and driven by the host in the rest clocks is

within 4 to 8-clock cycles, the start frame is detected.

If the sum of pulse width of “L” is less than 4 clocks, or 9

clocks or more; the start frame is not detected and the next

start (the falling edge of SERIRQ) is waited.

st

In this mode the 3885 drives the SERIRQ line to “L” in the 1

clock. After that the host drives the rest start frame (Note). The

IRQ1 frame, IRQ12 frame or IRQx frame is asserted.

Start frame (Note)

IRQ0 frame

IRQ1 frame

IRQ2 frame

IRQ3 fra

LCLK

SERIRQ line

Host SERIRQ output

3885 SERIRQ output

Drive source

3885

Host

Note: The start frame count is 4 clocks as exemple

Fig. 56 Timing diagram of Quiet mode

61

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Clock Restart/Stop Inhibition Request

Asserting the CLKRUN signal can request the host to restart for

clocks stopped or slowed down, or maintain the clock tending to

stop or slow down.

(1) Clock restart operation

In case the LPC clock restart enable bit (bit 1 of SERCON) is “1”

and the CLKRUN (BUS) is “H”, when the serialized interrupt re-

quest occurs, the 3885 drives CLKRUN to “L” for requesting the

PCI clock generator to restart the LCLK if the clock is slowed

down or stopped.

Figure 57 shows the timing diagram of clock restart request; Fig-

ure 58 shows an example of timing of clock stop inhibition

request.

LCLK

Bus CLKRUN

Central Resource CLKRUN

3885 CLKRUN

Restart frame

Start frame

Bus SERIRQ

Host SERIRQ

3885 SERIRQ

φ

Interrupt request

Internal restart

request signal

Fig. 57 Timing diagram of clock restart request

(2) Clock stop inhibition request

In case the LPC clock stop inhibition bit (bit 2 of SERCON) is “1”

and the serialized interrupt request is held, if the LCLK tends to

stop, the 3885 drives CLKRUN to “L” for requesting the PCI clock

generator not to stop LCLK.

LCLK

Bus CLKRUN

Central Resource CLKRUN

3885 CLKRUN

Inhibition

request

Bus SERIRQ

IRQSER cycle

Interrupt request

Internal inhibition request signal

Fig. 58 Timing diagram of clock stop inhibition request

62

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

A-D CONVERTER

[A-D Conversion Register 1,2 (AD1, AD2)]

003516, 003816

Channel Selector

The channel selector selects one of ports P60/AN0 to P67/AN7,

and inputs the voltage to the comparator.

The A-D conversion register is a read-only register that stores the

result of an A-D conversion. When reading this register during an

A-D conversion, the previous conversion result is read.

Bit 7 of the A-D conversion register 2 is the conversion mode se-

lection bit. When this bit is set to “0,” the A-D converter becomes

the 10-bit A-D mode. When this bit is set to “1,” that becomes the

8-bit A-D mode. The conversion result of the 8-bit A-D mode is

stored in the A-D conversion register 1. As for 10-bit A-D mode,

10-bit reading or 8-bit reading can be performed by selecting the

reading procedure of the A-D conversion register 1, 2 after A-D

conversion is completed (in Figure 60).

Comparator and Control Circuit

The comparator and control circuit compares an analog input volt-

age with the comparison voltage, and then stores the result in the

A-D conversion registers 1, 2. When an A-D conversion is com-

pleted, the control circuit sets the A-D conversion completion bit

and the A-D interrupt request bit to “1”.

Note that because the comparator consists of a capacitor cou-

pling, set f(XIN) to 500 kHz or more during an A-D conversion.

b7

b0

The A-D conversion register 1 performs the 8-bit reading inclined

to MSB after reset, the A-D conversion is started, or reading of the

A-D converter register 1 is generated; and the register becomes

the 8-bit reading inclined to LSB after the A-D converter register 2

is generated.

AD/DA control register

(ADCON : address 0034¹⁶)

Analog input pin selection bits

b2 b1 b0

0 0 0: P6⁰/AN0

0 0 1: P61/AN1

0 1 0: P6²/AN²

0 1 1: P63/AN3

1 0 0: P6⁴/AN⁴

1 0 1: P65/AN5

1 1 0: P66/AN6

1 1 1: P67/AN7

[AD/DA Control Register (ADCON)] 003416

The AD/DA control register controls the A-D conversion process.

Bits 0 to 2 select a specific analog input pin. Bit 3 signals the

completion of an A-D conversion. The value of this bit remains at

“0” during an A-D conversion, and changes to “1” when an A-D

conversion ends. Writing “0” to this bit starts the A-D conversion.

A-D conversion completion bit

0: Conversion in progress

1: Conversion completed

PWM0 output pin selection bit

0: P56/PWM01

Comparison Voltage Generator

1: P30/PWM00

The comparison voltage generator divides the voltage between

AVSS and VREF into 1024, and outputs the divided voltages in the

10-bit A-D mode (256 division in 8-bit A-D mode).

The A-D converter successively compares the comparison voltage

Vref in each mode, dividing the VREF (see below), with the input

voltage.

PWM1 output pin selection bit

0: P57/PWM11

1: P31/PWM10

DA1 output enable bit

0: DA1 output disabled

1: DA1 output enabled

DA2 output enable bit

0: DA2 output disabled

1: DA2 output enabled

• 10-bit A-D mode (10-bit reading)

VREF

Vref = n (n = 0–1023)

1024

Fig. 59 Structure of AD/DA control register

• 10-bit A-D mode (8-bit reading)

VREF

Vref = n (n = 0–255)

256

• 8-bit A-D mode

VREF

10-bit reading

(Read address 003816 before 003516)

Vref = (n–0.5) (n = 1–255)

256

b0

b7

=0

(n = 0)

(Address 003816)

(Address 003516)

b9 b8

0

b7

b0

b7 b6 b5 b4 b3 b2 b1 b0

Note: Bits 2 to 6 of address 003816 becomes “0”at reading.

8-bit reading (Read only address 003516)

b7

b0

(Address 003516)

b9 b8 b7 b6 b5 b4 b3 b2

Fig. 60 Structure of 10-bit A-D mode reading

63

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Data bus

b7

3

b0

AD/DA control register

(Address 003416

)

A-D interrupt request

A-D control circuit

P60/AN0

P61/AN1

(Address 003816

(Address 0035¹⁶

)

P6

2

/AN

2

3

A-D conversion register 2

A-D conversion register 1

Comparator

P63

/AN

P64

4

5

10

P65

P6

6

/AN

6

7

Resistor ladder

P67

/AN

V

REF AVSS

Fig. 61 Block diagram of A-D converter

64

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

D-A CONVERTER

The 3885 group has two internal D-A converters (DA1 and DA2)

with 8-bit resolution.

The D-A converter is performed by setting the value in each D-A

conversion register. The result of D-A conversion is output from

the DA1 or DA2 pin by setting the DA output enable bit to “1”.

When using the D-A converter, the corresponding port direction

register bit (P56 for DA1 or P57 for DA2) must be set to “0” (input

status).

D-A1 conversion register (8)

DA1

output enable bit

P5 /DA /PWM01

The output analog voltage V is determined by the value n (decimal

notation) in the D-A conversion register as follows:

R-2R resistor ladder

6

1

V = VREF ✕ n/256 (n = 0 to 255)

Where VREF is the reference voltage.

D-A2 conversion register (8)

DA

At reset, the D-A conversion registers are cleared to “0016”, the

DA output enable bits are cleared to “0”, and the P56/DA1/PWM01

and P57/DA2/PWM11 pins become high impedance.

2

output enable bit

P5 /DA /PWM11

R-2R resistor ladder

7

2

The DA output does not have buffers. Accordingly, connect an ex-

ternal buffer when driving a low-impedance load.

Fig. 62 Block diagram of D-A converter

DA1

output enable bit

R

“0”

R

2R

R

P56/DA1/PWM01

“1”

2R

MSB

LSB

D-A1 conversion register

“0”

“1”

AVSS

V

REF

Fig. 63 Equivalent connection circuit of D-A converter (DA1)

65

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

COMPARATOR CIRCUIT

data register (CMPD). After 14 cycles of the internal system clock

φ (the time required for the comparison), the comparison result is

stored in the comparator data register (CMPD).

Comparator Configuration

The comparator circuit consists of the ladder resistors, the analog

comparators, a comparator control circuit, the comparator refer-

ence input selection bit (bit 7 of PCTL2), a comparator data

register (CMPD), the comparator reference power source input pin

(P20/CMPREF) and analog input pins (P30–P37). The analog input

pin (P30–P37) also functions as an ordinary digital port.

If the analog input voltage is greater than the internal reference

voltage, each bit of this register is “1”; if it is less than the internal

reference voltage, each bit of this register is “0”. To perform an-

other comparison, the voltage comparison must be performed

again by writing to the comparator data register (CMPD).

Read the result when 14 cycles of φ or more have passed after the

comparator operation starts. The ladder resistor is turned on dur-

ing 14 cycles of φ , which is required for the comparison, and the

reference voltage is generated. An unnecessary current is not

consumed because the ladder resistor is turned off while the com-

parator operation is not performed. Since the comparator consists

of capacitor coupling, the electric charge may lost if the clock fre-

quency is low.

Comparator Operation

To activate the comparator circuit, first set port P3 to input mode

by setting the corresponding direction register (P3D) to “0” to use

port P3 as an analog voltage input pin. The internal fixed analog

voltage (VCC ✕✕29/32) can be generated by setting “1” to the com-

parator reference input selection bit (bit 7 of PCTL2). The internal

fixed analog voltage becomes about 2.99 V at VCC = 3.3 V. When

setting “0” to the comparator reference input selection bit, the P20/

CMPREF pin becomes the comparator reference power source in-

put pin and it is possible to input the comparator reference power

source optionally from the external. The voltage comparison is im-

mediately performed by the writing operation to the comparator

Keep the clock frequency more than 1 MHz during the comparator

operation. Do not execute the STP, WIT, or port P3 I/O instruction.

Data bus

8

Comparator data register

P3 (8)

b0

P37

Compar-

ator

P3

6

0

Compar-

ator

Comparator reference input selection bit

(bit 7 of PCTL2)

“0”

VCC

P3

Compar-

ator

“1”

V

CC✕29/32

Comparator

control circuit

Comparator connecting

signal

Ladder resistor

connecting signal

P20/CMPREF

V

SS

Fig. 64 Comparator circuit

66

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

RESET CIRCUIT

____________

To reset the microcomputer, RESET pin should be held at an “L”

level for 16 XIN cycle or more. (When the power source voltage

should be between 3.3V ± 0.3V and the oscillation should be

stable.) Then the R^___E^___S^__E^__T^__pin set to “H”, the reset state is released.

After the reset is completed, the program starts from the address

contained in address FFFD16 (high-order byte) and address

FFFC16 (low-order byte). Make sure that the reset input voltage is

less than 0.6 V for VCC of 3.0 V.

Poweron

(Note)

Power source

voltage

0V

RESET

VCC

Reset input

voltage

0V

0.2VCC

Note : Reset release voltage ; Vcc=3.0 V

RESET

V

CC

Power source

voltage detection

circuit

Fig. 65 Reset circuit example

XIN

φ

RESET

Internal

reset

Address

AD

H L

,

?

FFFC

FFFD

Reset address from the vector table.

Data

AD

H

?

AD

L

?

SYNC

XIN: 10.5 to 18.5 clock cycles

Notes

1: The frequency relation of f(XIN) and f(φ) is f(XIN)=8

• f(φ).

2: The question marks (?) indicate an undefined data that depends on the previous state.

Fig. 66 Reset sequence

67

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Address

Register contents

Address

(1)

Port P0 (P0)

0016

FF¹⁶

(38)Timer X (TX)

0000¹⁶

000116

000216

000316

000416

000516

000616

000716

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

001016

001116

001216

001316

001416

001516

001616

001716

001816

002516

002616

002716

002816

002916

002A16

002B16

002C16

002D16

002E16

002F16

003016

003116

003216

003316

003416

003516

003616

003716

003816

003916

003A16

003B16

003C16

003D16

003E16

003F16

0FF016

0FF116

0FF216

0FF316

0FF816

0FF916

0FFE16

(PS)

(2)

Port P0 direction register (P0D)

Port P1 (P1)

0016

FF16

(39)Prescaler Y (PREY)

(3)

0016

(40)Timer Y (TY)

(4)

Port P1 direction register (P1D)

Port P2 (P2)

0016

X X X X X X X X

00¹⁶

(41)Data bus buffer register 0 (DBB0)

(42)^{Data bus buffer status register 0 (DBBSTS0)}

(43)LPC control register (LPCCON)

(44)Data bus buffer register 1 (DBB1)

(45)^{Data bus buffer status register 1 (DBBSTS1)}

(46)Comparator data register (CMPD)

(47)Port control register 1 (PCTL1)

(48)Port control register 2 (PCTL2)

(49)PWM0H register (PWM0H)

(50)PWM0L register (PWM0L)

(51)PWM1H register (PWM1H)

(52)PWM1L register (PWM1L)

(53)AD/DA control register (ADCON)

(54)A-D conversion register 1 (AD1)

(55)D-A1 conversion register (DA1)

(56)D-A2 conversion register (DA2)

(57)A-D conversion register 2 (AD2)

(58)^{Interrupt source selection register (INTSEL)}

(59)^{Interrupt edge selection register (INTEDGE)}

(60)CPU mode register (CPUM)

(61)Interrupt request register 1 (IREQ1)

(62)Interrupt request register 2 (IREQ2)

(63)Interrupt control register 1 (ICON1)

(64)Interrupt control register 2 (ICON2)

(65)LPC0 address register L (LPC0ADL)

(66)LPC0 address register H (LPC0ADH)

(67)LPC1 address register L (LPC1ADL)

(68)LPC1 address register H (LPC1ADH)

(69)Port P5 input register (P5I)

(70)Port control register 3 (PCTL3)

(71)Flash memory control register (FMCR)

(72)Processor status register

(5)

0016

(6)

Port P2 direction register (P2D)

Port P3 (P3)

0016

(7)

X X X X X X X X

0016

(8)

Port P3 direction register (P3D)

Port P4 (P4)

0016

00¹⁶

0016

00¹⁶

0016

(9)

0016

(10)

(11)

(12)

(13)

(14)

(15)

(16)

(17)

(18)

(19)

(20)

(21)

(22)

(23)

(24)

(25)

(26)

(27)

(28)

(29)

(30)

(31)

(32)

(33)

(34)

(35)

(36)

(37)

Port P4 direction register (P4D)

Port P5 (P5)

0016

Port P5 direction register (P5D)

Port P6 (P6)

0016

X X X X X X X X

X 0 X X X X X X

0016

Port P6 direction register (P6D)

Port P7 (P7)

0016

X X X X X X X X

X 0 X X X X X X

0 0 0 0 1 0 0 0

0016

Port P7 direction register (P7D)

Port P8 (P8)

0016

X X X X X X X X

Port P8 direction register (P8D)

0016

00¹⁶

2

X X X X X X X X

00¹⁶

I C data shift register (S0)

0016

2

I C address register (S0D)

0 0 0 0 0 0 X X

2

I C status register (S1)

0 0 0 1 0 0 0 X

0016

00¹⁶

2

I C control register (S1D)

0016

2

I C clock control register (S2)

0016

0 1 0 0 1 0 0 0

2

0 0 0 1 1 0 1 0

X X X X X X X X

I

C start/stop condition control register (S2D)

0016

Transmit/Receive buffer register (TB/RB)

Serial I/O status register (SIOSTS)

Serial I/O control register (SIOCON)

UART control register (UARTCON)

Baud rate generator (BRG)

0019¹⁶1 0 0 0 0 0 0 0

00¹⁶

001A16

1 1 1 0 0 0 0 0

001B16

001C¹⁶X X X X X X X X

Serialized IRQ control register (SERCON)

Watchdog timer control register (WDTCON)

Serialized IRQ request register (SERIRQ)

Prescaler 12 (PRE12)

00¹⁶

001D16

0 0 1 1 1 1 1 1

001E16

X X X X X X X X

001F16

FF¹⁶

002016

Timer 1 (T1)

0116

002116

0 0

1

X X X

Timer 2 (T2)

FF16

002216

X X X X X

1

X X

Timer XY mode register (TM)

Prescaler X (PREX)

0016

(73)Program counter

002316

(PCH)

FFFD16 contents

FFFC¹⁶contents

FF16

002416

(PCL)

Note : X : Not fixed

Since the initial values for other than above mentioned registers and

RAM contents are indefinite at reset, they must be set.

Fig. 67 Internal status at reset

68

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

CLOCK GENERATING CIRCUIT

(2) Wait mode

The 3885 group has two built-in oscillation circuits. An oscillation

circuit can be formed by connecting a resonator between XIN and

XOUT (XCIN and XCOUT). Use the circuit constants in accordance

with the resonator manufacturer’s recommended values. No exter-

nal resistor is needed between XIN and XOUT since a feed-back

resistor exists on-chip. However, an external feed-back resistor is

needed between XCIN and XCOUT.

If the WIT instruction is executed, the internal clock φ stops at an

“H” level, but the oscillator does not stop. The internal clock φ re-

starts at reset or when an interrupt is received. Since the oscillator

does not stop, normal operation can be started immediately after

the clock is restarted.

Immediately after power on, only the XIN oscillation circuit starts

oscillating, and XCIN and XCOUT pins function as I/O ports.

Frequency Control

X

CIN

X

COUT

X

IN

XOUT

(1) Middle-speed mode

The internal clock φ is the frequency of XIN divided by 8. After re-

Rf

Rd

set, this mode is selected.

C

COUT

C

IN

COUT

CCIN

(2) High-speed mode

The internal clock φ is half the frequency of XIN.

Fig. 68 Ceramic resonator circuit

(3) Low-speed mode

The internal clock φ is half the frequency of XCIN.

✕Note

If you switch the mode between middle/high-speed and low-

speed, stabilize both XIN and XCIN oscillations. The sufficient time

is required for the sub clock to stabilize, especially immediately af-

ter power on and at returning from stop mode. When switching the

mode between middle/high-speed and low-speed, set the fre-

quency on condition that f(XIN) > 3f(XCIN).

X

CIN

X

COUT

X

IN

X

OUT

Open

External oscillation

circuit

External oscillation

circuit

(4) Low power dissipation mode

V

CC

V

CC

SS

The low power consumption operation can be realized by stopping

the main clock XIN in low-speed mode. To stop the main clock, set

bit 5 of the CPU mode register to “1”. When the main clock XIN is

restarted (by setting the main clock stop bit to “0”), set sufficient

time for oscillation to stabilize.

V

SS

V

Fig. 69 External clock input circuit

Oscillation Control

(1) Stop mode

If the STP instruction is executed, the internal clock φ stops at an

“H” level, and XIN and XCIN oscillators stop. When the oscillation

stabilizing time set after STP instruction released bit is “0,” the

prescaler 12 is set to “FF16” and timer 1 is set to “0116”. When the

oscillation stabilizing time set after STP instruction released bit is

“1”, set the sufficient time for oscillation of used oscillator to stabi-

lize since nothing is set to the prescaler 12 and timer 1.

Either XIN or XCIN divided by 16 is input to the prescaler 12 as

count source, and the output of the prescaler 12 is connected to

timer 1. Set the timer 1 interrupt enable bit to disabled (“0”) before

executing the STP instruction. Oscillator restarts when an external

interrupt is received, but the internal clock φ is not supplied to the

CPU (remains at “H”) until timer 1 underflows. The internal clock φ

is supplied for the first time, when timer 1 underflows. Therefore

make sure not to set the timer 1 interrupt request bit to “1” before

the STP instruction stops the oscillator. When the oscillator is re-

started by reset, apply “L” level to the RESET pin until the

oscillation is stable since a wait time will not be generated.

69

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

XCOUT

XCIN

“0”

Port X

switch bit

“1”

C

XOUT

XIN

Main clock division ratio

selection bits (Note 1)

Low-speed mode

1/2

Prescaler 12

FF16

Timer 1

0116

1/4

1/2

High-speed or

middle-speed

mode

Reset or

STP instruction

(Note 2)

Main clock division ratio

selection bits (Note1)

Middle-speed mode

Timing φ (internal clock)

High-speed or

low-speed mode

Main clock stop bit

Q

S

R

S Q

Q

S

R

STP instruction

WIT instruction

R

Reset

Interrupt disable flag l

Interrupt request

Notes 1: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.

When low-speed mode is selected, set port Xc switch bit (b4) to “1”.

2: f(X^IN)/16 is supplied as the count source to the Prescaler 12 at reset. When exciting STP instruction, the count source

does not change either f(X^IN))/16 or f(XCIN))/16 after releasing stop mode. Oscillation stabilizing time is not fixed “01FF16

when the bit 6 of PCTL2 is “1”.

”

Fig. 70 System clock generating circuit block diagram (Single-chip mode)

70

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Reset

Middle-speed mode

High-speed mode

(f(φ)=1 MHz)

(f(φ)=4 MHz)

CM6

CM

7

6

5

4

=0

“1”←→“0”

CM

7

6

5

4

=0

=1

=0(8 MHz oscillating)

=0(32 kHz stopped)

=0(8 MHz oscillating)

=0(32 kHz stopped)

C

M

“

”

0

4

0

”

“

←

C

M⁴

→

M

→

“

”

C

←

1

6

“

”

0

”

1

”

“

←

1

M⁶

“

→

C

←

“

”

0

1

”

“

High-speed mode

(f(φ)=4 MHz)

Middle-speed mode

(f(φ)=1 MHz)

CM6

“1”←→“0”

CM

7

=0

CM

7

6

5

4

=0

6

5

4

=1

CM

=0(8 MHz oscillating)

=1(32 kHz oscillating)

=0(8 MHz oscillating)

=1(32 kHz oscillating)

C

M

“

7

0

”

←

C

M

→

“

6

1

“

1

”

←

”

→

“

0

”

Low-speed mode

(f(φ)=16 kHz)

CM

7

=1

6

5

4

=0

=0(8 MHz oscillating)

=1(32 kHz oscillating)

b7

b4

CPU mode register

(CPUM : address 003B16

)

CM

4

5

7

: Port Xc switch bit

0 : I/O port function (stop oscillating)

1 : X^CIN-XCOUT oscillating function

: Main clock (XIN- XOUT) stop bit

0 : Operating

1 : Stopped

, CM

6: Main clock division ratio selection bit

Low-speed mode

(f(φ)=16 kHz)

b7 b6

0

1

0 : φ = f(XIN)/2 ( High-speed mode)

1 : φ = f(X^IN)/8 (Middle-speed mode)

0 : φ = f(X^CIN)/2 (Low-speed mode)

1 : Not available

CM

7

=1

=0

6

5

4

=1(8 MHz stopped)

=1(32 kHz oscillating)

Notes

1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)

2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is

ended.

3 : Timer operates in the wait mode.

4 : When the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 and Timer 1 in middle/high-speed mode.

5 : When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 and Timer 2 in low-speed mode.

6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed

mode.

7 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.

Fig. 71 State transitions of system clock

71

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FLASH MEMORY MODE

The flash memory of the 3885 is divided into User ROM area and

Boot ROM area as shown in Figure 72.

The 3885 (flash memory version) has an internal new DINOR

flash memory that can be reprogrammed with 2 power sources

when VCC is 3.3 V.

In addition to the ordinary user ROM area to store a microcom-

puter operation control program, 3885 program has a Boot ROM

area that is used to store a program to control reprogramming in

CPU reprogram mode. The user can store a reprogram control

software in this area that suits the user’s application system. This

Boot ROM area can be reprogrammed in only parallel I/O mode.

For this flash memory , two flash memory modes are available in

which to read, program, and erase: parallel I/O and a CPU repro-

gram mode in which the flash memory can be manipulated by the

Central Processing Unit (CPU). Each mode is detailed in the

pages to follow.

Parallel I/O mode

100016

Block 1 : 28 Kbyte

800016

F00016

4 Kbyte

FFFF16

Block 0 : 32Kbyte

FFFF16

User ROM area

Boot ROM area

BSEL = 0

BSEL = 1

CPU reprogram mode

100016

Block 1 : 28 Kbyte

800016

F00016

4 Kbyte

FFFF16

Block 0 : 32 Kbyte

Flash memory

start address

Product name

FFFF16

User ROM area

Boot ROM area

M38859FF

100016

User area / Boot area selection bit = 0

User area / Boot area selection bit = 1

Notes 1: The Boot ROM area can be rewritten in only parallel input/

output mode.

2: To specify a block, use the maximum address in the block.

Fig. 72 Block diagram of flash memory version

72

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Parallel I/O Mode

The parallel I/O mode is entered by making connections shown in

Bus Operation Modes

Read

_____

Figures 73 and then turning the Vcc power supply on.

The Read mode is entered by pulling the OE pin low when the CE

_____

pin is low and the WE and RP pins are high. There are two read

modes: array, and status register, which are selected by software

command input. In read mode, the data corresponding to each soft-

ware command entered is output from the data I/O pins D0–D7. The

read array mode is automatically selected when the device is pow-

ered on or after it exits deep power down mode.

Address

The user ROM is divided into two blocks as shown in Figure 72. The

block address referred to in this data sheet is the maximum address

value of each block.

User ROM and Boot ROM Areas

Output Disable

The output disable mode is entered by pulling the ^_C^__E^__pin low and the

In parallel I/O mode, the user ROM and boot ROM areas shown in Fig-

ure 72 can be rewritten. The BSEL pin is used to choose between these

two areas. The user ROM area is selected by pulling the BSEL input

low; the boot ROM area is selected by driving the BSEL input high. Both

areas of flash memory can be operated on in the same way.

Program and block erase operations can be performed in the user ROM

area. The user ROM area and its blocks are shown in Figure 72.

The user ROM area is 60 Kbytes in size. In parallel I/O mode, it is

located at addresses 100016 through FFFF16. The boot ROM area is

4 Kbytes in size. In parallel I/O mode, it is located at addresses

F00016 through FFFF16. Make sure program and block erase opera-

tions are always performed within this address range. (Access to any

location outside this address range is prohibited.)

_____ _____

WE, OE, and ^_R^__P^__pins high. Also, the data I/O pins are placed in the

high-impedance state.

Standby

The standby mode is entered by driving the ^_C^__E^__pin high when the RP

_____

pin is high. Also, the data I/O pins are placed in the high-impedance

_____

state. However, if the CE pin is set high during erase or program

operation, the internal control circuit does not halt immediately and

normal power consumption is required until the operation under way

is completed.

Write

_____

In the Boot ROM area, an erase block operation is applied to only

one 4 Kbyte block.

The write mode is entered by pulling the WE pin low when the CE pin

_____

is low and the OE and RP pins are high. In this mode, the device

accepts the software commands or write data entered from the data

I/O pins. A program, erase, or some other operation is initiated de-

pending on the content of the software command entered here. The

Functional Outline (Parallel I/O Mode)

In parallel I/O mode, bus operation modes—Read, Output Disable,

Standby, Write, and Deep Power Down—are selected by the status

input data such as address and software command is latched at the

_____ _____ _____

_____

rising edge of WE or ^_C^__E^__whichever occurs earlier.

of the CE, OE, WE, and RP input pins.

The contents of erase, program, and other operations are selected

by writing a software command. The data, status register, etc. in

memory can only be read out by a read after software command

input.

Deep Power Down

_____

The deep power down is entered by pulling the RP pin low. Also, the

data I/O pins are placed in the high-impedance state. When the de-

vice is freed from deep power down mode, the read array mode is

Program and erase operations are controlled using software com-

mands.

selected and the content of the status register is set to “8016.” If the

_____

The following explains about bus operation modes, software com-

mands, and status register.

RP pin is pulled low during erase or program operation, the opera-

tion under way is canceled and the data in the relevant block be-

comes invalid.

Table 19 Relationship between control signals and bus operation modes

_____

______

_____

Pin name

Mode

Read

CE

OE

WE

RP

D0 to D7

Data output

Array

VIL

VIH

VIL

X

VIL

VIH

X

VIH

X

VIH

VIL

Status register

Status register data output

Output disabled

Stand by

Hi-z

Program

Erase

VIH

X

VIL

X

Command/data input

Command input

Hi-z

Write

Other

Deep power down

Note : X can be VIL or VIH.

73

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Table 20 Description of Pin Function (Flash Memory Parallel I/O Mode)

Function

Apply 3.0 ± 0.3 V to the Vcc pin and 0 V to the Vss pin.

Pin name

CC,VSS

Signal name

I/O

V

I

Power supply input

Power suppy input

CNVSS

RESET

Connect to Vpp = 5V ± 0.5V.

Input “L” level.

Reset input

I

Connect a ceramic or crystal resonator between the XIN and XOUT pins.

When entering an externally derived clock, enter it from XIN and leave

X

IN

OUT

AVSS

REF

Clock input

I

X

Clock output

O

X

OUT open.

Analog power supply input

Reference voltage input

I

Connect to Vss.

V

P00 to P07

Address input A

0

8

to A

7

I

This is address A

0

–A

7

input pins.

These are address A –A15 input pins.

–D7 input/output pins.

P1

P2

0

to P1

to P2

7

Address input A

to A15

8

I/O These are data D

0

Data I/O D0 to D7

P3

0

1

2

Input P3

0

I

Input “H” or “L” or keep open.

This is a BSEL input pin.

BSEL input

Input P3

2

Input “H” or “L” or keep open.

P3

3

4

WE input

RP input

I

This is a WE input pin.

P3

This is a RP input pin.

This is a RY/BY output pin.

This is a CE input pin.

P3

5

6

O

I

RY/BY output

CE input

P3

7

OE input

I

This is a OE input pin.

P4

0

to P4

to P5

5

7

Input P4

0

to P4

5

Input “H” or “L” or keep open.

P4

6

7

Flash mode Input

I

Connect “L” for Pallarel I/O mode.

Input “H” or “L” or keep open.

P4

Input P4

Input P5

7

P5

0

P6

P7

0

to P6

to P7

7

Input P6

Input P7

I

Input “H” or “L” or keep open.

P8

0

to P8

7

Input P8

I

Input “H” or “L” or keep open.

74

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

40

BSEL

61

62

63

64

65

66

67

68

69

70

P1

P2

6

7

A14

A15

D0

D1

D2

D3

D4

D5

D6

D7

P3

1

/PWM10

/PWM00

39

38

37

36

35

34

33

32

31

30

29

28

/CMPREF

0

P8

7

/SERIRQ

P8 /LCLK

/LRESET#

/LFRAME#

1

6

2

P8

5

P2

3

4

P2

4(LED0)

P8

3

2

1

0

/LAD

3

2

1

0

5(LED

6(LED

7(LED

1)

2)

3)

M38859FFHP

Vss

Vcc

71

72

73

74

75

76

77

78

79

80

V

X

SS

OUT

IN

V

CC

REF

AVSS

V

*

27

26

25

24

23

22

21

P6

7

/AN

7

P4

RESET

CNVSS

P4

0

/XCOUT

/XCIN

6

1

5/AN

4/AN

3/AN

5

4

3

Vpp

2

/INT

/R

0

P4

3

1

P6

2

1

/AN

2

1

4

X

D

✽ :Connect to the ceramic oscillation circuit.

Mode setup method

indicates the flash memory pin.

Signal

Value

Vpp

CNVSS

P4

6

/SCLK

V

SS

RESET

Fig. 73 Pin connection diagram in parallel I/O mode

75

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Read Status Register Command (7016)

Software Commands

When the command code “7016” is written in the first bus cycle, the

content of the status register is output from the data I/O pins (D0–D7)

by a read in the second bus cycle. Since the content of the status

Table 21 lists the software commands. By entering a software com-

mand from the data I/O pins (D0–D7) in Write mode, specify the con-

tent of the operation, such as erase or program operation, to be per-

formed.

_____

register is updated at the falling edge of OE or CE, the OE or CE

signal must be asserted each time the status is read. The status

register is explained in the next section.

The following explains the content of each software command.

Read Array Command (FF16)

Clear Status Register Command (5016)

This command is used to clear the bits SR4,SR5 of the status regis-

ter after they have been set. These bits indicate that operation has

ended in an error. To use this command, write the command code

“5016” in the first bus cycle.

The read array mode is entered by writing the command code “FF16”

in the first bus cycle. When an address to be read is input in one of

the bus cycles that follow, the content of the specified address is

output from the data I/O pins (D0–D7).

The read array mode is retained intact until another command is writ-

ten.

The read array mode is also selected automatically when the device

is powered on and after it exits deep power down mode.

Table 21 Software command list (parallel I/O mode)

Second bus cycle

First bus cycle

Address

Command

Read array

Cycle number

Data

Mode

Read

Address

X

(D0 to D7)

1

2

1

2

Write

X(Note 4)

FF16

7016

5016

4016

2016

Read status register

Clear status register

Program

X

SRD(Note 1)

Write

WA(Note 2) WD(Note 2)

BA(Note 3) D016

Block erase

Notes 1: SRD = Status Register Data

2: WA = Write Address, WD = Write Data

3: BA = Block Address (Enter the maximum address of each block)

4: X denotes a given address in the user ROM area or boot ROM area.

76

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Program Command (4016)

Block Erase Command (2016/D016)

The program operation starts when the command code “4016” is writ-

ten in the first bus cycle. Then, if the address and data to program

are written in the 2nd bus cycle, program operation (data program-

ming and verification) will start.

By writing the command code “2016” in the first bus cycle and the

confirmation command code “D016” in the second bus cycle that

follows to the block address of a flash memory block, the system

initiates a block erase (erase and erase verify) operation.

Whether the write operation is completed can be confirmed by read-

ing the status register or the RY/^_B^__Y^__signal status. When the program

starts, the read status register mode is accessed automatically and

the content of the status register can be read out from the data bus

(D0–D7). The status register bit 7 (SR7) is set to “0” at the same time

the write operation starts and is returned to “1” upon completion of

the write operation. In this case, the read status register mode re-

Whether the block erase operation is completed can be confirmed

____

by reading the status register or the RY/BY signal. At the same time

the block erase operation starts, the read status register mode is

automatically entered, so the content of the status register can be

read out. The status register bit 7 (SR7) is set to “0” at the same time

the block erase operation starts and is returned to “1” upon comple-

tion of the block erase operation. In this case, the read status regis-

ter mode remains active until the read array command (FF16) is writ-

mains active until the read array command (FF16) is written.

____

The RY/BY pin is “L” during write operation and “H” when the write

operation is completed as is the status register bit 7.

At program end, program results can be checked by reading the sta-

tus register.

ten.

____

The RY/BY pin is “L” during block erase operation and “H” when the

block erase operation is completed as is the status register bit 7.

After the block erase operation is completed, the status register can

be read out to know the result of the block erase operation. For de-

tails, refer to the section where the status register is detailed.

Start

Write 4016

Write 2016

Write address

Write

D016

Write

Write data

Block address

Status register

read

Status register

read

SR7=1?

or

NO

SR7=1?

or

RY/BY=1?

YES

NO

Program

error

SR4=0?

Erase error

SR5=0?

YES

In this case, the read status

Program

register mode remains

completed

In this case, the read status

register mode remains active

until the read array command

(FF16) is written.

Erase completed

active until the read array

command (FF16) is written.

Fig. 74 Page program flowchart

Fig. 75 Block erase flowchart

77

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Status Register

Program Status (SR4)

The status register indicates status such as whether an erase opera-

tion or a program ended successfully or in error. It can be read under

the following conditions.

The program status reports the operating status of the write opera-

tion. If a write error occurs, it is set to “1”. When the program status is

cleared, it is set to “0”.

(1) In the read array mode when the read status register command

(7016) is written and the block address is subsequently read.

(2) In the period from when the program write or auto erase starts to

when the read array command (FF16)

If “1” is written for any of the SR5, SR4 bits, the program erase all

blocks, block erase, commands are not accepted. Before executing

these commands, execute the clear status register command (5016)

and clear the status register.

Also, any commands are not correct, both SR5 and SR4 are set to

“1”.

The status register is cleared in the following situations.

(1) By writing the clear status register command (5016)

(2) In the deep power down mode

Full Status Check

(3) In the power supply off state

Results from executed erase and program operations can be known

by running a full status check. Figure 76 shows a flowchart of the full

status check and explains how to remedy errors which occur.

Table 22 gives the definition of each status register bit. When power

is turned on or returning from the deep power down mode, the status

register outputs “8016”.

____

Ready/Busy (RY/BY) pin

____

The RY/BY pin is an output pin (N-chanel open drain output) which,

like the sequencer status (SR7), indicates the operating status of the

flash memory. It is “L” level during auto program or auto erase opera-

Sequencer status (SR7)

The sequencer status indicates the operating status of the flash

memory. When power is turned on or returning from the deep power

down mode, “1” is set for it. This bit is “0” (busy) during the write or

erase operations and becomes “1” when these operations ends.

tions and becomes to the high impedance state (ready state) when

____

these operations end. The RY/BY pin requires an external pull-up.

Erase Status (SR5)

The erase status reports the operating status of the erase operation.

If an erase error occurs, it is set to “1”. When the erase status is

cleared, it is set to “0”.

Table 22 Status register

Definition

Each bit of

SRD0 bits

Status name

“1”

“0”

SR7 (D7)

SR6 (D6)

SR5 (D5)

SR4 (D4)

SR3 (D3)

SR2 (D2)

SR1 (D1)

SR0 (D0)

Sequencer status

Reserved

Ready

Busy

-

Erase status

Program status

Reserved

Ended in error

Ended successfully

Ended in error

Ended successfully

-

Reserved

78

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Read status register

YES

Command

sequence error

Execute the clear status register command (5016

to clear the status register. Try performing the

)

SR4=1 and SR5

=1 ?

operation one more time after confirming that the

command is entered correctly.

NO

Should a block erase error occur, the block in error

cannot be used.

Block erase error

Program error

SR5=0?

YES

Should a program error occur, the block in error

cannot be used.

SR4=0?

YES

End (block erase, program)

Note: When one of SR5 to SR4 is set to “1” , none of the program, all blocks erase, or block erase

is accepted. Execute the clear status register command (50¹⁶) before executing these commands.

Fig. 76 Full status check flowchart and remedial procedure for errors

79

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CPU Reprogram Mode

trol software in RAM for write to bit 1. To set this bit to “1”, it is neces-

sary to write “0” and then write “1” in succession. The bit can be set

to “0” by only writing a “0”.

In CPU reprogram mode, the on-chip flash memory can be operated

on (read, program, or erase) under control of the Central Processing

Unit (CPU).

Bit 2 is the CPU reprogram mode entry flag. This bit can be read to

check whether the CPU reprogram mode has been entered or not.

Bit 3 is the flash memory reset bit used to reset the control circuit of

the internal flash memory. This bit is used when exiting CPU repro-

gram mode and when flash memory access has failed. When the

CPU reprogram mode select bit is “1”, writing “1” for this bit resets

the control circuit. To release the reset, it is necessary to set this bit

to “0”.

In CPU reprogram mode, only the user ROM area shown in Figure

72 can be reprogrammed; the Boot ROM area cannot be repro-

grammed. Make sure the program and block erase commands are

issued for only the user ROM area.

The control program for CPU reprogram mode can be stored in ei-

ther user ROM or Boot ROM area. In the CPU reprogram mode,

because the flash memory cannot be read from the CPU, the repro-

gram control software must be transferred to internal RAM area be-

fore it can be executed.

Bit 4 is the User area/Boot area selection bit. When this bit is set to

“1”, Boot ROM area is accessed, and CPU reprogram mode in Boot

ROM area is available. In boot mode, this bit is set “1” automatically.

To set and clear this bit must be operated in RAM area.

Figure 78 shows a flowchart for setting/releasing the CPU repro-

gram mode.

Microcomputer Mode and Boot Mode

The control software for CPU reprogram mode must be programed

into the user ROM or Boot ROM area in parallel I/O mode before-

hand. (If the control software is programed into the Boot ROM area,

the standard serial I/O mode becomes unusable.)

Notes on CPU Reprogram Mode

Described below are the precautions to be observed when repro-

gram the flash memory in CPU reprogram mode.

(1) Operation speed

See Figure 72 for details about the Boot ROM area.

Normal microcomputer mode is entered when the microcomputer is

released from reset with pulling CNVSS pin low. In this case, the

CPU starts operating using the control software in the user ROM

area.

During CPU reprogram mode, set the internal clock φ frequency

4MHz or less using the main clock division ratio selection bits (bit

6,7 at 003B16).

When the microcomputer is released from reset by pulling the P46/

SCLK pin high, the CNVSS pin high, the CPU starts operating using

the control software in the Boot ROM area (program start address

should be stored FFFC16, FFFD16). This mode is called the “boot

mode”.

(2) Instructions inhibited against use

The instructions which refer to the internal data of the flash

memory cannot be used during CPU reprogram mode .

(3) Interrupts inhibited against use

The interrupts cannot be used during CPU reprogram mode be-

cause they refer to the internal data of the flash memory.

(4) Watchdog timer

Block Address

Block addresses refer to the maximum address of each block. These

addresses are used in the block erase command. In case of the

M38859FF, these are two block.

In case of the watchdog timer has been running already, the in-

ternal reset generated by watchdog timer underflow does not

happen, because of watchdog timer is always clearing during

program or erase operation.

Outline Performance (CPU Reprogram Mode)

In the CPU reprogram mode, the CPU erases, programs and reads

the internal flash memory as instructed by software commands. This

reprogram control software must be transferred to internal RAM be-

fore it can be executed.

(5) Reset

Reset is always valid. In case of CNVSS = “H” when reset is re-

leased, boot mode is active. So the program starts from the ad-

dress contained in address FFFC16 and FFFD16 in boot ROM

area.

The CPU reprogram mode is accessed by applying 5V ± 10% to the

CNVSS pin and writing “1” for the CPU reprogram mode select bit (bit

1 in address 0FFE16). Software commands are accepted once the

mode is accessed.

Use software commands to control software and erase operations.

Whether a program or erase operation has terminated normally or in

error can be verified by reading the status register.

Figure 77 shows the flash memory control register.

Bit 0 is the RY/^_B^__Y^__status flag used exclusively to read the operating

status of the flash memory. During programming and erase opera-

tions, it is “0”. Otherwise, it is “1”.

Bit 1 is the CPU reprogram mode select bit. When this bit is set to “1”

and 5V ± 10% are applied to the CNVSS pin, the M38859FF enters

the CPU reprogram mode. Software commands are accepted once

the mode is accessed. In CPU reprogram mode, the CPU becomes

unable to access the internal flash memory. Therefore, use the con-

80

MITSUBISHI MICROCOMPUTERS

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b7

b0

Flash memory control register (address 0FFE16)

FMCR

RY/BY status flag (FMCR0)

0: Busy (being programmed or erased)

1: Ready

CPU reprogram mode select bit (FMCR1) (Note 2)

0: Normal mode (Software commands invalid)

1: CPU rewrite mode (Software commands acceptable)

CPU reprogram mode entry flag (FMCR2)

0: Normal mode

1: CPU rewrite mode

Flash memory reset bit (FMCR3) (Note 3)

0: Normal operation

1: Reset

User ROM area / Boot ROM area select bit (FMCR4) (Note 4)

0: User ROM area accessed

1: Boot ROM area accessed

Reserved bits (Indefinite at read/ “0” at write)

Notes 1: The contents of flash memory control register are “XXX00001” just after reset release.

2: For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession. If it is not

this procedure, this bit will not be set to ”1”. Additionally, it is required to ensure that no interrupt

will be generated during that interval.

Use the control program in the area except the built-in flash memory for write to this bit.

3: This bit is valid when the CPU rewrite mode select bit is “1”. Set this bit 3 to “0” subsequently after

setting bit 3 to “1”.

4: Use the control program in the area except the built-in flash memory for write to this bit.

Fig. 77 Flash memory control registers

Program in ROM

Program in RAM

*1

Start

Set CPU reprogram mode select bit to “1” (by

writing “0” and then “1” in succession)(Note 3)

Single-chip mode, or boot mode

Set CPU mode register (Note 1)

Check the CPU reprogram mode entry flag

Transfer CPU reprogram mode

control program to internal RAM

Using software command execute erase,

program, or other operation

Jump to transferred control program in RAM

(Subsequent operations are executed by control

program in this RAM)

Execute read array command or reset flash

memory by setting flash memory reset bit (by

writing “1” and then “0” in succession) (Note 2)

*1

Write “0” to CPU reprogram mode select bit

End

Notes 1: Set bit 6,7 (Main clock division ratio selection bits ) at CPU mode register (003B16).

2: Before exiting the CPU reprogram mode after completing erase or program operation, always be sure to

execute a read array command or reset the flash memory.

Fig. 78 CPU rewrite mode set/reset flowchart

81

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Software Commands

Table 23 lists the software commands.

Read Status Register Command (7016)

When the command code “7016” is written in the first bus cycle, the

content of the status register is read out at the data bus (D0–D7) by a

read in the second bus cycle.

After setting the CPU reprogram mode select bit to “1”, write a soft-

ware command to specify an erase or program operation.

The content of each software command is explained below.

The status register is explained in the next section.

Clear Status Register Command (5016)

Read Array Command (FF16)

This command is used to clear the bits SR1,SR4 and SR5 of the

status register after they have been set. These bits indicate that op-

eration has ended in an error. To use this command, write the com-

mand code “5016” in the first bus cycle.

The read array mode is entered by writing the command code “FF16”

in the first bus cycle. When an address to be read is input in next bus

cycles, the content of the specified address is read out at the data

bus (D0–D7).

The read array mode is retained intact until another command is writ-

ten. And after power on and after recover from deep power down

mode, this mode is selected also.

Table 23 List of software commands (CPU rewrite mode)

First bus cycle

Address

Second bus cycle

Mode Address

Command

Cycle number

Data

(D to D

Data

to D7)

Mode

0

7

)

(D0

(Note 4)

Read array

1

2

1

2

Write

X

FF16

7016

5016

4016

2016

Read status register

Clear status register

Program

X

Read

X

SRD ^{(Note 1)}

(Note 2)

Write

WD

WA

BA ^{(Note 3)}

Block erase

D016

Note 1: SRD = Status Register Data

2: WA = Write Address, WD = Write Data

3: BA = Block Address (Enter the maximum address of each block.)

4: X denotes a given address in the user ROM area .

82

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Program Command (4016)

Block Erase Command (2016/D016)

Program operation starts when the command code “4016” is written

in the first bus cycle. Then, if the address and data to program are

written in the 2nd bus cycle, program operation (data programming

and verification) will start.

By writing the command code “2016” in the first bus cycle and the

confirmation command code “D016” in the second bus cycle that

follows to the block address of a flash memory block, the system

initiates a block erase (erase and erase verify) operation.

Whether the program operation is completed can be confirmed by

reading the status register or the RY/B^___Y^__status flag. When the pro-

gram starts, the read status register mode is accessed automatically

and the content of the status register is read into the data bus (D0–

D7). The status register bit 7 (SR7) is set to “0” at the same time the

program operation starts and is returned to “1” upon completion of

the program operation. In this case, the read status register mode

Whether the block erase operation is completed can be confirmed

____

by reading the status register or the RY/BY status flag. At the same

time the block erase operation starts, the read status register mode

is automatically entered, so the content of the status register can be

read out. The status register bit 7 (SR7) is set to “0” at the same time

the block erase operation starts and is returned to “1” upon comple-

tion of the block erase operation. In this case, the read status regis-

ter mode remains active until the read array command (FF16) is writ-

remains active until the read array command (FF16) is written.

____

The RY/BY status flag is “0” during program operation and “1” when

the program operation is completed as is the status register bit 7.

At program end, program results can be checked by reading the sta-

tus register.

ten.

____

The RY/BY status flag is “0” during block erase operation and “1”

when the block erase operation is completed as is the status register

bit 7.

After the block erase operation is completed, the status register can

be read out to know the result of the block erase operation. For de-

tails, refer to the section where the status register is detailed.

Start

Write 4016

Write 2016

Program address

Write

D016

Block address

Write

Program data

Status register

read

Status register

read

SR7=1?

or

RY/BY=1?

NO

SR7=1?

or

RY/BY=1?

YES

NO

Program

SR4=0?

SR5=0?

Erase error

error

YES

Program

completed

Erase completed

Fig. 79 Program flowchart

Fig. 80 Erase flowchart

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Status Register

Sequencer status (SR7)

After power-on, and after recover from deep power down mode, the

The status register shows the operating state of the flash memory

and whether erase operations and programs ended successfully or

in error. It can be read in the following ways.

sequencer status is set to “1”(ready).

The sequencer status indicates the operating status of the device.

This status bit is set to “0” (busy) during program or erase operation

and is set to “1” upon completion of these operations.

(1) By reading an arbitrary address from the user ROM area after

writing the read status register command (7016)

(2) By reading an arbitrary address from the user ROM area in the

period from when the program starts or erase operation starts to

when the read array command (FF16) is input

Erase status (SR5)

The erase status informs the operating status of erase operation to

the CPU. When an erase error occurs, it is set to “1”.

The erase status is reset to “0” when cleared.

Table 24 shows the status register.

Also, the status register can be cleared in the following way.

(1) By writing the clear status register command (5016)

(2) In the deep power down mode

Program status (SR4)

The program status informs the operating status of write operation to

the CPU. When a write error occurs, it is set to “1”.

The program status is reset to “0” when cleared.

(3) In the power supply off state

After a reset, the status register is set to “8016”.

Each bit in this register is explained below.

If “1” is set for any of the SR5 or SR4 bits, the program, erase all

blocks, and block erase commands are not accepted. Before ex-

ecuting these commands, execute the clear status register com-

mand (5016) and clear the status register.

Also, any commands are not correct, both SR5 and SR4 are set to

“1”.

Table 24 Definition of each bit in status register

Definition

Each bit of

SRD0 bits

Status name

“1”

“0”

SR7 (bit7)

SR6 (bit6)

SR5 (bit5)

SR4 (bit4)

SR3 (bit3)

SR2 (bit2)

SR1 (bit1)

SR0 (bit0)

Sequencer status

Reserved

Ready

Busy

-

Erase status

Program status

Reserved

Terminated in error

Terminated normally

Terminated in error

Terminated normally

-

Reserved

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Full Status Check

By performing full status check, it is possible to know the execution

results of erase and program operations. Figure 81 shows a full sta-

tus check flowchart and the action to be taken when each error oc-

curs.

Read status register

YES

Command

sequence error

Execute the clear status register command (5016

to clear the status register. Try performing the

)

SR4=1 and SR5

=1 ?

operation one more time after confirming that the

command is entered correctly.

NO

Should a block erase error occur, the block in error

cannot be used.

Block erase error

Program error

SR5=0?

YES

SR4=0?

YES

NO

Should a program error occur, the block in error

cannot be used.

End (block erase, program)

Note: When one of SR5 to SR4 is set to “1” , none of the program, erase all blocks,

and block erase commands is accepted. Execute the clear status register

command (50¹⁶) before executing these commands.

Fig. 81 Full status check flowchart and remedial procedure for errors

85

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protect is turned on, so that the contents of the flash memory data

are protected against readout and reprogram. ROM code protect is

implemented in two levels. If level 2 is selected, the flash memory is

protected even against readout by a manufactures inspection test

also. When an attempt is made to select both level 1 and level 2,

level 2 is selected by default.

Functions To Inhibit Rewriting Flash Memory

To prevent the contents of the flash memory data from being read

out or rewritten easily, the device incorporates a ROM code protect

function for use in parallel I/O mode.

ROM code protect function

If both of the two ROM code protect reset bits are set to “00”, ROM

code protect is turned off, so that the contents of the flash memory

data can be read out or reprogram. Once ROM code protect is

turned on, the contents of the ROM code protect reset bits cannot

be modified in parallel I/O mode. Use CPU reprogram mode to re-

program the contents of the ROM code protect reset bits.

The ROM code protect function is the function inhibit reading out or

modifying the contents of the flash memory version by using the

ROM code protect control address (FFDB16) during parallel I/O

mode. Figure 82 shows the ROM code protect control address

(FFDB16). (This address exists in the user ROM area.)

If one of the pair of ROM code protect bits is set to “0”, ROM code

b7

b0

ROM code protect control (address FFDB16) (Note 1)

ROMCP

1 1

Reserved bits (“1” at read/write)

ROM code protect level 2 set bits (ROMCP2) (Notes 2, 3)

b3b2

0 0: Protect enabled

0 1: Protect enabled

1 0: Protect enabled

1 1: Protect disabled

ROM code protect reset bits (ROMCR) (Note 4)

b5b4

0 0: Protect removed

0 1: Protect set bits effective

1 0: Protect set bits effective

1 1: Protect set bits effective

ROM code protect level 1 set bits (ROMCP1) (Note 2)

b7b6

0 0: Protect enabled

0 1: Protect enabled

1 0: Protect enabled

1 1: Protect disabled

Notes 1: The contents of ROM code protect control register are “FF16” just after reset

release. This area is on the ROM in the mask ROM version.

2: When ROM code protect is turned on, the internal flash memory is protected

against readout or modification in parallel I/O mode.

3: When ROM code protect level 2 is turned on, ROM code readout by a shipment

inspection LSI tester, etc. also is inhibited.

4: The ROM code protect reset bits can be used to turn off ROM code protect level 1

and ROM code protect level 2. However, since these bits cannot be modified in

parallel I/O mode, they need to be rewritten in standard serial I/O mode or CPU

rewrite mode.

Fig. 82 ROM code protect control address

86

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Flash Memory Electrical Characteristics

Table 25 Flash memory mode Electrical characteristics

(Ta = 25^oC, Vcc = 3.3 ± 0.3V unless otherwise noted)

Limits

Typ.

Symbol

Parameter

Unit

Test conditions

Min.

Max.

100

60

IPP1

IPP2

IPP3

VIL

VPP power source current (read)

VPP power source current (program)

VPP power source current (erase)

“L” input voltage (Note)

µA

mA

V

30

0

0.8

VCC

5.5

VIH

“H” input voltage (Note)

2.0

4.5

V

VPP

VPP power source voltage

V

Note: Input pins for parallel I/O mode.

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NOTES ON PROGRAMMING

Serial I/O

In clock synchronous serial I/O, if the receive side is using an ex-

ternal clock and it is to output the SRDY signal, set the transmit

enable bit, the receive enable bit, and the SRDY output enable bit

to “1”.

Processor Status Register

The contents of the processor status register (PS) after a reset are

undefined, except for the interrupt disable flag (I) which is “1”. Af-

ter a reset, initialize flags which affect program execution. In

particular, it is essential to initialize the index X mode (T) and the

decimal mode (D) flags because of their effect on calculations.

Serial I/O continues to output the final bit from the TXD pin after

transmission is completed.

In clock-synchronous mode, an external clock is used as synchro-

nous clock, write transmission data to the transmit buffer register

during transfer clock is “H”.

Interrupts

The contents of the interrupt request bits do not change immedi-

ately after they have been written. After writing to an interrupt

request register, execute at least one instruction before perform-

ing a BBC or BBS instruction.

A-D Converter

The comparator uses capacitive coupling amplifier whose charge

will be lost if the clock frequency is too low.

Therefore, make sure that f(XIN) is at least on 500 kHz during an

A-D conversion.

Decimal Calculations

• To calculate in decimal notation, set the decimal mode flag (D)

to “1”, then execute an ADC or SBC instruction. After executing

an ADC or SBC instruction, execute at least one instruction be-

fore executing a SEC, CLC, or CLD instruction.

Do not execute the STP or WIT instruction during an A-D conver-

sion.

D-A Converter

When a D-A converter is not used, set all values of D-Ai conver-

• In decimal mode, the values of the negative (N), overflow (V),

and zero (Z) flags are invalid.

sion registers (i=1, 2) to “0016”.

Timers

Instruction Execution Time

If a value n (between 0 and 255) is written to a timer latch, the fre-

The instruction execution time is obtained by multiplying the pe-

riod of the internal clock φ by the number of cycles needed to

execute an instruction.

quency division ratio is 1/(n+1).

Multiplication and Division Instructions

• The index X mode (T) and the decimal mode (D) flags do not af-

fect the MUL and DIV instruction.

The number of cycles required to execute an instruction is shown

in the list of machine instructions.

The period of the internal clock φ is twice of the XIN period in high-

speed mode.

• The execution of these instructions does not change the con-

tents of the processor status register.

Ports

The contents of the port direction registers cannot be read. The

following cannot be used:

• The data transfer instruction (LDA, etc.)

• The operation instruction when the index X mode flag (T) is “1”

• The instruction with the addressing mode which uses the value

of a direction register as an index

• The bit-test instruction (BBC or BBS, etc.) to a direction register

• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to

a direction register.

Use instructions such as LDM and STA, etc., to set the port direc-

tion registers.

88

MITSUBISHI MICROCOMPUTERS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

NOTES ON USAGE

Handling of Power Source Pins

In order to avoid a latch-up occurrence, connect a capacitor suit-

able for high frequencies as bypass capacitor between power

source pin (VCC pin) and GND pin (VSS pin), between power

source pin (VCC pin) and analog power source input pin (AVSS

pin), and between program power source pin (CNVss/VPP) and

GND pin for flash memory version when on-board reprogramming

is executed. Besides, connect the capacitor to as close as pos-

sible. For bypass capacitor which should not be located too far

from the pins to be connected, a ceramic capacitor of 0.01 µF–0.1 µF

is recommended.

Flash Memory Version

The CNVSS pin is connected to the internal memory circuit block

by a low-ohmic resistance, since it has the multiplexed function to

be a programmable power source pin (VPP pin) as well.

To improve the noise reduction, connect a track between CNVSS

pin and VSS pin with 1 to 10 kΩ resistance.

For the mask ROM version, there is no operational interference

even if CNVSS pin is connected to Vss pin via a resistor.

Electric Characteristic Differences Between

Mask ROM and Flash Memory Version MCUs

There are differences in electric characteristics, operation margin,

noise immunity, and noise radiation between Mask ROM and

Flash Memory version MCUs due to the difference in the manufac-

turing processes.

When manufacturing an application system with the Flash

Memory version and then switching to use of the Mask ROM ver-

sion, please perform sufficient evaluations for the commercial

samples of the Mask ROM version.

DATA REQUIRED FOR MASK ORDERS

The following are necessary when ordering a mask ROM produc-

tion:

1. Mask ROM Order Confirmation Form

2. Mark Specification Form

3. Data to be written to ROM, in EPROM form (three identical cop-

ies) or one floppy disk.

For the mask ROM confirmation and the mark specifications, refer

to the “Mitsubishi MCU Technical Information” Homepage:

http://www.infomicom.maec.co.jp/indexe.htm

89

MITSUBISHI MICROCOMPUTERS

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ELECTRICAL CHARACTERISTICS

Table 26 Absolute maximum ratings

Symbol

Parameter

Power source voltages

Conditions

Ratings

Unit

V

VCC

–0.3 to 4.6

Input voltage P00–P07, P10–P17, P20–P27,

P30–P37, P40–P47, P50–P57,

P60–P67, P80–P87, VREF

VI

–0.3 to VCC +0.3

V

RESET, XIN

VI

Input voltage P70–P77

–0.3 to 5.8

–0.3 to 6.5

V

All voltages are based on VSS.

Output transistors are cut off.

Input voltage CNVSS (Note 1)

Input voltage CNVSS (Note 2)

–0.3 to VCC +0.3

Output voltage P00–P07, P10–P17, P20–P27,

P30–P37, P40–P47, P50–P57,

VO

–0.3 to VCC +0.3

V

P60–P67, P80–P87, XOUT

VO

Output voltage P70–P77

Power dissipation

–0.3 to 5.8

500

V

mW

°C

Pd

Ta = 25 °C

Topr

Tstg

Operating temperature

Storage temperature

–20 to 85

–40 to 125

°C

Notes 1: Flash memory version

2: Mask ROM version

Table 27 Recommended operating conditions

(VCC = 3.3 V ± 0.3V, Ta = –20 to 85 °C, unless otherwise noted)

Limits

Symbol

Parameter

Unit

Min.

Typ.

3.3

Max.

VCC

Power source voltage

Analog reference voltage

3.0

3.6

V

VSS

0

VREF

when A-D converter is used

when D-A converter is used

2.0

2.7

VCC

AVSS

VIA

Analog power source voltage

A-D converter input voltage

“H” input voltage

V

AN0–AN7

AVSS

VCC

VIH

P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

P50–P57, P60–P67, P80–P87, RESET, CNVSS

0.8VCC

VIH

“H” input voltage

P70–P77

0.8VCC

2.0

5.5

V

“H” input voltage (when TTL input level is selected)

P70–P75

2

VIH

“H” input voltage (when I C-BUS input level is selected)

0.7VCC

1.4

5.5

V

SDA, SCL

“H” input voltage (when SMBUS input level is selected)

SDA, SCL

VIH

VIL

“H” input voltage

“L” input voltage

XIN, XCIN

0.8VCC

0

VCC

V

P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

P50–P57, P60–P67, P70–P77, P80–P87, RESET,

CNVSS

0.2VCC

VIL

“L” input voltage (when TTL input level is selected)

P70–P75

0

0.8

0.3VCC

0.6

V

2

“L” input voltage (when I C-BUS input level is selected)

SDA, SCL

“L” input voltage (when SMBUS input level is selected)

SDA, SCL

“L” input voltage

XIN, XCIN

0.16VCC

90

MITSUBISHI MICROCOMPUTERS

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Table 28 Recommended operating conditions

(VCC = 3.3 V ± 0.3V, Ta = –20 to 85 °C, unless otherwise noted)

Limits

Unit

Symbol

Parameter

–P0 , P1 –P1

Min.

Typ.

Max.

–80

80

“H” total peak output current

“L” total peak output current

P0

P40–P47, P50–P57, P60–P67

P0 –P0 , P1 –P1 , P2 –P2 , P3

P24–P27

P40–P47,P50–P57, P60–P67, P70–P77

0

7

0

7

, P2

0

–P2

3

, P3

0

–P3

7

, P8

0

–P8

7

mA

ΣIOH(peak)

ΣIOL(peak)

ΣIOH(avg)

ΣIOL(avg)

0

7

0

7

0

3

0

–P3

7

, P8

80

“H” total average output current P0

“H” total average output current P40–P47,P50–P57, P60–P67

“L” total average output current P0 –P0 , P1 –P1 , P2 –P2 , P3

“L” total average output current P24–P27

“L” total average output current P40–P47,P50–P57, P60–P67, P70–P77

0

–P0

7

, P1

0

–P1

7

, P2

0

–P2

7

, P3

0

–P3

7

, P8

0

–P8

7

–40

40

0

7

0

7

0

3

0

–P3

7

, P8

40

Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured

over 100 ms. The total peak current is the peak value of all the currents.

Table 29 Recommended operating conditions

(VCC = 3.3 V ± 0.3V, Ta = –20 to 85 °C, unless otherwise noted)

Limits

Symbol

Parameter

Unit

mA

Min.

Typ.

Max.

–10

IOH(peak)

“H” peak output current

“L” peak output current

P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

P50–P57, P60–P67, P80–P87 (Note 1)

IOL(peak)

P00–P07, P10–P17, P20–P23, P30–P37, P40–P47,

10

mA

P50–P57, P60–P67, P70–P77, P80–P87 (Note 1)

IOL(peak)

IOH(avg)

“L” peak output current

P24–P27 (Note 1)

20

–5

mA

“H” average output current

P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,

P50–P57, P60–P67, P80–P87 (Note 2)

IOL(avg)

“L” average output current

“L” peak output current

P00–P07, P10–P17, P20–P23, P30–P37, P40–P47,

P50–P57, P60–P67, P70–P77, P80–P87 (Note 2)

5

mA

P24–P27 (Note 2)

15

8

mA

MHz

kHz

f(XIN)

Main clock input oscillation frequency (Note 3)

Sub-clock input oscillation frequency (Notes 3, 4)

f(XCIN)

32.768

50

Notes 1: The peak output current is the peak current flowing in each port.

2: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms.

3: When the oscillation frequency has a duty cycle of 50%.

4: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.

91

MITSUBISHI MICROCOMPUTERS

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Table 30 Electrical characteristics

(VCC = 3.3 V ± 0.3V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Limits

Symbol

Parameter

“H” output voltage

Unit

Test conditions

Min.

Typ.

Max.

VOH

VOL

P00–P07, P10–P17, P20–P27

P30–P37, P40–P47, P50–P57

P60–P67, P80–P87 (Note)

IOH = –5 mA

VCC–1.0

V

“L” output voltage

IOL = 5 mA

1.0

0.4

V

P00–P07, P10–P17, P20–P27

P30–P37, P40–P47, P50–P57

P60–P67, P70–P77, P80–P87

IOL = 1.6 mA

Hysteresis

CNTR0, CNTR1, INT0, INT1

INT20–INT40, INT21–INT41, INT5

P30–P37, RxD, SCLK, LRESET

LFRAME, LCLK, SERIRQ

VT+–VT–

0.4

V

“H” input current

P00–P07, P10–P17, P20–P27

P30–P37, P40–P47, P50–P57

P60–P67, P70–P77, P80–P87

RESET, CNVSS

VI = VCC

(Pin floating.

Pull-up transistors “off”)

5.0

IIH

IIL

µA

“H” input current XIN

VI = VCC

3

“L” input current

P00–P07, P10–P17, P20–P27

P30–P37, P40–P47, P50–P57

P60–P67, P70–P77, P80–P87

RESET,CNVSS

VI = VSS

(Pin floating.

Pull-up transistors “off”)

–5.0

IIL

“L” input current

P30–P37 (at Pull-up)

XIN

VI = VSS

–3

–100

3.6

µA

–13

2.0

–50

VRAM

RAM hold voltage

When clock stopped

V

Note: P00–P03 are measured when the P00–P03 output structure selection bit (bit 0 of PCTL1) is “0”.

P04–P07 are measured when the P04–P07 output structure selection bit (bit 1 of PCTL1) is “0”.

P10–P13 are measured when the P10–P13 output structure selection bit (bit 2 of PCTL1) is “0”.

P14–P17 are measured when the P14–P17 output structure selection bit (bit 3 of PCTL1) is “0”.

P42, P43, P44, and P46 are measured when the P4 output structure selection bit (bit 2 of PCTL2) is “0”.

P45 is measured when the P45/TXD P-channel output disable bit (bit 4 of UARTCON) is “0”.

92

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Table 31 Electrical characteristics

(VCC = 3.3 V ± 0.3V, VSS = 0 V, Ta = –20 to 85 °C, Mask ROM version unless otherwise noted)

Limits

Typ.

Symbol

Parameter

Test conditions

High-speed mode

f(XIN) = 8 MHz

f(XCIN) = 32.768 kHz

Output transistors “off”

Unit

mA

Min.

Max.

7

2.5

0.8

1.5

0.6

15

High-speed mode

f(XIN) = 8 MHz (in WIT state)

f(XCIN) = 32.768 kHz

Output transistors “off”

2

4

mA

µA

Middle-speed mode

f(XIN) = 8 MHz

f(XCIN) = stopped

Output transistors “off”

Middle-speed mode

f(XIN) = 8 MHz (in WIT state)

f(XCIN) = stopped

1.5

40

20

ICC

Power source current

Output transistors “off”

Low-speed mode

f(XIN) = stopped

f(XCIN) = 32.768 kHz

Output transistors “off”

Low-speed mode

f(XIN) = stopped

10

µA

f(XCIN) = 32.768 kHz (in WIT state)

Output transistors “off”

Additional current when A-D converter

works

f(XIN) = 8 MHz

500

1.5

0.1

µA

Additional current when LPC I/F functions

LCLK = 33 MHz

mA

Ta = 25 °C

All oscillation stopped

(in STP state)

Output transistors “off”

1.0

10

µA

Ta = 85 °C

93

MITSUBISHI MICROCOMPUTERS

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Table 32 Electrical characteristics

(VCC = 3.3 V ± 0.3V, VSS = 0 V, Ta = –20 to 85 °C, Flash memory version, unless otherwise noted)

Limits

Typ.

Symbol

Parameter

Test conditions

High-speed mode

Unit

mA

Min.

Max.

13

f(XIN) = 8 MHz

6.0

0.8

2.0

0.6

100

10

f(XCIN) = 32.768 kHz

Output transistors “off”

High-speed mode

f(XIN) = 8 MHz (in WIT state)

f(XCIN) = 32.768 kHz

Output transistors “off”

mA

µA

2

7

Middle-speed mode

f(XIN) = 8 MHz

f(XCIN) = stopped

Output transistors “off”

Middle-speed mode

f(XIN) = 8 MHz (in WIT state)

f(XCIN) = stopped

1.5

200

20

ICC

Power source current

Output transistors “off”

Low-speed mode

f(XIN) = stopped

f(XCIN) = 32.768 kHz

Output transistors “off”

Low-speed mode

f(XIN) = stopped

µA

f(XCIN) = 32.768 kHz (in WIT state)

Output transistors “off”

Additional current when A-D converter

works

500

µA

f(XIN) = 8 MHz

Additional current when LPC I/F functions

LCLK = 33 MHz

mA

1.5

0.1

Ta = 25 °C

All oscillation stopped

(in STP state)

µA

1.0

10

Ta = 85 °C

Output transistors “off”

94

MITSUBISHI MICROCOMPUTERS

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Table 33 A-D converter characteristics (1)

(VCC = 3.3 V ± 0.3V, VREF = 2.0 V to VCC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

10-bit A-D mode (when conversion mode selection bit (bit 7 of AD2) is “0”)

Limits

Typ.

Symbol

Parameter

Test conditions

Unit

Min.

Max.

10

–

Resolution

bit

LSB

2tc(XIN)

kΩ

VCC = VREF = 3.3 V

Absolute accuracy (excluding quantization error)

Conversion time

±4

tCONV

61

RLADDER

Ladder resistor

12

50

35

100

200

5

VREF = 3.3 V

at A-D converter operated

at A-D converter stopped

Reference power

150

µA

IVREF

source input current

µA

II(AD)

A-D port input current

µA

5.0

Table 34 A-D converter characteristics (2)

(VCC = 3.3 V ± 0.3V, VREF = 2.0 V to VCC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

8-bit A-D mode (when conversion mode selection bit (bit 7 of AD2) is “1”)

Limits

Typ.

Symbol

Parameter

Test conditions

Unit

Min.

Max.

8

–

Resolution

bit

LSB

2tc(XIN)

kΩ

VCC = VREF = 3.3 V

Absolute accuracy (excluding quantization error)

Conversion time

±2

tCONV

50

RLADDER

Ladder resistor

12

50

35

100

200

5

VREF = 3.3 V

at A-D converter operated

at A-D converter stopped

Reference power

150

µA

IVREF

source input current

µA

II(AD)

A-D port input current

µA

5.0

Table 35 D-A converter characteristics

(VCC = 3.3 V ± 0.3V, VREF = 2.7 V to VCC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Limits

Typ.

Symbol

Parameter

Test conditions

Unit

Min.

Max.

8

–

Resolution

Bits

%

Absolute accuracy

Setting time

1.0

3

tsu

µs

RO

Output resistor

2

3.5

5

kΩ

mA

IVREF

Reference power source input current

2.1

Table 36 Comparator characteristics

(VCC = 3.3 V ± 0.3V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Limits

Typ.

Symbol

–

Parameter

Test conditions

1LSB = VCC/16

Unit

Min.

Max.

1/2

3.5

7

Absolute accuracy

Conversion time

LSB

µs

V

at 8 MHz operating

at 4 MHz operating

TCONV

Analog input voltage

VIA

0

20

VCC

5.0

50

Analog input current

IIA

µA

kΩ

V

Ladder resistor

RLADDER

CMPREF

40

Internal reference voltage

External reference input voltage

29VCC/32

VCC/32

VCC

V

95

MITSUBISHI MICROCOMPUTERS

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Table 37 Timing requirements

(VCC = 3.3 V ± 0.3V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Limits

Unit

Symbol

Parameter

Min.

16

125

50

20

5

Typ.

Max.

tc(XIN)

ns

tW(RESET)

tC(XIN)

Reset input “L” pulse width

Main clock input cycle time

ns

tWH(XIN)

Main clock input “H” pulse width

Main clock input “L” pulse width

Sub-clock input cycle time

ns

tWL(XIN)

µs

tC(XCIN)

µs

tWH(XCIN)

tWL(XCIN)

tC(CNTR)

tWH(CNTR)

tWL(CNTR)

Sub-clock input “H” pulse width

Sub-clock input “L” pulse width

CNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse width

CNTR0, CNTR1 input “L” pulse width

µs

5

ns

200

80

ns

INT0, INT1, INT20, INT30, INT40, INT21, INT31, INT41

input “H” pulse width

ns

tWH(INT)

tWL(INT)

80

INT0, INT1, INT20, INT30, INT40, INT21, INT31, INT41

input “L” pulse width

ns

tC(SCLK1)

Serial I/O clock input cycle time (Note)

Serial I/O clock input “H” pulse width (Note)

Serial I/O clock input “L” pulse width (Note)

Serial I/O input setup time

800

370

220

100

tWH(SCLK1)

tWL(SCLK1)

tsu(RxD-SCLK1)

th(SCLK1-RxD)

Serial I/O input hold time

Note : When bit 6 of SIOCON is “1” (clock synchronous).

Divide this value by four when bit 6 of SIOCON is “0” (UART).

Table 38 Switching characteristics

(VCC = 3.3 V ± 0.3V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Limits

Test

conditions

Symbol

Parameter

Unit

Min.

Typ.

Max.

tWH (SCLK)

tWL (SCLK)

td (SCLK-TXD)

tV (SCLK-TXD)

tr (SCLK)

Serial I/O clock output “H” pulse width

Serial I/O clock output “L” pulse width

Serial I/O output delay time (Note 1)

Serial I/O output valid time (Note 1)

Serial I/O clock output rising time

Serial I/O clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

tC(SCLK)/2–30

ns

140

Fig. 90

–30

30

tf (SCLK)

tr (CMOS)

tf (CMOS)

10

Notes 1: When the P45/TXD P-channel output disable bit (bit 4 of UARTCON) is “0”.

2: The XOUT pin is excluded.

96

MITSUBISHI MICROCOMPUTERS

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Measurement output pin

50pF

CMOS output

Fig. 83 Circuit for measuring output switching characteristics

97

MITSUBISHI MICROCOMPUTERS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Timing diagram

tC(CNTR)

t

WH(CNTR)

tWL(CNTR)

0.8VCC

CNTR

0

, CNTR

1

0.2VCC

t

WH(INT)

t

WL(INT)

INT0, INT1, INT

INT20, INT30, INT40

INT21, INT31, INT41

5

0.8VCC

t

W(RESET)

RESET

0.8VCC

0.2VCC

tC(XIN)

tWH(XIN)

tWL(XIN)

0.8VCC

X

IN

0.2VCC

t

C(XCIN

)

t

WH(XCIN)

t

WL(XCIN)

0.8VCC

CIN

t

C(SCLK)

tr

tf

t

WL(SCLK

)

tWH(SCLK)

S

R

CLK

0.8VCC

0.2VCC

t

h(SCLK-RxD)

t

su(RxD-SCLK)

0.8V

0.2VC^CC^C

XD

t

v(SCLK-TXD)

t

d(SCLK-TXD)

TXD

Fig. 84 Timing diagram

98

MITSUBISHI MICROCOMPUTERS

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2

Table 39 Multi-master I C-BUS bus line characteristics

Standard clock mode

High-speed clock mode

Symbol

Parameter

Unit

Min.

4.7

Max.

Min.

1.3

tBUF

Bus free time

µs

ns

µs

ns

µs

tHD;STA

tLOW

0.6

1.3

Hold time for START condition

Hold time for SCL clock = “0”

Rising time of both SCL and SDA signals

Data hold time

4.0

4.7

tR

20+0.1Cb

0

300

0.9

1000

300

tHD;DAT

tHIGH

tF

0

Hold time for SCL clock = “1”

Falling time of both SCL and SDA signals

Data setup time

4.0

0.6

20+0.1Cb

100

300

tSU;DAT

tSU;STA

tSU;STO

250

4.7

4.0

Setup time for repeated START condition

Setup time for STOP condition

0.6

Note: Cb = total capacitance of 1 bus line

S

DA

t

HD:STA

t

su:STO

t

BUF

t

LOW

t

R

t

F

S

P

Sr

P

S

CL

t

HD:STA

t

HD:DAT

t

HIGH

tsu:DAT

t

su:STA

S : START condition

Sr: RESTART condition

P : STOP condition

2

Fig. 85 Timing diagram of multi-master I C-BUS

99

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Table 40 Timing requirements and switching characteristics

(VCC = 3.3 V ± 0.3V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Standard

Unit

Symbol

Parameter

LCLK clock input cycle time

LCLK clock input “H” pulse width

LCLK clock input “L” pulse width

Min.

30

11

13

Typ.

Max.

tC(CLK)

tWH(CLK)

tWL(CLK)

tsu(D-C)

ns

input set up time LAD3 to LAD0,

SERIRQ, CLKRUN, LFRAME

7

0

th(C-D)

tV(C-D)

ns

input hold time LAD3 to LAD0, CLKRUN, LFRAME

SERIRQ,

2

15

28

LAD3 to LAD0, SERIRQ, CLKRUN

valid delay time

toff(A-F)

ns

LAD3 to LAD0,SERIRQ,CLKRUN

floating output delay time

Timing diagrams of LPC Bus Interface and Serial Interrupt Output

tC(CLK)

t

WH(CLK)

tWL(CLK)

VIH

VIL

LCLK

tsu(D-C)

th(C-D)

LAD[3:0]

SERIRQ, CLKRUN, LFRAME

(Input)

tv(C-D)

LAD[3:0]

SERIRQ, CLKRUN

(Active output)

toff(A-F)

LAD[3:0]

SERIRQ, CLKRUN

(Floating output )

Fig. 86 Timing diagram of LPC Interface and Serialized IRQ

100

MITSUBISHI MICROCOMPUTERS

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PACKAGE OUTLINE

MMP

80P6Q-A

Plastic 80pin 12✕12mm body LQFP

EIAJ Package Code

LQFP80-P-1212-0.5

JEDEC Code

–

Weight(g)

0.47

Lead Material

Cu Alloy

MD

HD

D

80

61

l

2

1

60

Recommended Mount Pad

Dimension in Millimeters

Symbol

A

Min

–

Nom

–

Max

1.7

0.2

–

A1

0

0.1

A

2

–

1.4

b

0.13

0.105

11.9

–

0.18

0.125

12.0

0.5

0.28

0.175

12.1

–

c

D

E

e

20

41

21

40

H

L

D

13.8

0.3

–

0.45

–

0°

–

14.0

0.5

1.0

0.6

0.25

–

14.2

0.7

–

0.75

–

0.08

0.1

10°

–

A

E

L

1

F

L1

e

Lp

A3

x

y

–

b

y

x

M

L

b2

0.225

–

12.4

I

2

0.9

–

Lp

Detail F

M

D

E

Keep safety first in your circuit designs!

•

Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to

personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable

material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

•

These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property

rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.

Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples

contained in these materials.

All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by

Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product

distributor for the latest product information before purchasing a product listed herein.

The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.

Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).

When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision

on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.

Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric

Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical,

aerospace, nuclear, or undersea repeater use.

•

The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.

If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved

destination.

Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.

•

Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.

New publication, effective June 2002.

Specifications subject to change without notice.

REVISION HISTORY

3885 GROUP DATA SHEET

Rev.

1.0

Date

Description

Summary

Page

06/04/02

First edition issued.

(1/X)


型号：	M38853FB-HP
厂家：	RENESAS TECHNOLOGY CORP
描述：	SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单片8位CMOS微机计算机
文件：	总103页 (文件大小：1567K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M38853FB-HP [RENESAS]

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