M37754M8C-XXXGP [RENESAS]
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER; 单芯片16位CMOS微机
| 型号： | M37754M8C-XXXGP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| 文件： | 总115页 (文件大小：1558K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no ces whatsoever have been
made to the contents of the document, and these changes do not cony alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business opof high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Instruction execution time
•
DESCRIPTION
The M37754M8C-XXXGP is a single-chip microcomputer designed
with high-performance CMOS silicon gate technology. This is housed
in a 100-pin plastic molded QFP.
The fastest instruction at 40 MHz frequency ...................... 100 ns
Single power supply ...................................................... 5V 10 %
Low power dissipation (at 40 MHz frequency) .......125 mW (Typ.)
Interrupts ........................................................... 21 types, 7 levels
Multiple-function 16-bit timer ................................................... 5+3
(three-phase motor drive waveform or pulse motor control wave-
form output)
•
•
•
•
This microcomputer has a CPU and a bus interface unit. The CPU is
a 16-bit parallel processor that can also be switched to perform 8-bit
parallel processing, and the bus interface unit enhances the memory
access efficiency to execute instructions fast.
Serial I/O (UART or clock synchronous) ..................................... 2
10-bit A-D converter ............................................ 8-channel inputs
8-bit D-A converter ............................................ 2-channel outputs
12-bit watchdog timer
•
•
•
•
•
In addition to the 7700 Family basic instructions, the M37754M8C-
XXXGP has 6 special instructions which contain instructions for
signed multiplication/division; these added instructions improve the
servo arithmetic performance to control hard disk drives and so on.
This microcomputer also include the ROM, RAM, multiple-function
timers, motor control function, serial I/O, A-D converter, D-A con-
verter, and so on.
Programmable input/output
(ports P0—P11) ......................................................................... 87
Small package [M37754M8C-XXXHP]
•
.................................10-pin fine pitch QFP (read pitch : 0.5 mm)
The differences between M37754M8C-XXXGP, M37754M8C-XXXHP,
M37754S4CGP and M37754S4CHP are listed in the table on the
next page: the internal ROM, usable processor mode, and package.
Therefore, the following descriptions will be for the M37754M8C-
XXXGP unless otherwise noted.
APPLICATION
Control devices computer peripheral equipment such as
CD-ROM drik drives, high density FDD, printers
Control dce equipment such as copiers and facsimiles
Controindustrial equipment such as communication and
meuments
DISTINCTIVE FEATURES
Number of basic machine instructions .................................... 109
•
ces for equipment required for motor control such as in-
conditioner and general purpose inverter
(103 basic instructions of 7700 Family + 6 special instructions)
Memory size
ROM ................................................ 60 Kbytes
RAM................................................2048 byte
•
M37754M8C-XXXGP PIN CONFIGURATP VIEW)
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
81
8
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P87/TXD1
P86/RXD1
P85/CLK1
P111/D9
P112D10
P113/D11
P114/D12
P115/D13
P116/D14
P117/D15
P30/WR
P31/BHE
P32/ALE
P33/HLDA
VCC
VSS
E/RD
XOUT
XIN
RESET
CNVSS
BYTE
P84/CTS1/RTS1/DA1/INT4
P83/TX
P82/RXD0/C
P81/C
P80/CTS0/RTS0/CLKS1/DA0
VCC
AVCC
VREF
AVSS
VSS
M37754M8C-XXXGP
or
→
M37754S4CGP
↔
↔
↔
↔
↔
↔
↔
→
→
←
←
P77/AN7/ADTRG
P76/AN6
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
←
↔
P40/HOLD
Outline 100P6S-A
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M37754M8C-XXXHP PIN CONFIGURATION (TOP VIEW)
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
50 ↔ P107/D7/LA7
49 ↔ P110/D8
48 ↔ P111/D9
47 ↔ P112/D10
46 ↔ P113/D11
45 ↔ P114/D12
44 ↔ P115/D13
43 ↔ P116/D14
42 ↔ P117/D15
41 ↔ P30/WR
0 ↔ P31/BHE
↔ P32/ALE
P33/HLDA
P02/A2 ↔
P01/A1 ↔
P00/A0 ↔
P87/TXD1 ↔
P86/RXD1 ↔
P85/CLK1 ↔
P84/CTS1/RTS1/DA1/INT4 ↔
P83/TXD0 ↔
P82/RXD0/CLKS0 ↔
P81/CLK0 ↔
P80/CTS0/RTS0/CLKS1/DA0 ↔
VCC
M37754M8C-XXXHP
or
AVCC
VREF →
AVSS
36
VCC
VSS
M37754S4CHP
V
SS
35 → E/RD
34 → XOUT
33 ← XIN
P77/AN7/ADTRG ↔ 92
P76/AN6 ↔ 93
P75/AN5 ↔ 94
32 ← RESET
P74/AN4 ↔ 95
31
CNVSS
P73/AN3 ↔
P72/AN2 ↔
P71/AN1 ↔
96
97
98
99
100
30 ← BYTE
29 ↔ P40/HOLD
28 ↔ P41/RDY
27 ↔ P42/φ1
26 ↔ P43
P70/AN0 ↔
P95/INT3/KI4 ↔
Outline 100P6Q-A
Differences between M37754M8C-XXXGP, M37754M8C-XXXHP, M37754S4CGP, and M37754S4CHP
Product
M37754M8C-XXXGP
M37754M8C-XXXHP
Internal ROM
Equipped
Usable processor mode
Single-chip mode
Package
100-pin QFP (100P6S-A)
100-pin fine pitch QFP
(100P6Q-A)
•
•
•
•
(60 Kbytes)
Memory expansion mode
Microprocessor mode
Microprocessor mode
M37754S4CGP
M37754S4CHP
Not equipped
100-pin QFP (100P6S-A)
100-pin fine pitch QFP (100P6Q-A)
(External ROM)
2
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Data Bus(Even)
Data Bus(Odd)
Data Buffer DBH(8)
Data Buffer DBL(8)
Instruction Queue Buffer Q
Instruction Queue Buffer Q
Instruction Queue Buffer Q
0(8)
1(8)
2(8)
Address B
Incrementer(24)
Program Address Register PA(24)
Data Address Register DA(24)
Incrementer/Decrementer(24)
Program Counter PC(1
Program Bank Reg
Data Bank
Igister IB(16)
ssor Status Register PS(11)
Direct Page Register DPR(16)
Stack Pointer S(16)
Index Register Y(16)
Index Register X(16)
Accumulator B(16)
Accumulator A(16)
Arithmetic Logic
Unit(16)
3
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
FUNCTIONS OF M37754M8C-XXXGP
Parameter
Number of basic machine instructions
Instruction execution time
Functions
109
100 ns (the fastest instruction at external clock 40 MHz frequency)
ROM (Note 1)
60 Kbytes
Memory size
RAM
2048 bytes
P0, P1, P4 – P8, P10, P11
8-bit × 9
P2
Input/Output ports (Note 2)
P3
5-bit × 1
4-bit × 1
P9
6-bit × 1
TA0, TA1, TA2, TA3, TA4
Multiple-function timers
16-bit × 5
TB0, TB1, TB2
16-bit × 3
Serial I/O
(UART or clock synchronous serial I/O) × 2
A-D converter
10-bit × 1(8 channels)
8-bit × 2
D-A converter
Watchdog timer
Short-circuit prevention time set timer
Interrupts
12-bit × 1
8-bit × 3
5 external typel types
(Each interrt to priority levels 0 – 7.)
Clock generating circuit
Supply voltage
Built-in (exed to a ceramic resonator or quartz crystal resonator)
5 V±
Power dissipation
1ernal clock 40 MHz frequency)
Input/Output withstand voltage
Input/Output characteristic
Output current
Memory expansion
Operating temperature range
Device structure
imum 16 Mbytes
20 to 85 °C
CMOS high-performance silicon gate process
100-pin plastic molded QFP
Package
Notes 1: The M37754S4CGP and the M37754S4CHP are ith ROM.
2: Input/Output ports for the M37754S4CGP and tCHP are as shown below :
•
•
•
P5-P8, P11 (8-bit × 5)
P4 (5-bit × 1)
P9 (6-bit × 1)
4
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION (MICROCOMPUTER MODE)
Input/
Output
Pin
Name
Functions
VCC, VSS
CNVSS
Power supply
Supply 5 V±10 % to VCC and 0 V to VSS.
CNVSS input
Reset input
Clock input
Input
Input
This pin controls the processor mode. Connect to VSS for single-chip mode or memory
expansion mode. Connect to VCC for microprocessor mode and external ROM version.
RESET
XIN
This is reset input pin. The microcomputer is reset when supplying “L” level to this
pin.
These are I/O pins of internal clock generating circuit.Connect a ceramic or quartz-
crystal resonator between XIN and XOUT. When an external clock is used, the clock
Input
XOUT
E
Clock output
Output
source should be connected to the XIN pin and the XOUT pin should be left open.
_
Output This pin outputs enable signal E, which indicates access state of data bus for
Enable output
single-chip mode.
___
This pin outputs RD signal for memory expansion mode or microprocessor mode.
BYTE
(Note)
Bus width select input
Analog supply input
Input
This pin determines whether the external data bus is 8-bit width or 16-bit width for
memory expansion mode or microprocessor mode. The width is 16 bits when “L”
signal inputs and 8 bits when “H” signal inp.
AVCC,
AVSS
Power supply for the A-D converter and onverter. Connect AVCC to VCC
and AVSS to VSS externally.
VREF
Reference voltage input
I/O port P0
Input
I/O
This is reference voltage input pin onverter and the D-A converter.
P00 – P07
In single-chip mode, port P0 is port. This port has an I/O direction
register and each pin can bd for input or output. These ports are in
the input mode when resA0 - A7) is output in memory expansion mode
or microprocessor mod
P10 – P17
I/O port P1
I/O
I/O
I/O
In single-chip modehave the same functions as port P0. Address (A8 -
A15) is output in ansion mode or microprocessor mode.
P20 – P23, I/O port P2
P27
In single-chip pins have the same functions as port P0. Address (A16 -
A19, A23) is emory expansion mode or microprocessor mode.
P30 – P33
I/O port P3
In singlthese pins have the same functions as port P0. In memory
___ ____
_____
expaor microprocessor mode, WR, BHE , ALE, and HLDA signals are
ou
P40 – P47
I/O port P4
I/O
ip mode, these pins have the same functions as port P0. In memory
_____
n mode or micro processor mode, P40, P41, and P42 become HOLD and
put pins, and clock φ1 output pin respectively. Functions of other pins are
same as in single-chip mode. In memory expansion mode, P42 can be
rogrammed as I/O port.
P50 – P57
P60 – P67
I/O port P5
I/O port P6
I/O
In addition to having the same functions as port P0 in single-chip mode, these pins
also function as I/O pins for timer A0, timer A1, timer A2, timer A3, output pins for
motor drive waveform, and input pins for key input interrupt.
In addition to having the same functions as port P0 in single-chip mode, these pins
____
also function as I/O pins for timer A4, input pins for external interrupt input INT0,
____
____
INT1, and INT2, and input pins for timer B0, timer B1, and timer B2.
P70 – P77
P80 – P87
I/O port P7
I/O port P8
I/O
I/O
In addition to having the same functions as port P0 in single-chip mode, these pins
also function as input pins for A-D converter.
In addition to having the same functions as port P0 in single-chip mode, these pins
also function as I/O pins for UART0, UART1, output pins for D-A converter, and
____
input pin for INT4.
P90 – P95
I/O port P9
I/O
In addition to having the same functions as port P0 in single-chip mode, these pins
____
also function as input pin for INT3, output pins for motor drive waveform.
In memory expansion mode and microprocessor mode, these pins can be
___ ___
programmed as address (A20 - A22) or output pins for CS0 – CS4
Note: It is impossible to change the input level of the BYTE pin in each bus cycle. In other words, bus width cannot be switched dynamically. Fix the input
level of the BYTE pin to “H” or “L” according to the bus width used.
5
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Input/
Output
Pin
Name
I/O port P10
Functions
I/O
In single-chip mode, these pins have the same functions as port P0. In memory
expansion mode or microprocessor mode, these pins become data I/O pins and
operate as follows:
P100 – P107
(1) When using 16-bit width as external data bus width:
Accessing external memory
<When reading>
•
Pins’ value is input into low-order internal data bus (DB0 to DB7).
<When writing>
Value of low-order internal data bus (DB0 to DB7) is output to these pins.
Accessing internal memory
<When reading>
•
These pins become high impedance.
<When writing>
Value of internal data bus is output to these pins.
(2) When using 8-bit width as external data bus width:
Accessing external memory
<When reading>
•
Pins’ value is input into internhe value is input into low-order
internal data bus (DB0 to Dessing an even address; it is input
into high-order internal dto DB15) when accessing an odd
address.
<When writing>
Value of internal utput to these pins. The value of low-order
internal data bB7) is output when accessing an even address;
the value of ternal data bus (DB8 to DB15) is output when
accessinress.
Accessiemory
<Whe
•
Tcome high impedance.
g>
nternal data bus is output to these pins.
he external bus width is 8 bits, the mode where low-order address
___ ___
– LA7) is output when RD or WR output is “H” and data (D0 – D7) is
___ ___
put/output when RD or WR output is “L” can be selected in specified
external memory area access cycle.
P110 – P117
I/O port P11
n single-chip mode, these pins have the same functions as port P0. In memory
expansion mode or microprocessor mode, these pins operate as follows:
(1) When using 16-bit width as external data bus width
Accessing external memory
<When reading>
•
The value is input into high-order internal data bus (DB8 to DB15) when
accessing an odd address; these pins enter high impedance state when not
accessing an odd address.
<When writing>
Value of high-order internal data bus (DB8-DB15) is output to these pins.
Accessing internal memory
<When reading>
•
These pins enter high impedance state.
<When writing>
Value of internal data bus is output to these pins.
(2) When using 8-bit width as external data bus width
These pins become I/O port P110 – P117.
6
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Addresses FFD216 to FFFF16 are the RESET and interrupt vector
addresses and contain the interrupt vectors. Refer to the section on
BASIC FUNCTION BLOCKS
The M37754M8C-XXXGP contains the following devices on a single
chip: ROM, RAM, CPU, bus interface unit, timers, UART, A-D con-
verter, D-A converter, I/O ports, clock generating circuit and others.
Each of these devices is described below.
interrupts for details.
The 2048-byte area from addresses 8016 to 87F16 contains the inter-
nal RAM. In addition to storing data, the RAM is used as stack during
a subroutine call, or interrupts.
Assigned to addresses 016 to 7F16 are peripheral devices such as
I/O ports, A-D converter, D-A converter, UART, timer, and interrupt
control registers.
MEMORY
The memory map is shown in Figure 1. The address space is 16
Mbytes from addresses 016 to FFFFFF16. The address space is di-
vided into 64-Kbyte units called banks. The banks are numbered
from 016 to FF16.
Additionally the internal ROM area can be modified by software.
Refer to the section on ROM area modification function for details.
A 256-byte direct page area can be allocated anywhere in bank 016
using the direct page register DPR. In direct page addressing mode,
the memory in the direct page area can be accessed with two words
thus reducing program steps.
Internal ROM, internal RAM, and control registers for internal periph-
eral devices are assigned to bank 016.
The 60-Kbyte area from addresses 100016 to FFFF16 is the internal
ROM.
00000016
00000016
00007F16
00008016
0000016
Peripherai devices
control registers
Bank 016
see Fig. 2 for
further information
Intern
20
00007F16
00FFFF16
01000016
00087F16
Interrupt vector table
00FFD216
INT4
Bank 116
INT3
A–D
•
•
•
•
•
•
•
•
•
•
•
•
•
01FFFF16
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Internal ROM
60 Kbytes
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
FE000016
Bank FE16
INT2
INT1
FEFFFF16
FF000016
INT0
Watchdog timer
DBC
BRK instruction
Zero divide
Bank FF16
00FFFE16
RESET
00FFFF16
FFFFFF16
Note: Internal ROM area can be modified. (Refer to the section on ROM area modification function.)
Fig. 1 Memory map
7
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address (Hexadecimal notation)
Address (Hexadecimal notation)
Count start register
000000
000001
000040
000041
000042
000043
000044
000045
000046
000047
000048
000049
00004A
00004B
00004C
00004D
00004E
00004F
000050
000051
000052
000053
000054
000055
000056
000057
000058
0000
00
E
05F
00060
000061
000062
000063
000064
000065
000066
000067
000068
000069
00006A
00006B
00006C
00006D
00006E
00006F
000070
000071
000072
000073
000074
000075
000076
000077
000078
000079
00007A
00007B
00007C
00007D
00007E
00007F
One-shot start register
Port P0 register
Port P1 register
Port P0 direction register
Port P1 direction register
Port P2 register
Port P3 register
Port P2 direction register
Port P3 direction register
Port P4 register
Port P5 register
000002
000003
000004
000005
000006
000007
000008
000009
00000A
00000B
00000C
00000D
00000E
00000F
000010
000011
000012
000013
000014
000015
000016
000017
000018
000019
00001A
00001B
00001C
00001D
00001E
00001F
000020
000021
000022
000023
000024
000025
000026
000027
000028
000029
00002A
00002B
00002C
00002D
00002E
00002F
000030
000031
000032
000033
000034
000035
000036
000037
000038
000039
00003A
00003B
00003C
00003D
00003E
00003F
Up-down register
Timer A write register
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 registe
Timer B1 r
Timer
Port P4 direction register
Port P5 direction register
Port P6 register
Port P7 register
Port P6 direction register
Port P7 direction register
Port P8 register
Port P9 register
Port P8 direction register
Port P9 direction register
Port P10 register
Port P11 register
Port P10 direction register
Port P11 direction register
Waveform output mode register
Dead-time timer
Pulse output data register 1
Pulse output data register 0
A-D control register 0
Tregister
e register
ode register
3 mode register
r A4 mode register
mer B0 mode register
Timer B1 mode register
Timer B2 mode register
Processor mode register 0
Processor mode register 1
Watchdog timer register
Watchdog timer frequency select register
Chip select control register
Chip select area register
Comparator function select register
Reserved area (Note)
A-D control register 1
A-D register 0
A-D register 1
A-D register 2
A-D register 3
A-D register 4
A-D register 5
A-D registe
A-D register 7
Comparator result register
Reserved area (Note)
D-A register 0
D-A register 1
Particular function select register 0
Particular function select register 1
INT4 interrupt control register
INT3 interrupt control register
A-D interrupt control register
UART0 transmit/receive mode register
UART0 baud rate register
UART0 trasmit interrupt control register
UART0 receive interrupt control register
UART1 trasmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
UART0 transmit buffer register
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
UART0 receive buffer register
UART1 transmit/receive mode register
UART1 baud rate register
UART1 transmit buffer register
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
INT1 interrupt control register
INT2 interrupt control register
UART1 receive buffer register
Note: Do not write to this address.
Fig. 2 Location of peripheral devices and interrupt control registers
8
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
In index addressing mode, register X is used as the index register
CENTRAL PROCESSING UNIT (CPU)
The CPU has ten registers and is shown in Figure 3. Each of these
registers is described below.
and the contents of this address is added to obtain the real address.
Index register X functions as a pointer register which indicates an
address of data table in instructions MVP, MVN, RMPA (Repeat
MultiPly and Accumulate).
ACCUMULATOR A (A)
Accumulator A is the main register of the microcomputer. It consists
of 16 bits and the low-order 8 bits can be used separately. The data
length flag m determines whether the register is used as 16-bit regis-
ter or as 8-bit register. It is used as a 16-bit register when flag m is “0”
and as an 8-bit register when flag m is “1”. Flag m is a part of the pro-
cessor status register (PS) which is described later.
INDEX REGISTER Y (Y)
Index register Y consists of 16 bits and the low-order 8 bits can be
used separately. The index register length flag x determines whether
the register is used as 16-bit register or as 8-bit register. It is used as
a 16-bit register when flag x is “0” and as an 8-bit register when flag x
is “1”. Flag x is a part of the processor status register (PS) which is
described later.
Data operations such as calculations, data transfer, input/output,
etc., is executed mainly through the accumulator.
In index addressing mode, register Y is used as the index register
and the contents of this adis added to obtain the real address.
Index register Y functionter register which indicates an
address of data tabtions MVP, MVN, RMPA (Repeat
MultiPly and Acc
ACCUMULATOR B (B)
Accumulator B has the same functions as accumulator A, but the use
of accumulator B requires more instruction bytes and execution
cycles than accumulator A.
INDEX REGISTER X (X)
Index register X consists of 16 bits and the low-order 8 bits can be
used separately. The index register length flag x determines whether
the register is used as 16-bit register or as 8-bit register. It is used as
a 16-bit register when flag x is “0” and as an 8-bit register when
x is “1”. Flag x is a part of the processor status register (PS) w
described later.
7
7
0
0
0
0
0
0
0
0
AH
AL
BL
XL
YL
Accumulator A
5
15
15
15
15
15
BH
XH
YH
Accumulator B
7
7
Index register X
Index register Y
7
7
0
0
S
Stack pointer S
PG
DT
Program bank register PG
Data bank register DT
PC
Program counter PC
Direct page register DPR
Processor status register PS
DPR
7
15
0
IPL2 IPL1 IPL0
0
0
0
0
N
V
m
x
D
I
Z C
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Index register length flag
Data length flag
Overflow flag
Negative flag
Processor interrupt priority level IPL
Fig. 3 Register structure
9
MITSUBISHI MICROCOMPUTERS
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M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
STACK POINTER (S)
PROCESSOR STATUS REGISTER (PS)
Stack pointer (S) is a 16-bit register. It is used during a subroutine call
or interrupts. It is also used during stack, stack pointer relative, or
stack pointer relative indirect indexed Y addressing mode.
Processor status register (PS) is an 11-bit register. It consists of a
flag to indicate the result of operation and CPU interrupt levels.
Branch operations can be performed by testing the flags C, Z, V, and
N.
The details of each bit of the processor status register are described
below.
PROGRAM COUNTER (PC)
Program counter (PC) is a 16-bit counter that indicates the low-order
16 bits of the next program memory address to be executed. There
is a bus interface unit between the program memory and the CPU,
so that the program memory is accessed through bus interface unit.
This is described later.
1. Carry flag (C)
The carry flag contains the carry or borrow generated by the ALU af-
ter an arithmetic operation. This flag is also affected by shift and ro-
tate instructions. This flag can be set and reset directly with the SEC
and CLC instructions or with the SEP and CLP instructions.
PROGRAM BANK REGISTER (PG)
Program bank register is an 8-bit register that indicates the high-or-
der 8 bits of the next program memory address to be executed.
When a carry occurs by incrementing the contents of the program
counter, the contents of the program bank register (PG) is increased
by 1. Also, when a carry or borrow occurs after adding or subtracting
the offset value to or from the contents of the program counter (PC)
using the branch instruction, the contents of the program bank regis-
ter (PG) is increased or decreased by 1, so that programs can be
written without worrying about bank boundaries.
2. Zero flag (Z)
The zero flag is set if the of an arithmetic operation or data
transfer is zero and re. This flag can be set and reset
directly with the SEstructions.
3. Interrule flag (I)
When the sable flag is set to “1”, all interrupts except
watchC, and software interrupt are disabled. This flag
is smatically when there is an interrupt. It can be set and
with the SEI and CLI instructions or SEP and CLP in-
.
DATA BANK REGISTER (DT)
Data bank register (DT) is an 8-bit register. With some addressing
modes, the data bank register (DT) is used to specify a part of the
memory address. The contents of data bank register (DT) is used
the high-order 8 bits of a 24-bit address. Addressing modes t
the data bank register (DT) are direct indirect, direct index
rect, direct indirect indexed Y, absolute, absolute bit-
dexed X, absolute indexed Y, absolute bit relative, nter
relative indirect indexed Y.
Decimal mode flag (D)
The decimal mode flag determines whether addition and subtraction
are performed as binary or decimal. Binary arithmetic is performed
when this flag is “0”. If it is “1”, decimal arithmetic is performed with
each word treated as 2- or 4- digit decimal. Arithmetic operation is
performed using four digits when the data length flag m is “0” and
with two digits when it is “1”. Decimal adjust is automatically per-
formed. (Decimal operation is possible only with the ADC and SBC
instructions.) This flag can be set and reset with the SEP and CLP
instructions.
DIRECT PAGE REGISTER
Direct page register (DPR) is a 16-contents is used as
the base address of a 256-byte area. The direct page
area is allocated in bank 016, but n the contents of DPR is
FF0116 or greater, the direct page area spans across bank 016 and
bank 116. All direct addressing modes use the contents of the direct
page register (DPR) to generate the data address. If the low-order 8
bits of the direct page register (DPR) is “0016”, the number of cycles
required to generate an address is minimized.
Normally the low-order 8 bits of the direct page register (DPR) is set
to “0016”.
10
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5. Index register length flag (x)
9. Processor interrupt priority level (IPL)
The index register length flag determines whether index register X
and index register Y are used as 16-bit registers or as 8-bit registers.
The registers are used as 16-bit registers when flag x is “0” and as 8-
bit registers when it is “1”.
The processor interrupt priority level (IPL) consists of 3 bits and de-
termines the priority of processor interrupts from level 0 to level 7.
Interrupt is enabled when the interrupt priority of the device request-
ing interrupt (set using the interrupt control register) is higher than the
processor interrupt priority. When interrupt is enabled, the current
processor interrupt priority level is saved in a stack and the proces-
sor interrupt priority level is replaced by the interrupt priority level of
the device requesting the interrupt. Refer to the section on interrupts
for more details.
This flag can be set and reset with the SEP and CLP instructions.
6. Data length flag (m)
The data length flag determines whether the data length is 16-bit or
8-bit. The data length is 16-bit when flag m is “0” and 8-bit when it is
“1”. This flag can be set and reset with the SEM and CLM instructions
or with the SEP and CLP instructions.
Note: Fix bits 11 to 15 of the processor status register (PS) to “0”.
BUS INTERFACE UNIT
The CPU operates on the basis of internal clock φ CPU frequency. In
order to speed-up processing, a bus interface unit is used to pre-
fetch instructions when thbus is idle. The bus interface unit
synchronizes the CPU and pre-fetches instructions. Fig-
ure 4 shows the relaeen the CPU and the bus interface
unit.
7. Overflow flag (V)
The overflow flag is valid when addition or subtraction is performed
with a word treated as a signed binary number. If data length flag m
is “0”, the overflow flag is set when the result of addition or subtrac-
tion is outside the range between –32768 and +32767. If data length
flag m is “1”, the overflow flag is set when the result of addition or
subtraction is outside the range between –128 and +127. It is reset
in all other cases. The overflow flag can also be set and reset directly
with the SEP, and CLV or CLP instructions.
The bus intentrols buses to access memories easily.
Refer to Bn the following pages. The bus interface unit
has a ess register, a 3-byte instruction queue buffer, a
datister, and a 2-byte data buffer.
Additionally, the overflow flag is set when a result of unsigned/signed
division exceeds the length of the register where the result is to be
stored; the flag is also set when the addition result is outside range
of –2147483648 to +2147483647 in the RMPA operation.
face unit obtains an instruction code from memory and
n the instruction queue buffer, obtains data from memory
ores it in the data buffer, or writes the data form the data buffer
he memory.
8. Negative flag (N)
The negative flag is set when the result of arithmetic op
data transfer is negative (If data length flag m is “0”, d
“1”. If data length flag m is “1”, data’s bit 7 is “1”.) It is ther
cases. It can also be set and reset with the SEnstruc-
tions.
D'8–D'15
D'0–D'7
A'0–A'23
D8–D15
D0–D7
A0–A23
BHE
Bus interface
CPU
WR
unit
RD
ALE
Control signal
BYTE
HOLD
Fig. 4 Relationship between the CPU and the bus interface unit
11
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Figure 5 shows basic waveforms of the bus interface unit. The RD
(BYTE) to “L” (external data bus width = 16 bits). The internal
memory area is always treated as 16-bit bus width regardless of
BYTE.
signal becomes “L” when the bus interface unit reads an instruction
___
code or data from memory. The WR signal becomes “L” when the
bus interface unit writes data to memory.
When performing 16-bit data read or write, if the conditions for simul-
taneously accessing two bytes are not satisfied, waveforms (2) and
(4) are used to access each byte, one by one.
Waveforms (1) and (3) in Figure 5 are used to access a single byte
or two bytes simultaneously. To read or write two bytes simulta-
neously, the first address accessed must be even. Furthermore,
when accessing an external memory area in memory expansion
mode or microprocessor mode, set the bus width select input pin
However, when prefetching the instruction code, if the address of the
instruction code is odd, only one byte is read in the instruction queue
buffer.
(1)
(2)
WR
RD
WR
RD
Internal address
bus
Internal address
bus
Address
A
Address (even)
(A0 – A23)
(A0 – A23)
Internal data bus
(D0 – D7)
Internal data bus
(D0 – D7)
Data (even)
Invalid data
Data (even)
Internal data bus
(D8 – D15)
Internal data bus
(D8 – D
Data (odd)
Data (odd)
Invalid data
(3)
WR
WR
RD
RD
Internal address
bus
Internal address
bus
A
Address (odd)
Address (even)
(A0 – A23)
(A0 – A23)
Internal data bus
(D0 – D7)
Internal data bus
(D0 – D7)
(even)
Data (odd)
Invalid data
Data (odd)
Data (even)
Invalid data
Internal data bus
(D8 – D15)
Internal data bus
(D8 – D15)
Fig. 5 Basic waveforms of bus interface unit
12
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M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Instruction code read, data read, and data write are described below.
BUS CYCLE
The M37754M8C-XXXGP can select bus cycles shown in Figures 6
Instruction code read will be described first.
The CPU obtains instruction codes from the instruction queue buffer
and executes them. The CPU notifies the bus interface unit that CPU
is requesting an instruction code during an instruction code request
cycle. If the requested instruction code is not yet stored in the instruc-
tion queue buffer, the bus interface unit halts the CPU until it can
store more instructions than requested in the instruction queue
buffer.
and 7.
Central processing unit (CPU) running speed can be selected from
low-speed running (clock φ1 ≤ 12.5 MHz) and high-speed running
(clock φ1 ≤ 20 MHz); it is selected by bit 3 of processor mode register
1 (see Figure 9).
When accessing the external memory, the bus cycle is selected by
bits 4 and 5 of processor mode register 1.
Even if there is no instruction code request from the CPU, the bus
interface unit reads instruction codes from memory and stores them
in the instruction queue buffer when the instruction queue buffer is
empty or when only one instruction code is stored and the bus is idle
on the next cycle.
When accessing the internal memory, the bus cycle is selected by bit
2 of processor mode register 0 (see Figure 14).
Figure 8 shows output signals at 3-φ access in high-speed running.
The BHE signal becomes “L” when accessing the odd address.
Signals A0 and BHE indicate the differences between 1-byte read in
even address, 1-byte read in odd address, and simultaneous 2-byte
read in even and odd as; these signals also indicate the
differrences between in even address, 1-byte write in
odd address, and s2-byte write in even and odd ad-
dress.
This is referred to as instruction pre-fetching.
Normally, when reading an instruction code from memory, if the ac-
cessed address is even, the next odd address is read together with
the instruction code and stored in the instruction queue buffer.
However, in memory expansion mode or microprocessor mode, if the
bus width select input (BYTE) is “H” and external data bus width is 8
bits, and if the address to be read is in external memory area or is
odd, only one byte is read and stored in the instruction queue buffer.
Data read and write are described below.
The A0 signa0 of address, becomes “L” when access-
ing an eve
TablA0 and BHE
thod
Simultaneous
access of 2 bytes in even address
Access of 1 byte Access of 1 byte
The CPU notifies the bus interface unit when performing data read
or write. At this time, the bus interface unit halts the CPU if the bus
interface unit is already using the bus or if there is a request with
higher priority. When data read or write is enabled, the bus interfa
unit performs data read or write.
in odd address
0
“L”
“L”
“L”
“H”
“L”
BHE
“H”
During data read, the CPU waits until the entire data is sto
data buffer. The bus interface unit sends the address s
CPU to the address bus. Then it reads the memory wig-
nal is “L” and stores the result in the data buffer.
During data write, the CPU writes the data in er and the
bus interface unit writes it to memory. ThePU can pro-
ceed to the next step without waiting fmplete. The bus
interface unit sends the address seCPU to the address
___
bus. Then, when the WR signal us interface unit sends
the data in the data buffer to the dand writes it to memory.
13
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Low-speed running (φ1 ≤ 12.5 MHZ)
Internal memory access
External memory access
2-φ access
2-φ access
Read
Write
Read
Write
φ
φ
φ
φ
RD
WR
Ai
RD
RD
WR
Ai
RD
WR
Ai
WR
ADRS
Ai
Di
ADRS
ADRS
ADRS
Di
W-D
1bus cycle = 2φ
Di
R-D
Di
W-D
1bus cycle = 2φ
1bus cycle = 2φ
1bus cycle = 2φ
3-φ access
Read
Write
φ
φ
Ai
RD
WR
Ai
––––––––––––––––––––––––––––––
ADRS
ADRS
W-D
Di
R-D
Di
1bus cycle = 3φ
1bus cycle = 3φ
4-φ access
Read
Write
φ
φ
RD
WR
RD
WR
ADRS : Address
Ai
Di
Ai
Di
ADRS
ADRS
R-D : Read data
W-D : Write data
R-D
W-D
1bus cycle = 4φ
1bus cycle = 4φ
Fig. 6 Bus cycle selection (low-speed running)
14
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
High-speed running (φ1 ≤ 20 MHZ)
Internal memory access
External memory access
2-φ access (Note)
3-φ access
Read
Write
Read
Write
φ
φ
φ
φ
RD
WR
Ai
RD
RD
WR
Ai
RD
WR
Ai
WR
ADRS
Ai
Di
ADRS
ADRS
ADRS
Di
W-D
Di
R-D
Di
W-D
1bus cycle = 3φ
1bus cycle = 3φ
1bus cycle = 2φ
1bus cycle = 2φ
3-φ access (Note)
4-φ access
Read
Write
Read
Write
φ
φ
φ
φ
RD
RD
RD
RD
WR
Ai
WR
Ai
WR
Ai
ADRS
ADRS
ADRS
ADRS
W-D
Di
R-D
Di
W-D
1bus cycle = 4φ
Di
Di
1bus cycle = 3φ
1bus cycle =
1bus cycle = 4φ
5-φ access
Read
Write
φ
φ
RD
RD
WR
Ai
WR
Ai
ADRS
ADRS
Note: Refer to internal memory access bus cycle select bit (bit 2
of processor mode register 0 ; Figure 14).
Di
R-D
Di
W-D
1bus cycle = 5φ
ADRS : Address
R-D : Read data
W-D : Write data
1bus cycle = 5φ
Fig. 7 Bus cycle selection (high-speed running)
15
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Access from even address
Access from odd address
φ1
φ1
Ai
A0 – A23
D0 – D7
Ai
A0 – A23
D0 – D7
Di
Di
BHE
ALE
RD, WR
BHE
ALE
RD, WR
φ1
φ1
Ai
D0 – D7
A0 – A23
D0 – D7
Ai
A0 – A23
D0 – D7
A0 – A23
D0 – D7
Di
Di
B
WR
BHE
ALE
RD, WR
φ1
φ1
Ai
A0 – A19
Ai
A0 – A23
(Note 1)
DHi
DLi
DHi
DLi
D8 – D15
(Note 1)
BHE
ALE
BHE
ALE
RD, WR
RD, WR
φ1
φ1
Ai
A0 – A23
A0 – A23
(Note 1)
Ai
A0 – A23
D8 – D15
D0 – D7
DHi
D8 – D15
(Note 1)
DHi
D0 – D7
DLi
DLi
BHE
BHE
ALE
ALE
RD, WR
RD, WR
Notes 1: It becomes Hi-Z when reading, and it outputs undefined data when writing.
2: When the external data bus width is 8 bits, the function to output the low-order address from the Di pin while RD or WR is “H” can be selected only
in special area access cycle. Refer to the section on the processor mode for details.
Fig. 8 Output signals at 3-φ access in high-speed running
16
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7
0
6
5
4
3
2
1
0
0
0
Address
Processor mode register 1 5F16
These bits must be “00.”
Clock source for peripheral devices select bit (Note)
0 : φ1/2
1 :φ1
CPU running speed select bit
0 : High-speed running
1 : Low-speed running
Bus cycle select bits
In high-speed running
00 : 5-φ access in high-speed running
01 : 4-φ access in high-speed runn
10 : 3-φ access in high-speed r
11 : Do not select.
In low-speed running
00 : Do not select.
01 : 4-φ access in ning
10 : 3-φ access unning
11 : 2-φ acced running
Clock bit
0
must be “0.”
Note: When φ1 > 12.5 MHz”
Fig. 9 Processor mode register 1 bit config
17
MITSUBISHI MICROCOMPUTERS
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Table 2. Interrupt types and the interrupt vector addresses
INTERRUPTS
Table 2 shows the interrupt types and the corresponding interrupt
vector addresses. Reset is also treated as a type of interrupt and is
discussed in this section, too.
Interrupts
Vector addresses
00FFD216 00FFD316
00FFD416 00FFD516
____
INT4 external interrupt
____
INT3 external interrupt
A-D
DBC is an interrupt used during debugging.
00FFD616
00FFD816
00FFD716
00FFD916
Interrupts other than reset, DBC, watchdog timer, zero divide, and
BRK instruction all have interrupt control registers. Table 3 shows the
addresses of the interrupt control registers and Figure 10 shows the
bit configuration of the interrupt control register.
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
00FFDA16 00FFDB16
00FFDC16 00FFDD16
00FFDE16 00FFDF16
The interrupt request bit is automatically cleared by the hardware
during reset or when processing an interrupt. Also, interrupt request
00FFE016
00FFE216
00FFE416
00FFE616
00FFE816
00FFE116
00FFE316
00FFE516
00FFE716
00FFE916
Timer B1
bits other than DBC and watchdog timer can be cleared by software.
____ ___
Timer B0
INT4 to INT0 are external interrupts; whether to cause an interrupt at
the input level (level sense) or at the edge (edge sense) can be se-
lected with the level/edge select bit. Furthermore, the polarity of the
interrupt input can be selected with the polarity select bit.
Timer A4
Timer A3
Timer A2
00FFEA16 00FFEB16
00FFEC16 00FFED16
00FFEE16 00FFEF16
Timer A1
In the INT3 external interrupt, the INT3 input, KI3 to KI0 inputs, or KI4
____
Timer A0
____
to KI0 inputs can be selected with bits 7 and 6 of INT3 interrupt con-
trol register.
INT2 external in
____
00FFF016
00FFF216
00FFF416
00FFF616
00FFF816
00FFFA16
00FFF116
00FFF316
00FFF516
00FFF716
00FFF916
00FFFB16
INT1 externa
____
Timer and UART interrupts are described in the respective section.
The priority of interrupts when multiple interrupts are caused simul-
taneously is partially fixed by hardware, but, it can also be adjusted
by software as shown in Figure 11.
INT0 exte
Watc
____
Dlect.)
ction
de
The hardware priority is fixed as the following:
reset > DBC > watchdog timer > other interrupts
00FFFC16 00FFFD16
00FFFE16 00FFFF16
t
7
6
5
4
3
2
1
0
Interrupt priority leve
Interrupt reque
0 : No inte
1 : Inter
Interrupt control register configuration for, UART0, UART1, timer A0 to timer A4, and timer B0 to timer B2.
Note 1: The A-D conversion interrupt comes undefined after reset. Clear this bit to “0” before use of the A-D conversion interrupt.
7
6
5
4
3
2
1
0
Interupt priority level
Interrupt request bit
0 : No interrupt
1 : Interrupt
Polarity select bit
0 : Set interrupt request bit at “H” level for level sense and when changing from “H” to “L”
level for edge sense.
1 : Set interrupt request bit at “L” level for level sense and when changing from “L” to “H”
level for edge sense.
Level/Edge select bit
0 : Edge sense
1 : Level sense
Key input interrupt select bits 1, 0 (only for INT3 interrupt control register)
0 0 : INT3 interrupt selected
0 1 : Do not select.
1 0 : Key input interrupt (KI3 to KI0) selected
1 1 : Key input interrupt (KI4 to KI0) selected
Interrupt control register configuration for INT4– INT0 (Note 2).
Note 2: The contents of INT4 interrupt control register after reset cannot be changed unless bit 5 of the particular function select register 1 (see
Figure 15) is set to “1.”
Fig. 10 Interrupt control register bit configuration
18
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Table 3. Addresses of interrupt control registers
The interrupt request bit and the interrupt priority level of each inter-
rupt source are sampled and latched at each operation code fetch
Interrupt control registers
____
Addresses
cycle while φBIU is “H”. However, no sampling pulse is generated
until the cycles whose number is selected by software has passed,
even if the next operation code fetch cycle is generated. The detec-
tion of an interrupt which has the highest priority is performed during
that time.
INT4 interrupt control register
____
00006E16
00006F16
00007016
00007116
00007216
00007316
00007416
00007516
00007616
00007716
00007816
00007916
00007A16
00007B16
00007C16
00007D16
00007E16
00007F16
INT3 interrupt control register
A-D interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Priority is determined by hardware
4
3
2
1
Watchdog
timer
DBC
Reset
Timer B2 interrupt control register
____
A-D converter, UARTs
INT0 interrupt control register
____
Priority can be coftware inside 4
Fig. 11 Iity
INT1 interrupt control register
____
INT2 interrupt control register
Interrupts caused by a BRK instruction and when dividing by zero are
software interrupts and are not included in this list.
Level 0
INT
4
Other interrupts previously mentioned are A-D converter, UART, etc.
interrupts. The priority of these interrupts can be changed by chang
ing the priority level in the corresponding interrupt control registe
software.
INT
3
A-D
Figure 12 shows a diagram of the interrupt priority detec
When an interrupt is caused, each interrupt device com
priority with the priority from above and if its own her,
then it sends the priority below and requests ththe pri-
orities are the same, the one above has prio
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Interrupt request
This comparison is repeated to select thth the highest
priority among the interrupts that are sted. Finally the
selected interrupt is compared witsor interrupt priority
level (IPL) contained in the pros register (PS) and the
request is accepted if it is higher tL and the interrupt disable
flag I is “0”. The request is not accepted if flag I is “1”. The reset, DBC,
and watchdog timer interrupts are not affected by the interrupt dis-
able flag I.
Reset
Timer B1
Timer B0
DBC
Timer A4
Timer A3
When an interrupt is accepted, the contents of the processor status
register (PS) is saved to the stack and the interrupt disable flag I is
set to “1”.
Timer A2
Watchdog timer
Timer A1
Furthermore, the interrupt request bit of the accepted interrupt is
cleared to “0” and the processor interrupt priority level (IPL) in the
processor status register (PS) is replaced by the priority level of the
accepted interrupt.
Timer A0
INT
INT
INT
2
1
0
Interrupt disable flag I
IPL
Therefore, multi-level priority interrupts are possible by resetting the
interrupt disable flag I to “0” and enable further interrupts.
For reset, DBC, watchdog timer, zero divide, and BRK instruction in-
terrupts, which do not have an interrupt control register, the proces-
sor interrupt level (IPL) is set as shown in Table 4.
Fig. 12 Interrupt priority detection
19
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
As shown in Figure 13, there are three different interrupt priority de-
Table 4. Value set in processor interrupt level (IPL) during an interrupt
tection time from which one is selected by software. After the se-
lected time has elapsed, the highest priority is determined and is
processed after the currently executing instruction has been com-
pleted.
Interrupt types
Setting value
Reset
0
____
DBC
7
Watchdog timer
Zero divide
7
The time is selected with bits 4 and 5 of the processor mode register
0 (address 5E16) shown in Figure 14. Table 5 shows the relationship
between these bits and the number of cycles. After a reset, the pro-
cessor mode register 0 is initialized to “0016.” Therefore, the longest
time is automatically set, however, the shortest time must be se-
lected by software.
Not change value of IPL.
Not change value of IPL.
BRK instruction
Table 5. Relationship between interrupt priority detection time select
bit and number of cycles
Priority detection time select bit
Number of cycles
Bit 5
Bit 4
0
0
1
0
1
0
7 cycles of φBIU
4 cycles of φBIU
2 cycles of φBIU
φBIU
Operation code fetch cycle
Sampling pulse
Priority detection time
0
1
2
Select one from 0 to 2 with
bits 4 and 5 of processor
mode register 0
Fig. 13 Interrupt priority detection tim
20
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
0
5
4
3
2
1
0
Processor mode register 0 (5E16)
Processor mode bits
00 : Single-chip mode
01 : Memory expansion mode
10 : Microprocessor mode
11 : Do not select.
Internal memory access bus cycle select bit (Note)
Internal memory access condition in high-speed running
0 : 2-φ access for internal RAM, 3-φ access for internal ROM and SFR
1 : 2-φ access for internal RAM, internal ROM, SFR
Software reset bit
The microcomputer is reset when this bit is set to “1”.
Interrupt priority detection time select bit
0 0 : Select 0 in Figure 13
0 1 : Select 1 in Figure 13
1 0 : Select 2 in Figure 13
Test mode bit
This bit must be “0.”
Clock φ1 output select bit
0 : No φ1 output
1 : φ1 output
Note: When selecting low-speed running, set bit 2 t
Fig. 14 Processor mode register 0 bit configuration
7
6
5
4
3
2
1
0
Particular functioer 1 (6D16)
TC1 TC0
Transmit in select bit
00 : Nutput only to CLK0)
01 specified; output to CLK0
ks specified; output to CLKS0
ocks specified; output to CLKS1
l clock stop select bit at WIT (Note 1)
lock for peripheral function and watchdog timer are operating at WIT
: Internal clock except that for oscillation circuit and watchdog timer are stopped at WIT
Watchdog timer’s clock select bit (Note 1)
0 : Exclusive clock deviding circuit output (Wf512, Wf32) is used as clock for watchdog
timer. Clock (Wf512, Wf32) for watchdog timer does not change in hold.
1 : Clock for peripheral device deviding circuit output (Pf512, Pf32) is used as clock for
watchdog timer. Clock (Pf512, Pf32) for watchdog timer changes in hold.
Watchdog timer exclusive clock dividing circuit is stopped.
Signal output stop select bit (Note 1)
Refer to Table 8.
Expansion function select bit (Note 2)
Refer to Figure 62.
Pull-up select bit 0 (Note 3)
0 : With no pull-up for P57, P56, P55, P54
1 : With pull-up for P57, P56, P55, P54
Pull-up select bit 1 (Note 3)
0 : With no pull-up for P95
1 : With pull-up for P95
Notes 1: Bits 2, 3, and 4 can be re-write after bit 5 (expansion function select bit) is set to “1.”
2: After bit 5 is set to “1” once, bit 5 cannot be cleared to “0” except external reset and software reset.
3: Bits 6 and 7 are write-only bits and undefined at read. Do not use SEB or CLB insturuction when setting bits 0–7.
Fig. 15 Processor mode register 0 bit configuration
21
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The INT3 interrupt can function as the key input interrupt by setting
to KI0 pins is performed.
bits 7 and 6 of the INT3 interrupt control register. The key input inter-
rupt uses inputs KI3 to KI0 or inputs KI4 to KI0. Figure 10 shows the
interrupt control register bit configuration. Figure 15 shows the par-
ticular function select register 1 bit configuration, and Figure 16
shows the INT3/key input interrupt input circuit block diagram.
When the INT3 interrupt control register’s bit 7 is “0” and its bit 6 is
“0”, a signal from the INT3 pin is connected to the INT3 interrupt con-
trol circuit and INT3 external interrupt is normally performed.
When the INT3 interrupt control register’s bit 7 is “1” and its bit 6 is
“0”, signals from the KI3 to KI0 pins, which correspond to ports P57 to
P54, are inverted and then the logical sum of these signals is con-
nected to the INT3 interrupt control circuit. In this case, the external
interrupt which uses the KI3 to KI0 pins is performed.
When using the above key input interrupt, select the edge sense
which uses the falling edge from “H” to “L” with the INT3 interrupt
control register so that an interrupt request can occur by inputting “L”
to each of the KI3 to KI0 pins or the KI4 to KI0 pins. The interrupt vec-
tor is common to the INT3 interrupt’s one. Additionally, pull-up resis-
tor (transistors) can be added to the KI4 to KI0 pins by setting the
contents of the particular function select register 1’s bits 7 and 6 and
setting “0” to each bit of the corresponding port’s direction register.
When the INT3 interrupt control register’s bit 7 is “1” and its bit 6 is
“1”, signals from the KI4 pin, which corresponds to port P95, KI3 to
KI0 pins, which correspond to ports P57 to P54, are inverted and then
the logical sum of these signals is connected to the INT3 interrupt
control circuit. In this case, the external interrupt which uses the KI4
INT3 interrupt control register
(Address 6F16)
Pull-up select bit 1
Port P95 direction register
When the key input interrupt
is selected, select the edge
sense which uses falling edge
from “H” to “L”.
P95/INT3/KI4
Key input interrupt select bit 1
Bit 7 of INT interrupt
control register
3
Key input interrupt select bit 0
(Bit 6 of INT3 interrupt control regis
0
Interrupt control circuit
INT3 interrupt request
Pu0
on
Pull-up
transistor
1
P57/TA3IN/KI3
Pull-up
transistor
Port P56 direction
register
P56/TA3OUT/KI2
Pull-up
transistor
Port P55 direction
register
P55/TA2IN/KI1
Pull-up
Port P54 direction
register
transistor
P54/TA2OUT/KI0
Fig. 16 INT3/key input interrupt input circuit block diagram
22
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TIMER
(1) Timer mode [00]
There are eight 16-bit timers. They are divided by type into timer A(5)
Figure 18 shows the bit configuration of the timer Ai mode register
during timer mode. Bits 0 and 1 of the timer Ai mode register must be
“0” in timer mode. Bits 3, 4, and 5 are used to select the gate func-
tion. Bits 4 and 5 must be “0” when not selecting the gate function.
Bit 3 is ignored if bit 4 is “0”.
and timer B(3).
The timer I/O pins are multiplexed with I/O pins for port P5 and P6.
To use these pins as timer input pins, the data direction register bit
corresponding to the pin must be cleared to “0” to specify input mode.
Bits 6 and 7 are used to select the timer counter source.
The counting of the selected clock starts when the count start bit is
“1” and stops when it is “0”.
TIMER A
Figure 17 shows a block diagram of timer A.
Figure 19 shows the bit configuration of the count start bit. The
counter is decremented, an interrupt is caused and the interrupt re-
quest bit in the timer Ai interrupt control register is set when the con-
tents becomes 000016. At the same time, the contents of the reload
register is transferred to the counter and count is continued.
When data is written to timer Ai register with timer Ai halted, the same
data is also written to the rregister and the counter. When data
is written to timer Ai whthe data is written to the reload
register, but not to the new data is reloaded from the re-
load register to ththe next reload time and counting con-
tinues. The cocounter can be read at any time.
When the he timer Ai register is n, the timer frequency
dividin+1).
Timer A has four modes: timer mode, event counter mode, one-shot
pulse mode, and pulse width modulation mode. The mode is se-
lected with bits 0 and 1 of the timerAi mode register (i = 0 to 4). Each
of these modes is described below.
Data bus (odd)
Data bus (even)
(Lower 8 bits)
(Higher 8 bits)
Clock source selection
• Timer
Pf
2
• One-shot
Reload register(16)
• Pulse wid
Pf16
Pf64
ion)
ounter
Pf512
Counter(16)
A
ddresses
Up/Down
Polarity
selection
Count start bit
(4016
Down count
Always decremented
except in event count mode
Timer A0 4716 4616
Timer A1 4916 4816
Timer A2 4B16 4A16
Timer A3 4D16 4C16
Timer A4 4F16 4E16
TAiIN
(i = 0–4)
)
External trigger
Up-down bit
(4416
)
Pulse output
Toggle flip-flop
TAiOUT
(i = 0–4)
Note: Perform write and read to/from timer Ai register in the condition of 16-bit data length : data length flag (m) = “0”.
Fig. 17 Block diagram of timer A
23
MITSUBISHI MICROCOMPUTERS
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When bit 5 is “0, counting restarts from the value which is contained
Pulse output function
at restarting (gate function 0 [no reload]) and an overflow occurs (n +
1) cycles of the count source later. Figure 21 shows that operation.
When bit 5 is “1”, counting restarts from the value which is obtained
by reload at restarting (gate function 1 [reload]) and the first overflow
occurs (n + 2) cycles of the count source later. Figure 22 shows that
operation. After that, while the input signal from the TAiIN pin keeps
valid level, an overflow occurs at (n + 1)- cycle intervals. Make sure
to set the value of 1 or more to n.
When bit 2 of the timer Ai mode register is “1”, the output is gener-
ated from TAiOUT pin. The output is toggled each time the contents of
the counter reaches to 000016. When the contents of the count start
bit is “0”, “L” is output from TAiOUT pin.
When bit 2 is “0”, TAiOUT can be used as a normal port pin. When bit
4 is “0”, TAiIN can be used as a normal port pin.
Gate function
When gate functions are used, the duration of “H” or “L” on the TAiIN
pin must be 2 or more cycles of the timer count source.
When bit 4 is “1”, counting is performed only while the input signal
from the TAiIN pin is “H” or “L” as shown in Figure 20. Therefore, this
can be used to measure the pulse width of the TAiIN input signal.
Whether to count while the input signal is “H” or while it is “L” is de-
termined by bit 3. If bit 3 is “1”, counting is performed while the TAiIN
pin input signal is “H” and if bit 3 is “0”, counting is performed while it
is “L”.
es
Timer A0 mode
Timer A1 mo
Timer A2
Timer Ar
Timester
16
5716
5816
5916
5A16
7
6
5
4
3
2
1
0
0
0
0 0 in timer mode
se output (TAiOUT is normal port pin)
e output
: No gate function (TAiIN is normal port pin)
0 : Count only while TAiIN input is “L”
1 1 : Count only while TAiIN input is “H”
0 : Gate function 0 (No reload)
1 : Gate function 1 (Reload) ; Note
Clock source select bit
0 0 : Select Pf
2
0 1 : Select Pf16
1 0 : Select Pf64
1 1 : Select Pf512
Note: When selecting no gate functiobit 4 = “0”) in timer mode, fix bit 5 to “0”.
Fig. 18 Timer Ai mode register bit configuration during timer mode
24
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
1
0
Count start register
(Stop at “0”, Start at “1”)
Address
4016
Timer A0 count start bit
Timer A1 count start bit
Timer A2 count start bit
Timer A3 count start bit
Timer A4 count start bit
Timer B0 count start bit
Timer B1 count start bit
Timer B2 count start bit
Fig. 19 Count start flag bit configuration
Selected clock source Pfi
TAiIN
Timer mode regist
Bit 4
Bit 3
1
0
Timer mode register
Bit 4
Bit 3
1
1
Fig. 20 Count waveform when gate function is available
25
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
FFFF16
n
Count start
Count stop
Overflow
Count stop
Time
“1”
Count start flag
“0”
Valid level
Input level to
TAiIN pin
Invalid level
TAi interrupt
request bit
Clearethe interrupt request or by software
Fig. 21 Timer operation example with gate function 0 (no reload) selected
FFFF16
n
Count start
ed
Reloaded
duration
ount stop
Overflow
Time
“1”
Count start flag
“
Valid level
Input level to
TAiIN pin
Invalid level
TAi interrupt
request bit
Cleared by accepting the interrupt request or by software
Fig. 22 Timer operation example with gate function 1 (reload) selected
26
MITSUBISHI MICROCOMPUTERS
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(2) Event counter mode [01]
Figure 23 shows the bit configuration of the timer Ai mode register
during event counter mode. In event counter mode, bit 0 of the timer
Ai mode register must be “1” and bits 1 and 5 must be “0”.
The input signal from the TAiIN pin is counted when the count start bit
shown in Figure 19 is “1” and counting is stopped when it is “0”.
Count is performed at the fall of the input signal when bit 3 is “0” and
at the rise of the signal when it is “1”.
Addresses
5616
5716
5816
5916
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
7
×
6
×
5
0
4
3
2
1
0
0
1
5A16
0 1 : Always “01” in event counter mode
In event counter mode, whether to increment or decrement the count
can be selected with the up-down bit or the input signal from the
TAiOUT pin.
0 : No pulse output
1 : Pulse output
When bit 4 of the timerAi mode register is “0”, the up-down bit is used
to determine whether to increment or decrement the count (decre-
ment when the bit is “0” and increment when it is “1”). Figure 24
shows the bit configuration of the up-down register.
0 : Count at the falling edge of input signal
1 : Count at the rising edge of input signal
0 ncrement or decrement according
p/down flag
ent or decrement according
iOUT pin input signal level
When bit 4 of the timer Ai mode register is “1”, the input signal from
the TAiOUT pin is used to determine whether to increment or decre-
ment the count. However, note that bit 2 must be “0” if bit 4 is “1.” It is
because if bit 2 is “1”, TAiOUT pin becomes an output pin to output
pulses.
0 : Always “0” in event counter mode
The count is decremented when the input signal from the TAiOUT pin
is “L” and incremented when it is “H”. Determine the level of the input
signal from the TAiOUT pin before a valid edge is input to theTAiIN pin.
An interrupt request signal is generated and the interrupt request bit
in the timer Ai interrupt control register is set when the counter
reaches 000016 (decrement count) or FFFF16 (increment count). At
the same time, the contents of the reload register is transferred to
counter and the count is continued.
× × : Not used in event counter mode
3 Timer Ai mode register bit configuration during event
counter mode
When bit 2 is “1,” each time the counter reaches 000016 (d
count) or FFFF16(increment count), the waveform’s p
versed and is output from TAiOUT pin.
Address
4416
7
6 5 4 3 2 1 0
Up-down register
If bit 2 is “0”, TAiOUT pin can be used as a norma
However, if bit 4 is “1” and the TAiOUT pin is utput pin,
the output from the pin changes the count erefore, bit 4
must be “0” unless the output from the to be used to se-
lect the count direction.
Timer A0 up-down bit
Timer A1 up-down bit
Timer A2 up-down bit
Timer A3 up-down bit
Timer A4 up-down bit
Timer A2 two-phase pulse signal
processing select bit
0 : Two-phase pulse signal processing
disabled
1 : Two-phase pulse signal processing
mode
Timer A3 two-phase pulse signal
processing select bit
0 : Two-phase pulse signal processing
disabled
1 : Two-phase pulse signal processing
mode
Timer A4 two-phase pulse signal
processing select bit
0 : Two-phase pulse signal processing
disabled
1 : Two-phase pulse signal processing
mode
Fig. 24 Up-down register bit configuration
27
MITSUBISHI MICROCOMPUTERS
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Data write and data read are performed in the same way as for timer
be set to “1” and bits 1, 2, 3, and 5 must be “0”. Bits 6 and 7 are ig-
nored. Note that bits 5, 6, and 7 of the up-down register (4416) are
the two-phase pulse signal processing select bits for timers A2, A3
and A4 respectively. Each timer operates in normal event counter
mode when the corresponding bit is “0” and performs two-phase
pulse signal processing when it is “1”.
mode. That is, when data is written to timerAi halted, it is also written
to the reload register and the counter. When data is written to timer
Ai which is busy, the data is written to the reload register, but not to
the counter. The counter is reloaded with new data from the reload
register at the next reload time. The counter can be read at any time.
Count is started by setting the count start bit to “1”. Data write and
read are performed in the same way as for normal event counter
mode. Note that the direction register of the input port must be set to
input mode because two kinds of pulse signals, described above, are
input. Also, there can be no pulse output in this mode.
Two-phase pulse processing
In event counter mode, whether to increment or decrement the
counter can also be determined by supplying two kinds of pulses of
which phases differ by 90° to timer A2, A3, orA4. There are two types
of two-phase pulse processing operations. One uses timers A2 and
A3, and the other uses timer A4. In both processing operations, two
pulses described above are input to the TAjOUT (j = 2 to 4) pin and
TAjIN pin respectively.
Addresses
imer A2 mode register
er A3 mode register
A4 mode register
5816
5916
5A16
When timers A2 and A3 are used, as shown in Figure 25, the count is
incremented when a rising edge is input to the TAkIN pin after the
level of TAkOUT(k=2,3) pin changes from “L” to “H”, and when the fall-
ing edge is input, the count is decremented.
7
×
6
×
5
0
4
1
3
0
2
0
1
0
0
1
: Always “01” in event counter mode
For timerA4, as shown in Figure 26, when a phase-related pulse with
a rising edge input to the TA4IN pin is input after the level of TA4OUT
pin changes from “L” to “H”, the count is incremented at the respec-
tive rising edge and falling edge of the TA4OUT pin and TA4IN pin.
When a phase-related pulse with a falling edge input to the TA4OUT
pin is input after the level of TA4IN pin changes from “H” to “L”, the
count is decremented at the respective rising edge and falling edge
of the TA4IN pin and TA4OUT pin. When performing this two-pha
pulse signal processing, timer Aj mode register bit 0 and bit 4
0 1 0 0 : Always “0100” when processing
two-phase pulse signal
× × : Not used in event counter mode
7 Timer Aj mode register bit configuration when performing
two-phase pulse signal processing in event counter mode
TAkOUT
TAkIN
(k = 2, 3)
Increment-
count
Increent- Decrement- Decrement-
cont count count
Decrement-
count
Fig. 25 Two-phase pulse processing operation of timers A2 and timer A3
TA4OUT
Increment-count at each edge
Decrement-count at each edge
TA4IN
Increment-count at each edge
Decrement-count at each edge
Fig. 26 Two-phase pulse processing operation of timer A4
28
MITSUBISHI MICROCOMPUTERS
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(3) One-shot pulse mode [10]
Figure 28 shows the bit configuration of the timer Ai mode register
during one-shot pulse mode. In one-shot pulse mode, bit 0 and bit 5
must be “0” and bit 1 and bit 2 must be “1”.
The trigger is enabled when the count start bit is “1”. The trigger can
be generated by software or it can be input from the TAiIN pin. Soft-
ware trigger is selected when bit 4 is “0” and the input signal from the
TAiIN pin is used as the trigger when it is “1“.
Addresses
5616
5716
5816
5916
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
7
6
5
0
4
3
2
1
1
1
0
0
5A16
Bit 3 is used to determine whether to trigger at the fall of the trigger
signal or at the rise. The trigger is at the fall of the trigger signal when
bit 3 is “0” and at the rise of the trigger signal when it is “1”.
Software trigger is generated by setting the bit in the one-shot start
bit corresponding to each timer.
1 0 : Always “10” in one-shot pulse mode
1 : Always “1” in one-shot pulse mode
0 × : Software trigger
1 0 : Trigger at the falling edge of TAiIN
input
igger at the rising edge of TAiIN
ays “0” in one-shot pulse mode
Figure 29 shows the bit configuration of the one-shot start register.
As shown in Figure 30, when a trigger signal is received, the counter
counts the clock selected by bits 6 and 7.
If the contents of the counter is not 000016, the TAiOUT pin goes “H”
when a trigger signal is received. The count direction is decrement.
When the counter reaches 000116, The TAiOUT pin goes “L” and
count is stopped. The contents of the reload register is transferred to
the counter. At the same time, an interrupt request signal is gener-
ated and the interrupt request bit in the timer Ai interrupt control reg-
ister is set. This is repeated each time a trigger signal is received.
The output pulse width is
ck source select
0 : Select Pf2
0 1 : Select Pf16
1 0 : Select Pf64
1 1 : Select Pf512
1
pulse frequency of the selected clock
× (counter’s value at the time of trig
Fig. 28 Timer Ai mode register bit configuration during one-shot
pulse mode
If the count start flag is “0”, TAiOUT goes “L”. Therefore,
corresponding to the desired pulse width must be writt
before setting the timer Ai count start bit.
As shown in Figure 31, a trigger signal can be rre the
operation for the previous trigger signal is cthis case,
the contents of the reload register is transfounter by the
trigger and then that value is decreme
Except when retriggering while opentents of the reload
register is not transferred to the iggering.
When retriggering, there must be st one timer count source
cycle before a new trigger can be issued.
Address
4216
7
6 5 4 3 2 1 0
One-shot start register
Timer A0 one-shot start bit
Timer A1 one-shot start bit
Timer A2 one-shot start bit
Timer A3 one-shot start bit
Timer A4 one-shot start bit
Data write is performed in the same way as for timer mode.
When data is written in timer Ai halted, it is also written to the reload
register and the counter.
When data is written to timer Ai which is busy, the data is written to
the reload register, but not to the counter. The counter is reloaded
with new data from the reload register at the next reload time.
Undefined data is read when timer Ai is read.
Fig. 29 One-shot start register bit configuration
29
MITSUBISHI MICROCOMPUTERS
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Selected clock
source Pfi
TAiIN
(rising edge)
TAiOUT
Example when the contents of the reload register is 000316
Fig. 30 Pulse output example when external rising edge is selected
Selected clock
source Pfi
TAiIN
(rising edge)
TAiOUT
Exampntents of the reload register is 000416
Fig. 31 Example when trigger is reduring pulse output
30
MITSUBISHI MICROCOMPUTERS
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function as the 8-bit length pulse width modulator. The prescaler
(4) Pulse width modulation mode [11]
Figure 32 shows the bit configuration of the timer Ai mode register
during pulse width modulation mode. In pulse width modulation
mode, bits 0, 1, and 2 must be set to “1”.
counts the clock selected by bits 6 and 7. A pulse is generated
when the counter reaches 000016 as shown in Figure 34. At the
same time, the contents of the reload register is transferred to the
counter and count is continued.
Bit 5 is used to determine whether to perform 16-bit length pulse
width modulator or 8-bit length pulse width modulator. 16-bit length
pulse width modulator is selected when bit 5 is “0” and 8-bit length
pulse width modulator is selected when it is “1”. The 16-bit length
pulse width modulator is described first.
The pulse width modulator can be started with a software trigger or
with an input signal from a TAiIN pin (external trigger).
The software trigger mode is selected when bit 4 is “0”.
Pulse width modulator is started and a pulse is output from TAiOUT
when the timer Ai start bit is set to “1”.
Addresses
Timer A0 mode register
Timer A1 mode register
imer A2 mode register
er A3 mode register
A4 mode register
5616
5716
5816
5916
5A16
The external trigger mode is selected when bit 4 is “1”.
Pulse width modulation starts when a trigger signal is input from the
TAiIN pin when the timer Ai start bit is “1”. Whether to trigger at the
fall or rise of the trigger signal is determined by bit 3. The trigger is at
the fall of the trigger signal when bit 3 is “0” and at the rise when it is
“1”.
7
6
5
4
3
2
1
1
1
0
1
: Always “11” in pulse width modulation
mode
1 : Always “1” in pulse width modulation
mode
When data is written to timer Ai with the pulse width modulator
halted, it is written to the reload register and the counter.
Then when the timer Ai start bit is set to “1” and a software trigger or
an external trigger is issued to start modulation, the waveform shown
in Figure 33 is output continuously.
0 × : Software trigger
1 0 : Trigger at the falling of TAiIN input
1 1 : Trigger at the rising of TAiIN input
0 : 16-bit pulse width modulator
1 : 8-bit pulse width modulator
Once modulation is started, triggers are not accepted. If the value in
the reload register is m, the duration “H” of pulse is
Clock source select bit
0 0 : Select Pf2
0 1 : Select Pf16
1 0 : Select Pf64
1 1 : Select Pf512
1
× m
selected clock frequency
and the output pulse period is
1
× (21
selected clock frequency
An interrupt request signal is generaterrupt request bit
in the timer Ai interrupt control regisach fall of the output
pulse.
Fig. 32 Timer Ai mode register bit configuration during pulse width
modulation mode
The width of the output pulse is chay updating timer data. The
update can be performed at any time. The output pulse width is
changed at the rise of the pulse after data is written to the timer.
The contents of the reload register are transferred to the counter just
before the rise of the next pulse so that the pulse width is changed
from the next output pulse.
Undefined data is read when timer Ai is read.
The 8-bit length pulse width modulator is described next.
The 8-bit length pulse width modulator is selected when the timer Ai
mode register bit 5 is “1”.
The reload register and the counter are both divided into 8-bit halves.
The low-order 8 bits function as a prescaler and the high-order 8 bits
31
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Therefore, if the low-order 8 bits of the reload register are n, the pe-
high-order 8 bits of the reload register are m, the duration “H” of pulse
is
riod of the generated pulse is
1
× (n+1) × m.
1
selected clock frequency
× (n+1).
selected clock frequency
The high-order 8 bits function as an 8-bit length pulse width modula-
tor using this pulse as input. The operation is the same as for 16-bit
length pulse width modulator except that the length is 8 bits. If the
And the output pulse period is
1
× (n+1) × (28–1).
selected clock frequency
16
1/Pfi × (2 – 1)
Selected clock
source Pfi
TAiIN
(rising edge)
This trigger is not accepted
1/Pfi × (m)
TAiOUT
Example when the conoad register is 000316
Fig. 33 16-bit length pulse width modulator output pulse e
8
1/Pfi × (n + 1) × (2 – 1)
Selected clock
source Pfi
TAiIN
(falling edge)
1/Pfi × (n + 1)
Prescaler output
(when n = 2)
1/Pfi × (n + 1) × (m)
8-bit length pulse
width modulator
output
(when m = 2)
Fig. 34 8-bit length pulse width modulator output pulse example
32
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As shown in Figure 19, the timer Bi count start bit is at the same ad-
dress as the timer Ai count start bit. The count is decremented, an
TIMER B
Figure 35 shows a block diagram of timer B.
interrupt occurs, and the interrupt request bit in the timer Bi interrupt
control register is set when the contents becomes 000016. At the
same time, the contents of the reload register is stored in the counter
and count is continued.
Timer B has three modes: timer mode, event counter mode, and
pulse period measurement/pulse width measurement mode. The
mode is selected with bits 0 and 1 of the timer Bi mode register (i=0
to 2). Each of these modes is described below.
(1) Timer mode [00]
Figure 36 shows the bit configuration of the timer Bi mode register
during timer mode. Bits 0 and 1 of the timer Bi mode register must
always be “0” in timer mode.
Timer Bi does not have a pulse output function or a gate function like
timer A.
When data is written to timer Bi halted, it is written to the reload reg-
ister and the counter. When data is written to timer Bi which is busy,
the data is written to the reload register, but not to the counter. The
new data is reloaded from the reload register to the counter at the
next reload time and counting continues.
Bits 6 and 7 are used to select the clock source. The counting of the
selected clock starts when the count start bit is “1” and stops when
“0”.
The contents of the counter can be read at any time.
Data bus
D
8 bits)
(Higher 8 bits)
Clock source selection
• Timer
Pf2
• Pulse period measurement/Pulse
width measurement
ad register (16)
Pf16
Pf64
Pf512
Addresses
Counter (16)
Timer B0 5116 5016
Timer B1 5316 5216
Timer B2 5516 5416
Polarity selection
and edge pulse
generator
Event counter
TBiIN
(i = 0 – 2)
start bit
(4016)
Counter reset
circuit
Note: Perform write and read Bi register in the condition of 16-bit data length : data length flag (m) =“0”.
Fig. 35 Timer B block diagram
33
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(2) Event counter mode [01]
Addresses
5B16
Figure 37 shows the bit configuration of the timer Bi mode register
during event counter mode. In event counter mode, bit 0 in the timer
Bi mode register must be “1” and bit 1 must be “0”.
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
5C16
5D16
The input signal from the TBiIN pin is counted when the count start
flag is “1” and counting is stopped when it is “0”.
7
6
5
×
4
3
×
2
×
1
0
0
0
Count is performed at the fall of the input signal when bits 2, and 3
are “0” and at the rise of the input signal when bit 3 is “0” and bit 2 is
“1”.
0 0 : Always “00” in timer mode
× × : Not used in timer mode and
may be any
Not used in timer mode
Clock source select bit
0 0 : Select Pf2
When bit 3 is “1” and bit 2 is “0”, count is performed at the rise and
fall of the input signal.
Data write, data read and timer interrupt are performed in the same
way as for timer mode.
0 1 : Select Pf16
1 0 : Select Pf64
(3) Pulse period measurement/pulse width
measurement mode [10]
1 1 : Select Pf512
Figure 38 shows the bit configuration of the timer Bi mode register
during pulse period measurement/pulse width measurement mode.
In pulse period measurement/pulse width measurement mode, bit 0
must be “0” and bit 1 must be “1”. Bits 6 and 7 are used to select the
clock source. The selected clock is counted when the count start flag
is “1” and counting stops when it is “0”.
Fig. 36 Timer Bi mode rt configuration during timer mode
Addresses
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
5B16
5C16
5D16
The pulse period measurement mode is selected when bit 3 is “0”. In
pulse period measurement mode, the selected clock is counted dur-
ing the interval starting at the fall of the input signal from the TBiIN pin
to the next fall or at the rise of the input signal to the next rise; the
result is stored in the reload register. In this case, the reload register
acts as a buffer register.
2
1
0
0
1
0 1 : Always “01” in event counter
mode
0 0 : Count at the falling edge of
input signal
0 1 : Count at the rising edge of
input signal
1 0 : Count at the both falling edge
and rising edge of input signal
When bit 2 is “0”, the clock is counted from the fall of the input
to the next fall. When bit 2 is “1“, the clock is counted from
the input signal to the next rise.
In the case of counting from the fall of the input signfall,
counting is performed as follows. As shown in Fen the
fall of the input signal from TBiIN pin is detectnts of the
counter is transferred to the reload rege counter is
cleared and count is started from the nen the fall of the
next input signal is detected, the che counter is trans-
ferred to the reload register onccounter is cleared, and
the count is started. The period from ll of the input signal to the
next fall is measured in this way.
× × × : Not used in event counter mode
Fig. 37 Timer Bi mode register bit configuration during event
counter mode
Addresses
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
5B16
5C16
5D16
After the contents of the counter is transferred to the reload register,
an interrupt request signal is generated and the interrupt request bit
in the timer Bi interrupt control register is set. However, no interrupt
request signal is generated when the contents of the counter is trans-
ferred first to the reload register after the count start bit is set to “1”.
When bit 3 is “1”, the pulse width measurement mode is selected.
Pulse width measurement mode is the same as the pulse period
measurement mode except that the clock is counted from the fall of
the TBiIN pin input signal to the next rise or from the rise of the input
signal to the next fall as shown in Figure 40.
7
6
5
4
3
2
1
1
0
0
1 0 : Always “10” in pulse period
measurement/pulse width
measurement mode
0 0 : Count from the falling edge of
input signal to the next falling one
0 1 : Count from the rising edge of
input signal to the next rising one
1 0 : Count from the falling edge of
input signal to the next rising one
and from the rising edge to the
next falling one
Timer Bi overflow flag
Clock source select bit
0 0 : Select Pf
2
0 1 : Select Pf16
1 0 : Select Pf64
1 1 : Select Pf512
Fig. 38 Timer Bi mode register bit configuration during pulse period
measurement/pulse width measurement mode
34
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When timer Bi is read, the contents of the reload register is read.
Note that in this mode, the interval between the fall of the TBiIN pin
input signal to the next rise or from the rise to the next fall must be at
least two cycles of the timer count source.
Timer Bi overflow flag which is bit 5 of timer Bi mode register is set to
“1” when the timer Bi counter reaches 000016, which indicates that a
pulse width or pulse period is longer than that which can be mea-
sured by a 16-bit length.
This flag is cleared by writing data to the corresponding timer Bi
mode register. This bit is set to “1”at reset.
Selected clock
source Pfi
TBiIN
Reload register ← counter
Counter ← 0
Count start flag
Interrupt request signal
Fig. 39 Pulse period measurement mode xample of measuring the interval between the falling edge to next falling one)
Selected cloc
source Pfi
TBiIN
Reload register ← counter
Counter ← 0
Count start flag
Interrupt request signal
Fig. 40 Pulse width measurement mode operation
35
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7
6
5
×
4
3
2
1
1
0
0
0
Timer function for motor control
Three-phase motor drive waveform and pulse motor drive waveform
can be output by using plural internal timers A and B. Those modes
are explained bellow.
Address
1A16
Waveform output mode register
Waveform output select bits
100 : Fix to “100” in three-phase
waveform mode
(Valid in three-phase mode 1)
Three-phase output polarity set buffer
0 : “H” output
1 : “L” output
Three-phase motor drive waveform output
mode (three-phase waveform mode)
Three-phase waveform mode using four timers of the timers A0, A1,
A2 and B4 is selected by setting the waveform output select bits of
the waveform output mode register (address 1A16, Figure 41) to
“1002”.
Three-phase mode select bit
0 : Three-phase mode 0
1 : Three-phase mode 1
Not used in three-phase
waveform mode
There are two types of the three-phase waveform mode: three-
phase mode 0 and three-phase mode 1. Bit 4 of the waveform out-
put mode register selects either mode. In three-phase waveform
mode, set the corresponding timer mode registers of timers A0, A1,
and A2 to select the one-shot pulse mode with the rising edge of ex-
ternal trigger; set the timer mode register of timer B2 to select the
timer mode.
ead-time timer trigger select bit
Both edge of one-shot pulse
h timers A2 to A0
nly the falling edge of one-shot
pulse with timers A2 to A0
Waveform output control bit
0 : Waveform output disabled
1 : Waveform output enabled
Figure 43 shows the three-phase waveform mode block diagram.
The three-phase waveform mode outputs six waveforms, positive
_
_ __
waveforms (U, V, W phases) and negative waveforms (U, V, W
phases), from the respective ports with “L” level active.
Nn bit 5 of the particular function select register 1
. 15) is set to “1”, this register’s contents can be changed
m the status during reset (in Fig.76).
_
_
Timer A2 controls U and U phases; timer A1 does V and V phases
__
and timer A0 does W and W phases. Timer B2 controls those one-
shot pulses’ period of timers A2, A1 and A0.
1 Waveform output mode register bit configuration
In the waveform output, a short circuit prevention time can be s
prevent “L” level of positive waveforms (U, V, W phases) fro
_ _ __
Address
7
6
5
0
4
1
3
1
2
1
1
0
0
Timer A0 mode register 5616
Timer A1 mode register 5716
Timer A2 mode register 5816
lapping with “L” level of their negative waveforms (U, V,
The short circuit prevention time can be set with thrd-
time timers, sharing one reload register. The deaoper-
ates as a one-shot timer. As its start trigger, botd falling
edges of timers A0 to A2’s one-shot pulses edge. Bit 6
of the waveform output mode register hen that is “0”,
both the rising and falling edges bectrigger; when that
is “1”, the falling edge becomes it
Fix to “10” in three-phase
waveform mode
Fix to “1” in timers A0, A1
in timer A2
0 : No one-shot pulse output
1 : One-shot pulse output
Fix to “011” in three-phase
waveform mode
Clock source select bit
0 0 : Select Pf2
0 1 : Select Pf16
1 0 : Select Pf64
1 1 : Select Pf512
7
6
5
×
4
3
×
2
×
1
0
0
0
Address
5D16
Timer B2 mode register
Fix to “00” in three-phase
waveform mode
Not used in three-phase
waveform mode
Clock source select bit
0 0 : Select Pf2
0 1 : Select Pf16
1 0 : Select Pf64
1 1 : Select Pf512
Fig. 42 Timer A0, A1, A2, mode register and timer B2 mode regis-
ter bit configuration
36
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s
s
Fig. 43 Three-phase waveform mode block diagram
37
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When writing data to the dead-time timer (address 1B16), the data is
In the three-phase waveform mode, setting bit 7 of the waveform out-
written to the reload register shared by three dead-time timers.
When the dead-time timers catch the start trigger from the respec-
tive timers, the reload register contents are transferred to its counter
and the dead-time timer decrements with the clock source selected
by bits 6 and 7 of pulse output data register (address 1C16). Addition-
ally, this timer can accept another trigger before completion of the
preceding trigger operation. In this case, after transferring the reload
register contents to the dead-time timer at acceptance of the trigger,
the value is decremented.
put mode register (address 1A16) to “1” makes positive waveforms
_ _ __
(U, V, W phases) and their negative waveforms (U, V, W phases)
output from the respective ports. When that bit is “0”, their ports are
____
floating. That bit is cleared to “0” by inputting falling edge to the INT0
pin or reset other than clearing by an instruction..
Additionally, setting bits 5 to 3 of the pulse output data register 1 (ad-
dress 1C16) to “1” makes the corresponding positive waveforms
fixed to “H”, and setting bits 7 to 5 of the pulse output data register 0
(address 1D16) to “1” makes the corresponding negative waveforms
The dead-time timer operates as a one-shot timer. Accordingly, this
timer starts pulse output when the trigger is caught, and finishes
pulse output and stops operation when its contents become “0016”,
and waits next trigger.
fixed to “H”.
____
When selecting the three-phase waveform mode, INT0 pin become
input-only pin.
7
6
5
4
3
2
×
1
7
6
5
4
3
2
×
1
0
Address
1D16
Address
1C16
Pulse output data register 1
e output data register 0
V-phase output polarity set buffer
(Three-phase mode 0)
0 : “H” output
✕ : Not used in three-phase waveform mode
(Valid in three-phase mode 0)
W-phase output polarity set buffer
0 : “H” output
1 : “L” output
Interrupt request interval set bit
(Three-phase mode 1)
0 : At every second time
1 : At every fourth time
1 : “L” output
“H” output of W-phase fix buffer
0 : Released from fixed output
1 : “H” output fixed
U-phase output polarity set buffer
(Three-phase mode 0)
0 : “H” output
1 : “L” output
Interrupt validity output select bit
(Three-phase mode 1)
0 : Timer B2 interrupt requeeach
even-numbered unde.
1 : Timer B2 interrupt ed at each
odd-numbered uer B2.
“H” output of V-phase fix buffer
0 : Released from fixed output
1 : “H” output fixed
“H” output of U-phase fix buffer
0 : Released from fixed output
1 : “H” output fixed
✕ : Not usewaveform mode
Note : Only when bit 5 of the particular function select register 1 (in Fig. 15)
is set to “1”, these registers’ contents can be changed from the status
during reset (in Fig.76).
“H” oue fix buffer
0 : Refixed output
1 : “H” oed
“H” output of V-phase fix buffer
0 : Released from fixed output
1 : “H” output fixed
“H” output of U-phase fix buffer
0 : Released from fixed output
1 : “H” output fixed
Clock-source-of-dead-time timer select bits
00 : Pf
01 : Pf
10 : Pf
2
4
8
selected
selected
selected
11 : Do not select.
Fig. 44 Bit configuration of pulse output data registers 1 and 0 in three-phase waveform mode
38
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Three-phase mode 0
Then, write “1” to the U-phase output polarity set buffer (bit 1 at ad-
In selecting three-phase waveform mode, three-phase mode 0 is se-
lected by setting bit 4 of the waveform output mode register (address
1A16) to “0”.
dress 1C16) before the counter of timer B2 becomes 000016.
After that, when the counter of timer B2 becomes 000016, the
timer A2 starts one-shot pulse output. Simultaneously, the con-
tents of U-phase output polarity set buffer, “1” in this case, are set
into the output polarity set toggle flip-flop 2 and the U phase wave-
form remains “L” level.
The output polarity of three-phase waveform depends on the output
polarity set toggle flip-flop. The positive waveform of the three-phase
waveform is “H” output when the toggle flip-flop is “0”; it is “L” output
when the toggle flip-flop is “1”. (Three-phase waveform is output as
a negative waveform.)
When the one-shot pulse output of timer A2 is completed, the con-
tents of output polarity set toggle flip-flop 2 is reversed from “1” to
“0”. Simultaneously, the one-shot pulse output of the dead-time
timer starts.
Each output polarity set toggle flip-flop has the output polarity set
buffer shown in Figure 44. When the timer B2’s counter contents be-
come 000016, the contents of output polarity set buffer are set into
the output polarity set toggle flip-flop. After that, the polarity of the
contents of output polarity set toggle flip-flop are reversed each time
completion of one-shot pulse of timer (timers A2 to A0) correspond-
ing to each phase.
When the contents of output polarity set toggle flip-flop 2 are re-
versed from “1” to “0”, the U-phase waveform changes its output
level from “L” to “H” without waiting for completion of the one-shot
pulse output of the dead-timtimer.
U-phase waveform is ged by repeating the operation
Figure 45 shows an example of U-phase waveform and the output
operation is explained. Three-phase mode 0 becomes valid when
writing “0” to the U-phase output polarity set buffer (bit 1 at address
1C16) and actuating the timer B2. When the counter of timer B2 be-
comes 000016, the timer B2 interrupt request signal occurs and the
timer A2 simultaneously starts one-shot pulse output. At this time,
the contents of U-phase output polarity set buffer, “0” in this case, are
set into the output polarity set toggle flip-flop 2.
above. The way to ghase waveform, which is the
negative phase of e same as that for U-phase wave-
form except thas of output polarity set toggle flip-flop
2 are treateersed signal from the case of U-phase
wavefor
_
In thise waveform and U-phase waveform, having
thhase of U-phase, are output from the pins so that
ls do not overlap each other. The width of “L” level can
modified by changing the value of timer B2 or timer A2.
When the one-shot pulse output of timer A2 is completed, the con-
tents of output polarity set toggle flip-flop 2 is reversed from “0” to “1
Simultaneously, the one-shot pulse of the 8-bit dead-time tim
_
__
-phase waveform and V-, W-phase waveform, having their
egative phase, are similarly output according to the correspond-
ing timer operation.
output for ensuring time not to overlap “L” levels of U phas
_
form and its negative U phase waveform.
The explanation above is an example of three-phase waveform
generating due to an triangular wave modulation. Three-phase
waveform due to a saw-tooth-wave modulation can also be gen-
erated by fixing each beginning level of phases.
The U-phase waveform output keeps “H” level from the
one-shot pulse output of the dead-time timer is cen if
the contents of output polarity set toggle flip-floed from
“0” to “1” owing to the timer A2’s one-shot . When the
one-shot pulse output of the dead-time mpleted, “1” of
output polarity set toggle flip-flop 2 een reversed be-
comes valid and the U phase waves to “L” level.
Signal output each time
Timer B2 becomes 000016
One-shot pulse output
with timer A2
Contents of output polarity
set toggle flip-flop 2
Reversed pulse output
signal with dead-time timer
U-phase waveform output
U-phase waveform output
Fig. 45 U-phase waveform output example in three-phase mode 0 (triangular wave modulation)
39
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Three-phase mode 1
After the procedure above, three-phase mode 1 starts operation
In selecting three-phase waveform mode, three-phase mode 1 is
selected by setting bit 4 of the waveform output mode register (ad-
dress 1A16) to “1”.
when actuating the timer B2.
When the counter of timer B2 becomes 000016, the timer B2 inter-
rupt request occurs and timer A2 simultaneously starts one-shot
pulse output. At this time, the contents of three-phase output polarity
set buffer, “0” in this case, are set into the output polarity set toggle
flip-flop 2. The contents of three-phase output polarity set buffer are
reversed from “0” to “1” after that operation.
In this mode, each of timers A0 to A2 can have two timer registers
and the contents of those registers are alternately reloaded into the
counter each time the counter of timer B2 becomes 000016. About
write operation to two timer registers, when rewriting to each timer
register of timers A0, A1 and A2 after writing to each timer register of
them, the data is written each to timers A01, A11 andA21. When writ-
ing to each timer register, the timer A write register (in Figure 46) in-
dicates the timer to be intended for write.
When the timerA2 counter counts the value written into the timer A2
and the one-shot pulse output of timer A2 is completed, the contents
of output polarity set toggle flip-flop 2 are reversed from “0” to “1”. Si-
multaneously, the one-shot pulse of the 8-bit dead-time timer is out-
__
The interrupt request normally occurs when the counter of timer B2
becomes 000016. However, this occurrence interval can be switched
between “every second time” and “every fourth time.” Bit 0 of the
pulse output data register 1 (address 1C16) selects that.
Additionally, “0” or “1” of the three-phase output polarity set buffer
can be used as the occurrence factor of timer B2 interrupt request.
Bit 1 of the pulse output data register 1 (address 1C16) selects that.
When the timer B2’s counter contents become 000016, the contents
of three-phase output polarity set buffer are set into the output polar-
ity set toggle flip-flop on which .the output polarity of three-phase
waveform depends. The contents of three-phase output polarity set
buffer are reversed after that operation.
put for ensuring time, so that “L” levels of U- and U-phase waveforms
do not overlap.
7
6
0
Address
Timer A write register 4516
Timer A0 write bit
0 : Write to timer A0
1 : Write to timer A0
1
1
1
The polarity of the contents of output polarity set toggle flip-flop is re-
versed each time completion of one-shot pulse of timer (timers A2 to
A0) corresponding to each phase.
Timer A1 write bit
0 : Write to timer A1
1 : Write to timer A1
Figure 47 shows an example of U-phase waveform and the
operation is explained.
Timer A2 write bit
0 : Write to timer A2
1 : Write to timer A2
Write “0” to the three-phase output polarity set buffe-
dress 1A16). Clear the interrupt request interval sad-
dress 1C16) to “0” so that the timer B2 interrupt roccur at
every second time. Additionally, clear the intoutput se-
lect bit (bit 1 at address 1C16) so that the errupt request
may occur at “0” of the three-phase oset buffer.
Note : Only when bit 5 of the particular function select register 1 (in Fig. 15)
is set to “1”, this register’s contents can be changed from the status
after reset (in Fig.76).
Fig. 46 Timer A write flag bit configuration
Timer B2 interrupt request
signal
Signal output each time
Timer B2 becomes 000016
One-shot pulse output with
n1
n1
n2
n2
n3
n3
n4
n5
n5
n6
n7
timer A2
Timer A2
Timer A2
1
n4
n6
n8
Contents of output polarity
set toggle flip-flop 2
Reversed pulse output
signal with dead-time timer
U-phase waveform output
U-phase waveform output
Fig. 47 U-phase waveform output example in three-phase mode 1 (triangular wave modulation)
40
MITSUBISHI MICROCOMPUTERS
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M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The U-phase waveform output keeps “H” level from the start until the
one-shot pulse output of the dead-time timer is completed, even if
the contents of output polarity set toggle flip-flop 2 are reversed from
“0” to “1” owing to the timer A2’s one-shot pulse output.
When the one-shot pulse output of the dead-time timer is completed,
“1” of output polarity set toggle flip-flop 2 which has been reversed
becomes valid and the U-phase waveform changes to “L” level.
Then, when the counter of timer B2 becomes 000016, the timer A2
counter counts the value written into timer A2 and timer A2 starts
one-shot pulse output. Simultaneously, the contents of three-phase
output polarity set buffer are set into the output polarity set toggle
flip-flop 2. However, the U-phase waveform remains “L” level, be-
cause the value is the same (“1”).
The contents of three-phase output polarity set buffer are reversed
from “1” to “0” after that operation.
When the one-shot pulse output of timer A2 is completed, the con-
tents of output polarity set toggle flip-flop 2 is reversed from “1” to “0”.
Simultaneously, the one-shot pulse output of the dead-time timer
starts.
When the contents of output polarity set toggle flip-flop 2 is reversed
from “1” to “0”, the U-phase waveform changes its output level from
“L” to “H” without waiting for completion of the one-shot pulse output
of the dead-time timer.
U-phase waveform is generated by repeating the operation above.
_
The way to generate U-phase waveform, which is the negative
phase of U-phase, is the same as that for U-phase waveform excep
that the contents of output polarity set toggle flip-flop 2 is treate
the reversed signal from the case of U-phase waveform.
_
In this way, U-phase waveform and U-phase waveform,
negative phase of U-phase, are output from the pins s”
levels do not overlap each other. The width of “L” also
modified by changing the value of timer B2, timr A21.
_
__
V-, W-phase waveform and V-, W-phase aving their
negative phase, are similarly output acccorresponding
timer operation.
41
MITSUBISHI MICROCOMPUTERS
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M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pulse output port mode
Set timersA1 and A0 to the timer mode because they are used in the
Figure 48 shows the pulse output port mode block diagram.
This mode has an 8-bit pulse output port. The waveform output se-
lect bits (bits 0 to 2) of waveform output mode register (address
1A16, Figure 49) select use of pulse output port. The 8-bit pulse out-
put port is divided into 4 bits and 4 bits, or 6 bits and 2 bits with the
pulse output mode select bit (bit 4) of pulse output data register 1
(address 1C16, Figure 51) ; each of them can be individually con-
trolled.
pulse output mode. Additionally, set bit 2 of the corresponding timer
Ai mode register to “1” to use a pulse output port because the pulse
output port are multiplexed with the TAiOUT (i = 0 to 4). Figure 50
shows the bit configuration of timer A1 and A0 mode registers in the
pulse output port mode.
Timers A1 and A0 start count when setting the corresponding timer
count start flag to “1”, and they stop it when clearing that flag to “0”.
Pulse width modulation Pulse width modulation
select bit 1
select bit 0
Pulse width modulation
output of timer A4
Pulse width modulation
output of timer A3
Pulse width modulation
output of timer A2
Timer A1
Pulse width modulation data bit
T
D15
D14
D13
D Q
Waveform output control bit 0
D Q
D Q
D Q
R
Reset
Pulse output data register 1
D3
RTP13
RTP12
RTP11
RTP10
Q
D Q
Pulse output mod
select bit
T
D11
D10
D Q
RTP03
RTP02
D Q
D Q
D9
D8
RTP01
RTP00
Q
D
T
Waveform output control bit 0
D Q
Pulse output data register 0
Timer A0
Polarity select bit
R
Reset
Note : Only when bit 5 of the particular function select register 1 (in Fig. 15) is set to “1”, the following registers’ contents can be changed from the
status after reset (in Fig.76) : Waveform output mode register (address 1A16) and Pulse output data registers 0 and 1 (addresses 1C16, 1D16).
Fig. 48 Pulse output port mode block diagram
42
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pulse mode 0
7
6
5
4
3
2
1
0
Address
This mode divides a pulse output port into 4 bits and 4 bits and indi-
Waveform output mode register 1A16
vidually controls them.
Waveform output select bits
000 : Parallel port
When setting the pulse output mode select bit to “0”, and setting bits
2 and 1 to “0” and bit 0 to “1” of the waveform output select bits, four
of RTP13, RTP12, RTP11, and RTP10 become the pulse output
ports with RTP1 selected.
001 : RTP1 selected
(Valid in pulse mode 0)
010 : RTP0 selected
(Valid in pulse mode 0)
011 : In pulse mode 0
RTP1 and RTP0 selected
In pulse mode 1
When setting the pulse output mode select bit to “0”, and setting bits
2 and 0 to “0” and bit 1 to “1” of the waveform output select bits, four
of RTP03, RTP02, RTP01, RTP00 become the pulse output ports
with RTP0 selected.
RTP1, RTP0
3
, RTP0
2,
RTP0 , RTP0
1
0 selected
When setting the pulse output mode select bit to “0”, and setting bit
2 to “0” and bits 1 and 0 to “1” of the waveform output select bits,
the following two groups become the pulse output ports with RTP1
and RTP0 selected:
Polarity select bit
(Valid for RTP0 in pulse mode 0)
0 : Positive polarity
1 : Negative polarity
•Four of RTP13, RTP11, RTP10
Pulse width modulation select bit 0
(Valid for RTP1 in pulse mode 0;
•Four of RTP03, RTRTP00.
Valid for RTP1, RTP0
pulse mode 1)
3, RTP02 in
Each time thf timer A1 counter become 000016, the
contents ut data register 1 (low-order 4 bits at address
1C16) g to RTP13, RTP12, RTP11, RTP10 are output
fro
0 : No modulation by timer A2
1 : Modulation by timer A2
Pulse width modulation select bit 1*
(Valid in pulse mode 1)
0 : Modulation by timer A2
e contents of timer A0 counter become 000016, the
of pulse output data register 0 (low-order 4 bits at address
corresponding to RTP03, RTP02, RTP01, RTP00 are output
m ports.
1 : Modulation for RTP0
by timer A2
3, RTP02
Modulation for RTP1
by timer A3
Modulation for RTP1
by timer A4
1
3
, RTP1
, RTP1
0
2
When writing “0” to the specified bit of pulse output data register, “L”
level is output from the pulse output port when the contents of cor-
responding timer counter become 000016; when writing “1” to it, “H”
level is output from the pulse output port.
* when selecting pulse mode 0, f
this bit to “0”.
Waveform output contro
0 : In pulse mode 0
Disable RTPtput
In pulse m
Disabl
outp
1 : In
waveform output
de 1
0 waveform
Address
Timer A0 mode register 5616
Timer A1 mode register 5716
7
6
5
0
4
0
3
×
2
1
1
0
0
0
100 : Fix to “100” in pulse output port mode
RTP0
t
1, RTP00 waveform
×
: Not used in pulse output port mode
Waveform output control bit 1
0 : In pulse mode 0
00 : Fix to “00” in pulse output port mode
Clock source select bit
00 : Pf2 selected
01 : Pf16 selected
10 : Pf64 selected
11 : Pf512 selected
Disable RTP1 waveform output
In pulse mode 1
Disable RTP1, RTP0
waveform output
3, RTP02
1 : In pulse mode 0
Enable RTP1 waveform output
In pulse mode 1
Fig. 50 Bit configuration of timer A1 and A0 mode registers in pulse
output port mode
Enable RTP1, RTP0
waveform output
3, RTP02
Note : Only when bit 5 of the particular function select register 1
(in Fig. 15) is set to “1”, this register’s contents can be
changed from the status after reset (in Fig.76).
Fig. 49 Bit configuration of waveform output mode register in pulse
output port mode
43
MITSUBISHI MICROCOMPUTERS
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M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Additionally, pulse width modulation can be applied for the pulse out-
The polarity select bit (bit 3) of waveform output mode register must
be “0” to select the positive polarity. The other operations are the
same as that of pulse mode 0. Figure 53 shows example waveforms
in the pulse mode 1.
put port RTP1. Because the timerA2 is used for pulse width modula-
tion, actuate timer A2 in the pulse width modulation mode. When any
bit of pulse output data is “1”, the pulse to which pulse width modula-
tion is applied is output from the pulse output port when the contents
of timer A1 counter become 000016.
In ports selecting the pulse mode 1, output of RTP01 and RTP00 is
controlled by the waveform output control bit 0 (bit 6) of waveform
output mode register; output of RTP13, RTP12, RTP11, RTP10,
RTP03 and RTP02 is done by the waveform output control bit 1
(bit 7).
Pulse width modulation by timer A2 is applied when setting the pulse
width modulation select bit 0 (bit 4) of waveform output mode regis-
ter to “1”, pulse width modulation select bit 1 (bit 5) to “0,” and the
pulse width modulation data bit of RTP1 (bit 5) of pulse output data
register 0 to “1”.
When setting the waveform output control bit to “1”, waveform is out-
put from the corresponding port. When clearing that bit to “0”, wave-
form output from the corresponding port stops and the port becomes
floating. The waveform output control bits are cleared to “0” by reset
other than clearing with instructions.
RTP03, RTP02, RTP01 and RTP00 can output the contents of pulse
output data register 0 by setting the polarity select bit (bit 3) of wave-
form output mode register. When the polarity select bit is “1”, the re-
versed contents of pulse output data register 0 is output; when that
bit is “0”, the contents of pulse output data register 0 are output as it
is. Figure 52 shows example waveforms in the pulse mode 0.
In ports selecting the pulse mode 0, output of RTP03, RTP02, RTP01
and RTP00 is controlled by the waveform output control bit 0 (bit 6)
of waveform output mode register; output of RTP13, RTP12, RTP11
and RTP10 is done by the waveform output control bit 1 (bit 7).
When setting the waveform output control bit to “1”, waveform is out-
put from the corresponding port. When clearing that bit to “0”, wave-
form output from the corresponding port stops, and the port
becomes floating. The waveform output control bits are cleared to “0”
by reset other than clearing with instructions.
Address
e output data register 1
7
×
6
×
5
×
4
3
2
1C16
RTP1
RTP1
RTP1
RTP1
0
1
2
3
pulse output data bit
pulse output data bit
pulse output data bit
pulse output data bit
Pulse output mode select bit
0 : Pulse mode 0
1 : Pulse mode 1
✕
: Not used in pulse output port mode
7
6
5
4
3
2
1
0
Address
Pulse output data register 0
Pulse mode 1
1D16
This mode divides a pulse output port into 6 bits and 2 i-
vidually controls them.
RTP0
RTP0
RTP0
RTP0
0
1
2
3
pulse output data bit
pulse output data bit
pulse output data bit
pulse output data bit
When setting the pulse output mode select bit ting bit 2
to “0” and bits 1 and 0 to “1” of the waveforect bits, the
following two groups become the pulse
In pulse mode 0
Pulse width modulation data bit of RTP1
In pulse mode 1
Pulse width modulation data bit of
•Six of RTP13, RTP12, RTP11, RTP1P02
•Two of RTP01, RTP00.
RTP03, RTP02
Timer A1 controls six of RTP13, P11, RTP10, RTP03, and
RTP02; timer A0 controls two of RRTP00.
In pulse mode 1
Pulse width modulation data bit of
Additionally, pulse width modulation can be applied for the pulse out-
put ports (RTP1, RTP03, RTP02). The pulse width modulation select
bit 1 (bit 5) of waveform output mode register selects the type of
modulation: the common modulation to six of RTP13, RTP12, RTP11,
RTP10, RTP03 and RTP02 or the modulation to every two ports of
RTP13 and RTP12, RTP11 and RTP10, RTP03 and RTP02.
When setting that bit to “0”, the common modulation to six ports is
applied; when setting that bit to “1”, the modulation to every two ports
is applied. The timer A2 is used for the common modulation to six
ports; the timers A2, A3 andA4 are used for the modulation to every
two ports. Accordingly, actuate the respective timers in the pulse
width modulation mode. When any bit of pulse output data is “1”, the
pulse to which pulse width modulation is applied is output from the
pulse output port when the contents of timer A1 counter become
000016.
RTP11, RTP10
In pulse mode 1
Pulse width modulation data bit of
RTP1 , RTP1
3
2
Note : Only when bit 5 of the particular function select register 1
(in Fig. 15) is set to “1”, this register’s contents can be
changed from the status after reset (in Fig.76).
Fig. 51 Bit configuration of pulse output data registers 1 and 0 in
pulse output port mode
Pulse width modulation by corresponding timers is applied when set-
ting the pulse width modulation select bit 0 of waveform output mode
register to “1” and the corresponding pulse width modulation data
bits (bits 7 to 5) of pulse output data register 0 to “1”.
44
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pulse outpu port (RTP1) example
Signal output each time
timer A1 becomes 000016
RTP13
RTP12
RTP11
RTP10
Example of pulse width modulation for above pulse output port using timer A2
Signal output each time
timer A1 becomes 000016
RTP13
RTP12
RTP11
RTP10
Pulse outpu port (RTP0) example in the case of pola“1”
Signal output each time
timer A0 becomes 000016
RTP03
RTP02
RTP01
RTP00
Fig. 52 Example waveforms in pulse mode 0
Pulsbits) example
Signal output each time
timer A1 becomes 000016
RTP13
RTP
RT
RTP03
RTP02
Example of pulse width modulation for above pulse output port using timer A2
Signal output each time
timer A1 becomes 000016
RTP13
RTP12
RTP11
RTP10
RTP03
RTP02
Fig. 53 Example waveforms in pulse mode 1
45
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(UART) serial I/O port using start and stop bits.
SERIAL I/O PORTS
Figures 56 and 57 show the connections of receiver/transmitter ac-
cording to the mode.
Two independent serial I/O ports are provided. Figure 54 shows a
block diagram of the serial I/O ports.
Figure 58 shows the bit configuration of the UARTi Transmit/Receive
control register.
Bits 0, 1, and 2 of the UARTi(i = 0,1) Transmit/Receive mode register
shown in Figure 55 are used to determine whether to use port P8 as
parallel port, clock synchronous serial I/O port, or asynchronous
Each communication method is described below.
Data bus(odd)
Data bus(even)
Bit converter
0
0
0
0
0
0
0 D8 D7 D6 D5 D4 D3 D2 D1 D0 Receive buffer register
UART0(3716,3616)
UART1(3F16,3E16)
RXDi
Receive regist
Receive clock
UART receive
Receive
control
circuit
1/16 Divider
Bit rate
generator
Clock synchronous
UART transmission
UART0(3116)
UART1(3916)
Internal
Clock source selection
Transm
1/16 Divider
Transmission
control circuit
Pf2
Clock synchronous
Pf16
Pf64
Pf512
Clock synchronous
TXDi
1/(n + 1)
Divider
(Internal clock)
nsmit register
1/2 Divider
External Clock synchronous
(Internal clock)
Clock synchronous
(External clo
CLKi
Transmit
buffer register
D8 D7 D6 D5 D4 D3 D2 D1 D0
UART0(3316,3216)
UART1(3B16,3A16)
CTSi/RTSi
Data bus
(odd)
Bit converter
Data bus(even)
Fig. 54 Serial I/O port block diagram
Addresses
3016
3816
7
6 5 4 3 2 1 0
UART ceive mode register
UART Receive mode register
Serial I/O moe select bit
0 0 0 : Parallel port
0 0 1 : Clock synchronous
1 0 0 : 7-bit UART
1 0 1 : 8-bit UART
1 1 0 : 9-bit UART
Internal/External clock select bit
0 : Internal clock
1 : External clock
Stop bit length select bit
0 : 1 stop bit
1 : 2 stop bits
Even/Odd parity select bit
0 : Odd parity
1 : Even parity
Parity enable select bit
0 : No parity
1 : With parity
Sleep select bit
0 : No sleep
1 : Sleep
Fig. 55 UARTi Transmit/Receive mode register bit configuration
46
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Data bus(odd)
Data bus(even)
Bit Converter
Receive buffer register
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
8bit
9bit
2 stop bit
Parity
7bit
8bit
9bit
9 bit
Synchronous
7 bit
RXDi
Stop
bit
Stop
bit
Parity
bit
No
parity
Receive register
1 stop bit
7bit
8bit
Synchronous
Synchronous
Fig. 56 Receiver block diagram
Data bus(odd)
Data bus(even)
verter
Transmit buffer register
D8
D7
D4
D3
D2
D1
D0
7bit
8bit
9
9bit
Synchr-
onous
2 stop bit
Parity 7bit
8bit
Parity
bit
TXDi
9bit
Stop
Stop
bit
“0”
bit
No
parity
7 bit
Transmit register
1 stop bit
“0”
us
Fig. 57 Transmitter block diagram
Addresses
7
6
5
4
3
UART 0 Transmit/Receive control register 0 3416
UART 1 Transmit/Receive control register 0 3C16
MSB/
LSB
0
BRG count source select bit
0 0 : Select Pf
2
0 1 : Select Pf16
1 0 : Select Pf64
1 1 : Select Pf512
CTS, RTS select bit
0 : Select CTS
1 : Select RTS
Transmit register empty bit
CTS, RTS enable bit
0 : Enable CTS, RTS
1 : Disable CTS, RTS (Input/Output port)
Transfer format select bit (Note)
0 : LSB first
Note : This bit is valid in clock synchronous mode.
Fix this bit to “0” in UART mode.
1 : MSB first
Addresses
7
6
5
4
3
2
1
0
UART 0 Transmit/Receive control register 1 3516
UART 1 Transmit/Receive control register 1 3D16
SUM PER FER OER RI
RE
TI
TE
Transmit enable flag
Transmit buffer empty flag
Receive enable flag
Receive complete flag
Overrun error flag
Framing error flag
Parity error flag
Error sum flag
Fig. 58 UARTi Transmit/Receive control register bit configuration
47
MITSUBISHI MICROCOMPUTERS
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transmission clock CLKj. Therefore, when the selected clock is Pfi,
CLOCK SYNCHRONOUS SERIAL COMMUNI-
CATION
Bit Rate = Pfi/ {(n+1)×2}
A case where communication is performed between two clock syn-
chronous serial I/O ports as shown in Figure 59 will be described.
(The transmission side will be denoted by subscript j and the receiv-
ing side will be denoted by subscript k.)
On the clock receiving side, the TCS0 and TCS1 bits of the UARTk
Transmit/Receive control register 0 are ignored because an external
clock is selected.
Bit 0 of the UARTj Transmit/Receive mode register and UARTk
Transmit/Receive mode register must be set to “1” and bits 1 and 2
must be “0”. The length of the transmission data is fixed at 8 bits.
Bit 3 of the UARTj Transmit/Receive mode register of the clock send-
ing side is cleared to “0” to select the internal clock. Bit 3 of the
UARTk Transmit/Receive mode register of the clock receiving side is
set to “1” to select the external clock. Bits 4, 5 and 6 are ignored in
clock synchronous mode. Bit 7 must always be “0”.
Bit 2 of the clock-sending-side UARTj Transmit/Receive control reg-
____
ister 0 is cleared to “0” to select CTSj input. Bit 2 of the clock receiv-
____
ing side is set to “1” to select RTSk output.
Bit 4 of the UART Transmit/Receive control register 0 is used to de-
____ ____
termine whether to use CTS or RTS signal. Bit 4 must be “0” when
____ ____
____
____
CTS or RTS signal is used. Bit 4 must be “1” when CTS and RTS sig-
____ ____ ____
nals are not used. When CTS and RTS signals are not used, CTS/
____ ____ ____
RTS pin can be used as a normal port. The case using CTS and RTS
____ ____
The clock source is selected by bit 0 (TCS0) and bit 1 (TCS1) of the
clock-sending-side UARTj Transmit/Receive control register 0. As
shown in Figure 54, the selected clock is divided by (n+1), then by 2,
is passed through a transmission control circuit, and is output as
signals are explained beloowever, when CTS and RTS signals
____
are not used, there aron of CTSj input, and there is no
_____
RTSk output.
TxDj
UARTj transmit register
UARTk transmit register
UARTj transmit buffer register
UARTj receive buffer register
UARTk transmit buffer register
UARTk receive buffer register
RxDk
UARTj receive register
UARTk receive register
UARTj Transmit/Receive mod
UARTk Transmit/Receive mode register
×
×
×
×
×
×
0
0
1
0
1
0
0
1
CLKj
CTSj
CLKk
RTSk
UARTj Transmit/Rtrol
register 0
UARTk Transmit/Receive control
register 0
MSB/
LSB
TX
MSB/
LSB
TX
×
×
0
TCS1 TCS0
1
EPTY
EPTY
UARTj Transmit/Receive control
register 1
UARTk Transmit/Receive control
register 1
SUM PER FER OER RI
RE
TI
TE
SUM PER FER OER RI
RE
TI
TE
Fig. 59 Clock synchronous serial communication
48
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
changes to “1” at the next cycle just after the TENDj signal goes “H”
Transmission
and changes to “0” when transmission starts. Therefore, this flag can
be used to determine whether data transmission has completed.
When the TIj flag changes from “0” to “1”, the interrupt request bit in
the UARTj transmit interrupt control register is set to “1”.
Transmission is started when bit 0 (TEj flag) of UARTj Transmit/Re-
____
ceive control register 1 is “1”, bit 1 (TIj flag) of one is “0”, and CTSj
input is “L”. As shown in Figure 60, data is output from TXDj pin each
time when transmission clock CLKj changes from “H” to “L”. The data
is output from the least significant bit.
In only UART0, data can be output to a maximum of 3 external re-
ceive devices. This is realized under the condition in which the inter-
nal clock is selected and the transmission clock is output from one of
The TIj flag indicates whether the transmit buffer register is empty or
not. It is cleared to “0” when data is written in the transmit buffer reg-
ister and set to “1” when the contents of the transmit buffer register is
transferred to the transmit register.
pins CLK0, CLKS0 (multiplexed with RXD0) and CLKS1 (multiplexed
____ ____
with CTS0/RTS0). Make sure that do not switch the selection of the
clock during transmission. Figure 61 shows an external connection
example.
When the transmit register becomes empty after the contents has
been transmitted, data is transferred automatically from the transmit
buffer register to the transmit register if the next transmission start
Plural output of transmit clock mode is set with bits 1 and 0 of the
particular function select register 1. Additionally, it is necessary to se-
condition is satisfied. If bit 2 of UARTj Transmit/Receive control reg-
____
___
___
lect the internal clock, disable CTS and RTS, receive and D-A output
with the UART0 Transmit/ive mode register, UART0 Transmit/
Receive control registeand A-D control register 1. Figure
62 shows the other ronfiguration in plural output of trans-
mit clock mode 3 shows the particular function select
register 1 bit .
ister 0 is “1”, CTSj input is ignored, and transmission start is con-
trolled only by the TEj flag and TIj flag. Once transmission has
____
started, the TEj flag, TIj flag, and CTSj signals are ignored until data
transmission completes. Therefore, transmission is not interrupt
____
when CTSj input is changed to “H” during transmission.
The transmission start condition indicated by TEj flag, TIj flag, and
____
Table 6 shtion of the particular function select register
1’s bits ch is the output pin of transmit clock select bits:
TCccording to this table, select the CLK0, CLKS0 or
rresponding to the contents of TC1 and TC0, and out-
nsmit clock.
CTSj is checked while the TENDj signal (shown in Figure 60) is “H”.
Therefore, data can be transmitted continuously if the next transmis-
sion data is written in the transmit buffer register and TIj flag is
cleared to “0” before theTENDj signal goes “H”.
Bit 3 (TXEPTYj flag) of UARTj Transmit/Receive control register 0
1/Pfi × (
Transmission
clock
TE
TIj
j
Write in transmr
Transmit register ←Transmit buffer register
CTSj
/Pfi × (n + 1) × 2
Stopped because TEj = “0”
CLKj
TENDj
TXDj
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
TXEPTYj
Fig. 60 Clock synchronous serial I/O timing
49
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Receive
TXD0
Receive starts when bit 2 (REk flag) of UARTk Transmit/Receive
CLKS1
CLKS0
CLK0
control register 1 is set to “1”.
____
UART0
The RTSk output is “H” when the REk flag is “0” and goes “L” when
the REk flag changed to “1” and the TIk flag did to “0”. It goes back to
“H” when receive starts. The TIk flag is cleared to “0” by write dummy
____
data to the transmit buffer register. It is ready to receive when RTSk
DIN
DIN
DIN
output is “L”.
CLK
CLK
CLK
The data from the RxDk pin is retrieved and the contents of the re-
ceive register is shifted by 1 bit each time when the transmission
clock CLKj changes from “L” to “H.” When an 8-bit data is received,
Note: This is available in clock synchronous serial I/O, using internal clock
and transmission mode.
the contents of the receive register is transferred to the receive buffer
register and bit 3 (RIk flag) of UARTk Transmit/Receive control reg-
ister 1 is set to “1”. In other words, the setting “1” to the RIk flag indi-
cates that the receive buffer register contains the received data.
When the RIk flag change“0” to “1”, the interrupt request bit in
the UARTk receive interegister is set to “1”. Bit 4 (OERk
flag) of UARTk Trancontrol register 1 is set to “1” when
the next data is rom the receive register to the receive
buffer registeag is “1”, and indicates that the next data
was transreceive register before the contents of the re-
ceive was read. RIk flag is automatically cleared to “0”
whder byte of the receive buffer register is read or when
is cleared to “0”. The OERk flag is cleared when the REk
ared or port P8 is set to a parallel port. Bit 5 (FERk flag), bit
Rk flag), and bit 7 (SUMk flag) are ignored in clock synchro-
us mode.
Fig. 61 External connection example in plural output of transmit
clock mode
7
0
6
5
4
3
0
2
0
1
0
0
1
Address
UART0 Transmit/Receive mode register 3016
0 0 1 : Clock synchronous
0
: Internal clock
This bit must be “0”
7
7
6
6
6
5
5
5
4
1
3
3
3
2
1
1
1
0
0
0
Address
3416
UART0 Transmit/Receive control register 0
1
: Disable CTS, RTS
When reading the contents of the receive buffer register, the received
data is pulled from the least significant bit (LSB) in the received order
if bit 7 (TEM) of the UARTj Transmit/Receive control registers 0 is “0”.
If bit 7 (TEM) is “1”, the received data is pulled from the most signifi-
cant bit (MSB).
4
4
2
0
UART0 Transmit/Receive control reg
: Disable receive
0
As shown in Figure 54, with clock synchronous serial communica-
tion, data cannot be received unless the transmitter is operating be-
cause the receive clock is created from the transmission clock.
Therefore, the transmitter must be operating even when there is no
need to sent data from UARTk to UARTj.
7
0
2
A-D control registe
0
: Disabl
Fig. 62 Other registers except special function select register 1 bit
configuration in plural output of transmit clock mode
Table 6. Output pin of transmit clock select bits and pins’ function
Output pin of trans-
Pin name
mit clock select bits
____ ____
TC1
0
TC0
0
P81/CLK0 P82/RXD0 P80/CTS0/RTS0/DA0
____ ____
CLK0
CLK0
“H”
RXD0
P80/CTS0/RTS0/DA0
0
1
“H” (Note)
CLKS2
P80
P80
1
0
1
1
“H”
“H” (Note)
CLKS1
Note:It outputs “H” when bit 2 of the port P8 direction register is “1”, and it
becomes floating when bit 2 is “0”.
50
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
1
0
Particular function select register 1 (6D16)
TC1 TC0
Transmit clock output pin select bit
00 : Normal mode (output only to CLK0)
01 : Plural clocks specified; output to CLK0
10 : Plural clocks specified; output to CLKS0
11 : Plural clocks specified; output to CLKS1
Internal clock stop select bit at WIT (Note 1)
0 : Clock for peripheral function and watchdog timer are operating at WIT
1 : Internal clock except that for oscillation circuit and watchdog timer are stopped at WIT
Watchdog timer’s select bit (Note 1)
0 : Exclusive clock deviding circuit output (Wf512, Wf32used as clock for watchdog
timer. Clock (Wf512, Wf32) for watchdog timer doange in hold.
1 : Clock for peripheral device deviding circuit ou2) is used as clock for
watchdog timer. Clock (Pf512, Pf32) for watcnges in hold.
Watchdog timer exclusive clock dividing ed.
Signal output stop select bit (Note 1)
Refer to Table 8.
Expansion function select bit
Refer to Figure 62.
Pull-up select bit 0 (
0 : With no pull-uP55, P54
1 : With pull-uP55, P54
Pull-up se3)
0 : WiP95
1 : P95
Control bits affected by expansion
function select bit
Control registers affected by expansion
function select register
Register
A
5
Register
Address
1A16
A-D control register 1
Waveform output mode register
Dead-time timer
Chip select area register
2, 5, 6, 7
16 0, 1, 5, 6
6D16 2, 3, 4
1B16
Particular function select re
Particular function selec
Pulse output data register 1
Pulse output data register 0
1C16
1D16
4516
Timer A write flag
____
INT4
interrupt control register
6E16
Notes 1: Bits 2, 3, and 4 can be re-write after bit 5 (expansion function select bit) is set to “1.”
2: After bit 5 is set to “1” once, bit 5 cannot be cleared to “0” except external reset and software reset.
3: Bits 6 and 7 are write-only bits and undefined at read. Do not use SEB or CLB insturuction when setting bits 0–7.
Fig. 63 Particular function select register 1 bit configuration
51
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selection of transfer format
In clock synchronous serial communication, transfer format can be
selected by bit 7 of the Transmit/Receive control register 0. When bit
7 is “0”, transfer format is LSB first. When bit 7 is “1”, transfer format
is MSB first.
transmit buffer register and the receive buffer register when writing
transmit data to the transmit buffer register or reading receive data
from the receive buffer register. Accordingly, the transmitter’s opera-
tion is the same in both transfer formats.
This function is realized by changing connection relation between the
Figure 64 shows the connection relation.
Bit 7 in Transmit/Receive
control register 0
Write to transmit
buffer register
Read from receive
buffer register
Transmit buffer
register
Receive buffer
register
Data bus
DB7
Data bus
DB7
D7
D7
D5
D4
D3
D2
D1
D0
DB6
D6
D5
D4
D3
D2
D1
DB6
DB5
DB5
0
(LSB first)
DB4
D
DB3
DB2
DB1
B1
DB0
DB0
ter
Receive buffer
register
Data bus
DB7
Data bus
DB7
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D
DB6
DB5
1
(MSB first)
DB4
B3
DB3
DB2
DB2
DB1
DB1
DB0
DB0
Fig. 64 Connection relation between transmit buffer register, receive buffer register, and data bus
52
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bit 5 is a select bit of odd parity or even parity.
ASYNCHRONOUS
In the odd parity mode, the parity bit is adjusted so that the sum of 1s
SERIAL COMMUNICATION
in the data and parity bit is always odd.
Asynchronous serial communication can be performed using 7-, 8-,
or 9-bit length data. The operation is the same for all data lengths.
The following is the description for 8-bit asynchronous communica-
tion.
In the even parity mode, the parity bit is adjusted so that the sum of
the 1s in the data and parity bit is always even.
Bit 6 is the parity bit select bit which indicates whether to add parity
bit or not.
With 8-bit asynchronous communication, bit 0 of UARTi Transmit/
Receive mode register is “1”, bit 1 is “0”, and bit 2 is “1”.
Bit 3 is used to select an internal clock or an external clock. If bit 3 is
“0”, an internal clock is selected and if bit 3 is “1”, then external clock
is selected. If an internal clock is selected, bit 0 (TCS0) and bit 1
(TCS1) of UARTi Transmit/Receive control register 0 are used to se-
lect the clock source. When an internal clock is selected for asyn-
chronous serial communication, the CLKi pin can be used as a
normal I/O pin.
Bits 4 to 6 must be set or reset according to the data format used in
the communicating devices.
Bit 7 is the sleep select bit. The sleep mode is described later.
The UARTi Transmit/Receive control register 0 bit 2 is used to deter-
____
____
mine whether to use CTSi input or RTSi output.
____
____
CTSi input is used if bit 2 is “0” and RTSi output is used if bit 2 is “1”.
____
If CTSi input is selected, the user can control whether to stop or start
____
transmission by external CTSi input.
Bit 4 of the UART Transmitceive control register 0 is used to de-
The selected internal or external clock is divided by (n+1), then by
16, and is passed through a control circuit to create the UART trans-
mission clock or UART receive clock.
_
___
termine whether to use TS signal. Bit 4 must be “0” when
____ ____ ___ ___
CTS or RTS signal imust be “1” when CTS or RTS sig-
_ ___ ___
nal is not used. WRTS signal is not used, CTS/RTS pin
___ ___
Therefore, the transmission speed can be changed by changing the
contents (n) of the bit rate generator. If the selected clock is an inter-
nal clock Pfi or an external clock fEXT,
can be used aort. The case using CTS and RTS signals
___ ___
are explaiowever, when CTS and RTS signals are not
____ ____
used, tondition of CTSi input, and there is no RTSi out-
put.
Bit Rate = (Pfi or fEXT) / {(n+1)×16}
Transmit/Receive control register 0 bit 7 to “1” in asyn-
communication.
Bit 4 is the stop bit length select bit to select 1 stop bit or 2 stop bits.
53
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
____
Once transmission has started, the TEi flag, TIi flag, and CTSi signal
____
Transmission
(if CTSi input is selected ) are ignored until data transmission is com-
pleted.
Transmission is started when bit 0 (TEi flag) of UARTi Transmit/Re-
____
ceive control register 1 is “1”, bit 1 (TIi flag) is “0”, and CTSi input is
____
Therefore, transmission does not stop until it completes event if the
TEi flag is cleared during transmission.
“L” if CTSi input is selected. As shown in Figures 65 and 66, data is
output from the TXDi pin with the stop bit or parity bit specified by bits
4 to 6 of UARTi Transmit/Receive mode register. The data is output
from the least significant bit.
The transmission start condition indicated by TEi flag, TIi flag, and
____
CTSi is checked while the TENDi signal shown in Figure 65 is “H”.
Therefore, data can be transmitted continuously if the next transmis-
sion data is written in the transmit buffer register and TIi flag is
cleared to “0” before the TENDi signal goes “H”.
The TIi flag indicates whether the transmit buffer is empty or not. It is
cleared to “0” when data is written in the transmit buffer, and is set to
“1” when the contents of the transmit buffer register is transferred to
the transmit register.
Bit 3 (TXEPTYi flag) of UARTi Transmit/Receive control register 0
changes to “1” at the next cycle just after the TENDi signal goes “H”
and changes to “0” when transmission starts. Therefore, this flag can
be used to determine whether data transmission is completed.
When the TIi flag changes from “0” to “1”, the interrupt request bit of
the UARTi transmit interruntrol register is set to “1”.
When the transmit register becomes empty after the contents has
been transmitted, data is transferred automatically from the transmit
buffer register to the transmit register if the next transmit start condi-
tion is satisfied.
(1/Pfi or 1/fEXT) × (n + 1) × 16
Transmission clock
TE
i
TI
i
Written in transmit buffer register
register ← Transmit
buffer register
CTS
i
T
T
T
ENDi
Stopped because TE
ST
i = “0”
Start bit
ST
ity bit Stop bit
SP ST
X
X
Di
D0
D1
D2
D
D
7
P
D
0
D1
D2
D3
D4
D5
D6
D7
P
SP
D0 D1
EPTY
i
Fig. 65 Transmit timing example synchronous communication with parity and 1 stop bit selected
(1/Pfi or 1/fEXT) × (n + 1) × 16
Transmission clock
TEi
TI
i
Written in transmit buffer register
Start bit
Transmit register ← Transmit
buffer register
T
T
T
ENDi
Stopped because TE
i = “0”
Stop bit Stop bit
SP SP ST
X
X
Di
ST
D0
D1
D
2
D3
D4
D5
D6
D7
D8
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP SP ST D0 D1 D2
EPTY
i
Fig. 66 Transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits selected
54
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Receive
to “0” when reading the low-order byte of the receive buffer register
Receive is enabled when bit 2 (REi flag) of UARTi Transmit/Receive
control register 1 is set to “1.” As shown in Figure 67, the frequency
divider circuit (1/16) at the receiving side begin to work when a start
or when writing “0” to the REi flag or when setting to a parallel port.
The OERi and SUMi flags are cleared to “0” when writing “0” to the
REi flag or when setting to a parallel port.
bit arrives and the data is received.
____
The SUMi flag is cleared to “0” when the OERi, FERi, PERi flags are
cleared to “0” all.
If RTSi output is selected by setting bit 2 of UARTi Transmit/Receive
____
control register 0 to “1”, the RTSi output is “H” when the REi flag is
____
“0”. When the REi flag changes to “1”, the RTSi output goes “L” to
indicate receive ready and returns to “H” once receive has started. In
____
Sleep mode
other words, RTSi output can be used to determine externally
whether the receive register is ready to receive.
The sleep mode is used to communicate only between certain micro-
computers when multiple microcomputers are connected through se-
rial I/O.
The entire transmission data bits are received when the start bit
passes the final bit of the receive block shown in Figure 56. At this
point, the contents of the receive register is transferred to the receive
buffer register and bit 3 (Rli flag) of UARTi Transmit/Receive control
The microcomputer enters the sleep mode when bit 7 of UARTi
Transmit/Receive mode register is set to “1.”
The operation of the sleep mode for an 8-bit asynchronous commu-
nication is described belo
register 1 is set to “1.” In other words, the RIi flag indicates that the
____
receive buffer register contains data when it is set to “1.” If RTSi out-
____
When sleep mode is scontents of the receive register is
not transferred to thfer register if bit 7 (bit 6 if 7-bit asyn-
chronous commbit 8 if 9-bit asynchronous communica-
tion) of the ris “0”. Also the RIi, OERi, FERi, PERi, and
the SUMi hanged. Therefore, the interrupt request bit of
the UAinterrupt control register is also unchanged. Nor-
maration takes place when bit 7 of the received data is
put is selected, RTSi output goes “L” to indicate that the register is
ready to receive the next data.
The interrupt request bit of the UARTi receive interrupt control regis-
ter is set to “1” when the RIi flag changes from “0” to “1”.
Bit 4 (OERi flag) of UARTi Transmit/Receive control register 1 is set
to “1” when the next data is transferred from the receive register to
the receive buffer register while the RIi flag is “1”, in other words,
when an overrun error occurs. If the OERi flag is “1”,
it indicates that the next data has been transferred to the receive
buffer register before the contents of the receive buffer register
been read.
wing is an example of how the sleep mode can be used.
ain microcomputer first sends data: bit 7 is “1” and bits 0 to 6
set to the address of the subordinate microcomputer to be com-
municated with. Then all subordinate microcomputers receive this
data. Each subordinate microcomputer checks the received data,
clears the sleep bit to “0” if bits 0 to 6 are its own address and sets
the sleep bit to “1” if not. Next, the main microcomputer sends data
with bit 7 cleared. Then the microcomputer which cleared the sleep
bit will receive the data, but the microcomputers which set the sleep
bit to “1” will not. In this way, the main microcomputer is able to com-
municate only with the designated microcomputer.
Bit 5 (FERi flag) is set to “1” when the number of stop bits i
required (framing error).
Bit 6 (PERi flag) is set to “1” when a parity error oc
Bit 7 (SUMi flag) is set to “1” when either the OEflag, or
the PERi flag is set to “1.” Therefore, the SUbe used to
determine whether there is an error.
The setting of the RIi flag, OERi flag, d the PERi flag is
performed while transferring the ce receive register to
the receive buffer register. The RPERi flags are cleared
Pfi or fEXT
RE
i
Stop bit
Start bit
Start bit
Check to be “L” level
RX
Di
D0
D1
D7
Data fetched
Receive
Clock
Starting at the falling
edge of start bit
RI
i
RTS
i
Fig. 67 Receive timing example when 8-bit asynchronous communication with no parity and 1 stop bit selected
55
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D CONVERTER
The A-D converter is a 10-bit successive approximation converter.
The use of A-D converter or the use of comparator can be selected
for each A-D input pin. The contents of the comparator function se-
lect register specify it.
Figure 68 shows a block diagram of the A-D converter.
V
REF connection
select bit
V
REF
Vref
Ladder network
AVSS
Comparator function select register
(0: A-D converter, 1: Comparator)
A-D control register 1
(Address 1F16
)
(Address 6416
)
A-D control register 0
(Address 1E16
)
Selector
1
Control circuit
Selector
Successive approximation
register
Comparator result registe
(Address 6616
)
Address
Address
A-D register 0 (2116
A-D register 1 (2316
A-D register 2 (2516
A-D register 3 (2716
A-D register 4 (2916
)
)
)
)
)
A-D register 0 (2016
A-D register 1 (2216
A-D register 2 (2
A-D register 3
A-D regis
)
)
Compa-
rator
Decoder
A-D register 5 (2B16
)
A-D re
A-D register 6 (2D16
)
A-6
)
A-D register 7 (2F16
)
2E16
)
Data bus (odd)
Data bus (even)
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7/ADTRG
Selector
A-D conversion speed selection
φ1
Frequency select
flag 0, 1
0
1
Pf
Pf
2
4
0
f(XIN
)
1/2
φ1
φAD
1/2
Pf
2
1/2
Pf
8
1
Clock source for peripheral
devices select bit
(bit 2 of processor mode register 1)
Clock source select bit
(bit 6 of processor mode register 1)
1/2
Fig. 68 A-D converter block diagram
56
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 69 shows the comparator function select register (address
der network or not depends on bit 5 of the A-D control register 1. The
VREF pin is connected when bit 5 is “0” and is disconnected when bit
5 is “1” (High impedance state).
6416) bit configuration. Bits 7 to 0 correspond to channels 7 to 0 re-
spectively. Each channel can be selected as either an A-D converter
or a comparator. When the bit is “0”, the channel corresponding to it
functions as a 10-bit or an 8-bit A-D converter. When the bit is “1”, the
channel functions as a comparator.
When A-D or D-Aconversion is not performed, current from the VREF
pin to the ladder network can be cut off by disconnecting ladder net-
work from the VREF pin.
When selecting an A-D converter, an input voltage to a selected ana-
log input pin is A-D converted and the result is stored into the A-D
register.
Before starting A-D or D-A conversion, wait for 1 µs or more after
clearing bit 5 to “0”.
When selecting a comparator, D-A conversion is performed to the
value of which high-order 8 bits are the value stored in an even ad-
dress of the A-D converter and of which low-order 2 bits are “102.”
Then, this D-A converted value is compared with the voltage sup-
plied to an analog input pin. After the comparison, when the voltage
supplied to an analog input pin is higher, “1” is stored into the com-
parator result register (address 6616) shown in Figure 70. When it is
lower, “0” is stored into that register.
7
6
5
4
3
2
1
0
Address
Comparator function select register 6416
“0” : Select A-D converter
“1” : Select comparator
AN0 pin comparator function select bit
AN1 pin comparator function select bit
pin comparator function select bit
in comparator function select bit
n comparator function select bit
pin comparator function select bit
N6 pin comparator function select bit
AN7 pin comparator function select bit
Be sure to perform only read to the A-D register of which channel is
selected as an A-D converter, and perform only write to the A-D reg-
ister of which channel is selected as a comparator. Additionally, do
not write to the comparator function select register and the A-D reg-
ister while an A-D converter or a comparator is operating.
Port direction register’s bits corresponding to pins to be A-D con-
verted must be “0” (input mode) because analog input ports are mul-
tiplexed with port P7.
Fig. 6or function select register bit configuration
5
4
3
2
1
0
Address
Figure 71 shows the bit configuration of the A-D control register 0
(address 1E16) and the A-D control register 1 (address 1F16).
An operation clock (φAD) of an A-D converter or a comparator c
selected with bit 7 of the A-D control register 0 and bit 4 o
control register 1.
Comparator result register 6616
“0” : ANi input level is lower than set digital value
“1” : ANi input level is higher than set digital value
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
pin comparator result bit
pin comparator result bit
pin comparator result bit
pin comparator result bit
pin comparator result bit
pin comparator result bit
pin comparator result bit
pin comparator result bit
When bit 4 (frequency select flag 1) of the A-D contis
“0”, φAD becomes Pf8 when bit 7 (frequency selece A-D
control register 0 is “0”, φAD becomes Pf4 wheA-D con-
trol register 0 is “1”.
When the frequency select flag 1 is “1”es Pf2 when the
frequency select flag 0 is “0”, φAD bhen the frequency
select flag 0 is “1”. The last case n φ1 is forcibly used as
φAD in high-speed running (f(XIN) > 5 MHz). However, this se-
lection is available only in 8-bit resoluton mode.
Note: Do not access with the SEB or CLB instruction.
Fig. 70 Comparator result register bit configuration
φAD during A-D conversion must be 250 kHz or more because the
comparator uses a capacity coupling amplifier.
Bit 3 of A-D control register 1 is used to select whether to regard the
conversion result as 10-bit or as 8-bit data. The conversion result is
regarded as 10-bit data when bit 3 is “1” and as 8-bit data when bit 3
is “0”.
When the conversion result is used as 10-bit data, the low-order 8
bits of the conversion result is stored in the even address of the cor-
responding A-D register and the high-order 2 bits are stored in bits 0
and 1 at the odd address of the corresponding A-D register. Bits 2 to
7 of the A-D register odd address are “0000002” when read.
When the conversion result is used as 8-bit data, the high-order 8
bits of the 10-bit A-D conversion result are stored in even address of
the corresponding A-D register. In this case, the value at the A-D
register’s odd address is “0016” when read.
Whether to connect the reference voltage input (VREF) with the lad-
57
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When the bit of comparator function select register is “0” and bit 3 of
Operation mode
A-D control register 1 is “1”, A-D conversion ends after 59 fAD cycles,
and the interrupt request bit of the A-D interrupt control register is set
to “1.” At the same time, A-D control register 0 bit 6 (A-D conversion
start bit) is cleared to “0” and A-D conversion stops. The result of A-D
conversion is stored in the A-D register corresponding to the selected
pin.
The operation mode is selected by bits 3 and 4 of A-D control regis-
ter 0 and bit 2 of A-D control register 1. The available operation
modes are one-shot, repeat, single sweep, repeat sweep 0, and re-
peat sweep 1. Either an A-D converter or a comparator can be se-
lected respectively for every pin in the following 5 modes. The
following description applies to the case where the bit of the com-
parator function select register is “0” and an A-D converter is se-
lected. It also applies to a comparator’s operation except that an A-D
conversion is changed to a comparator operation and the result of a
comparison is stored into the comparator result register.
When the bit of the comparator function select register is “1”, a com-
parator operation ends after 14 fAD cycles and the interrupt request
bit of the A-D interrupt control register is set to “1”. At the same
time, the A-D control register 0 bit 6 (A-D conversion start bit) is
cleared to “0” and the comparator operation stops. The result of the
comparison is stored into the bit of the comparator result register cor-
responding to the selected pin.
(1) One-shot mode
One-shot mode is selected when bits 3 and 4 of A-D control register
0 are “0” and bit 2 of A-D control register 1 is “0”. The A-D conversion
pins are selected with bits 0 to 2 of A-D control register 0. A-D con-
version can be started by a software trigger or by an external trigger.
A software trigger is selected when bit 5 of A-D control register 0 is
“0” and an external trigger is selected when it is “1”. When a software
trigger is selected, A-D conversion or comparator operation is started
when bit 6 (A-D conversion start flag) is set to “1.”
If an external trigger is selected, A-D conversion starts when the A-D
_____
conversion start bit is “1” ae ADTRG input changes from “H” to
“L”. In this case, the pins used for A-D conversion are AN0
__
to AN6 because the Amultiplexed with analog voltage in-
put pin AN7. This the same as that for software trigger
except that thsion start bit is not cleared after A-D con-
version ancan be available during A-D conversion.
Address
7
×
6
×
5
4
3
2
1
0
Address
1F16
A-D control register 1
6
5
4
3
2
1
0
1E16
A-D control register 0
Analog input select bit
A-D sweep pin select bit
When single sweep or repeat sweep
mode 0 is selected
0 0 0 : Select AN
0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
, AN1
(2 pins)
(4 pins)
(6 pins)
(8 pins)
0 0 1 : Select AN
0 1 0 : Select AN
0 1 1 : Select AN
1 0 0 : Select AN
1 0 1 : Select AN
1
2
3
4
5
– AN
– AN
– AN
3
5
7
When repeat sweep mo
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
(1
1 1 0 : Select AN
6
, AN
– AN
– A
1
1 1 1 : Select AN
7
2
A-D operation mode select bit 0
0 0 : One-shot mode
A-D operatt bit 1
0 : Otsweep mode 1
1 : mode 1
8/1ct bit
0 : 8
1 : 10-bode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0
Repeat sweep mode 1
Trigger select bit
0 : Software trigger
A-D converter frequency select bit 1
1 : ADTRG input trigger
A-D conversion start bit
0 : Stop A-D conversion
1 : Start A-D conversion
A-D conversion frequency select bit 0
V
REF connection select bit (Note 5)
0 : VREF is connected
1 : VREF is not connected
These bits are not used for A-D converter.
A-D conversion frequency select bit
A-D conversion frequency select bit
Bit 6 at address
5F16 (Note 1)
Bit 2 at address
5F16 (Note 2)
Bit 6 at address
5F16 (Note 1)
Bit 2 at address
5F16 (Note 2)
fAD
fAD
Bit 1
0
Bit 0
0
Bit 1
0
Bit 0
0
f(XIN)/8
f(XIN)/4
f(XIN)/2
f(XIN) (Note 4)
f(XIN)/4
f(XIN)/2
f(XIN)/16
f(XIN)/8
0
1
0
1
0
1
0
1
1
0
1
0
f(XIN)/4
1
1
1
1
f(XIN)/2 (Note 3)
f(XIN)/8
0
1
0
0
0
0
0
1
0
1
f(XIN)/4
1
0
1
0
f(XIN)
f(XIN)/2
1
1
1
1
Notes1, 2: Refer to Figure 9 Processor mode register 1 bit configuration.
3: When f(XIN) > 25 MHz, this can be selected only in 8-bit resolution
mode.
Notes 4: When f(XIN) > 12.5 MHz, this can be selected only in 8-bit resolution mode.
5: When the expansion function select bit (bit 5 of particular function select
register 1 ; refer to Fig. 62) is “1”, bit 5 can be written and changed.
Fig. 71 A-D control register bit configuration
58
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Repeat mode
(5) Repeat sweep mode 1
Repeat mode is selected when bit 3 of A-D control register 0 is “1”,
Repeat sweep mode 1 is selected when bit 3 of A-D control register
0 is “1”, bit 4 is “1” and bit 2 of A-D control register 1 is “1”.
The difference from the repeat sweep mode 0 is that A-D conversion
for one unselected pin is performed each time when A-D conversion
for selected pins is completed and A-D conversion is repeated once
again from AN0 pin. The number of analog input pins to be swept is
also different.
bit 4 is “0” and bit 2 of A-D control register 1 is “0”.
The operation of this mode is the same as the operation of one-shot
mode except that when A-D conversion of the selected pin is com-
plete and the result is stored in theA-D register, conversion does not
stop, but is repeated.
No interrupt request is generated in this mode. Furthermore, if soft-
ware trigger is selected, the A-D conversion start bit is not cleared.
The contents of the A-D register can be read at any time.
Be sure not to write to the A-D register corresponding to the pins se-
lected for a comparator during operation.
The analog input pins for repeatedly sweep are selected with bits 1
and 0 of A-D control register 1. The contents of these pins are used
to select one pin, two pins, three pins, or four pins.
The unselected pins are converted from the pin next to the pins se-
lected as repeat sweep pins. No interrupt request is generated. Fur-
thermore, if software trigger is selected, the A-D conversion start bit
is not cleared.
(3) Single sweep mode
Single sweep mode is selected when bit 3 of A-D control register 0
is “0”, bit 4 is “1” and bit 2 of A-D control register 1 is “0”.
In the single sweep mode, the number of analog input pins to be
swept can be selected. Analog input pins are selected by bits 1 and
0 of the A-D control register 1 (address 1F16). Two pins, four pins,
six pins, or eight pins can be selected as analog input pins, depend-
ing on the contents of these bits.
The A-D register can be rany time.
Be sure not to write to ter corresponding to the pins se-
lected for a comparperation.
Note: Clear request bit of the A-D interrupt control reg-
istdress 7016) before using the A-D interrupt. It is
interrupt request bit is undefined just after reset.
A-D conversion is performed only for selected input pins. After A-D
conversion is performed for input of AN0 pin, the conversion result
is stored in A-D register 0, and in the same way, A-D conversion is
performed for selected pins one after another. After A-D conversion
is performed for all selected pins, the sweep is stopped.
A-D conversion can be started with a software trigger or with an
ternal trigger input. A software trigger is selected when bit 5
and an external trigger is selected when it is “1”.
When a software trigger is selected, A-D conversion is
A-D control register 0 bit 6 (A-D conversion start 1.”
When A-D conversion of all selected pins end, tequest
bit of the A-D conversion interrupt control regi“1.” At the
same time, A-D conversion start bit is cleaA-D conver-
sion stops.
When an external trigger is selectersion starts when
the A-D conversion start bit is “1RG input changes from
“H” to “L”. In this case, the A-D conn result which is stored in
_____
the A-D register 7 becomes invalid because the ADTRG pin is multi-
plexed with AN7 pin.
The operation by external trigger is the same as that by software
trigger except that the A-D conversion start bit is not cleared to “0”
after A-D conversion and a retrigger can be available during A-D
conversion.
(4) Repeat sweep mode 0
Repeat sweep mode 0 is selected when bit 3 of A-D control register
0 is “1”, bit 4 is “1” and bit 2 of A-D control register 1 is “0”.
The difference from the single sweep mode is that A-D conversion
does not stop after conversion for all selected pins, but repeats
again from the AN0 pin. The repeat is performed among the selected
pins. Also, no interrupt request is generated. Furthermore, if soft-
ware trigger is selected, the A-D convension start bit is not cleared.
The A-D register can be read at any time.
Be sure not to write to the A-D register corresponding to the pins se-
lected for a comparator during operation.
59
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
WhenA-D or D-A conversion is not performed, current from the VREF
pin to the ladder network can be cut off by disconnecting ladder net-
D-A CONVERTER
The D-A converter is an 8-bit R-2R method D-A converter and con-
sists of two independent D-A converters. Figure 72 shows the block
diagram of the D-A converter and Figure 73 shows the bit configura-
tion of A-D control register 1.
work from the VREF pin.
Before starting A-D or D-A conversion, wait for 1 µs or more after
clearing bit 5 to “0”. An external buffer must be connected when con-
necting to a low impedance load because there is no built-in D-A out-
put buffer.
D-A conversion is performed by writing a value in the corresponding
D-A register. The conversion result is output by bits 6 and 7 of A-D
control register 1 (address 1F16). When bit 7 is “1”, the conversion
result is output from DA0 pin.
7
6
5
4
×
3
×
2
×
1
×
0
×
Address
1F16
When bit 6 is “1”, the conversion result is output from DA1pin.
The output analog voltage V is determined according to the value n
(“n” is a decimal number) set in the D-A register.
A-D control register 1
Not used for D-A converter
VREF connection select bit (Note)
0 : VREF is connected
1 : VREF is not connected
D-A1 output enable bit
0 : Disable output
V = VREF × n/256 (n = 0 to 255)
VREF : Reference voltage
1 : Enable output
0 output enable bit
isable output
: Enable output
The D-A output enable bit is cleared to “0” at reset. Whether to con-
nect the reference voltage input (VREF) with the ladder network or not
depends on bit 5 of the A-D control register 1. The VREF pin is con-
nected when bit 5 is “0” and is disconnected when bit 5 is “1” (High
impedance state).
Note : When thnction select bit (bit 5 of peripheral
functior 1 ; refer to Fig. 62) is “1,” bit 5 can be
writtd.
Fig. 73 register 1 bit configuration
)
VREF connection
select
ter 0
ss 6816)
D-A register 1
(Address 6A16)
VREF
R-2k
R-2R ladder network
AVSS
AVSS
D-A0 output
enable bit
D-A1 output
enable bit
D-A0 pin
D-A1 pin
Fig. 72 D-A converter block diagram
60
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
The watchdog timer is used to detect unexpected execution se-
quence caused by software runaway and others. Figure 74 shows
the block diagram of the watchdog timer.
Clock source for peripheral
devices Pf2
Hold request
Pf512
The watchdog timer consists of a 12-bit binary counter.
1/8
1/2
1/2
1/8
Pf32
The watchdog timer counts clock Wf32/Pf32, which is obtained by di-
viding the peripheral devices’ clock Pf2 by 16; or clock Wf512/Pf512,
which is obtained by doing it by 256. The watchdog timer frequency
select register shown in Figure 75 selects which clock is counted.
Wf512/Pf512 is selected when its contents are “0”, and Wf32/Pf32 is
selected when they are “1”. They are cleared to “0” after reset.
The watchdog timer clock select bit (bit 3 of particular function select
register 1; Figure 62) selects use of clock Wf512/Wf32 or Pf512/Pf32
as the clock source of watchdog timer. When selecting Wf512/Wf32,
the clock source of watchdog timer (Wf512/Wf32) is not active during
Hold state. When selecting Pf512/Pf32, the clock source of watchdog
timer (Pf512/Pf32) is active during Hold state, however, current con-
sumption can be reduced. It is because the Wf512/Wf32 division cir-
cuit stops.
Pf16
Watchdog timer frequency select register
Wf32
Address 6016
Wachdog timer
1/16
Hold request
1/16
Set FFF16
Wf512
Watchdog timer clock select bit
Write to watchdog timer
RESET
FFF16 is set in the watchdog timer when “L” or 2Vcc is applied to the
______
STP ins
S
R
Q
RESET pin, STP instruction is executed, data is written to the watch-
dog timer, or the most significant bit of the watchdog timer becomes
“0”.
After FFF16 is set in the watchdog timer, when the watchdog timer
counts the clock source by 2048 counts, the most significant bit of
watchdog timer becomes “0”, the watchdog timer interrupt reques
bit is set to “1”, and FFF16 is set again in the watchdog timer.
Normally, a program is written so that data is written in the wa
timer before the most significant bit of the watchdog timer
“0”. If this routine is not executed owing to unexpected -
ecution and others, the most significant bit of the mer
becomes “0” and an interrupt is generated.
Pf16
STP return select bit
Fig. 74 Watchdog timer block diagram
Address
6116
7
6
5
4
3
2
1
0
0
The microcomputer can be reset by writing “ftware re-
set bit) of processor mode register 0 in t routine, de-
scribed in Figure 16 in the interrupt senerating a reset
Watchdog timer frequency
select register
pulse.
0 : Wf512 or Pf512 selected
1 : Wf32 or Pf32 selected
______
The watchdog timer stops its futhe RESET pin voltage
is raised to double the Vcc voltage
This bit must be fixed to “0.”
The watchdog timer can also be used to return from when the clock
is stopped by the STP instruction. Refer to the section on the clock
generating circuit for more details.
Fig. 75 Watchdog timer frequency select register bit configuration
The watchdog timer also becomes Hold state during Hold state and
the clock input to it is stopped.
61
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
INPUT/OUTPUT PINS
______
Reset is released when the RESET pin is returned to “H” level after
holding it at “L” level while the supply voltage is at 5V ±10%. As the
result, program execution starts at the address formed by setting the
address A23–A16 to 0016, A15–A8 to the contents of address FFFF16,
and A7–A0 to the contents of address FFFE16.
Ports P0 to P11 all have the direction register and each bit can be
programmed for input or output. A pin becomes an output pin when
the corresponding bit of direction register is “1”, and an input pin
when it is “0”.
When a pin is programmed for output, the data is written to its port
latch and it is output to the output pin. When a pin is programmed for
output, the contents of the port latch is read instead of the value of
the pin. Accordingly, a previously output value can be read correctly
even when the output “H” voltage is lowered or the output “L” voltage
is raised owing to an external load and others.
Figure 76 shows the status of the internal registers during reset.
Figure 77 shows an example of a reset circuit. When a stabilized
clock is input from the external to the oscillation circuit, the reset in-
put voltage must be held 0.9V or lower when the supply voltage
reaches 4.5V. When connecting a resonator to the oscillation circuit,
return the reset input voltage from “L” to “H” after the main-clock os-
cillation is fully stabilized
A pin programmed as an input pin is floating, and the value input to
the pin can be read. When a pin is programmed as an input pin, the
data is written only in the port latch and the pin remains floating.
Additionally, ports P95, P54 o P57 include pull-up transistors. The
pull-up function of ports ied with bits 7 and 6 of the particular
function select registthe section on Interrupts for the
pull-up function.
Power on
Figures 78 and ock diagrams of ports P0 to P11 in the
single-chip output.
4.5V
VCC
RESET
VCC
0 V
Ports P0 nd P11 are also used as pins of address, data
and c. Refer to the section on Processor mode for more
de
RESET
0 V
0.9V
Fig. 77 Reset circuit example (perform careful evaluation at sys
design before using)
62
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address
Address
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
)
Watchdog timer
(
)
0416 ···
0016
0016
0
6016 ···
FFF16
Port P0 direction register
Port P1 direction register
Port P2 direction register
)
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
)
0516 ···
Watchdog timer frequency select register
Chip select control register
Chip select area register
6116 ···
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
?
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
?
)
)
0816 ···
0
0
0
0
0
0
0
6216 ···
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
)
)
6316 ···
0916 ···
0
Port P3 direction register
Port P4 direction register
Port P5 direction register
Port P6 direction register
Port P7 direction register
Port P8 direction register
Port P9 direction register
Port P10 direction register
)
)
0C16 ···
0016
0016
0016
0016
0016
Comparator function select register
Comparator result register
6416 ···
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
?
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
)
)
0D16 ···
6616 ···
)
)
6816 ···
1016 ···
D-A register 0
)
)
6A16 ··· 0
1116 ···
D-A register 1
Particular function select register 0
)
)
6C16 ··· 0
1416 ···
)
)
1516 ···
0
0
0
0
0
0
6D16 ··· 0
Particular function select register 1
)
1816 ···
0016
0016
0016
0016
0
···
INT
INT
4
3
interrupt control regis
interrupt control
)
)
6F16 ··· 0
0
1916 ···
Port P11 direction register
Waveform output mode register
Pulse output data register 1
Pulse output data register 0
A-D control register 0
)
)
7016 ···
1A16 ···
A-D interrupt co
)
)
7116 ···
1C16 ···
UART 0 tranl register
)
)
1D16 ··· 0
0
0
0
0
0
0
0
?
0
0
?
1
0
?
1
7216 ···
UART control register
terrupt control register
eive interrupt control register
)
)
1E16 ··· 0
0
0
0
0
7316 ···
)
)
7416 ···
A-D control register 1
1F16 ··· 0
)
)
7516 ···
3016 ···
0016
0016
r A0 interrupt control register
UART 0 Transmit/Receive mode register
UART 1 Transmit/Receive mode register
UART 0 Transmit/Receive control register 0
UART 1 Transmit/Receive control register 0
UART 0 Transmit/Receive control register 1
UART 1 Transmit/Receive control register 1
Count start register
)
)
7616 ···
3816 ···
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
)
)
7716 ···
3416 ···
0
0
0
0
0
0
1
1
0
0
0
)
)
3C16 ··· 0
7816 ···
)
)
3516 ···
7916 ···
)
3D
7A16 ···
Timer B0 interrupt control register
Timer B1 interrupt control register
)
0016
7B16 ···
)
7C16 ···
0
0
0
0
0
0
0
0
0
0
0
0
0
Timer B2 interrupt control register
One-shot start register
Up-down register
)
)
16 ···
0
0
0
7D16 ···
0
0
0
0
0
0
0
0
INT
INT
INT
0
1
interrupt control register
interrupt control register
interrupt control register
)
)
7E16 ···
Timer A write register
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
4516 ···
)
)
7F16 ···
5616 ···
0016
0016
0016
0016
0016
0
2
)
5716 ···
0 0 0 ? ?
Processor status register PS
Program bank register PG
)
5816 ···
0016
Program counter PC
H
L
)
5916 ···
Contents of FFFF16
Contents of FFFE16
000016
)
Program counter PC
5A16 ···
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Processor mode register 0
Processor mode register 1
)
5B16 ··· 0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Direct page register DPR
Data bank register DT
)
5C16 ··· 0
0
0016
)
5D16 ··· 0
0
Contents of other registers and RAM are not initiallzed and must be in-
itiallzed by software.
)
5E16 ··· 0
0 0
)
5F16 ···
0016
Note : Bit 0 of chip select control register (address 6216) becomes “0” when CNVss pin level is “L”; that bit becomes “1” when the pin level is “H”.
Fig. 76 Microcomputer internal registers status after reset
63
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Port P00 to P07, P10 to P17, P20 to P23, P27, P30 to P33, P43 to P46, P100 to P107, P110 to P117 (Inside dotted-line not included)
Port P40, P41, P47, P51, P53, P61 to P67, P86 (Inside dotted-line included)
Direction register
Data bus
Port latch
• Port P70 to P76 (Inside dotted-line not included)
• Port P77 (Inside dotted-line included)
Direction register
Data bus
Port latch
Ana
• Port P42, P83, P87, P90 to P94 (Inside dotted-lind)
Port P50, P52, P60, P82 (Inside dotted-line in
register
“1”
Output
Da
Port latch
• Port P54, P56
Pull-up select
Direction register
Port latch
“1”
Output
Data bus
_
Fig. 78 Block diagram for ports P0 to P11 in single-chip mode and E output (1)
64
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pull-up select
• Port P55, P57, P95
Direction register
Data bus
Port latch
• Port P80 (Inside dotted-line not included.)
• Port P84 (Inside dotted-line included.)
“1”
“0”
Direction register
Port latch
Output
Data bus
TSi
alog output
Enable D-A output
• Port P81, P85
“1”
“0”
Direction register
Port latch
Output
us
_
• E
Hold
acknowledge
_
Fig. 79 Block diagram for ports P0 to P11 in single-chip mode and E output (2)
65
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
The clock generating circuit makes basic clocks, which activate the
central processing unit (CPU), bus interface unit (BIU) and internal
peripheral devices, of an oscillation circuit output. Figure 82 shows
the block diagram of the clock generating circuit.
XIN
XOUT
The clock source φ 1 to activate internal peripheral devices, the clock
source φ BIU to activate the bus interface unit and the clock source
φ CPU to activate the CPU are made of an clock input to the XIN pin.
When bit 6 (clock source select bit) of processor mode register 1 is
“0”, the clock which is obtained by dividing an input clock to the XIN
pin by 2 becomes the clock source φ 1. When bit 6 is “1”, the clock
which is an input clock to the XIN pin becomes the clock source φ 1
as it is. When bit 2 (clock source for peripheral devices select bit) is
“0”, the clock source φ 1 which is more divided by 2 becomes the
standard clock for peripheral devices. When bit 2 is “1”, the clock
source φ 1 becomes the standard clock for peripheral devices as it
is.
Rf
Rd
COUT
CIN
Fig. 80 Circuit example mic (or quartz crystal) resonator
The standard clock is more divided with the division circuit shown in
Figure 82 and the clocks having all kinds of frequencies are made.
Each internal peripheral device can select one of 4 clocks, Pf2, Pf16,
Pf64 and Pf512, and use it.
Pf2 means f(XIN), which is an oscillation circuit’s frequency, divided
by 2 when the clock source for peripheral devices select bit is “1”. It
means f(XIN) divided by 4 when that bit is “0”. In the case of φ 1 > 12.5
MHz, fix the bit to “0”.
XIN
XOUT
Open
Figure 80 shows a circuit example using a ceramic (or quartz crys
tal) resonator. Use the manufactures’ recommended values for
stants such as capacitance which differs for each resonator.
Figure 81 shows a circuit example inputting clocks extern
inputting clocks externally, setting bit 1 (clock externt
bit) of particular function select register 0 (in Figure akes
operation of the clock oscillation circuit stop, thaT output
stays at “H”, and the current consumption re
External clock source
Vcc
Vss
Fig. 81 Circuit example inputting clocks externally
66
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Fig. 82 Clock generating circuit block diagram
67
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
1
0
0
Address
6C16
Particular function select register 0
This bit must be fixed to “0.”
External clock input select bit (Notes 1, 2)
0 : Actuated oscillation circuit; connecting resonator
1 : Stopped oscillation circuit; inputting externaly genarated clock
Memory allocation select bit (Note 2)
0 : ROM 60 Kbytes, RAM 2048 Bytes
(
)
ROM : 00100016 to 00FFFF16, RAM : 00008016 to 00087F16
1 : ROM 56 Kbytes, RAM 2048 Bytes
(
)
ROM:00200016 to 00FFFF16, RAM:00008016 to 00087F16
Standby state select bit 0 (Notes 1, 3)
; in execution of WIT or STP instruction in memansion
or microprocessor mode
0 : External bus for P0 to P3, P10, P11
1 : Port Input/Output for P0 to P3, P10
Standby state select bit 1 (Note
; in execution of WIT or STP
0 : “H” or “L” output for pi
1 : “H” output for pins
STP rerurn sel
0 : Wachdowhen returning from Stop mode.
1 : Wacot used when returning from Stop mode ; the maicrocompnuter returns
at
Notes 1 : After the expansion function selecrticular function select register 1; Figure 62) is “1”,
bits 1, 5 and 6 can be written a
2 : To set bits 1 and 2, continuooperations to address 6C16 are required.
3 : When BYTE = “H” (8-bit eth), P11 becomes an input/output port independent of bit 5’s contents.
4 : When the signal output bit = “1” and bit 5 = “1”, the E/RD pin outputs “L” independent of bit 6’s contents
in execution of WIT ion.
Fig. 83 Particular function select reonfigulation
68
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
STANDBY FUNCTION
STP instruction
The WIT and the STP instructions make the microcomputer standby
When the STP instruction is executed, the oscillation circuit is
stopped and the clock sources φ 1, φ BIU and φ CPU are at “L”. Fur-
thermore, “FFF16” is automatically set into the watchdog timer, and
its clock source is forced to connect with Wf32 when the watchdog
timer clock select bit = “0”, or Pf32 when the bit = “1”. This connection
is cut off when the most significant bit of the watchdog timer be-
comes “0” or the microcomputer is reset, and the clock source is con-
nected with the input depending on the contents of the watchdog
timer frequency select register and the watchdog timer clock select
bit. In STP state, all of the internal peripheral devices and the watch-
dog timer which use divided clocks Pf2 to Pf512, Wf32, and Wf512 are
stopped.
state.
Table 7 shows the relation between standby state and each block’s
operation.
The WIT/STP state is terminated by interrupt acceptance or reset.
Accordingly, it is necessary to prepare the state in which any inter-
rupt can be accepted before the WIT/STP instruction is executed.
WIT instruction
When the WIT instruction is executed with the internal clock stop
select bit at WIT (bit 2 of particular function select register 1; Figure
62) = “0”, the clock sources φ BIU and φ CPU are stopped at “L”, how-
ever, the oscillation circuit, the clock source φ 1, and the divided
clocks Pf2 to Pf512, Wf32, Wf512 are not stopped. Accordingly, al-
though the CPU and bus interface unit stop operation, internal pe-
ripheral devices which use these divided clocks can operate even at
WIT state.
The STP state is terminated by reset or interrupt request accep-
tance, and then oscillation is restarted. At the same time, supply of
the clock source φ 1 and dlocks Pf2 to Pf512, Wf32 and Wf512
is restarted.
In that condition, wreturn select bit (bit 7 of particular
function select “0”, the clock sources φ BIU and φ CPU
stop at “L” st significant bit of the watchdog timer
decremeded clock Pf32 or Wf32 becomes “0”. However,
supplsources φ BIU and φ CPU is restarted immediately
afttion restarts by reset. Accordingly, in this case, wait
ime to stabilize the oscillation before the reset input of
Otherwise, when the WIT instruction is executed with the internal
clock stop select bit at WIT = “1”, the oscillation circuit is not stopped,
however, the clock source φ 1, divided clocks, and the clock sources
φ BIU and φ CPU are stopped. Accordingly, in this case, all of the inter-
nal peripheral devices and the watchdog timer which use divided
clocks Pf2 to Pf512, Wf32, and Wf512 are stopped.
When internal peripheral devices are not used in WIT state, the lat-
ter state (internal clock stop select bit at WIT = “1”) is more effectiv
to reduce current consumption.
wise in that condition, when the STP return select bit is “1”,
pply of the clock sources φ BIU and φ CPU is restarted at the timing
of the divided clock Pf16’s “H” to “L” after the oscillation restarts. This
function makes it possible to immediately return from STP state
when the clock supply input to the XIN from the external is stabilized.
Even though clocks are input from the external, make sure to clear
the STP return select bit to “0” if the external clock is unstable for a
short time when returning from STP state
Make sure to set the internal clock stop select bit at WIT to “1
diately before the WIT instruction execution and clear th
immediately after the WIT state is terminated.
The WIT state is terminated when an interrupt reqted,
and the internal clock φ operation is restarted. cessing
can immediately be executed because oscils operation
is not stopped during WIT state.
Table 7 Relation between standeach block’s operation.
Operation at WIT/STP state
Internal peripheral devices
Internal clock
Instruction
stop bit at WIT
Oscillation
circuit
φ 1
Pf2 to Pf512
Wf2, Wf512
φ BIU, φ CPU
using Pf2 to Pf512, Wf32,
Wf512
Operating
(Note 1)
Operating
Operating
Operating
(Note 2)
Stopped
(“L”)
Operation enabled
(Watchdog timer operating)
“0”
“1”
—
WIT
STP
Operating
(Note 1)
Stopped
(“L”)
Stopped
(“H”)
Stopped
(“H”)
Stopped
(“L”)
Operation disabled
(Watchdog timer stopped)
Stopped
(“L”)
Stopped
(“H”)
Stopped
(“H”)
Stopped
(“L”)
Operation disabled
(Watchdog timer stopped)
Stopped
Notes 1 : When the clock external input select bit is “1”, the clock oscillation circuit stops. An external clock can be input.
2 : When the watchdog timer clock select bit is “1”, Wf32 and Wf512 stop. The watchdog timer operates with Pf32 or Pf512.
69
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus cycle in WIT/STP
direction register and port latch in WIT/STP state like ports in single-
When the WIT/STP instruction is executed with the standby state se-
lect bit 1 (bit 6 of particular function select register 0) = “0”, the clock
sources φ BIU and φ CPU or oscillation stop without waiting for
completion of the bus cycle being executed. Accordingly, the micro-
computer may enter WIT/STP state during bus access in which out-
chip mode. That is, when setting arbitrary data to the port latch and
the contents of direction register to “1”, that data is output from the
pin; when clearing the contents of direction register to “0”, the pin
becomes floating. This function makes the external bus arbitrary
state in WIT/STP state. When making pins floating, take consider-
ation with an external circuit to prevent their electric potential from
becoming half level of the electric potential.
_ ___
___
put of pins E, RD and WR is “L”.
Otherwise, when the WIT/STP instruction is executed with the
standby state select bit 1 = “1”, the clock sources φ BIU and φ CPU or
oscillation stop after completion of read or write in the bus access
cycle being executed. Consequently, in WIT/STP state, the bus be-
When writing to registers relevant to ports P0 to P3, P10, P11 in the
memory expansion/microprocessor mode, set the standby state se-
lect bit 0 to “1” before that write. If that bit is “0”, write is impossible,
because addresses corresponding to registers relevant to ports P0
to P3, P10, P11, which are addresses 216 to 916, 1616 to 1916, are
the external memory areas shown in Figure 86.
_ ___
___
comes the nonaccess state in which output of pins E, RD and WR is
“H”.
[Note]
Bus state in WIT/STP
Port P11 functions as a/output port regardless of processor
modes when inputtinYTE pin.
Normally, pins for the address output, data input/output and bus
control signal output in the memory expansion/microprocessor mode
(ports P0 to P3, P10, P11 in single-chip mode; refer to section on
Processor mode) retain the state as external bus pins when the
clock sources φ BIU and φ CPU stop in WIT/STP state.
___
The RD pin starily be selected in WIT/STP state in the
memory exoprocessor mode, too. Refer to the Table 8
for deta
However, when the WIT/STP instruction is executed with the
standby state select bit 0 (bit 5 of particular function select register
0) = “1”, those pins function depending on the contents of each port
Note ction of arbitrary data output cannot be emulated
uger.
Table 8 Signal output disable select bit function (bit 4 of particulelect register 1; Figure 62)
Function
Processor mode
Pin
Signal e select bit = “0”
Signal output disable select bit = “1”
Outputs l E.
_ ___
Outputs “L”.
Single-chip mode
E/RD
___ ___
___ ___
Outwhen accessing internal/
ery area.
Outputs RD/WR when accessing external
memory area only.
RD, WR
” or “L” after executing WIT/STP
on
Outputs “H” or “L” after executing WIT/STP
instruction.
___
RD
uts “H” when standby state select bit 1 is
”.
Outputs “L” when standby state select bit 0 is
“1”.
Memory expansion mode
Microprocessor mode
Outputs “H” when standby state select bit 1 is
“1” and standby state select bit 0 is “0.”
Outputs “L” when multiplex bus select bit =
“0”.
Outputs ALE.
ALE
Outputs ALE when multiplex bus select bit =
“1”.
Outputs clock φ 1 regardless of φ 1 output
select bit.
Outputs contents of port P42 latch; necessary
to set its direction register bit to “1”.
φ 1
Microprocessor mode
Note : All functions of signal output disable select bit cannot be debugged using an debugger.
70
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PROCESSOR MODE
• BYTE pin
Bits 0 and 1 of processor mode register 0 (address 5E16) shown in
Figure 84 are used to select any mode of the single-chip mode, the
memory expansion mode and the microprocessor mode.
Ports P0 to P3, P10, P11 and a part of port P4 are used as I/O pins
of address, data, and control signals in the modes except the single-
chip mode.
When accessing the external memory, the level of the BYTE pin is
used to determine whether to use the data bus as 8-bit width or 16-
bit width.
The data bus has a width of 16 bits when the level of the BYTE pin is
“L”, and ports P10 and P11 become the data I/O pins.
The data bus has a width of 8 bits when level of the BYTE pin is “H”,
and port P10 becomes data I/O pins. Port P11 functions then as an
input/output port similarly in the single-chip mode.
Figure 85 shows the functions of ports P0 to P4, P10 and P11 in
each mode.
The external memory area depends on the mode. Figure 86 shows
the memory map for each mode. Refer to Figure 1 for the addresses
of RAM and ROM in the single-chip mode. The external memory
area can be accessed in the modes except the single-chip mode.
The access to the external memory is affected by the BYTE pin
When accessing the internal memory, the data bus always has a
width of 16 bits regardless of the BYTE pin level.
A
7
6
0
5
4
3
2
1
0
Processor mode register 0
Processor mode bits
0 0 : Single-chip m
0 1 : Memory e
1 0 : Micropr
1 1 : Do n
Intercess bus cycle select bit (Note)
; y access condition in high-speed running
s for internal RAM; 3-φ access for internal ROM and SFR
cess for internal RAM, internal ROM and SFR
are reset bit
set occurs when writing “1” to this bit
Interrupt priority detection time select bit
0 0 : Select case 0 shown in Figure 13
0 1 : Select case 1 shown in Figure 13
1 0 : Select case 2 shown in Figure 13
Test mode bit
This bit must be fixed to “0.”
Clock φ1 output select bit
0 : No φ1 output
1 : φ1 output
Note : Clear bit 2 to “0” in low-speed running.
Fig. 84 Processor mode register 0 bit configuration
71
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1
PM1
PM0
0
0
0
1
0
Port
Microprocessor mode (Note 1)
Mode
Single-chip mode
Memory expansion mode (Note 1)
E/RD
Same as left
Same as left
(Note 1)
RD
(Note 2)
E
E/RD
E
E/RD
E
Port P0
Port P1
Port P2
P00
to
P27
P00
to
P27
I/O port
Address A0 to A19,A23
E
BYTE = “L”
Same as left
Same as left
P100
to
P107
Data (even)
E
P100
to
P107
• Condition except following
E
I/O port
Port
P10
P100
to
P107
D
(
BYTE = “H”
• When multiplex bus seld
___
accessing CS4 area
E
Same as left
P100
to
Data
P107
o LA7 (odd, even)
E
Same as left
Same as left
BYTE = “L”
BYTE = “H”
P117
Data (odd)
I/O port
Port
P11
P110
to
P117
I/O port
P110
to
P117
E
E
P30
P31
(Note 2)
WR
BHE
Same as left
Port P3
P30
to
P33
I/O port
ALE
HLDA
P32
P33
E
E
P40
to
P40
P41
input
HOLD
I/O port
Clock φ1 is output from P42 regardless of
bit 7 of processor mode register 0 ; others
are the same as left (Note 2)
P47
input
RDY
Port P4
Clock φ 1 is output from P42 when bit 7 of
processor mode register 0 is “1”.
P42
to
P47
I/O port
Clock φ 1 is output from P42 when bit 7 of
processor mode register 0 is “1.”
Fig. 85 Processor modes and ports P0 to P4, P10 and P11
__
Notes 1 : E signal is not output in the memory expansion and microprocessor modes.
__
2 : The signal output stop disable bit (bit 4 of particular function select register 0) can stop E output in the single-chip mode and φ1 output in the micro-
___ ___
processor mode. Similarly, when accessing the internal memory in the memory expansion and microprocessor modes, RD and WR output can be
fixed to “H”. Refer to Table 8 for details.
72
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor modes are explained bellow.
follows during the bus cycle in which the external memory area cor-
___
responding to the chip select CS4 are accessed:
•Output pins of addresses LA0 to LA7, same as low-order addresses
___ ___
A0 to A7, during “H” of RD or WR.
___
Memory expansion
mode
216 to 916
1616 to 1916
SFR
Microprocessor
mode
•Data input/output pins at even and odd addresses during “L” of RD
___
or WR.
That is, it functions as a multiplex bus during that bus cycle.
Port P11 has two functions depending on the level of the BYTE pin.
When the BYTE pin level is “L”, those pins function as data D8 to D15
I/O pins at an odd address. The I/O port function is lost. However, if
an internal memory area is read, external data is not input. When the
BYTE pin level is “H”, port P11 functions as a programmable port
P11 similarly in the single-chip mode.
SFR
8016
RAM
RAM
___ ____
_____
Ports P30, P31, P32, and P33 become WR, BHE, ALE, and HLDA
ROM
output pins respectively and ose their I/O port functions.
___
WR is a write signal whictes a write when it is “L”.
____
BHE is a byte-high-ewhich indicates that an odd ad-
dress is accessed .
Therefore, two n and odd addresses are accessed si-
____
multaneousess A0 is “L” and BHE is “L”.
ALE is ach-enable signal. The latch is open while ALE
is “H”ddress signal passes through; the address is held
FFFFFF16
w”.
_
hold-acknowledge signal and is used to indicate to the
_____
The shaded area is the external memory area.
that the microcomputer accepts HOLD input and enters
state.
_____
____
Fig. 86 External memory area for each mode
orts P40 and P41 become HOLD and RDY input pins, respectively,
and their I/O port function are lost.
_____
HOLD is a hold-request signal. It is an input signal used to make the
_____
(1) Single-chip mode [00]
microcomputer enter Hold state. HOLD input is accepted when the
φ BIU has fallen from “H” to “L” level while the bus is not used. In Hold
state, φ CPU stops at “L”. A0 to A19, A23, D0 to D7, D8 to D15 (at BYTE
The microcomputer enters the single-chip mode by he
CNVss pin to Vss and starting from reset. Ports 0 and
P11 all function as normal I/O ports. Port Put clock
source φ 1 by setting bit 7 of the processor r 0 to “1”.
___ ___
____
= “L”), RD, WR and BHE become floating then. These pins become
_____
_
_
floating one cycle of φ BIU later than HLDA signal becomes “L” level.
In this mode, enable signal E is output f. Signal E out-
put can be stopped by setting the sigsable select bit (bit
4 of particular function select reg”, and it is possible to
switch the output to “L” level. Tablthe function of the signal
output disable select bit’s function.
When terminating Hold state, these pins are terminated from floating
_____
state one cycle of φ BIU later than HLDA signal becomes “H” level.
____
RDY is a ready signal. When this signal goes “L”, φ CPU and φ BIU
____
stop at “L”. RDY is used when a slow external memory is connected
and others.
Port P42 becomes a normal I/O port when bit 7 of the processor
mode register 0 is “0” and becomes the clock φ 1 output pin when bit
(2) Memory expansion mode [01]
The microcomputer enters the memory expansion mode by setting
the processor mode bits to “01” after connecting the CNVss pin to
Vss and starting from reset.
____
7 is “1”. The φ 1 output is independent of RDY and does not stop
____
even when φ CPU and φ BIU stop owing to “L” input to the RDY pin.
_ __
___
___
Pin E/RD becomes the RD output pin. RD is an read signal, and read
is performed during it is “L” level. When the internal memory area is
___
read, the RD output can be fixed to “H” by setting the signal output
disable select bit to “1”.
Ports P0, P1 and P2 become the output pins of addresses A0 to A19
and A23, and their I/O port function are lost.
Port P10 becomes I/O pins of data D0 to D7 and loses its I/O port
function. When the BYTE pin’s level is “L”, those pins function as
data I/O pins at an even address. When the level is “H”, those pins
function as data I/O pins at even and odd addresses. However, if an
internal memory area is read, external data is not input
When the BYTE pin’s level is “H” and the multiplex bus select bit (bit
5 of chip select area register; Figure 88) is “1”, port P10 functions as
73
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Microprocessor mode [10]
Table 9. Relationship between CNVSS pin’s input levels and proces-
The microcomputer enters the microprocessor mode by connecting
the CNVss pin to Vcc and starting from reset. It is possible to enter
this mode by programming the processor mode bits to “10” after con-
necting the CNVss pin to Vss and starting from reset. This mode is
the same as the memory expansion mode except the following: the
internal ROM is disabled and an external memory is required, and
clock φ 1 is always output from port P42 independent of bit 7 of the
processor mode register 0.
sor modes
CNVSS
Mode
• Single-chip
• Memory expansion
• Microprocessor
Description
Single-chip mode upon start-
ing after reset. Each mode
can be selected by changing
the processor mode bits by
software.
VSS
Microprocessor mode upon
starting after reset.
• Microprocessor
VCC
As shown in Table 8, φ 1 output can also be stopped by setting the
signal output disable select bit to “1”. In this case, write “1” to the port
P42 direction register bit.
Table 9 shows the relationship between the CNVss pin’s input level
and the processor modes.
___
___
Additionally, addresses A20 to A22 or chip select signals CS0 to CS4
can be output from port P9 regardless of processor modes. For de-
tails, refer to the following sections: output function of chip select sig-
nal and address output function.
74
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
OUTPUT FUNCTION OF CHIP SELECT SIGNAL
___
___
Ports P90 to P94 can output the chip select signals CS0 to CS4 ac-
cording to the contents of chip select control register and chip select
area register. Bits 0 to 3 of chip select control register select either
chip select output (or addresses A20 to A22 output) or port function.
Additionally, bits 0 to 2 of chip select area register select the area in-
tended for each chip select signal.
7
6
5
4
3
2
1
0
Address
Chip select control register 6216
CS
CS
CS
CS
0
function select bit (Note 1)
: Port P9 function
: CS output
0
1
0
0
1
, CS2 function select bit (Note 2)
: Port P9 , P9 function
: CS1, CS output or A20, A21 output
0
1
1
2
2
Figure 87 shows the bit configuration of chip select control register
and Figure 88 shows that of chip select area register. Figure 89
shows the chip select areas.
3
function select bit (Note 2)
: Port P9 function
: CS output or A22 output
0
1
3
3
___
___
The bus cycle of CS3 and CS4 can be selected with bits 4 to 7 of chip
select control register. That selection is valid regardless of the bus
cycle select bits of processor mode register 1. Additionally, that bus
4
function select bit
: Port P9 function
: CS output
0
1
4
4
___
___
CS
3
bus cycle select bits
cycle selection of CS3 and CS4 is valid when selecting port function
___ ___
b5 b4 In high-speed In low-speed
with the CS3 and CS4 function select bits.
0
1
: 5-φ access
: 4-φ access
: 3-φ access
Do not select.
4-φ access
3-φ access
When accessing addresses in which the chip select area specified
by bits 0 to 2 of chip select area register and the internal memory
area overlap one another, chip select signals are not output. In this
case, its bus cycle is the cycle of internal memory area access.
It is possible to make the chip select output floating during Hold
state. That is realized by clearing the corresponding bit of port P9
direction register (address 1516) to “0” and bits 0 to 2 of waveform
output mode register (address 1A16) to “000”. The timing of Hold
start and termination is the same as that of addresses A0 to A19. (Re-
fer to section on processor mode.)
: Do not select. 2-φ access
S
4
bus cycle select bits
b7 b6 In high-speed In low-speed
0
0
1
1
0
1
0
1
: 5-φ access
: 4-φ access
: 3-φ access
Do not select.
4-φ access
3-φ access
: Do not select. 2-φ access
et, bit 0 becomes “0” when the CNVss pin’s level is “L”;
0 becomes “1” when the CNVss pin’s level is “H”.
its 6 and 7 of chip select area register (address 6316) specify
whether the chip select signal or address is output.
ADDRESS OUTPUT FUNCTION
Fig. 87 Chip select control register bit configuration
Port P91 to P93 can output the high-order addresses (A20
cording to bits 1 and 2 of chip select control register, a7
of chip select area register.
___
___
___
About signal pairs of A20 and CS1, A21 and CSnd CS3,
___
only one signal can be output. It is because ignals CS1
___
to CS3 output are common to ports P91 tdresses A20 to
A22 output.
It is possible to make the address ng during Hold state.
That is realized by clearing the cog bit of port P9 direction
register (address 1516) to “0” and 0 to 2 of waveform output
mode register (address 1A16) to “000”. The timing of Hold start and
termination is the same as that of addressesA0 to A19. (Refer to sec-
tion on processor mode.)
75
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
1
0
Address
Chip select area register
6316
Chip select area switch bits (Notes 1, 2)
000 : CS0 00100016 to 02FFFF16 (188 Kbytes)
CS1 03000016 to 04FFFF16 (128 Kbytes)
CS2 05000016 to 06FFFF16 (128 Kbytes)
CS3 00088016 to 000DFF16 (1408 bytes)
CS4 000E0016 to 000FFF16 (512 bytes)
001 : CS0 00800016 to 02FFFF16 (160 Kbytes)
CS1 03000016 to 04FFFF16 (128 Kbytes)
CS2 05000016 to 06FFFF16 (128 Kbytes)
CS3 00088016 to 000FFF16 (1920 bytes)
CS4 00100016 to 007FFF16 (28 Kbyt)
010 : CS0 00100016 to 02FFFF16 (188 K
CS1 03000016 to 04FFFF16 (1
CS2 05000016 to 06FFFF16
CS3 07000016 to 077FFF)
CS4 07800016 to 07Ftes)
011 : CS0 00800016 to 0Kbytes)
CS1 03000016 t28 Kbytes)
CS2 0500001(128 Kbytes)
CS3 070016 (32 Kbytes)
CS4 07FFF16 (32 Kbytes)
100 : CS0 2FFFF16 (190 Kbytes)
Co 04FFFF16 (128 Kbytes)
16 to 06FFFF16 (128 Kbytes)
0016 to 3FFFFF16 (3.5 Mbytes)
7000016 to 07FFFF16 (64 Kbytes)
00088016 to 02FFFF16 (190 Kbytes)
CS1 03000016 to 04FFFF16 (128 Kbytes)
CS2 05000016 to 06FFFF16 (128 Kbytes)
CS3 07000016 to 07FFFF16 (64 Kbytes)
CS4 08000016 to 7FFFFF16 (7.5 Mbytes)
110 : CS0 00088016 to 06FFFF16 (446 Kbytes)
CS1 , CS2 Not available
CS3 08000016 to 3FFFFF16 (3.5 Mbytes)
CS4 07000016 to 07FFFF16 (64 Kbytes)
111 : CS0 00088016 to 06FFFF16 (446 Kbytes)
CS1 , CS2 Not available
CS3 07000016 to 07FFFF16 (64 Kbytes)
CS4 08000016 to 7FFFFF16 (7.5 Mbytes)
Multiplex bus select bit (Note 1)
0 : D0 to D7 input/output (separate bus)
1 : When BYTE pin input is “H” and accessing CS4 area
LA0/D0 to LA7/D7 input/output (multiplex bus)
In condition except above
D0 to D7 input/output (separate bus)
Expansion address output select bits (Notes 1, 3)
0 0 : P91.... CS1 output, P92...CS2 output, P93...CS3 output
0 1 : P91.... A20 output, P92...CS2 output, P93...CS3 output
1 0 : P91.... A20 output, P92...A21 output, P93...CS3 output
1 1 : P91.... A20 output, P92...A21 output, P93...A22 output
Notes 1 : When the expansion function select bit (bit 5 of particular function select register 1; Figure 62) is “1”,
bits 2, 5, 6 and 7 can be written and changed.
2 : When accessing the internal memory area, CSi is not output. When only accessing the external area, CSi output is valid.
3 : Select function of bits 6 and 7 is valid when both the CS1, CS2 function select bit and the CS3 function select bit (chip
select control register) are “1”.
Fig. 88 Chip select area register bit configuration
76
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Fig. 89 Chip select areas
77
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MEMORY MODIFICATION FUNCTION
When ordering a mask ROM, Mitsubishi Electric corp. produces the
The M37754M8C-XXXGP’s internal memory size and address area
can be modified by set of bit 2 (memory allocation select bit) of the
particular function select register 0. Figure 90 shows the memory al-
location when modifying the internal memory area.
mask ROM using the data within 60 Kbytes (between addresses
00100016 to 00FFFF16). It is regardless of the selected ROM size
(refer to MASK ROM ORDER CONFIRMATION FORM). Therefore,
on the EPROM tendered for ordering a mask ROM, program data
“FF16” to addresses which correspond to the area out of the selected
ROM area.
Additionally, address 00FFFF16 of the microcomputer corresponds
to the lowest address of the tendered EPROM.
Memory allocation select bit = “1”
ROM size : 56 Kbytes
Memory allocation select bit = “0”
ROM size : 60 Kbytes
RAM size : 2048 bytes
RAM size : 2048 bytes
00 000016
00 008016
00 087F16
00 000016
00 008016
00 087F16
SFR
SFR
Internal RAM 2048 bytes
Internal RAM 2048 bytes
00 100016
00 200016
00 FFFF16
Internal ROM
60 Kbytes
Internal ROM
56 Kbytes
00 FFFF16
External memory area
ory area
Note : The internal ROM area becomes external memory area
in microprocessor mode.
FF FFFF16
16
Fig. 90 Memory allocation when ernal memory area with memory allocation select bit
78
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ADDRESSING MODES AND INSTRUCTION SET
The M37754M8C-XXXGP and M37754M8C-XXXHP have 29 pow-
erful addressing modes; 1 addressing mode is added to the basis of
the 7700 series. Refer to the “7751 Series Software Manual” for the
details.
INSTRUCTION SET
The M37754M8C-XXXGP and M37754M8C-XXXHP have the ex-
tended instruction set; 6 instructions are added to the instruction set
of 7700 series. The object code of this extended instruction set is
upwards compatible to that of 7700 series instruction set.
Refer to the “7751 Series Software Manual” for the details.
SHORTENING NUMBER OF INSTRUCTION
EXECUTION CYCLES
Shortening number of instruction execution cycles is realized in the
M37754M8C-XXXGP and M37754M8C-XXXHP owing to modifica-
tions of the instruction execution algorithm and the CPU circuit, and
others.
Refer to the “7751 Series Software Manual” about the number of in-
struction execution cycles.
DATA REQUIRED FOR MASK ROM ORDERING
Please send the following data for mask orders:
<M37754M8C-XXXGP>
(1) M37754M8C-XXXGP mask ROM order confirmation
(2) 100P6S mark specification form
(3) ROM data (EPROM 3 sets)
<M37754M8C-XXXHP>
(1) M37754M8C-XXXHP mask ROM ordon form
(2) 100P6Q mark specification form
(3) ROM data (EPROM 3 sets)
79
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Ratings
–0.3 to 7
–0.3 to 7
–0.3 to 12
Symbol
Parameter
Unit
V
VCC
AVCC
VI
Power source voltage
Analog power source voltage
V
Input voltage RESET, CNVSS, BYTE
V
Input voltage P00–P07, P10–P17, P20–P23, P27, P30–P33, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87, P90–P95,
P100–P107, P110–P117, VREF, XIN
VI
V
V
–0.3 to VCC+0.3
–0.3 to VCC+0.3
Output voltage P00–P07, P10–P17, P20–P23, P27, P30–P33, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87, P90–P95,
P100–P107, P110–P117, XOUT, E
VO
Power dissipation
Pd
300
mW
°C
Operating temperature
Storage temerature
Topr
Tstg
–20 to 85
–40 to 150
°C
RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V±10 %, Ta = –20 to s otherwise noted)
Limits
Symbol
Parameter
Unit
in.
4.5
Max.
5.5
Typ.
5.0
VCC
0
V
V
V
V
VCC
Supply voltage
AVCC
VSS
Analog supply voltage
Supply voltage
0
AVSS
Analog supply voltage
High-level input voltage P00–P07, P10–P17, P20–P23, P27, 0–P47,
P50–P57, P60–P67, P70–P77, P8P95, XIN,
RESET, CNVSS, BYTE
0.8 VCC
VIH
VCC
V
______
VCC
VCC
0.8 VCC
0.5 VCC
V
V
VIH
VIH
High-level input voltage P100–P107, P110–P117 (in mode)
High-level input voltage P100–P107, P110–P117
(in memory expansiomicroprocessor mode)
Low-level input voltage P00–P07, P10–P1P27, P30–P33, P40–P47,
VIL
P50–P57, P60–7, P80–P87, P90–P95, XIN,
0
V
0.2 VCC
______
RESET, CNV
VIL
VIL
Low-level input voltage P100–P107 (in single-chip mode)
0
0
0.2 VCC
V
V
Low-level input voltage P100–117
0.16 VCC
(in mnsion mode and microprocessor mode)
High-level peak output curre
P10
P1
0
–
P1
P6
–
7
, P2
, P7
P11
0
–
P2
P7
3
, P2
7
, P3
P8
0
–
, P9
P3
3
, P4
P9
0
–
, P9
P4
7,
5,
IOH(peak)
7, P6
0–
7
0–
7, P8
0–
7
0–
2
–10
–20
mA
mA
mA
mA
–
7, P11
0
7
P93, P94
IOH(peak)
IOH(avg)
High-level average outprent P0
P5
0
–
P0
P5
7, P1
0
–
P1
P6
7
, P2
, P7
P11
0
–
P2
P7
3, P2
7, P3
0–
P3
3, P4
0–
P4
7,
5,
0–
7, P6
0–
7
0–
7, P8
0–
P8
7, P9
0–
P9
2, P9
–5
–15
10
P10
0–
P10
7
, P11
0
–
7
IOH(avg)
IOL(peak)
P93, P94
Low-level peak output current P0
P5
0
–
P0
P5
P10
7
, P1
0
–
P1
P6
7
, P2
, P7
P11
0
–
P2
P7
3
, P2
7
, P3
0
7
–
P3
3
, P4
0–P47,
5,
4–
7, P6
0–
7
0–
7, P8
0–
P8
, P9
0, P9
mA
P10
0–
7, P11
0–
7
IOL(peak)
IOL(avg)
P50–P53, P91–P94
Low-level average output current P0
P5
20
5
mA
mA
0
–
–
P0
P5
P10
7
, P1
, P6
, P11
0
–
–P6
P1
7
, P2
, P7
P11
0
–
P2
P7
3
, P2
7
, P3
P8
0
–
, P9
P3
3
, P4
0–P47,
5,
4
7
0
7
0–
7, P8
0–
7
0, P9
P10
0
–
7
0
–
7
mA
IOL(avg)
f(XIN)
15
25
40
P50–P53,P91–P94
External clock frequency input (Note 3)
Low-speed running
High-speed running
MHz
Notes 1: Average output current is the averaage value of a 100 ms interval.
2: The sum of IOL(peak) for ports P0, P1, P2, P3, P8, P10, and P11 must be 80 mA or less, the sum of IOH(peak) for ports P0, P1, P2,
P3, P8, P10, and P11 must be 80 mA or less, the sum of IOL(peak) for ports P4, P5, P6, P7, and P9 must be 110 mA or less, the
sum of IOH(peak) for ports P4, P5, P6, P7, and P9 must be 80 mA or less.
3: When the clock source select bit is “1,” f(XIN)’s maximum limit is 12.5 MHz at low-speed running and is 20 MHz at high-speed
running.
80
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 40 MHz (Note))
Limits
Typ.
Symbol
Test conditions
Parameter
Unit
V
Max.
Min.
3.4
High-level output voltage P0
P2
P5
P8
0
–P0
7
, P1
0
3
–P1
, P4
–P6
–P9
, P11 –P11
7
0
7
2
, P2
–P4
, P7
, P9
0–P23,
7
, P3
1
, P3
7,
VOH
IOH = –10 mA
0–P77,
0–P5
7
7
, P6
0
0
0
–P8
, P9
5,
7
P10
High-level output voltage P0
P2
0–P10
7
0
0
–P07, P1 –P1 , P2
, P3 , P3 , P9 –P9
P10 –P10 , P11 –P117
0
3
7
0
0–P23,
IOH = –400 µA
4.8
7
1
2
,
V
VOH
VOH
0
7
0
_
High-level output voltage E, P30, P32
IOH = –10 mA
IOH = –400 µA
IOH = –15 mA
IOH = –600 µA
3.4
4.8
3.4
4.8
V
V
High-level output voltage P93, P94
VOH
VOL
Low-level output voltage P0
P2
P5
P8
0
–P0
7
, P1
0
–P1
, P4
–P6
, P9
, P11 –P11
7
, P2
–P4
,P7
0–P23,
7,
7
, P3
1
, P3
3
0
0
0
4–P5
7, P6
7
0
–P77,
V
V
2
IOL = 10 mA
0–P8
7, P9
5,
P10
Low-level output voltage P0 –P0
P2 , P3
P10
0–P10
7
0
7
0
7
1
, P1 –P1 , P2
, P3 , P9
–P10 , P11 –P11
Low-level output voltage E, P30, P32
0
3
7
0–P23,
7
0,
IOL = 2 mA
0.45
VOL
VOL
0
7
0
7
_
IOL = 10 mA
IOL = 2 mA
IOL = 2
IOL
1.6
0.4
2
V
V
Low-level output voltage P50–P53, P91–P94
VOL
0.4
_____ ____
Hysteresis
HOLD, RDY, TA0IN–TA4IN,
TB0IN–TB2IN, INT0–INT4, ADTRG,
____ ____
____ ____ _____
VT+ —VT–
1
0.4
V
CTS0, CTS1, CLK0, CLK1, RxD0,
RxD1
______ _____ ____
VT+ —VT–
VT+ —VT–
Hysteresis
Hysteresis
RESET, HOLD, RDY
XIN
0.2
0.1
0.5
0.3
V
V
High-level input current P0
P2
P5
P8
P
S, BYTE
0
7
–P0
, P3
–P5
–
7
0
, P1
–
–P11
,
0
0
0
–P7
, XIN
–P2
7,
µA
IIH
VI = 5 V
VI = 0 V
5
7
,
Low-level input curreP1 –P1 , P2
–P3 , P4 –P4
P5 , P6 –P6 , P7
8 –P8 , P9 –P9
P10 –P10 , P11 –P11
RESET, CNVSS, BYTE
P57, P95
0
7
0
3,
0
3
3
0
0
7
7,
0
–P77,
µA
–5
IIL
0
7
0
5,
0
7
0
7
, XIN
,
Low-level input current P54
–
VI = 0 V, No pull-up transistor
VI = 0 V, Pull-up transistor used
When clock is stoped.
–5
IIL
µA
mA
V
–0.25
2
–0.5
25
–1.0
RAM hold voltage
VRAM
Power supply current (target value)
f(XIN) = 40 MHz, square
Output-only pin is
open and other
pins are Vss during
reset.
50
1
mA
waveform (Note)
Ta = 25 °C when clcock
is stopped.
ICC
µA
Ta = 85 °C when clcock
is stopped.
20
Note: f(XIN) = 20 MHz when the clock source select bit = “1.”
81
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D CONVERTER CHARACTERISTICS
(VCC = AVCC = 5 V ± 10 %, VSS = AVSS = 0 V, Ta = –20 to 85 °C, the clock source select bit = 0, unless otherwise noted)
Limits
Symbol
Parameter
Resolution
Test conditions
Unit
Min.
Typ.
Max.
10
A-D converter selected
Comparator selected
10-bit mode
Bits
V
—————
VREF = VCC
1
256 VREF
± 3
LSB
LSB
mV
LSB
mV
kΩ
250 kHz ≤ φAD
≤ 12.5 MHz
8-bit mode
± 2
—————
RLADDER
Absolute accuracy
Ladder resistance
VREF = VCC
VREF = VCC
Comparator
± 40
± 3
8-bit mode
250 kHz ≤ φAD
≤
20 MHz (Note 1)
Comparator
± 60
20
5
10-bit mode
8-bit mode
Comparator
8-bit mode
Comparator
10-bit mode
8-bit mo
Com
5.9
4.9
72
3.92
1.12
2.7
0
φ
AD = f(XIN)/4
High-speed
running
(f(XIN) ≤ 40 MHz)
selected
φAD = f(XIN)/2
selected
tCONV
Conversion time
µs
(Note 2)
Low-speed running
(f(XIN) 25 MHz) (Note 2)
≤
VREF
VIA
Reference voltage
VCC
V
V
Analog input voltage
VREF
Notes 1: This is valid when the high-speed running is selected.
2: When the clock source select bit = 1, f(XIN) is 20 MHz or less at the hing, and f(XIN) is 12.5 MHz or less at the low-speed running.
D-A CONVERTER CHARACTERISTICS
(VCC = 5 V, VSS = AVSS = 0 V, VREF = 5 V, Ta = –20 to 85 °erwise noted)
Limits
Test conditions
Symbol
——
Parameter
Unit
Min.
1
Typ.
Max.
8
Resolution
Bits
%
——
tsu
Absolute accuracy
Set time
± 1.0
3
µs
RO
Output resistance
2.5
4
kΩ
mA
IVREF
Reference power current
(Note)
3.2
Note: The test conditions are as follo
• One D-A converter is used.
• The D-A register value of the unused D-A converter is “0016.”
• The reference power supply input current of the ladder resistance of the A-D converter is excluded.
82
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PERIPHERAL DEVICE INPUT/OUTPUT TIMING (VCC = 5 V±10 %, VCC = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
If the values depends on external clock frequency f(XIN), formulas of the limits are shown below. Also, the values at f(XIN) = 40 MHz in high-
speed running and at f(XIN) = 25 MHz in low-speed running are shown in ( ). At this time, the clock source select bit is “0.” When the clock
source select bit is “1”, regard f(XIN) in tables as 2·f(XIN).
The rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted.
Timer A input (Count input in event counter mode)
Limits
Symbol
Parameter
Unit
Min.
80
Max.
tc(TA)
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input high-level pulse width
TAiIN input low-level pulse width
40
40
Timer A input (Gating input in timer mode)
Limits
Symbol
Parameter
Unit
ns
ns
ns
ns
ns
ns
109
(XIN)
8 × 109
f(XIN)
4 × 109
f(XIN)
8 × 109
f(XIN)
4 × 109
f(XIN)
Max.
f(XIN)
≤
40 MHz
25 MHz
40 MH
5 MHz
(400)
tc(TA)
TAiIN input cycle time
(XIN)
f(XIN)
f(XIN)
f(
≤
(320)
(200)
(160)
(200)
(160)
≤
≤
tw(TAH)
tw(TAL)
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Note :The TAiIN input cycle time requires 4 or more cycles of coe TAiIN input high-level pulse width and the TAiIN input low-level pulse width
respectively require 2 or more cycles of the count sourn the table are the values when the count source is f(XIN)/4 in high-speed running
(f(XIN)
≤
40 MHz) and when the count source is f(XIed running (f(XIN)
≤
25 MHz). At this time, the clock source select bit is “0.”
Timer A input (External trigger input in oe mode)
Symbol rameter
Limits
Unit
ns
Min.
8 × 109
f(XIN)
4 × 109
f(XIN)
Max.
f(XIN) ≤ 40 MHz
f(XIN) ≤ 25 MHz
(200)
(160)
tc(TA)
TAiIN input cycl
ns
tw(TAH)
tw(TAL)
TAiIN input high-level pulse width
TAiIN input low-level pulse width
ns
ns
80
80
Timer A input (External trigger input in pulse width modulation mode)
Symbol Parameter
Limits
Unit
Min.
80
Max.
Max.
tw(TAH)
tw(TAL)
TAiIN input high-level pulse width
TAiIN input low-level pulse width
ns
ns
80
Timer A input (Up-down input in event counter mode)
Symbol Parameter
Limits
Unit
Min.
2000
1000
1000
400
tc(UP)
TAiOUT input cycle time
ns
ns
ns
ns
ns
tw(UPH)
TAiOUT input high-level pulse width
TAiOUT input low-level pulse width
TAiOUT input setup time
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
TAiOUT input hold time
400
83
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A input (Two-phase pulse input in event counter mode)
Limits
Symbol
Parameter
Unit
Min.
800
200
200
Max.
TAiIN input cycle time
TAjIN input setup time
TAjOUT input setup time
tc(TA)
ns
ns
ns
tsu(TAjIN-TAjOUT)
tsu(TAjOUT-TAjIN)
• Count input in event counter mode
• Gating input in timer mode
• External trigger input in one-shot pulse mode
• External trigger input in pulse width modulation mode
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
• Up-down and count input in event counter mode
tw(UPH)
tc(UP)
TAiOUT input
(Up-down input)
tw(UPL)
TAiOUT input
(Up-down input)
t
su(UP-TIN)
TAiIN input
(When count by falling)
TAiIN input
(When count by rising)
• Two-phase pulse input in event cou
TAjIN input
tc(TA)
tsu(TAjIN-TAjOUT)
tsu(TAjIN-TAjOUT)
tsu(TAjOUT-TAjIN)
TAjOUT input
tsu(TAjOUT-TAjIN)
Test conditions
• VCC = 5 V±10 %
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
84
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B input (Count input in event counter mode)
Symbol
Limits
Parameter
Unit
Min.
80
Max.
tc(TB)
TBiIN input cycle time (one edge count)
ns
ns
ns
ns
ns
ns
tw(TBH)
tw(TBL)
tc(TB)
TBiIN input high-level pulse width (one edge count)
TBiIN input low-level pulse width (one edge count)
TBiIN input cycle time (both edge count)
40
40
160
80
tw(TBH)
tw(TBL)
TBiIN input high-level pulse width (both edge count)
TBiIN input low-level pulse width (both edge count)
80
Timer B input (Pulse period measurement mode)
Symbol Parameter
Limits
Unit
ns
ns
ns
ns
ns
ns
.
1
N)
× 109
f(XIN)
4 × 109
f(XIN)
8 × 109
f(XIN)
4 × 109
f(XIN)
Max.
f(XIN) ≤ 40 MHz
f(XIN) ≤ 25 MHz
f(XIN) ≤ 40 MHz
f(XIN) ≤ 25
f(XI
MHz
00)
tc(TB)
TBiIN input cycle time
(320)
(200)
(160)
(200)
(160)
tw(TBH)
tw(TBL)
TBiIN input high-level pulse width
TBiIN input low-level pulse width
Note : The TBiIN input cycle time requires 4 or more cycles of count iIN input high-level pulse width and the TBiIN input low-level pulse width
respectively require 2 or more cycles of the count source. table are the values when the count source is f(XIN)/4 in high-speed running
(f(XIN) ≤ 40 MHz) and when the count source is f(XIN)/2 unning (f(XIN) ≤ 25 MHz). At this time, the clock source select bit is “0.”
Timer B input (Pulse width measurement m
Limits
Symbol
eter
Unit
ns
ns
ns
ns
ns
ns
Min.
16 × 109
f(XIN)
8 × 109
f(XIN)
8 × 109
f(XIN)
4 × 109
f(XIN)
8 × 109
f(XIN)
4 × 109
f(XIN)
Max.
f(XIN) ≤ 40 MHz
f(XIN) ≤ 25 MHz
f(XIN) ≤ 40 MHz
f(XIN) ≤ 25 MHz
f(XIN) ≤ 40 MHz
f(XIN) ≤ 25 MHz
(400)
(320)
(200)
(160)
(200)
(160)
tc(TB)
TBiIN input cycle
tw(TBH)
tw(TBL)
TBiIN input high-level pulse width
TBiIN input low-level pulse width
Note : The TBiIN input cycle time requires 4 or more cycles of count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width
respectively require 2 or more cycles of the count source. The limits in the table are the values when the count source is f(XIN)/4 in high-speed running
(f(XIN) ≤ 40 MHz) and when the count source is f(XIN)/2 in low-speed running (f(XIN) ≤ 25 MHz). At this time, the clock source select bit is “0.”
A-D trigger input
Limits
Symbol
Parameter
Unit
Min.
1000
125
Max.
tc(AD)
tw(ADL)
ADTRG input cycle time (minimum allowable trigger)
ADTRG input low-level pulse width
ns
ns
85
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Limits
Symbol
Parameter
Unit
Min.
200
100
100
Max.
80
tc(CK)
CLKi input cycle time
ns
ns
ns
ns
ns
ns
ns
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
CLKi input high-level pulse width
CLKi input low-level pulse width
TXDi output delay time
TXDi hold time
0
20
90
RXDi input setup time
RXDi input hold time
External interrupt INTi input
Limits
Symbol
Parameter
Unit
Min.
250
250
Max.
tw(INH)
tw(INL)
INTi input high-level pulse width
INTi input low-level pulse width
ns
ns
tc(TB)
tw(TBH)
TBiIN input
tw(ADL)
ADTRG input
tc(CK)
CKH)
CLKi
tw(CKL)
th(C - Q)
TxDi
RxDi
th(C - D)
td(C - Q)
tsu(D - C)
tw(INL)
INTi input
tw(INH)
Test conditions
• Vcc = 5 V±10 %
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V,VOH = 2.0 V,CL = 100 pF
86
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
READY, HOLD TIMING
Timing requirements (VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 40 MHz when the clock source select bit = “0” , unless
otherwise noted)
The rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted.
Limits
Symbol
Parameter
Unit
Min.
42
42
0
Max.
tsu(RDY-φ1)
tsu(HOLD-φ1)
th(φ1-RDY)
RDY input setup time
HOLD input setup time
RDY input hold time
HOLD input hold time
ns
ns
ns
ns
th(φ1-HOLD)
0
: f(XIN) = 20 MHz when the clock source select bit = “1”.
Switching characteristics (VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 40 MHz when the clock source select bit =
“0” , unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Max.
50
td(φ1-HLDA)
HLDA output delay time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
pxz(HLDA-RDZ)
Floating start delay time (at hold state)
Floating start delay time (at hold state)
50
pxz(HLDA-WRZ)
50
pxz(HLDA-BHEZ) Floating start delay time (at hold state)
Floating start delay time (at hold state)
50
pxz(HLDA-AZ)
50
t
pxz(HLDA-DLZ/DHZ) Floating start delay time (at hold state)
50
t
t
t
t
pzx(HLDA-RDZ)
Floating release delay time (at hold state)
Floating release delay time (at hold state)
0
0
0
0
0
pzx(HLDA-WRZ)
pzx(HLDA-BHEZ) Floating release delay time (at hold state)
Floating release delay time (at hold state)
pzx(HLDA-AZ)
t
pzx(HLDA-DLZ/DHZ) Floating release delay time (at hold state)
: f(XIN) = 20 MHz when the clock source select bit = “1”.
87
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
RDY input (when 3-φ access in high-speed running)
φ1
RD,WR
RDY input
tsu(RDY-φ1)
th(φ1-RDY)
✽ RDY input is always sampled at the falling edge of φ1 just before the RD and WR signals’ rise regus mode and the number of waits.
HOLD input
φ1
tsu(HOLD-φ1)
th(φ1-HOLD)
HOLD input
HLDA output
RD
td(φ1-HLDA)
tpzx(HLDA-RDZ)
tpzx(HLDA-WRZ)
tpzx(HLDA-BHE)
tpzx(HLDA-AZ)
tpxz(HLDA-RDZ)
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
tpxz(HLDA-WRZ)
tpxz(HLDA-BHE)
tpxz(HLDA-AZ)
WR
BHE output
A0–A7 output
A8–A15 output
A16–A23 output
tpzx(HLDA-DLZ/DHZ)
tpxz(HLDA-DLZ/DHZ)
D0–D7 output
D8–D15 output
(BYTE =“L”)
Test conditions
• VCC = 5 V±10 %
• RDY input, HOLD input : VIL = 1.0 V, VIH = 4.0 V
• HLDA output : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
88
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing requirements (VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 40 MHz when the clock source select bit = “0”✽, unless
otherwise noted)
✽ The rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted.
Single-chip mode
Limits
Symbol
Parameter
Unit
Min.
25
Max.
tc
External clock input cycle time (Note 1)
ns
ns
ns
ns
ns
ns
ns
tw(H)
External clock input high-level pulse width (Note 2)
External clock input low-level pulse width (Note 2)
External clock rise time
tc/2 – 8
tc/2 – 8
tw(L)
tr
8
8
tf
External clock fall time
tsu(PiD–E)
th(E–PiD)
Port Pi input setup time (i = 0—11)
Port Pi input hold time (i = 0—11)
60
0
✽: f(XIN) = 20 MHz when the clock source select bit = “1”
Notes 1: When the clock source select bit = “1”, tc’s minimum limit is 50 ns.
2: When the clock source select bit = “1”, set tw(H)/tc and tw(L)/tc ratios to 45 to 55 %.
Switching characteristics (VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 40 Mclock source select bit = “0”✽, unless
otherwise noted)
(Single-chip mode)
Limits
Symbol
Parameter
Unit
ns
Min.
Max.
60
td(E–PiQ)
Port Pi data output delay time (i = 0—11)
✽: f(XIN) = 20 MHz when the clock source select bit = “1”
tr
tw(H)
tw(L)
f(XIN)
E
td(E – PiQ)
th(E – PiD)
Port Pi output (i = 0—11)
tsu(PiD – E)
Port Pi input
(i = 0—11)
Test conditions
• VCC = 5 V±10 %
• Intput timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
89
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing requirements (VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz when the clock source select bit = “0” , unless
otherwise noted)
✽ The rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted.
Memory expansion and Microprocessor mode : Low-speed running
Limits
Symbol
Parameter
Unit
Min.
40
Max.
tc
External clock input cycle time (Note 1)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tw(H)
External clock input high-level pulse width (Note 2)
External clock input low-level pulse width (Note 2)
External clock rise time
tc/2 – 8
tc/2 – 8
tw(L)
tr
8
8
tf
External clock fall time
tsu(DH-RD)
tsu(DL-RD)
tsu(PiD–RD)
th(RD-DH)
th(RD-DL)
th(RD–PiD)
High-order data input setup time (BYTE = “L”)
Low-order data input setup time
30
30
60
0
Port Pi input setup time (i = 4—9, 11)
High-order data input hold time (BYTE = “L”)
Low-order data input hold time
0
Port Pi input hold time (i = 4—9, 11)
0
60 (2-φ access)
tsu(A–DL/DH)
tsu(CS–DL/DH)
tsu(LA–DL)
Data setup time with address stabilized (Note 3)
Data setup time with chip select stabilized (Note 3)
Data setup time with address stabilized (Note
140 (3-
220 (4-
φ
φ
access)
access)
ns
ns
ns
60 (2-φ access)
140 (3-
220 (4-
φ
φ
access)
access)
55 (2-φ access)
135 (3-
215 (4-
φ
φ
access)
access)
: f(XIN) = 12.5 MHz when the clock source selet bit = “
Notes 1: When the clock source select bit = “1”, tc’s mis 80 ns.
2: When the clock source select bit = “1”, stw(L)/tc ratios to 45 to 55 %.
3: Since the values depend on external equency f(XIN), calculate them using the bus timing data formula on the page after
the next page.
90
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Switching characteristics (VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz when the clock source select bit = “0” ,
unless otherwise noted)
Memory expansion and Microprocessor mode : Low-speed running
2-φ access
3-φ access
4-φ access
Symbol
Parameter
Unit
Min. Max. Min. Max. Min. Max.
tw(φH), tw(φL)
td(φ1–WR)
φ high-level pulse width, φ low-level pulse width (Note)
20
–7
–7
60
60
15
15
8
20
–7
–7
140
140
15
15
8
20
–7
–7
140
140
95
95
55
95
95
55
95
95
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
___
WR output delay time
12
12
12
12
12
12
td(φ1–RD)
__
tw(WR)
__
RD output delay time
___
WR low-level pulse width (Note)
RD low-level pulse width (Note)
Address output delay time (Note)
Address output delay time (Note)
tw(RD)
td(A–WR)
td(A–RD)
td(A–ALE)
Address output delay time (Note)
____
td(BHE–WR)
td(BHE–RD)
td(BHE–ALE)
td(CS–WR)
td(CS–RD)
td(CS–ALE)
BHE output delay time (Note)
15
15
8
15
15
____
BHE output delay time (Note)
____
BHE output delay time (Note)
Chip select output delay time (Note)
Chip select output delay time (Note)
Chip select output delay time (Note)
Data output delay time
15
1
15
8
td(WR–DLQ/DHQ)
35
30
35
30
35
30
tpxz(WR–DLZ/DHZ)
Floating start delay time (Note)
ALE output delay time
td(ALE–WR)
td(ALE–RD)
tw(ALE)
4
4
4
4
4
4
ALE output delay time
ALE pulse width (Note)
22
10
10
10
10
10
10
15
0
22
10
10
10
10
10
10
15
0
62
10
10
10
10
10
10
15
0
th(WR–A)
Address hold time (Note)
th(RD–A)
Address hold time (Note)
th(WR–BHE)
th(RD–BHE)
th(WR–CS)
th(RD–CS)
BHE hold time (Note)
BHE hold time (Note)
Chip select hold time (Note)
Chip select hold time (Note)
Data hold time (Note)
th(WR–DLQ/DHQ)
tpzx(WR–DLZ/DHZ)
Floating release delay
Address output del)
Address output ote)
Address oute (Note)
Address hold
td(LA–WR)
12
12
5
12
12
5
92
92
52
25 (Note)
td(LA–RD)
td(LA–ALE)
th(ALE–LA)
tpxz(RD–DLZ)
tpzx(RD–DLZ)
td(WR–PiQ)
9
9
Floating start dey time
5
5
5
Floating release delay time (Note)
Port Pi data output delay time (i = 4—9, 11)
18
18
18
60
60
60
: f(XIN) = 12.5 MHz when the clock source selet bit = “1”
Note: Since the values depend on external clock input frequency f(XIN), calculate them using the bus timing data formula on the next page.
91
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus timing data formulas
Memory expansion and Microprocessor mode : Low-speed running (VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) ≤ 25 MHz when
the clock source select bit = “0” , unless otherwise noted)
Symbol
Parameter
Data setup time with address stabilized
Data setup time with chip select stabilized
φ high-level pulse width, f low-level pulse width
2-φ access
3 × 109
3-φ access
5 × 109
4-φ access
7 × 109
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu(A–DL/DH)
tsu(CS–DL/DH)
tw(φH), tw(φL)
– 60
– 60
– 60
f(XIN)
f(XIN)
f(XIN)
3 × 109
f(XIN)
1 × 109
f(XIN)
2 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 ×
109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
3 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
5 × 109
f(XIN)
7 × 109
f(XIN)
– 60
– 20
– 20
– 25
– 25
– 25
– 32
– 25
– 25
– 32
– 18
– 30
– 30
– 30
– 30
– 30
– 30
– 25
– 10
– 65
– 28
– 28
– 35
– 60
– 60
___
___
4 × 109
f(XIN)
__
__
tw(WR), tw(RD) WR, RD low-level pulse width
– 20
3 × 109
f(XIN)
3 × 109
f(XIN)
3 × 109
f(XIN)
3 × 109
f(XIN)
3 × 109
f(XIN)
3 × 109
f(XIN)
3 × 109
f(XIN)
3 × 109
f(XIN)
td(A–WR)
Address output delay time
Address output delay time
Address output delay time
– 25
– 25
– 65
– 25
– 25
– 65
– 25
– 25
– 65
– 18
td(A–RD)
td(A–ALE)
td(BHE–WR)
td(BHE–RD)
td(BHE–ALE)
td(CS–WR)
td(CS–RD)
td(CS–ALE)
tw(ALE)
____
BHE output delay time
____
BHE outupt delay time
____
BHE output delay time
Chip select output delay time
Chip select output delay time
Chip select output delay time
ALE pulse width
3 × 109
f(XIN)
2 × 109
f(XIN)
th(WR–A)
Address hold time
th(RD–A)
Address hold time
____
td(WR–BHE)
td(RD–BHE)
td(WR–CS)
td(RD–CS)
BHE hold time
____
BHE hold time
Chip select hold time
Chip select holt time
t
h(WR–DLQ/DHQ)
Data hold time
t
pxz(WR–DLZ/DHZ)
Floating start delay time
Data setup time with address stabilized
Address output delay time
Address output delay time
Address output delay time
7 × 109
f(XIN)
3 × 109
f(XIN)
3 × 109
f(XIN)
2 × 109
f(XIN)
5 × 109
f(XIN)
– 65
– 28
– 28
– 28
– 15
tsu(LA–DL)
td(LA–WR)
td(LA–RD)
– 65
1 × 109
f(XIN)
td(LA–ALE)
th(ALE–LA)
tpzx(RD–DLZ)
1 × 109
f(XIN)
ns
ns
Address hold time
1 × 109
f(XIN)
Floating release delay time
– 22
✽: f(XIN) ≤ 12.5 MHz when the clock source select bit = “1”
Note: When the clock source select bit is “1”, regard f(XIN) in tables as 2·f(XIN).
92
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 2-φ access in low-speed running <Write>)
tw(H) tw(L)
tr
tf
tc
f(XIN)
tw(φL)
φ1
tw(φH)
td(φ1-WR)
td(φ1-WR)
RD
WR
tw(WR)
td(ALE-WR)
tw(ALE)
ALE output
BHE output
td(BHE-WR)
th(WR-BHE)
td(BHE-
td
th(WR-A)
A0 to A7 output
A8 toA15 output
A16 toA23 output
Address
LE)
td(CS-WR)
th(WR-CS)
Chip select
CS0 to CS4 output
td(CS-ALE)
td(WR-DLQ/DHQ)
Output data
th(WR-DLQ/DHQ)
Hi-Z
D0 to D7 output
D8 to D15 output (BYTE L”)
tpxz(WR-DLZ/DHZ)
th(WR-DLQ)
tpzx(WR-DLZ/DHZ)
td(WR-DLQ)
Data
td(LA-WR)
Address
D0/LA0 to D7/LA7 output
(multiplex bus (Note))
th(ALE-LA)
td(LA-ALE)
td(WR-PiQ)
Port Pi output
Note: These become a multiplex bus only when all of the following conditions are satisfied:
• BYTE = “H”
• Multiplex bus select bit = “1”
• While the address which corresponds to chip select signal CS4 is accessed
Test conditions (except Port Pi, f(XIN))
• VCC = 5 V±10 %
Test conditions (Port Pi, f(XIN))
• VCC = 5 V±10 %
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF • Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Data input : VIL = 0.8 V, VIH = 2.5 V • Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
93
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 2-φ access in low-speed running <Read>)
t
w(H)
t
w(L)
t
r
t
f
t
c
f(XIN
)
t
w(φL)
φ1
tw(φH)
t
d(φ1-RD)
td(φ1-RD)
RD
t
w(RD)
WR
t
w(ALE)
t
d(ALE-RD)
ALE output
BHE output
t
d(BHE-RD)
E)
t
d(BHE-ALE)
t
d(A-RD)
t
h(RD-A)
A
A
A
0—
A
A
A
7
output
15 output
23 output
A
8—
16—
t
d(A-ALE)
t
d(
th(RD-CS)
ip select
CS0—CS4 output
t
(CS-DL/DH)
su(A-DL/DH)
t
su(DL/DH-RD)
Input data
t
h(RD-DL/DH)
D
0—
D
7
input
D
8—
D
15 input (BYTE = “L”)
t
d(LA-RD)
Address
tpzx(RD-DLZ)
t
pxz(RD-DLZ)
LA0—LA7 output (D0/LA0—A7)
(multiplex bus (Note))
t
d(LA-ALE)
t
su(DL-RD)
t
h(ALE-LA)
t
h(RD-DL)
t
su(LA-DL)
D
0—D7 input
Data
(multiplex bus (Note))
t
su(PiD-RD)
Input data
t
h(RD-PiD)
Port Pi input
Note: These become a multiplex bus only when all of the following conditions are satisfied:
• BYTE = “H”
• Multiplex bus select bit = “1”
• While the address which corresponds to chip select signal CS4 is accessed
Test conditions (Port Pi, f(XIN))
• VCC = 5 V±10 %
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, C
Test conditions (except Port Pi, f(XIN))
• VCC = 5 V±10 %
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, C
• Data input : VIL = 0.8 V, VIH = 2.5 V
L = 100 pF
L
= 100 pF
94
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 3-φ access in low-speed running <Write>)
tw(H) tw(L)
tr
tf
tc
f(XIN)
tw(φL)
φ1
tw(φH)
td(φ1-WR)
td(φ1-WR)
RD
WR
tw(WR)
tw(ALE)
td(ALE-WR)
ALE output
BHE output
td(BHE-WR)
th(WR-BHE)
td(BHE-ALE)
td(A-WR)
th(WR-A)
A0—A7 output
A8—A15 output
A16—A23 output
Address
WR)
th(WR-CS)
Chip select
CS0—CS4 output
td(CS-ALE)
td(WR-DLQ/DHQ)
th(WR-DLQ/DHQ)
D0—D7 output
D8—D15 output (BYTE = “L”)
Output data
tpzx(WR-DLZ/DHZ)
td(WR-DLQ)
tpxz(WR-DLZ/DHZ)
th(WR-DLQ)
td(LA-WR)
D0/LA0—D7/LA7 output
(multiplex bus (Note))
Address
Data
th(ALE-LA)
td(LA-ALE)
td(WR-PiQ)
Port Pi output
Note: These become a multiplex bus only when all of the following conditions are satisfied:
•BYTE = “H”
•Multiplex bus select bit = “1”
•While the address which corresponds to chip select signal CS4 is accessed
Test conditions (Port Pi, f(XIN))
• VCC = 5 V±10 %
Test conditions (except Port Pi, f(XIN))
• VCC = 5 V±10 %
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
• Data input : VIL = 0.8 V, VIH = 2.5 V
95
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 3-φ access in low-speed running <Read>)
tw(H) tw(L)
tr
tf
tc
f(XIN)
tw(φL)
φ1
tw(φH)
td(φ1-RD)
td(φ1-RD)
RD
tw(RD)
WR
tw(ALE)
td(ALE-RD)
ALE output
BHE output
td(BHE-RD)
th(RD-BHE)
td(BHE-ALE)
td(A-RD)
th(RD-A)
A0—A7 output
A8—A15 output
A16—A23 output
Address
td(A-ALE)
td(C
th(RD-CS)
Chip select
CS0—CS4 output
tsu(CS-DL/DH)
ttsu(A-DL/DH)
tsu(DL/DH-RD)
Input data
th(RD-DL/DH)
D0—D7 input
D8—D15 input (BYTE = “L”)
td(LA-RD)
tpxz(RD-DLZ)
tpzx(RD-DLZ)
LA0—LA7 output
(D0/LA0—D7/LA7)
(multiplex bus (Note))
Address
td(LA-ALE)
tsu(DL-RD)
th(ALE-LA)
th(RD-DL)
tsu(LA-DL)
D0—D7 input
(multiplex bus (Note))
Data
tsu(PiD-RD)
th(RD-PiD)
Input data
Port Pi input
Note: These become a multiplex bus only when all of the following conditions are satisfied:
• BYTE = “H”
• Multiplex bus select bit = “1”
• While the address which corresponds to chip select signal CS4 is accessed
Test conditions (Port Pi, f(XIN))
• VCC = 5 V±10 %
Test conditions (except Port Pi, f(XIN))
• VCC = 5 V±10 %
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
• Data input : VIL = 0.8 V, VIH = 2.5 V
96
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 4-φ access in low-speed running <Write>)
tw(H) tw(L)
tr
tf
tc
f(XIN)
tw(φL)
φ1
tw(φH)
td(φ1-WR)
td(φ1-WR)
RD
WR
tw(WR
tw(ALE)
td(ALE-WR)
ALE output
td(BHE-WR)
th(WR-BHE)
BHE output
td(BHE-ALE)
td(A-WR)
th(WR-A)
A0–A7 output
A8–A15 output
A16–A23 output
Address
t
th(WR-CS)
Chip select
CS0–CS4 output
td(CS-ALE)
td(WR-DLQ/DHQ)
th(WR-DLQ/DHQ)
tpxz(WR-DLZ/DHZ)
th(WR-DLQ)
D0–D7 output
D8–D15 output (BYTE = “L”)
Output data
tpzx(WR-DLZ/DHZ)
td(WR-DLQ)
th(ALE-LA)
td(LA-WR)
D0/LA0–D7/LA7 output
(multiplex bus (Note))
Data
Address
td(LA-ALE)
td(RD-PiQ)
Port Pi output
Note: These become a multiplex bus only when all of the following conditions are satisfied:
• BYTE = “H”
• Multiplex bus select bit = “1”
• While the address which corresponds to chip select signal CS4 is accessed
Test conditions (Port Pi, f(XIN))
• VCC = 5 V±10 %
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
Test conditions (except Port Pi, f(XIN))
• VCC = 5 V±10 %
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
• Data input : VIL = 0.8 V, VIH = 2.5 V
97
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 4-φ access in low-speed running <Read>)
t
w(H)
t
w(L)
t
r
t
f
tc
f(XIN
)
t
w(φL)
φ1
tw(φH)
t
d(φ1
-RD)
td(φ1-RD)
RD
t
w(RD)
WR
t
w(ALE)
t
d(ALE-RD)
ALE output
BHE output
t
d(BHE-RD)
d(BHE-ALE)
t
h(RD-BHE)
t
t
d(A-RD)
t
h(RD-A)
A
A
A
0—
A
A
A
7
output
15 output
23 output
Address
8—
16—
t
d(A-A
t
h(RD-CS)
Chip select
CS0—CS4 output
ALE)
t
su(CS-DL/DH)
su(A-DL/DH)
t
t
su(DL/DH-RD)
Input data
t
h(RD-DL/DH)
D
0—
D
7
input
D
8—
D
15 input (BYTE =“L
t
pxz(RD-DLZ)
t
d(LA-RD)
Address
t
pzx(RD-DLZ)
LA0—LA7 output (D0/LA0—D7A7)
(multiplex bus (Note))
t
h(ALE-LA)
t
su(DL-RD)
t
d(LA-ALE)
t
h(RD-DL)
t
su(LA-DL)
D
0—D7 input
Data
(multiplex bus (Note))
t
su(PiD-RD)
Input data
th(RD-PiD)
Port Pi input
Note: These become a multiplex bus only when all of the following conditions are satisfied:
• BYTE = “H”
• Multiplex bus select bit = “1”
• While the address which corresponds to chip select signal CS4 is accessed
Test conditions (Port Pi, f(XIN))
Test conditions (except Port Pi, f(XIN))
• VCC = 5 V±10 %
• VCC = 5 V±10 %
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, C
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, C
• Data input : VIL = 0.8 V, VIH = 2.5 V
L = 100 pF
L
= 100 pF
98
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing requirements (VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN)=40 MHz when the clock source select bit = “0” , unless
otherwise noted)
✽ The rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted.
Memory expansion and Microprocessor mode : High-speed running
Limits
Symbol
Parameter
External clock input cycle time (Note 1)
Unit
Min.
25
Max.
tc
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tw(H)
External clock input high-level pulse width (Note 2)
External clock input low-level pulse width (Note 2)
External clock rise time
tc/2 – 8
tc/2 – 8
tw(L)
tr
8
8
tf
External clock fall time
tsu(DH–RD)
tsu(DL–RD)
tsu(PiD–RD)
th(RD–DH)
th(RD–DL)
th(RD–PiD)
High-order data input setup time (BYTE = “L”)
Low-order data input setup time
30
30
0
Port Pi input setup time (i = 4—9, 11)
High-order data input hold time (BYTE = “L”)
Low-order data input hold time
Port Pi input hold time (i = 4—9, 11)
65 (3-φ access)
110 (4-φ access)
160 (5-φ access)
65 (3-φ access)
110 (4-φ access)
160 (5-φ access)
50 (3-φ access)
100 (4-φ access)
150 (5-φ access)
tsu(A–DL/DH)
tsu(CS–DL/DH)
tsu(LA–DL)
Data setup time with address stabilized (Note 3)
Data setup time with chip select stabilized (Note 3)
Data setup time with address stabilized (Note 3
ns
ns
ns
: f(XIN) = 20 MHz when the clock source selet bit = “1”
Notes 1: When the clock source select bit = “1”, tc’s mis 50 ns.
2: When the clock source select bit = “1”, stw(L)/tc ratios to 45 to 55 %.
3: Since the values depend on external equency f(XIN), calculate them using the bus timing data formula on the page after
the next page.
99
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Switching characteristics (VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 40 MHz when the clock source select bit =
“0” , unless otherwise noted)
Memory expansion and Microprocessor mode : High-speed running
3-φ access
4−φ access
5-φ access
Symbol
Parameter
Unit
Min. Max. Min. Max. Min. Max.
tw(φH), tw(φL)
td(φ1–WR)
φ high-level pulse width, φ low-level pulse width
(Note)
5
5
5
–7
–7
130
130
45
45
35
45
45
35
45
45
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
___
WR output delay time
___
–7
–7
55
55
25
25
10
25
25
10
25
2
12
12
–7
–7
80
80
45
45
35
45
45
45
35
12
12
12
12
td(φ1–RD)
__
tw(WR)
__
RD output delay time
___
WR low-level pulse width
___
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
tw(RD)
RD low-level pulse width
Address output delay time
Address output delay time
td(A–WR)
td(A–RD)
td(A–ALE)
Address output delay time
____
td(BHE–WR)
td(BHE–RD)
td(BHE–ALE)
td(CS–WR)
td(CS–RD)
td(CS–ALE)
BHE output delay time
____
BHE output delay time
____
BHE output delay time
Chip select output delay time
Chip select output delay time
Chip select output delay time
Data output delay time
Floating start delay time
ALE output delay time
ALE output delay time
ALE pulse width
td(WR–DLQ/DHQ)
35
30
35
30
35
30
tpxz(WR–DLZ/DHZ)
(
td(ALE–WR)
td(ALE–RD)
tw(ALE)
4
4
4
4
4
4
e)
Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
10
10
10
10
10
10
10
15
0
35
10
10
10
10
10
10
15
0
35
10
10
10
10
10
10
15
0
th(WR–A)
Address hold time
th(RD–A)
Address hold time
____
th(WR–BHE)
th(RD–BHE)
th(WR–CS)
th(RD–CS)
BHE hold time
____
BHE hold time
Chip select hold time
Chip select hold time
th(WR–DLQ/DHQ)
Data hold time
tpzx(WR–DLZ/DHZ)
Floating release delay
Address output del
Address output
Address oute
Address hold
td(LA–WR)
(Note)
(Note)
(Note)
(Note)
15
15
5
40
40
30
10
40
40
30
10
td(LA–RD)
td(LA–ALE)
th(ALE–LA)
tPXZ(RD–DLZ)
tPZX(RD–DLZ)
td(WR–PiQ)
10
Floating start dely time
Floating release delay time
Port Pi data output delay time (i = 4—9, 11)
5
5
5
(Note)
15
15
15
60
60
60
: f(XIN) = 20 MHz when the clock source selet bit = “1”
Note: Since the values depend on external clock frequency f(XIN), calculate them by using the bus timing data formulas on the next page.
100
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus timing data formulas
Memory expansion and Microprocessor mode : High-speed running (VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) ≤ 40 MHz when
the clock source select bit = “0” , unless otherwise noted)
Symbol
tsu(A–DL/DH)
tsu(CS–DL/DH)
tw(φH), tw(φL)
Parameter
Data setup time with address stabilized
Data setup time with chip select stabilized
3-φ access
5 × 109
4-φ access
7 × 109
5-φ access
9 × 109
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
– 60
– 65
– 65
f(XIN)
f(XIN)
f(XIN)
5 × 109
f(XIN)
1 × 109
f(XIN)
3 × 109
f(XIN)
2 × 109
f(XIN)
2 × 109
f(XIN)
1 × 109
f(XIN)
2 ×
09
XIN)
2 × 109
f(XIN)
2 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
7 × 109
f(XIN)
9 × 109
f(XIN)
– 60
– 20
– 20
– 25
– 25
– 25
– 15
– 25
– 25
– 15
– 15
– 15
– 15
– 15
– 15
– 15
– 15
– 10
+ 5
– 65
– 65
φ high-level pulse width, φ low-level pulse width
4 × 109
f(XIN)
3 × 109
f(XIN)
3 × 109
f(XIN)
109
N)
× 109
f(XIN)
3 × 109
f(XIN)
2 × 109
f(XIN)
3 × 109
f(XIN)
6 × 109
f(XIN)
___ ___
__
__
tw(WR), tw(RD) WR, RD low-level pulse width
– 20
– 30
– 30
– 15
– 30
– 30
– 15
– 30
– 30
– 15
– 15
– 20
td(A–WR)
Address output delay time
Address output delay time
Address output delay time
td(A–RD)
td(A–ALE)
td(BHE–WR)
td(BHE–RD)
td(BHE–ALE)
td(CS–WR)
td(CS–RD)
td(CS–ALE)
tw(ALE)
____
BHE outuput delay time
____
BHE outuput delay time
____
BHE outuput delay time
Chip select output delay time
Chip select output delay time
Chip select output delay time
ALE pulse width
3 × 109
f(XIN)
2 × 109
f(XIN)
2 × 109
f(XIN)
th(WR–A)
Address hold time
th(RD–A)
Address hold time
____
td(WR–BHE)
td(RD–BHE)
td(WR–CS)
td(RD–CS)
BHE hold time
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
____
BHE hold time
Chip select hold time
Chip select hold time
t
h(WR–DLQ/DHQ)
Data hold time
1 × 109
f(XIN)
tpxz(WR–DLZ/DHZ)
Floating start delay time
Data setup time with address stabilized
Address outuput delay time
Address outuput delay time
Address outuput delay time
Address hold time
5 × 109
f(XIN)
2 × 109
f(XIN)
2 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
7 × 109
f(XIN)
3 × 109
f(XIN)
3 × 109
f(XIN)
2 × 109
f(XIN)
9 × 109
f(XIN)
tsu(LA–DL)
td(LA–WR)
td(LA–RD)
– 75
– 35
– 35
– 20
– 15
– 10
– 75
– 35
– 35
– 20
– 75
td(LA–ALE)
td(ALE–LA)
tpzx(RD–DLZ)
Floating release delay time
✽: f(XIN) ≤ 20 MHz when the clock source select bit = “1”
Note: When the clock source select bit is “1”, regard f(XIN) in tables as 2·f(XIN).
101
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 3-φ access in high-speed running <Write>)
t
w(H)
t
w(L)
t
r
t
f
tc
f(XIN
)
t
w(φL)
φ1
t
w(φH)
t
d(φ1-WR)
td(φ1-WR)
RD
WR
t
w(WR
t
w(ALE)
t
d(ALE-WR)
ALE output
BHE output
t
d(BHE-WR)
t
h(WR-BHE)
t
d(BHE-ALE
td(A-
t
h(WR-A)
A
A
A
0—
A
A
A
7
output
15 output
23 output
8—
Address
16—
S-WR)
t
h(WR-CS)
Chip select
CS0—CS4 output
t
d(CS-ALE)
t
d(WR-DLQ/DHQ)
t
h(WR-DLQ/DHQ)
D
0—
D
7
output
Output data
D
8—
D
15 output (B
t
pzx(WR-DLZ/DHZ)
t
pxz(WR-DLZ/DHZ)
t
d(WR-DLQ)
t
d(LA-WR)
t
h(WR-DLQ)
D0/LA0—D7/LA7 output
(multiplex bus (Note))
Address
Data
t
d(LA-ALE)
th(ALE-LA)
t
d(WR-PjQ)
Port Pi output
Note: These become a multiplex bus only when all of the following conditions are satisfied:
• BYTE = “H”
• Multiplex bus select bit = “1”
• While the address which corresponds to chip select signal CS4 is accessed
Test conditions (Port Pi, f(XIN))
Test conditions (except Port Pi, f(XIN))
• VCC = 5 V±10 %
• VCC = 5 V±10 %
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, C
L = 100 pF
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
• Data input : VIL = 0.8 V, VIH = 2.5 V
102
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 3-φ access in high-speed running <Read>)
t
w(H)
t
w(L)
t
r
t
f
tc
f(XIN
)
t
w(φL)
φ1
tw(φH)
t
d(φ1-RD)
td(φ1-RD)
RD
t
w(RD)
WR
t
w(ALE)
t
d(ALE-RD)
ALE output
BHE output
t
d(BHE-RD)
t
h(RD-BHE)
t
d(BHE-ALE)
d(A-RD)
t
t
h(RD-A)
A
A
A
0—
A
A
A
7
output
15 output
23 output
Address
8—
16—
t
d(
t
h(RD-CS)
Chip select
CS0—CS4 output
(CS-ALE)
t
su(CS-DL/DH)
su(A-DL/DH)
t
su(DL/DH-RD)
Input data
t
t
h(RD-DL/DH)
D
0—
D
7
input
D8—
D15 input (
t
pxz (RD-DLZ)
t
d(LA-RD)
t
pzx(RD-DLZ)
LA0—LA
(D /LA0—
(multiplex bus (Note))
7
output
Address
0
D7/LA7)
t
d(LA-ALE)
t
h(ALE-LA)
t
su(DL-RD)
Data
t
h(RD-DL)
t
su (LA-DL)
D
0—D7 input
(multiplex bus (Note))
t
su(PiD-RD)
Input data
t
h(RD-PiD)
Port Pi input
Note: These become a multiplex bus only when all of the following conditions are satisfied:
• BYTE = “H”
• Multiplex bus select bit = “1”
• While the address which corresponds to chip select signal CS
4
is accessed
Test conditions (Port Pi, f(XIN))
Test conditions (except Port Pi, f(XIN))
• VCC = 5 V±10 %
• VCC = 5 V±10 %
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, C
L = 100 pF
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
• Data input : VIL = 0.8 V, VIH = 2.5 V
103
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 4-φ access in high-speed running <Write>)
t
w(H)
t
w(L)
t
r
t
f
tc
f(XIN
)
t
w(φL)
φ1
t
w(φH)
t
d(φ1-WR)
td(φ1-WR)
RD
WR
t
w(W
t
w(ALE)
t
d(ALE-WR)
ALE output
BHE output
t
d(BHE-WR)
t
h(WR-BHE)
t
d(BHE-ALE)
d(A-WR)
t
t
h(WR-A)
A
A
A
0—
A
A
A
7
output
15 output
23 output
8—
Address
16—
t
d
t
t
h(WR-CS)
Chip select
CS0—CS4 output
t
d(CS-ALE)
t
d(WR-DLQ/DHQ)
h(WR-DLQ/DHQ)
D
0—
D
7
output
Output data
D
8—
D
15 output (BYTE = “L”)
t
pzx(WR-DLZ/DHZ)
t
pxz(WR-DLZ/DHZ)
t
d(WR-DLQ)
t
d(LA-WR)
Address
t
h(WR-DLQ)
D0/LA0—D7/LA7 output
(multiplex bus (Note))
Data
t
h(ALE-LA)
t
d(LA-ALE)
t
d(WR-PiQ)
Port Pi output
Note: These become a multiplex bus only when all of the following conditions are satisfied:
• BYTE = “H”
• Multiplex bus select bit = “1”
• While the address which corresponds to chip select signal CS4 is accessed
Test conditions (Port Pi, f(XIN))
Test conditions (except Port Pi, f(XIN))
• VCC = 5 V±10 %
• VCC = 5 V±10 %
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, C
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, C
• Data input : VIL = 0.8 V, VIH = 2.5 V
L = 100 pF
L
= 100 pF
104
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 4-φ access in high-speed running <Read>)
t
w(H)
t
w(L)
t
r
t
f
tc
f(XIN
)
t
w(φL)
φ1
t
w (φH)
t
d(φ1
-RD)
td(φ1-RD)
RD
t
w(RD)
WR
t
w(ALE)
t
d(ALE-RD)
ALE output
BHE output
t
d(BHE-RD)
t
h(RD-BHE)
t
d(BHE-ALE)
td(A-RD)
t
h(RD-A)
A
A
A
0—
A
A
A
7
output
15 output
23 output
Address
8—
16—
t
d(A-ALE
t
t
h(RD-CS)
CS0–CS4 output
Chip select
LE)
t
t
su(CS-DL/DH)
su(A-DL/DH)
t
su(DL/DH-RD)
Input data
t
h(RD-DL/DH)
D
0
–D
7 input
D
8–D15 input (BYTE = “L”)
t
pxz(RD-DLZ)
t
d(LA-RD)
t
pzx(RD-DLZ)
LA
(D
(multiplex bus (Note))
0
–LA
0
7
output
0/LA –D
7/LA
7)
Address
t
h(ALE-LA)
t
su(DL-RD)
t
d(LA-ALE)
t
h(RD-DL)
t
su(LA-DL)
D0–D7 input
Data
(multiplex bus (Note))
t
su(PiD-RD)
Input data
t
h(RD-PiD)
Port Pi input
Note: These become a multiplex bus only when all of the following conditions are satisfied:
• BYTE = “H”
• Multiplex bus select bit = “1”
• While the address which corresponds to chip select signal CS4 is accessed
Test conditions (Port Pi, f(XIN))
Test conditions (except Port Pi, f(XIN))
• VCC = 5 V±10 %
• VCC = 5 V±10 %
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, C
• Data input : VIL = 0.8 V, VIH = 2.5 V
L = 100 pF
105
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 5-φ access in high-speed running <Write>)
t
w(H)
t
w(L)
t
r
t
f
tc
f(XIN
)
t
w(φL)
φ1
tw(φH)
t
d(φ1-WR)
t
d(φ1-WR)
RD
WR
t
w(WR)
t
w(ALE)
t
d(ALE-WR)
ALE output
BHE output
t
h(WR-BHE)
t
d(BHE-WR)
t
t
d(BHE-ALE)
d(A-WR)
t
h(WR-A)
A
A
A
0—
A
7
output
15 output
23 output
8—A
Address
16—
A
t
d(A-ALE)
t
h(WR-CS)
t
d(CS-WR
Chip select
CS0—CS4 output
t
h(WR-DLQ/DHQ)
t
d(WR-DLQ/DHQ)
D
0—
D
7
output
Output data
D
8—D
15 output (BYTE = “L”)
t
pzx(WR-DLZ/DHZ)
t
pxz(WR-DLZ/DHZ)
td(WR-DLQ)
t
d(LA-WR)
Address
t
h(WR-DLQ)
D0/LA0—D7/LA7 output
(multiplex bus (Note))
Data
t
h(ALE-LA)
t
d(LA-ALE)
t
d(WR-PiQ)
Port Pi output
Note: These become a multiplex bus only when all of the following conditions are satisfied:
• BYTE = “H”
• Multiplex bus select bit = “1”
• While the address which corresponds to chip select signal CS4 is accessed
Test conditions (Port Pi, f(XIN))
Test conditions (except Port Pi, f(XIN))
• VCC = 5 V±10 %
• VCC = 5 V±10 %
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, C
L = 100 pF
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
• Data input : VIL = 0.8 V, VIH = 2.5 V
106
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 5-φ access in high-speed running <Read>)
t
w(H)
t
w(L)
t
r
t
f
tc
f(XIN
)
t
w(φL)
φ1
t
w(φH)
t
d(φ1-RD)
td(φ1-RD)
RD
t
w(RD)
WR
t
w(ALE)
t
d(ALE-RD)
ALE output
BHE output
t
d(BHE-RD)
t
h(RD-BHE)
t
d(BHE-ALE)
d(A-RD)
t
t
h(RD-A)
A
A
A
0—
A
7
output
15 output
23 output
Address
8—A
16—
A
t
d(A-ALE)
t
d(CS-RD)
t
h(RD-CS)
Chip select
CS0—CS4 output
t
d(
t
t
su(CS-DL/DH)
su(A-DL/DH)
t
su(DL/DH-RD)
Input data
t
h(RD-DL/DH)
D
0—
D
7
input
D8—
D15 input (BYTE = “L”)
t
pxz(RD-DLZ)
t
t
pzx(RD-DLZ)
h(RD-DL)
t
d(LA-RD)
LA0—LA
(D /LA0—
(multiplex bus (Note))
7
output
Address
0
D7/LA7)
t
h(ALE-LA)
t
su(DL-RD)
t
d(LA-ALE)
tsu(LA-DL)
D
0—D7 input
Data
(multiplex bus (Note))
t
su(PiD-RD)
t
h(RD-PiD)
Port Pi input
Input data
Note: These become a multiplex bus only when all of the following conditions are satisfied:
•BYTE = “H”
•Multiplex bus select bit = “1”
•While the address which corresponds to chip select signal CS
4
is accessed
Test conditions (Port Pi, f(XIN))
Test conditions (except Port Pi, f(XIN))
• VCC = 5 V±10 %
• VCC = 5 V±10 %
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, C
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, C
• Data input : VIL = 0.8 V, VIH = 2.5 V
L = 100 pF
L
= 100 pF
107
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
<NOTE> External bus timing when internal memory area is accessed (2-φ access) in high-speed
running
(VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) ≤ 40 MHz when the clock source select bit = “0” )
f (XIN) = 40 MHz
Bus timing
data formula
Symbol
Parameter
Unit
Min.
Max.
1 × 109
f(XIN)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tw(φH), tw(φL)
td(φ1–WR)
td(φ1–RD)
φ high-level pulse width, φ low-level pulse width
5
– 20
___
WR output delay time
–7
–7
5
12
12
___
RD output delay time
1 × 109
– 20
___
__
tw(WR)
WR low-level pulse width
f(XIN)
1 × 109
f(XIN)
2 × 109
f(XIN)
2 × 109
f(XIN)
2 × 109
f(XIN)
2 × 109
f(XIN)
2 × 109
f(XIN)
2 × 109
f(XIN)
2 × 109
f(XIN)
___
__
tw(RD)
RD low-level pulse width
5
– 20
td(A–WR)
Address output delay time
Address output delay time
Address output delay time
25
25
25
10
25
25
10
– 25
td(A–RD)
– 25
td(A–ALE)
– 40
____
td(BHE–WR)
td(BHE–RD)
td(BHE–ALE)
td(CS–WR)
td(CS–RD)
td(CS–ALE)
BHE output delay time
– 25
____
BHE output delay time
– 25
____
BHE output delay time
– 40
Chip select output delay time
Chip select output delay time
Chip select output delay time
Data output delay time
– 25
2 × 109
f(XIN)
2 × 109
f(XIN)
– 25
– 40
————
t
t
d(WR–DLQ/DHQ)
35
1 × 109
+ 5
pxz(WR–DLZ/DHZ) Floating start delay time
30
4
f(XIN)
————
td(ALE–WR)
td(ALE–RD)
tw(ALE)
ALE output delay ti
ALE output dela
ALE pulse width
————
4
1 × 109
– 15
10
10
10
10
10
10
10
15
0
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
1 × 109
f(XIN)
th(WR–A)
Address hold time
Address hold time
– 15
th(RD–A)
– 15
____
td(WR–BHE)
td(RD–BHE)
td(WR–CS)
td(RD–CS)
BHE hold time
– 15
____
BHE hold time
– 15
Chip select hold time
Chip select hold time
Data hold time
– 15
– 15
t
t
h(WR–DLQ/DHQ)
– 10
pzx(WR–DLZ/DHZ) Floating release delay time
————
: f(XIN) ≤ 20 MHz when the clock source select bit = “1”.
: f(XIN) = 20 MHz when the clock source select bit = “1”.
108
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(External bus timing on internal RAM access (2-φ access) in high-speed running)
t
w(H)
t
w(L)
tw(H) tw(L)
t
r
t
f
t
c
t
r
t
f
tc
f(XIN
)
t
w(φL)
tw(φL)
φ1
t
d(φ1-WR)
td(φ1-RD)
t
d(φ1-WR)
td(φ1-RD)
t
w(φH)
t
w(φH)
RD
t
w(RD)
WR
t
w(WR)
ALE)
t
d(ALE-RD)
t
w(ALE)
t
d(ALE-WR)
ALE output
t
h(WR-BHE)
t
h(RD-BHE)
h(RD-A)
t
d(BHE-WR)
td(BHE-RD)
BHE output
t
d(BHE-ALE)
d(A-WR)
t
d(BHE-ALE)
t
t
td(A-RD)
A
A
A
0—
A
7
output
15 output
23 output
8—A
Address
Address
16—
A
t
d(A-ALE)
td(A-ALE)
t
h(WR-CS)
th(RD-CS)
t
d(CS-WR)
td(CS-RD)
CS0—CS4 output
td(CS-ALE)
td(CS-AL
t
h(WR-DLQ/DHQ)
WR-DLQ/DHQ)
Hi-Z
Hi-Z
D
0—
D
7
output
Data
D
8—
D
15 output (BYTE = “L”)
t
pzx(WR-DLZ/DHZ)
t
pxz(WR-DLZ/DHZ)
✽ The value of output data is undefined.
Test conditions
• VCC = 5 V±10 %
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
109
GZZ–SH00–85B<85A0>
Mask ROM number
Date:
7700 FAMILY MASK ROM ORDER CONFIRMATION FORM
SINGLE-CHIP 16-BIT MICROCOMPUTER
M37754M8C-XXXGP
Section head
signature
Supervisor
signature
M37754M8C-XXXHP
MITSUBISHI ELECTRIC
Note : Please fill in all items marked
Responsible
Supervisor
officer
TEL
(
Company
name
)
Customer
Date
issued
Date:
1. Confirmation
Specify the name of the product being ordered.
Three sets of EPROMs are required for each pattern (Check @ in the ax).
If at least two of the three sets of EPROMs submitted contain the idee will produce masks based on this data.
We shall assume the responsibility for errors only if the mask ROe products we produce differ from this data.
Thus, the customer must be especially careful in verifying the ed in the EPROMs submitted.
Checksum code for entire EPROM area
(hexadecimal notation)
EPROM Type :
27512
(1) Set “FF16” in the shaded area.
0000
Address 016 to 1016 are the area for storing the data
on model designation and options.This area must be
written with the data shown below.
(2)
0000
0010
00010
Details for option data are given next in the section
describing the STP instruction option.
1000
FFFF
11000
Address and data are written in hexadecimal notation.
DATA
DATA
60K
Address
8
9
A
B
C
D
E
F
Address
Address
10
Option data
43
2D
FF
FF
FF
FF
FF
FF
4D
33
37
37
35
34
4D
38
0
1
2
3
4
5
6
1FFFF
7
2. STP instruction option
One of the following sets of data should be written to the option data address (1016) of the EPROM you have ordered.
Check @ in the appropriate box.
STP instruction enable
STP instruction disable
Address 1016
Address 1016
0116
0016
3. Mark specification
Mark specification must be submitted using the correct form for the type of package being ordered fill out the appropriate
100P6S Mark Specification Form (for M37754M8C-XXXGP), 100P6Q Mark Specification Form (for M37754M8C-XXXHP)
and attach to the Mask ROM Order Confirmation Form.
4. Comments
100P6S (100-PIN QFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
80
51
81
50
Mitsubishi IC catalog name
Mitsubishi lot number
(6-digit or 7-digit)
100
31
1
30
B. Customer’s Parts Number + Mitsubishi catalog name
80
51
81
50
mer’s Parts Number
te : The fonts and size of characters are standard Mitsubishi type.
Mitsubishi IC catalog name
Note1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard Mitsubishi type.
3 : Customer’s Parts Number can be up to 14 characters : Only 0 ~
,
100
1
9, A ~ Z, +, –, /, (, ), &,
, (periods), (commas) are usable.
.
1
30
C. Special Mark Required
Note1 : If the Special Mark is to be Printed, indicate the desired
layout of the mark in the left figure. The layout will be
duplicated as close as possible.
80
51
81
50
Mitsubishi lot number (6-digit or 7-digit) and Mask ROM
number (3-digit) are always marked.
2 : If the customer’s trade mark logo must be used in the
Special Mark, check the box below.
Please submit a clean original of the logo.
For the new special character fonts a clean font original
(ideally logo drawing) must be submitted.
100
31
1
30
Special logo required
100P6Q (100-PIN LQFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
75
51
76
50
Mitsubishi IC catalog name
Mitsubishi IC catalog name
Mitsubishi lot number
(6-digit or 7-digit)
100
26
1
25
B. Customer’s Parts Number + Mitsubishi catalog name
75
51
76
50
tomer’s Parts Number
ote : The fonts and size of characters are standard Mitsubishi type.
Mitsubishi IC catalog name
Note1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard Mitsubishi type.
3 : Customer’s Parts Number can be up to 12 characters : Only 0 ~
,
Mitsubishi lot
(6-digit
9, A ~ Z, +, –, /, (, ), &,
, (periods), (commas) are usable.
.
100
26
1
25
C. Special Mark Required
Note1 : If the Special Mark is to be Printed, indicate the desired
layout of the mark in the left figure. The layout will be
duplicated as close as possible.
75
51
76
50
Mitsubishi lot number (6-digit or 7-digit) and Mask ROM
number (3-digit) are always marked.
2 : If the customer’s trade mark logo must be used in the
Special Mark, check the box below.
Please submit a clean original of the logo.
For the new special character fonts a clean font original
(ideally logo drawing) must be submitted.
100
26
Special logo required
1
25
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•
•
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
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© 1999 MITSUBISHI ELECTRIC CORP.
New publication, effective Apr. 1999.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
M37754M8C-XXXGP/HP DATA SHEET
Rev.
Rev.
Revision Description
No.
date
1.0 First Edition
971114
1.01 (1) Page 14 is updated. (The previous version of this page cannot be read in.)
980602
(2 ) The following are added:
•MASK ROM ORDER CONFIRMATION FORM
•MARK SPECIFICATION FORM
2.00 (1) For the “valid output polarity select bit for interrupt request (bit 1 at address 1C16)” (three-
phase mode 1), it’s name and function are corrected:
990428
• New bit name in three-phase mode 1: interrupt validity output s
• Corrected function:
0: Timer B2 interrupt request generated at each even-nnderflow of timer B2
1: Timer B2 interrupt request generated at each oddunderflow of timer B2
• Related pages: pages 37, 38, 40
(2) For the following register, it’s internal status t is corrected:
• Target register: processor mode registss 5E16
• Correction: the status of bit 1 is “0”.
• Related page: page 63
)
(3) The names of registers at 5C16, 5D16 are corrected:
• Address 5C16: timer Bgister
• Address 5D16: timee register
• Related page:
(4) For the “timer A write flag (address 4516)”, it’s name and it’s bit name are corrected:
• New register name: timer A write register
• New bit name: timer Ai write bit (i = 0 to 2)
• Related pages: pages 8, 37, 40, 63
(1/1)
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