M37630M4T-XXXFP [RENESAS]

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER; 单片8位CMOS微机

M37630M4T-XXXFP


型号：	M37630M4T-XXXFP
厂家：	RENESAS TECHNOLOGY CORP
描述：	SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单片8位CMOS微机计算机
文件：	总49页 (文件大小：836K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

To all our customers

Regarding the change of names mentioned in the document, such as Mitsubishi

Electric and Mitsubishi XX, to Renesas Technology Corp.

The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas

Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)

Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi

Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names

have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.

Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been

made to the contents of the document, and these changes do not constitute any alteration to the

contents of the document itself.

Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices

and power devices.

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

^MI7^TSU6^BI3^SHI0^MICG^ROCr^Oo^MPUu^TEp^RS

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 24 sources, 24 vectors

Timers

16-bit Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 channels

8-bit Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 channels

Serial I/Os

Clock synchronous. . . . . . . . . . . . . . . . . . . . . . . . . . . 1 channel

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 channel

CAN module

DESCRIPTION

The 7630 group is a single chip 8-bit microcomputer designed with

CMOS silicon gate technology.

Being equipped with a CAN (Controller Area Network) module cir-

cuit, the microcomputer is suited to drive automotive equipments.

The CAN module complies with CAN specification version 2.0, part

B and allows priority-based message management.

In addition to the microcomputers simple instruction set, the ROM,

RAM and I/O addresses are placed in the same memory map to

enable easy programming.

(CAN specification version 2.0, part B) . . . . . . . . . . . 1 channel

A-D converter. . . . . . . . . . . . . . . . . . . . . . . . 8-bits x 8 channels

Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Clock Generating Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Built-in with internal feedback resistor

The built-in ROM is available as mask ROM or One Time PROM.

For development purposes, emulator- and EPROM-type microcom-

puters are available as well.

Power source voltage

(at 10 MHz oscillation frequency). . . . . . . . . . . . . . . 4.0 to 5.5 V

Power dissipation

FEATURES

In high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 mW

(at 8 MHz oscillation frequency, at 5 V power source voltage)

Operating temperature range. . . . . . . . . . . . . . . . . –40 to 85 °C

Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44QFP (44P6N-A)

Basic machine-language instructions . . . . . . . . . . . . . . . . . . 71

Minimum instruction execution time

(at 10 MHz oscillation frequency) . . . . . . . . . . . . . . . . . . 0.2 µs

Memory size

ROM . . . . . . . . . . . . . . . . .16252 bytes (M37630M4T-XXXFP)

RAM . . . . . . . . . . . . . . . . . . .512 bytes (M37630M4T-XXXFP)

APPLICATION

I/O ports

Automotive controls

Programmable I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

PIN CONFIGURATION (TOP VIEW)

22

21

20

19

18

17

16

15

14

13

12

P0₂/AN₂

P0₁/AN₁

P0₀/AN₀

V_REF

34

35

36

37

38

39

40

41

42

43

44

P1₇

P2₀/S_IN

P2₁/S_OUT

P2₂/S_CLK

P2₃/S_RDY

V_SS

M37630M4T-XXXFP

M37630E4T-XXXFP

AV_SS

V_CC

X_OUT

P2₄/UR_XD

P2₅/UT_XD

X_IN

V_SS

P2₆/U_RTS

P2₇/U_CTS

P3₀

RESET

P4₇/KW₇

Package type: 44P6N-A

44-pin plastic molded QFP

Fig. 1

Pin configuration of M37630M4T–XXXFP

1

M37630MXT-XXXFP FUNCTIONAL BLOCK DIAGRAM (PACKAGE: 44P6N-A)

Clock

output

X_OUT

Clock

input

X_IN

Reset

input

RESET

V_CC

17

V_SS

AV_SS

18

16

15

13

14 39

Clock generating circuit

CPU

A (8)

ROM

RAM

WDT

Timer X (16)

Timer Y (16)

Timer 1 (8)

Timer 2 (8)

Timer 3 (8)

X (8)

Y (8)

S (8)

2

PWM

PC_H(8) PC_L(8)

PS (8)

key on

CAN

UART

Serial I/O

A-D Converter

wake up

2

4

4

8

INT₀, INT₁

2

P4 (8)

P3 (5)

P2 (8)

P1 (7)

P0 (8)

3

12 11 10

9

8

7

6

5

4

3

2

1

44

43 42 41 40 38 37 36 35

19

V_REFinput

27 26 25 24 23 22 21 20

34 33 32 31 30 29 28

I/O port P4

I/O port P3

I/O port P2

I/O port P1

I/O port P0

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PIN DESCRIPTION

Table 1: Pin description

Pin

Name

Input/Output

Description

Power source

voltage

V_CC, V_SS

Power supply pins; apply 4.0 to 5.5 V to V_CCand 0 V to V_SS

Analog power

source voltage

AV_SS

Ground pin for A-D converter. Connect to V_SS

Reset pin. This pin must be kept at “L” level for more than 2 µs, to enter the reset

state. If the crystal or ceramic resonator requires more time to stabilize, extend the

“L” level period.

RESET

Reset input

Input

X_IN

Input and output pins of the internal clock generating circuit. Connect a ceramic or

quartz–crystal resonator between the X_INand X_OUTpins. When an external clock

source is used, connect it to X_INand leave X_OUTopen.

Clock input

Input

X_OUT

Clock output

Output

Reference volt-

age input

V_REF

Input

I/O

Reference voltage input pin for A-D converter

CMOS I/O ports or analog input ports

P0₀/AN₀—

P0₇/AN₇

I/O port P0

CMOS input port or external interrupt input port. The active edge (rising or falling) of

external interrupts can be selected. This pin will be used as V_PPpin during PROM

programming of One Time PROM Versions.

P1₁/INT₀

Input

CMOS I/O port or external interrupt input port. The active edge (rising or falling) of

external interrupts can be selected.

P1₂/INT₁

P1₃/TX₀

CMOS I/O port or input pin used in the bi-phase counter mode

CMOS I/O port or timer X input pin used for the event counter, pulse width measure-

ment and bi-phase counter mode

P1₄/CNTR₀

I/O port P1

I/O

CMOS I/O port or timer Y input pin used for the event counter, pulse width and pulse

period measurement mode

P1₅/CNTR₁

P1₆/PWM

P1₇

CMOS I/O port or PWM output pin used in the PWM mode of timers 2 and 3

CMOS I/O port

P2₀/S_IN

P2₁/S_OUT

P2₂/S_CLK

P2₃/S_RDY

CMOS I/O ports or clock synchronous serial I/O pins

CMOS I/O ports or asynchronous serial I/O pins

I/O

I/O port P2

P2₄/UR_XD

P2₅/UT_XD

P2₆/U_RTS

P2₇/U_CTS

P3₀

CMOS I/O port

P3₁/CTX

P3₂/CRX

P3₃—P3₄

CMOS I/O port or CAN transmit data pin

CMOS I/O port or CAN receive data pin

CMOS I/O port

I/O port P3

I/O port P4

I/O

I/O

P4₀/KW₀—

P4₇/KW₇

CMOS I/O ports. These ports can be used for key-on wake-up when configured as

inputs.

3

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PART NUMBERING

Product

M37630

M

4

T– XXX FP

Package type

FP: 44P6N-A package

FS: 80D0 package

ROM number

Omitted in One Time PROM version (blank) and EPROM version

T: Automotive use

ROM/PROM size

4: 16384 bytes

The first 128 bytes and the last 4 bytes of ROM are reserved areas.

They cannot be used.

Memory type

M: Mask ROM version

E: EPROM or One Time PROM version

Fig. 3

Part numbering

4

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

GROUP EXPANSION

Mitsubishi plans to expand the 7630 group as follows:

Memory Size

ROM/PROM size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Kbytes

RAM size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 bytes

Memory Type

Package

Support mask ROM, One Time PROM and EPROM versions.

44P6N-A . . . . . . . . . . . . . . . . .0.8mm-pitch plastic molded QFP

80D0 . . . . . . . . . . .0.8mm-pitch ceramic LCC (EPROM version)

ROM

External

60K

48K

32K

28K

24K

20K

Under development

M37630M4T

16K

12K

8K

M37630E4T

Mass product

384

512

640

768

896

1024

RAM size (bytes)

Fig. 4

Memory expansion plan

Currently supported products are listed below:

Table 2: List of supported products

As of March 1998

(P)ROM size (bytes)

Product

RAM size (bytes)

Package

Remarks

ROM size for User ( )

M37630M4T-XXXFP

Mask ROM version

M37630E4T-XXXFP

M37630E4FP

16384

512

44P6N-A

80D0

One Time PROM version

One Time PROM version (blank)

EPROM version

(16252)

M37630E4FS

5

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FUNCTIONAL DESCRIPTION

Central Processing Unit (CPU)

CPU Mode Register CPUM

The core of 7630 group microcomputers is the 7600 series CPU.

This core is based on the standard instruction set of 740 series;

however the performance is improved by allowing to execute the

same instructions as that of the 740 series in less cycles. Refer to

the 7600 Series Software Manual for details of the instruction set.

The CPU mode register contains the stack page selection bit and

internal system clock selection bit. The CPU mode register is allo-

cated to address 0000₁₆

.

7

0

CPU mode register (address 0000₁₆

CPUM

)

Processor mode bits (set these bits to “00”)

b1 b0

0

0

1

1

0: Single–chip mode

1: Not used

0: Not used

1: Not used

Stack page selection bit

0 : 0 page

1 : 1 page

Not used (“0” when read, do not write “1”)

Internal system clock selection bit

0: φ=f(X_IN) divided by 2 (high–speed mode)

1 : φ=f(X_IN) divided by 8 (middle–speed mode)

Not used (“0” when read, do not write “1”)

Fig. 5

Structure of CPU mode register

6

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MEMORY

Special Function Register (SFR) Area

Interrupt Vector Area

The special function register (SFR) area contains the registers

relating to functions such as I/O ports and timers.

The interrupt vector area is for storing jump destination addresses

used at reset or when an interrupt is generated.

RAM

Zero Page

RAM is used for data storage and for stack area of subroutine calls

and interrupts.

This area can be accessed most efficiently by means of the zero

page addressing mode.

ROM

Special Page

ROM is used for storing user’s program code as well as the inter-

rupt vector area.

This area can be accessed most efficiently by means of the special

page addressing mode.

RAM area

Address

XXXX₁₆

RAM size

(byte)

0000₁₆

011F₁₆

015F₁₆

01DF₁₆

025F₁₆

02DF₁₆

035F₁₆

03DF₁₆

045F₁₆

06DF₁₆

085F₁₆

SFR area

0040₁₆

192

256

CAN

Zero page

SFRs

0060₁₆

00FF₁₆

384

512

640

User RAM

768

896

XXXX₁₆

0860₁₆

1024

1536

2048

ROM area

Not used

Address

YYYY₁₆

Address

ZZZZ₁₆

ROM size

(byte)

YYYY₁₆

F000₁₆

E000₁₆

D000₁₆

C000₁₆

B000₁₆

A000₁₆

9000₁₆

8000₁₆

7000₁₆

6000₁₆

5000₁₆

4000₁₆

3000₁₆

2000₁₆

1000₁₆

F080₁₆

E080₁₆

D080₁₆

C080₁₆

B080₁₆

A080₁₆

9080₁₆

8080₁₆

7080₁₆

6080₁₆

5080₁₆

4080₁₆

3080₁₆

2080₁₆

1080₁₆

4096

8192

Reserved ROM area

ZZZZ₁₆

12288

16384

20480

24576

28672

32768

36864

40960

45056

49152

53248

57344

61440

ROM

FF00₁₆

FFCA₁₆

Special page

Interrupt vector area

Reserved ROM area

FFFB₁₆

FFFC₁₆

FFFF₁₆

Fig. 6

Memory map diagram

7

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

SPECIAL FUNCTION REGISTERS (SFR)

0000₁₆

0001₁₆

0002₁₆

0003₁₆

0004₁₆

0005₁₆

0006₁₆

0007₁₆

0008₁₆

0009₁₆

000A₁₆

000B₁₆

000C₁₆

000D₁₆

000E₁₆

000F₁₆

0010₁₆

0011₁₆

0012₁₆

0013₁₆

0014₁₆

0015₁₆

0016₁₆

0017₁₆

0018₁₆

0019₁₆

001A₁₆

001B₁₆

001C₁₆

001D₁₆

001E₁₆

001F₁₆

0020₁₆

0021₁₆

0022₁₆

0023₁₆

0024₁₆

0025₁₆

0026₁₆

0027₁₆

0028₁₆

0029₁₆

002A₁₆

002B₁₆

002C₁₆

002D₁₆

002E₁₆

002F₁₆

0030₁₆

0031₁₆

0032₁₆

0033₁₆

0034₁₆

0035₁₆

0036₁₆

0037₁₆

0038₁₆

0039₁₆

003A₁₆

003B₁₆

003C₁₆

003D₁₆

003E₁₆

003F₁₆

0040₁₆

0041₁₆

0042₁₆

0043₁₆

0044₁₆

0045₁₆

0046₁₆

0047₁₆

0048₁₆

0049₁₆

004A₁₆

004B₁₆

004C₁₆

004D₁₆

004E₁₆

004F₁₆

0050₁₆

0051₁₆

0052₁₆

0053₁₆

0054₁₆

0055₁₆

0056₁₆

0057₁₆

0058₁₆

0059₁₆

005A₁₆

005B₁₆

005C₁₆

005D₁₆

005E₁₆

005F₁₆

CPU mode register

CPUM

CAN transmit control register

CAN bus timing control register 1

CAN bus timing control register 2

CAN acceptance code register 0

CAN acceptance code register 1

CAN acceptance code register 2

CAN acceptance code register 3

CAN acceptance code register 4

CAN acceptance mask register 0

CAN acceptance mask register 1

CAN acceptance mask register 2

CAN acceptance mask register 3

CAN acceptance mask register 4

CAN receive control register

CAN transmit abort register

Reserved

CTRM

CBTCON1

CBTCON2

CAC0

Not used

Interrupt request register A

Interrupt request register B

Interrupt request register C

Interrupt control register A

Interrupt control register B

Interrupt control register C

Port P0 register

IREQA

IREQB

IREQC

ICONA

ICONB

ICONC

P0

CAC1

CAC2

CAC3

CAC4

CAM0

Port P0 direction register

Port P1 register

P0D

CAM1

P1

CAM2

Port P1 direction register

Port P2 register

P1D

CAM3

P2

CAM4

Port P2 direction register

Port P3 register

P2D

CREC

P3

CABORT

Port P3 direction register

Port P4 register

P3D

P4

CAN transmit buffer register 0

CAN transmit buffer register 1

CAN transmit buffer register 2

CAN transmit buffer register 3

CAN transmit buffer register 4

CAN transmit buffer register 5

CAN transmit buffer register 6

CAN transmit buffer register 7

CAN transmit buffer register 8

CAN transmit buffer register 9

CAN transmit buffer register A

CAN transmit buffer register B

CAN transmit buffer register C

CAN transmit buffer register D

Reserved

CTB0

CTB1

CTB2

CTB3

CTB4

CTB5

CTB6

CTB7

CTB8

CTB9

CTBA

CTBB

CTBC

CTBD

Port P4 direction register

Serial I/O shift register

Serial I/O control register

A-D conversion register

A-D control register

P4D

SIO

SIOCON

AD

ADCON

T1

Timer 1

Timer 2

T2

Timer 3

T3

Timer 123 mode register

Timer XL

T123M

TXL

Timer XH

TXH

Timer YL

TYL

Timer YH

TYH

Timer X mode register

Timer Y mode register

UART mode register

UART baud rate generator

UART control register

UART status register

UART transmit buffer register 1

UART transmit buffer register 2

UART receive buffer register 1

UART receive buffer register 2

Port P0 pull-up control register

Port P1 pull-up control register

Port P2 pull-up control register

Port P3 pull-up control register

Port P4 pull-up/down control register

Interrupt polarity selection register

Watchdog timer register

Polarity control register

TXM

TYM

Reserved

UMOD

UBRG

UCON

USTS

UTBR1

UTBR2

URBR1

URBR2

PUP0

PUP1

PUP2

PUP3

PUP4

IPOL

WDT

PCON

CAN receive buffer register 0

CAN receive buffer register 1

CAN receive buffer register 2

CAN receive buffer register 3

CAN receive buffer register 4

CAN receive buffer register 5

CAN receive buffer register 6

CAN receive buffer register 7

CAN receive buffer register 8

CAN receive buffer register 9

CAN receive buffer register A

CAN receive buffer register B

CAN receive buffer register C

CAN receive buffer register D

Reserved

CRB0

CRB1

CRB2

CRB3

CRB4

CRB5

CRB6

CRB7

CRB8

CRB9

CRBA

CRBB

CRBC

CRBD

Reserved

Fig. 7

Memory map of special register (SFR)

8

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

I/O PORTS

The 7630 group has 35 programmable I/O pins and one input pin

arranged in five I/O ports (ports P0 to P4). The I/O ports are con-

trolled by the corresponding port registers and port direction regis-

ters; each I/O pin can be controlled separately.

as an input port becomes floating and its level can be read. Data

written to this port will affect the port latch only; the port remains

floating.

Refer to Structure of port- and port direction registers, Structure of

port I/Os (1) and Structure of port I/Os (2).

When data is read from a port configured as an output port, the port

latch’s contents are read instead of the port level. A port configured

7

0

Port Pi register (i = 0 to 4) (address 0008₁₆+ 2 · i)

Pi

Port Pi_jcontrol bit (j = 0 to 7)

0 : “L” level

1 : “H” level

Note : The control bits corresponding to P1₀, P3₅, P3₆and P3₇are not used

(“0” when read, do not write “1”).

7

0

Port Pi direction register (i = 0 to 4) (address 0009₁₆+ 2 · i)

PiD

Port Pi_jdirection control bit (j = 0 to 7)

0 : Port configured as input

1 : Port configured as output

Note : The direction control bits corresponding to P1₀, P1₁, P3₅, P3₆and

P3₇are not used (“0” when read, do not write “1”). Port direction re-

gisters are undefined when read (write only).

Fig. 8

Structure of port- and port direction registers

9

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(1) Ports P0₀/AN₀to P0₇/AN₇

(4) Port P1₃/TX₀

Pull-up control bit

Pull-up control bit

Analog input selection

Direction

direction

register

register

Port latch

Port latch

Data bus

Data bus

ADC input

Timer bi-phase mode input

Analog input selection

(5) Ports P1₄/CNTR₀, P1₅/CNTR₁

Pull-up control bit

(2) Port P1₁/INT₀

Direction

register

Interrupt input

Data bus

Port latch

Data bus

Timer bi-phase mode input

(3) Port P1₂/INT₁

(6) Port P1₆/PWM

Pull-up control bit

Pull-up control bit

PWM output enable

Direction

register

Direction

register

Port latch

Data bus

Port latch

Data bus

Interrupt input

PWM output

Fig. 9

Structure of port I/Os (1)

10

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(7) Ports P1₇, P3₀, P3₃, P3₄

(12) Ports P2₄/UR_XD, P2₇/U_CTS

Transmission or reception* in

progress

Pull-up control bit

Pull-up control bit

Transmit or receive* enable bit

Direction

register

Direction

register

Port latch

Data bus

Port latch

Data bus

U_RXDor U_CTSinput

(8) Port P2₀/S_IN

(13) Ports P2₅/UT_XD, P2₆/U_RTS

Transmission or reception** in

Pull-up control bit

Pull-up control bit

progress

SIO Port Select

Transmit or receive** enable bit

Direction

register

Direction

register

Port latch

Data bus

Port latch

Data bus

U_TXDor U_RTSoutput

SIO1 input

(*) for U_CTS

(**) for U_RTS

(14) Port P3₁/CTX

(9) Port P2₁/S_OUT

Pull-up control bit

CAN port selection bit

Pull-up control bit

SIO port selection bit

Transmit complete signal

Direction

Direction

register

register

Port latch

Data bus

Port latch

Data bus

CTX output

SIO output

(15) Port P3₂/CRX

CAN dominant level control bit

Pull-up/down control bit

(10) Port P2₂/S_CLK

Direction

register

Pull-up control bit

Clock selection bit

Port selection bit

direction

Port latch

Data bus

register

Port latch

Data bus

CAN interrupt

External clock input

SIO clock output

CRX input

(16) Ports P4₀/KW₀to P4₇/KW₇

Key-on wake-up control bit

Pull-up/down control bit

(11) Port P2₃/S_RDY

Pull-up control bit

SRDY output selection bit

Direction

register

Direction

register

Port latch

Data bus

Port latch

Data bus

Key-on wake-up interrupt

SRDY output

Fig. 10 Structure of port I/Os (2)

11

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

port pull-up control registers (see Structure of port pull-up/down

control registers). The pull-up/down function of ports P3₂and P4

can be controlled by the corresponding port pull-up/pull-down regis-

ters together with the polarity control register (see Structure of

polarity control register).

Port Pull-up/pull-down Function

Each pin of ports P0 to P4 except P1₁is equipped with a program-

mable pull-up transistor. P3₂/CRX and P4₀/KW₀to P4₇/KW₇are

equipped with programmable pull-down transistors as well. The

pull-up function of P0 to P3 can be controlled by the corresponding

7

0

Port Pi pull-up control register (address 0028₁₆+ i) (i = 0, 2)

PUP0, PUP2

Pi_jpull-up transistor control bit (j = 0 to 7)

0 : Pull-up transistor disabled

1 : Pull-up transistor enabled

7

0

Port P1 pull-up control register (address 0029₁₆

PUP1

)

Not used (“0” when read, do not write “1”)

P1_jpull-up transistor control bit (j = 2 to 7)

7

0

Port P3 pull-up control register (address 002B₁₆

PUP3

)

P3_jpull-up transistor control bit (j = 0, 1)

P3₂pull-up/down transistor control bit

P3_jpull-up transistor control bit (j = 3, 4)

Not used (“0” when read, do not write “1”)

7

0

Port P4 pull-up/down control register (address 002C₁₆

PUP4

)

P4_jpull-up/down transistor control bit (j = 0 to 7)

0 : Pull-up/down transistor disabled

1 : Pull-up/down transistor enabled

Fig. 11 Structure of port pull-up/down control registers

7

0

Polarity control register (address 002F₁₆

PCON

)

Key-on wake-up polarity control bit

0 : Low level active

1 : High level active

CAN module dominant level control bit

0 : Low level dominant

1 : High level dominant

Not used (undefined when read)

Fig. 12 Structure of polarity control register

12

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

•

•

Avoid to subject ports to overvoltage causing V_CCto rise above

5.5 V.

Port Overvoltage Application

When configured as input ports, P1 to P4 may be subjected to over-

voltage (V_I> V_CC) if the input current to the applicable port is limited

to the specified values (see “Table 8:”). Use a serial resistor of

appropriate size to limit the input current. To estimate the resistor

value, assume the port voltage to be V_CCat overvoltage condition.

The overvoltage condition causing input current flowing through

the internal port protection circuits has a negative effect on the

ports noise immunity. Therefore, careful and intense testing of

the target system’s noise immunity is required. Refer to the

“countermeasures against noise” of the corresponding users

manual.

Notes:

•

Subjecting ports to overvoltage may effect the supply voltage.

Assure to keep V_CCand V_SSwithin the target limits.

•

Port P0 must not be subjected to overvoltage conditions.

13

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

INTERRUPTS

There are 24 interrupts: 6 external, 17 internal, and 1 software.

2. The contents of the program counter and processor status

register are automatically pushed onto the stack.

Interrupt Control

3. Concurrently with the push operation, the interrupt jump

destination address is read from the vector table into the

program counter.

Each interrupt except the BRK instruction interrupt has both an

interrupt request bit and an interrupt enable bit, and is controlled by

the interrupt disable flag. An interrupt occurs when the correspond-

ing interrupt request and enable bits are “1” and the interrupt dis-

able flag is “0”. Interrupt enable bits can be cleared or set by

software. Interrupt request bits can be cleared by software but can-

not be set by software. The BRK instruction interrupt and reset can-

not be disabled with any flag or bit. The I flag disables all interrupts

except the BRK instruction interrupt and reset. If several interrupt

requests occur at the same time, the interrupt with the highest prior-

ity is accepted first.

4. The interrupt disable flag is set and the corresponding interrupt

request bit is cleared.

Notes on use

When the active edge of an external interrupt (INT₀, INT₁, CNTR₀,

CNTR₁, CWKU or KOI) is changed, the corresponding interrupt

request bit may also be set. Therefore, take the following sequence.

(1) Disable the external interrupt which is selected.

(2) Change the active edge in interrupt edge selection register.

Interrupt Operation

(in the case of CNTR₀: Timer X mode register; in the case of

CNTR₁: Timer Y mode register)

Upon acceptance of an interrupt, the following operations are auto-

matically performed.

(3) Clear the interrupt request bit to “0”.

1. The processing being executed is stopped.

(4) Enable the external interrupt which is selected.

14

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

.

Table 3: Interrupt vector addresses and priority

Vector Address (Note 1)

Interrupt Request Generating

Conditions

Interrupt source

Priority

Remarks

High

Low

Reset (Note 2)

Watchdog timer

FFFB₁₆

FFF9₁₆

FFFA₁₆

FFF8₁₆

1

2

At Reset

Non-maskable

At Watchdog timer underflow

Non-maskable

At detection of either rising or falling

edge of INT₀interrupt

External Interrupt

(active edge selectable)

FFF7₁₆

FFF5₁₆

FFF3₁₆

FFF1₁₆

FFEF₁₆

FFED₁₆

FFEB₁₆

FFE9₁₆

FFF6₁₆

FFF4₁₆

FFF2₁₆

FFF0₁₆

FFEE₁₆

FFEC₁₆

FFEA₁₆

FFE8₁₆

INT0

INT1

3

4

At detection of either rising or falling

edge of INT₁interrupt

External Interrupt

(active edge selectable)

At CAN module successful

transmission of message

Valid when CAN module is

activated and request transmit

CAN successful

transmit

5

CAN successful

receive

At CAN module successful reception

of message

Valid when CAN module is

activated

6

If CAN module receives message

when receive buffers are full.

Valid when CAN module is

activated

CAN overrun

7

CAN error

passive

When CAN module enters into error

passive state

Valid when CAN module is

active

8

When CAN module enters into bus

off state

Valid when CAN module is

active

CAN error bus off

CAN wake up

9

When CAN module wakes up via

CAN bus

10

FFE7₁₆

FFE5₁₆

FFE3₁₆

FFE1₁₆

FFDF₁₆

FFE6₁₆

FFE4₁₆

FFE2₁₆

FFE0₁₆

FFDE₁₆

Timer X

Timer Y

Timer 1

Timer 2

Timer 3

11

12

13

14

15

At Timer X underflow or overflow

At Timer Y underflow

At Timer 1 underflow

At Timer 2 underflow

At Timer 3 underflow

At detection of either rising or falling

edge in CNTR₀input

External Interrupt

(active edge selectable)

FFDD₁₆

FFDB₁₆

FFDC₁₆

FFDA₁₆

CNTR0

CNTR1

16

17

At detection of either rising or falling

edge in CNTR₁input

External Interrupt

(active edge selectable)

FFD9₁₆

FFD7₁₆

FFD8₁₆

FFD6₁₆

UART receive

UART transmit

18

19

At completion of UART receive

At completion of UART transmit

Valid when UART is selected

Valid when UART is selected

UART transmit

buffer empty

FFD5₁₆

FFD3₁₆

FFD4₁₆

FFD2₁₆

20

21

At UART transmit buffer empty

Valid when UART is selected

Valid when UART is selected

UART receive

error

When UART reception error occurs.

At completion of serial I/O data

transmit and receive

Valid when serial I/O is

selected

FFD1₁₆

FFD0₁₆

Serial I/O

22

FFCF₁₆

FFCD₁₆

FFCB₁₆

FFCE₁₆

FFCC₁₆

FFCA₁₆

A-D conversion

Key-on wake-up

BRK instruction

23

24

25

At completion of A-D conversion

At detection of either rising or falling

edge of P4 input

External Interrupt

(active edge selectable)

At BRK instruction execution

Non-maskable

Notes 1: Vector addresses contain interrupt jump destination address

2: Reset function in the same way as an interrupt with the highest priority

15

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Interrupt request bit

Interrupt enable bit

Interrupt disable flag I

BRK instruction

Reset

Interrupt request

Fig. 13 Interrupt control

For the external interrupts INT0 and INT1, the active edge causing

the interrupt request can be selected by the INT0 and INT1 interrupt

edge selection bits of the interrupt polarity selection register (IPOL);

please refer to Fig. 14 below.

7

0

Interrupt polarity selection register (Address 002D₁₆

IPOL

)

Not used (returns to “0” when read, do not write “1” in this bit)

INT₀interrupt edge selection bit

INT₁interrupt edge selection bit

Not used (returns to “0” when read, do not write “1” in these bits)

0 : Falling edge active

1 : Rising edge active

Fig. 14 Structure of interrupt polarity selection register

16

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Interrupt request register A

(address 0002₁₆

IREQA

Interrupt control register A

0

7

7

0

)

(address 000516)

ICONA

Not used (returns to ”0” when read)

External interrupt INT₀enable bit

External interrupt INT₁enable bit

CAN successful transmission

interrupt enable bit

Not used

(returns to ”0” when read)

External interrupt INT₀request bit

External interrupt INT₁request bit

CAN successful transmission

interrupt request bit

CAN successful receive

interrupt enable bit

CAN successful receive

interrupt request bit

CAN overrun interrupt enable bit

CAN error passive

CAN overrun interrupt request bit

CAN error passive

interrupt enable bit

CAN bus off interrupt enable bit

interrupt request bit

CAN bus off interrupt request bit

Interrupt control register B

0

7

7

0

Interrupt request register B

(address 000316)

IREQB

(address 000616)

ICONB

CAN wake–up interrupt enable bit

Timer X interrupt enable bit

Timer Y interrupt enable bit

Timer 1 interrupt enable bit

Timer 2 interrupt enable bit

Timer 3 interrupt enable bit

CNTR₀interrupt enable bit

CNTR₁interrupt enable bit

CAN wake up

interrupt request bit

Timer X interrupt request bit

Timer Y interrupt request bit

Timer 1 interrupt request bit

Timer 2 interrupt request bit

Timer 3 interrupt request bit

CNTR₀interrupt request bit

CNTR₁interrupt request bit

Interrupt request register C

(address 000416)

IREQC

7

0

7

0

Interrupt control register C

(address 000716)

ICONC

UART receive complete

(receive buffer full)

UART receive complete

(receive buffer full)

interrupt request bit

interrupt enable bit

UART transmit complete

(transmit register empty)

interrupt request bit

UART transmit complete

(transmit register empty)

interrupt enable bit

UART transmit buffer empty

interrupt request bit

UART transmit buffer empty

interrupt enable bit

UART receive error interrupt

request bit

UART receive error interrupt

enable bit

Serial I/O interrupt request bit

AD conversion complete

interrupt request bit

Serial I/O interrupt enable bit

AD conversion complete

interrupt enable bit

Key-on wake-up interrupt request bit

Not used (returns to ”0” when read)

Key-on wake-up interrupt enable bit

Not used (returns to ”0” when read)

0 : No interrupt request

1 : Interrupt requested

0: Interrupt disabled

1: Interrupt enabled

Fig. 15 Structure of interrupt request and control registers A, B and C

17

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

KEY-ON WAKE-UP

“Key-on wake-up” is one way of returning from a power-down state

caused by the STP or WIT instruction. Any terminal of port P4 can

be used to generate the key-on wake-up interrupt request. The

active polarity can be selected by the key-on wake-up polarity con-

trol bit of PCON (see Fig. 12). If any pin of port P4 has the selected

active level applied, the key-on wake-up interrupt request will be set

to “1”. Please refer to Fig. 16.

key-on wake-up control bit

P4D_j

PUP4_j

port P4_j/KW_j

key-on wake-up interrupt

port P4_jI/O circuit

j = 0 to 7

Fig. 16 Block diagram of key-on wake-up circuit

18

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

TIMERS

The 7630 group has five timers: two 16-bit timers and three 8-bit

timers . All these timers will be described in detail below.

16-bit Timers

Timers X and Y are 16-bit timers with multiple operating modes.

Please refer to Fig. 17.

TYM_1,0

φ

“00”

1/4

TX_Llatch (8)

TX_Hlatch (8)

TXM_5,4

TXM₇

“01”

“10”

1/16

1/64

“00”, “11”

“01”

TX_Lcounter (8)

TX_Hcounter (8)

TX interrupt request

“10”

“11”

1/128

count

direction

control

P1₃/TX₀

down

edge detector

“00”, “10”,

“11”

“01”

sign generator

edge detector

P1₄/CNTR₀

TXM_{5, 4}

“0”

CNTR0 interrupt request

“1”

TXM₆

TXM_{5, 4}=“11”

TYM_{3, 2}

TY_Llatch (8)

TY_Lcounter (8)

TYM_{5, 4}=“11”

TY_Hlatch (8)

“00”

TYM₇

1/2

1/8

“01”

“10”

“11”

TYM_{5, 4}

“0x”, “11”

TY interrupt request

TY_Hcounter (8)

1/32

1/64

“10”

rising edge detector

falling edge detector

TYM_{5, 4}=“01”

P1₅/CNTR₁

“11”

“0”

CNTR1 interrupt request

“1”

“0x”, “10”

TYM₆

TYM_{5, 4}

Fig. 17 Block diagram of timers X and Y (φ is internal system clock)

same address as TX_L. Next, write the high-order byte. When this is

finished, the data is placed in the timer X high-order reload latch

and the low-order byte is transferred from its temporary register to

the timer X low-order reload latch. Depending on the timer X write

control bit, the latch contents are reloaded to the timer immediately

(write control bit = “0”) or on the next timer underflow (write control

bit = “1”).

Timer X

Timer X is a 16-bit timer with a 16-bit reload latch supporting the fol-

lowing operating modes:

(1) Timer mode

(2) Bi-phase counter mode

(3) Event counter mode

(4) Pulse width measurement mode

Read method

These modes can be selected by the timer X mode register (TXM).

In the timer- and pulse width measurement mode, the timer’s count

source can be selected by the timer X count source selection bits of

the timer Y mode register (TYM). Please refer to the Figures below

for the TXM and TYM bit assignment.

When reading the timer X, read the high-order byte first. This

causes the timer X high- and low-order bytes to be transferred to

temporary registers being assigned to the same addresses as TX_H

and TX_L. Next, read the low-order byte which is read from the tem-

porary register. This method assures the correct timer value can be

read during the timer count operation.

On read or write access to timer X, note that the high-order and low-

order bytes must be accessed in the specific order.

Timer X count stop control

Write method

Regardless of the actual operating mode, timer X can be stopped

by setting the timer X count stop bit (bit 7 of the timer X mode regis-

ter) to “1”.

When writing to the timer X, write the low-order byte first. The data

written is stored in a temporary register which is assigned to the

19

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7

0

Timer X mode register (address 001E₁₆

)

TXM

Timer X data write control bit

0 : Data is written to latch and timer

1 : Data is written to latch only

Not used (“0” when read, do not write “1”)

Timer X mode bits

b5 b4

0

0

1

1

0: Timer mode

1: Bi-phase counter mode

0: Event counter mode

1: Pulse width measurement mode

CNTR₀polarity selection bit

0 : For event counter mode, rising edge active

For interrupt request, falling edge active

For pulse width measurement mode, measure “H” period

1 : For event counter mode, falling edge active

For interrupt request, rising edge active

For pulse width measurement mode, measure “L” period

Timer X stop control bit

0 : Timer counting

1 : Timer stopped

Fig. 18 Structure of Timer X mode register

address as TY_L. Next, write the high-order byte. When this is fin-

Timer Y

ished, the data is placed in the timer Y high-order reload latch and

the low-order byte is transferred from its temporary register to the

timer Y low-order reload latch.

Timer Y is a 16 bit timer with a 16-bit reload latch supporting the fol-

lowing operating modes:

(1) Timer mode

Read method

(3) Event counter mode

(5) Pulse period measurement mode

When reading the timer Y, read the high-order byte first. This

causes the timer Y high- and low-order bytes to be transferred to

temporary registers being assigned to the same addresses as TY_H

and TY_L. Next, read the low-order byte which is read from the tem-

porary register. This method assures the correct timer value can be

read during timer count operation.

(6) H/L pulse width measurement mode

These modes can be selected by the timer Y mode register (TYM).

In the timer, pulse period- and pulse width measurement modes’

the timer’s count source can be selected by the timer Y count

source selection bits. Please refer to Fig. 19.

On read or write access to timer Y, note that the high-order and low-

order bytes must be accessed in a specific order.

Timer Y count stop control

Write method

Regardless of the actual operating mode, timer Y can be stopped

by setting the timer Y count stop bit (bit 7 of the timer Y mode regis-

ter) to “1”.

When writing to timer Y, write the low-order byte first. The data writ-

ten is stored in a temporary register which is assigned to the same

20

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7

0

Timer Y mode register (address 001F₁₆

)

TYM

Timer X count source selection bits

b1 b0

0

0

1

1

0: φ divided by 4

1: φ divided by 16

0: φ divided by 64

1: φ divided by 128

Timer Y count source selection bits

b3 b2

0

0

1

1

0: φ divided by 2

1: φ divided by 8

0: φ divided by 32

1: φ divided by 64

Timer Y operation mode bits

b5 b4

0

0

1

1

0: Timer mode

1: Pulse period measurement mode

0: Event counter mode

1: H/L pulse width measurement mode

CNTR₁polarity selection bit

0 : For event counter mode, rising edge active

For interrupt request, falling edge active

For pulse period measurement mode, refer to falling edges

1 : For event counter mode, falling edge active

For interrupt request, rising edge active

For pulse period measurement mode, refer to rising edges

Timer Y stop control bit

0 : Timer counting

1 : Timer stopped

Fig. 19 Structure of timer Y mode register (φ is internal system clock)

The count direction is determined by the edge polarity and level

of count source inputs and may change during the count opera-

tion. Refer to the table below.

Operating Modes

(1) Timer mode

This mode is available with timer X and timer Y.

Table 4: Timer X count direction in Bi-phase counter mode

•

Count source

The count source for timer X and Y is the output of the corre-

sponding clock divider. The division ratio can be selected by the

timer Y mode register.

P1₃/TX₀

P1₄/CNTR₀

Count direction

L

H

L

Up

Down

Down

Up

↑ Edge

•

Operation

Both timers X and Y are down counters. On a timer underflow,

the corresponding timer interrupt request bit will be set to “1”, the

contents of the corresponding timer latches will be reloaded to

the counters and counting continues.

↓ Edge

H

L

H

L

Down

Up

↑ Edge

↓ Edge

(2) Bi-phase counter mode (quadruplicate)

This mode is available with timer X only.

Up

•

Count source

H

Down

The count sources are P1₄/CNTR₀and the P1₃/TX₀pins.

Operation

•

Timer X will count both rising and falling edges on both input pins

(see above). Refer to Timer X bi-phase counter mode operation

for the timing chart of the bi-phase counter mode.

On a timer over- or underflow, the corresponding interrupt

request bit will be set to “1” and counting continues.

21

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

P1₃/TX₀input signal

P1₄/CNTR₀input signal

TX counter

count direction

down

up

Fig. 20 Timer X bi-phase counter mode operation

•

Operation

(3) Event counter mode

The active edge of input signal to be measured can be selected

by CNTR₁polarity selection bit (Fig. 18). When this bit is set to

“0”, the time between two consecutive falling edges of the signal

input to P1₅/CNTR₁pin will be measured, when the polarity bit is

set to “1”, the time between two consecutive rising edges will be

measured.

The timer counts down. On detection of an active edge of input

signal, the contents of the TY counters will be transferred to tem-

porary registers assigned to the same addresses as TY. At the

same time, the contents of TY latches will be reloaded to the

counters and counting continues. The active edge of input signal

also causes the CNTR₁interrupt request bit to be set to “1”. The

measurement result may be obtained by reading timer Y during

interrupt service.

This mode is available with timer X and timer Y.

•

Count source

The count source for timer X is the input signal to the P1₄/CNTR₀

pin and for timer Y the input signal to P1₅/CNTR₁pin.

Operation

•

The timer counts down. On a timer underflow, the corresponding

timer interrupt request bit will be set to “1”, the contents of the

corresponding timer latches will be reloaded to the counters and

counting continues. The active edge used for counting can be

selected by the polarity selection bit of the corresponding pin

P1₄/CNTR₀or P1₅/CNTR₁. These bits are part of TXM (Structure

of Timer X mode register) and TYM (Structure of timer Y mode

register (f is internal system clock)) registers.

(4) Pulse width measurement mode

(6) H/L pulse width measurement mode

This mode is available with timer X only.

•

Count source

This mode is available with timer Y only.

The count source is the output of timer X clock divider. The divi-

sion ratio can be selected by the timer Y mode register.

Operation

•

Count source

The count source is the output of the timer Y’s clock divider.

•

The timer counts down while the input signal level on

P1₄/CNTR₀matches the active polarity selected by the CNTR₀

polarity selection bit of TXM (Structure of Timer X mode regis-

ter). On a timer underflow, the timer X interrupt request bit will be

set to “1”, the contents of the timer latches are reloaded to the

counters and counting continues. When the input level changes

from active polarity (as selected), the CNTR₀interrupt request bit

will be set to “1.” The measurement result may be obtained by

reading timer X during interrupt service.

•

Operation

This mode measures both the “H” and “L” periods of a signal

input to P1₅/CNTR₁pin continuously. On detection of any edge

(rising or falling) of input signal to P1₅/CNTR₁pin, the contents of

timer Y counters are stored to temporary registers which are

assigned to the same addresses as timer Y. At the same time,

the contents of timer Y latches are reloaded to the counters and

counting continues. The detection of an edge causes the

CNTR1 interrupt request bit to be set to “1” as well. The result of

measurement may be obtained by reading timer Y during inter-

rupt service. This read access will address the temporary regis-

ters. On a timer underflow, the timer Y interrupt request bit will

be set to “1”, the contents of timer Y latches will be transferred to

the counters and counting continues.

(5) Pulse period measurement mode

This mode is available with timer Y only.

•

Count source

The count source is the output of timer Y clock divider.

22

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

TIMER 1, TIMER 2, TIMER 3

Timers 1 to 3 are 8-bit timers with 8-bit reload latches and one com-

mon pre-divider. Timer 1 can operate in the timer mode only,

whereas timers 2 and 3 can be used to generate a PWM output sig-

nal timing as well. Timers 1 to 3 are down count timers. See Fig. 21.

T123M₆₇

φ

T1 latch (8)

“00”

1

“01”

1/8

T1 counter (8)

T1 interrupt

T2 interrupt

T3 interrupt

“10”

1/32

“11”

1/128

T2 latch (8)

“1” “0”

T123M₃

T2 counter (8)

“0”

“1”

T123M₁

S

R

Q

T3 latch (8)

“1”

“0”

T3 counter (8)

T123M₄

“0”

“1”

T123M₁

S

R

Q

P1D₆

T123M₁

T123M₀

S

P1₆latch

P1₆/PWM

T

Q

Fig. 21 Block diagram of timers 1 to 3 (φ is internal system clock)

be selected by the timer count source selection bits of timer 123

mode register (T123M).

Timer 1

The count source of timer 1 is the output of timer 123 pre-divider.

The division ratio of the pre-divider can be selected by the pre-

divider division ratio bits of timer 123 mode register (T123M). Refer

to Timer 123 mode register configuration (f is internal system clock).

On a timer 1 underflow, the timer 1 interrupt request bit will be set to

“1”.

Writing to timer 2 register affects the reload latch only or both of the

reload latch and counter depending on the timer 2 write control bit

of T123M. When the timer write control bit is set to “0”, both latch

and counter will be initialized simultaneously; when set to “1” only

the reload latch will be initialized, on an underflow, the counter will

be set to the modified reload value. Writing to timer 3 initializes

latch and counter both.

Writing to timer 1 initializes the latch and counter.

Timers 2 and 3

The count source of timers 2 and 3 can be either the output of the

timer 123 pre-divider or the timer 1 underflow. The count source can

Timer 2 or 3 underflow causes the timer 2 or 3 interrupt request bit

to be set to “1”.

23

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7

0

Timer 123 mode register (address 0019₁₆

)

T123M

PWM polarity selection bit

0 : Start on “H” level output

1 : Start on “L” level output

PWM output enable bit

0 : PWM output disabled

1 : PWM output enabled

Timer 2 write control bit

0 : Latch and counter

1 : Latch only

Timer 2 count source selection bit

0 : Timer 1 underflow

1 : Pre-divider output

Timer 3 count source selection bit

0 : Timer 1 underflow

1 : Pre-divider output

Not used (“0” when read, do not write “1”)

Pre-divider division ratio bits

b7 b6

0

0

1

1

0: φ divided by 1

1: φ divided by 8

0: φ divided by 32

1: φ divided by 128

Fig. 22 Timer 123 mode register configuration (φ is internal system clock)

Operating Modes

(2) PWM Mode

This mode is available with timer 2 and 3.

(1) Timer Mode

•

Count source

The count source can be separately selected to be either the

pre-divider output or timer 1 underflow.

This mode is available with timers 1 to 3.

•

•

Count source

•

Operation

For timer 1, the count source is the output of the corresponding

pre-divider. For timers 2 and 3, the count source can be sepa-

rately selected to be either the pre-divider output or timer 1

underflow.

When the PWM-mode is enabled, timer 2 starts counting. As

soon as timer 2 underflows, timer 2 stops and timer 3 starts

counting. If bit 0 is set, timer 2 determines the low duration and

the initial output level is low. Timer 3 determines the high dura-

tion. If bit 0 is zero timer 2 determines the high duration and the

initial output level is high. In this case timer 3 determines the low

duration.

Operation

The timer counts down. On a timer underflow, the corresponding

timer interrupt request bit will be set to “1”, the contents of the

corresponding timer latch will be reloaded to the counter and

counting continues.

Note: Be sure to configure the P1₆/PWM pin as an output port

before using PWM mode.

24

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

SERIAL I/Os

The serial I/O section of 7630 group consists of one clock synchro-

nous and one asynchronous (UART) interface.

speeds. Refer to Block diagram of clock synchronous I/O (f is inter-

nal system clock). The operation of the clock synchronous serial I/O

can be configured by the serial I/O control register SIOCON; refer to

Fig. 25.

Clock Synchronous Serial I/O (SI/O)

The clock synchronous interface allows full duplex communication

based on 8 bit word length. The transfer clock can be selected from

an internal or external clock. When an internal clock is selected, a

programmable clock divider allows eight different transmission

SIOCON_{2, 1, 0}

φ

Clock divider

P2₃/S_RDY

SIOCON₄

“1”

SIOCON₆

Sync. circuit

“1”

“0”

“0”

P2₃latch

P2₂/S_CLK

SIOCON₃

SIO counter (3)

SIO interrupt

“1”

“0”

P2₂latch

P2₁/S_OUT

SIOCON₃

SIO shift register (8)

“1”

“0”

P2₁latch

P2₀/S_IN

SIOCON₃

“1”

“0”

P2₀latch

Fig. 23 Block diagram of clock synchronous I/O (φ is internal system clock)

0012₁₆). After an 8–bit transmission has been completed, the S_OUT

pin will change to high impedance and the SIO interrupt request bit

will be set to “1”.

(1) Clock synchronous serial I/O operation

Either an internal or external transfer clock can be selected by bit 6

of SIOCON. The internal clock divider can be programmed by bits 0

to 2 of SIOCON. Bit 3 of SIOCON determines whether the double

function pins P2₀to P2₂will act as I/O ports or serve as SIO pins.

Bit 4 of SIOCON allows the same selection for pin P2₃.

When an external transfer clock is selected, the SIO interrupt

request bit will be set to “1” after 8 cycles but the contents of the

SI/O shift register continue to be shifted while the transfer clock is

being input. Therefore, the clock needs to be controlled externally;

the S_OUTpin will not change to high impedance automatically.

When an internal transfer clock is selected, transmission can be

triggered by writing data to the SI/O shift register (SIO, address

25

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

synchronous clock

transfer clock

write signal to SIO

receive enable signal S_RDY

Serial Output SOUT

D₀

D₀

D₁

D₁

D₂

D₂

D₃

D₃

D₄

D₄

D₅

D₅

D₆

D₆

D₇

D₇

Serial input SIN

SIO interrupt request bit = “1”

Note: When an internal clock is selected, S_OUTpin will change to high impedance after 8 bits of data have been transmitted.

Fig. 24 Timing of clock synchronous SI/O function (LSB first selected)

7

0

SIO control register (address 0013₁₆

SIOCON

)

Clock divider selection bits

b2 b1 b0

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0: φ divided by 4

1: φ divided by 8

0: φ divided by 16

1: φ divided by 32

0: φ divided by 64

1: φ divided by 128

0: φ divided by 256

1: φ divided by 512

P2₀/S_IN, P2₁/S_OUTand P2₂/S_CLKfunction selection bit

0 : I/O port function

1 : SI/O function

P2₃/S_RDYfunction selection bit

0 : I/O port function

1 : SI/O function

Transmission order selection bit

0 : LSB first

1 : MSB first

Synchronization clock selection bit

0 : use external clock

1 : use internal clock

Not used (“0” when read)

Fig. 25 Structure of serial I/O control register (φ is internal system clock)

written to or read from directly, transmit data is written to the trans-

Clock Asynchronous Serial I/O (UART)

mit buffer and receive data is read from the receive buffer. A trans-

mit or receive operation will be triggered by the transmit enable bit

and receive enable bit of the UART control register UCON (see

Structure of UART control register). The double function terminals

P2₅/UT_XD, P2₆/URTS and P2₄/UR_XD, P2₇/UCTS will be switched to

serve as UART pins automatically.

The UART is a full duplex asynchronous transmit/receive unit. The

built-in clock divider and baud rate generator enable a broad range

of transmission speeds. Please refer to Block diagram of UART.

(1) Description

The transmit and receive shift registers have a buffer (consisting of

high and low order byte) each. Since the shift registers cannot be

26

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(2) Baud rate selection

UART status register (USTS, Structure of UART

status register)

The baud rate of transmission and reception is determined by the

setting of the prescaler and the contents of the UART baud rate

generator register. It is calculated by: where p is the division ratio of

The read-only UART status register consists of 7 bits (bit 0 to bit 6)

which indicate the operating status of the UART function and vari-

ous errors.

φ

----------------------------------

b =

(3) Handshaking signals

16 p (n + 1)

When used as transmitter the UART will recognize the clear-to-

send signal via P2₇/UCTS terminal for handshaking. When used as

receiver it will issue a request-to-send signal through P2₆/URTS

pin.

the prescaler and n is the content of UART baud rate generator reg-

ister. The prescalers division ration can be selected by the UART

mode register (see below).

UART mode register (UMOD, Structure of UART

mode register)

Clear-to-send input

When used as a transmitter (transmit enable bit set to “1”), the

UART starts transmission after recognizing “L” level on P2₇/UCTS.

After started the UART will continue to transmit regardless of the

actual level of P2₇/UCTS or status of the transmit enable bit.

The UART mode register allows to select the transmission and

reception format with the following options:

•

•

•

word length: 7, 8 or 9 bits

parity: none, odd or even

stop bits: 1 or 2

Request-to-send output

The UART controls the P2₆/URTS output according to the following

conditions.

Table 5: Output control conditions

It allows to select the prescalers division ratio as well.

P2₆/URTS

“L”

Condition

UART baud rate generator (UBRG)

Receive enable bit is set to “1”

This 8 bit register allows to select the baud rate of the UART (see

above). Set this register to the desired value before enabling recep-

tion or transmission.

Reception completed during receive enable

bit set to “1”

Start bit (falling edge) detected

UART control register (UCON, Structure of UART

control register)

Receive enable bit is set to “0” before recep-

tion started

“H”

Hardware reset

The UART control register consists of four control bits (bit 0 to bit 3)

which allow to control reception and transmission.

Receive initialization bit is set to “1”

data bus

UART control register

UMOD_{2, 1}

UART status register

transmit buffer (9)

transmit buffer empty interrupt request

transmit buffer empty flag

φ

“00”

1

UMOD_{7, 6}

transmit register empty interrupt request

P2₅/UTXD

“01”

1/8

UBRG (8)

bit counter

transmit shift register (9)

UMOD_4,3,2

“10”

1/32

“11”

1/256

transmit register empty flag

P2₇/UCTS

transmission

control circuit

reception control

circuit

P2₆/URTS

UMOD_{7, 6}

receive error interrupt request

P2₄/URXD

bit counter

receive shift register (9)

receive buffer (9)

receive error flags

receive buffer full interrupt request

receive buffer full flag

data bus

Fig. 26 Block diagram of UART

27

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7

0

UART mode register

UMOD (address 0020₁₆

)

Not used (“0” when read, do not write “1”)

clock divider selection bits

b2 b1

0

0

1

1

0 : φ divided by 1

1 : φ divided by 8

0 : φ divided by 32

1 : φ divided by 256

Stop bits selection bit

0 : One stop bit

1 : Two stop bits

Parity selection bit

0 : Even parity

1 : Odd parity

Parity enable bit

0 : Parity disabled

1 : Parity enabled

UART word length selection bits

b7 b6

0

0

1

1

0 : 7 bits

1 : 8 bits

0 : 9 bits

1 : Not used

Fig. 27 Structure of UART mode register

7

0

UART control register

UCON (address 0022₁₆

)

Transmit enable bit

0 : Transmit disabled (an ongoing transmission will be finished correctly)

1 : Transmit enabled

Receive enable bit

0 : Receive disabled (an ongoing reception will be finished correctly)

1 : Receive enabled

Transmission initialization bit

0 : No action

1 : Clear transmit buffer full flag and transmit shifter full flag, set the

transmit status register bits and stop transmission

Receive initialization bit

0 : No action

1 : Clear receive status flags and the receive enable bit

Not used (“0” when read, do not write “1”)

Fig. 28 Structure of UART control register

28

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7

0

UART status register (address 0023₁₆

)

USTS

Transmit register empty flag

0 : Register full

1 : Register empty

Transmit buffer empty flag

0 : Buffer full

1 : Buffer empty

Receive buffer full flag

0 : Buffer full

1 : Buffer empty

Receive parity error flag

0 : No parity error detected

1 : Parity error detected

Receive framing error flag

0 : No framing error detected

1 : Framing error detected

Receive overrun flag

0 : No overrun detected

1 : Overrun detected

Receive error sum flag

0 : No error detected

1 : Error detected

Not used (“0” when read)

Note: this register is read only; writing does not affect its contents.

Fig. 29 Structure of UART status register

29

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

CAN MODULE

The CAN (Controller Area Network) interface of the 7630 group

complies with the 2.0B specification, enabling reception and trans-

mission of frames with either 11- or 29- bit identifier length. Refer to

Fig. 31 for a block diagram of the CAN interface.

CAN Bus Timing Control

Each bit-time consists of four different segments (see Fig. 30):

•

•

•

•

Synchronization segment (SS),

Propagation time segment (PTS),

Phase buffer segment 1 (PBS1) and

Phase buffer segment 2 (PBS2).

The programmer’s interface to the CAN module is formed by three

status/control registers (Fig. 32, Fig. 33, Fig. 34), two bus timing

control registers (Fig. 35 Fig. 36), several registers for acceptance

filtering (Fig. 37), the transmit and receive buffer registers (Fig. 38)

and one dominant level control bit (Fig. 22).

Bit-time

SS

PTS

PBS1

PBS2

Baud Rate Selection

A programmable clock prescaler is used to derive the CAN mod-

ule’s basic clock from the internal system clock frequency (φ). Bit 0

to bit 3 of the CAN bus timing control register represent the pres-

caler allowing a division ratio from 1 to 1/16 to be selected. So the

CAN module basic clock frequency f_CANBcan be calculated as fol-

lows:

Sample point

Fig. 30 Bit time of CAN module

The first of these segments is of fixed length (one Time Quantum)

and the latter three can be programmed to be 1 to 8 Time Quanta

by the CAN bus timing control register 1 and 2 (see Fig. 35 and Fig.

36). The whole bit-time has to consist of minimum 8 and maximum

25 Time Quanta. The duration of one Time Quantum is the cycle

time of f_CANB. For example, assuming φ = 5 MHz, p = 0, one Time

Quantum will be 200 ns long. This allows the maximum transmis-

sion rate of 625 kb/s to be reached (assuming 8 Time Quanta per

bit-time).

φ

p + 1

-----------

f_CANB

=

where p is the value of the prescaler (selectable from 1 to 15). The

effective baud rate of the CAN bus communication depends on the

CAN bus timing control parameters and will be explained below.

data bus

bus timing control

register

acceptance mask

register

acceptance code

register

polarity control

register

CAN status/control

registers

receive buffer 1

acceptance filter

P3₁/CTX

P3₂/CRX

receive buffer 2

protocol controller

wake-up logic

transmit buffer

CAN wake-up

data bus

Fig. 31 Block diagram of CAN module

30

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7

0

CAN transmit control register (address 0030₁₆

)

CTRM

Sleep control bit

0 : CAN module in normal mode

1 : CAN module in sleep mode

Reset/configuration control bit

0 : CAN module in normal mode

1 : CAN module in configuration mode (plus reset at write)

Port double function control bit

0 : P3₁/CTX serves as I/O port

1 : P3₁/CTX serves as CTX output port

Transmit request bit

0: No transmission requested

1 : Transmission requested

(write “0” has no effect)

Not used (no operation, “0” when read)

Transmit buffer control bit

0: CPU access possible

1 : No CPU access

(write “0” has no effect, while CTRM(3) = 1)

Not used (no operation, “0” when read)

Transmit status bit (read only)

0 : CAN module idle or receiving

1 : CAN module transmitting

Fig. 32 Structure of CAN transmit control register

31

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7

0

CAN receive control register (address 003D₁₆

)

CREC

Receive buffer control bit

0 : Receive buffer empty

1 : Receive buffer full

(write “1” has no effect)

Receive status bit (read only)

0 : CAN module idle or transmitting

1 : CAN module receiving

Not used (do not write “1”, read as “0”)

Auto-receive disable bit

0 : Auto-receive enabled

1 : Auto-receive disabled

Note: Suppresses reception of self initiated/transmitted frames

Not used (do not write “1”, “0” when read)

Fig. 33 Structure of CAN receive control register

7

0

CAN transmit abort register (address 003E₁₆

CABORT

)

Transmit Abort control bit

0 : No Transmit Abort Request

1 : Transmit Abort Request

(write “1” has no effect, while CTRM(3) = 0)

Not used (No operation, “0” when read)

Fig. 34 Structure of CAN transmit abort register

32

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7

0

CAN bus timing control register 1 (address 0031₁₆)

CBTCON1

Prescaler division ratio selection bits

b3 b2 b1 b0

0 0 0 0: φ divided by 1

0 0 0 1: φ divided by 2

0 0 1 0: φ divided by 3

…

1 1 1 0: φ divided by 15

1 1 1 1: φ divided by 16

Sampling control bit

0 : One sample per bit

1 : Three sample per bit

Propagation time duration control bits

b7 b6 b5

0 0 0: One Time Quantum

0 0 1: Two Time Quanta

…

1 1 0: Seven Time Quanta

1 1 1: Eight Time Quanta

Fig. 35 Structure of CAN bus timing control register 1

7

0

CAN bus timing control register 2 (address 0032₁₆

CBTCON2

)

Phase buffer segment 1 duration control bits

b2 b1 b0

0 0 0: One Time Quantum

0 0 1: Two Time Quanta

…

1 1 0: Seven Time Quanta

1 1 1: Eight Time Quanta

Phase buffer segment 2 duration control bits

b5 b4 b3

0 0 0: One Time Quantum

0 0 1: Two Time Quanta

…

1 1 0: Seven Time Quanta

1 1 1: Eight Time Quanta

Synchronization jump width control bits

b7 b6

0 0 : One Time Quantum

0 1 : Two Time Quanta

1 0 : Three Time Quanta

1 1 : Four Time Quanta

Fig. 36 Structure of CAN bus timing control register 2

33

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

name

CAC0

address

0033₁₆

7

0

Not used Not used Not used CSID₁₀

CSID₉

CSID₁

CSID₈

CSID₇

CSID₆

Acceptance code

registers:

CAC1 CSID₅

CSID₄

CSID₃

CSID₂

CSID₀Not used Not used 0034₁₆

CAC2 Not used Not used Not used Not used CEID₁₇CEID₁₆CEID₁₅CEID₁₄

0035₁₆

0036₁₆

CAC3 CEID₁₃CEID₁₂CEID₁₁CEID₁₀

CAC4 CEID₅

CEID₄CEID₃CEID₂

CEID₉

CEID₁

CEID₈

CEID₇

CEID₆

CEID₀Not used Not used 0037₁₆

Select the bit pattern of identifiers which allows to pass acceptance filtering.

7

0

Acceptance mask

registers:

CAM0

CAM1

CAM2

CAM3

CAM4

0038₁₆

0039₁₆

003A₁₆

003B₁₆

003C₁₆

Not used Not used Not used MSID₁₀MSID₉

MSID₅MSID₄MSID₃MSID₂MSID₁

Not used Not used Not used Not used MEID₁₇MEID₁₆MEID₁₅MEID₁₄

MEID₁₃MEID₁₂MEID₁₁MEID₁₀MEID₉MEID₈MEID₇MEID₆

MEID₀Not used Not used

MSID₈

MSID₇

MSID₆

MSID₀Not used Not used

MEID₅

MEID₄

MEID₃

MEID₂

MEID₁

0 : Mask identifier bit (do not care)

1 : Compare identifier bit with acceptance code register bit

(Not used: write to “0”)

Fig. 37 Structure of CAN mask and code registers

name

CTB0, CRB0 Not used Not used Not used SID₁₀

offset

7

0

SID₉

SID₁

SID₈

SID₀

EID₁₆

EID₈

EID₀

DLC₂

SID₇

RTR/SRR

EID₁₅

EID₇

SID₆

IDE

0000₁₆

CTB1, CRB1

SID₅

SID₄

SID₃

SID₂

0001₁₆

0002₁₆

0003₁₆

0004₁₆

0005₁₆

0006₁₆

0007₁₆

0008₁₆

0009₁₆

000A₁₆

000B₁₆

000C₁₆

000D₁₆

CTB2, CRB2 Not used Not used Not used Not used EID₁₇

EID₁₄

EID₆

r1

CTB3, CRB3

CTB4, CRB4

EID₁₃

EID₅

EID₁₂

EID₄

EID₁₁

EID₃

EID₁₀

EID₂

r₀

EID₉

EID₁

DLC₃

RTR

CTB5, CRB5 Not used Not used Not used

CTB6, CRB6

DLC₁

DLC₀

data byte 0

CTB7, CRB7

data byte 1

data byte 2

data byte 3

data byte 4

data byte 5

data byte 6

data byte 7

CTB8, CRB8

CTB9, CRB9

CTBA, CRBA

CTBB, CRBB

CTBC, CRBC

CTBD, CRBD

Calculate the actual address as follows:

TxD buffer address = 0040₁₆+ offset

RxD buffer address = 0050₁₆+offset

(Not used: write to “0”)

Fig. 38 Structure of CAN transmission and reception buffer registers

Note 1:

All CAN related SFRs must not be written in “CAN sleep” mode.

34

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

A-D CONVERTER

The A-D converter uses the successive approximation method with

8 bit resolution. The functional blocks of the A-D converter are

described below. Refer to Block diagram of A-D converter.

Channel Selector

The channel selector selects one of ports P0₀/AN₀to P0₇/AN₇, and

inputs its voltage to the comparator.

Comparison Voltage Generator

A-D conversion register AD

The comparison voltage generator divides the voltage between

AV_SSand V_REFby 256, and outputs the divided voltage.

The A-D conversion register is a read-only register that stores the

result of an A-D conversion. This register must not be read during

an A-D conversion.

Data bus

b7

b0

A-D control register

3

A-D control circuit

A-D interrupt request

P0₀/AN₀

A-D conversion register

Comparator

comparison voltage

generator

P0₇/AN₇

V_REF/Input switch bit

V_REF

AV_SS

Fig. 39 Block diagram of A-D converter

D conversion, and changes to “1” when an A-D conversion ends.

A-D control register (Structure of A-D control reg-

ister)

Writing “0” to this bit starts the A-D conversion. Bit 4 is the V_REF

/

Input switch bit.

The A-D control register controls the A-D conversion process. Bits 0

to 2 select a specific analog input pin. Bit 3 signals the completion

of an A-D conversion. The value of this bit remains “0” during an A-

35

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7

0

A-D control register (address 0015₁₆

)

ADCON

Analog input pin selection bits

b2 b1 b0

0 0 0 : P0₀/AN₀

0 0 1 : P0₁/AN₁

0 1 0 : P0₂/AN₂

0 1 1 : P0₃/AN₃

1 0 0 : P0₄/AN₄

1 0 1 : P0₅/AN₅

1 1 0 : P0₆/AN₆

1 1 1 : P0₇/AN₇

A-D conversion completion bit

0 : Conversion in progress

1 : Conversion completed

V_REF/Input switch bit

0 : Off

1 : On

Not used (“0” when read, do not write “1”)

Fig. 40 Structure of A-D control register

rupt request bit to “1”. The result of A-D conversion can be obtained

A-D Converter Operation

from the A-D conversion register, AD (address 0014₁₆).

Note that the comparator is linked to a capacitor, so set f(X_IN) to 500

kHz or higher during A-D conversion.

The comparator and control circuit reference an analog input volt-

age with the reference voltage, then stores the result in the A-D

conversion register. When an A-D conversion is complete, the con-

trol circuit sets the A-D conversion completion bit and the A-D inter-

36

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

WATCHDOG TIMER

The watchdog timer consists of two separate counters: one 7-bit

counter (WD_H) and one 4-bit counter (WD_L). Cascading both

counters or using the high-order counter allows only to select the

time-out from either 524288 or 32768 cycles of the internal clock φ.

Refer to Fig. 41 and Fig. 42. Both counters are addressed by the

same watchdog timer register (WDT). When writing to this register,

both counters will be set to the following default values:

Once the WDT register is written to, the watchdog timer starts

counting down and the watchdog timer interrupt is enabled. Once it

is running, the watchdog timer cannot be disabled or stopped

except by reset. On a watchdog timer underflow, a non-maskable

watchdog timer interrupt will be requested.

To prevent the system being stopped by STP instruction, this

instruction can be disabled by the STP instruction disable bit of

WDT register. Once the STP instruction is disabled, it cannot be

enabled again except by RESET.

•

•

the high-order counter will be set to address 7F₁₆

the low-order counter will be set to address F₁₆

regardless of the data written to the WDT register. Reading the

watchdog timer register will return the corresponding control bit sta-

tus, not the counter contents.

“1”

φ

“0”

1/256

WD_Lcounter (4)

“F₁₆

WD_Hcounter (7)

“7F₁₆

WDT interrupt

WDT₇

”

”

WDT register (8)

Fig. 41 Block diagram of watchdog timer

7

0

Watchdog timer register (address 002E₁₆

WDT

)

Not used (undefined when read)

Stop instruction disable bit

0 : Stop instruction enabled

1 : Execute two NOP instructions instead (once this bit is set to

“1” it can not be cleared to “0” again, except on RESET.)

Upper byte count source selection bit

0 : Underflow of the low order counter

1 : φ divided by 256

Fig. 42 Structure of watchdog timer register (φ is internal clock system)

37

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

RESET CIRCUIT

The 7630 group is reset according to the sequence shown in Fig.

44. It starts program execution from the address formed by the con-

tents of the addresses FFFB₁₆and FFFA₁₆, when the RESET pin is

held at “L” level for more than 2 µs while the power supply voltage is

in the recommended operating condition and then returned to “H”

level.

Refer to Fig. 43 for an example of the reset circuit.

power on

4.0V

power source voltage

0V

reset input voltage

0V

0.8V

V_CC

1

5

4

RESET

M51953AL

0.1µF

3

V_SS

7630 group

Fig. 43

Example of reset circuit

X_IN

RESET

internal reset

Address

Data

?

?

?

?

?

FFFA₁₆

FFFB₁₆AD_L, AD_H

…

1st op code

?

?

?

?

?

AD_L

AD_H

28 to 34

cycles of X_IN

24 cycles of X_IN

20 cycles of X_IN

8192 cycles of

_IN(T1, T2)

X

Fig. 44 Reset sequence

38

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Register

Address

Register contents

Register

Address

Register contents

0000₁₆

0002₁₆

0003₁₆

0004₁₆

0005₁₆

0006₁₆

0007₁₆

0008₁₆

0009₁₆

000A₁₆

000B₁₆

000C₁₆

000D₁₆

000E₁₆

000F₁₆

0010₁₆

0011₁₆

0013₁₆

0015₁₆

0016₁₆

0017₁₆

0018₁₆

0019₁₆

001A₁₆

48₁₆

00₁₆

00₁₆

00₁₆

00₁₆

00₁₆

00₁₆

00₁₆

00₁₆

00₁₆

00₁₆

00₁₆

00₁₆

00₁₆

00₁₆

00₁₆

00₁₆

00₁₆

08₁₆

FF₁₆

01₁₆

FF₁₆

40₁₆

FF₁₆

001B₁₆

001C₁₆

001D₁₆

001E₁₆

001F₁₆

0020₁₆

0022₁₆

0023₁₆

0028₁₆

0029₁₆

002A₁₆

002B₁₆

002C₁₆

002D₁₆

002E₁₆

002F₁₆

0030₁₆

0031₁₆

0032₁₆

003D₁₆

003E₁₆

(PS)

FF₁₆

CPU mode reg.

Interrupt request reg. A

Interrupt request reg. B

Interrupt request reg. C

Interrupt control reg. A

Interrupt control reg. B

Interrupt control reg. C

Port P0 reg.

Timer XH

FF₁₆

Timer YL

FF₁₆

Timer YH

00₁₆

Timer X mode reg.

00₁₆

Timer Y mode reg.

00₁₀

UART mode reg.

00₁₆

UART control reg.

07₁₀

UART status reg.

00₁₆

Port P0 direction reg.

Port P1 reg.

Port P0 pull-up control reg.

Port P1 pull-up control reg.

Port P2 pull-up control reg.

Port P3 pull-up control reg.

Port P4 pull-up/down control reg.

Interrupt polarity selection reg.

Watchdog timer reg.

00₁₆

00₁₆

Port P1 direction reg.

Port P2 reg.

00₁₆

00₁₆

Port P2 direction reg.

Port P3 reg.

00₁₆

3F₁₆

Port P3 direction reg.

Port P4 reg.

00₁₆

Polarity control reg.

02₁₆

Port P4 direction reg.

Serial I/O control reg.

A-D control reg.

Timer 1

CAN transmit control reg.

CAN bus timing control reg. 1

CAN bus timing control reg. 2

CAN receive control reg.

CAN transmit abort reg.

Processor status reg.

Program counter (high-order byte)

Program counter (low-order byte)

00₁₆

00₁₆

00₁₆

00₁₆

Timer 2

04₁₆

Timer 3

contents of FFFB₁₆

contents of FFFA₁₆

Timer 123 mode reg.

Timer XL

(PCH)

(PCL)

Note: The contents of RAM and registers other than the above registers are undefined after reset; thus software initialization is required.

Fig. 45 Internal status of microcomputer after reset

39

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

CLOCK GENERATING CIRCUIT

The 7630 group is equipped with an internal clock generating cir-

cuit.

Please refer to Fig. 46 for a circuit example using a ceramic resona-

tor or quartz crystal oscillator. For the capacitor values, refer to the

manufacturers recommended parameters which depend on each

oscillators characteristics. When using an external clock, input it to

the X_INpin and leave X_OUTopen.

X_IN

X_OUT

C_IN

C_OUT

Fig. 46

Ceramic resonator circuit

.

clock oscillation becomes stable. When using reset, a fixed time-out

will be generated allowing oscillation to stabilize.

Wait mode

Oscillation Control

The 7630 group has two low power modes: the stop and the wait

mode.

The microcomputer enters the wait mode by executing the WIT

instruction. The internal clock ø stops at “H” level while the oscillator

keeps running.

Stop mode

The microcomputer enters the stop mode by executing the STP

instruction. The oscillator stops with the internal clock φ at “H” level.

Timers 1 and 2 will be cascaded and initialized by their reload

latches contents. The count source for timer 1 will be set to

f(X_IN)/16.

Recovery from wait mode can be done in the same way as from

stop mode. However, the time-out period mentioned above is not

required to return from wait-mode, thus no such time-out mecha-

nism has been implemented.

Oscillation is restarted if an external interrupt is accepted or at

reset. When using an external interrupt, the internal clock φ remains

at “H” level until timer 2 underflows allowing a time-out until the

Note: Set the interrupt enable bit of the interrupt source to be used

to return from stop or wait mode to “1” before executing STP or WIT

instruction.

X_OUT

1/4

“1”

X_IN

“0”

1/2

CPUM₆

internal clock

for

peripherals

φ

R

S

Q

D

T

Q

interrupt request

interrupt disable flag

S

R

Q

STP

RESET

STP

delay

2

internal clock

for CPU

R

S

Q

Q

φ

D

T

Q

STP

WIT

oscillator countdown

(timer 1 and 2)

R

S

P2

Fig. 47 Block diagram of clock generating circuit

40

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

DATA REQUIRED FOR MASK ORDERS

The PROM of the blank One Time PROM version is not tested or

screened in the assembly process and following processes. To

ensure proper operation after programming, the procedure shown

in Fig. 48 is recommended to verify programming.

The following are necessary when ordering a mask ROM produc-

tion:

1

2

3

Mask ROM Order Confirmation Form

Mark Specification Form

Contents of Mask ROM, in EPROM form (three identical

copies)

Programming with PROM programmer

PROM PROGRAMMING METHOD

The built-in PROM of the blank One Time PROM version and built-

in EPROM version can be read or programmed with a general pur-

pose PROM programmer using a special programming adapter. Set

the address of PROM programmer to the user ROM area.

Screening *(Note)

(150 °C for 40 hours)

For the programming adapter type name, please refer to the follow-

ing table:

Verification with PROM programmer

Functional test in target unit

Table 6: Programming adapter name

MCU type

Package

Programming adapter type

One Time

PROM

44P6N-A

80D0

PCA7430

PCA7431

EPROM

Note on screening:

The screening temperature is far higher than the storage temper-

ature. Never subject the device to 150 °C exceeding 100 hours.

Fig. 48 Programming and testing of One Time PROM version

41

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Table 7: ABSOLUTE MAXIMUM RATINGS

Symbol

V_CC

Parameter

Conditions

Ratings

Unit

V

Power source voltage

Input voltage

–0.3 to 7.0

P0₀—P0₇, P1₁—P1₇,

V_I

P2₀—P2₇, P3₀—P3₄,

P4₀—P4₇, RESET, X_IN

–0.3 to V_CC+ 0.3

–0.3 to V_CC+ 0.3

V

V

All voltages with respect to V_SS

and output transistors are “off”.

Output voltage

P0₀—P0₇, P1₂—P1₇,

P2₀—P2₇, P3₀—P3₄,

P4₀—P4₇, X_OUT

V_O

P_d

Power dissipation

Ta = 25 °C

500

mW

°C

T_opr

T_stg

Operating temperature

Storage temperature

–40 to 85

–60 to 150

°C

(V_CC= 4.0 to 5.5 V, V_SS= AV_SS= 0 V, T_a= – 40 to 85 °C unless otherwise noted)

Table 8: RECOMMENDED OPERATING CONDITIONS

Limits

Symbol

Parameter

Unit

min.

4.0

typ.

max.

5.5

V_CC

V_SS

5.0

0

V

V

Power source voltage

“H” Input voltage

P0₀—P0₇, P1₁—P1₇, P2₀—P2₇,

P3₀—P3₄, P4₀—P4₇, RESET, X_IN

V_IH

V_IL

0.8 · V_CC

0

V_CC

0.2 · V_CC

–80

V

V

P0₀—P0₇, P1₁—P1₇, P2₀—P2₇,

P3₀—P3₄, P4₀—P4₇, RESET, X_IN

“L” Input voltage

P0₀—P0₇, P1₂—P1₇, P2₀—P2₇,

P3₀—P3₄, P4₀—P4₇

“H” sum peak output current

mA

∑ ^I_OH(peak)

“H” sum average output current

“L” sum peak output current

“L” sum average output current

–40

80

mA

mA

mA

∑ ^I_OH(avg)

∑ ^I_OL(peak)

40

∑ ^I_OL(avg)

I_OH(peak)

I_OH(avg)

“H” peak output current

“H” average output current

“L” peak output current

“L” average output current

–10

–5

10

5

mA

mA

mA

mA

I_OL(peak)

I_OL(avg)

input current at overvoltage condi-

tion

P1₁—P1₇, P2₀—P2₇,

P3₀—P3₄, P4₀—P4₇

I_IO

1

mA

(V_I> V_CC

)

total input current at overvoltage

condition

P1₁—P1₇, P2₀—P2₇,

P3₀—P3₄, P4₀—P4₇

16

mA

∑ ^I_IO

(V_I> V_CC

)

P1₄/CNTR₀, P1₅/CNTR₁

(except bi-phase counter mode)

f(X_IN)/16

MHz

Timer input frequency

(based on 50 % duty)

f(CNTR)

f(X_IN)

P1₃/TX₀, P1₄/CNTR₀

(bi-phase counter mode)

f(X_IN)/32

10

MHz

MHz

Clock input oscillation frequency

42

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Table 9: ELECTRICAL CHARACTERISTICS

(V_CC= 4.0 to 5.5 V, V_SS= AV_SS= 0 V, T_a= – 40 to 85 °C unless otherwise noted)

Limits

Symbol

Parameter

Test conditions

Unit

min.

typ.

max.

P0₀—P0₇, P1₂—P1₇,

V_OH

P2₀—P2₇, P3₀—P3₄,

P4₀—P4₇

I_OH= –5 mA

0.8 · V_CC

“H” output voltage

“L” output voltage

V

V

P0₀—P0₇, P1₂—P1₇,

P2₀—P2₇, P3₀—P3₄,

P4₀—P4₇

V_OL

I_OL= 5 mA

2.0

P1₁/INT₀, P1₂/INT₁,

P1₃/TX₀, P1₄/CNTR₀,

P1₅/CNTR₁,P2₀/S_IN,

V

_T+– V_T–

Hysteresis

0.5

V

P2₂/S_CLK, P2₆/U_RTS

,

P2₇/U_CTS, P3₂/CRX,

RESET

P0₀—P0₇, P1₁—P1₇,

P2₀—P2₇, P3₀—P3₄,

P4₀—P4₇, RESET

I_IH

I_IH

I_IL

V_I= V_CC

V_I= V_CC

V_I= V_SS

V_I= V_SS

“H” input current

“H” input current

“L” input current

5

µA

µA

µA

X_IN

4

P0₀—P0₇, P1₁—P1₇,

P2₀—P2₇, P3₀—P3₄,

P4₀—P4₇, RESET

–5

I_IL

X_IN

“L” input current

“H” input current

–4

µA

µA

P3₂,

P4₀—P4₇

V_I= V_CC

Pull-Down = ’On’

I_IH

20

200

-20

P0₀—P0₇, P1₁—P1₇,

P2₀—P2₇, P3₀—P3₄,

P4₀—P4₇, RESET

V_I= V_SS

Pull-Up = ’On’

“L” input current

I_IL

-200

2.0

µA

V_RAM

RAM hold voltage

When clock stopped

V

43

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Limits

Symbol

Parameter

Test conditions

Unit

mA

min.

typ.

max.

18.0

high speed mode,

f(X_IN) = 8MHz, V_CC= 5V,

output transistors off,

CAN module running,

ADC running

11.0

high speed mode,

f(X_IN) = 8MHz, V_CC= 5V,

output transistors off,

CAN module stopped,

ADC running

9.0

6.0

16.0

11.0

mA

mA

mA

middle speed mode,

f(X_IN) = 8MHz, V_CC= 5V,

output transistors off,

CAN module running,

ADC running

I_CC

Power source current

middle speed mode, wait

mode, f(X_IN) = 8MHz,

V_CC= 5V, output transis-

tors off, CAN module

stopped, ADC stopped

2.0

0.1

stop mode, f(X_IN) = 0MHz,

V_CC= 5V, T_a= 25°C

1.0

µA

µA

stop mode, f(X_IN) = 0MHz,

V_CC= 5V, T_a= 85°C

10.0

(V_CC= 4.0 to 5.5 V, V_SS= AV_SS= 0 V, T_a= –40 to 85 °C, unless otherwise noted)

Limits

Table 10: A-D converter characteristics

Symbol

Parameter

Test conditions

Unit

min.

typ.

max.

—

—

Resolution

8

Bit

Absolute accuracy

±1.0

±2.5

108

432

V_CC

200

LSB

t_C(X_IN)

t_C(X_IN)

high–speed mode

middle–speed mode

106

424

2.0

t_CONV

Conversion time

V_REF

I_REF

R_LADDER

I_IAN

Reference input voltage

Reference input current

Ladder resistor value

Analog input current

V

V_CC= V_REF= 5.12 V

150

35

µA

kΩ

µA

V_I= V_SSto V_CC

0.5

5.0

44

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Table 11: Timing requirements

(V_CC=4.0 to 5.5 V, V_SS=AV_SS=0 V, T_a=–40 to 85 °C unless otherwise noted)

Limits

typ.

Symbol

Parameter

Unit

min.

max.

Reset input “L” pulse width

2

µs

ns

ns

ns

t_W(RESET)

t_C(X_IN)

External clock input cycle time

100

37

t_WH(X_IN)

External clock input “H” pulse width

External clock input “L” pulse width

t

_WL(X_IN)

37

CNTR₀, CNTR₁input cycle time

(except bi-phase counter mode)

1600

2000

800

ns

ns

ns

ns

ns

ns

ns

t_C(CNTR)

CNTR₀input cycle time (bi-phase counter mode)

CNTR₀, CNTR₁input “H” pulse width

(except bi-phase counter mode)

t_WH(CNTR)

CNTR₀input “H” pulse width (bi-phase counter mode)

1000

800

CNTR₀, CNTR₁input “L” pulse width

(except bi-phase counter mode)

t_WL(CNTR)

CNTR₀input “L” pulse width (bi-phase counter mode)

1000

500

Lag of CNTR₀and TX₀input edges

(bi-phase counter mode)

t_L(CNTR₀-TX₀)

t_C(TX₀)

TX₀input cycle time (bi-phase counter mode)

TX₀input “H” pulse width (bi-phase counter mode)

TX₀input “L” pulse width (bi-phase counter mode)

INT₀, INT₁input “H” pulse width

3200

1600

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

t_WH(TX₀)

t

t

_WL(TX₀)

_WH(INT)

1600

460

t_WL(INT)

t_C(S_CLK

_WH(S_CLK

t_WL(S_CLK

_SU(S_IN–S_CLK

t_H(S_CLK–S_IN)

INT₀, INT₁input “L” pulse width

460

)

8 · t_C(X_IN)

4 · t_C(X_IN)

4 · t_C(X_IN)

200

Serial I/O clock input cycle time

t

)

Serial I/O clock input “H” pulse width

Serial I/O clock input “L” pulse width

Serial I/O input setup time

)

t

)

Serial I/O input hold time

150

45

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Table 12: Switching characteristics

(V_CC= 4.0 to 5.5 V, V_SS= AV_SS= 0 V, T_a= –40 to 85 °C, unless otherwise noted)

Limits

Symbol

Parameter

Unit

min.

typ.

max.

t_WH(S_CLK

_WL(S_CLK

t_D(S_CLK–S_OUT

t_V(S_CLK–S_OUT

t_R(S_CLK

)

Serial I/O clock output “H” pulse width

Serial I/O clock output “L” pulse width

Serial I/O output delay time

Serial I/O output valid time

0.5 · t_C(S_CLK) – 50

0.5 · t_C(S_CLK) – 50

ns

ns

ns

ns

ns

ns

ns

t

)

)

50

50

50

50

50

)

0

)

Serial I/O clock output rise time

CMOS output rise time

t_R(CMOS)

t_F(CMOS)

10

10

CMOS output fall time

measurement output pin

100 pF

CMOS output

Fig. 49 Circuit for measuring output switching characteristics

46

MITSUBISHI MICROCOMPUTERS

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

TIMING DIAGRAM

t_C(TX₀)

t_WH(TX₀)

t_WL(TX₀)

0.8·V_CC

TX₀

0.2·V_CC

t_C(CNTR)

t_WH(CNTR)

0.8·V_CC

t_WL(CNTR)

CNTR₀, CNTR₁

0.2·V_CC

t_WH(INT)

t_WL(INT)

0.8·V_CC

INT₀, INT₁

0.2·V_CC

t_WL(RESET)

RESET

0.2·V_CC

t_C(X_IN

)

t_WH(X_IN

)

t_WL(X_IN)

0.8·V_CC

X_IN

0.2·V_CC

t_C(S_CLK

t_R

)

t_F

t_WL(S_CLK

)

t_WH(S_CLK)

0.8·V_CC

S_CLK

0.2·V_CC

t_H(S_CLK-S_IN

)

t_SU(S_IN-S_CLK

)

0.8·V_CC

0.2·V_CC

S_IN

t_D(S_CLK-S_OUT

)

t_V(S_CLK-S_OUT)

S_OUT

Fig. 50 Timing diagram

47

REVISION

7630 English Data Sheets

REVISION

DATE

Page

MODIFICATIONS

New

Old

1.1

10. 98

“CAN controller” is replaced by “CAN module” in whole

document.

11

11 Schematics (8) and (11) are corrected.

18 Replaced: “PUPD ” with “PUP4 ”

18

26

j

j

26 Replaced: “UT D” with “SOUT”

X

Replaced: “UR D” with “SIN”

X

38

38 Replaced: “FFFB ” with “FFFB ”

H 16

Replaced: “FFFA ” with “FFFA ”

H

16

41

43

Replaced: “44P6N” with “44P6N-A)

(1.2) 13.01.99

43 Values changed:Iih(35, 113) to (20, 200) and Iil(-122, -70) to

(-200, -20); typical values are removed.

10

35

10 Schematic (1) is modified.

35 Fig. 39 is modified.

Revision Report M37630 E4/M4

1

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