M37560MEA-XXXGP [RENESAS]
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER; 单片8位CMOS微机
| 型号： | M37560MEA-XXXGP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 文件： | 总71页 (文件大小：880K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
7560 Group (A version)
REJ03B0039-0102Z
Rev.1.02
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
2003.07.31
Timers ............................................................ 8-bit ✕ 3, 16-bit ✕ 2
Serial I/O1 ..................... 8-bit ✕ 1 (UART or Clock-synchronous)
Serial I/O2 .................................... 8-bit ✕ 1 (Clock-synchronous)
PWM output .................................................................... 8-bit ✕ 1
A-D converter ................................................ 10-bit ✕ 8 channels
D-A converter .................................................. 8-bit ✕ 2 channels
LCD drive control circuit
DESCRIPTION
•
•
•
•
•
•
•
The 7560 group (A version) is the 8-bit microcomputer based on
the 740 family core technology.
The 7560 group (A version) has the LCD drive control circuit, an 8-
channel A-D converter, D-A converter, serial I/O and PWM as ad-
ditional functions.
The various microcomputers in the 7560 group (A version) include
variations of internal memory size and packaging. For details, re-
fer to the section on part numbering.
Bias ......................................................................... 1/2, 1/3
Duty .................................................................. 1/2, 1/3, 1/4
Common output ................................................................ 4
Segment output .............................................................. 40
2 Clock generating circuits
For details on availability of microcomputers in the 7560 group (A
version), refer the section on group expansion.
•
(connect to external ceramic resonatuartz-crystal oscillator)
Watchdog timer ........................................... 14-bit ✕ 1
Power source voltage
FEATURES
Basic machine-language instructions ....................................... 71
•
•
•
•
The minimum instruction execution time ............................ 0.4 µs
In high-speed mode (f(XIN) ................... 4.5 V to 5.5 V
In high-speed mode (f(Hz) ..................... 4.0 V to 5.5 V
In middle-speed mo= 6 MHz) ................. 1.8 V to 5.5 V
In low-speed mo..................................... 1.8 V to 5.5 V
Power dissip
(at 10 MHz oscillation frequency)
Memory size
•
ROM ................................................................ 32 K to 60 K bytes
RAM ............................................................... 1024 to 2560 bytes
Programmable input/output ports ............................................. 55
•
•
•
In high-sp................................................... Typ. 23 mW
z oscillation frequency, VCC = 5 V, Ta = 25 °C)
In loode......................................................Typ. 14 µW
emperature range ................................... – 20 to 85°C
Software pull-up resistors .................................................... Built-in
•
Output ports ................................................................................. 8
•
Input ports .................................................................................... 1
•
Interrupts .................................................. 17 sources, 16 vectors
•
External ................ 7 sources (includes key input interrupt)
Internal ................................................................ 9 sources
Software ................................................................ 1 sourc
LICATIONS
mera, household appliances, consumer electronics, etc.
Rev.1.02 Jul 31, 2003 page 1 of 69
7560 Group (A version)
PIN CONFIGURATION (TOP VIEW)
PIN CONFIGURATION (TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
3
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
9
8
7
6
5
4
3
2
1
0
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
6
7
0
1
2
3
4
5
6
7
M37560MXA-XXXFP
V
V
CC
REF
AVSS
V
COM
COM
COM
COM
3
2
1
0
T
7
P7
P7
1
2
3
/INT0
VL3
VL2
C
2
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 2
Package ty0P6S-A
Fig. 1 Pin configuration (Package type: 100P6S-A)
2 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
SEG12
SEG1
SE
9
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P1
P1
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
4
5
6
7
0
1
2
3
4
5
6
7
/SEG38
/SEG39
G
SEG
SEG
SEG
SEG
5
4
3
2
1
0
V
X
X
X
X
SS
M37560MXA-XXXGP
V
CC
REF
AVSS
OUT
IN
V
COUT
CIN
COM
COM
COM
COM
3
2
1
0
RESET
P7
P7
P7
P7
P7
P7
P7
0
1
2
3
4
5
6
/INT0
V
V
L3
L2
C
C
2
1
V
L1
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Package type : 100P6Q-A
Fig. 2 Pin configuration (Package type: 100P6Q-A)
Rev.1.02 Jul 31, 2003 page 2 of 69
7560 Group (A version)
t p u r r e t n i ) p u e k a w n o - y
n o i t c n u f
2 T N I , 1 T N I
T D A
0 T N I
Fig. 3 Functional block diagram
Rev.1.02 Jul 31, 2003 page 3 of 69
7560 Group (A version)
PIN DESCRIPTION
Table 1 Pin description (1)
Pin
Name
Function
Function except a port function
VCC
VSS
Power source
•Apply voltage of power source to VCC, and 0 V to VSS. (For the limits of VCC, refer to “Recom-
mended operating conditions”.
VREF
Analog refer-
ence voltage
•Reference voltage input pin for A-D converter and D-A converter.
AVSS
Analog power
source
•GND input pin for A-D converter and D-A converter.
•Connect to VSS.
Reset input
Clock input
•Reset input pin for active “L”.
RESET
XIN
•Input and output pins for the main clock generating circuit.
•Connect a ceramic resonator or a quartz-crystal oscillator between tXOUT pins to set
the oscillation frequency.
XOUT
Clock output
•If an external clock is used, connect the clock source to the Xeave the XOUT pin open. A
feedback resistor is built-in.
LCD power
source
•Input 0 ≤ VL1 ≤ VL2 ≤ VL3 voltage.
VL1–VL3
C1, C2
•Input 0 – VL3 voltage to LCD. (0 ≤ VL1 ≤ VL2 ≤ VL3 wge is multiplied.)
•External capacitor pins for a voltage multiplier (3 CD control.
Charge-pump
capacitor pin
Common output
•LCD common output pins.
COM0–COM3
•COM2 and COM3 are not used at 1/2 d
•COM3 is not used at 1/3 duty ratio.
•LCD segment output pins.
SEG0–SEG17 Segment output
P00/SEG26–
P07/SEG33
I/O port P0
•8-bit I/O port.
•LCD segment output pins
•CMOS compatible input
•CMOS 3-state outpu
•Pull-up control is
•I/O direction lows each 8-bit pin to be pro-
grammed aut or output.
P10/SEG34– I/O port P1
P15/SEG39
•6-bit I/O
•CMOble input level.
•Cte output structure.
ontrol is enabled.
rection register allows each 6-bit pin to be pro-
mmed as either input or output.
P16, P17
•2-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually programmed as either input or output.
•Pull-up control is enabled.
P20 – P27
•8-bit I/O port.
•Key input (key-on wake-up) interrupt
input pins
I/O port P2
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•LCD segment output pins
P3
P3
0
7
/SEG18
/SEG25
–
Output port P3
•8-bit output.
•CMOS 3-state output structure.
•Port output control is enabled.
Rev.1.02 Jul 31, 2003 page 4 of 69
7560 Group (A version)
Table 2 Pin description (2)
Pin
Name
Function
Function except a port function
P40
I/O port P4
•1-bit I/O port.
•CMOS compatible input level.
•N-channel open-drain output structure.
•I/O direction register allows this pin to be individually programmed as either input or output.
P41/INT1,
P42/INT2
•INTi interrupt input pins
•7-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
P43/φ/TOUT
•System clock φ output pin
•Timer 2 output pin
•I/O direction register allows each pin to be individually
programmed as either input or output.
P44/RXD,
P45/TXD,
P46/SCLK1,
P47/SRDY1
•Serial I/O1
•Pull-up control is enabled.
•8-bit I/O port.
•t pins
P50/PWM0,
P51/PWM1
I/O port P5
•CMOS compatible input level.
•CMOS 3-state output structure.
time port output pins
Timer X, Y I/O pins
P52/RTP0,
P53/RTP1
•I/O direction register allows each pin to be individ
programmed as either input or output.
P54/CNTR0,
P55/CNTR1
•Pull-up control is enabled.
P56/DA1
•D-A converter output pin
•D-A converter output pin
•A-D external trigger input pin
•A-D converter input pins
•Serial I/O2 I/O pins
P57/ADT/DA2
•8-bit I/O port.
I/O port P6
P6
P6
P6
P6
0/SIN2/AN0,
1
2
3
/SOUT2/AN1,
/SCLK21/AN2,
/SCLK22/AN
•CMOS compatible input level.
•CMOS 3-state output struct
•A-D converter input pins
3
•I/O direction register alpin to be individually
programmed as either utput.
P64/AN4–
P67/AN7
•Pull-up control is e
•1-bit input port.
P70/INT0
P71–P77
Input port P7
I/O port P7
•INT0 interrupt input pin
•7-bit I/O po
•CMOS input level.
•N-chn-drain output structure.
•Iregister allows each pin to be individually programmed as either input or output.
k generating circuit I/O pins.
XCOUT
XCIN
Sub-clock output
Sub-clock inpu
nect a oscillator. External clock cannot be used.)
Rev.1.02 Jul 31, 2003 page 5 of 69
7560 Group (A version)
PART NUMBERING
Product
M37560
M
F
A
–
XXX FP
Package type
FP : 100P6S-A
GP : 100P6Q-A
ROM number
Characteristics
A : A version
ROM size
1
2
3
4
5
6
A
B
C
D
E
F
: 4096 bytes
: 8192 by
: 1228
: 16
: tes
bytes
72 bytes
2768 bytes
: 36864 bytes
: 40960 bytes
: 45056 bytes
: 49152 bytes
: 53248 bytes
: 57344 bytes
: 61440 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used.
Memory type
M: Mask ROM version
Fig. 4 Part numbering
Rev.1.02 Jul 31, 2003 page 6 of 69
7560 Group (A version)
GROUP EXPANSION
Renesas expands the 7560 group (A version) as follows.
Packages
100P6Q-A .................................. 0.5 mm-pitch plastic molded QFP
100P6S-A ................................ 0.65 mm-pitch plastic molded QFP
Memory Type
Support for mask ROM version.
Memory Size
ROM size ........................................................... 32 K to 60 K bytes
RAM size .......................................................... 1024 to 2560 bytes
Memory Expansion Plan
ROM size (bytes)
60K
M37560MFA
56K
52K
48K
44K
40K
36K
32K
28K
24K
M37560M8A
20K
16K
12K
8K
4K
192 256
768
1024
1280
1536
1792
2048
2304
2560
RAM size (bytes)
Proevelopment or planning: the development schedule and specification may be revised
e. The development of planning products may be stopped.
Fig. 5 Memory expa
Currently planning products are listed below.
As of Jul. 2003
Table 3 Support products
ROM size (bytes)
Part number
RAM size (bytes)
1024
Package
Remarks
ROM size for User in (
)
M37560M8A-XXXFP
32768
100P6S-A Mask ROM version
100P6Q-A Mask ROM version
100P6S-A Mask ROM version
100P6Q-A Mask ROM version
(32638)
M37560M8A-XXXGP
M37560MFA-XXXFP
M37560MFA-XXXGP
61440
(61310)
2560
Rev.1.02 Jul 31, 2003 page 7 of 69
7560 Group (A version)
FUNCTIONAL DESCRIPTION
[Stack Pointer (S)]
CENTRAL PROCESSING UNIT (CPU)
The 7560 group uses the standard 740 family instruction set. Re-
fer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack
address are determined by the stack page selection bit. If the
stack page selection bit is “0” , the high-order 8 bits becomes
“0016”. If the stack page selection bit is “1”, the high-order 8 bits
becomes “0116”.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
The central processing unit (CPU) has six registers. Figure 6
shows the 740 Family CPU register structure.
Figure 9 shows the operations of pushing register contents onto
the stack and popping them from the ack. Table 6 shows the
push and pop instructions of accumuprocessor status reg-
ister.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as
arithmetic data transfer, etc., are executed mainly through the ac-
cumulator.
Store registers other than thbed in Figure 9 with pro-
gram when the user needing interrupts or subroutine
calls.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Program CoPC)]
The program a 16-bit counter consisting of two 8-bit
registers PCL. It is used to indicate the address of the
next insbe executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
Accumulator
b0
b0
b0
b0
b0
b
X
Index register X
Index register Y
b7
Y
b7
S
Stack pointer
b15
b7
b7
PCH
PC
L
Program counter
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 6 740 Family CPU register structure
Rev.1.02 Jul 31, 2003 page 8 of 69
7560 Group (A version)
On-going Routine
Execute JSR
Interrupt request
(Note)
M (S) (PC
(S) (S) – 1
M (S) (PC
H
)
Push return address
on stack
M (S) (PC
(S) (S) – 1
M (S) (PC
H)
Push return address
on stack
L
)
(S) (S) – 1
M (S) (PS)
(S) (S) –
L
)
tents of processor
register on stack
(S) (S)– 1
Subroutine
Interr
Servic
I Flag is set from “0” to “1”
Fetch the jump vector
Execute RTS
(S) (S) + 1
RTI
(S) + 1
POP return
POP contents of
processor status
register from stack
address from stack
(PC
(S) (S) + 1
(PC M (S)
L
)
M (S)
(PS)
(S) (S) + 1
(PC M (S)
(S) (S) + 1
(PC M (S)
M (S)
H
)
L
)
POP return
address
from stack
H
)
Note: Condition for acceptancrrupt request here
Interrupt enable bit corresponding to each interrupt source is “1”
Interrupt disable flag is “0”
Fig. 7 Register push op at interrupt generation and subroutine call
Table 4 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PHP
PLA
PLP
Processor status register
Rev.1.02 Jul 31, 2003 page 9 of 69
7560 Group (A version)
[Processor status register (PS)]
• Bit 4: Break flag (B)
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
The B flag is used to indicate that the current interrupt was gen-
erated by the BRK instruction. When the BRK instruction is
generated, the B flag is set to “1” automatically. When the other
interrupts are generated, the B flag is set to “0”, and the proces-
sor status register is pushed onto the stack.
• Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed be-
tween accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled be-
tween memory locations.
• Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arith-
metic logic unit (ALU) immediately after an arithmetic operation.
It can also be changed by a shift or rotate instruction.
• Bit 1: Zero flag (Z)
• Bit 6: Overflow flag (V)
The V flag is used during the addibtraction of one byte
of signed data. It is set to “1” if exceeds +127 to -128.
When the BIT instruction is bit 6 of the memory loca-
tion operated on by the Bon is stored in the V flag.
• Bit 7: Negative flag (N
The Z flag is set to “1” if the result of an immediate arithmetic op-
eration or a data transfer is “0”, and set to “0” if the result is
anything other than “0”.
• Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt gener-
ated by the BRK instruction.
The N flag is set tresult of an arithmetic operation or
data transfer is When the BIT instruction is executed,
bit 7 of the mation operated on by the BIT instruction is
stored in ve flag.
Interrupts are disabled when the I flag is “1”.
• Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed
when this flag is “0”; decimal arithmetic is executed when it is
“1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
Table 5 Instructions to set each bit of processor ster to “0” or “1”
N flag
C flag
SEC
CLC
I flag
SEI
D flag
SED
CLD
B flag
T flag
SET
CLT
V flag
–
–
–
–
–
Instruction setting to “1”
Instruction setting to “0”
CLI
CLV
Rev.1.02 Jul 31, 2003 page 10 of 69
7560 Group (A version)
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the system clock control bits, etc.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM (CM) : address 003B16
1
)
Processor mode bits
b1 b0
0
0
1
1
0 : Single-chip mode
1 :
0 :
1 :
Do not select
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (“1” at readin
(Write “1” to this bit
X
C
switch bit
0 : Oscillati
1 : XCIN–ing function
Main clocstop bit
0 :
1
Msion ratio selection bit
2 (high-speed mode)
N)/8 (middle-speed mode)
clock selection bit
: XIN–XOUT selected (middle-/high-speed mode)
1 : XCIN–XCOUT selected (low-speed mode)
Fig. 8 Structure of CPU mode register
Rev.1.02 Jul 31, 2003 page 11 of 69
7560 Group (A version)
MEMORY
Zero Page
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis-
ters (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
Special Page
ROM
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in special page area. Ac-
cess to this area with only 2 bytes ie in the special page
addressing mode.
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM size
(bytes)
Address
XXXX16
SFR area
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
0A3F16
192
256
Zero page
04016
005416
LCD display RAM area
384
512
010016
AM
640
768
896
XXXX16
1024
1536
2048
2560
Not used
ROM area
ROM size
(bytes)
Ad
Address
ZZZZ16
YYYY16
ZZZZ16
Reserved ROM area
(128 bytes)
4096
0016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
ROM
FF0016
FFDC16
Special page
Interrupt vector area
Reserved ROM area
FFFE16
FFFF16
Fig. 9 Memory map diagram
Rev.1.02 Jul 31, 2003 page 12 of 69
7560 Group (A version)
000016
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
00361
003
6
3B16
003C16
003D16
003E16
003F16
Port P0 register (P0)
Timer X low-order register (TXL)
Timer X high-order register (TXH)
Timer Y low-order register (TYL)
Timer Y high-order register (TYH)
Timer 1 register (T1)
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
Port P0 direction register (P0D)
Port P1 register (P1)
Port P1 direction register (P1D)
Port P2 register (P2)
Port P2 direction register (P2D)
Timer 2 register (T2)
Timer 3 register (T3)
Port P3 register (P3)
Timer X mode register (TXM)
Timer Y mode register (TYM)
Timer 123 mode register (T123M)
Port P3 output control register (P3C)
Port P4 register (P4)
Port P4 direction register (P4D)
Port P5 register (P5)
TOUT/φ output control register (CKOUT)
Port P5 direction register (P5D)
Port P6 register (P6)
PWM control register (PWMCON)
PWM prescaler (PREPWM)
PWM register (PWM)
Port P6 direction register (P6D)
Port P7 register (P7)
Reserved area (Note)
Port P7 direction register (P7D)
Reserved area (Note)
Reserved area (No
Reserved area
D-A1 conve(DA1)
D-A2 coster (DA2)
A-D er (ADCON)
A-D conversion low-order register (ADL)
Key input control register (KIC)
PULL register A (PULLA)
An high-order register (ADH)
l register (DACON)
PULL register B (PULLB)
g timer control register (WDTCON)
Transmit/Receive buffer register(TB/RB)
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CO
UART control register (UARTCO
Baud rate generator (BRG)
ment output enable register (SEG)
LCD mode register (LM)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1(IREQ1)
Interrupt request register 2(IREQ2)
Interrupt control register 1(ICON1)
Interrupt control register 2(ICON2)
Serial I/O2 control register
Reserved area (Note)
Serial I/O2 register
Note: Do he addresses of reserved area.
Fig. 10 Memory map of special functer (SFR)
Rev.1.02 Jul 31, 2003 page 13 of 69
7560 Group (A version)
I/O PORTS
b7
b0
Direction Registers
Port P0 direction register
(P0D : address 000116)
The I/O ports (ports P0, P1, P2, P4, P5, P6, P71–P77) have direc-
tion registers. Ports P16, P17, P4, P5, P6, and P71–P77 can be set
to input mode or output mode by each pin individually. P00–P07
and P10-P15 are respectively set to input mode or output mode in
a lump by bit 0 of the direction registers of ports P0 and P1 (see
Figure 11).
Ports P00 to P07 direction register
0 : Input mode
1 : Output mode
Not used (Undefined at reading)
(If writing to these bits, write “0”.)
When “0” is set to the bit corresponding to a pin, that pin becomes
an input mode. When “1” is set to that bit, that pin becomes an
output mode.
b7
b0
Port P1 direction register
(P1D : addres00316)
If data is read from a port set to output mode, the value of the port
latch is read, not the value of the pin itself. A port set to input mode
is floating. If data is read from a port set to input mode, the value
of the pin itself is read. If a pin set to input mode is written to, only
the port latch is written to and the pin remains floating.
Ports Pdirection register
0
ode
Undefined at reading)
g to these bits, write “0”.)
P16 direction register
rt P17 direction register
0 : Input mode
Port P3 Output Control Register
Bit 0 of the port P3 output control register (address 000716) en-
1 : Output mode
ables control of the output of ports P30–P37.
When the bit is set to “1”, the port output function is valid.
When resetting, bit 0 of the port P3 output control register is set to
“0” (the port output function is invalid) and pulled up.
Note: o output mode, the pull-up control bit becomes
d pull-up resistor is not connected.
ructure of port P0 direction register, port P1 direc-
tion register
b7
b0
Port P3 output control register
(P3C : address 000716)
Ports P30 to P37 output control bit
0 : Output function is invalid (Pulled up)
1 : Output function is valid (No pull up)
Not used (Undefined at reading)
(If writing to these bits, write “0”.)
Note: In pins set to segment output by segment output enable bits
0, 1 (bits 0, 1 of segment output enable register (address
3816)), this bit becomes invalid and pull-up resistor is not
connected.
Fig. 12 Structure of port P3 output control register
Rev.1.02 Jul 31, 2003 page 14 of 69
7560 Group (A version)
Pull-up Control
b7
b0
By setting the PULL register A (address 001616) or the PULL reg-
ister B (address 001716), ports P0 to P2, P4 to P6 can control
pull-up with a program.
PULL register A
(PULLA : address 001616)
P00, P01 pull-up control bit
P02, P03 pull-up control bit
P04–P07 pull-up control bit
P10–P13 pull-up control bit
P14, P15 pull-up control bit
P16, P17 pull-up control bit
P20–P23 pull-up control bit
P24–P27 pull-up control bit
However, the contents of PULL register A and PULL register B do
not affect ports set to output mode and the ports are no pulled up.
The PULL register A setting is invalid for pins selecting segment
output with the segment output enable register and the pins are
not pulled up.
b7
b0
PULL regier B
(PULLB ess 001716)
-up control bit
ull-up control bit
3 pull-up control bit
–P57 pull-up control bit
60–P63 pull-up control bit
P64–P67 pull-up control bit
Not used “0” at reading)
0 : Disable
1 : Enable
Noents of PULL register A and PULL register B
t affect ports set to output mode.
ructure of PULL register A and PULL register B
Rev.1.02 Jul 31, 2003 page 15 of 69
7560 Group (A version)
Table 6 List of I/O port function (1)
Name
Input/Output
Non-Port Function
I/O Format
Related SFRs
Pin
Diagram No.
(1)
P00/SEG26–
P07/SEG33
Port P0
Input/output,
byte unit
CMOS compatible
input level
LCD segment output
PULL register A
Segment output enable
register
(2)
CMOS 3-state output
P10/SEG34–
P15/SEG39
Port P1
Input/output,
6-bit unit
CMOS compatible
input level
LCD segment output
PULL register A
(1)
(2)
Segment output enable
register
CMOS 3-state output
Input/output,
individual bits
CMOS compatible
input level
PULL register A
P16 , P17
P20–P27
(4)
CMOS 3-state output
Port P2
Port P3
Input/output,
individual bits
CMOS compatible
input level
Key input (key-on
wake-up) interrupt
input
PULL rA
Interl register 2
ontrol register
CMOS 3-state output
t output enable
er
(3)
P30/SEG18–
P37/SEG25
Output
CMOS 3-state output
LCD segment output
rt P3 output control
register
CMOS compatible
input level
(13)
P40
Port P4
Input/output,
individual bits
N-channel open-drain
output
CMOS compatible
input level
rrupt input
(4)
Interrupt edge selection
register
P41/INT1,
P42/INT2
CMOS 3-state o
(12)
PULL register B
P43/φ/TOUT
mer 2 output
Timer 123 mode register
System clock φ output
TOUT/φ output control
register
PULL register B
P44/RXD,
P45/TXD,
P46/SCLK1,
P47/SRDY1
Serial I/O1 I/O
(5)
(6)
Serial I/O1 control register
Serial I/O1 status register
UART control register
(7)
(8)
(10)
P50/PWM0,
P51/PWM1
Port P5
Input/ou
indivi
MOS compatible
input level
PWM output
PULL register B
PWM control register
CMOS 3-state output
P52/RTP0,
P53/RTP1
Real time port output
(9)
PULL register B
Timer X mode register
P54/CNTR0
(11)
(14)
PULL register B
Timer X I/O
Timer X mode register
PULL register B
P55/CNTR1
Timer Y input
DA1 output
DA2 output
Timer Y mode register
PULL register B
P56/DA1
(15)
(15)
D-A control register
PULL register B
P57/ADT/
DA2
A-D external trigger
input
D-A control register
A-D control register
Rev.1.02 Jul 31, 2003 page 16 of 69
7560 Group (A version)
Table 7 List of I/O port function (2)
Pin
Name
Input/Output
I/O Format
Non-Port Function
Related SFRS
Diagram No.
P60/SIN2/AN0
Port P6
Input/
A-D converter input
Serial I/O2 I/O
PULL register B
A-D control register
Serial I/O2 control
register
(17)
CMOS compatible input
level
CMOS 3-state output
output,
individual
bits
P61/SOUT2/
AN1
(18)
(19)
(20)
(16)
P62/SCLK21/
AN2
P63/SCLK22 /
AN3
A-D converter input
INT0 interrupt input
A-D control register
PUister B
P64/AN4–
P67/AN7
P70/INT0
Port P7
Input
CMOS compatible input
level
edge
on register
(23)
(13)
P71–P77
Input/
CMOS compatible input
level
output,
individual
bits
N-channel open-drain
output
COM0–COM3
SEG0–SEG17
LCD mode register
Common
Segment
Output
Output
LCD common output
LCD segment output
(21)
(22)
Notes 1: How to use double-function ports as function I/O pins, refer to the applns.
2: Make sure that the input level at each pin is either 0 V or VCC ution of the STP instruction. When an electric potential is at an
intermediate potential, a current will flow from VCC to VSS througtage gate and power source current may increase.
Rev.1.02 Jul 31, 2003 page 17 of 69
7560 Group (A version)
(1) Ports P01–P07, P11–P15
Pull-up
V
L2/VL3/VCC
LCD drive timing
Segment/Port
Segment data
Interface logic level
shift circuit
Segment
Data bus
Port latch
V
L1/VSS
Port direction register
Port
Segment output
enable bit
Port direction register
(2) Ports P00, P10
Pull-up
V
L2/V
LCD drive timing
Segm
Direction register
Segment data
Port latch
Interface logic level
shift circuit
Data bus
V
L1/VSS
Segment output
enable bit
Port
Porgister
(3) Port P3
Pull-up
V
L2/VL3/VCC
Lng
Segment/Port
Segment data
Port latch
ce logic level
shift circuit
Segment
Data bus
Port P3 o
control
V
L1/VSS
Port
Segment output
Port P3 output control bit
enable bit
(4) Ports P1
6
, P1
7
, P
4
2
(5) Port P4
4
Pull-up control
Pull-up control
Serial I/O1 enable bit
Receive enable bit
tion
register
Direction
register
Port latch
Data bus
Port latch
Data bus
Key input interrupt input
INT , INT interrupt input
Except P1 , P1
Serial I/O1 input
1
2
6
7
Fig. 14 Port block diagram (1)
Rev.1.02 Jul 31, 2003 page 18 of 69
7560 Group (A version)
(6) Port P4
5
(7) Port P46
Serial I/O1 synchronous
clock selection bit
Serial I/O1 enable bit
Pull-up control
Pull-up control
P45
/TxD P-channel output disable bit
Serial I/O1 enable bit
Transmit enable bit
Direction
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Direction
register
register
Port latch
Data bus
Port latch
Data bus
Serial I/O1 output
Serial I/O1 clock output
Sock input
(8) Port P4
7
(9) Ports P5
Pull-up control
Pull-up control
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Direction
register
S
RDY1 output enable bit
Direction
register
bus
Port latch
Data bus
Port latch
Real time port control bit
Real time port data
Serial I/O1 ready output
Pull-up control
(11) Port P5
4
(10) Ports P50,P51
Pull-up control
Direction
register
rer
Data bus
Port latch
Data bus
Port latch
Pulse output mode
Timer output
PWM function enable bit
PWM output
CNTR0 interrupt input
Fig. 15 Port block diagram (2)
Rev.1.02 Jul 31, 2003 page 19 of 69
7560 Group (A version)
(13) Ports P40,P71–P77
(12) Port P4
3
Pull-up control
Direction
register
Direction
register
Data bus
Port latch
Port latch
Data bus
T
OUT/φ output enable bit
Timer 2 TOUT output
OUT/φ output selection bit
System clock φ output
T
(15) P57
(14) Port P5
5
Pull-up control
Pull-up control
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
A-D external trigger input
D-A converter output
CNTR1 interrupt inpu
Except P5
6
DA1, DA2 output enable bits
(16) Ports P64–P6
7
(17) Port P6
0
Pull-up control
Pull-up control
Direction
register
Data bus
Port latch
Data bus
Port latch
A-D converter input
Analog input pin selection bit
Serial I/O2 input
A-D converter input
Analog input pin selection bit
Fig. 16 Port block diagram (3)
Rev.1.02 Jul 31, 2003 page 20 of 69
7560 Group (A version)
(19) Port P6
2
(18) Port P6
1
Serial I/O2 synchronous clock
selection bit
Pull-up control
P61/SOUT2 P-channel output disable bit
Pull-up control
Serial I/O2 port selection bit
Synchronous clock output pin
selection bit
Serial I/O2 transmit end signal
Serial I/O2 synchronous clock selection bit
Serial I/O2 port selection bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Serial I/O2 output
Serial I/O2 clock outp
A-D converter input
clock input
Analog input pin selection bit
A-D converter input
Analog input pin selection bit
(20) Port P6
3
Pull-up control
Serial I/O2 synchronous clock selection bit
Serial I/O2 port selection bit
0–COM
3
Synchronous clock output pin selection
bit
Direction
register
The gate input signal of each
transistor is controlled by the LCD
duty ratio and the bias value.
VL2
VL1
Data bus
Port latch
Serial I/O2 clock output
VSS
A-D ut
g input pin selection bit
(23) Port P7
0
(22) SEG0–SEG17
VL2/VL3
Data bus
The voltage applied to the sources of P-
channel and N-channel transistors is the
controlled voltage by the bias value.
INT0
input
VL1/VSS
Fig. 17 Port block diagram (4)
Rev.1.02 Jul 31, 2003 page 21 of 69
7560 Group (A version)
INTERRUPTS
Interrupt Operation
Interrupts occur by seventeen sources: seven external, nine inter-
nal, and one software. When an interrupt request is accepted, the
program branches to the interrupt jump destination address set in
the vector address (see Table 8).
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt jump destination address is read from the vector
table into the program counter.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt is accepted if the
corresponding interrupt request and enable bits are “1” and the in-
terrupt disable flag is “0”.
3. The interrupt disable flag is set to “1” and the corresponding in-
terrupt request bit is set to “0”.
Interrupt enable bits can be set to “0” or “1” by program.
Interrupt request bits can be set to “0” by program, but cannot be
set to “1” by program.
The BRK instruction interrupt and reset cannot be disabled with
any flag or bit. When the interrupt disable (I) flag is set to “1”, all
interrupt requests except the BRK instruction interrupt and reset
are not accepted.
When several interrupt requests occur at the same time, the inter-
rupts are received according to priority.
Table 8 Interrupt vector addresses and priority
t Request
Remarks
Vector Addresses (Note 1)
Interrupt Source
Priority
High
Low
ating Conditions
Reset (Note 2)
1
2
FFFD16
FFFB16
FFFC16
FFFA16
Non-maskable
INT0
etection of either rising or
ling edge of INT0 input
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT1 input
INT1
FFF916
FFF716
FFF516
FF
FF416
External interrupt
(active edge selectable)
3
4
Serial I/O1
reception
At completion of serial I/O1 data
reception
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
At completion of serial I/O1
transmit shift or when transmis-
sion buffer is empty
Serial I/O1
transmission
5
Timer X
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
6
7
F16
FED16
FFEB16
FFF216
FFF016
FFEE16
FFEC16
FFEA16
Timer Y
Timer 2
Timer 3
8
9
CNTR0
At detection of either rising or
falling edge of CNTR0 input
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of CNTR1 input
CNTR1
FFE916
FFE816
External interrupt
(active edge selectable)
FFE616
FFE416
At timer 1 underflow
Timer 1
INT2
12
13
FFE716
FFE516
At detection of either rising or
falling edge of INT2 input
External interrupt
(active edge selectable)
Serial I/O2
At completion of serial I/O2 data
transmission or reception
14
15
16
FFE316
FFE116
FFDF16
FFE216
FFE016
FFDE16
Valid when serial I/O2 is selected
Key input
(Key-on wake-up)
At falling of conjunction of input External interrupt
level for port P2 (at input mode) (valid at falling)
Valid when ADT interrupt is selected
ADT
At falling edge of ADT input
External interrupt
(valid at falling)
At completion of A-D conversion Valid when A-D interrupt is selected
A-D conversion
BRK instruction
17
FFDD16
FFDC16
At BRK instruction execution
Non-maskable software interrupt
Notes1: Vector addresses contain interrupt jump destination addresses.
2: Reset is not an interrupt. Reset has the higher priority than all interrupts.
Rev.1.02 Jul 31, 2003 page 22 of 69
7560 Group (A version)
When not requiring for the interrupt occurrence synchronous with
these setting, take the following sequence.
✕Notes on interrupts
When setting the followings, the interrupt request bit may be set to
“1”.
✕Set the corresponding interrupt enable bit to “0” (disabled).
✕Set the interrupt edge select bit (polarity switch bit) or the inter-
rupt source selection bit.
•When switching external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
Timer X mode register (address 2716)
✕Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
Timer Y mode register (address 2816)
✕Set the corresponding interrupt enable bit to “1” (enabled).
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: Interrupt source selection bit of A-D control reg-
ister (bit 6 of address 3416)
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
Inteceptance
BRK instruction
Reset
Fig. 18 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16
)
INT
INT
INT
0
1
2
interrupt edge selection bit
interrupt edge selection bit
interrupt edge selection bit
Not used (“0” at reading)
ing edge active
Rising edge active
b7
b0
b7
b0
Interrupt request register 2
(IREQ2 : address 003D16
Interrupt request r
(IREQ1 : addre
)
INT
INT
0
inest bit
quest bit
CNTR
CNTR
0
1
interrupt request bit
interrupt request bit
ceive interrupt request bit
transmit interrupt request bit
interrupt request bit
r Y interrupt request bit
mer 2 interrupt request bit
Timer 1 interrupt request bit
INT interrupt request bit
Serial I/O2 interrupt request bit
Key input interrupt request bit
ADT/AD conversion interrupt request bit
Not used (“0” at reading)
2
Timer 3 interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b7
b0
Interrupt control register 1
Interrupt control register 2
0
(ICON1 : address 003E16
)
(ICON2 : address 003F16
)
INT
INT
0
1
interrupt enable bit
interrupt enable bit
CNTR
CNTR
0
1
interrupt enable bit
interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
Timer 1 interrupt enable bit
INT interrupt enable bit
Serial I/O2 interrupt enable bit
Key input interrupt enable bit
ADT/AD conversion interrupt enable bit
Not used (“0” at reading)
2
(Write “0” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 19 Structure of interrupt-related registers
Rev.1.02 Jul 31, 2003 page 23 of 69
7560 Group (A version)
abled. In other words, it is generated when AND of input level
goes from “1” to “0”. A connection example of using a key input in-
terrupt is shown in Figure 22, where an interrupt request is gener-
ated by pressing one of the keys consisted as an active-low key
matrix which inputs to ports P20–P23.
Key Input Interrupt (Key-on Wake Up)
The key input interrupt is enabled when any of port P2 is set to in-
put mode and the bit corresponding to key input control register is
set to “1”.
A Key input interrupt request is generated by applying “L” level
voltage to any pin of port P2 of which key input interrupt is en-
Port PXx
“L” level output
PULL register A
P27 key input control bit
direction register = “1”
Port P27
Bit 7
Key errupt request
✕
✕
✕
✕
✕✕
Port P27
latch
P27 output
P26 output
P25 output
P24 output
P23 input
P21 input
P20 input
P26 key input control bit
direction register = “1”
Port P26
✕✕
Port P26
latch
P25 key input control
Port P25
direction register = “1”
✕✕
Port P25
latch
Pontrol bit
Port P24
direction regi
✕✕
P
PULL register A
Bit 6 =
P23 key input control bit = “1”
n register = “0”
Port P2
Input reading circuit
✕
✕
✕
✕
✕
Port P23
latch
P22 key input control bit = “1”
Port P22
direction register = “0”
✕✕
Port P22
latch
P21 key input control bit = “1”
Port P21
direction register = “0”
✕✕
Port P21
latch
P20 key input control bit = “1”
Port P20
direction register = “0”
✕✕
Port P20
latch
✕
P-channel transistor for pull-up
✕ ✕ CMOS output buffer
Fig. 20 Connection example when using key input interrupt and port P2 block diagram
Rev.1.02 Jul 31, 2003 page 24 of 69
7560 Group (A version)
The key input interrupt is controlled by the key input control regis-
ter and the port direction register. When enabling the key input
interrupt, set “1” to the key input control bit. A key input can be ac-
cepted from pins set as the input mode in ports P20–P27.
b7
b0
Key input control register
(KIC : address 001516
)
P20
P21
P22
P23
P24
P25
P26
P27
key input control bit
key input control bit
key input control bit
key input control bit
key input control bit
key input control bit
key input control bit
key input control bit
0 : Key input interrupt disabled
1 : Key input interrupt enabled
Fig. 21 Structure of key input control register
Rev.1.02 Jul 31, 2003 page 25 of 69
7560 Group (A version)
TIMERS
The 7560 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0”, an
underflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
Data bus
Real time port
control bit “1”
RTP
real time port
0 data for
Q D
P5
P5
2
3
/RTP
/RTP
0
Latch
“0”
P5
2
3
direction register
P52 latch
Real time port
control bit “1”
RTP1 data for
real time port
Q D
1
Real time port
control bit “0”
Latch
“0”
P5
direction register
Timer X mode register
write signal
P53 latch
“1”
f(XIN)/16
(f(XCIN)/16 when φ = XCIN/2)
Timer X stop
control bit
Timer X write
control bit
Timer X operat-
ing mode bits
“00”,“01”,“11”
CNTR0 active
edge switch bit
“0”
Timer X (low) latc
(high) latch (8)
Timer X
interrupt
request
er X high-order register (8)
P5
4
/CNTR
0
Timer X low-orde
“10”
“1”
Pulse width
measurement
mode
mode
CNTR0 active
edge switch bit
“0”
“1”
S
Q
P54 direction register
Pulse width HL continuously
measurement mode
P54 latch
Rising edge detection
Pulse output mo
f(
Period
measurement mode
Falling edge detection
hen φ = XCIN/2)
Timer Y stop
control bit
CNTR1 activ
edge switc
Timer Y (low) latch (8)
Timer Y (high) latch (8)
00”,“01”,“11”
Timer Y
interrupt
request
P55/CNTR1
Timer Y low-order register (8) Timer Y high-order register (8)
Timer Y
“10”
operating
mode bits
“1”
when φ = XCIN/2)
Timer 1
interrupt
request
Timer 2 write
control bit
Timer 1 count source
selection bit
Timer 2 count source
selection bit
Timer 2 latch (8)
“0”
“0”
Timer 1 latch (8)
Timer 2
interrupt
request
Timer 1 register (8)
Timer 2 register (8)
X
CIN
“1”
“1”
f(XIN)/16
(f(XCIN)/16 when φ = XCIN/2)
TOUT/φ
output
enable bit
T
OUT output
active edge
switch bit “0”
S
Q
P43/φ/TOUT
T
T
OUT/φ
“1”
output
selection bit
Q
P4
register
3 direction
Timer 3 latch (8)
“0”
Timer 3
interrupt
request
f(XIN)/16
(f(XCIN)/16
φ
Timer 3 register (8)
T
OUT/φ output
enable bit
when φ = XCIN/2)
“1”
Timer 3 count
source selection bit
P43 latch
Fig. 22 Timer block diagram
Rev.1.02 Jul 31, 2003 page 26 of 69
7560 Group (A version)
Timer X
✕Timer X Write Control
Timer X is a 16-bit timer and is equipped with the timer latch. The
division ratio of timer X is given by 1/(n+1), where n is the value in
the timer latch. Timer X is a down-counter. When the contents of
timer X reach “000016”, an underflow occurs at the next count
pulse and the contents of the timer latch are reloaded into the
timer and the count is continued. When the timer underflows, the
timer X interrupt request bit is set to “1”.
Which write control can be selected by the timer X write control bit
(bit 0) of the timer X mode register (address 002716), writing data
to both the latch and the timer at the same time or writing data
only to the latch. When the operation “writing data only to the
latch” is selected, the value is set to the timer latch by writing data
to the timer X register and the timer is updated at next underflow.
After reset, the operation “writing data to both the latch and the
timer at the same time” is selected, and the value is set to both
the latch and the timer at the same time by writing data to the
timer X register. The write operation iindependent of timer X
count operation, operating or stoppi
Timer X can be selected in one of four modes by the timer X mode
register and can be controlled the timer X write and the real time
port.
(1) Timer mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
When the value is written in latcalue is simultaneously
set to the timer X and the timif the writing in the high-
order register and the undmer X are performed at the
same timing. Unexpectay be set in the high-order timer
on this occasion.
(2) Pulse output mode
Each time the timer underflows, a signal output from the CNTR0
pin is inverted. Except for this, the operation in pulse output mode
is the same as in timer mode. When using a timer in this mode,
set the P54/CNTR0 pin to output mode (set “1” to bit 4 of port P5
direction register).
✕Real Time Por
While the real unction is valid, data for the real time port
are outpurts P52 and P53 each time the timer X
underflever, if the real time port control bit is changed
from after set of the real time port data, data are output
int of the timer X operation.) If the data for the real time
hanged while the real time port function is valid, the
ged data are output at the next underflow of timer X.
fore using this function, set the P52/RTP0, P53/RTP1 pins to
output mode (set “1” to bits 2, 3 of port P5 direction register).
(3) Event counter mode
The timer counts signals input through the CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the P54/
CNTR0 pin to input mode (set “0” to bit 4 of port P5 direction re
ister).
✕Note on CNTR0 interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
(4) Pulse width measurement mode
The count source is f(XIN)/16 (or f(XCIN)/16 in low-se). If
CNTR0 active edge switch bit is “0”, the timehile the
input signal of CNTR0 pin is at “H”. If it is mer counts
while the input signal of CNTR0 pin is at “sing a timer in
this mode, set the P54/CNTR0 pin to i(set “0” to bit 4 of
port P5 direction register).
b7
b0
Timer X mode register
(TXM : address 002716
)
Timer X write control bit
0 : Write value in latch and timer
1 : Write value in latch only
Real time port control bit
0 : Real time port function invalid
1 : Real time port function valid
✕Read and write to timer X er, low-order registers
When reading and writing er X high-order and low-order
registers, be sure to roth the timer X high- and low-or-
der registers.
RTP
RTP
0
data for real time port
data for real time port
1
Timer X operating mode bits
b5 b4
When reading the timer X high-order and low-order registers, read
the high-order register first. When writing to the timer X high-order
and low-order registers, write the low-order register first. The timer
X cannot perform the correct operation if the next operation is per-
formed.
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement mode
CNTR0 active edge switch bit
0 : Count at rising edge in event counter mode
Start from “H” output in pulse output mode
Measure “H” pulse width in pulse width measurement
mode
•Write operation to the high- or low-order register before reading
the timer X low-order register
Falling edge active for CNTR0 interrupt
1 : Count at falling edge in event counter mode
Start from “L” output in pulse output mode
Measure “L” pulse width in pulse width measurement
mode
•Read operation from the high- or low-order register before writing
to the timer X high-order register
Rising edge active for CNTR
Timer X stop control bit
0 : Count start
0 interrupt
1 : Count stop
Fig. 23 Structure of timer X mode register
Rev.1.02 Jul 31, 2003 page 27 of 69
7560 Group (A version)
Timer Y
Timer Y is a 16-bit timer and is equipped with the timer latch. The
division ratio of timer Y is given by 1/(n+1), where n is the value in
the timer latch. Timer Y is a down-counter. When the contents of
timer Y reach “000016”, an underflow occurs at the next count
pulse and the contents of the timer latch are reloaded into the
timer and the count is continued. When the timer underflows, the
timer Y interrupt request bit is set to “1”.
b7
b0
Timer Y mode register
(TYM : address 002816)
Not used (“0” at reading)
Timer Y operating mode bits
b5 b4
0
0
1
1
0 : Timer mode
1 : Period measurement mode
0 : Event counter mode
1 : Pulse width HL continuously
measurement mode
Timer Y can be selected in one of four modes by the timer Y mode
register.
CNTR1 active edge switch bit
0 : Count at rising edge in event counter mode
Measure thng edge to falling edge
period in asurement mode
Fallinfor CNTR1 interrupt
1 : Codge in event counter mode
ising edge period in period
nt mode
dge active for CNTR1 interrupt
op control bit
unt start
(1) Timer mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
(2) Period measurement mode
CNTR1 interrupt request is generated at rising or falling edge of
CNTR1 pin input signal. Simultaneously, the value in timer Y latch
is reloaded in timer Y and timer Y continues counting down.
Except for this, the operation in period measurement mode is the
same as in timer mode.
ount stop
Fig. 24 Strimer Y mode register
The timer value just before the reloading at rising or falling of
CNTR1 pin input signal is retained until the next valid edge is
input.
The rising or falling timing of CNTR1 pin input signal can be
discriminated by CNTR1 interrupt. When using a timer in this
mode, set the P55/CNTR1 pin to input mode (set “0” to bit 5 of port
P5 direction register).
(3) Event counter mode
The timer counts signals input through the CNTR1 pin
Except for this, the operation in event counter moame
as in timer mode. When using a timer in thset the
P55/CNTR1 pin to input mode (set “0” to bit 5 direction
register).
(4) Pulse width HL consly measure-
ment mode
CNTR1 interrupt request is at both rising and falling
edges of CNTR1 pin inpuxcept for this, the operation in
pulse width HL continusurement mode is the same as in
period measurement When using a timer in this mode, set
the P55/CNTR1 pin to iput mode (set “0” to bit 5 of port P5
direction register).
✕Note on CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the value of the CNTR1
active edge switch bit. However, in pulse width HL continuously
measurement mode, CNTR1 interrupt request is generated at both
rising and falling edges of CNTR1 pin input signal regardless of
the value of CNTR1 active edge switch bit.
Rev.1.02 Jul 31, 2003 page 28 of 69
7560 Group (A version)
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers and is equipped with
the timer latch. The count source for each timer can be selected
by the timer 123 mode register.
b7
b0
Timer 123 mode register
(T123M :address 002916
)
The division ratio of each timer is given by 1/(n+1), where n is the
value in the timer latch. All timers are down-counters. When the
contents of the timer reach “0016”, an underflow occurs at the next
count pulse and the contents of the timer latch are reloaded into
the timer and the count is continued. When the timer underflows,
the interrupt request bit corresponding to that timer is set to “1”.
When a value is written to the timer 1 register and the timer 3 reg-
ister, a value is simultaneously set as the timer latch and the timer.
When the timer 1 register, the timer 2 register, or the timer 3 regis-
ter is read, the count value of the timer can be read.
T
OUT output active edge switch bit
0 : Start at “H” output
1 : Start at “L” output
OUT/φ output enablel bit
0 : TOUT/φ output disabled
1 : TOUT/φ output enabled
T
Timer 2 write control bit
0 : Write data in latch and counter
1 : Write data in latch only
Timer 2 count ce selection bit
0 : Timer gnal
1 : f(XI
(n low-speed mode)
Timource selection bit
output signal
16
✕Timer 2 Write Control
Which write can be selected by the timer 2 write control bit (bit 2)
of the timer 123 mode register (address 002916), writing data to
both the latch and the timer at the same time or writing data only
to the latch. When the operation “writing data only to the latch” is
selected, the value is set to the timer 2 latch by writing data to the
timer 2 register and the timer 2 is updated at next underflow. After
reset, the operation “writing data to both the latch and the timer at
the same time” is selected, and the value is set to both the timer 2
latch and the timer 2 at the same time by writing data to the timer
2 register.
f(XCIN)/16 in low-speed mode)
1 count source selection bit
: f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
1 : f(XCIN
)
Not used (“0” at reading)
m clock φ is f(XCIN)/2 in the low-speed mode.
Structure of timer 123 mode register
If the value is written in latch only, a value is simultaneously set
the timer 2 and the timer 2 latch when the writing in the
order register and the underflow of timer 2 are perform
same timing.
✕Timer 2 Output Control
When the timer 2 (TOUT) output is enabled UT/φ output
enable bit and the TOUT/φ output selectioversion signal
from the TOUT pin is output each time derflows.
In this case, set the P43/φ/TOUT pin mode (set “1” to bit 3
of port P4 direction register).
✕Note on Timer mer 3
When the count sourimers 1 to 3 is changed, the timer
counting value may become arbitrary value because a thin pulse
is generated in count input of timer. If timer 1 output is selected as
the count source of timer 2 or timer 3, when timer 1 is written, the
counting value of timer 2 or timer 3 may become undefined value
because a thin pulse is generated in timer 1 output.
Therefore, set the value of timer in the order of timer 1, timer 2
and timer 3 after the count source selection of timer 1 to 3.
Rev.1.02 Jul 31, 2003 page 29 of 69
7560 Group (A version)
ceiver must use the same clock as an operation clock.
When an internal clock is selected as an operation clock, transmit
or receive is started by a write signal to the transmit buffer regis-
ter.
SERIAL I/O
Serial I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
When an external clock is selected as an operation clock, serial I/
O1 becomes the state where transmit or receive can be performed
by a write signal to the transmit buffer register. Transmit and re-
ceive are started by input of an external clock.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode is selected by setting the se-
rial I/O1 mode selection bit of the serial I/O1 control register to “1”.
For clock synchronous serial I/O mode, the transmitter and the re-
Data bus
Serial I/O1 control register
Add
Address 001816
Receive buffer register
Receive buffer full flag (R
Receive shift register
Receive uest
P44/RXD
Shift clock
Receive clock control circuit
P46/SCLK1
Serial I/O1 synchronous
clock selection bit
Frequency division ratio
BRG count source selection bit
1/4
X
IN
Baud rate generat
Address 001
P4
7
/SRDY1
lock control circuit
Falling-edge detector
F/F
S
Trans
egister
Transmit shift register shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request
P45/TXD
Transmit buffer empty flag (TBE)
Serial I/O1 status register
Address 001916
Address 001816
Data bus
Fig. 26 Block diagram of clock syserial I/O1
Transmit and receive shif
(1/2 to 1/2048 of the int
clock, or an external
(Note 1)
Se
X
D
D
D
0
0
D
1
1
D
2
D
D
3
3
D
D
4
4
D
5
5
D
6
6
D
7
7
D
D
D
D
D
D
2
Serial iput R
Receive enable signal SRDY1
Write signal to receive/transmit
buffer register (address 001816
)
(Note 4)
(Note 3)
RBF = “1”
TSC = “1”
TBE = “0”
(Note 3)
(Note 2)
TBE = “1”
TSC = “0”
Overrun error (OE)
detection
Notes
1 : After data transferring, the TxD pin keeps D
2 : If data is written to the transmit buffer register when TSC = “0”, the transmit clock is generated continuously and serial data can
be output continuously from the T D pin.
7 output value.
X
3 : Select the serial I/O1 transmit interrupt request factor between when the transmit buffer register has emptied (TBE = “1”) or
after the transmit shift operation has ended (TSC = “1”), by setting the transmit interrupt source selection bit (TIC) of the serial
I/O1 control register.
4 : The serial I/O1 receive interrupt request occurs when the receive buffer full flag (RBF) becomes “1”.
Fig. 27 Operation of clock synchronous serial I/O1 function
Rev.1.02 Jul 31, 2003 page 30 of 69
7560 Group (A version)
ter, but the two buffers have the same address (001816) in
memory. Since the shift register cannot be written to or read from
directly, transmit data is written to the transmit buffer, and receive
data is read from the receive buffer.
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) is selected by setting
the serial I/O1 mode selection bit of the serial I/O1 control register
to “0”.
The transmit buffer can also hold the next data to be transmitted
during transmitting, and the receive buffer register can hold re-
ceived one-byte data while the next one-byte data is being re-
ceived.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
Data bus
Address 001816
Address 001A16
Serial I/O1 control register
OE
Receive buffer full flag (RBF)
Receive interrupt request
Receive buffer register
Character length selection bit
7 bits
P44/RXD
STdetector
Receive shift register
1/16
8 bits
UAgister
SP detector
PE FE
ess 001B16
Clock control circuit
Serial I/O1 synchronization clock selection bit
P46/SCLK1
XIN
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
Baud rate generator
Address 001C16
ST/SP/PA generator
1/1
Transmit shift register shift completion flag (TSC)
Transmit interrupt source selection bit
P45/TXD
Transmit sh
Transmit interrupt request
Character length selection bit
Transmit buffer empty flag (TBE)
Transter
dress 001816
Address 001916
Serial I/O1 status register
Fig. 28 Block diagram of UART serial I/O
Transmit or receive clock
Transmit buffer register write
TBE = “0”
TSC = “0”
TBE = “1”
TBE = “0”
D1
TBE = “1”
ST
TSC = “1”✕
SP
ST
Serial output TxD
D0
SP
D0
D1
1 start bit
✕ Generated at 2nd bit in 2-stop-bit mode
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer register read signal
(Notes 1, 2)
(Notes 1, 2)
RBF = “1”
RBF = “0”
RBF = “1”
ST
D0
D1
SP
ST
D0
D1
Serial input RxD
SP
1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit for reception).
2 : The serial I/O1 receive interrupt request occurs when the receive buffer full flag (RBF) becomes “1”.
Notes
3 : Select the serial I/O1 transmit interrupt request occurrence factor between when the transmit buffer register has emptied (TBE = “1”) or
after the transmit shift operation has ended (TSC = “1”), by setting the transmit interrupt source selection bit (TIC) of the serial
I/O1 control register.
Fig. 29 Operation of UART serial I/O1 function
Rev.1.02 Jul 31, 2003 page 31 of 69
7560 Group (A version)
[Transmit Buffer/Receive Buffer Register (TB/
RB)] 001816
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer register is write-
only and the receive buffer register is read-only. If a character bit
length is 7 bits, the MSB of data stored in the receive buffer regis-
ter is “0”.
[Serial I/O1 Status Register (SIO1STS)]
001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O1
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is set to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set to “1”. A write signal to
the serial I/O1 status register sets all the error flags (OE, PE, FE,
and SE) (bit 3 to bit 6, respectively) to “0”. Writing “0” to the serial
I/O1 enable bit (SIOE) also sets all the status flags to “0”, includ-
ing the error flags.
All bits of the serial I/O1 status register are set to “0” at reset, but
if the transmit enable bit of the serial I/O1 control register has
been set to “1”, the transmit shift register shift completion flag and
the transmit buffer empty flag become “1”.
[Serial I/O1 Control Register (SIO1C
001A16
The serial I/O1 control register contains eight conr the
serial I/O1 function.
[UART Control Register (UAR)] 001B16
The UART control register consists ohich set the data
format of an data transmit and reche bit which sets the
output structure of the P45/TXD
[Baud Rate GenerRG)] 001C16
The baud rate gener8-bit counter equipped with a
reload register. Set thn value of the BRG count source to
the baud rate generator.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate
generator.
✕Notes on serial I/O
When setting the transmit enable bit to “1”, the serial I/O1 transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronous with the transmission en-
abled, take the following sequence.
✕Set the serial I/O1 transmit interrupt enable bit to “0” (disabled).
✕Set the transmit enable bit to “1”.
✕Set the serial I/O1 transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
✕Set the serial I/O1 transmit interrupt enable bit to “1” (enabled).
Rev.1.02 Jul 31, 2003 page 32 of 69
7560 Group (A version)
b7
b0
b7
b0
Serial I/O1 status register
(SIO1STS : address 001916
Serial I/O1 control register
(SIO1CON : address 001A16
)
)
BRG count source selection bit (CSS)
0: f(XIN
1: f(XIN)/4
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
)
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous serial
I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronous serial I/O is
selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
External clock input divided by 16 when UART is selected.
S
0: P4
1: P4
RDY1 output enable bit (SRDY)
Overrun error flag (OE)
0: No error
1: Overrun error
7
pin operates as ordina
pin operates as SRD
7
Transmit interrupt soubit (TIC)
0: Interrupt when trhas emptied
1: Interrupt whet operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit e
0: Trans
1: Tra
Framing error flag (FE)
0: No error
1: Framing error
Re bit (RE)
disabled
e enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE) =0
1: (OE) U (PE) U (FE) =1
al I/O1 mode selection bit (SIOM)
: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Not used (“1” at reading)
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
b7
b0
UART control register
(UARTCON : address 001B16
(pins P4
1: Serial I/O1 enabled
(pins P4 –P4 operate as serial I/O pins)
4–P47 operate as ordinary I/O pins)
)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
4
7
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selecS)
0: 1 stop bit
1: 2 stop bits
P45/TXD put disable bit (POFF)
0: CMOoutput mode)
1: Nn-drain output (in output mode)
No” at reading)
Fig. 30 Structure of serial I/O1 control registers
Rev.1.02 Jul 31, 2003 page 33 of 69
7560 Group (A version)
b7
b0
Serial I/O2
Serial I/O2 control register
(SIO2CON : address 001D16
Serial I/O2 can be used only for clock synchronous serial I/O.
For serial I/O2, the transmitter and the receiver must use the
same clock as a synchronous clock. When an internal clock is se-
lected as a synchronous clock, the serial I/O2 is initialized and,
transmit and receive is started by a write signal to the serial I/O2
register.
)
Internal synchronous clock select bits
b2 b1 b0
0 0 0: f(XIN)/8
0 0 1: f(XIN)/16
0 1 0: f(XIN)/32
0 1 1: f(XIN)/64
1 0 0:
1 0 1:
Do not select
When an external clock is selected as an synchronous clock, the
serial I/O2 counter is initialized by a write signal to the serial I/O2
register, serial I/O2 becomes the state where transmission or re-
ception can be performed. Write to the serial I/O2 register while
SCLK21 is “H” state when an external clock is selected as an syn-
chronous clock.
1 1 0: f(XIN)/128
1 1 1: f(XIN)/256
Serial I/O2 port selection bit
0: I/O port
1: SOUT2,SCLK21/2 signal output
Either P62/SCLK21 or P63/SCLK22 pin can be selected as an output
pin of the synchronous clock. In this case, the pin that is not se-
lected as an output pin of the synchronous clock functions as a I/
O port.
P61/SOUT2 Putput disable bit
0: CMOS utput mode)
1: N-ch-drain output
(in de)
ection selection bit
st
first
[Serial I/O2 Control Register (SIO2CON)] 001D16
The serial I/O2 control register contains eight control bits for the
serial I/O2 functions. After setting to this register, write data to the
serial I/O2 register and start transmit and receive.
erial I/O2 synchronous clock selection bit
0: External clock
1: Internal clock
Synchronous clock output pin selection bit
0: SCLK21
1: SCLK22
31 Structure of serial I/O2 control register
Internal synchronous
clock select bits
1/8
1/16
Data bus
1/32
XIN
1/64
1/128
1/256
P6
3
Serial I/O2 synchronous
clock selection bit
(N
“1”
P63
/SCLK22
Synchronous circuit
“0”
External clock
P62 latch
“0”
P6
2
1
/SCLK21
/SOUT2
Serial I/O2
interrupt request
Serial I/O2 counter (3)
(Note) “1”
P6
1
latch
“0”
P6
“1”
Serial I/O2 port selection bit
P60/SIN2
Serial I/O 2 register (8)
Note: It is selected by the serial I/O2 synchronous clock selection bit, the
synchronous clock output pin selection bit, and the serial I/O2 port
selection bit.
Fig. 32 Block diagram of serial I/O2 function
Rev.1.02 Jul 31, 2003 page 34 of 69
7560 Group (A version)
When the external clock is selected as a synchronous clock, if a
synchronous clock is counted 8 times, the serial I/O2 interrupt re-
quest bit is set to “1”, and the SOUT2 pin holds the output level of
D7. However, if a synchronous clock continues being input, the
shift of the serial I/O2 register is continued and transmission data
continues being output from the SOUT2 pin.
✕Serial I/O2 Operating
The serial I/O2 counter is initialized to “7” by writing to the serial
I/O2 register.
After writing, whenever a synchronous clock changes from “H” to
“L”, data is output from the SOUT2 pin. Moreover, whenever a syn-
chronous clock changes from “L” to “H”, data is taken in from the
SIN2 pin, and 1 bit shift of the serial I/O2 register is carried out si-
multaneously.
When the internal clock is selected as a synchronous clock, it is
as follows if a synchronous clock is counted 8 times.
•Serial I/O2 counter = “0”
•Synchronous clock stops in “H” state
•Serial I/O2 interrupt request bit = “1”
The SOUT2 pin is in a high impedance state after transfer is com-
pleted.
Synchronous clock
(Note 1)
Serial I/O2 register
write signal
(Notes 2, 3)
Serial I/O2 output
SOUT2
D2
D
0
D
1
D
4
D
5
D
6
D7
Serial I/O2 input SIN2
Serial I/O2 interrupt request bit = “1”
Notes 1: When the internal clock is selsynchronous clock, the divide ratio can be selected by setting bits 0 to 2 of the
serial I/O2 control register.
2: When the internal clock ithe synchronous clock, the SOUT2 pin goes to high impedance after transfer
completion.
3: When the external cted as the synchronous clock, the SOUT2 pin keeps D
completion. Howhronous clocks input are carried on, the transmit data will be output continuously from the
OUT2 pin becaserial I/O2 shift register is continued as long as synchronous clocks are input.
7 output level after transfer
S
Fig. 33 Timing of serial I/n
Rev.1.02 Jul 31, 2003 page 35 of 69
7560 Group (A version)
PULSE WIDTH MODULATION (PWM)
The 7560 group has a PWM function with an 8-bit resolution,
using f(XIN) or f(XIN)/2 as a count source.
PWM Operation
When either bit 1 (PWM0 function enable bit) or bit 2 (PWM1 func-
tion enable bit) of the PWM control register or both bits are
enabled, operation starts from initializing status, and pulses are
output starting at “H”. When one PWM output is enabled and that
the other PWM output is enabled, PWM output which is enabled to
output later starts pulse output from halfway of PWM period (see
Figure 37).
Data Setting
The PWM output pins are shared with ports P50 and P51. Set the
PWM period by the PWM prescaler, and set the period during
which the output pulse is an “H” by the PWM register.
If PWM count source is f(XIN) and the value in the PWM prescaler
is n and the value in the PWM register is m (where n = 0 to 255
and m = 0 to 255) :
When the PWM register or PWM prescaler is updated during
PWM output, the pulses will change in the cycle after the one in
which the change was made.
PWM period = 255 ✕ (n+1)/f(XIN)
= 31.875 ✕ (n+1) µs (when f(XIN) = 8 MHz)
Output pulse “H” period = PWM period ✕ m/255
= 0.125 ✕ (n+1) ✕ m µs
31.875 ✕ m ✕
25
(when f(XIN) = 8 MHz)
PWM output
T = [31.875 ✕ (n+1)] µs
nts of PWM register
tents of PWM prescaler
WM cycle (when f(XIN) = 8 MHz)
Timing of PWM cycle
Data bus
PWM
register pre-latch
PW
presca
PWM
enable bit
1 function
Transfer control circuit
Port P5
1
lacth
PWM
prescaler latch
PWM
register latch
P5
1
0
/PWM
/PWM
1
0
Cnt source
selection bit
“0”
PWM prescaler
PWM circuit
X
IN
P5
“1”
1/2
Port P5
lacth
0
0
PWM
function
enable bit
Fig. 35 Block diagram of PWM function
Rev.1.02 Jul 31, 2003 page 36 of 69
7560 Group (A version)
b0
b7
PWM control register
(PWMCON : address 002B16)
Count source selection bit
0: f(XIN)
1: f(XIN)/2
PWM0 function enable bit
0: PWM0 disabled
1: PWM0 enabled
PWM1 function enable bit
0: PWM1 disabled
1: PWM1 enabled
Not used (“0” at reading)
Fig. 36 Structure of PWM control register
C
T2
B
T
=
C
A
B
PWM
(internal)
stop
Port
stop
T2
T
Port
PWM
PWM
0
1
output
output
Port
Port
PWM register
write signal
(Changes from “A” to “B” during “H” period)
PWM prescal
write signal
(Changes from “T” to “T2” during PWM period)
PWM
0 function
enable bit
PWM
1 function
enable bit
When the contents of the PWM register or PWM prescaler have changed, the PWM
output will change from the next period after the change.
Fig. 37 PWM output timing when PWM register or PWM prescaler is changed
Rev.1.02 Jul 31, 2003 page 37 of 69
7560 Group (A version)
A-D CONVERTER
[A-D Conversion Low-Order Register (ADL)]
001416
[A-D Conversion High-Order Register (ADH)]
003516
The A-D conversion registers are read-only registers that store the
result of an A-D conversion . When reading this register during an
A-D conversion, the previous conversion result is read.
The high-order 8 bits of a conversion result is stored in the A-D
conversion high-order register (address 003516), and the low-or-
der 2 bits of the same result are stored in bit 7 and bit 6 of the A-D
conversion low-order register (address 001416).
Bit 0 of the A-D conversion low-order register is the conversion
mode selection bit. When this bit is set to “0”, that becomes the
10-bit A-D mode. When this bit is set to “1”, that becomes the 8-bit
A-D mode.
Comparator and Control Circuit
The comparator and control circuit compare an analog input volt-
age with the comparison voltage and store the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
converter interrupt request bit to “1”.
Note that because the comparator consists of a capacitor
coupling, set f(XIN) to 500 kHz or more during an A-D conversion.
Use the clock divided from the main clock f(XIN) as the system clock
φ.
b7
b0
A-D co
(ADC03416
)
pin selection bits
0
1
1
1
1
1
1
0
0
1
1
: P6
1 : P6
0 : P6
1 : P6
0 : P6
1 : P6
0 : P6
1 : P6
0
1
2
3
4
5
6
7
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
[A-D Control Register (ADCON)] 003416
The A-D control register controls the A-D conversion process. Bits
0 to 2 of this register select specific analog input pins. Bit 3 indi-
cates the completion of an A-D conversion. The value of this bit re-
mains at “0” during an A-D conversion, then it is set to “1” when
the A-D conversion is completed. Writing “0” to this bit starts the
A-D conversion.
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
V
REF input switch bit
0 : AUTO
1 : ON
Bit 4 is the VREF input switch bit which controls connection of the
resistor ladder and the reference voltage input pin (VREF). The
resistor ladder is always connected to VREF when bit 4 is set
“1”. When bit 4 is set to “0”, the resistor ladder is cut off from
except for A-D conversion performed. When bit 5, which i
external trigger valid bit, is set to “1”, A-D conversion sty
a falling edge of an ADT input. When using an A-D eger,
set the P57/ADT pin to input mode (set “0” to bit 5 direc-
tion register).
AD external trigger valid bit
0 : A-D external trigger invalid
1 : A-D external trigger valid
Interrupt source selection bit
0 : Interrupt request at A-D
conversion completed
1 : Interrupt request at ADT
input falling
Not used (“0” at reading)
b7
b0
A-D conversion low-order register
(ADL : address 001416
)
Conversion mode selection bit
0 : 10-bit A-D mode
1 : 8-bit A-D mode
Comparison Voltage Gener
Not used (“0” at reading)
The comparison voltage generatohe voltage between
AVSS and VREF by 256 (when 8ode) or 1024 (when 10-
bit A-D mode), and outputs tvoltages.
•For 10-bit A-D mode
A-D conversion result
•For 8-bit A-D mode
Not used (undefined at reading)
Channel Selecto
The channel selector se of the input ports P67/AN7–P60/AN0.
Fig. 38 Structure of A-D converter-related registers
Rev.1.02 Jul 31, 2003 page 38 of 69
7560 Group (A version)
•10-bit reading
(Read address 003516, then 001416)
b0
b7
A-D conversion high-order register
(ADH: Address 003516)
(high-order)
(low-order)
b9 b8 b7 b6 b5 b4 b3 b2
b0
b7
A-D conversion low-order register
(ADL: Address 001416)
b1 b0
Conversion mode section bit
0 : 10-bit A-D mod
1 : 8-bit A-D mo
Note : Bits 0 to 5 of address 001416 become “0” at reading.
•8-bit reading
(Read only address 003516)
b7
b0
A-D conversion high-order register
(ADH: Address 003516)
b7 b6 b5 b4 b3 b2 b1 b0
Fig. 39 Read of A-D conversion register
Data
bus
b
0
A-D control regist
/ADT/DA
P57
2
3
ADT/A-D
interrupt
request
A-D control
circuit
P6
0
/SIN2/A
1
2
3
P61/SOUT2/AN
A-D conversion
high-order register
A-D conversion
low-order register
P6
2
/SCLK21/AN
/SCLK22/AN
Comparato
r
P63
(Address 003516
)
(Address 001416
)
8
P6
4
/
P64
5
/
AN
Resistor
ladder
P65
AN
6
/
AN
P66
7
/
AN7
AVSS
VRE
Fig. 40 A-D converter block diagram
Rev.1.02 Jul 31, 2003 page 39 of 69
7560 Group (A version)
D-A Converter
The 7560 group has a D-A converter with 8-bit resolution and 2
b7
b0
D-A control register
(DACON : address 003616
channels (DA1, DA2).
0 0 0 0 0 0
)
The D-A converter is started by setting the value in the D-A con-
version register. When the DA1 output enable bit or the DA2 output
enable bit is set to “1”, the result of D-A conversion is output from
the corresponding DA pin. When using the D-A converter, set the
P56/DA1 pin and the P57/DA2 pin to input mode (set “0” to bits 6,
7 of port P5 direction register) and the pull-up resistor should be in
the OFF state (set “0” to bit 3 of PULL register B) previously.
The output analog voltage V is determined by the value n (base
10) in the D-A conversion register as follows:
DA1 output enable bit
0 : Disabled
1 : Enabled
DA2 output enable bit
0 : Disabled
1 : Enabled
Not useat reading)
(Writese bits at writing.)
V=VREF ✕ n/256 (n=0 to 255)
Where VREF is the reference voltage.
Fig. 41 Structure of D-A ister
At reset, the D-A conversion registers are set to “0016”, the DA1
output enable bit and the DA2 output enable bit are set to “0”, and
the P56/DA1 pin and the P57/DA2 pin goes to high impedance
state. The DA converter is not buffered, so connect an external
buffer when driving a low-impedance load.
Data bus
✕ Note on applied voltage to VREF pin
-A1 conversion register (8)
(DA1: address 003216
)
When these pins are used as D-A conversion output pins, the Vcc
level is recommended for the applied voltage to VREF pin.
When the voltage below Vcc level is applied, the D-A conversion
accuracy may be worse.
DA
1
output enable bit
P5 /DA
R-2R resistor ladder
6
1
D-A2 conversion register (8)
(DA2: address 003316
)
DA
2
output enable bit
P5 /DA
R-2R resistor ladder
7
2
Fig. 42 Block diagram of D-A converter
Rev.1.02 Jul 31, 2003 page 40 of 69
7560 Group (A version)
DAi output enable bit
“0”
R
2R
R
R
R
R
R
R
DAi
“1”
2R
2R
2R
2R
2R
2R
2R
2R
LSB
MSB
“0”
D-Ai conversion register
“1”
AVSS
VREF
Fig. 43 Equivalent connection circuit of D-A converter
Rev.1.02 Jul 31, 2003 page 41 of 69
7560 Group (A version)
enable bit is set to “1” (LCD ON) after data is set in the LCD mode
register, the segment output enable register and the LCD display
RAM, the LCD drive control circuit starts reading the display data
automatically, performs the bias control and the duty ratio control,
and displays the data on the LCD panel.
LCD DRIVE CONTROL CIRCUIT
The 7560 group has the Liquid Crystal Display (LCD) drive control
circuit consisting of the following.
LCD display RAM
•
Segment output enable register
•
LCD mode register
•
Table 9 Maximum number of display pixels at each duty ratio
Voltage multiplier
•
Selector
•
Duty ratio
2
Maximum number of display pixel
80 dots
Timing controller
•
Common driver
•
or 8 segment LCD 10 digits
120 dots
Segment driver
•
3
4
Bias control circuit
•
or 8 segment LCD 1its
160 dots
A maximum of 40 segment output pins and 4 common output pins
can be used.
or 8 segment its
Up to 160 pixels can be controlled for LCD display. When the LCD
b7
b0
Segment output enable regis
0
(SEG : address 003816
)
Segment output en
0 : Output port
1 : Segment 8–SEG23
Segment ouit 1
0 : Out, P37
1 : Sut SEG24,SEG25
Segnable bit 2
P00–P05
nt output SEG26–SEG31
output enable bit 3
O ports P06,P07
: Segment output SEG32,SEG33
egment output enable bit 4
0 : I/O port P1
0
1 : Segment output SEG34
Segment output enable bit 5
0 : I/O ports P11–P15
1 : Segment output SEG35–SEG39
LCD output enable bit
0 : Disabled
1 : Enabled
Not used (“0” at reading)
(Write “0” to this bit at writing.)
b0
LCD mode register
(LM : address 003916
)
Duty ratio selection bits
b1b0
0 0 : Not used
0 1 : 2 duty (use COM
1 0 : 3 duty (use COM
1 1 : 4 duty (use COM
Bias control bit
0 : 1/3 bias
0
, COM
–COM
–COM
1
2
3
)
)
)
0
0
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Voltage multiplier control bit
0 : Voltage multiplier disable
1 : Voltage multiplier enable
LCD circuit divider division ratio selection bits
b6b5
0 0 : Clock input
0 1 : 2 division of Clock input
1 0 : 4 division of Clock input
1 1 : 8 division of Clock input
LCDCK count source selection bit (Note)
0 : f(XCIN)/32
1 : f(XIN)/8192 (f(XCIN)/8192 in low-speed mode)
Note : LCDCK is a clock for a LCD timing controller.
Fig. 44 Structure of segment output enable register and LCD mode register
Rev.1.02 Jul 31, 2003 page 42 of 69
Data bus
LCD enable bit
Duty ratio selec
Address 005316
Address 004116
Address 004016
LCD display RAM
L
n
on bits
LCDCK count source
selection bit
“0”
2
f(XCIN)/ 32
LCD
divider
f(XIN)/8192
(f(XCIN)/8192 in low-
speed mode)
Voltage multiplier
control bit
Bias control bit
“1”
Selector Selector Selector
Selector Selector
Selector
Timing controller
LCDCK
Level Level Level Level
Level
shift
Level
shift
Level
shift
Level
shift
Level
shift
Level
shift
as control
Shift
Shift
Shift
Shift
VCC
LCD output
enable bit
Common Common Common Common
Segment Segment Segment Segment
driver driver driver driver
Sent
river
driver
driver
driver
driver
SEG3
P14/SEG38 P15/SEG39
VSS VL1 VL2 VL3 C1 C2
SEG0
SEG1
SEG2
PG18
COM0
COM3
COM1 COM2
7560 Group (A version)
Voltage Multiplier (3 Times)
Bias Control and Applied Voltage to LCD
Power Input Pins
The voltage multiplier performs threefold boosting. This circuit in-
puts a reference voltage for boosting from LCD power input pin
VL1.
To the LCD power input pins (VL1–VL3), apply the voltage shown
in Table 10 according to the bias value.
Set each bit of the segment output enable register and the LCD
mode register in the following order for operating the voltage mul-
tiplier.
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
1. Set the segment output enable bits (bits 0 to 5) of the seg-
ment output enable register to “0” or “1”.
Table 10 Bias control and applied voltage to VL1–VL3
Bias value
Voltage value
2. Set the duty ratio selection bits (bits 0 and 1), the bias con-
trol bit (bit 2), the LCD circuit divider division ratio selection
bits (bits 5 and 6), and the LCDCK count source selection
bit (bit 7) of the LCD mode register to “0” or “1”.
3. Set the LCD output enable bit (bit 6) of the segment output
enable register to “1” (enabled). Apply the limit voltage or
less to the VL1 pin.
VL3=VLCD
1/3 bias
VL2=2/3 VLCD
VL1=1/3 VLCD
VL3=VLCD
1/2 bias
VL2=VL1=1/2 V
Note : VLCD is the maximof supplied voltage for the
LCD panel.
4. Set the voltage multiplier control bit (bit 4) of the LCD mode
register to “1” (voltage multiplier enabled). However, be sure
to select 1/3 bias for bias control.
When voltage is input to the VL1 pin during operating the voltage
multiplier, voltage that is twice as large as VL1 occurs at the VL2
pin, and voltage that is three times as large as VL1 occurs at the
VL3 pin.
✕Notes on Voltage Multiplier
When using the voltage multiplier, apply the limit voltage or less to
the VL1 pin, then set the voltage multiplier control bit to “1” (e
abled).
When not using the voltage multiplier, set the LCD outpu
bit to “1”, then apply proper voltage to the LCD powes
(VL1–VL3). When the LCD output enable bit is set to led)
(during reset is included), the VL3 pin is connecinside
of this microcomputer. When the voltage exceis applied
to VL3, apply VL3 voltage after setting the t enable bit to
“1” (enabled).
V
CC
VCC
Contrast control
Contrast control
V
V
L3
L2
V
L3
L2
V
L3
L2
R4
R1
V
V
Open
Open
Open
Open
C
2
1
C
2
1
C
2
1
R2
C
C
C
V
L1
V
L1
V
L1
1/3 bias
when using the voltage
multiplier
1/3 bias
when not using the voltage
multiplier
1/2 bias
R5
R3
R1 = R2 = R3
R4 = R5
Fig. 46 Example of circuit at each bias
Rev.1.02 Jul 31, 2003 page 44 of 69
7560 Group (A version)
Common Pin and Duty Ratio Control
The common pins (COM0–COM3) to be used are determined by
duty ratio.
LCD Display RAM
Addresses 004016 to 005316 are the designated RAM for the LCD
display. When “1” are written to these addresses, the correspond-
ing segments of the LCD display panel are turned on.
Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the
LCD mode register).
After reset, the VCC (VL3) voltage is output from the common pins.
LCD Drive Timing
The frequency of internal signal LCDCK decided LCD drive timing
and the frame frequency can be determined with the following
equation:
Table 11 Duty ratio control and common pins used
Duty
ratio
Duty ratio selection bits
Common pins used
Bit 1
0
Bit 0
1
2
COM0, COM1 (Note 1)
COM0–COM2 (Note 2)
COM0–COM3
(frequency of count souDCK)
f(LCDCK)=
3
4
1
1
0
1
(divider division rD)
f(LCDCK
Frame frequency=
duty r
Notes 1: COM2 and COM3 are open.
2: COM3 is open.
Segment Signal Output Pins
Segment signal output pins are classified into the segment-only
pins (SEG0–SEG17), the segment or output port pins (SEG18–
SEG25), and the segment or I/O port pins (SEG26–SEG39).
Segment signals are output according to the bit data of the LCD
RAM corresponding to the duty ratio. After reset, a VCC (=VL3)
voltage is output to the segment-only pins and the segment/out-
put port pins are the high impedance condition and pulled up to
VCC (=VL3) voltage.
Also, the segment/I/O port pins(SEG26–SEG39) are set to in
mode as I/O ports, and VCC (=VL3) is applied to them by
resistor.
6
5
4
3
2
1
0
A
COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
SEG1
SEG3
SEG0
SEG2
16
04116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
SEG5
SEG4
SEG7
SEG6
SEG9
SEG8
SEG11
SEG13
SEG15
SEG17
SEG19
SEG21
SEG23
SEG25
SEG27
SEG29
SEG31
SEG33
SEG35
SEG37
SEG39
SEG10
SEG12
SEG14
SEG16
SEG18
SEG20
SEG22
SEG24
SEG26
SEG28
SEG30
SEG32
SEG34
SEG36
SEG38
Fig. 47 LCD display RAM map
Rev.1.02 Jul 31, 2003 page 45 of 69
7560 Group (A version)
Internal signal
LCDCK timing
1/4 duty
Voltage level
V
V
V
L3
L2=VL1
SS
COM
COM
COM
COM
0
1
2
3
V
L3
SEG
0
VSS
OFF
ON
OFF
ON
COM
3
COM3
COM
2
COM
1
COM
0
COM
1
COM0
1/3 duty
V
V
V
L3
L2=VL1
SS
COM
COM
COM
0
1
2
V
L3
SEG
0
VSS
OFF
ON
OFF
ON
OFF
COM
0
0
COM
2
COM
1
COM
2
COM
1
COM
0
COM2
1/2 duty
V
V
V
L3
L2=VL1
SS
COM
COM
0
1
V
L3
SEG
0
VSS
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM
0
COM
1
COM
0
COM
1
COM
1
COM
0
COM
1
COM0
Fig. 48 LCD drive waveform (1/2 bias)
Rev.1.02 Jul 31, 2003 page 46 of 69
7560 Group (A version)
Internal signal
LCDCK timing
1/4 duty
Voltage level
VL3
V
VL2
VSL1S
COM
0
COM
COM
COM
1
2
3
VL3
SEG
0
VSS
OFF
ON
OFF
ON
COM
3
COM
COM
2
COM
1
COM
0
2
COM
1
COM0
1/3 duty
VL3
VL2
VSL1S
V
COM
COM
COM
0
1
2
VL3
SEG
0
VSS
OFF
ON
OFF
ON
OFF
OM
0
COM
2
COM
1
COM
0
COM2
COM
2
COM
1
COM0
1/2 duty
VL3
VL2
VSL1S
V
COM
COM
0
1
VL3
SEG
0
VSS
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM
1
COM
0
COM
1
COM
0
COM
1
COM0
COM
1
COM0
Fig. 49 LCD drive waveform (1/3 bias)
Rev.1.02 Jul 31, 2003 page 47 of 69
7560 Group (A version)
✕value of high-order 6-bit counter
✕value of STP instruction disable bit
✕value of count source selection bit.
Watchdog Timer
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software runaway).
When the STP instruction disable bit is “0”, the STP instruction is
enabled. The STP instruction is disabled when this bit is set to “1”.
If the STP instruction which is disabled is executed, it is processed
as an undefined instruction, so that a reset occurs internally.
This bit can be set to “1” but cannot be set to “0” by program. This
bit is “0” after reset.
The watchdog timer consists of an 8-bit watchdog timer L and a 6-
bit watchdog timer H. At reset or writing to the watchdog timer
control register (address 003716), the watchdog timer is set to
“3FFF16”. When any data is not written to the watchdog timer con-
trol register (address 003716) after reset, the watchdog timer is
stopped. The watchdog timer starts to count down from “3FFF16”
by writing to the watchdog timer control register and an internal re-
set occurs at an underflow. Accordingly, when using the watchdog
timer function, write the watchdog timer control register before an
underflow. The watchdog timer does not function when writing to
the watchdog timer control register has not been done after reset.
When not using the watchdog timer, do not write to it. When the
watchdog timer control register is read, the following values are
read:
When the watchdog timer H count source selection bit is “0”, the
detection time is set to 8.19 s at f(XCIN) = 32 kHz and 32.768 ms
at f(XIN) = 8 MHz.
When the watchdog timer H counelection bit is “0”, the
detection time is set to 32 ms = 32 kHz and 128 µs at
f(XIN) = 8 MHz. There is ne in the detection time be-
tween the middle-speed the high-speed mode.
“FF16” is set when
watchdog timer is
ata bus
X
CIN
Watchdog timer H co
source selection bi
“0”
written to.
Watchdog timer
L (8)
“1”
“0”
Internal
g timer
H (6)
system clock
selection bit
(Note)
1/16
“1”
“3F16” is set when
watchdog timer is
written to.
X
IN
Undefined instruction
Reset
STP instruction disable bit
STP instruction
Internal reset
Reset circuit
RESET
Reset release time wait
Note: This is the bit 7 of CPU mode s used to switch the middle-/high-speed mode and low-speed mode.
Fig. 50 Block diagram of watchdog timer
b7
b0
Watchdog timer register
(WDTCON: address 003716)
Watchdog timer H (for read-out of high-order 6 bit)
“3FFF16” is set to the watchdog timer by writing values to this address.
STP instruction disable bit
0 : STP instruction enabled
1 : STP instruction disabled
Watchdog timer H count source selecion bit
0 : Watchdog timer L underflow
1 : f(XIN)/16 or f(XCIN)/16
Fig. 51 Structure of watchdog timer control register
f(XIN)
Approx. 1 ms (f(XIN) = 8 MHZ)
Internal
reset signal
Watchdog timer
detection
Fig. 52 Timing of reset output
Rev.1.02 Jul 31, 2003 page 48 of 69
7560 Group (A version)
TOUT/φ OUTPUT FUNCTION
The system clock φ or timer 2 divided by 2 (TOUT output) can be
output from port P43 by setting the TOUT/φ output enable bit of the
timer 123 mode register and the TOUT/φ output control register.
Set the P43/φ/TOUT pin to output mode (set “1” to bit 3 of port P4
direction register) when outputting TOUT/φ.
b7
b0
T
OUT/φ output control register
(CKOUT : address 002A16
)
T
OUT/φ output control bit
0 : System clock φ output
1 : TOUT output
Not used (“0” at reading)
b7
b0
Timer 123 mode register
(T123M : address 002916
)
T
OUT output active bit
0 : Start at “H
1 : Start at
T
OUT/φ outit
0 : Tdisabled
1 : ut enabled
Tiontrol bit
ata in latch and timer
e data in latch only
count source selection bit
Timer 1 output
1 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
Timer 3 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
Timer 1 count source selection bit
0 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
1 : f(XCIN
)
Not used (“0” at reading)
Fig. 53 Structure of TOUTelated registers
Rev.1.02 Jul 31, 2003 page 49 of 69
7560 Group (A version)
and address FFFC16 (low-order byte). Make sure that the reset in-
put voltage is less than 0.2 VCC(min.) for the power source voltage
of VCC(min.).
RESET CIRCUIT
When the power source voltage is within limits, and main clock
XIN-XOUT is stable, or a stabilized clock is input to the XIN pin, if
the RESET pin is held at an “L” level for 2 µs or more, the micro-
computer is in an internal reset state. Then the RESET pin is
returned to an “H” level, reset is released after approximate 8200
cycles of f(XIN), the program in address FFFD16 (high-order byte)
*VCC(min.) = Minimum value of power supply voltage limits
applied to VCC pin
(Note)
V
CC
0V
0V
0V
RESET
VCC
VCC
RESET
RESET
Power source
voltage detection
circuit
X
IN
Oscillation stabilized
e: Reset release voltage Vcc = Vcc (min.)
Fig. 54 Example of reset circuit
X
IN
System
clock φ
RESET
Internal reset
Reset address from
vector table
Address
Data
Undefined Undefined Undefined Undefined
ADH,ADL
FFFC
FFFD
AD
H
AD
L
SYNC
X
IN : Approx. 8200 cycles
Note : The frequency of system clock φ is f(XIN) divided by 8.
Fig. 55 Reset Sequence
Rev.1.02 Jul 31, 2003 page 50 of 69
7560 Group (A version)
Address Register contents
(1)
(2)
000116
0016
Port P0 direction register
Port P1 direction register
000316
0016
(3) Port P2 direction register
000516
000716
000916
000B16
000D16
000F16
001416
001516
001616
001716
001916
001A16
001B16
001D16
002016
002116
002216
002316
00
716
002816
002916
002A16
002B16
003216
003316
003416
003616
0016
0016
0016
0016
(4)
Port P3 output control register
Port P4 direction register
(5)
(6)
Port P5 direction register
Port P6 direction register
Port P7 direction register
AD conversion low-order register
(7)
0016
0016
(8)
(9)
✕ ✕ 0 0 0 0 0
1
Key input control register
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
0016
3F16
0016
PULL register A
PULL register B
Serial I/O1 status register
Serial I/O1 control register
UART control register
Serial I/O2 control register
Timer X low-order register
Timer X high-order register
Timer Y low-order register
Timer Y high-order register
Timer 1 register
1
1
0
1
0 0 0 0 0
0016
0
1 0 0 0 0
0016
FF
16
FF16
0116
FF16
0016
0016
0016
0016
0016
Timer 2 register
(23) Timer 3 register
(24)
Timer X mode register
(25) Timer Y mode reg
(26) Timer 123 m
(27)
T
OUT/φ ogister
(28) PWer
(29) on register
0016
0016
version register
control register
D-A control register
0 0 0 0 1 0 0
0016
0
1
(33) Watchdog timer control register 003716
(34) Segment output enable register 003816
1
0
0
1 1 1 1
0016
(35) LCD mode register
003916
0016
(36)
Interrupt edge selection register 003A16
0016
(37) CPU mode register
003B16
003C16
003D16
003E16
003F16
0 1 0 0 1 0 0
0
(38) Interrupt request register 1
(39) Interrupt request register 2
(40) Interrupt control register 1
(41) Interrupt control register 2
0016
0016
0016
0016
(42)
(43)
Processor status register
Program counter
(PS)
✕ ✕ ✕ ✕ ✕ 1 ✕ ✕
(PCH)
Contents of address FFFD16
(PC
L
)
Contents of address FFFC16
(44)
(45)
Watchdog timer (high-order)
Watchdog timer (low-order)
3F16
FF16
Note: The contents of all other registers and RAM are undefined after
reset, so they must be initialized by software.
✕ : Undefined
Fig. 56 Internal state of microcomputer immediately after reset
Rev.1.02 Jul 31, 2003 page 51 of 69
7560 Group (A version)
Oscillation Control
CLOCK GENERATING CIRCUIT
(1) Stop mode
The 7560 group has two built-in oscillation circuits: main clock
XIN-XOUT oscillation circuit and sub-clock XCIN-XCOUT oscillation
circuit. An oscillation circuit can be formed by connecting an oscil-
lator between XIN and XOUT (XCIN and XCOUT). Use the circuit
constants in accordance with the oscillator manufacturer’s recom-
mended values. No external resistor is needed between XIN and
XOUT since a feed-back resistor exists on-chip. However, an exter-
nal feed-back resistor is needed between XCIN and XCOUT since a
resistor does not exist between them.
If the STP instruction is executed, the system clock φ stops at an
“H” level, and main and sub clock oscillators stop.
In this time, values set previously to timer 1 latch and timer 2 latch
are loaded automatically to timer 1 and timer 2. Before the STP
instruction, set the values to generate the wait time required for
oscillation stabilization to timer 1 latch and timer 2 latch (low-order
8 bits are set to timer 1, high-order 8 bits are set to timer 2). Either
f(XIN) or f(XCIN) divided by 16 is input to timer 1 as count source,
and the output of timer 1 is connected to timer 2.
To supply a clock signal externally, input it to the XIN pin and make
the XOUT pin open. The sub-clock oscillation circuit cannot directly
input clocks that are externally generated. Accordingly, be sure to
cause an external oscillator to oscillate.
The bits of the timer 123 mode register xcept bit 4 are set to “0”.
Set the timer 1 and timer 2 interrupbits to “0” before ex-
ecuting the STP instruction.
Oscillation restarts at reset n external interrupt is re-
ceived, but the system clot supplied to the CPU until
timer 2 underflows. Thime for the clock circuit oscillation
to stabilize when a conator is used.
Immediately after poweron, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins go to high-impedance state.
Frequency Control
(1) Middle-speed mode
The clock input to the XIN pin is divided by 8 and it is used as the
system clock φ.
(2) Wait m
If the WIT is executed, only the system clock φ stops at
an “H” states of main clock and sub clock are the same
as tfore the executing the WIT instruction, and oscilla-
tot stop. Since supply of internal clock φ is started im-
ly after the interrupt is received, the instruction can be ex-
d immediately.
After reset, this mode is selected.
(2) High-speed mode
The clock input to the XIN pin is divided by 2 and it is used as the
system clock φ.
(3) Low-speed mode
The clock input to the XCIN pin is divided by 2 and it is
•
the system clock φ.
A low-power consumption operation can be realizping
•
XCIN
X
COUT
XIN
XOUT
the main clock in this mode. To stop the main he main
clock stop bit of the CPU mode register to
Rf
When the main clock is restarted, aftehe main clock
stop bit to “0”, set enough time for oo stabilize by pro-
gram.
Rd
C
OUT
C
CIN
C
COUT
CIN
Note: If you switch the mode bedle/high-speed and low-
speed, stabilize both CIN oscillations. The suffi-
cient time is requisub clock to stabilize, espe-
cially immediatweron and at returning from stop
mode. When sg the mode between middle/high-
speed and low-sped, set the frequency in the condition
that f(XIN) > 3•f(XCIN).
Fig. 57 Oscillator circuit
X
CIN
XCOUT
XIN
XOUT
Rf
Open
Rd
External oscillation circuit
C
CIN
CCOUT
VCC
VSS
Fig. 58 External clock input circuit
Rev.1.02 Jul 31, 2003 page 52 of 69
7560 Group (A version)
X
COUT
X
CIN
“0”
“1”
X
C
switch bit (Note)
Timer 1 count
source selection
bit
Timer 2 count
source selection
bit
X
IN
X
OUT
System clock selection bit (Note)
“1”
Low-speed mode
“0”
Timer 1
1/2
Middle-/High-speed mode
1/4
1/2
mer 2
“0”
Main clock divisiotion bit
Middle-speed
System clock φ
High-speed mode
or Low-speed mode
Main clock stop bit
Q
S
R
Q
R
S
R
Q
on
STP instruction
STP instruction
Reset
Interrupt disable flag I
Interrupt request
Note: When uclock for the system clock φ, set the X
C
switch bit to “1”.
Fig. 59 Clock generating circuit block diagram
Rev.1.02 Jul 31, 2003 page 53 of 69
7560 Group (A version)
Reset
Middle-speed mode
(f(φ) = 1 MHz)
High-speed mode
(f(φ) = 4 MHz)
CM
“1”
6
CM
CM
CM
CM
7
6
5
4
= 0 (8 MHz selected)
= 1 (Middle-speed)
= 0 (8 MHz oscillating)
= 0 (32 kHz stopped)
CM
CM
CM
CM
7
= 0 (8 MHz selected)
= 0 (High-speed)
= 0 (8 MHz oscillating)
= 0 (32 kHz stopped)
“0”
6
5
4
”
0
“
M4
”
”
C
0
“
M6
”
1
“
C
1
“
Middle-speed mode
(f(φ) = 1 MHz)
High-speed mode
(f(φ) = 4 MHz)
CM
“1”
6
CM
CM
CM
CM
7
6
5
4
= 0 (8 MHz selected)
= 1 (Middle-speed)
= 0 (8 MHz oscillating)
CM
CM
CM
CM
7
6
5
4
= 0 (8 MHz selecte
= 0 (High-speed)
= 0 (8 MHz os
= 1 (32 kHz
“0”
= 1 (32 kHz oscillating)
Low-speed mode
(f(φ) = 16 kHz)
Low-speed mode
(f(φ) = 16 kHz)
CM
“1”
6
CM
CM
CM
CM
7
6
5
4
= 1 (32 kHz selected)
= 1 (Middle-speed)
= 0 (8 MHz oscillating)
= 1 (32 kHz oscillating)
CM
CM
CM
CM
7
6
5
4
= 1 (32 kHz selected)
= 0 (High-speed)
= 0 (8 MHz oscillating)
= 1 (32 kHz oscillating)
b7
b4
CPU mode register
(CPUM : address 003B16
)
CM
CM
CM
CM
4 : Xc switch bit
0: Oscillation stop
1: XCIN, XCOUT
”
0
“
5
: Main clock (XIN–XOUT) stop bit
M6
0: Oscillating
1: Stopped
C
”
1
“
6
: Main clock division ratio selection bit
Low-speed mo
(f(φ) = 16 kHz)
Low-speed mode
(f(φ) = 16 kHz)
0: f(XIN)/2 (high-speed mode)
1: f(XIN)/8 (middle-speed mode)
CM
“1”
6
CM
CM
CM
CM
7
6
5
4
= 1 (32 kHz selected)
= 1 (Middle-speed)
CM
CM
CM
CM
7
6
5
4
= 1 (32 kHz selected)
= 0 (High-speed)
= 1 (8 MHz stopped)
= 1 (32 kHz oscillating)
“0”
7
: System clock selection bit
0: XIN–XOUT selected
= 1 (8 MHz stopped)
= 1 (32 kHz oscillating)
(middle-/high-speed mode)
1: XCIN–XCOUT selected
(low-speed mode)
Notes
1: Switch the mode according to the arrows shown between the mode blocks. (Do not switch between the mode directly without an arrow.)
2: The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait
mode is ended.
3: When the stop mode is ended, a delay time can be set by timer 1 and timer 2.
4: Timer and LCD operate in the wait mode.
5: Wait until oscillation stabilizes after oscillating the main clock before the switching from the low-speed mode to middle-/high-speed mode.
6: The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the system clock.
Fig. 60 State transitions of system clock
Rev.1.02 Jul 31, 2003 page 54 of 69
7560 Group (A version)
NOTES ON PROGRAMMING
Serial I/O
Processor Status Register
In clock synchronous serial I/O, if the receive side is using an ex-
ternal clock and it is to output the SRDY signal, set the transmit en-
able bit, the receive enable bit, and the SRDY output enable bit to
“1”.
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags (T flag, D flag, etc.) which affect program
execution.
The TxD pin of serial I/O1 retains the level then after transmission
is completed.
Interrupt
In serial I/O2 selecting an internal clock, the SOUT2 pin goes to
high impedance state after transmission is completed.
In serial I/O2 selecting an external clock, the SOUT2 pin retains the
level then after transmission is completed.
When the contents of an interrupt request bits are changed by the
program, execute a BBC or BBS instruction after at least one in-
struction. This is for preventing executing a BBC or BBS
instruction to the contents before change.
A-D Converter
Decimal Calculations
The input to the comparator is cy internal capacitors.
Therefore, since conversion aay be worse by losing of
an electric charge when tsion speed is not enough,
make sure that f(XIN) i00 kHz during an A-D conver-
sion.
To calculate in decimal notation, set the decimal mode flag (D) to
“1”, then execute an ADC or SBC instruction. After executing an
ADC or SBC instruction, execute at least one instruction before
executing a SEC, CLC, or CLD instruction.
The normal operD conversion cannot be guaranteed
when performit operation:
In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
•When wrU mode register during A-D conversion op-
erati
Multiplication and Division Instructions
The index mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
•Wto A-D control register during A-D conversion op-
executing STP instruction or WIT instruction during A-D
nversion operation
The execution of these instructions does not change the contents
of the processor status register.
Instruction Execution Time
Ports
The instruction execution time is obtained by multiplying the fre-
quency of the system clock φ by the number of cycles needed to
execute an instruction.
Use instructions such as LDM and STA, etc., to set the -
tion registers.
The contents of the port direction registers cann
The following cannot be used:
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
• LDA instruction
The frequency of the system clock φ depends on the main clock
division ratio selection bit and the system clock selection bit.
• The memory operation instruction whag is “1”
• The bit-test instruction (BBC or BB
• The read-modify-write instructition instruction such as
ROR etc., bit manipulation isuch as CLB or SEB etc.)
• The addressing mode wthe value of a direction regis-
ter as an index
Rev.1.02 Jul 31, 2003 page 55 of 69
7560 Group (A version)
NOTES ON USE
Countermeasures Against Noise
Noise
(1) Shortest wiring length
✕ Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin
as short as possible. Especially, connect a capacitor across the
RESET pin and the VSS pin with the shortest possible wiring
(within 20 mm).
X
X
V
IN
X
X
V
IN
OUT
OUT
SS
SS
✕ Reason
O.K.
N.G.
The width of a pulse input into the RESET pin is determined by
the timing necessary conditions. If noise having a shorter pulse
width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is com-
pletely initialized. This may cause a program runaway.
Fig. 62 Wiring for clock I/O
(2) Connection of bypar across VSS line and VCC line
In order to stabilize operation and avoid the latch-up,
connect an appro.1 µF bypass capacitor across the VSS
line and the Vfollows:
Noise
• Connect apacitor across the VSS pin and the VCC pin
at equ
Reset
• Copass capacitor across the VSS pin and the VCC pin
hortest possible wiring.
RESET
circuit
es with a larger diameter than other signal lines for VSS
and VCC line.
VSS
VSS
Connect the power source wiring via a bypass capacitor to the
VSS pin and the VCC pin.
N.G.
Reset
circuit
V
CC
V
CC
RESE
V
VSS
O.K
Fig. 61 Wiring for the RES
V
SS
V
SS
✕ Wiring for clock inpins
• Make the length of g which is connected to clock I/O pins
as short as possible.
N.G.
O.K.
• Make the length of wiring (within 20 mm) across the grounding
lead of a capacitor which is connected to an oscillator and the
VSS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS
patterns.
Fig. 63 Bypass capacitor across the VSS line and the VCC line
✕ Reason
If noise enters clock I/O pins, clock waveforms may be de-
formed. This may cause a program failure or program runaway.
Also, if a potential difference is caused by the noise between
the VSS level of a microcomputer and the VSS level of an oscil-
lator, the correct clock will not be input in the microcomputer.
Rev.1.02 Jul 31, 2003 page 56 of 69
7560 Group (A version)
(3) Oscillator concerns
(4) Analog input
In order to obtain the stabilized operation clock on the user system
and its condition, contact the oscillator manufacturer and select
the oscillator and oscillation circuit constants. Be careful espe-
cially when range of voltage or/and temperature is wide.
Also, take care to prevent an oscillator that generates clocks for a
microcomputer operation from being affected by other signals.
The analog input pin is connected to the capacitor of a compara-
tor. Accordingly, sufficient accuracy may not be obtained by the
charge/discharge current at the time of A-D conversion when the
analog signal source of high-impedance is connected to an analog
input pin. In order to obtain the A-D conversion result stabilized
more, please lower the impedance of an analog signal source, or
add the smoothing capacitor to an analog input pin.
✕ Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as
possible from signal lines where a current larger than the toler-
ance of current value flows.
(5) Difference of memory type and size
When Mask ROM and PROM version and memory size differ in
one group, actual values such as an eletrical characteristics, A-D
conversion accuracy, and the amouoof of noise incorrect
operation may differ from the ide
✕ Reason
In the system using a microcomputer, there are signal lines for
controlling motors, LEDs, and thermal heads or others. When a
large current flows through those signal lines, strong noise oc-
curs because of mutual inductance.
When these products are use, perform system evalua-
tion for each product after confirming product
specification.
✕ Installing oscillator away from signal lines where potential levels
change frequently
Install an oscillator and a connecting pattern of an oscillator
away from signal lines where potential levels change frequently.
Also, do not cross such signal lines over the clock lines or the
signal lines which are sensitive to noise.
✕ Reason
Signal lines where potential levels change frequently (su
the CNTR pin signal line) may affect other lines at sign
edge or falling edge. If such lines cross over a clock
waveforms may be deformed, which causes a uter
failure or a program runaway.
✕ Keeping oscillator away from large cal lines
omputer
Mutual inductance
M
XIN
XOUT
La
curr
VSS
GND
✕ Installing oscillator away from signal lines where potential
levels change frequently
N.G.
CNTR
Do not cross
X
X
V
IN
OUT
SS
Fig. 64 Wiring for a large current signal line/Wiring of signal
lines where potential levels change frequently
Rev.1.02 Jul 31, 2003 page 57 of 69
7560 Group (A version)
ROM ORDERING METHOD
1.Mask ROM Order Confirmation Form
2.Mark Specification Form
3.Data to be written to ROM, in EPROM form (three identical cop-
ies) or one floppy disk.
• For the mask ROM confirmation and the mark specifications,
refer to the “Renesas Technology Corp.” Homepage
(http://www.renesas.com/en/
Rev.1.02 Jul 31, 2003 page 58 of 69
7560 Group (A version)
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Table 12 Absolute maximum ratings
Symbol
VCC
Parameter
Power source voltage
Conditions
Ratings
Unit
V
–0.3 to 6.5
VI
Input voltage P00–P07, P10–P17, P20–P27,
P40–P47, P50–P57, P60–P67
–0.3 to VCC +0.3
V
VI
VI
VI
VI
VI
VI
VO
–0.3 to VCC +0.3
–0.3 to VL2
VL1 to VL3
V
V
V
V
V
V
V
V
V
Input voltage P70–P77
Input voltage VL1
All voltages are based on VSS.
Output transistors are cut off.
Input voltage VL2
VL2 to 6.5
Input voltage VL3
3 to 6.5
Input voltage C1, C2
Input voltage RESET, XIN
Output voltage C1, C2
C +0.3
3 to 6.5
0.3 to VCC
–0.3 to VL3
At output port
VO
Output voltage P00–P07, P10–P15, P30–P37
At segment output
Output voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P71–P77
–0.3 to VCC +0.3
V
VO
VO
Output voltage VL3
–0.3 to 6.5
–0.3 to VL3
V
V
VO
Output voltage VL2, SEG0–SEG17
Output voltage XOUT
VO
–0.3 to VCC +0.3
V
Ta = 25°C
Pd
Power dissipation
Operating temperature
Storage temperature
300
–20 to 85
–40 to 125
mW
°C
°C
Topr
Tstg
RECOMMENDED OPERATING CONDITI
Table 13 Recommended operating conditions (1) (to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
eter
Unit
Min.
4.5
Typ.
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
Max.
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
VCC
Power source voltage
(Note 1)
V
V
V
V
V
V
V
V
V
V
V
V
V
V
-speed mode
f(XIN) = 10 MHz
f(XIN) = 8 MHz
f(XIN) = 6 MHz
f(XIN) = 4 MHz
f(XIN) = 10 MHz
f(XIN) = 8 MHz
f(XIN) = 6 MHz
4.0
3.0
2.0
Middle-speed mode
Low-speed mode
3.0
2.0
1.8
1.8
At start oscillating (Note 2)
0.15 ✕ f+1.3
VSS
VLI
Power source voltage
Power source voltage
0
1.8
2.1
At using voltage multiplier
1.3
2.0
VREF
AVSS
VIA
A-D, D-A conversion reference voltage
Analog power source voltage
VCC
0
Analog input voltage AN0–AN7
VCC
AVSS
Notes 1: When using the A-D or D-A converter, refer to “A-D Converter Characteristics” or “D-A Converter characteristics”.
2: The oscillation start voltage and the oscillation start time differ in accordance with an oscillator, a circuit constant, or temperature, etc. When power
suppl voltage is low and high frequency oscillator is used, an oscillation start will require sufficient conditions.
f: This is an oscillator’s oscillation frequency. For example, when oscillation frequency is 8 MHz, substitute “8”.
Rev.1.02 Jul 31, 2003 page 59 of 69
7560 Group (A version)
Table 14 Recommended operating conditions (2) (VCC = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
VCC
“H” input voltage
“H” input voltage
P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
VIH
0.7 VCC
V
V
P20–P27, P41, P42, P44, P46, P54, P55, P57, P60,
P62, P63, P70
VIH
0.8 VCC
VCC
VIH
VIH
“H” input voltage
“H” input voltage
“L” input voltage
RESET
XIN
0.8 VCC
0.8 VCC
VCC
VCC
V
V
P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
V
V
VIL
VIL
0
0
0.3 VCC
0.2 VCC
“L” input voltage
P20–P27, P41, P42, P44, P46, P54, P55, P57, P60,
P62, P63, P70
VIL
VIL
“L” input voltage
“L” input voltage
0.2 VCC
0.2 VCC
V
V
RESET
XIN
Table 15 Recommended operating conditions (3) (VCC = 1.8 to 5.5 V, Ta = –20 to 85°C, unlwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
–20
–20
20
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
“L” total peak output current
“H” total average output current
“H” total average output current
“L” total average output current
“L” total average output current
“L” total average output current
“H” peak output current
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
P00–P07, P10–P17, P20–P27, P30–1)
P41–P47, P50–P57, P60–P67 (N
P00–P07, P10–P17, P20–P27(Note 1)
P41–P47, P50–P57, P60–1)
P40, P71–P77 (Note 1
20
80
–10
–10
10
P00–P07, P10–P17P30–P37 (Note 1)
P41–P47, P50–67 (Note 1)
P00–P07, P10–P27, P30–P37 (Note 1)
P41–P47P60–P67 (Note 1)
P40, Note 1)
10
40
–1.0
P00–P15, P30–P37 (Note 2)
“H” peak output current
P20–P27, P41–P47, P50–P57, P60–P67
2)
IOH(peak)
IOL(peak)
IOL(peak)
–5.0
5.0
mA
mA
“L” peak output current
“L” peak output current
–P07, P10–P15, P30–P37 (Note 2)
P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 2)
10
mA
“L” peak output cur
IOL(peak)
IOH(avg)
IOH(avg)
20
mA
mA
mA
P40, P71–P77 (Note 2)
“H” average outt
“H” average rent
–0.5
–2.5
P00–P07, P10–P15, P30–P37 (Note 3)
P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 3)
“L” avut current
“L” averutput current
2.5
5.0
mA
mA
IOL(avg)
IOL(avg)
P00–P07, P10–P15, P30–P37 (Note 3)
P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 3)
“L” average output current
IOL(avg)
10
P40, P71–P77 (Note 3)
mA
Notes1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
Rev.1.02 Jul 31, 2003 page 60 of 69
7560 Group (A version)
Table 16 Recommended operating conditions (4) (VCC = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
(4.5 V ≤ VCC ≤ 5.5 V)
Unit
Min.
Typ.
Max.
5.0
MHz
f(CNTR0)
f(CNTR1)
Input frequency for timers X and Y
(duty cycle 50%)
(4.0 V ≤ VCC < 4.5 V)
(2.0 V ≤ VCC < 4.0 V)
(VCC < 2.0 V)
2✕VCC–4 MHz
VCC
5✕VCC–8 MHz
MHz
Main clock input oscillation frequency
f(XIN)
High-speed mode
10.0
MHz
(Note 1)
(4.5 V ≤ VCC ≤ 5.5 V)
High-speed mode
4✕VCC–8 MHz
(4.0 V ≤ VCC < 4.5 V)
High-speed mode
(2.0 V ≤ VCC < 4.0 V)
2✕VCC
10.0
8.0
MHz
MHz
MHz
Middle-speed mode (Note 3)
(3.0 V ≤ VCC ≤ 5.5 V)
Middle-speed mode (Note 3)
(2.0 V ≤ VCC ≤ 5.5 V)
Middle-speed mode (Note 3)
6.0
50
MHz
kHz
Sub-clock input oscillation frequency (At duty 50 %) (Notes 2, 3)
f(XCIN)
32.768
Notes 1: When using the A-D or D-A converter, refer to “A-D Converter Characteristics” or “D-A Coacteristics”.
2: When using the microcomputer in low-speed mode, set the clock input oscillation frequdition that f(XCIN) < f(XIN)/3.
3: The oscillation start voltage and the oscillation start time differ in accordance with aa circuit constant, or temperature, etc. When power
suppl voltage is low and high frequency oscillator is used, an oscillation start will cient conditions.
Rev.1.02 Jul 31, 2003 page 61 of 69
7560 Group (A version)
Table 17 Electrical characteristics (1) (VCC =4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
IOH = –1 mA
Unit
Max.
Min.
VCC–2.0
V
V
“H” output voltage
P00–P07, P10–P15, P30–P37
VOH
IOH = –0.25 mA
VCC = 2.2 V
VCC–0.8
IOH = –5 mA
VCC–2.0
VCC–0.5
V
V
“H” output voltage
P16, P17, P20–P27, P41–P47, P50–P57,
P60–P67
IOH = –1.5 mA
VOH
VOL
VOL
IOH = –1.25 mA
VCC = 2.2 V
VCC–0.8
V
IOL = 5 mA
2.0
0.5
0.8
V
V
V
“L” output voltage
P00–P07, P10–P15, P30–P37
IOL = 1.5 mA
IOL = 1.25 mA
VCC = 2.2 V
2.0
0.5
0.8
V
V
V
IOL = 10 mA
IOL = 3.0 mA
“L” output voltage
P16, P17, P20–P27, P41–P47, P50–P57,
P60–P67
IOL = 2.5 mA
VCC = 2.2 V
0.5
0.3
IOL = 10 mA
V
V
“L” output voltage
P40, P71–P77
VOL
IOL = 5 mA
VCC = 2.2 V
Hysteresis
0.5
V
VT+ – VT–
INT0–INT2, ADT, CNTR0, CNTR1, P20–P27
0.5
0.5
Hysteresis
SCLK, RXD, SIN2
RESET
VT+ – VT–
VT+ – VT–
V
V
VCC = 2.0 V
VI = VCC
Hysteresis
“H” input current
P00–P07, P10–P17, P20–P27, P40–P47,
P50–P57, P60–P67, P70–P77
5.0
µA
IIH
µA
µA
IIH
IIH
IIL
“H” input current RESET
“H” input current XIN
C
5.0
4.0
“L” input current
P00–P07,P10–P17, P20–P27,P41–P
P50–P57, P60–P67
–5.0
µA
VSS
ull-ups “off”
µA
VCC = 5 V, VI = VSS
Pull-ups “on”
–60.0
–5.0
–120.0 –240.0
µA
VCC = 2.2 V, VI = VSS
Pull-ups “on”
–20.0
–40.0
IIL
–5.0
–5.0
µA
µA
µA
µA
“L” input current P40
“L” input current
“L” input current
IIL
VI = VSS
VI = VSS
IIL
–4.0
VCC = 5.0 V, VO = VCC, Pullup ON
Output transistors “off”
–60.0
–5.0
–120.0 –240.0
ILOAD
Output load
P30–P3
µA
VCC = 2.2 V,VO = VCC, Pullup ON
Output transistors “off”
–20.0
–40.0
5.0
VO = VCC, Pullup OFF
Output transistors “off”
µA
µA
ILEAK
Output leacurrent
P30–P37
VO = VSS, Pullup OFF
Output transistors “off”
–5.0
Rev.1.02 Jul 31, 2003 page 62 of 69
7560 Group (A version)
Table 18 Electrical characteristics (2) (VCC = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
1.8
Max.
5.5
V
VRAM
ICC
RAM retention voltage
Power source current
At clock stop mode
• High-speed mode, VCC = 5 V
f(XIN) = 10 MHz
4.5
9.0
mA
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz
4.0
0.9
8.0
1.8
mA
mA
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter stop
• Low-speed mode, VCC = 5 V, Ta ≤ 55
f(XIN) = stopped
15
7
30
14
µA
µA
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC 25°C
f(XIN) = stopped
f(XCIN) = 32.768 T state)
Output transi
• Low-speeCC = 3 V, Ta ≤ 55°C
f(XIN) =
9
18
µA
µA
µA
f(X68 kHz
nsistors “off”
eed mode, VCC = 3 V, Ta = 25°C
N) = stopped
4.5
9.0
(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
Output transistors “off”
Ta = 25 °C
Ta = 85 °C
0.1
4.0
1.0
10
µA
µA
Power rrent
IL1
VL1 = 1.8 V
(VL1)
(Note)
Note: When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”.
Rev.1.02 Jul 31, 2003 page 63 of 69
7560 Group (A version)
Table 19 A-D converter characteristics (1)
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, f(XIN) = 500 kHz to 10 MHz, in middle/high-speed mode unless otherwise noted)
8-bit A-D mode (when conversion mode selection bit (bit 0 of address 001416) is “1”)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
8
Bits
–
–
Resolution
VCC = VREF = 2.7 to 5.5 V
±2
LSB
Absolute accuracy
(excluding quantization error)
µS
12.5
(Note)
100
tCONV
Conversion time
RLADDER
IVREF
IIA
Ladder resistor
12
50
35
kΩ
µA
µA
200
5.0
Reference power source input current
Analog port input current
VREF = 5 V
150
Note: When the internal trigger is used in the middle-speed mode, the max. value of tCONV is 14 µS.
Table 20 A-D converter characteristics (2)
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, f(XIN) = 500 kHz to 10 MHz, in middle/himode unless otherwise noted)
10-bit A-D mode (when conversion mode selection bit (bit 0 of address 001416) is “0”)
Limits
Symbol
Parameter
Test conditi
Unit
Min.
Typ.
Max.
10
Bits
–
–
Resolution
VCC = VREF = V
±4
LSB
Absolute accuracy
(excluding quantization error)
µS
15.5
(Note)
100
tCONV
Conversion time
RLADDER
IVREF
IIA
Ladder resistor
12
50
35
kΩ
µA
µA
200
5.0
Reference power source input current
Analog port input current
V
150
Note: When the internal trigger is used in the middle-spethe max. value of tCONV is 17 µS.
Table 21 D-A converter characteristics
(VCC = 2.7 to 5.5 V, VCC = VREF, VSS = AVSS = 20 to 85°C, in middle/high-speed mode unless otherwise noted)
Limits
Symbol
Paramet
Test conditions
Unit
Min.
Typ.
Max.
8
Bits
%
–
–
Resolution
1.0
2.0
VCC = VREF = 5 V
Absolute accura
%
VCC = VREF = 2.7 V
Setting time
µs
tsu
3
1
4
kΩ
mA
Output r
RO
2.5
(Note)
IVREF
Referer source input current
3.2
Note: Using one D-A conve, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding currents flowing through
the A-D resistance ladder.
Rev.1.02 Jul 31, 2003 page 64 of 69
7560 Group (A version)
Table 22 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
2
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
100
1000/(4✕Vcc-8)
twH(XIN)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
40
45
twL(XIN)
40
45
tc(CNTR)
twH(CNTR)
twL(CNTR)
200
1000/(2✕Vcc-4)
85
10
twH(INT)
twL(INT)
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
80
tc(SCLK1)
twH(SCLK1)
twL(SCLK1)
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
800
370
370
220
100
1000
400
400
200
200
t
su(RXD–SCLK1)
th(SCLK1–RXD) Serial I/O1 input hold time
tc(SCLK2)
Serial I/O2 clock input cycle time (Note)
twH(SCLK2)
twL(SCLK2)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O2 input set up time
t
su(RXD–SCLK2)
th(SCLK2–RXD) Serial I/O2 input hold time
Note: When bit 6 of address 001A16 is “1”.
Divide this value by four when bit 6 of address 001A
Rev.1.02 Jul 31, 2003 page 65 of 69
7560 Group (A version)
Table 23 Timing requirements (2) (VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
2
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
(2.0 V ≤ VCC ≤ 4.0 V)
(VCC < 2.0 V)
125
1000/(10✕Vcc-12)
twH(XIN)
twL(XIN)
tc(CNTR)
(2.0 V ≤ VCC ≤ 4.0 V)
(VCC < 2.0 V)
50
70
(2.0 V ≤ VCC ≤ 4.0 V)
(VCC < 2.0 V)
50
70
(2.0 V ≤ VCC ≤ 4.0 V)
(VCC < 2.0 V)
1000/VCC
1000/(5✕Vcc-
tc(CNTR)/2
twH(CNTR)
twL(CNTR)
twH(INT)
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
ns
ns
tc(CNT
twL(INT)
00
950
950
400
200
2000
950
950
400
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tc(SCLK1)
twH(SCLK1)
twL(SCLK1)
t
su(RXD–SCLK1)
th(SCLK1–RXD)
tc(SCLK2)
Serial I/O1 input hold time
Serial I/O2 clock input cycle time (Note)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O2 input set up time
twH(SCLK2)
twL(SCLK2)
t
su(R
XD–SCLK2)
th(SCLK2–RXD)
Serial I/O2 input hold time
Note: When bit 6 of address 001A16 is “1”.
Divide this value by four when bit 6 of address 001A16 is “
Rev.1.02 Jul 31, 2003 page 66 of 69
7560 Group (A version)
Table 24 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Max.
140
Typ.
tC (SCLK1)/2–30
tC (SCLK1)/2–30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
twH(SCLK1)
twL(SCLK1)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
td(SCLK1–TXD) Serial I/O1 output delay time (Note)
tv(SCLK1–TXD) Serial I/O1 output valid time (Note)
–30
tr(SCLK1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
30
30
tf(SCLK1)
t
t
C
C
(SCLK2)/2–160
(SCLK2)/2–160
twH(SCLK2)
twL(SCLK2)
t
t
d(SCLK2–SOUT2
v(SCLK2–SOUT2
)
0.2 ✕ t
C
(SCLK2
)
0
)
Serial I/O2 output valid time
tf(SCLK2)
Serial I/O2 clock output falling time
40
Note: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”
Table 25 Switching characteristics (2) (VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to ess otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
350
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse w
Serial I/O2 output delay time
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
tC (SCLK1)/2–100
tC (SCLK1)/2–100
–30
100
100
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
t
t
C
C
(SCLK2)/2–240
(SCLK2)/2–240
t
t
d(SCLK2–SOUT2
v(SCLK2–SOUT2
)
0.2 ✕ t
C
(SCLK2
)
Serial I/O2 output valid time
)
0
Serial I/O2 clock output f
tf(SCLK2)
100
Notes1: When the P45/TXD P-channel oubit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excl
1 kΩ
Measurement output pin
Measurement output pin
100 pF
100 pF
CMOS output
N-channel open-drain output (Note)
–P7 , P4 and bit 4 of the UART control
Note: When P7
1
7
0
register (address 001B16) is “1” (N-channel open-
drain output mode).
Fig. 65 Circuit for measuring output switching characteristics
Rev.1.02 Jul 31, 2003 page 67 of 69
7560 Group (A version)
t
C(CNTR)
t
WL(CNTR)
t
WH(CNTR)
0.8VCC
CNTR
0
, CNTR
1
0.2VCC
t
WL(INT)
t
WH(INT)
0.8VCC
INT0–INT
RESET
2
0.2VCC
t
W(RESET)
0.8VCC
0.2VCC
t
C(XIN)
t
WL(XIN)
0
XIN
0.2VCC
t
C(SCLK1),
t
C(SCLK2
)
t
r
t
f
t
WL(SCLK1),
t
WL(SCLK2
)
t
WH(SCLK1), WH(SCLK2)
t
S
S
CLK1
CLK2
0.8VCC
0.2VCC
t
t
su(R
X
D
-
S
CLK1),
CLK2
th(SCLK1-
R
X
D),
su(SIN2-
S
)
t
h(SCLK2-S
IN2)
R D
X
0.8VCC
0.2VCC
SIN2
t
t
v(SCLK1-T
X
D),
t
d(SCLK1-T
XD),td(SCLK2-
SOUT2)
v(SCLK2-
S
OUT2
)
TXD
SOUT2
Fig. 66 Timing diagram
Rev.1.02 Jul 31, 2003 page 68 of 69
7560 Group (A version)
PACKAGE OUTLINE
MMP
100P6Q-A
Plastic 100pin 14✕14mm body LQFP
EIAJ Package Code
JEDEC Code
–
Weight(g)
0.63
Lead Material
Cu Alloy
MD
LQFP100-P-1414-0.50
HD
D
100
76
l2
Recommended Mount Pad
1
75
Dimension iMillimeters
Symbol
A
Min
–
Max
1.7
0.2
–
A1
0
A
2
4
b
3.9
–
0.18
0.125
14.0
14.0
0.5
0.28
0.175
14.1
14.1
–
c
25
51
L
15.8
15.8
0.3
–
0.45
–
–
–
0°
–
16.0
16.0
0.5
1.0
0.6
0.25
–
–
16.2
16.2
0.7
–
0.75
–
0.08
0.1
10°
–
26
50
E
A
L
1
L1
F
e
Lp
A3
x
y
–
b
x
y
M
b2
0.225
–
14.4
14.4
I2
0.9
–
–
–
–
–
Lp
M
M
D
E
MMP
100P6S-A
Plastic 100pin 14✕20mm body QFP
EIAJ Package Code
JEDEC Code
W
Lead Material
Alloy 42
MD
QFP100-P-1420-0.65
–
HD
D
100
1
80
I
2
Recommended Mount Pad
Dimension in Millimeters
Symbol
Min
–
0
–
0.25
0.13
13.8
19.8
–
16.5
22.5
0.4
–
–
–
0°
–
1.3
–
Nom
–
Max
3.05
0.2
–
0.4
0.2
14.2
20.2
–
17.1
23.1
0.8
–
0.13
0.1
10°
–
A
A
A
1
2
0.1
2.8
0.3
0.15
14.0
20.0
0.65
16.8
22.8
0.6
1.4
–
b
c
D
E
e
30
51
31
50
HD
A
L1
HE
L
L1
x
y
–
–
F
b2
0.35
–
14.6
20.6
e
b
L
x
M
I2
–
–
–
Detail F
y
M
M
D
E
–
Rev.1.02 Jul 31, 2003 page 69 of 69
7560 Group (A version) Data Sheet
REVISION HISTORY
Rev.
Date
Description
Summary
Page
1.00 Feb. 18, 2003
1.02 Jul. 31, 2003
–
1
First edition issued
Power dissipation revised.
4
Table 1 Pin description (1) VCC VSS; Function description revised.
Fig.5 Memory expansion plan revised.
7
18
Fig.14 Port block diagram (1);
(4) Ports P16, P17,P2, P41, P42 and (5) Port P44 revised
Fig.15 Port block diagram (2);
19
20
21
(7) Port P46 and (11) Port P54 revised.
Fig.16 Port block diagram (3);
(14) Port P55, (15) Ports P56, P57 and (170 revised.
Fig.17 Port block diagram (4);
(19) Port P62 revised.
39
44
Fig.40 A-D converter block diagr
Voltage Multiplier (3 Times)
Description of order for opthe voltage multiplier revised.
ROM ORDERING MEvised.
58
61
63
64
Table 16 Recommperating conditions (4); f(CNTR0) f(CNTR1) revised.
Table 18 Electriacteristics (2); ICC revised.
Table 19 A-ter characteristics (1); Note revised.
Table 20 verter characteristics (2); Note revised.
Table ng requirements (1);
65
66
tc(WH(SCLK), tWL(SCLK), tsu(RxD-SCLK), th(SCLK-RxD); revised.
3 Timing requirements (2);
CLK), tWH(SCLK), tWL(SCLK), tsu(RxD-SCLK), th(SCLK-RxD); revised.
Table 25 Switching characteristics (2) ; tr(SCLK1) tf(SCLK1) revised.
Sales Strategic Planning Div. 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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