M37151MC [RENESAS]
SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER; SNGLE - CHIP 8 - BIT的CMOS微机型号: | M37151MC |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
文件: | 总138页 (文件大小:1167K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER
REJ03B0129-0100Z
Rev.1.00
Nov 01, 2002
1. DESCRIPTION
The M37151M6/M8/MA/MC/MF-XXXFP and M37151EFFP are
(It is possible to display 3 lines or more by software)
Kinds of characters ........................................................ 254 kinds
single-chip microcomputers designed with CMOS silicon gate tech-
(coloring unit)
(per charactor unit)
2
nology. They have an OSD, data slicer, and I C-BUS interface, mak-
Character display area ............................ CC mode: 16 ● 26 dots
OSD mode: 16 ● 20 dots
ing them perfect for TV channel selection systems with a closed cap-
tion decoder. The M37151EFFP has a built-in PROM that can be
written electrically.
Kinds of character sizes ..................................... CC mode: 1 kind
OSD mode: 8 kinds
Kinds of character colors .................................. 8 colors (R, G, B)
Coloring unit ................... character, character background, raster
Display position
2. FEATURES
●Number of basic instructions .................................................... 71
●Memory size
Horizontal: 128 levels
Vertical: 512 levels
ROM .............. 24K bytes
Attribute ........................................................................................
CC mode: smooth italic, underline, flash, automatic solid space
OSD mode: border
(M37151M6-XXXFP)
32K bytes
(M37151M8-XXXFP)
Smooth roll-up
40K bytes
Window function
(M37151MA-XXXFP)
48K bytes
3. APPLICATION
TV with closed caption decoder
(M37151MC-XXXFP)
60K bytes
(M37151MF-XXXFP, M37151EFFP)
RAM ............... 1024 bytes
(M37151M6-XXXFP)
1152 bytes
(M37151M8-XXXFP)
1472 bytes
(M37151MA-XXXFP, M37151MC-XXXFP)
2048 bytes
(M37151MF-XXXFP, M37151EFFP)
(*ROM correction memory included)
●Minimum instruction execution time
................................................................. 0.5 µs (Min.)(at 8 MHz)
●Power source voltage ................................................. 5 V ± 10 %
●Subroutine nesting ............................................. 128 levels (Max.)
●Interrupts ....................................................... 17 types, 16 vectors
●8-bit timers .................................................................................. 6
●Programmable I/O ports (Ports P0, P1, P2, P30, P31) ............. 25
●Serial I/O ............................................................ 8-bit ● 1 channel
2
●Multi-master I C-BUS interface .............................. 1 (3 systems)
●A-D comparator (7-bit resolution) ................................ 8 channels
●PWM output circuit......................................................... 8-bit ● 5
●Power dissipation
High-speed mode ............................................................ 165 mW
(at VCC = 5.5V, Oscillation frequency 8 MHz, OSD on, and Data
slicer on)
Low-speed mode ............................................................ 0.33 mW
(at VCC = 5.5V, 32 kHz oscillation frequency)
●Closed caption data slicer
●ROM correction function ................................................ 2 vectors
●OSD function
Display characters ................................... 32 characters ● 2 lines
Rev.1.00 Nov 01, 2002 page 1 of 136
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TABLE OF CONTENTS
14. MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS..... 102
15. PROM PROGRAMMING METHOD......................... 103
16. DATA REQUIRED FOR MASK ORDERS ................ 103
17. ONE TIME PROM VERSION M37151EFFP MARKING .............. 104
18. APPENDIX ............................................................... 105
19. PACKAGE OUTLINE ............................................... 136
1. DESCRIPTION............................................................... 1
2. FEATURES .................................................................... 1
3. APPLICATION ................................................................ 1
4. PIN CONFIGURATION .................................................. 3
5. FUNCTIONAL BLOCK DIAGRAM ................................. 4
6. PERFORMANCE OVERVIEW ....................................... 5
7. PIN DESCRIPTION........................................................ 7
8. FUNCTIONAL DESCRIPTION..................................... 11
8.1 CENTRAL PROCESSING UNIT (CPU) .......... 11
8.2 MEMORY........................................................ 12
8.3 INTERRUPTS ................................................. 17
8.4 TIMERS .......................................................... 22
8.5 SERIAL I/O ..................................................... 26
8.6 MULTI-MASTER I2C-BUS INTERFACE ......... 29
8.7 PWM OUTPUT FUNCTION............................ 42
8.8 A-D COMPARATOR........................................ 46
8.9 ROM CORRECTION FUNCTION................... 48
8.10 DATA SLICER ............................................... 49
8.11 OSD FUNCTIONS ........................................ 60
8.11.1 Display Position ................................. 65
8.11.2 Dot Size ............................................. 69
8.11.3 Clock for OSD .................................... 70
8.11.4 Field Determination Display ............... 71
8.11.5 Memory for OSD ................................ 73
8.11.6 Character color .................................. 77
8.11.7 Character background color............... 77
8.11.8 OUT signals ....................................... 78
8.11.9 Attribute .............................................. 79
8.11.10 Multiline Display ............................... 84
8.11.11 Automatic Solid Space Function....... 85
8.11.12 Window Function ............................. 86
8.11.13 OSD Output Pin Control................... 88
8.11.14 Raster Coloring Function ................. 89
8.12 SOFTWARE RUNAWAY DETECT FUNCTION.... 91
8.13 RESET CIRCUIT .......................................... 92
8.14 CLOCK GENERATING CIRCUIT ................. 93
8.15 OSD OSCILLATION CIRCUIT ...................... 97
8.16 AUTO-CLEAR CIRCUIT ............................... 98
8.17 ADDRESSING MODE .................................. 98
8.18 MACHINE INSTRUCTIONS ......................... 98
9. PROGRAMMING NOTES ............................................ 98
10. ABSOLUTE MAXIMUM RATINGS ............................. 99
11. RECOMMENDED OPERATING CONDITIONS ......... 99
12. ELECTRIC CHARACTERISTICS ............................ 100
13. A-D CONVERTER CHARACTERISTICS................. 102
Rev.1.00 Nov 01, 2002 page 2 of 136
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4. PIN CONFIGURATION
1
42
P12/SCL2
P13/SDA1
P14/SDA2
P16/AD8/TIM2
P50/HSYNC
P51/VSYNC
P52/B
P11/SCL1
2
3
41
40
39
P00/PWM0
P01/PWM1
P02/PWM2
P03/PWM3/AD1
P04/PWM4/AD2
P05/AD3
4
5
38
37
6
7
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
8
P53/G
P06/INT2/AD4
P07/INT1
9
P54/R
10
11
12
13
14
15
16
17
18
19
20
21
P20/SCLK/AD5
P21/SOUT/AD6
P22/SIN/AD7
P23/TIM3
P55/OUT
CLKCONT/P10
P30/SDA3
P31/SCL3
P15
P24/TIM2
10KΩ
P25/INT3
P26/XCIN
RESET
CVIN
VHOLD
HLF
P27/XCOUT
CNVSS
XIN
XOUT
VSS
FLIT
VCC
Outline 42P2R
Fig. 4.1 Pin Configuration (Top View)
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5. FUNCTIONAL BLOCK DIAGRAM
C N Y S H
C N Y S V
B
G
R
T U O
0 M W P
1 M W P
2 M W P
3 M W P
4 M W P
T U O S
K L C S
N I S
1 L C S
2 L C S
3 L C S
1 A D S
2 A D S
3 A D S
8 – A D 1
3 T I N
2 T I N
1 T I N
Fig. 5.1 Functional Block Diagram of M37151
Rev.1.00 Nov 01, 2002 page 4 of 136
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6. PERFORMANCE OVERVIEW
Table 6.1 Performance Overview
Parameter
Number of basic instructions
Instruction execution time
Functions
71
0.5 ms (the minimum instruction execution time, at 8 MHz oscillation fre-
quency)
Clock frequency
8 MHz (maximum)
Memory size
ROM M37151M6-XXXFP
M37151M8-XXXFP
24K bytes
32K bytes
M37151MA-XXXFP
M37151MC-XXXFP
40K bytes
48K bytes
M37151MF-XXXFP, M37151EFFP
60K bytes
RAM M37151M6-XXXFP
M37151M8-XXXFP
1024 bytes (ROM correction memory included)
1152 bytes (ROM correction memory included)
1472 bytes (ROM correction memory included)
2048 bytes (ROM correction memory included)
M37151MA-XXXFP, M37151MC-XXXFP
M37151MF-XXXFP, M37151EFFP
I/O
Input/Output
ports
P0
8-bit ✕ 1 (N-channel open-drain output structure, can be used as PWM
output pins, INT input pins, A-D input pin)
7-bit ✕ 1 (CMOS input/output structure, however, N-channel open-drain
output structure, when P11–P14 are used as multi-master I C-BUS inter-
P10–P16
P20–P27
I/O
I/O
2
face, can be used as A-D input pins, timer external clock input pins, multi-
2
master I C-BUS interface)
8-bit ✕ 1 (P2 is CMOS input/output structure, however, N-channel open-
drain output structure when P20 and 21 are used as serial output, can be
used as serial input/output pins, timer external clock input pins, A-D input
pins, INT input pin, sub-clock input/output pins)
P30, P31
2-bit ✕ 1 (CMOS input/output structure, however, N-channel open-drain output structure,
I/O
when used as multi-master I2C-BUS interface, can be used as multi-master I2C-BUS interface.)
P50, P51
P52–P55
2-bit ✕ 1(can be used as OSD input pins)
Input
4-bit ✕ 1(CMOS output structures, can be used as OSD output pins)
Output
Serial I/O
8-bit ✕ 1
2
Multi-master I C-BUS interface
A-D comparator
One (Three lines)
8 channels (7-bit resolution)
8-bit ✕ 5
PWM output circuit
Timers
8-bit ✕ 6
2 vectors
ROM correction function
128 levels (maximum)
<17 types>
Subroutine nesting
Interrupt
INT external interrupt ✕ 3, Internal timer interrupt ✕ 6, Serial I/O interrupt ✕
2
1, OSD interrupt ✕ 1, Multi-master I C-BUS interface interrupt ✕ 1, Data
slicer interrupt ✕✕1, f(XIN)/4096 interrupt ✕ 1, VSYNC interrupt ✕ 1, BRK
instruction interrupt ✕ 1, reset ✕ 1
Clock generating circuit
Data slicer
2 built-in circuits (externally connected to XCIN/OUT is a ceramic resonator
or a quartz-crystal oscillator)
Built-in
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Table 6.2 Performance Overview (Continued)
Parameter
Functions
Number of display characters
32 characters ✕ 2 lines
OSD function
Dot structure
CC mode: 16 ✕ 26 dots (character display area : 16 ✕✕20 dots)
OSD mode: 16 ✕✕20 dots
Kinds of characters
254 kinds
Kinds of character sizes
1 screen : 8
CC mode: 1 kinds
OSD mode: 8 kinds
Character font coloring
Display position
1 screen: 8 kinds (per character unit)
Horizontal: 128 levels, Vertical: 512 levels
5V ± 10%
Power source voltage
Power
dissipation
In high-speed
mode
OSD ON
Data slicer ON
165 mW typ. ( at oscillation frequency f(XIN) = 8 MHz, fOSC = 26 MHz)
OSD OFF Data slicer OFF
OSD OFF Data slicer OFF
82.5 mW typ. ( at oscillation frequency f(XIN) = 8 MHz)
In low-speed
mode
0.33 mW typ. ( at oscillation frequency f(XCIN) = 32 kHz, f(XIN) = stop)
In stop mode
0.055 mW ( maximum )
–10 °C to 70 °C
Operating temperature range
Device structure
CMOS silicon gate process
42-pin plastic molded SSOP
Package
Rev.1.00 Nov 01, 2002 page 6 of 136
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7. PIN DESCRIPTION
Table 7.1 PIN DESCRIPTION
Input/
Output
Pin
Name
Functions
VCC, VSS
Power source
CNVSS
Apply voltage of 5 V ± 10 % to (typical) VCC, and 0 V to VSS.
This is connected to VSS.
CNVSS
______
RESET
Reset input
Input
To enter the reset state, the reset input pin must be kept at a LOW for 2 ms or more (under
normal VCC conditions).
If more time is needed for the quartz-crystal oscillator to stabilize, this LOW condition should
be maintained for the required time.
XIN
Clock input
Input
This is the input pin for the main clock generating circuit. Built-in clock clock generation
circuit, when set
XOUT
Clock output
Output
to oscillation frequency, connect ceramic resonator or crystal frequency between XIN and
XOUT. When use external clock input, connect clock oscillation source to XIN pin, and open
XOUT pin.
P0
P0
0
/PWM0– I/O port P0
/PWM2,
I/O
Port P0 is an 8-bit I/O port with a direction register allowing each I/O bit to be individually
programmed as input or output. At reset, this port is set to input mode. The output structure
is N-channel open-drain output. (See note)
2
P03/PWM3/AD1,
P0
4
/PWM4/AD2, PWM output
Output
Input
Input
I/O
Output Pins P00 to P04 are also used as PWM output pins PWM0 to PWM4, respectively.
The output structure is N-channel open-drain output.
P05/AD3,
P0
6
/INT2/AD4, External interrupt
Pins P06 and P07 are also used as INT external interrupt input pins INT2 and INT1 respectively.
P07/INT1
input
Analog input
Pins P03, P04, P05 and P06 are also used as analog input pins AD1, AD2, AD3 and AD4,
respectively.
P10
/CLK CONT, I/O port P1
Port P1 is a 7-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output. (See note)
P11/SCL1,
P12/SCL2, Multi-master
I/O
Pins P11–P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master
I C-BUS interface is used. The output structure is N-channel open-drain output.
2
2
P13/SDA1
I C-BUS interface
,
P14/SDA2, Clock control
Output
Input
P10 pin is also used as Clock control output CLK CONT. The output structure is CMOS
output.
P16 pin is also used as timer external clock input pin TIM2.
P15
,
P16/AD8
/
TIM2 External clock
input for timer
Analog input
Input
I/O
P16 pin is also used as analog input pin AD8.
P20
/SCLK/AD5, I/O port P2
/AD6
Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output. (See note)
P21
/SOUT
,
P2
2
/SIN/AD7, Serial I/O synchronous
I/O
P20 pin is also used as serial I/O synchronous clock input/output pin SCLK. The output
structure is N-channel open-drain output.
clock input/output port
P23/TIM3,
P24/TIM2,
/INT3
P25
Serial I/O data
output
Output
P21 pin is also used as serial I/O data output pin SOUT. The output structure is open-drain
output.
,
P2
6
/
XCIN,
Serial I/O data input
Input
Input
P22 pin is also used as serial I/O data input pin SIN.
P27/XCOUT External clock
input for timer
Pins P23 and P24 are also used as timer external clock input pins TIM3 and TIM2
respectively.
Analog input
Input
Input
Pins P20–P22 are also used as analog input pins AD5, AD6 and AD7 respectively.
P26 pin is also used as sub-clock input pin XCIN.
Sub-clock input
Sub-clock output
External interrupt
input
Output
Input
P27 pin is also used as sub-clock output pin XCOUT. The output structure is CMOS output.
P25 pin is also used as INT external interrupt input pin INT3.
P30/SDA3 I/O port P3
P31/SCL3
I/O
I/O
Port P30,P31 is an 2-bit I/O port and has basically the same functions as port P0.
The output structure is CMOS output. (See note)
2
Multi-master
Pins P30,P31 are used as SDA3,SCL3 respectively, when multi-master I C-BUS
2
I C-BUS Interface
interface is used. The output structure is N-channel open-drain output.
Rev.1.00 Nov 01, 2002 page 7 of 136
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Table 7.2 PIN DESCRIPTION (continued)
Input/
Pin
Name
Functions
Output
Input
Input
Input
P50/HSYNC Input P5
Port P5 is a 2-bit input port.
P51/VSYNC Horizonta synchronous signal
Vertical synchronous signal
The P50 pin is also used as a horizontal synchronous signal input HSYNC for OSD.
The P51 pin is also used as a vertical synchronous signal input VSYNC for OSD.
P52/B,
Output P5
OSD output
output
output
Pins P52–P55 are a 4-bit output port. The output structure is CMOS output.
Pins P52–P55 are also used as OSD output pins R, G, B and OUT respectively. The output
structure is CMOS output.
P53/G,
P54/R,
P55/OUT
CVIN
VHOLD
HLF
I/O for data slicer
Input
Input
I/O
Input the composite video signal through a capacitor.
Connect a capacitor between VHOLD and Vss.
Connect a filter consisting of a capacitor and a resistor, between HLF and Vss.
Connect a capacitor between FILT and Vss.
FILT
Clock oscillation
filter
Input
Notes : Port Pi (i = 0 to 3) has the port Pi direction register which can be used to program each bit for input (“0”) or an output (“1”). The pins programmed as “1” in
the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are programmed as output pins, the output data are
written into the port latch and then output. When data is read from the output pins, the data of the port latch, not the output pin level, is read. This allows a
previously-output value to be read correctly even if the output LOW voltage has risen due to, for example, a directly-driven light emitting diode was directly
driven. The input pins are in the floating state, so the values of the pins can be read. When data is written into the input pin, it is written only into the port latch,
while the pin remains in the floating state.
✕✕✕✕LED drive ports 4 (P24–P27)
Rev.1.00 Nov 01, 2002 page 8 of 136
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Ports P00–P07
Direction register
Port latch
N-channel open-drain output
Ports P00–P07
Data bus
Note : Each port is also used as follows :
P00–P04 : PWM0–PWM4
P05: AD3
P06: INT2/AD4
P07: INT1
Ports P1, P2, P30, P31
Direction register
Port latch
CMOS output
Data bus
Ports P1, P2, P30, P31
Notes 1 : Each port is also used as follows :
P10 : CLKCONT
P11 : SCL1
P12 : SCL2
P20 : SCLK/AD5
P21 : SOUT/AD6
P22 : SIN/AD7
P23 : TIM3
P27 : XCOUT
P30 : SDA3
P31 : SCL3
P13 : SDA1
P14 : SDA2
P24 : TIM2
P16 : AD8/TIM2
P25 : INT3
P26 : XCIN
2: The output structure of ports P11–P14, P30–P31 is N-channel open-drain output when using as multi-master
2
I C-BUS interface (it is the same with P00–P07).
3: The output structure of ports P20 and P21 is N-channel open-drain output when using as serial output (it is the
same as P00–P07).
Fig. 7.1 I/O Pin Block Diagram (1)
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P50, P51
P52–P55
CMOS input
CMOS output
Ports P52–P55
Internal circuit
Ports P50, P51
Internal circuit
Note : Each pin is also used
as follows :
Note : Each pin is also used
as follows :
P52 : B
P50 : HSYNC
P51 : VSYNC
P53 : G
P54 : R
P55 : OUT
Fig. 7.2 I/O Pin Block Diagram (2)
Rev.1.00 Nov 01, 2002 page 10 of 136
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8. FUNCTIONAL DESCRIPTION
8.1.1 CPU Mode Register
8.1 CENTRAL PROCESSING UNIT (CPU)
This microcomputer uses the standard 740 Family instruction set.
Refer to the table of 740 Family addressing modes and machine
instructions or the SERIES 740 <Software> User’s Manual for de-
tails on the instruction set.
The CPU mode register includes the stack page selection bit and
internal system clock selection bit. The CPU mode register is allo-
cated at address 00FB16.
Availability of 740 Family instructions is as follows:
The FST and SLW instructions cannot be used.
The MUL, DIV, WIT and STP instructions can be used.
CPU Mode Register
b7b6 b5b4b3 b2b1b0
1 1
0 0
CPU mode register (CM) [Address 00FB16
]
Functions
After reset
B
Name
R W
R W
b1 b0
Processor mode bits
(CM0, CM1)
0, 1
0
0 0: Single-chip mode
0 1:
1 0:
1 1:
Not available
0: 0 page
1: 1 page
Stack page selection
bit (CM2) (See note)
2
1
R W
Fix these bits to “1.”
1
1
R W
R W
3, 4
5
0: LOW drive
1: HIGH drive
X
COUT drivability
selection bit (CM5)
6
7
0
0
R W
R W
0: Oscillating
1: Stopped
Main Clock (XIN–XOUT
stop bit (CM6)
)
Internal system clock 0: XIN selected
(high-speed mode)
1: XCIN–XCOUT selected
(low-speed mode)
selection bit
(CM7)
Note. This bit is set to “1” after the reset release.
Fig. 8.1.1 CPU Mode Register
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8.2 MEMORY
8.2.6 Interrupt Vector Area
8.2.1 Special Function Register (SFR) Area
The special function register (SFR) area in the zero page contains
control registers such as I/O ports and timers.
The interrupt vector area contains reset and interrupt vectors.
8.2.7 Zero Page
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
8.2.2 RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
8.2.8 Special Page
8.2.3 ROM
The special page addressing mode can be used to specify memory
addresses in the special page area. Access to this area with only 2
bytes is possible in the special page addressing mode.
ROM is used for storing user programs as well as the interrupt vector
area.
8.2.4 OSD RAM
RAM for display is used for specifying the character codes and col-
8.2.9 ROM Correction Memory (RAM)
This is used as the program area for ROM correction.
ors to display.
8.2.5 OSD ROM
ROM for display is used for storing character data.
ꢀ M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
000016
1000016
M37151M6-
XXXFP
RAM
M37151MF-XXXFP,
M37151EFFP
RAM
Zero page
00BF16
00C016
00FF16
010016
SFR1 area
(1024 bytes)
(2048 bytes)
M37151MB-XXXFP
01FF
02001166
RAM
Not used
SFR2 area
Not used
(1152 bytes)
020F16
M37151MA/MC-
030016
032016
XXXFP
RAM
ROM correction function
Vector 1: address 030016
Vector 2: address 032016
053F16
05BF16
06FF16
(1472 bytes)
Not used
Not used
OSD RAM
(128 bytes)
OSD ROM
1140016
080016
087F16
(10K bytes)
13BFF16
(See note)
090016
0B3F16
M37151MF-XXXFP,
M37151EFFP
ROM
(60K bytes)
Not used
Not used
M37151MC-XXXFP
ROM
(48K bytes)
M37151MA-XXXFP
100016
ROM
(40K bytes)
400016
600016
800016
M37151M8-XXXFP
A00016
ROM
(32K bytes)
FF0016
FFDE16
1FFFF16
M37151M6-XXXFP
Special page
ROM
(24K bytes)
Interrupt vector area
FFFF16
Fig. 8.2.1 Memory Map (M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP)
Rev.1.00 Nov 01, 2002 page 12 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
ꢀꢀSFR1 Area (addresses C016 to DF16
)
<Bit allocation>
<State immediately after reset>
:
:
0
1
?
: “0” immediately after reset
: “1” immediately after reset
Function bit
Name
: No function bit
: Indeterminate immediately
after reset
0
1
: Fix this bit to “0”
(do not write “1”)
: Fix this bit to “1”
(do not write “0”)
Bit allocation
State immediately after reset
Address Register
b7
b0 b7
b0
?
C016
C116
C216
C316
C416
C516
C616
C716
C816
C916
CA16
CB16
CC16
CD16
CE16
CF16
D016
D116
D216
D316
D416
D516
D616
D716
D816
D916
DA16
DB16
DC16
DD16
DE16
DF16
Port P0(P0)
0016
Port P0 direction register (D0)
0
0
?
?
0
0
1
?
0
?
?
0
?
0
?
1
Port P1(P1)
0
0
Port P1 direction register (D1)
Port P2(P2)
?
0016
Port P2 direction register (D2)
Port P3(P3)
BSEL21 BSEL20
P31 P30
0
0
?
0
0
0
0
0
0
0
?
0
?
0
T2SC T3SC
OUTS P31D P30D
0
0
1
0016
?
Port P3 direction register (D3)
0
0
0
0
0
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
1
0
0
?
0
?
Port P5(P5)
1
PF5 PF4 PF3 PF2
0
0
OSD port control register (PF)
Timer return set register (TMS)
TMS
0
0016
0016
1
0
0
0
0
0
0
0
0
CC10
Clock control register 1 (CC1)
Caption data register 3 (CD3)
Caption data register 4 (CD4)
OSD control register (OC)
CDL27 CDL26 CDL25 CDL24 CDL23 CDL22 CDL21 CDL20
?
?
CDH27 CDH26 CDH25 CDH24 CDH23 CDH22 CDH21 CDH20
OC7
0
0
OC4 OC3 OC2 OC1 OC0
0016
0016
?
HP6 HP5 HP4 HP3 HP2 HP1 HP0
Horizontal position register (HP)
Block control register 1(BC1)
Block control register 2(BC2)
Vertical position register 1(VP1)
Vertical position register 2(VP2)
BC17 BC16 BC15 BC14 BC13 BC12 BC11 BC10
BC27 BC26 BC25 BC24 BC23 BC22 BC21 BC20
VP17 VP16 VP15 VP14 VP13 VP12 VP11 VP10
?
?
VP27 VP26 VP25 VP24 VP23 VP22 VP21 VP20
WN17 WN16 WN15 WN14 WN13 WN12 WN11 WN10
WN27 WN26 WN25 WN24 WN23 WN22 WN21 WN20
?
?
Window register 1(WN1)
Window register 2(WN2)
I/O polarity control register (PC)
Raster color register (RC)
?
PC6 PC5
PC3 PC2 PC1 PC0
RC3 RC2 RC1 RC0
4016
0016
?
0
0
0
RC7
0
0
0
0
0
OC21 OC20
0
0
0
0
?
0
0
0
0
OSD control register 2(OC2)
INT3 INT2 INT1
0016
0016
0016
0016
Interrupt input polarity control register (RE)
0016
0016
0016
Fig. 8.2.2 Memory Map of Special Function Register 1 (SFR1) (1)
Rev.1.00 Nov 01, 2002 page 13 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
ꢀ SFR1 Area (addresses E016 to FF16
)
<Bit allocation>
:
<State immediately after reset>
: “0” immediately after reset
: “1” immediately after reset
0
1
?
Function bit
Name
:
: No function bit
: Indeterminate immediately
after reset
0
1
: Fix this bit to “0”
(do not write “1”)
: Fix this bit to “1”
(do not write “0”)
Bit allocation
State immediately after reset
Address
Register
b7
0
b0 b7
b0
DSC12 DSC11 DSC10
Data slicer control register 1 (DSC1)
Data slicer control register 2 (DSC2)
Caption data register 1 (CD1)
Caption data register 2 (CD2)
Clock run-in detect register (CRD)
Data clock position register (DPS)
Caption position register (CPS)
Data slicer test register 2
0016
E016
E116
E216
E316
1
0
1
0
0
DSC25 DSC24 DSC23
DSC20
1
?
0
?
0
?
?
0
?
CDL17 CDL16 CDL15 CDL14 CDL13 CDL12 CDL11 CDL10
CDH17 CDH16 CDH15 CDH14 CDH13 CDH12 CDH11 CDH10
CRD7 CRD6 CRD5 CRD4 CRD3
0016
0016
0016
0916
E416
E516
E616
DPS7 DPS6 DPS5 DPS4 DPS3
1
0
0
CPS7 CPS6 CPS5 CPS4 CPS3 CPS2 CPS1 CPS0
0
0
?
0
0
0
0
0
0
0016
0016
0016
E716
E816
E916
EA16
EB16
Data slicer test register 1
HC5 HC4 HC3 HC2 HC1 HC0
Synchronous signal counter register (HC)
Serial I/O register (SIO)
?
SM6 SM5
SM3 SM2 SM1 SM0
Serial I/O mode register (SM)
0016
?
0
0
ADC14
ADC12 ADC11 ADC10
0
0
0
0
EC16 A-D control register 1 (AD1)
0
0
ADC26 ADC25 ADC24 ADC23 ADC22 ADC21 ADC20
0016
0716
A-D control register 2 (AD2)
Timer 5 (T5)
ED16
EE16
EF16
F016
Timer 6 (T6)
FF16
FF16
0716
FF16
0716
Timer 1 (T1)
Timer 2 (T2)
F116
F216
F316
Timer 3 (T3)
Timer 4 (T4)
TM17 TM16 TM15 TM14 TM13 TM12 TM11 TM10
TM27 TM26 TM25 TM24 TM23 TM22 TM21 TM20
0016
F416 Timer mode register 1 (TM1)
Timer mode register 2 (TM2)
2
F516
0016
?
0016
D7 D6 D5 D4 D3 D2 D1 D0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
F616 I C data shift register (S0)
2
F716
F816
I C address register (S0D)
2
MST TRX BB PIN AL AAS AD0 LRB
10BIT
0
0
0
1
0
0
0
?
I C status register (S1)
BSEL1 BSEL0
ALS ESO BC2 BC1 BC0
CCR4 CCR3 CCR2 CCR1 CCR0
CM2
2
0016
SAD
FAST
MODE
I C control register (S1D)
F916
FA16
FB16
FC16
FD16
FE16
FF16
ACK
ACK
2
0016
3C16
0016
0016
0016
0016
BIT
I C clock control register (S2)
CM7 CM6 CM5
1
1
0
0
CPU mode register (CPUM)
VSCR OSDR TM4R TM3R TM2R TM1R
IN3R
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
TM56R
DSR
IN1R
IICR IN2R CKR S1R
0
VSCE OSDE TM4E TM3E TM2E TM1E
IICE IN2E CKE S1E DSE IN1E
IN3E
TM56C TM56E
Fig. 8.2.3 Memory Map of Special Function Register 1 (SFR1) (2)
Rev.1.00 Nov 01, 2002 page 14 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
ꢀSFR2 Area (addresses 20016 to 20F16
)
<Bit allocation>
<State immediately after reset>
:
0
1
?
: “0” immediately after reset
: “1” immediately after reset
Function bit
Name
:
: No function bit
: Indeterminate immediately
after reset
0
1
: Fix this bit to “0”
(do not write “1”)
: Fix this bit to “1”
(do not write “0”)
State immediately after reset
Register
Bit allocation
Address
b0
b0
b7
b7
?
?
?
?
?
?
?
?
20016
20116
20216
20316
PWM0 register (PWM0)
PWM1 register (PWM1)
PWM2 register (PWM2)
PWM3 register (PWM3)
20416 PWM4 register (PWM4)
20516
20616
0016
0016
PM13
20716
20816
20916
PWM mode register 1 (PM1)
PWM mode register 2 (PM2)
PM10
?
?
?
?
0
?
?
0
PM24 PM23 PM22 PM21 PM20
0
0
0
0016
0016
0016
0016
0016
20A16
20B16
20C16
ROM correction address 1 (high-order)
ROM correction address 1 (low-order)
ROM correction address 2 (high-order)
20D16
20E16
ROM correction address 2 (low-order)
ROM correction enable register (RCR)
RC1 RC0
0016
?
20F16
210
0
0
0
0
1
1
1
0
Clock frequency set register (CFS)
Clock control register 2(CC2)
211
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0016
0016
CC37
CC35
212 Clock control register 3(CC3)
Fig. 8.2.4 Memory Map of Special Function Register 2 (SFR2)
Rev.1.00 Nov 01, 2002 page 15 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
<
State immediately after reset>
<
Bit allocation
:
>
: “0” immediately after reset
: “1” immediately after reset
0
1
?
Function bit
:
:
Name
No function bit
: Indeterminate immediately
after reset
: Fix to this bit to “0”
(do not write to “1”)
0
1
: Fix to this bit to “1”
(do not write to “0”)
Register
Bit allocation
State immediately after reset
b0
b0
b7
N
b7
Processor status register (PS)
V
T
B
D
I
Z
C
?
?
?
?
?
1
?
?
Program counter (PC
Program counter (PC
H)
Contents of address FFFF16
Contents of address FFFE16
L
)
Fig. 8.2.5 Internal State of Processor Status Register and Program Counter at Reset
Rev.1.00 Nov 01, 2002 page 16 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.3 INTERRUPTS
8.3.1 Interrupt Causes
Interrupts can be caused by 17 different sources consisting of 4 ex-
ternal, 11 internal, 1 software, and reset. Interrupts are vectored in-
terrupts with priorities as shown in Table 8.3.1. Reset is also included
in the table because its operation is similar to an interrupt.
When an interrupt is accepted,
(1) VSYNC, OSD interrupts
The VSYNC interrupt is an interrupt request synchronized with
the vertical sync signal.
The OSD interrupt occurs after character block display to the
CRT is completed.
ꢀ The contents of the program counter and processor status regis-
ter are automatically stored into the stack.
(2) INT1 to INT3 external interrupts
ꢀ The interrupt disable flag I is set to “1” and the corresponding
interrupt request bit is set to “0.”
The INT1 to INT3 interrupts are external interrupt inputs, the sys-
tem detects that the level of a pin changes from LOW to HIGH or
from HIGH to LOW, and generates an interrupt request. The in-
put active edge can be selected by bits 3 to 5 of the interrupt
input polarity register (address 00DC16) : when this bit is “0,” a
change from LOW to HIGH is detected; when it is “1,” a change
from HIGH to LOW is detected. Note that both bits are cleared to
“0” at reset.
ꢀ The jump destination address stored in the vector address enters
the program counter.
Other interrupts are disabled when the interrupt disable flag is set to
“1.”
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits are
in interrupt request registers 1 and 2 and the interrupt enable bits are
in interrupt control registers 1 and 2. Figures 8.3.2 to 8.3.6 show the
interrupt-related registers.
(3) Timers 1 to 4 interrupts
An interrupt is generated by an overflow of timers 1 to 4.
Interrupts other than the BRK instruction interrupt and reset are ac-
cepted when the interrupt enable bit is “1,” interrupt request bit is “1,”
and the interrupt disable flag is “0.” The interrupt request bit can be
set to “0” by a program, but not set to “1.” The interrupt enable bit can
be set to “0” and “1” by a program.
Reset is treated as a non-maskable interrupt with the highest priority.
Figure 8.3.1 shows interrupt control.
Table 8.3.1 Interrupt Vector Addresses and Priority
Priority
Interrupt Source
Vector Addresses
Remarks
1
2
Reset
FFFF16, FFFE16
FFFD16, FFFC16
FFFB16, FFFA16
FFF916, FFF816
FFF716, FFF616
FFF516, FFF416
FFF316, FFF216
FFF116, FFF016
FFEF16, FFEE16
FFED16, FFEC16
FFEB16, FFEA16
FFE916, FFE816
FFE716, FFE616
FFE516, FFE416
FFE316, FFE216
FFDF16, FFDE16
Non-maskable
OSD interrupt
3
INT1 external interrupt
Data slicer interrupt
Serial I/O interrupt
Timer 4 interrupt
Active edge selectable
4
5
6
7
f(XIN)/4096 interrupt
VSYNC interrupt
8
9
Timer 3 interrupt
10
11
12
13
14
15
16
Timer 2 interrupt
Timer 1 interrupt
INT3 external interrupt
INT2 external interrupt
Active edge selectable
Active edge selectable
2
Multi-master I C-BUS interface interrupt
Timer 5 • 6 interrupt
Source switch by software (see note)
Non-maskable
BRK instruction interrupt
Note: Switching a source during a program causes an unnecessary interrupt. Therefore, set a source at initializing of program.
Rev.1.00 Nov 01, 2002 page 17 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
(4) Serial I/O interrupt
This is an interrupt request from the clock synchronous serial I/O
function.
Interrupt request bit
Interrupt enable bit
(5) f(XIN)/4096 interrupt
The f (XIN)/4096 interrupt occurs regularly with a f(XIN)/4096 pe-
riod. Set bit 0 of the PWM mode register 1 to “0.”
Interrupt disable flag I
(6) Data slicer interrupt
An interrupt occurs when slicing data is completed.
Interrupt
request
BRK instruction
Reset
2
(7) Multi-master I C-BUS interface interrupt
2
This is an interrupt request related to the multi-master I C-BUS
interface.
(8) Timer 5 • 6 interrupt
Fig. 8.3.1 Interrupt Control
An interrupt is generated by an overflow of timer 5 or 6. Their
priorities are same, and can be switched by software.
(9) BRK instruction interrupt
This software interrupt has the least significant priority. It does
not have a corresponding interrupt enable bit, and it is not af-
fected by the interrupt disable flag I (non-maskable).
Rev.1.00 Nov 01, 2002 page 18 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Interrupt Request Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address 00FC16]
B
0
Name
Functions
Afrer reset R W
0
0 : No interrupt request issued
1 : Interrupt request issued
ꢀ
R
Timer 1 interrupt request
bit (TM1R)
1
2
3
4
5
6
7
ꢀ
Timer 2 interrupt request 0 : No interrupt request issued
bit (TM2R) 1 : Interrupt request issued
0
0
0
R
Timer 3 interrupt request 0 : No interrupt request issued
bit (TM3R) 1 : Interrupt request issued
ꢀ
ꢀ
ꢀ
R
R
R
Timer 4 interrupt request 0 : No interrupt request issued
bit (TM4R)
1 : Interrupt request issued
OSD interrupt
request bit (OSDR)
0 : No interrupt request issued
1 : Interrupt request issued
0
0
0
0
VSYNC interrupt request
bit (VSCR)
0 : No interrupt request issued
1 : Interrupt request issued
ꢀ
ꢀ
R
R
INT3 external interrupt
request bit (IN3R)
0 : No interrupt request issued
1 : Interrupt request issued
R —
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
ꢀ: “0” can be set by software, but “1” cannot be set.
Fig. 8.3.2 Interrupt Request Register 1
Interrupt Request Register 2
b7b6 b5b4b3 b2b1b0
0
Interrupt request register 2 (IREQ2) [Address 00FD16
]
After reset
0
B
0
Name
Functions
R W
INT1 external interrupt
request bit (IN1R)
Data slicer interrupt
request bit (DSR)
Serial I/O interrupt
request bit (SIR)
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
ꢀ
ꢀ
ꢀ
R
R
R
R
1
2
3
4
0
0
0
ꢀ
f(XIN
)/4096 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
request bit (CKR)
INT2 external interrupt
request bit (IN2R)
ꢀ
ꢀ
0
0
R
R
2C-BUS
0 : No interrupt request issued
Multi-master I
5
6
interrupt request bit (IICR) 1 : Interrupt request issued
Timer 5 • 6 interrupt
request bit (TM56R)
ꢀ
0 : No interrupt request issued
1 : Interrupt request issued
0
0
R
7
Fix this bit to “0.”
R W
ꢀ: “0” can be set by software, but “1” cannot be set.
Fig. 8.3.3 Interrupt Request Register 2
Rev.1.00 Nov 01, 2002 page 19 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Interrupt Control Register 1
b7b6 b5b4b3 b2b1b0
Interrupt control register 1 (ICON1) [Address 00FE16]
Name
After reset
0
B
0
Functions
R W
R W
Timer 1 interrupt
enable bit (TM1E)
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
1
2
3
4
Timer 2 interrupt
enable bit (TM2E)
Timer 3 interrupt
enable bit (TM3E)
Timer 4 interrupt
enable bit (TM4E)
R W
R W
R W
R W
0
0
0
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
OSD interrupt enable bit
(OSDE)
VSYNC interrupt enable 0 : Interrupt disabled
5
6
7
R W
R W
R —
0
0
1 : Interrupt enabled
bit (VSCE)
0 : Interrupt disabled
1 : Interrupt enabled
INT3 external interrupt
enable bit (IN3E)
Nothing is assigned. This bit is a write disable
bit. When this bit is read out, the value is “0.”
0
Fig. 8.3.4 Interrupt Control Register 1
Interrupt Control Register 2
b7b6 b5b4b3 b2b1b0
Interrupt control register 2 (ICON2) [Address 00FF16
]
After reset
0
B
0
Name
Functions
R W
R W
INT1 external interrupt
enable bit (IN1E)
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Data slicer interrupt
enable bit (DSE)
1
2
3
4
0
R W
Serial I/O interrupt
enable bit (SIE)
0
0
0
R W
R W
R W
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
f(XIN
)/4096 interrupt
enable bit (CKE)
INT2 external interrupt
enable bit (IN2E)
I2
Multi-master C-BUS
5
0 : Interrupt disabled
1 : Interrupt enabled
0
R W
interface interrupt enable
bit (IICE)
0
0
R W
R W
Timer 5 • 6 interrupt
enable bit (TM56E
Timer 5 • 6 interrupt
switch bit (TM56C)
0 : Interrupt disabled
1 : Interrupt enabled
6
7
)
0 : Timer 5
1 : Timer 6
Fig. 8.3.5 Interrupt Control Register 2
Rev.1.00 Nov 01, 2002 page 20 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Interrupt Input Polarity Register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt input polarity register (RE) [Address 00DC16
]
B
0
Name
Functions
After reset
0
R
R
W
W
INT1 polarity switch bit
(INT1)
0 : Positive polarity
1 : Negative polarity
0
0
0
R
R
R
W
W
—
1
2
INT2 polarity switch bit
(INT2)
0 : Positive polarity
1 : Negative polarity
INT3 polarity switch bit
(INT3)
0 : Positive polarity
1 : Negative polarity
3
to
7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
Fig. 8.3.6 Interrupt Input Polarity Register
Rev.1.00 Nov 01, 2002 page 21 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.4 TIMERS
8.4.5 Timer 5
This microcomputer has 6 timers: timer 1, timer 2, timer 3, timer 4,
timer 5, and timer 6. All timers are 8-bit timers with the 8-bit timer
latch. The timer block diagram is shown in Figure 8.4.3.
All of the timers count down and their divide ratio is 1/(n+1), where n
is the value of timer latch. By writing a count value to the correspond-
ing timer latch (addresses 00F016 to 00F316 : timers 1 to 4, addresses
00EE16 and 00EF16 : timers 5 and 6), the value is also set to a timer,
simultaneously.
Timer 5 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• Timer 2 overflow signal
• Timer 4 overflow signal
The count source of timer 3 is selected by setting bit 6 of timer mode
register 1 (address 00F416) and bit 7 of the timer mode register 2
(address 00F516). When overflow of timer 2 or 4 is a count source
for timer 5, either timer 2 or 4 functions as an 8-bit prescaler. Either
f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Timer 5 interrupt request occurs at timer 5 overflow.
The count value is decremented by 1. The timer interrupt request bit
is set to “1” by a timer overflow at the next count pulse, after the
count value reaches “0016”.
8.4.6 Timer 6
8.4.1 Timer 1
Timer 1 can select one of the following count sources:
Timer 6 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• f(XIN)/16 or f(XCIN)/16
• Timer 5 overflow signal
• f(XIN)/4096 or f(XCIN)/4096
The count source of timer 6 is selected by setting bit 7 of the timer
mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected
by bit 7 of the CPU mode register. When timer 5 overflow signal is a
count source for timer 6, the timer 5 functions as an 8-bit prescaler.
Timer 6 interrupt request occurs at timer 6 overflow.
• External clock from the TIM2 pin
The count source of timer 1 is selected by setting bits 5 and 0 of
timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register.
Timer 1 interrupt request occurs at timer 1 overflow.
At reset, timers 3 and 4 are connected by hardware and “FF16” is
✽
8.4.2 Timer 2
automatically set in timer 3; “0716” in timer 4. The f(XIN) /16 is se-
Timer 2 can select one of the following count sources:
lected as the timer 3 count source. The internal reset is released by
timer 4 overflow in this state and the internal clock is connected.
At execution of the STP instruction, timers 3 and 4 are connected by
hardware and “FF16” is automatically set in timer 3; “0716” in timer 4.
• f(XIN)/16 or f(XCIN)/16
• Timer 1 overflow signal
• External clock from the TIM2 pin
✽
The count source of timer 2 is selected by setting bits 4 and 1 of
timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register. When timer 1 overflow
signal is a count source for the timer 2, the timer 1 functions as an 8-
bit prescaler.
However, the f(XIN) /16 is not selected as the timer 3 count source.
So set both bit 0 of timer mode register 2 (address 00F516) and bit 6
at address 00C716 to “0” before the execution of the STP instruction
✽
(f(XIN) /16 is selected as timer 3 count source). The internal STP
state is released by timer 4 overflow in this state and the internal
clock is connected.
Timer 2 interrupt request occurs at timer 2 overflow.
As a result of the above procedure, the program can start under a
stable clock.
8.4.3 Timer 3
Timer 3 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
✽: When CPU Mode Register bit 7 (CM7) = 1, f(XIN) becomes f(XCIN).
• f(XCIN)
• External clock from the TIM3 pin
The timer-related registers is shown in Figures 8.4.1 and 8.4.2.
The count source of timer 3 is selected by setting bit 0 of timer mode
register 2 (address 00F516) and bit 6 at address 00C716. Either f(XIN)
or f(XCIN) is selected by bit 7 of the CPU mode register.
Timer 3 interrupt request occurs at timer 3 overflow.
The input path for the TIM2 pin can be selected between ports P16 or
P24. Use Port P3 Direction Register (address 00C716) bit 7 to select
either port.
8.4.4 Timer 4
Timer 4 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• f(XIN)/2 or f(XCIN)/2
• f(XCIN)
The count source of timer 3 is selected by setting bits 1 and 4 of the
timer mode register 2 (address 00F516). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register. When timer 3 overflow
signal is a count source for the timer 4, the timer 3 functions as an 8-
bit prescaler.
Timer 4 interrupt request occurs at timer 4 overflow.
Rev.1.00 Nov 01, 2002 page 22 of 136
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Timer Mode Register 1
b7b6 b5b4b3 b2b1b0
Timer mode register 1 (TM1) [Address 00F4 16
]
After reset
B
0
Name
Functions
R W
R W
0: f(XIN)/16 or f(XCIN)/16 (See note)
1: Count source selected by bit 5 of TM1
Timer 1 count source
selection bit 1 (TM10)
0
0: Count source selected by bit 4 of TM1
1: External clock from TIM2 pin
0
R W
1
Timer 2 count source
selection bit 1 (TM11)
Timer 1 count
stop bit (TM12)
2
3
4
0: Count start
1: Count stop
0
0
0
R W
R W
R W
Timer 2 count stop
bit (TM13)
0: Count start
1: Count stop
Timer 2 count source
selection bit 2
(TM14)
0: f(XIN)/16 or f(XCIN)/16 (See note)
1: Timer 1 overflow
5
Timer 1 count source
selection bit 2 (TM15)
0: f(XIN)/4096 or f(XCIN)/4096 (See note)
1: External clock from TIM2 pin
0
R W
6
7
Timer 5 count source
selection bit 2 (TM16)
0: Timer 2 overflow
1: Timer 4 overflow
0
0
R W
R W
Timer 6 internal count 0: f(XIN)/16 or f(XCIN)/16 (See note)
source selection bit
(TM17)
1: Timer 5 overflow
Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Fig. 8.4.1 Timer Mode Register 1
Timer Mode Register 2
b7b6 b5b4b3 b2b1b0
Timer mode register 2 (TM2) [Address 00F516
]
After reset
0
B
0
Name
Functions
R W
R W
Timer 3 count source
selection bit (TM20)
(b6 at address 00C716
)
b0
0
1
0
1
0 : f(XIN)/16 or f(XCIN)/16 (See note)
0 : f(XCIN
)
1 :
1 :
External clock from TIM3 pin
b4 b1
1, 4
Timer 4 count source
selection bits
(TM21, TM24)
0
R W
0
0
1
1
0 : Timer 3 overflow signal
1 : f(XIN)/16 or f(XCIN)/16 (See note)
0 : f(XIN)/2 or f(XCIN)/2 (See note)
1 : f(XCIN
)
Timer 3 count
stop bit (TM22)
2
3
0: Count start
1: Count stop
0
0
R W
R W
Timer 4 count stop bit
(TM23)
0: Count start
1: Count stop
Timer 5 count stop bit
(TM25)
5
6
0: Count start
1: Count stop
0
0
R W
R W
Timer 6 count stop bit
(TM26)
0: Count start
1: Count stop
Timer 5 count source
selection bit 1
(TM27)
7
0: f(XIN)/16 or f(XCIN)/16 (See note)
1: Count source selected by bit 6
of TM1
0
R W
Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Fig. 8.4.2 Timer Mode Register 2
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Port P3 direction register
b7 b6 b5 b4 b3 b2 b1 b0
0
Port P3 direction register (D3) [Address 00C716
]
B
0
Name
Functions
After reset
0
R
R
W
W
0 : Port P3
0
0
input
Port P3 direction register
(See note 1)
1 : Port P3
output
1
0 : Port P3
1
1
input
0
0
R
R
W
W
1 : Port P3
output
Output amplitude level selection bit 0 : 2 value output
(See note 2)
2
3
(OUTS)
1 : 3 value output
Fix this bit to "0."
0
0
W
–
R
R
R
4, 5
6
Nothing is assigned fix these bits
When this bit are read out, the value are "0."
Timer 3 (T3SC)
0
0
W
W
Refer to explanation of a timer
Timer 2 (T2SC)
0 : P2
1 : P1
4
6
input
input
7
R
Notes 1: When using the port as the I2C-BUS interface, set the Port P3 Direction Register to 1.
2: Use the Clock Control Register 3 (address 021216) bit 5 to select the binary
output level of OUT.
Fig. 8.4.3 Port P3 direction register
Timer return setting register
b7 b6 b5 b4 b3 b2 b1 b0
1
1
0
0
0
0
0
Timer return setting register (TMS) [Address 00CC16
]
B
Name
Functions
After reset
R
W
0 to
4
Fix these bits to "0."
0
R W
Fix these bits to "1."
0
0
R W
R W
5, 6
7
STOP mode return selection bit
(TMS)
0: Timer Count "07FF16"
1: Timer Count Variable
Fig. 8.4.4 Timer return setting register
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Data bus
8
XCIN
CM7
TM15
Timer 1 latch (8)
8
1/4096
1/2
Timer 1
interrupt request
XIN
1/8
Timer 1 (8)
TM10
TM14
TM12
8
8
Timer 2 latch (8)
8
Timer 2
interrupt request
TIM2
Timer 2 (8)
TM11
TM13
8
8
Reset
STP instruction
FF16
T3SC
Timer 3 latch (8)
8
Timer 3
interrupt request
Timer 3 (8)
TIM3
TM20
TM22
8
8
0716
TM21
Timer 4 latch (8)
8
Timer 4
interrupt request
Timer 4 (8)
TM21
TM24
TM23
8
8
TM16
Timer 5 latch (8)
8
Selection gate: Connected to
black side at
reset
Timer 5
interrupt request
Timer 5 (8)
TM27
TM25
TM1 : Timer mode register 1
TM2 : Timer mode register 2
T3SC : Timer 3 count source
8
8
switch bit (address 00C716
)
CM : CPU mode register
Timer 6 latch (8)
8
Timer 6
interrupt request
Timer 6 (8)
8
TM17
TM26
Notes 1: HIGH pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more.
2: When the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal.
3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.
Fig. 8.4.5 Timer Block Diagram
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8.5 SERIAL I/O
The operation of the serial I/O is described below. The operation of
the serial I/O differs depending on the clock source; external clock or
internal clock.
This microcomputer has a built-in serial I/O which can either transmit
or receive 8-bit data serially in the clock synchronous mode.
The serial I/O block diagram is shown in Figure 8.5.1. The synchro-
nous clock I/O pin (SCLK), and data output pin (SOUT) also function
as port P4, data input pin (SIN) also functions as port P20–P22.
Bit 3 of the serial I/O mode register (address 00EB16) selects whether
the synchronous clock is supplied internally or externally (from the
SCLK pin). When an internal clock is selected, bits 1 and 0 select
whether f(XIN) or f(XCIN) is divided by 8, 16, 32, or 64. To use the SIN
pin for serial I/O, set the corresponding bit of the port P2 direction
register (address 00C516) to “0.”
XCIN
1/2
Data bus
XIN
Frequency divider
1/2 1/4 1/8 1/16
1/2
1/2
CM7
SM1
Selection gate: Connect to
black side at
reset.
SM2
SM0
Synchronous
circuit
S
CM : CPU mode register
SM : Serial I/O mode register
P20
Latch
SM3
Serial I/O
interrupt request
S
CLK
Serial I/O counter (8)
MSB
P21
Latch
SM3
SM5 : LSB
S
OUT
(See note)
SIN
Serial I/O shift register (8)
SM6
8
Note : When the data is set in the serial I/O register (address 00EA16), the register functions as the serial I/O shift register.
Fig. 8.5.1 Serial I/O Block Diagram
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Internal clock : The serial I/O counter is set to “7” during the write
cycle into the serial I/O register (address 00EA16), and the transfer
clock goes HIGH forcibly. At each falling edge of the transfer clock
after the write cycle, serial data is output from the SOUT pin. Transfer
direction can be selected by bit 5 of the serial I/O mode register. At
each rising edge of the transfer clock, data is input from the SIN pin
and data in the serial I/O register is shifted 1 bit.
External clock : The an external clock is selected as the clock source,
the interrupt request is set to “1” after the transfer clock has been
counted 8 counts. However, transfer operation does not stop, so the
clock should be controlled externally. Use the external clock of 1 MHz
or less with a duty cycle of 50%.
The serial I/O timing is shown in Figure 8.5.2. When using an exter-
nal clock for transfer, the external clock must be held at HIGH for
initializing the serial I/O counter. When switching between an inter-
nal clock and an external clock, do not switch during transfer. Also,
be sure to initialize the serial I/O counter after switching.
After the transfer clock has counted 8 times, the serial I/O counter
becomes “0” and the transfer clock stops at HIGH. At this time the
interrupt request bit is set to “1.”
Notes 1: On programming, note that the serial I/O counter is set by writing to
the serial I/O register with the bit managing instructions, such as SEB
and CLB.
2: When an external clock is used as the synchronous clock, write trans-
mit data to the serial I/O register when the transfer clock input level is
HIGH.
Synchronous clock
Transfer clock
Serial I/O register
write signal
(Note)
Serial I/O output
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D7
S
OUT
Serial I/O input
S
IN
Interrupt request bit is set to “1”
Note : When an internal clock is selected, the SOUT pin is at high-impedance after transfer is completed.
Fig. 8.5.2 Serial I/O Timing (for LSB first)
Rev.1.00 Nov 01, 2002 page 27 of 136
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Serial I/O Mode Register
b7b6 b5b4b3 b2b1b0
0
0
Serial I/O mode register (SM) [Address 00EB16
]
After reset
B
Functions
Name
R W
R W
0
b1 b0
0, 1
Internal synchronous
clock selection bits
(SM0, SM1)
0 0: f(XIN)/8 or f(XCIN)/8
0 1: f(XIN)/16 or f(XCIN)/16
1 0: f(XIN)/32 or f(XCIN)/32
1 1: f(XIN)/64 or f(XCIN)/64
0
0
R W
R W
2
3
0: External clock
1: Internal clock
Synchronous clock
selection bit (SM2)
0: P20, P21
Port function
1: SCLK, SOUT
selection bit (SM3)
0
0
R W
R W
Fix this bit to “0.”
4
5
6
7
0: LSB first
1: MSB first
Transfer direction
selection bit (SM5)
0: Input signal from SIN pin
1: Input signal from SOUT pin
Transfer clock input
pin selection bit (SM6)
0
0
R W
R W
Fix this bit to “0.”
Fig. 8.5.3 Serial I/O Mode Register
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2
2
8.6 MULTI-MASTER I C-BUS INTERFACE
Table 8.6.1 Multi-master I C-BUS Interface Functions
2
The multi-master I C-BUS interface is a serial communications cir-
Item
Function
2
cuit, conforming to the Philips I C-BUS data transfer format. This
2
In conformity with Philips I C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
interface, offering both arbitration lost detection and synchronous
function, is useful for multi-master serial communications.
Format
2
Figure 8.6.1 shows a block diagram of the multi-master I C-BUS in-
2
terface and Table 8.6.1 shows multi-master I C-BUS interface func-
2
tions.
In conformity with Philips I C-BUS
standard:
2
This multi-master I C-BUS interface consists of the address register,
Master transmission
Master reception
Slave transmission
Slave reception
the data shift register, the clock control register, the control register,
the status register and other control circuits.
Communication mode
SCL clock frequency 16.1 kHz to 400 kHz (φ = at 4 MHz)
φ : System clock = f(XIN)/2
Note : We are not responsible for any third party’s infringement of patent rights
or other rights attributable to the use of the control function (bits 6 and 7
of the I2C control register at address 00F916) for connections between
the I2C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2).
I2C address register (S0D)
b7
b0
Interrupt
generating
circuit
Interrupt
request signal
(IICIRQ)
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
Address comparator
Serial
data
(SDA)
Noise
elimination
circuit
Data
control
circuit
b7
b0
I2C data shift register
b7
b0
S0
AL AAS AD0 LRB
I2C control register (S1D)
MST TRX BB PIN
I2C status
register (S1)
AL
circuit
Internal data bus
BB
circuit
Noise
elimination
circuit
Serial
clock
(SCL)
Clock
control
circuit
b7
b0
b7
b0
FAST
MODE
10BIT
ACK
BIT
BSEL1 BSEL0
ALS
CCR4 CCR3 CCR2 CCR1 CCR0
ACK
ESO BC2 BC1 BC0
SAD
I2C control register (S1D)
System clock (φ)
I2C clock control register (S2)
Clock division
Bit counter
2
Fig. 8.6.1 Block Diagram of Multi-master I C-BUS Interface
Rev.1.00 Nov 01, 2002 page 29 of 136
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2
8.6.1 I C Data Shift Register
2
The I C data shift register (S0 : address 00F616) is an 8-bit shift
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to the
outside from bit 7 in synchronization with the SCL clock, and each
time one-bit data is output, the data of this register are shifted one bit
to the left. When data is received, it is input to this register from bit 0
in synchronization with the SCL clock, and each time one-bit data is
input, the data of this register are shifted one bit to the left.
2
The I C data shift register is in a write enable status only when the
2
ESO bit of the I C control register (address 00F916) is “1.” The bit
2
counter is reset by a write instruction to the I C data shift register.
2
When both the ESO bit and the MST bit of the I C status register
(address 00F816) are “1,” the SCL is output by a write instruction to
2
2
the I C data shift register. Reading data from the I C data shift regis-
ter is always enabled regardless of the ESO bit value.
Note: To write data into the I2C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
2
I C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0
2
I C data shift register 1(S0) [Address 00F616
]
B
Name
Functions
After reset
R
R
W
W
0
to
7
D0 to D7 This is an 8-bit shift register to store
receive data and write transmit data.
Indeterminate
2
Note : To write data into the I C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
2
Fig. 8.6.2 I C Data Shift Register
Rev.1.00 Nov 01, 2002 page 30 of 136
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2
8.6.2 I C Address Register
2
The I C address register (address 00F716) consists of a 7-bit slave
address and a read/write bit. In the addressing mode, the slave ad-
dress written in this register is compared with the address data to be
received immediately after the START condition is detected.
(1) Bit 0: read/write bit (RBW)
Not used when comparing addresses in the 7-bit addressing mode.
In the 10-bit addressing mode, the first address data to be received
2
is compared with the contents (SAD6 to SAD0 + RBW) of the I C
address register.
The RBW bit is cleared to “0” automatically when the stop condition
is detected.
(2) Bits 1 to 7: slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit address-
ing mode and the 10-bit addressing mode, the address data trans-
mitted from the master is compared with the contents of these bits.
2
I C Address Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C address register (S0D) [Address 00F716
BName Functions
]
After reset
0
R W
R —
0
<Only in 10-bit addressing (in slave) mode>
The last significant bit of address data is
compared.
Read/write bit
(RBW)
0: Wait the first byte of slave address after
START condition
(read state)
1: Wait the first byte of slave address after
(write state)
RESTART condition
<In both modes>
(SAD0 to SAD6) The address data is compared.
R
W
Slave address
0
1
to
7
2
Fig. 8.6.3 I C Address Register
Rev.1.00 Nov 01, 2002 page 31 of 136
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2
8.6.3 I C Clock Control Register
(4) Bit 7: ACK clock bit (ACK)
2
The I C clock control register (address 00FA16) is used to set ACK
This bit specifies a mode of acknowledgment which is an acknowl-
edgment response of data transmission. When this bit is set to “0,”
the no ACK clock mode is set. In this case, no ACK clock occurs
after data transmission. When the bit is set to “1,” the ACK clock
mode is set and the master generates an ACK clock upon comple-
tion of each 1-byte data transmission.The device for transmitting
address data and control data releases the SDA at the occurrence of
an ACK clock (make SDA HIGH) and receives the ACK bit generated
by the data receiving device.
control, SCL mode and SCL frequency.
(1) Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
These bits control the SCL frequency.
(2) Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0,” the stan-
dard clock mode is set. When the bit is set to “1,” the high-speed
clock mode is set.
Note: Do not write data into the I2C clock control register during transmission.
If data is written during transmission, the I2C clock generator is reset, so
that data cannot be transmitted normally.
(3) Bit 6: ACK bit (ACK BIT)
This bit sets the SDA status when an ACK clock is generated. When
✽
this bit is set to “0,” the ACK return mode is set and SDA goes to
LOW at the occurrence of an ACK clock. When the bit is set to “1,”
the ACK non-return mode is set. The SDA is held in the HIGH status
at the occurrence of an ACK clock.
However, when the slave address matches the address data in the
reception of address data at ACK BIT = “0,” the SDA automatically
goes to LOW (ACK is returned). If there is a mismatch between the
slave address and the address data, the SDA automatically goes to
HIGH (ACK is not returned).
✽ACK clock: Clock for acknowledgement
2
I C Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0
2
I C clock control register (S2) [Address 00FA16
]
After reset
0
B
Functions
R W
R W
Name
Setup value
of CCR4–
CCR0
Standard
clock
mode
High speed
clock mode
0
to
4
SCL frequency control
bits
(CCR0 to CCR4)
Setup disabled Setup disabled
00 to 02
Setup disabled
333
03
04
05
06
Setup disabled
250
400 (See note)
166
100
83.3
500/CCR value 1000/CCR value
17.2
16.6
16.1
34.5
33.3
32.3
1D
1E
1F
(φ = 4 MHz, unit : kHz)
0
5
SCL mode
specification bit
(FAST MODE)
0: Standard clock mode
1: High-speed clock mode
R W
6
7
ACK bit
(ACK BIT)
0: ACK is returned.
1: ACK is not returned.
0
0
R W
R W
ACK clock bit
(ACK)
0: No ACK clock
1: ACK clock
Note. At 400kHz in the high-speed clock mode, the duty is as below.
“0” period : “1” period = 3 : 2
In the other cases, the duty is as below.
“0” period : “1” period = 1 : 1
2
Fig. 8.6.4 I C Clock Control Register
Rev.1.00 Nov 01, 2002 page 32 of 136
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8.6.4 I C Control Register
(3) Bit 4: data format selection bit (ALS)
2
The I C control register (address 00F916) controls the data commu-
This bit decides whether or not to recognize slave addresses. When
this bit is set to “0,” the addressing format is selected, so that ad-
dress data is recognized. When a match is found between a slave
address and address data as a result of comparison or when a gen-
nication format.
(1) Bits 0 to 2: bit counter (BC0–BC2)
2
These bits decide the number of bits for the next 1-byte data to be
transmitted. An interrupt request signal occurs immediately after the
number of bits specified with these bits are transmitted.
eral call (refer to “8.6.5 I C Status Register,” bit 1) is received, trans-
mission processing can be performed. When this bit is set to “1,” the
free data format is selected, so that slave addresses are not recog-
nized.
When a START condition is received, these bits become “0002” and
the address data is always transmitted and received in 8 bits.
(4) Bit 5: addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit is
set to “0,” the 7-bit addressing format is selected. In this case, only
2
(2) Bit 3: I C interface use enable bit (ESO)
2
This bit enables usage of the multimaster I C BUS interface. When
2
this bit is set to “0,” interface is in the disable status, so the SDA and
the SCL become high-impedance. When the bit is set to “1,” use of
the interface is enabled.
the high-order 7 bits (slave address) of the I C address register (ad-
dress 00F716) are compared with address data. When this bit is set
to “1,” the 10-bit addressing format is selected and all the bits of the
2
When ESO = “0,” the following is performed.
I C address register are compared with the address data.
2
• PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I C
status register at address 00F816 ).
(5) Bits 6 and 7: connection control bits between
I2C-BUS interface and ports
(BSEL0, BSEL1)
2
• Writing data to the I C data shift register (address 00F616) is dis-
abled.
These bits control the connection between SCL and ports or SDA
and ports (refer to Figure 8.6.5).
Note: To connect with SCL3 and SDA3, set bits 2 and 3 of the port P3 register
(00C616) .
“0”
“1” BSEL20
Notes • The paths SCL1, SCL2, SDA1, and SDA2, as well as the paths
SCL3 and SDA3 cannot be connected at the same time.
SCL3/P3
1
“0”
BSEL21
“1”
“0”
“1”
BSEL0
BSEL1
SCL1/P1
1
2
SCL
• Port P3 Register (address 00C616) bit 3 is used to control the pin
“0”
“1”
connections of SCL3/P31 and SCL1/P11 and those of SDA3/P30 and SDA1/P13.
SCL2/P1
Multi-master
“0”
“1”
BSEL20
I2C-BUS
interface
• Set the corresponding direction register to "1" to use the port as
multi-master I2C-BUS interface.
SDA3/P3
0
“0”
BSEL21
“1”
“0”
“1” BSEL0
SDA1/P1
3
SDA
“0”
BSEL1
“1”
SDA2/P1
4
Fig. 8.6.5 Connection Port Control by BSEL0 and BSEL1
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2
I C Control Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C control register (S1D) [Address 00F916]
After reset
0
B
Name
Functions
R W
R W
Bit counter
(Number of transmit/recieve
b2 b1 b0
0
to
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : 8
bits)
1 : 7
0 : 6
1 : 5
0 : 4
1 : 3
0 : 2
1 : 1
(BC0 to BC2)
3
4
5
I2C-BUS interface use
enable bit (ESO)
0
0
0
0
0 : Disabled
1 : Enabled
R W
R W
R W
R W
Data format selection
bit(ALS)
0 : Addressing mode
1 : Free data format
Addressing format selection
bit (10BIT SAD)
0 : 7-bit addressing format
1 : 10-bit addressing format
b7 b6 Connection port (See note)
6, 7 Connection control bits
between I2C-BUS interface
and ports
0
0
1
1
0: None
1: SCL1, SDA1
0: SCL2, SDA2
1: SCL1, SDA1
SCL2, SDA2
(BSEL0, BSEL1)
Note: • Set the corresponding direction register to "1" to use the port as multi-master I2C-BUS interface.
• To use SCL1, SDA1, SCL2 and SDA2, set the port P3 Register (address 00C616) bit 2 to 0.
2
Fig. 8.6.6 I C Control Register
Port P3 register
b7 b6 b5 b4 b3 b2 b1 b0
Port P3 register (P3) [Address 00C616]
BName
Functions
After reset
Indeterminate
Indeterminate
0
R
R
R
R
W
W
W
W
0
1
2
Port P3 register
Port P3
0
1
data
data
Port P3
Switch bit of I2C-BUS
interface and port P3
0: Port P30, Port P31
1: I2CBUS (SDA3,SCL3)
(BSEL20)
(See note)
SCL3/P3 -SCL1/P1
1
1
3
R
R
0
0
W
–
0: Cutting
SDA3/P3 -SDA1/P1
0
3
1: Connection
Connection control bit (BSEL21)
Nothing is assigned. This bit is write disable bit.
When this bit is read out, the value is "0."
4 to
7
Notes
•
For the ports used as the Multi-master I2C-BUS interface, set their direction registers to 1.
• To use SCL3 and SDA3, set the I2C Control Register (address 00F916) bits 6–7 to 0.
Fig. 8.6.7 Port P3 Register
Rev.1.00 Nov 01, 2002 page 34 of 136
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2
8.6.5 I C Status Register
(5) Bit 4: I2C-BUS interface interrupt request bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte data
is transmitted, the state of the PIN bit changes from “1” to “0.” At the
same time, an interrupt request signal is sent to the CPU. The PIN bit
is set to “0” in synchronization with a falling edge of the last clock
(including the ACK clock) of an internal clock and an interrupt re-
quest signal occurs in synchronization with a falling edge of the PIN
bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock
generation is disabled. Figure 8.6.9 shows an interrupt request sig-
nal generating timing chart.
2
2
The I C status register (address 00F816) controls the I C-BUS inter-
face status. The low-order 4 bits are read-only bits and the high-
order 4 bits can be read out and written to.
(1) Bit 0: last receive bit (LRB)
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an ACK
clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is
set to “1.” Except in the ACK mode, the last bit value of received data
is input. The state of this bit is changed from “1” to “0” by executing a
The PIN bit is set to “1” in any one of the following conditions.
2
2
write instruction to the I C data shift register (address 00F616).
• Executing a write instruction to the I C data shift register (address
00F616).
(2) Bit 1: general call detecting flag (AD0)
• When the ESO bit is “0”
✽
This bit is set to “1” when a general call whose address data is all
• At reset
“0” is received in the slave mode. By a general call of the master
device, every slave device receives control data after the general
call. The AD0 bit is set to “0” by detecting the STOP condition or
START condition.
The conditions in which the PIN bit is set to “0” are shown below:
• Immediately after completion of 1-byte data transmission (includ-
ing when arbitration lost is detected)
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately after
completion of slave address or general call address reception
• In the slave reception mode, with ALS = “1” and immediately after
completion of address data reception
✽General call: The master transmits the general call address “0016”
to all slaves.
(3) Bit 2: slave address comparison flag (AAS)
This flag indicates a comparison result of address data.
(6) Bit 5: bus busy flag (BB)
✽ In the slave receive mode, when the 7-bit addressing format is
selected, this bit is set to “1” in either of the following conditions.
• The address data immediately after occurrence of a START con-
dition matches the slave address stored in the high-order 7 bits
This bit indicates the status of the bus system. When this bit is set to
“0,” this bus system is not busy and a START condition can be gen-
erated. When this bit is set to “1,” this bus system is busy and the
occurrence of a START condition is disabled by the START condition
duplication prevention function (See note).
2
of the I C address register (address 00F716).
• A general call is received.
This flag can be written by software only in the master transmission
mode. In the other modes, this bit is set to “1” by detecting a START
condition and set to “0” by detecting a STOP condition. When the
✽ In the slave reception mode, when the 10-bit addressing format is
selected, this bit is set to “1” in the following condition.
2
2
• When the address data is compared with the I C address regis-
ESO bit of the I C control register (address 00F916) is “0” at reset,
ter (8 bits consisting of slave address and RBW), the first bytes
match.
the BB flag is kept in the “0” state.
✽ The state of this bit is changed from “1” to “0” by executing a write
(7) Bit 6: communication mode specification bit
(transfer direction specification bit: TRX)
2
instruction to the I C data shift register (address 00F616).
This bit decides the direction of transfer for data communication. When
this bit is “0,” the reception mode is selected and the data of a trans-
mitting device is received. When the bit is “1,” the transmission mode
is selected and address data and control data are output into the
SDA in synchronization with the clock generated on the SCL.
✽
(4) Bit 3: arbitration lost detecting flag (AL)
In the master transmission mode, when a device other than the mi-
crocomputer sets the SDA to “L,” arbitration is judged to have been
lost, so that this bit is set to “1.” At the same time, the TRX bit is set to
“0,” so that immediately after transmission of the byte whose arbitra-
tion was lost is completed, the MST bit is set to “0.” When arbitration
is lost during slave address transmission, the TRX bit is set to “0” and
the reception mode is set. Consequently, it becomes possible to re-
ceive and recognize its own slave address transmitted by another
master device.
2
When the ALS bit of the I C control register (address 00F916) is “0” in
the slave reception mode, the TRX bit is set to “1” (transmit) if the
___
least significant bit (R/W bit) of the address data transmitted by the
___
master is “1.” When the ALS bit is “0” and the R/W bit is “0,” the TRX
bit is cleared to “0” (receive).
The TRX bit is cleared to “0” in one of the following conditions.
• When arbitration lost is detected.
✽Arbitration lost: The status in which communication as a master is
• When a STOP condition is detected.
disabled.
• When occurence of a START condition is disabled by the START
condition duplication prevention function (Note).
• When MST = “0” and a START condition is detected.
• When MST = “0” and ACK non-return is detected.
• At reset
Rev.1.00 Nov 01, 2002 page 35 of 136
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Note:The START condition duplication prevention function disables the START
condition generation, bit counter reset, and SCL output, when the follow-
ing condition is satisfied:
(8) Bit 7: Communication mode specification bit
(master/slave specification bit: MST)
This bit is used for master/slave specification in data communica-
tions. When this bit is “0,” the slave is specified, so that a START
condition and a STOP condition generated by the master are received,
and data communication is performed in synchronization with the
clock generated by the master. When this bit is “1,” the master is
specified and a START condition and a STOP condition are gener-
ated, and also the clocks required for data communication are gen-
erated on the SCL.
a START condition is set by another master device.
The MST bit is cleared to “0” in any of the following conditions.
• Immediately after completion of 1-byte data transmission when
arbitration lost is detected
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START
condition duplication prevention function (Note).
• At reset
2
I C Status Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register (S1) [Address 00F816
]
After reset
BName
Functions
W
R
0
1
2
Last receive bit (LRB)
(See note)
0 : Last bit = “0 ”
1 : Last bit = “1 ”
Indeterminate
R —
R —
R —
(See note)
General call detecting flag
(AD0) (See note)
0 : No general call detected
1 : General call detected
0
0
(See note)
Slave address comparison
flag (AAS) (See note)
0 : Address mismatch
1 : Address match
(See note)
(See note)
3
4
5
Arbitration lost detecting flag 0 : Not detected
(AL) (See note)
0
1
0
0
R —
R W
R W
R W
1 : Detected
I2C-BUS interface interrupt
request bit (PIN)
0 : Interrupt request issued
1 : No interrupt request issued
Bus busy flag (BB)
0 : Bus free
1 : Bus busy
6, 7 Communication mode
specification bits
b7 b6
0
0
1
1
0 : Slave recieve mode
1 : Slave transmit mode
0 : Master recieve mode
1 : Master transmit mode
(TRX, MST)
Note : These bits and flags can be read out, but cannnot be written.
2
Fig. 8.6.8 I C Status Register
SCL
PIN
IICIRQ
Fig. 8.6.9 Interrupt Request Signal Generation Timing
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8.6.6 START Condition Generation Method
2
When the ESO bit of the I C control register (address 00F916) is “1,”
I2C status register
write signal
2
execute a write instruction to the I C status register (address 00F816)
to set the MST, TRX and BB bits to “1.” A START condition will then
be generated. After that, the bit counter becomes “0002” and an SCL
is output for 1 byte. The START condition generation timing and BB
bit set timing are different in the standard clock mode and the high-
speed clock mode. Refer to Figure 8.6.10 for the START condition
generation timing diagram, and Table 8.6.2 for the START condition/
STOP condition generation timing table.
SCL
SDA
Setup
time
Hold time
Set time
for BB flag
BB flag
Fig. 8.6.10 START Condition Generation Timing Diagram
8.6.7 STOP Condition Generation Method
2
When the ESO bit of the I C control register (address 00F916) is “1,”
I2C status register
write signal
2
execute a write instruction to the I C status register (address 00F816)
to set the MST bit and the TRX bit to “1” and the BB bit to “0”. A STOP
condition will then be generated. The STOP condition generation tim-
ing and the BB flag reset timing are different in the standard clock
mode and the high-speed clock mode. Refer to Figure 8.6.11 for the
STOP condition generation timing diagram, and Table 8.6.2 for the
START condition/STOP condition generation timing table.
SCL
Setup
time
Hold time
SDA
Reset time
for BB flag
BB flag
Fig. 8.6.11 STOP Condition Generation Timing Diagram
Table 8.6.2 START Condition/STOP Condition Generation Tim-
ing Table
Item
Standard Clock Mode High-speed Clock Mode
Setup time
(START condition)
Setup time
(STOP condition)
Hold time
5.0 µs (20 cycles)
2.5 µs (10 cycles)
4.25 µs (17 cycles)
5.0 µs (20 cycles)
3.0 µs (12 cycles)
1.75 µs (7 cycles)
2.5 µs (10 cycles)
1.5 µs (6 cycles)
Set/reset time
for BB flag
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the
number of φ cycles.
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8.6.8 START/STOP Condition Detect Conditions
The START/STOP condition detect conditions are shown in
Figure 8.6.12 and Table 8.6.3. Only when the 3 conditions of Table
8.6.3 are satisfied, a START/STOP condition can be detected.
8.6.9 Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective ad-
dress communication formats are described below.
Note: When a STOP condition is detected in the slave mode
(MST = 0), an interrupt request signal “IICIRQ” is generated to the
CPU.
(1) 7-bit addressing format
To support the 7-bit addressing format, set the 10BIT SAD bit of the
2
I C control register (address 00F916) to “0.” The first 7-bit address
data transmitted from the master is compared with the high-order 7-
2
bit slave address stored in the I C address register (address 00F716).
At the time of this comparison, address comparison of the RBW bit of
2
the I C address register (address 00F716) is not made. For the data
transmission format when the 7-bit addressing format is selected,
refer to Figure 8.6.13, (1) and (2).
SCL release time
SCL
Setup
Hold time
time
SDA
(2) 10-bit addressing format
(START condition)
Setup
To support the 10-bit addressing format, set the 10BIT SAD bit of the
Hold time
time
2
I C control register (address 00F916) to “1.” An address comparison
SDA
(STOP condition)
is made between the first-byte address data transmitted from the
2
master and the 7-bit slave address stored in the I C address register
(address 00F716). At the time of this comparison, an address com-
Fig. 8.6.12 START Condition/STOP Condition Detect Timing
Diagram
2
parison is performed between the RBW bit of the I C address regis-
–
ter (address 00F716) and the R/W bit, which is the last bit of the
address data transmitted from the master. In the 10-bit addressing
–
mode, the R/W bit not only specifies the direction of communication
Table 8.6.3 START Condition/STOP Condition Detect Conditions
for control data but is also processed as an address data bit.
When the first-byte address data matches the slave address, the
Standard Clock Mode
High-speed Clock Mode
2
AAS bit of the I C status register (address 00F816) is set to “1.” After
6.5 µs (26 cycles) < SCL
1.0 µs (4 cycles) < SCL
2
the second-byte address data is stored into the I C data shift register
release time
release time
(address 00F616), perform an address comparison between the sec-
ond-byte data and the slave address by software. When the address
data of the 2nd byte matches the slave address, set the RBW bit of
3.25 µs (13 cycles) < Setup time
3.25 µs (13 cycles) < Hold time
0.5 µs (2 cycles) < Setup time
0.5 µs (2 cycles) < Hold time
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the num-
ber of φ cycles.
2
the I C address register (address 00F716) to “1” by software. This
–
processing can match the 7-bit slave address and R/W data, which
are received after a RESTART condition is detected, with the value
2
of the I C address register (address 00F716). For the data transmis-
sion format when the 10-bit addressing format is selected, refer to
Figure 8.6.13, (3) and (4).
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8.6.10 Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz with the ACK return mode enabled, is
shown below.
8.6.11 Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the
SCL frequency of 400 kHz, with the ACK Non-return mode enabled
while using the addressing format, is shown below.
2
2
✽ Set a slave address in the high-order 7 bits of the I C address
✽ Set a slave address in the high-order 7 bits of the I C address
register (address 00F716) and “0” in the RBW bit.
register (address 00F716) and “0” in the RBW bit.
✽ Set the ACK return mode and SCL = 100 kHz by setting “8516” in
✽ Set the ACK non-return mode and SCL = 400 kHz by setting “2516”
2
2
the I C clock control register (address 00FA16).
in the I C clock control register (address 00FA16).
2
2
✽ Set “1016” in the I C status register (address 00F816) and hold the
✽ Set “1016” in the I C status register (address 00F816) and hold the
SCL at HIGH.
SCL at HIGH.
2
2
✽ Set a communication enable status by setting “4816” in the I C
✽ Set a communication enable status by setting “4816” in the I C
control register (address 00F916).
control register (address 00F916).
✽ Set the address data of the destination of transmission in the high-
✽ When a START condition is received, an address comparison is
executed.
2
order 7 bits of the I C data shift register (address 00F616) and set
“0” in the least significant bit.
✽ •When all transmitted address are“0” (general call):
2
2
✽ Set “F016” in the I C status register (address 00F816) to generate
AD0 of the I C status register (address 00F816) is set to “1” and
a START condition. At this time, an SCL for 1 byte and an ACK
an interrupt request signal occurs.
clock automatically occurs.
•When the transmitted addresses match the address set in ✽:
2
2
✽ Set transmit data in the I C data shift register (address 00F616). At
ASS of the I C status register (address 00F816) is set to “1” and
this time, an SCL and an ACK clock automatically occurs.
an interrupt request signal occurs.
•In the cases other than the above:
✽ When transmitting control data of more than 1 byte, repeat step ✽.
2
2
✽ Set “D016” in the I C status register (address 00F816). After this, if
AD0 and AAS of the I C status register (address 00F816) are set
ACK is not returned or transmission ends, a STOP condition will
be generated.
to “0” and no interrupt request signal occurs.
2
✽ Set dummy data in the I C data shift register (address 00F616).
✽ When receiving control data of more than 1 byte, repeat step ✽.
✽ When a STOP condition is detected, the communication ends.
Rev.1.00 Nov 01, 2002 page 39 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
S
Slave address R/W
7 bits “0”
A
Data
A
Data
A/A
P
P
A
1 to 8 bits
1 to 8 bits
(1) A master-transmitter transmits data to a slave-receiver
R/W
“1”
S
Slave address
7 bits
A
Data
A
Data
A
1 to 8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
Slave address
1st 7 bits
Slave address
2nd byte
S
R/W
“0”
A
A
Data
1 to 8 bits
Data
A/A
P
7 bits
8 bits
1 to 8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
Slave address
1st 7 bits
Slave address
2nd byte
Slave address
1st 7 bits
S
R/W
“0”
A
A
Sr
R/W Data
A
Data
A
P
7 bits
8 bits
7 bits
“1” 1 to 8 bits
1 to 8 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S : START condition
A : ACK bit
Sr :Restart condition
P : STOP condition
R/W : Read/Write bit
From master to slave
From slave to master
Fig. 8.6.13 Address Data Communication Format
(2) START condition generating procedure us-
ing multi-master
8.6.12 Precautions when using multi-master
2
I C-BUS interface
✽ Procedure example (The necessary conditions for the procedure
are described in ✽ to ✽ below).
(1) Read-modify-write instruction
Precautions for executing the read-modify-write instructions, such
•
•
2
as SEB and CLB, is for each register of the multi-master I C-BUS
interface are described below.
LDA
SEI
—
(Take at slave address value)
(Interrupt disabled)
2
•I C data shift register (S0)
When executing the read-modify-write instruction for this register
during transfer, data may become an arbitrary value.
BBS 5,S1,BUSBUSY (BB flag confirmation and branch
process)
2
•I C address register (S0D)
BUSFREE:
STA S0
When the read-modify-write instruction is executed for this register
(Write slave address value)
(Trigger START condition generation)
(Interrupt enabled)
at detection of the STOP condition, data may become an arbitrary
LDM #$F0, S1
______
value because hardware changes the read/write bit (RBW) at the
CLI
above timing.
•
•
2
•I C status register (S1)
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by hardware.
BUSBUSY:
CLI
(Interrupt enabled)
2
•I C control register (S1D)
•
•
When the read-modify-write instruction is executed for this register
at detection of the START condition or at completion of the byte
transfer, data may become an arbitrary value because hardware
changes the bit counter (BC0–BC2) at the above timing.
✽ Use “STA,” “STX” or “STY” of the zero page addressing instruc-
2
tion for writing the slave address value to the I C data shift register.
2
•I C clock control register (S2)
✽ Use “LDM” instruction for setting trigger of START condition gen-
eration.
The read-modify-write instruction can be executed for this register.
✽ Write the slave address value of ✽ and set trigger of START con-
dition generation as in ✽ continuously, as shown in the procedure
example.
✽ Disable interrupts during the following three process steps:
• BB flag confirmation
• Write slave address value
• Trigger of START condition generation
When the condition of the BB flag is bus busy, enable interrupts
immediately.
Rev.1.00 Nov 01, 2002 page 40 of 136
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(3) RESTART condition generation procedure
✽ Procedure example (The necessary conditions for the procedure
are described in ✽ to ✽ below.)
(4) STOP condition generating procedure
✽ Procedure example (The necessary conditions for the procedure
are described in ✽ to ✽ below.)
Execute the following procedure when the PIN bit is “0.”
•
•
•
•
SEI
(Interrupt disabled)
LDM #$00, S1
(Select slave receive mode)
(Take out slave address value)
(Interrupt disabled)
LDM #$C0, S1
NOP
(Select master transmit mode)
(Set NOP)
LDA
SEI
—
LDM #$D0, S1
CLI
(Trigger STOP condition generation)
(Interrupt enabled)
STA
S0
(Write slave address value)
(Trigger RESTART condition generation)
(Interrupt enabled)
LDM #$F0, S1
•
CLI
•
•
•
✽ Write “0” to the PIN bit when master transmit mode is selected.
✽ Execute “NOP” instruction after master transmit mode is set. Also,
set trigger of STOP condition generation within 10 cycles after se-
lecting the master trasmit mode.
✽ Select the slave receive mode when the PIN bit is “0.” Do not write
“1” to the PIN bit. Neither “0” nor “1” is specified for the writing to
the BB bit.
✽ Disable interrupts during the following two process steps:
• Select master transmit mode
The TRX bit becomes “0” and the SDA pin is released.
✽ The SCL pin is released by writing the slave address value to the
• Trigger STOP condition generation
2
I C data shift register. Use “STA,” “STX” or “STY” of the zero page
2
addressing instruction for writing.
(5) Writing to I C status register
✽ Use “LDM” instruction for setting trigger of RESTART condition
generation.
Do not execute an instruction to set the PIN bit to “1” from “0” and an
instruction to set the MST and TRX bits to “0” from “1” simultaneously
as it may cause the SCL pin the SDA pin to be released after about
one machine cycle. Also, do not execute an instruction to set the
MST and TRX bits to “0” from “1” when the PIN bit is “1,” as it may
cause the same problem.
✽ Write the slave address value of ✽ and set trigger of RESTART
condition generation of ✽ continuously, as shown in the procedure
example.
✽ Disable interrupts during the following two process steps:
• Write slave address value
• Trigger RESTART condition generation
(6) Process after STOP condition generation
2
2
Do not write data in the I C data shift register S0 and the I C status
register S1 until the bus busy flag BB becomes “0” after generating
the STOP condition in the master mode. Doing so may cause the
STOP condition waveform from being generated normally. Reading
the registers does not cause the same problem.
Rev.1.00 Nov 01, 2002 page 41 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.7 PWM OUTPUT FUNCTION
This microcomputer is equipped with five 8-bit PWMs (PWM0–
PWM4). PWM0–PWM4 have the same circuit structure, an 8-bit reso-
lution with minimum resolution bit width of 4 µs (for f(XIN) = 8 MHz)
and repeat period of 1024 µs (for f(XIN) = 8 MHz).
Figure 8.7.1 shows the PWM block diagram. The PWM timing gen-
erating circuit applies individual control signals to PWM0–PWM4 us-
ing f(XIN) divided by 2 as a reference signal.
8.7.1 Data Setting
When outputting PWM0–PWM4, set 8-bit output data to the PWMi
register (i means 0 to 4; addresses 020016 to 020416).
8.7.2 Transmitting Data from Register to PWM
circuit
Data transfer from the 8-bit PWM register to the 8-bit PWM circuit is
executed when writing data to the register.
The signal output from the 8-bit PWM output pin corresponds to the
contents of this register.
8.7.3 Operating of 8-bit PWM
The following explains the PWM operation.
First, set bit 0 of PWM mode register 1 (address 020816) to “0” (at
reset, bit 0 is already set to “0” automatically), so that the PWM count
source is supplied.
PWM0–PWM4 are also used as pins P00–P04. Set the correspond-
ing bits of the port P0 direction register to “1” (output mode). And
select each output polarity by bit 3 of PWM mode register 1 (address
020816). Then, set bits 4 to 0 of PWM mode register 2 (address
020916) to “1” (PWM output).
The PWM waveform is output from the PWM output pins by setting
these registers.
Figure 8.7.2 shows the 8-bit PWM timing. One cycle (T) is com-
8
posed of 256 (2 ) segments. 8 kinds of pulses, relative to the weight
of each bit (bits 0 to 7), are output inside the circuit during 1 cycle.
Refer to Figure 8.7.2 (a). The 8-bit PWM outputs a waveform which
is the logical sum (OR) of pulses corresponding to the contents of
bits 0 to 7 of the 8-bit PWM register. Several examples are shown in
Figure 8.7.2 (b). 256 kinds of output (HIGH area: 0/256 to 255/256)
are selected by changing the contents of the PWM register. An en-
tirely HIGH section cannot be output, i.e. 256/256.
8.7.4 Output after Reset
At reset, the output of ports P00–P04 is in the high-impedance state,
and the contents of the PWM register and the PWM circuit are unde-
fined. Note that after reset, the PWM output is undefined until setting
the PWM register.
Rev.1.00 Nov 01, 2002 page 42 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Data bus
PWM timing
generating
circuit
XIN
1/2
PM10
PWM0 register
(Address 020016
)
b7
b0
8
PWM0
PWM1
PM13
D0
D0
0
1
P0
0
8-bit PWM circuit
PM20
P0
1
PM21
P0
PM22
P0
PM23
P0
PM24
PWM1 register (Address 020116)
PWM2 register (Address 020216)
PWM3 register (Address 020316)
PWM4 register (Address 020416)
PWM2
PWM3
PWM4
D0
D0
D0
2
3
4
2
3
4
Selection gate:
Connected to
black side at
reset.
PM1 : PWM mode register 1 (address 0208 16
PM2 : PWM mode register 2 (address 0209 16
P0 : Port P0 register (address 00C0 16
D0 : Port P0 direction register (address 00C1 16
)
)
)
)
Inside of
is as same contents with the others.
Fig. 8.7.1 PWM Block Diagram
Rev.1.00 Nov 01, 2002 page 43 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Fig. 8.7.2 PWM Timing
Rev.1.00 Nov 01, 2002 page 44 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
PWM Mode Register 1
b7b6 b5b4b3 b2b1b0
PWM mode register 1 (PM1) [Address 020816
]
After reset
0
B
0
Name
Functions
R W
PWM counts source
selection bit (PM10)
0 : Count source supply
1 : Count source stop
W
R
1, 2
3
—
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
Indeterminate
0
R
PWM output polarity
selection bit (PM13)
0 : Positive polarity
1 : Negative polarity
R W
4
to
7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
—
R
Indeterminate
Fig. 8.7.3 PWM Mode Register 1
PWM Mode Register 2
b7b6 b5b4b3 b2b1b0
0 0 0
PWM mode register 2 (PM2) [Address 020916
]
B
0
Name
Functions
output
1 : PWM0 output
0 : P0 output
1 : PWM1 output
After reset R W
0 : P0
0
P0
0
/PWM0 output
0
R W
selection bit (PM20)
P0 /PWM1 output
selection bit (PM21)
P0 /PWM2 output
selection bit (PM22)
P0 /PWM3 output
selection bit (PM23)
1
2
3
4
1
1
0
0
0
R W
R W
R W
2
0 : P02 output
1 : PWM2 output
3
0 : P0 output
3
1 : PWM3 output
P0 /PWM4 output
selection bit (PM24)
4
0
0
R W
R W
0 : P0 output
4
1 : PWM4 output
Fix these bits to “0.”
5 to
7
Fig. 8.7.4 PWM Mode Register 2
Rev.1.00 Nov 01, 2002 page 45 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.8 A-D COMPARATOR
The A-D comparator consists of a 7-bit D-A converter and a com-
parator. The A-D comparator block diagram is shown in Figure 8.8.1.
The reference voltage “Vref” for D-A conversion is set by bits 0 to 6 of
A-D control register 2 (address 00ED16).
The comparison result of the analog input voltage and the reference
voltage “Vref” is stored in bit 4 of A-D control register 1 (address
00EC16).
For A-D comparison, set “0” to corresponding bits of the direction
register to use ports as analog input pins. Write the data to select
analog input pins for bits 0 to 2 of A-D control register 1 and write the
digital value corresponding to Vref to be compared to bits 0
to 4 of A-D control register 2. The voltage comparison is started by
writing to A-D control register 2, and it is completed after 16 machine
cycles (NOP instruction ✕✕8).
Data bus
A-D control register 1
Comparator control
Bits 0 to 2
A-D control
register 1
A-D control
register 2
AD1
AD2
AD3
AD4
AD5
AD6
Analog
signal
switch
Compa-
rator
Bit 4
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AD7
AD8
Switch tree
Resistor ladder
Fig. 8.8.1 A-D Comparator Block Diagram
Rev.1.00 Nov 01, 2002 page 46 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
A-D Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register 1 (AD1) [Address 00EC16
]
B
Name
Functions
After reset R W
0
to
2
Analog input pin selection
bits
(ADC10 to ADC12)
b2 b1 b0
0
R W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : AD1
1 : AD2
0 : AD3
1 : AD4
0 : AD5
1 : AD6
0 : AD7
1 : AD8
3
4
This bit is a write disable bit.
When this bit is read out, the value is “0.”
0
—
R
0: Input voltage < reference voltage
1: Input voltage > reference voltage
Storage bit of comparison
result (ADC14)
R —
Indeterminate
0
5
to
7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
—
R
Fig. 8.8.2 A-D Control Register 1
A-D Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register 2 (AD2) [Address 00ED16
]
B
Name
Functions
After reset
0
R
R
W
W
b6 b5 b4 b3 b2 b1 b0
0
to
6
D-A converter set bits
(ADC20 to ADC25)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
: 1/256Vcc
: 3/256Vcc
: 5/256Vcc
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
: 251/256Vcc
: 253/256Vcc
: 255/256Vcc
Nothing is assigned. This bit is a write disable bit.
When these bits are reed out, the values are “ 0.”
0
R
—
7
Fig. 8.8.3 A-D Control Register 2
Rev.1.00 Nov 01, 2002 page 47 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.9 ROM CORRECTION FUNCTION
This can correct program data in the ROM. Up to 2 addresses can be
corrected; a program for correction is stored in the ROM correction
vector in the RAM as the top address. There are 2 vectors for ROM
correction:.
ROM correction address 1 (high-order) 020A16
ROM correction address 1 (low-order) 020B16
ROM correction address 2 (high-order) 020C16
Vector 1 : address 030016
Vector 2 : address 032016
Set the address of the ROM data to be corrected into the ROM cor-
rection address register. When the value of the counter matches the
ROM data address in the top address of the ROM correction vector,
the main program branches to the correction program stored in the
ROM memory. To return from the correction program to the main
program, the op code and operand of the JMP instruction (total of 3
bytes) are necessary at the end of the correction program.
The ROM correction function is controlled by the ROM correction
enable register.
ROM correction address 2 (low-order)
020D16
Fig. 8.9.1 ROM Correction Address Registers
Notes 1: Specify the first address (op code address) of each
instruction as the ROM correction address.
2: Use the JMP instruction (total of 3 bytes) to return from
the correction program to the main program.
3: Do not set the same ROM correction address to both vectors 1
and 2.
ROM Correction Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
ROM correction enable register (RCR) [Address 020E 16
]
After reset
0
B
Name
Functions
R W
R W
0
Vector 1 enable bit (RC0)
0: Disabled
1: Enabled
1
Vector 2 enable bit (RC1)
0: Disabled
1: Enabled
0
0
R W
R —
Nothing is assigned. These bits are write disable bits. When
these bits are read out, the values are “0.”
2
to
7
Rev.1.00 Nov 01, 2002 page 48 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.10 DATA SLICER
When the data slicer function is not used, the data slicer circuit and
the timing signal generating circuit can be cut off by setting bit 0 of
data slicer control register 1 (address 00E016) to “0.” These settings
support low-power dissipation.
This microcomputer includes the data slicer function for the closed
caption decoder (referred to as the CCD). This function takes out the
caption data superimposed in the vertical blanking interval of a com-
posite video signal. A composite video signal, which makes the sync
chip’s polarity negative, is input to the CVIN pin.
0.1 µF
1 MΩ
Composite
video
signal
470 Ω
1 kΩ
Sync pulse counter
register
560 pF
1 µF
200 pF
(address 00E916
)
CVIN
H
SYNC
HLF
Synchronizing
signal counter
Data slicer control register 2
(address 00E116
Clamping
circuit
)
Synchronizing
separation
circuit
Low-pass
filter
Sync slice
circuit
Data slicer control register 1
(address 00E016
)
Timing signal
generating
circuit
Data slicer ON/OFF
VHOLD
Reference
voltage
generating
circuit
+
–
Clock run-in
determination
circuit
1000 pF
Comparator
Clock run-in defect register
(address 00E416
)
Data slice line
specification
circuit
Caption position register
(address 00E616
Start bit detecting
circuit
)
External circuit
Note : Make the length of wiring which is
Data clock
connected to VHOLD, HLF, and CVIN pin as
short as possible so that a leakage current
may not be generated when mounting a
resistor or a capacitor on each pin.
generating circuit
Data clock position register
(address 00E516
)
16-bit shift register
Data slicer
interrupt
request
Interrupt request
generating circuit
high-order
low-order
Caption data register 1
Caption data register 2
(address 00E316
(address 00E216
)
)
Caption data register 4
(address 00CF16
Caption data register 3
(address 00CE16
)
)
Data bus
Fig. 8.10.1 Data Slicer Block Diagram
Rev.1.00 Nov 01, 2002 page 49 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.10.1 Notes When not Using Data Slicer
When bit 0 of data slicer control register 1 (address 00E016) is “0,”
terminate the pins as shown in Figure 8.10.2.
<When data slicer circuit and timing signal generating circuit are in OFF state>
Leave HLF pin open.
Open
Open
HLF
24
25
26
Leave VHOLD pin open.
V
HOLD
CVIN
Pull-down CVIN pin to VSS through
a resistor of 5 kΩ or more.
5 kΩ or more
Fig. 8.10.2 Termination of Data Slicer Input/Output Pins when Data Slicer Circuit and Timing Generating Circuit are in OFF State
When both bits 0 and 2 of data slicer control register 1 (address
00E016) are “1,” terminate the pins as shown in Figure 8.10.3.
<When using a reference clock generated in timing signal generating circuit as OSD clock>
1 kΩ
HLF
Connect the same external circuit as when
using data slicer to HLF pin.
24
25
1 µF
200pF
Open
HOLD
V
Leave VHOLD pin open.
Pull-up CVIN to VCC through a resistor
of 5 kΩ or more.
5 kΩ or more
CVIN
26
Fig. 8.10.3 Termination of Data Slicer Input/Output Pins when Timing Signal Generating Circuit Is in ON State
Rev.1.00 Nov 01, 2002 page 50 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Figures 8.10.4 and 8.10.5 the data slicer control registers.
Data Slicer Control Register 1
b7b6b5b4b3b2b1b0
0 1 1 0 0
Data slicer control register 1(DSC1) [Address 00E016
]
B
0
Name
Functions
0: Stopped
1: Operating
After reset
R
R
W
W
0
Data slicer and timing signal
generating circuit control bit (DSC10)
1
2
0: F2
1: F1
0
0
0
R
R
R
W
W
W
Selection bit of data slice reference
voltage generating field (DSC11)
0: Video signal
1: HSYNC signal
Reference clock source
selection bit (DSC12)
3, 4
Fix these bits to “0.”
5, 6
7
0
0
R
R
W
W
Fix these bits to “1.”
Fix this bit to “0.”
Definition of fields 1 (F1) and 2 (F2)
sep
H
F2:
sep
H
F1:
sep
V
sep
V
Fig. 8.10.4 Data Slicer Control Register 1
Data Slicer Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
1
Data slicer control register 2 (DSC2) [Address 00E116]
B
1
Name
Functions
After reset
R
R
W
0: Data is not latched yet
and a clock-run-in is not
determined.
1: Data is latched and a
clock-run-in is determined.
—
Indeterminate
Caption data latch
completion flag 1
(DSC20)
1
2
0
Fix this bit to “1.”
Test bit
R
R
R
R
W
—
—
W
0
Indeterminate
Read-only
0: F2
1: F1
Indeterminate
0
Field determination
flag(DSC23)
0: Method (1)
1: Method (2)
Vertical synchronous signal
(Vsep) generating method
selection bit (DSC24)
4
5
0: Match
1: Mismatch
Indeterminate
R
—
V-pulse shape
determination flag (DSC25)
0
R
R
6
7
W
—
Fix this bit to “0.”
Test bit
Indeterminate
Read-only
Definition of fields 1 (F1) and 2 (F2)
Hsep
Vsep
Hsep
Vsep
F2:
F1:
Fig. 8.10.5 Data Slicer Control Register 2
Rev.1.00 Nov 01, 2002 page 51 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.10.2 Clamping Circuit and Low-pass Filter
The clamp circuit clamps the sync chip part of the composite video
signal input from the CVIN pin. The low-pass filter attenuates the noise
of the clamped composite video signal. The CVIN pin to which com-
posite video signal is input requires an external capacitor (0.1 µF)
coupling. Pull down the CVIN pin with a resistor of hundreds of kilo-
ohms to 1 MΩ. In addition, we recommend installing a simple low-
pass filter externally, using a resistor and a capacitor at the CVIN pin
(refer to Figure 8.10.1).
Composite s
Measure LOW period
Timing
signal
Vsep signal
8.10.3 Sync Slice Circuit
This circuit takes out a composite sync signal from the output signal
of the low-pass filter.
A Vsep signal is generated at a rising of the timing signal
immediately after the LOW level width of the composite
sync signal exceeds a certain time.
8.10.4 Synchronous Signal Separation Circuit
This circuit separates a horizontal synchronous signal and a vertical
synchronous signal from the composite sync signal taken out in the
sync slice circuit.
Fig. 8.10.6 Vsep Generating Timing (method 2)
(1) Horizontal Synchronous Signal (Hsep)
A one-shot horizontal synchronizing signal Hsep is generated at
the falling edge of the composite sync signal.
(2) Vertical Synchronous Signal (Vsep)
As a Vsep signal generating method, it is possible to select one of
the following 2 methods by using bit 4 of data slicer control regis-
ter 2 (address 00E116).
•Method 1 The LOW level width of the composite sync signal is
measured. If this width exceeds a certain time, a Vsep
signal is generated in synchronization with the rising
of the timing signal immediately after this LOW level.
•Method 2 The LOW level width of the composite sync signal is
measured. If this width exceeds a certain time, it is
detected whether a falling of the composite sync sig-
nal exits or not in the LOW level period of the timing
signal immediately after this LOW level. If a falling
exists, a Vsep signal is generated in synchronization
with the rising of the timing signal (refer to Figure
8.10.6).
Figure 8.10.6 shows a Vsep generating timing. The timing signal shown
in the figure is generated from the reference clock which the timing
generating circuit outputs.
Reading bit 5 of data slicer control register 2 permits determinating
the shape of the V-pulse portion of the composite sync signal. As
shown in Figure 8.10.7, when the A level matches the B level, this bit
is “0.” In the case of a mismatch, the bit is “1.”
Rev.1.00 Nov 01, 2002 page 52 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.10.5 Timing Signal Generating Circuit
This circuit generates a reference clock which is 832 times as large
as the horizontal synchronous signal frequency. It also generates
various timing signals on the basis of the reference clock, horizontal
synchronous signal and vertical synchronizing signal. The circuit
operates by setting bit 0 of data slicer control register 1 (address
00E016) to “1.”
Bit 5 of
DSC2
0
1
1
The reference clock can be used as a display clock for the OSD
function in addition to the data slicer. The HSYNC signal can be used
as a count source instead of the composite sync signal. However,
when the HSYNC signal is selected, the data slicer cannot be used. A
count source of the reference clock can be selected by bit 2 of data
slicer control register 1 (address 00E016).
Composite
sync signal
A
B
For pins HLF, connect a resistor and a capacitor as shown in Figure
8.10.1. Make the length of wiring which is connected to these pins as
short as possible to prevent a leakage current from being generated.
Note: It takes a few tens of milliseconds until the reference clock becomes
stable after the data slicer and the timing signal generating circuit are
started. In this period, various timing signals, Hsep signals and Vsep sig-
nals become unstable. For this reason, take stabilization time into con-
sideration when programming.
Fig. 8.10.7 Determination of V-pulse Waveform
Rev.1.00 Nov 01, 2002 page 53 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.10.6 Data Slice Line Specification Circuit
(1) Specification of data slice line
(3) Field determination
The field determination flag can be read out by bit 3 of data slicer
This circuit determines the lines on to which caption data is super-
imposed. Data can be sliced for line 21 and one arbitrary line in
both field (2 lines total per field). The caption position register (ad-
dress 00E616) is used for each setting (refer to Table 8.10.1).
The counter is reset at the falling edge of Vsep and is incremented
by 1 every Hsep pulse. When the counter value matches the value
specified by bits 4 to 0 of the caption position register, this Hsep is
sliced.
control register 2. This flag changes at the falling edge of Vsep.
The values of “0016” to “1F16” can be set in the caption position
register (when setting only one arbitrary line). Figure 8.10.8 shows
the signals in the vertical blanking interval. Figure 8.10.9 shows
the structure of the caption position register.
(2) Specification of line to set slice voltage
Table 8.10.1 shows which field and line generates the reference
slice voltage for the clock run-in pulse of each line. The field to
generate slice voltage is specified by bit 1 of data slicer control
register 1. The line to generate slice voltage for one field is speci-
fied by bits 6 and 7 of the caption position register (refer to
Table 8.10.1).
Vertical blanking interval
Video signal
Composite
video signal
1 appropriate line is set by
the caption position register
(when setting line 19)
Vsep
Hsep
Line 21
Count value to be set in the caption position register (“0F 16” in this case)
Magnified
drawing
Hsep
Clock run-in
Start bit + 16-bit data
Start bit
Composite video
signal
Window for
deteminating
clock-run-in
Fig. 8.10.8 Signals in Vertical Blanking Interval
Rev.1.00 Nov 01, 2002 page 54 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Caption Position Register
b7 b6 b5 b4 b3 b2 b1 b0
Caption Position Register (CPS) [Address 00E616
]
R W
R W
Name
Functions
After reset
0
B
0
to
4
Caption position
bits(CPS0 to CPS4)
5
0: Data is not latched yet and a
clock-run-in is not determined.
1: Data is latched and a
Indeterminate
R
—
Caption data latch
completion flag 2
(CPS5)
clock-run-in is determined.
W
6, 7
Refer to the corresponding
Table (Table 8.10.1).
0
R
Slice line mode
specification bits
(in 1 field) (CPS6, CPS7)
Fig. 8.10.9 Caption Position Register
Table 8.10.1 Specification of Data Slice Line
CPS
Field and Line to Be Sliced Data
• Both fields of F1 and F2
• Line 21 and a line specified by bits 4 to 0 of CPS
(total 2 lines) (See note 2)
Field and Line to Generate Slice Voltage
• Field specified by bit 1 of DSC1
b7
0
b6
0
• Line 21 (total 1 line)
• Both fields of F1 and F2
• A line specified by bits 4 to 0 of CPS
(total 1 line) (See note 3)
• Field specified by bit 1 of DSC1
• A line specified by bits 4 to 0 of CPS
(total 1 line) (See note 3)
0
1
1
1
0
1
• Both fields of F1 and F2
• Line 21 (total 1 line)
• Field specified by bit 1 of DSC1
• Line 21 (total 1 line)
• Both fields of F1 and F2
• Line 21 and a line specified by bits 4 to 0 of CPS
(total 2 lines) (See note 2)
• Field specified by bit 1 of DSC1
• Line 21 and a line specified by bits 4 to 0 of CPS
(total 2 lines) (See note 2)
Notes 1: DSC1 is data slicer control register 1.
CPS is caption position register.
2: Set “0016” to “1016” to bits 4 to 0 of CPS.
3: Set “0016” to “1F16” to bits 4 to 0 of CPS.
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8.10.7 Reference Voltage Generating Circuit
and Comparator
8.10.8 Start Bit Detecting Circuit
This circuit detects a start bit at the line decided in the data slice line
specification circuit.
The composite video signal clamped by the clamping circuit is input
to the reference voltage generating circuit and the comparator.
The detection of a start bit is as follows:.
➀ A sampling clock is generated by dividing the reference clock out-
put by the timing signal.
(1) Reference voltage generating circuit
This circuit generates a reference voltage (slice voltage) by us-
ing the amplitude of the clock run-in pulse in the line specified by
the data slice line specification circuit. Connect a capacitor be-
tween the VHOLD pin and the VSS pin, and make the length of
wiring as short as possible to prevent a leakage current from be-
ing generated.
➀ A clock run-in pulse is detected by the sampling clock.
➀ After detection of the pulse, a start bit pattern is detected from the
comparator output.
8.10.9 Clock Run-in Determination Circuit
This circuit determinates clock run-in by counting the number of pulses
in a window of the composite video signal.
(2) Comparator
The reference clock count value in one pulse cycle is stored in bits 3
to 7 of the clock run-in detect register (address 00E416). Read out
these bits after the occurrence of a data slicer interrupt (refer to
“8.10.12 Interrupt Request Generating Circuit”).
The comparator compares the voltage of the composite video
signal with the voltage (reference voltage) generated in the refer-
ence voltage generating circuit, and converts the composite video
signal into a digital value.
Figure 8.10.10 shows the structure of the clock run-in detect register.
Clock Run-in Detect Register
b7 b6 b5 b4 b3 b2 b1 b0
Clock run-in detect register (CRD) [Address 00E416
]
R
R
After reset
0
W
—
B
Name
Test bits
Functions
0
to
2
Read-only
3
Clock run-in detection
Number of reference clocks to
be counted in one clock run-in
pulse period.
0
R
—
to bit(CRD3 to CRD7)
7
Fig. 8.10.10 Clock Run-in Detect Register
Rev.1.00 Nov 01, 2002 page 56 of 136
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8.10.10 Data Clock Generating Circuit
This circuit generates a data clock synchronized with the start bit
detected in the start bit detecting circuit. The data clock stores cap-
tion data to the 16-bit shift register. When the 16-bit data has been
stored and the clock run-in determination circuit determines clock
run-in, the caption data latch completion flag is set. This flag is reset
at a falling edge of the vertical synchronous signal (Vsep).
Data Clock Position Register
b7 b6 b5 b4 b3 b2 b1 b0
0
1
0
Data clock position register (DPS) [Address 00E516]
R
R
W
W
B
0
Name
Functions
After reset
1
Fix this bit to “0.”
1
Fix this bit to “1.”
Fix this bit to “0.”
0
R
W
2
3
0
1
R
R
W
W
Data clock position set
bits (DPS3 to DPS7)
4
to
7
0
Fig. 8.10.11 Data Clock Position Register
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8.10.11 16-bit Shift Register
8.10.12 Interrupt Request Generating Circuit
The interrupt requests as shown in Table 8.10.3 are generated by a
combination of the following bits; bits 6 and 7 of the caption position
register (address 00E616). Read out the contents of data registers 1
to 4 and the contents of bits 3 to 7 of the clock run-in detect register
after the occurrence of a data slicer interrupt request.
The caption data converted into a digital value by the comparator is
stored into the 16-bit shift register in synchronization with the data
clock. The contents of the high-order 8 bits of the stored caption data
can be obtained by reading out data register 2 (address 00E316) and
data register 4 (address 00CF16). The contents of the low-order 8
bits can be obtained by reading out data register 1 (address 00E216)
and data register 3 (address 00CE16), respectively. These registers
are reset to “0” at a falling edge of Vsep. Read out data registers 1
and 2 after the occurrence of a data slicer interrupt (refer to “8.10.12
Interrupt Request Generating Circuit”).
Table 8.10.2 Contents of Caption Data Latch Completion Flag and 16-bit Shift Register
Slice Line Specification Mode
CPS
Contents of Caption Data Latch Completion Flag
Contents of 16-bit Shift Register
Completion Flag 1
(bit 0 of DSC2)
Completion Flag 2
(bit 5 of CPS)
Caption Data
Caption Data
Registers 3, 4
Registers 1, 2
bit 7
bit 6
A line specified by
bits 4 to 0 of CPS
16-bit data of line 21
16-bit data of a line specified by
bits 4 to 0 of CPS
0
0
Line 21
A line specified by
bits 4 to 0 of CPS
16-bit data of a line specified
by bits 4 to 0 of CPS
0
1
1
1
0
1
Invalid
Invalid
Invalid
Invalid
Line 21
Line 21
16-bit data of line 21
16-bit data of line 21
A line specified by
bits 4 to 0 of CPS
16-bit data of a line specified by
bits 4 to 0 of CPS
CPS: Caption position register
DSC2: Data slicer control register 2
Table 8.10.3 Occurence Sources of Interrupt Request
Caption position register
Occurence Souces of Interrupt Request at End of Data Slice Line
After slicing line 21
b7
b6
0
0
1
After a line specified by bits 4 to 0 of CPS
After slicing line 21
0
1
1
After slicing line 21
Rev.1.00 Nov 01, 2002 page 58 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.10.13 Synchronous Signal Counter
The synchronous signal counter counts the composite sync signal
taken out from a video signal in the data slicer circuit or the vertical
synchronous signal Vsep as a count source.
The latch value can be obtained by reading out the sync pulse counter
register (address 00E916). A count source is selected by bit 5 of the
sync pulse counter register.
The synchronous signal counter is used when bit 0 of PWM mode
register 1 (address 020816) is set to “0.”
13
The count value in a certain time (T time) generated by f(XIN)/2 or
13
f(XIN)/2 is stored into the 5-bit latch. Accordingly, the latch value
Figure 8.10.12 shows the structure of the sync pulse counter and
Figure 8.10.13 shows the synchronous signal counter block diagram.
changes in the cycle of T time. When the count value exceeds “1F16,”
“1F16” is stored into the latch.
Sync Pulse Counter Register
b7 b6 b5 b4 b3 b2 b1 b0
Sync pulse counter register (HC) [Address 00E916
]
R
R
W
—
Name
Functions
After reset
0
B
0
to
4
Count value (HC0 to HC4)
5
Count source (HC5)
0: HSYNC signal
1: Composite sync signal
0
0
R
R
W
—
6, 7 Nothing is assigned. These bits are write disable bits.
“0.”
When these bits are read out, the values are
Fig. 8.10.12 Sync Pulse Counter Register
f(XIN)/213
Composite
sync signal
Reset
Counter
5-bit counter
H
SYNC signal
Sync pulse
counter register
Latch (5 bits)
b5
Selection gate : connected to black
side when reset.
Data bus
Fig. 8.10.13 Synchronous Signal Counter Block Diagram
Rev.1.00 Nov 01, 2002 page 59 of 136
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8.11 OSD FUNCTIONS
Table 8.11.1 outlines the OSD functions.
This microcomputer incorporates an OSD circuit of 32 characters ✕
2 lines. There are also 2 display modes which are selected in block
units. The display modes are selected by bits 0 and 1 of block con-
trol register i (i = 1 and 2).
The features of each mode are described below.
Table 8.11.1 Features of Each Display Mode
Display mode
Parameter
CC mode
(Closed caption mode)
OSD mode (Border OFF)
(On-screen display mode)
Number of display characters
Dot structure
32 characters ✕ 2 lines
16 ✕ 26 dots (Character display area : 16 ✕ 20 dots)
254 kinds
16 ✕ 20 dots
Kinds of characters
Kinds of character sizes
1 kinds
8 kinds
Pre-divide ratio (See note)
Dot size
✕ 2 (fixed)
✕ 2, ✕ 3
1T
Smooth italic, under line, flash
1 screen : 8 kinds (per character unit)
1 screen : 8 kinds (per character unit)
C
✕ 1/2H
1T
C
✕ 1/2H, 1T
C ✕ 1H, 2TC ✕ 2H, 3TC ✕ 3H
Attribute
Border (black)
Character font coloring
Character background coloring
OSD output
R, G, B
Possible (per character unit)
Auto solid space function
Window function
Horizontal: 128 levels, Vertical: 512 levels
Possible
Raster coloring
Function
Display position
Display expansion (multiline display)
Notes 1: The divide ratio of the frequency divider (the pre-divide circuit) is referred as “pre-divide ratio” hereafter.
2: The character size is specified with dot size and pre-divide ratio (refer to 8.11.2 Dot Size).
Rev.1.00 Nov 01, 2002 page 60 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
The OSD circuit has an extended display mode. This mode allows
multiple lines (3 lines or more) to be displayed on the screen by inter-
rupting the display each time one line is displayed and rewriting data
in the block for which display has been terminated by software.
Figure 8.11.1 shows the configuration of an OSD character. Figure
8.11.2 shows the block diagram of the OSD circuit. Figure 8.11.3
shows the OSD control register. Figure 8.11.4 shows block control
register i.
CC mode
OSD mode
16 dots
16 dots
Blank area✕
Underline area✕
Blank area✕
✕: Displayed only in CCD mode.
Fig. 8.11.1 Configuration of OSD Character Display Area
Rev.1.00 Nov 01, 2002 page 61 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
HSYNC VSYNC
Standard clock
Data slicer clock
for OSD f(OSC)
Control registers for OSD
OSD Control circuit
OSD bort control register
(address 00CB16)
OSD control register
(address 00D016)
Horizontal position register
Block control register i
Vertical position register i
Window register i
I/O polarity control register
Raster color register
(address 00D116)
(addresses 00D216, 00D316)
(addresses 00D416, 00D516)
(addresses 00D616, 00D716)
(address 00D816)
(address 00D916)
OSD control register 2
(address 00DB16)
RAM for OSD
2 bytes ✕ 32 characters ✕ 2 lines
ROM for OSD
16 dots ✕ 20 dots ✕ 254 characters
Shift register
16-bit
Output circuit
R
G
B
OUT
Data bus
Fig. 8.11.2 Block Diagram of OSD Circuit
Rev.1.00 Nov 01, 2002 page 62 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
OSD Control Register
b7 b6 b5b4 b3 b2b1 b0
0 0
OSD control register (OC) [Address 00D016
Functions
]
After reset
R
W
B
Name
0 : All-blocks display off
1 : All-blocks display on
OSD control bit
(OC0) (See note 1)
0
R W
R W
R W
R W
0
1
2
Automatic solid space 0 : OFF
0
0
0
1 : ON
control bit (OC1)
Window control bit
(OC2)
0 : OFF
1 : ON
CC mode clock
selection bit (OC3)
0 : Data slicer clock
1 : Internal oscillating clock f(osc)
3
4
OSD mode clock
selection bit (OC4)
0
R W
0 : Data slicer clock
1 : Internal oscillating clock f(osc)
R W
R W
5, 6 Fix these bits to “0.”
0
0
0 : Divide ratio by the block
control register
1 : Pre-divide ratios = ✕✕1
for blocks 1 and 2
Pre-divide ratio
7
selection bit (OC7)
(See note 2)
Notes 1:Even this bit is switched during display, the display screen
remains unchanged until a rising (falling) of the next VSYNC
2:This bit's priority is higher than BCi4 of Block Control
Register i setting.
Fig. 8.11.3 OSD Control Register
Rev.1.00 Nov 01, 2002 page 63 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Block Control register i
b7 b6 b5b4 b3 b2b1 b0
Block control register i (BCi) (i=1, 2) [Addresses 00D216 and 00D316]
After reset
B
Name
Functions
R W
R W
b1 b0
Indeterminate
0, 1 Display mode
selection bits
(BCi0, BCi1)
0 0: Display OFF
0 1: CC mode
1 0: OSD mode (Border OFF)
1 1: OSD mode (Border ON)
(See note 1)
b4 b3 b2 Pre-divide Ratio Dot Size
Indeterminate
Indeterminate
2, 3 Dot size selection
bits (BCi2, BCi3)
R W
R W
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
0
1
✕ 2
4
Pre-divide ratio
selection bit (BCi4)
✕ 3
0: 2 value output control
1: 3 value output control
(notes 3)
5
6
OUToutput control bit
(BCi5)
Indeterminate
Indeterminate
R W
R W
Vertical display start
position control bit
(BCi6)
BC16: Block 1
BC26: Block 1
BC17: Window top boundary
BC27: Window bottom boundary
Indeterminate
7
Window top/bottom
boundary control bit
(BCi7)
R W
Notes 1: Tc is OSD clock cycle divided in pre-divide circuit.
2: H is HSYNC.
3: Refer to the corresponding figure 8.11.18.
Fig. 8.11.4 Block Control Register i
Rev.1.00 Nov 01, 2002 page 64 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.11.1 Display Position
Blocks are displayed in conformance with the following rules:
• When the display position of block 1 is overlapped with that of block
2 (Figure 8.11.5 (b)), block 1 is displayed in front.
The display positions of characters are specified in units called
“blocks.” There are 2 blocks: blocks 1 and 2. Up to 32 characters can
be displayed in each block (refer to “8.11.5 Memory for OSD”).
The display position of each block can be set in both horizontal and
vertical directions by software.
• When another block display position appears while one block is
displayed (Figure 8.11.5 (c)), the block with a larger set value as
the vertical display start position is displayed.
The display start position in the horizontal direction can be selected
for all blocks from 128-step display positions in units of 4TOSC (TOSC
= OSD oscillation cycle).
The display start position in the vertical direction for each block can
be selected from 512-step display positions in units of 1 TH ( TH =
HSYNC cycle).
(HP)
VP1
Block 1
Block 2
VP2
(a) Example when each block is separated
(HP)
VP1 = VP2
Block 1
(Block 2 is not displayed)
(b) Example when block 2 overlaps with block 1
(HP)
VP1
VP2
Block 1
Block 2
(c) Example when block 2 overlaps in process of block 1
Note: VP1 or VP2 indicates the vertical display start position of display block 1 or 2.
Fig. 8.11.5 Display Position
Rev.1.00 Nov 01, 2002 page 65 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
The vertical display start position is determined by counting the hori-
zontal sync signal (HSYNC). At this time, when VSYNC and HSYNC are
positive polarity (negative polarity), the count starts at the rising edge
(falling edge) of HSYNC signal after the fixed cycle of the rising edge
(falling edge) of VSYNC signal. So the interval from the rising edge
(falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC
signal needs enough time (2 machine cycles or more) to avoid jitters.
The polarity of HSYNC and VSYNC signals can be select with the I/O
polarity control register (address 00D816).
8 machine cycles
or more
VSYNC signal input
0.25 to 0.50 [µs]
( at f(XIN) = 8MHz)
VSYNC control
signal in
microcomputer
Period of counting
HSYNC signal
(See note 2)
HSYNC
signal input
8 machine cycles
or more
1
2
3
4
5
Not count
When bits 0 and 1 of the I/O polarity control register
(address 00D816) are set to “1” (negative polarity)
Notes 1 : The vertical position is determined by counting falling edge of HSYNC
signal after rising edge of VSYNC control signal in the microcomputer.
2 : Do not generate falling edge of HSYNC signal near rising edge of
VSYNC control signal in microcomputer to avoid jitter.
3 : The pulse width of VSYNC and HSYNC needs 8 machine cycles or
more.
Fig. 8.11.6 Supplement Explanation for Display Position
Rev.1.00 Nov 01, 2002 page 66 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
The vertical display start position for each block can be set in 512
steps (where each step is 1TH (TH: HSYNC cycle)) as values “0016” to
“FF16” in vertical position register i (i = 1 and 2) (addresses 00D416
and 00D516) and values “0” or “1” in bit 6 of block control register i (i
= 1 and 2) (addresses 00D216 and 00D316). The vertical position
register is shown in Figure 8.11.7.
The vertical display start position of both blocks can be switched in
each step to 1TH or 2TH by setting values “0” or “1” in bit 1 of OSD
control register 2 (address 00DB16).
Vertical Position Register i
b7 b6 b5 b4 b3 b2 b1 b0
Vertical position register i (VPi) (i = 1 and 2) [Addresses 00D416, 00D516
]
After reset
Name
B
Functions
R
R
W
W
Vertical display start
position control bits
(VPi0 to VPi7)
Vertical display start position =
Inderterminate
0
to
7
TH
5 (BCi6 ✕ 162 + n)
(n: setting value, TH: HSYNC cycle,
(See note)
BCi6: bit 6 of block control register i)
Notes 1: Set values except “0016” to VPi when BCi6 is “0.”
2: When OS21 of OSD control register 2 = “0”, TH = 1HSYNC
,
and OS21 of OSD control register 2 = “1”, TH = 2HSYNC
.
Fig. 8.11.7 Vertical Position Register i (i = 1 and 2)
Rev.1.00 Nov 01, 2002 page 67 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
The horizontal display start position is common to all blocks, and can
be set in 128 steps (where 1 step is 4TOSC, TOSC being the OSD
oscillation cycle) as values “0016” to “FF16” in bits 0 to 6 of the hori-
zontal position register (address 00D116). The horizontal position reg-
ister is shown in Figure 8.11.8.
Horizontal Position Register
b7 b6 b5b4 b3 b2b1 b0
Horizontal position register (HP) [Address 00D116
]
B
0
Name
Functions
After reset R W
Horizontal display start position
4Tosc ✕ n
Horizontal display start
0
R W
to position control bits
6
(n: setting value, Tosc: OSD oscillation cycle)
(HP0 to HP6)
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
7
0
R —
Note: The setting value synchronizes with the V SYNC
.
Fig. 8.11.8 Horizontal Position Register
Notes 1 : 1TC (TC : OSD clock cycle divided in pre-divide circuit) gap occurs
between the horizontal display start position set by the horizontal
position register and the most left dot of the 1st block. Accordingly,
when 2 blocks have different pre-divide ratios, their horizontal dis-
play start position will not match.
2 : The horizontal start position is based on the OSD clock source cycle
selected for each block. Accordingly, when 2 blocks have different
OSD clock source cycles, their horizontal display start position will
not match.
3 : When setting “0016” to the horizontal position register, it needs an
approximately 62TOSC (= Tdef) interval from a rising edge (when nega-
tive polarity is selected) of HSYNC signal to the horizontal display start
position.
H
SYNC
1T
C
T
def
4TOSC ✕ N
Note 1
Block 2 (Pre-divide ratio = 2, clock source = data slicer clock)
1T
C
Block 3 (Pre-divide ratio = 3, clock source = data slicer clock)
1T
C
Tdef’
4TOSC’ ✕ N
Note 2
Block 4 (Pre-divide ratio = 3, clock source = OSC1)
: Value of horizontal position register (decimal notation)
N
1TC : OSD clock cycle divided in pre-divide circuit
TOSC : OSD oscillation cycle
Tdef : 62 TOSC
Fig. 8.11.9 Notes on Horizontal Display Start Position
Rev.1.00 Nov 01, 2002 page 68 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.11.2 Dot Size
The pre-divide ratio is specified by bit 7 of the OSD control register
(address 00D016) and bit 4 of block control register i (addresses
00D216 and 00D316) .
The dot size can be selected in block units. The vertical dot size is
determined by dividing HSYNC in the vertical dot size control circuit.
The horizontal dot size is determined by dividing the following clock
in the horizontal dot size control circuit : the clock gained by dividing
the OSD clock source (data slicer clock, f (OSC) in the pre-divide
circuit. The clock cycle divided in the pre-divide circuit is defined as
1TC.
When bit 7 of the OSD control register (address 00D016) is set to
"0," the double or triple pre-divide ratio can be chosen per block unit
by bit 4 of block control register i. And then, when it is set to "1", the
pre-divide ratio increases 1 time (both blocks 1 and 2). The pre-di-
vided dot size can be specified per block unit by bits 2 and 3 of block
control register i.
The dot size of each block is specified by bits 2 to 4 of block control
register i.
Refer to Figure 8.11.4 for the structure of the block control register.
The block diagram of the dot size control circuit is shown in Figure
8.11.10.
Clock cycle
= 1TC
f (OSC)
“0”
“1”
“1”
“0”
Synchronous
Horizontal dot size
control circuit
Cycle ✕ 2
circuit
OC7
OC3 or OC4
Data slicer clock
BCi4
Cycle ✕ 3
Pre-divide circuit
Vertical dot size
control circuit
H
SYNC
OSD control circuit
Note: To use data slicer clock, set bit 0 of data slicer control register 1 to “1.”
Fig. 8.11.10 Block Diagram of Dot Size Control Circuit
1 dot
1T
C
1T
C
2T
C
3TC
Scanning line of F1(F2 )
Scanning line of F2(F1 )
1/2 H
1H
2H
3H
Fig. 8.11.11 Definition of Dot Sizes
Rev.1.00 Nov 01, 2002 page 69 of 136
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8.11.3 Clock for OSD
The following 2 types of clocks can be selected for OSD display:
• Data slicer clock output from the data slicer (approximately 26 MHz)
• OSD clock f (osc) generated based on the reference clock from
pin XIN.
The OSD clock for each block can be selected by bits 3 and 4 of the
clock source control register (addresses 00D016).
Data slicer clock
(See note)
“0”
Data slicer circuit
CC mode block
OC3
OC4
“1”
“0”
OSD mode block
f(osc)
“1”
Note : To use data slicer clock, set bit 0 of data slicer control register 1 to “1.”
When use the clock for OSD generated based on the main clock,
set the bit 0 of the clock control register 1 to “0.”
Fig. 8.11.12 Block Diagram of OSD Selection Circuit
Clock control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
0
0
0
Clock control register 1 (CC1) [Address 00CD16]
B
0
Name
Functions
0: Operation
W
W
R
R
After reset
0
System clock generating
circuit control bit (CC10)
1: Stop
W
0
R
1 to
7
Fix these bits to "0"
Fig. 8.11.13 Clock control register 1
Rev.1.00 Nov 01, 2002 page 70 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.11.4 Field Determination Display
When displaying a block with vertical dot size of 1/2H, the differ-
ences in the synchronizing signal waveform of the interlacing system
determine whether the field is odd or even. The dot lines 0 and 1
(refer to Figure 8.11.15), corresponding to each field, are displayed
alternately.
In the following, the field determination standard for the case where
both the horizontal sync signal and the vertical sync signal are nega-
tive-polarity inputs will be explained. A field determination is deter-
mined by detecting the time from a falling edge of the horizontal sync
signal until a falling edge of the VSYNC control signal (refer to Figure
8.11.6) in the microcomputer and then comparing this time with the
time of the previous field. When the time is longer than the previous
time, it is regarded as an even field. When the time is shorter, it is
regarded as an odd field
The contents of this field can be read out by the field determination
flag (bit 6 of the I/O polarity control register at address 00D816). A dot
line is specified by bit 5 of the I/O polarity control register (refer to
Figure 8.11.15).
However, the field determination flag read out from the CPU is fixed
to “0” for even fields or “1” for odd fields, regardless of bit 5.
I/O Polarity Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
I/O polarity control register (PC) [Address 00D816
]
After reset
0
B
0
Name
Functions
R
R
W
W
H
SYNC input polarity
switch bit (PC0)
0 : Positive polarity input
1 : Negative polarity input
1
2
3
5
0 : Positive polarity input
1 : Negative polarity input
0
0
0
0
R
R
R
R
W
W
W
W
V
SYNC input polarity
switch bit (PC1)
0 : Positive polarity output
1 : Negative polarity output
R, G, B output polarity
switch bit (PC2)
OUT1 output polarity
switch bit (PC3)
0 : Positive polarity output
1 : Negative polarity output
Display dot line selection
bit (PC5) (See note)
0 : “
” at even field
” at odd field
” at even field
” at odd field
“
1 : “
“
6
Field determination flag
(PC6)
0 : Even field
1 : Odd field
1
0
R
R
—
W
4, 7
Fix these bits to “0.”
Note: Refer to the corresponding figure. 8.11.15
Fig. 8.11.14 I/O Polarity Control Register
Rev.1.00 Nov 01, 2002 page 71 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Both HSYNC cignal and VSYNC signal are negative-polarity input
Field
determination
flag(Note)
Display dot line
selection bit
Display dot line
H
SYNC
Field
Odd
V
V
SYNC and
SYNC
(n –1) field
(Odd-numbered)
control
0.25 to 0.50[ µs] at
T1
T2
T3
signal
in microcom-
puter
f(XIN) = 8 MHz
0
1
Dot line 1
Dot line 0
(n) field
(Even-numbered)
Even
Odd
0 (T2 > T1)
1 (T3 < T2)
Upper :
V
SYNC signal
Lower :
V
SYNC control
0
1
Dot line 0
Dot line 1
signal in
micro-
computer
(n +1) field
(Odd-numbered)
When using the field determination flag, be sure to set bit 0 of the PWM mode register 1 (address 0208 16) to “0.”
3 4 7 8 10 1112 1314 1516 3 4 9 10 1112 1314 1516
1
2
5
6
9
1
2
5
6 7 8
1
2
1
2
3
3
4
4
5
6
5
6
7
7
8
9
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
10
11
12
13
14
15
16
17
18
19
20
OSD mode
“0,”
” font is displayed at even field, the
24
25
I/O polarity control register can be read as the
field determination flag : “1” is read at odd field,
“0” is read at even field.
26
CC mode
OSD ROM font configuration diagram
Note : The field determination flag changes at a rising edge of the V SYNC control signal (negative-polarity input) in
the microcomputer.
Fig. 8.11.15 Relation between Field Determination Flag and Display Font
Rev.1.00 Nov 01, 2002 page 72 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.11.5 Memory for OSD
(1) OSD ROM
There are 2 types of memory for OSD: OSD ROM used to store
character dot data and OSD RAM used to specify the characters and
colors to be displayed.
The dot pattern data for OSD characters is stored in the OSD ROM.
To specify the kinds of character font, it is necessary to write the
character code into the OSD RAM.
Data of the character font is specified as shown in Figure 8.11.16.
OSD ROM : addresses 1140016 to 13BFF16
OSD RAM : addresses 080016 to 087F16
OSD ROM address of character font data
OSD ROM
AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
address bit
Font
bit
Line number/character
0
0
1
Line number
Character code
code/font bit
= “0A16” to “1D16”
Line number
Character code
Font bit
= “0016” to “FF16” (“7F16” and “8016” cannot be used)
= 0 : Left area
1 : Right area
Data in
OSD
ROM
Line
number
Left
area
Right
area
b7
b0 b7
b0
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
000016
7FF016
7FF816
601C16
600C16
600C16
600C16
600C16
601C16
7FF816
7FF016
630016
638016
61C016
60E016
607016
603816
601C16
600C16
000016
Character font
Fig. 8.11.16 Character Font Data Storing Address
Rev.1.00 Nov 01, 2002 page 73 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Notes 1 : The 80-byte addresses corresponding to the character code “7F16”
and “8016” in the OSD ROM are the test data storing area. Set data
to the area as follows.
2 : The character code “0916” is used for “transparent space” when
displaying Closed Caption.
Therefore, set “0016” to the 40-byte addresses corresponding to the
character code “0916.”
<Test data storing area>
addresses 1100016 + (4 + 2n) ✕✕10016 + FE16 to
1100016 + (5 + 2n) ✕✕10016 + 0116
(n = 0 to 19)
<Transparent space font data storing area>
addresses 1100016 + (4 + 2n) ✕✕10016 + 1216 to
1100016 + (4 + 2n) ✕✕10016 + 1316
(n = 0 to 19)
(1)Mask version (M37151M6/M8/MA/MC/MF-XXXFP)
Set “FF16” to the area (This sample has test data in this area but the actual
product will have different data.) When using our font editor, the test data is
written automatically.
(2)EPROM version (M37151EFFP)
Set the test data to the area. When using our font editor, the test data
is written automatically.
addresses 1141216 and 1141316
addresses 1161216 and 1161316
addresses 1381216 and 1381316
addresses 13A1216 and 13A1316
✕M37151EFFP
<“7F16”> address (test data)
114FE16 (0916), 114FF16 (5116)
116FE16 (0016), 116FF16 (5216)
118FE16 (1216), 118FF16 (5316)
11AFE16 (0016), 11AFF16 (5416)
11CFE16 (2416), 11CFF16 (5516)
11EFE16 (0016), 11EFF16 (5616)
120FE16 (8816), 120FF16 (5716)
122FE16 (0016), 122FF16 (5816)
124FE16 (9016), 124FF16 (5916)
126FE16 (4816), 126FF16 (5A16)
128FE16 (2416), 128FF16 (5B16)
12AFE16 (0016), 12AFF16 (5C16)
12CFE16 (2416), 12CFF16 (5D16)
12EFE16 (4816), 12EFF16 (5E16)
130FE16 (0016), 130FF16 (5F16)
132FE16 (4816), 132FF16 (5016)
134FE16 (9016), 134FF16 (5116)
136FE16 (0016), 136FF16 (5216)
138FE16 (0116), 138FF16 (5316)
13AFE16 (8016), 13AFF16 (5416)
<“8016”> address (test data)
1150016 (9016), 1150116 (A116)
1170016 (0016), 1170116 (A216)
1190016 (4816), 1190116 (A316)
11B0016 (0016), 11B0116 (A416)
11D0016 (2416), 11D0116 (A516)
11F0016 (0016), 11F0116 (A616)
1210016 (1216), 1210116 (A716)
1230016 (0016), 1230116 (A816)
1250016 (0916), 1250116 (A916)
1270016 (0016), 1270116 (AA16)
1290016 (8116), 1290116 (AB16)
12B0016 (1816), 12B0116 (AC16)
12D0016 (0016), 12D0116 (AD16)
12F0016 (4216), 12F0116 (AE16)
1310016 (2416), 1310116 (AF16)
1330016 (0016), 1330116 (B016)
1350016 (8116), 1350116 (B116)
1370016 (0C16), 1370116 (B216)
1390016 (0616), 1390116 (B316)
13B0016 (0016), 13B0116 (B416)
Rev.1.00 Nov 01, 2002 page 74 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
(2) OSD RAM
The RAM for OSD is allocated at addresses 080016 to 087F16, and
is divided into a display character code specification part, color code
1 specification part, and color code 2 specification part for each block.
Table 8.11.2 shows the contents of the OSD RAM.
For example, to display the first character position (the left edge) in
block 1, write the character code in address 080016 and write the
color code at 082016.
The structure of the OSD RAM is shown in Figure 8.11.17.
Table 8.11.2 Contents of OSD RAM
Display Position (from left)
Color Code Specification
Block
Character Code Specification
080016
080116
082016
082116
1st character
2nd character
080216
:
081D16
082216
:
083D16
3rd character
Block 1
:
30th character
081E16
081F16
084016
084116
083E16
083F16
086016
086116
31st character
32nd character
1st character
2nd character
3rd character
084216
:
086216
:
:
Block 2
30th character
085D16
087D16
31st character
32nd character
085E16
085F16
087E16
087F16
Rev.1.00 Nov 01, 2002 page 75 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Blocks 1, 2
b7
b0
b7
b0
RA6 RA5 RA4 RA3 RA2 RA1 RA0 RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0
(See note 1)
Color code 1
CC mode
Character code (See note 3)
OSD mode
Bit name
Bit
Bit name
Function
Function
RF0
RF1
RF2
RF3
RF4
RF5
RF6
RF7
RA0
Character code
Character code in
OSD ROM
Character code
Character code in
OSD ROM
0: Color signal output OFF
1: Color signal output ON
Control of
character color R
Control of
0: Color signal output OFF
1: Color signal output ON
Control of
character color R
Control of
RA1
RA2
RA3
RA4
RA5
RA6
character color G
Control of
character color G
Control of
character color B
character color B
(See note 2)
OUT control
(See note 2)
OUT control
Flash control
0: Flash OFF
1: Flash ON
Control of
background color R
Control of
0: Color signal output OFF
1: Color signal output ON
0: Underline OFF
1: Underline ON
0: Italic OFF
Underline control
Italic control
background color G
Control of
1: Italic ON
background color B
Notes 1: Read value of bits 7 of the color code is “0.”
2: For OUT control, refer to “8.11.8 OUT signal.”
3: “7F16” and “8016” cannot be used as character code.
Fig. 8.11.17 Bit structure of OSD RAM
Rev.1.00 Nov 01, 2002 page 76 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.11.6 Character color
8.11.7 Character background color
The character background color can be displayed in the character
display area only in the OSD mode. The character background color
for each character is specified by the color code.
The 7 kinds of color are specified by bits 0 (R), 1 (G), and 2 (B) of the
color code.
The color for each character is displayed by the color code.
The 7 kinds of color are specified by bits 0 (R), 1 (G), and 2 (B) of the
color code.
Note : The character background color is displayed in the following parts:
(character display area)–(character font)–(border).
Accordingly, the character background color does not mix with these
color signals.
Rev.1.00 Nov 01, 2002 page 77 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.11.8 OUT signal
The OUT signal is used to control the luminance of the video sig-
nal. The output waveform of the OUT signal is controlled by RA3 of
the OSD RAM. The setting values for controlling OUT and the cor-
responding output waveform are shown in Figure 8.11.18.
A'
A
Block Control
Display Register i
OUT control
(RA3 of OSD RAM)
Output Waveform (A-A')
Mode
OUT Output
Control Bit (b5)
Vcc
0V
0
1
0
1
0
1
0
1
OUT=FONT/BORDER
OUT=AREA
0
Vcc
0V
OSD
Vcc
OUT=FONT/BORDER
OUT=FONT/BORDER
OUT=FONT
0V
1
Vcc
About 0.6Vcc
0V
Vcc
0V
0
Vcc
OUT=AREA
0V
CC
Vcc
OUT=FONT
0V
1
Vcc
OUT=FONT
About 0.6Vcc
0V
Notes 1: FONT/BORDER.....In the OSD mode (Border ON), OUT outputs to the area of font and border.
In the OSD mode (Border OFF), OUT outputs to only the font area.
AREA.....................OUT outputs to entire display area of character.
FONT.....................In the CC mode, OUT outputs to font area.
2: When the automatic solid space function is OFF in the CC mode, AREA outputs according to bit 3 of color code.
When it is ON, the solid space is automatically output by a character code regardless of RA3.
3: The OUT signal's three-level outputs are useful only during positive polarity output.
4: For three-level OUT signal outputs, set Port P3 Direction Register (address 00C716) bit 2 to 1.
5: For three-level OUT signal outputs, set about 2 kΩ resistor between OUT pin and VSS
.
Fig. 8.11.18 Setting Value for Controlling OUT and Corresponding Output Waveform
Rev.1.00 Nov 01, 2002 page 78 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.11.9 Attribute
The attributes (border, flash, underline, italic) are controlled accord-
ing to the character font. The attributes to be controlled are different
depending on each mode.
CC mode ..................... Flash, underline, italic (per character unit)
OSD mode .................. Border (per character unit)
(1) Underline
The underline is output at the 23th and 24th dots in the vertical direc-
tion only in the CC mode. The underline is controlled by RA5 of the
OSD RAM. The color of the underline is the same color as that of the
character font.
(2) Flash
The character font and the underline are flashed only in the CC mode.
The flash is controlled by RA4 of OSD RAM. In the character font
part, the character output part is flashed, but the character back-
ground part is not flashed. The flash cycle is based on the VSYNC
count.
• VSYNC cycle ✕✕48 ≈ 800 ms (at display ON)
• VSYNC cycle ✕✕16 ≈ 267 ms (at display OFF)
(3) Italic
The italic is made by slanting the font stored in the OSD ROM to the
right only in the CC mode. The italic is controlled by RA6 of OSD
RAM.
Display examples of the italic and underline are shown in Figure
8.11.19, using “R.”
Notes 1: When setting both the italic and the flash, the italic character flashes.
2: The boundary of character color is displayed in italic. However, the
boundary of character background color is not affected by the italic
(refer to Figure 8.11.20).
3: The adjacent character (one side or both sides) to an italic character
is displayed in italic even when the character is not specified to be
displayed in italic (refer to Figure 8.11.20).
4: Italics display cannot be used at pre-divided ratio 1 setting .
Rev.1.00 Nov 01, 2002 page 79 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Color code
Color code
Bit 6
Bit 5
Bit 6
Bit 5
(RA6)
(RA5)
(RA6)
(RA5)
0
0
0
1
(a) Ordinary
(b) Under line
Color code
Bit 6
Bit 5
(RA6)
(RA5)
1
0
(c) Italic (pre-divide ratio = 2)
Color code
Bit 6
Bit 5
Bit 4
(RA6)
(RA5)
(RA4)
flash
flash
flash
1
1
1
ON
ON
OFF
OFF
(d) Under line amd Italic and flash
Fig. 8.11.19 Example of Attribute Display (in CC Mode)
Rev.1.00 Nov 01, 2002 page 80 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
26th chracter
(Refer to “8.11.9 Notes 2, 3”)
(Refer to “8.11.9 Notes 2, 3”)
RA6 of
OSD RAM
1
0
0
1
1
0
1
Notes 1 : The dotted line is the boundary of character color.
2 : When bit 1 of OSD control register is “0.”
Fig. 8.11.20 Example of Italic Display
Rev.1.00 Nov 01, 2002 page 81 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Notes 1 : The border dot area is the shaded area as shown in Figure 8.11.21.
2 : When the border dot overlaps on the next character font, the charac-
ter font has priority (refer to Figure 8.11.23 A).
(4) Border
The border is output around the character font (all bordered) in the
OSD mode only. The border ON/OFF is controlled by bit 0 and 1 of
block control register i (refer to Figure 8.11.4).
When the border dot overlaps the next character back ground, the
border has priority (refer to Figure 8.11.23 B).
3 : The border in vertical out of the character area is not displayed (refer
to Figure 8.11.23).
The OUT signal is used for border output.
The horizontal size (x) of the border is 1TC (OSD clock cycle divided
in pre-divide circuit) regardless of the character font dot size. The
vertical size (y) differs depending on the screen scan mode and the
vertical dot size of the character font.
OSD mode
16 dots
Character
font area
All bordered
1 dot width of border
1 dot width of border
Fig. 8.11.21 Example of Border Display
y
x
Scan mode
Normal scan mode
Bi-scan mode
Vertical dot size of
character font
1/2H
1H, 2H, 4H, 8H
1H, 2H, 3H
1Tc (OSD clock cycle divided in pre-divide circuit)
1/2H
Border dot size
Horizontal size (x)
Vertical size (y)
1H
1H
Fig. 8.11.22 Horizontal and Vertical Size of Border
Rev.1.00 Nov 01, 2002 page 82 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Character boundary Character boundary Character boundary
B
A
B
Fig. 8.11.23 Border Priority
Rev.1.00 Nov 01, 2002 page 83 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Notes 1: An OSD interrupt does not occur at the end of display when the block
is not displayed. In other words, if a block is set to display off by the
display control bit of the block control register (addresses 00D216,
00D316), an OSD interrupt request does not occur (refer to Figure
8.11.24 (A)).
8.11.10 Multiline Display
This microcomputer can display 2 lines on the CRT screen by dis-
playing 2 blocks at different vertical positions. In addition, it can dis-
play up to 16 lines by using OSD interrupts.
2: When another block display appears while one block is displayed, an
OSD interrupt request occurs only once at the end of the second
block display (refer to Figure 8.11.24 (B)).
3: On the screen setting window, an OSD interrupt occurs even at the
end of the CC mode block (display off) out of window (refer to Figure
8.11.24 (C)).
An OSD interrupt request occurs at the point at which that display of
each block has been completed. In other words, when a scanning
line reaches the point of the display position (specified by the vertical
position registers) of a certain block, the character display of that
block starts, and an interrupt occurs at the point at which the scan-
ning line exceeds the block.
Block 1 (on display)
Block 1 (on display)
“OSD interrupt request”
“OSD interrupt request”
“OSD interrupt request”
Block 2 (on display)
Block 1’ (on display)
Block 2’ (on display)
Block 2 (on display)
“OSD interrupt request”
Block 1’ (off display)
Block 2’ (off display)
No
“OSD interrupt request”
“OSD interrupt request”
“OSD interrupt request”
No
“OSD interrupt request”
On display (OSD interrupt request occurs
at the end of block display)
Off display (OSD interrupt request does
not occur at the end of block display)
(A)
Block 1
Block 2
“OSD interrupt request”
“OSD interrupt request”
Block 1
Block 2
No
“OSD interrupt request”
“OSD interrupt request”
Block 1’
“OSD interrupt request”
Window
In CC mode
(C)
(B)
Fig. 8.11.24 Note on Occurence of OSD Interrupt
Rev.1.00 Nov 01, 2002 page 84 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Notes : The character code “0916” is used for “transparent space” when dis-
playing Closed Caption.
8.11.11 Automatic Solid Space Function
This function automatically generates the solid space (OUT blank
output) of the character area in the CC mode.
Therefore, set “0016” to the 40-byte addresses corresponding to the
character code “0916.”
The solid space is output in the following areas:
<Transparent space font data storing area>
addresses 1100016 + (4 + 2n) ✕✕10016 + 1216 to
1100016 + (4 + 2n) ✕✕10016 + 1316
(n = 0 to 19)
• Any character area except character code “0916 ”
• Character area on the left and right sides of the above character
This function is turned on and off by bit 1 of the OSD control register
(refer to Figure 8.11.3).
addresses 1141216 and 1141316
addresses 1161216 and 1161316
addresses 1381216 and 1381316
addresses 13A1216 and 13A1316
When setting the character code “0516” as the character A, “0616” as the character B.
(OSD RAM)
• • •
05 09 09090 6 06
06 09 09 06
16
16
16
16
16
16
16
16
16
16
(Display screen)
• • •
1st
2nd
31st
character
32nd
character
No blank output
character character
The solid space is automatically output on the left side of the 1st character and on the right side
of the 32nd character by setting the 1st and 32nd of the character code.
Fig. 8.11.25 Display Screen Example of Automatic Solid Space
Rev.1.00 Nov 01, 2002 page 85 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.11.12 Window Function
The setting value per one step of the top and bottom window borders
can be switched to either 1TH or 2TH by setting “0” or “1” to bit 1 of
OSD control register 2 (address 02DB16).
This function sets the top and bottom boundaries for display limits
on a screen. The window function is valid only in the CC mode. The
top boundary is set by the window register 1 and bit 7 of block con-
trol register 1. The bottom boundary is set by window register 1 and
bit 7 of block control register 2. This function is turned on and off by
bit 2 of the OSD control register (refer to Figure 8.11.3).
Window registers 1 and 2 are shown in Figures 8.11.27 and 8.11.28.
Top
boundary
of window
OSD mode
CC mode
A B
C D E
F
G H
I
J
CC mode
CC mode
K L M N O
Window
P
Q R
S
T
Y
OSD mode
U V W X
Bottom
boundary
of window
Screen
Fig. 8.11.26 Example of Window Function
Rev.1.00 Nov 01, 2002 page 86 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Window Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Window register 1 (WN1) [Address 00D616]
After reset
Name
B
Functions
R
R
W
W
Window top border position =
TH 5 (BC17 ✕ 162 + n)
(n: setting value, TH: HSYNC cycle,
Inderterminate
Window top boundary
control bits
(WN10 to WN17)
0
to
7
BC17: bit 7 of block control register 1)
Notes 1: Set values except “0016” to WN1 when BC17 is “0.”
2: Set values fit for the following condition: WN1 < WN2.
3: When OC21 of OSD control register 2 is “0”, TH is 1 HSYNC.
And when “1”, TH is 2 HSYNC.
Fig. 8.11.27 Window Register 1
Window Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Window register 2 (WN2) [Address 00D716]
After reset
Name
B
Functions
R
R
W
Window bottom border position =
TH 5 (BC27 ✕✕162 + n)
(n: setting value, TH: HSYNC cycle,
Inderterminate
Window bottom boundary
control bits
(WN20 to WN27)
W
0
to
7
BC27: bit 7 of block control register 2)
Notes 1: Set values fit for the following condition: WN1 < WN2.
2: When OC21 of OSD control register 2 is “0”, TH is 1 HSYNC.
And when “1”, TH is 2 HSYNC.
Fig. 8.11.28 Window Register 2
Rev.1.00 Nov 01, 2002 page 87 of 136
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8.11.13 OSD Output Pin Control
The OSD output pins R, G, B and OUT can also function as ports
P52–P55. Set the corresponding bit of the OSD port control register
(address 00CB16) to “0” to specify these pins as OSD output pins, or
to “1” to specify as the general-purpose port P5.
The input polarity of the HSYNC and VSYNC, and the output polarity of
signals R, G, B, OUT can be specified with the I/O polarity control
register (address 00D8). Set bits to “0” to specify positive polarity;
“1” to specify negative polarity (refer to Figure 8.11.14).
The structure of the OSD port control register is shown in Figure
8.11.29.
OSD Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0
OSD port control register (PF) [Address 00CB16
]
1 0
0 0
R
R
B
Name
Functions
After reset
0
W
—
0, 1
Fix these bits to “0.”
2
3
4
Port P5
selection bit (PF2)
2
output signal
0 : B signal output
1 : Port P5 output
0
0
0
0
R
R
R
R
W
W
W
W
2
Port P5
3
output signal
0 : G signal output
1 : Port P5 output
selection bit (PF3)
3
0 : R signal output
1 : Port P5 output
Port P54 output signal
4
selection bit (PF4)
Port P5 output signal
5
0 : OUT signal output
1 : Port P5 output
5
6
7
selection bit (PF5)
5
Fix this bit to “0.”
—
R
W
W
Indeterminate
0
Fix this bit to “1.”
Fig. 8.11.29 OSD Port Control Register
Rev.1.00 Nov 01, 2002 page 88 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.11.14 Raster Coloring Function
An entire screen (raster) can be colored by setting bits 4 to 0 of the
raster color register. Since each of the R, G, B, OUT pins can be
switched to raster coloring output, 8 raster colors can be obtained.
When the character color/character background color overlaps with
the raster color, the color (R, G, B, OUT), specified for the character
color/character background color, takes priority over the raster color.
This ensures that character color/character background color is not
mixed with the raster color.
The raster color register is shown in Figure 8.11.30, an example of
raster coloring is shown in Figure 8.11.31.
Raster Color Register
b7 b6 b5b4 b3 b2b1 b0
0 0 0
Raster color register (RC) [Address 00D916]
Functions
After reset
R
W
B
Name
0 : No output
1 : Output
0
R W
R W
R W
R W
0
1
2
3
Raster color R
control bit (RC0)
Raster color G
control bit (RC1)
0 : No output
1 : Output
0
0
0
Raster color B
control bit (RC2)
0 : No output
1 : Output
Raster color OUT
control bit (RC3)
0 : No output
1 : Output
4
R W
R W
Fix these bits to “0.”
0
0
to
6
7
Port function
selection bit (RC7)
0 : XCIN,
XCOUT
1 : P26, P27
Fig. 8.11.30 Raster Color Register
Rev.1.00 Nov 01, 2002 page 89 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
: Character color “RED” (R + OUT)
: Border color “BLACK” (OUT)
: Background color “MAGENTA” (R + B + OUT)
: Raster color “BLUE” (B + OUT)
A'
A
H
SYNC
OUT
Signals
across
A-A'
R
G
B
Fig. 8.11.31 Example of Raster Coloring
Rev.1.00 Nov 01, 2002 page 90 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.12 SOFTWARE RUNAWAY DETECT FUNCTION
This microcomputer has a function to decode undefined instructions
to detect a software runaway.
When an undefined op-code is input to the CPU as an instruction
code during operation, the following processing is done.
➀ The CPU generates an undefined instruction decoding signal.
➀ The device is internally reset due to the undefined instruction de-
coding signal.
➀ As a result of internal reset, the same reset processing as in the
case of ordinary reset operation is done, and the program restarts
from the reset vector.
Note, however, that the software runaway detecting function cannot
be disabled.
φ
SYNC
AD
AD
H
,
Address
Data
PC
?
01,S
01,S–1
01,S–2
FFFE16
FFFF16
L
?
PCH
PC
L
PS
AD
L
ADH
Reset sequence
Undefined instruction decoding signal
occurs.Internal reset signal occurs.
: Undefined instruction decode
?
PC
S
: Invalid
: Program counter
: Stack pointer
AD
L, ADH
: Jump destination address of reset
Fig.8.12.1 Sequence at Detecting Software Runaway Detection
Rev.1.00 Nov 01, 2002 page 91 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.13. RESET CIRCUIT
Power on
When the oscillation of a quartz-crystal oscillator or a ceramic reso-
nator is stable and the power source voltage is 5 V ± 10 %, hold the
RESET pin at LOW for 2 µs or more, then return to HIGH. Then, as
shown in Figure 8.13.2, reset is released and the program starts from
the address formed by using the content of address FFFF16 as the
high-order address and the content of the address FFFE16 as the
low-order address. The internal states of the microcomputer at reset
are shown in Figures 8.2.2 to 8.2.5.
4.5 V
0.9 V
Power source voltage 0 V
Reset input voltage 0 V
An example of the reset circuit is shown in Figure 8.13.1.
The reset input voltage must be kept 0.9 V or less until the power
source voltage surpasses 4.5 V.
Vcc
1
5
RESET
M51953AL
4
0.1 µF
3
Vss
Microcomputer
Fig.8.13.1 Example of Reset Circuit
XIN
φ
RESET
Internal RESET
SYNC
AD
AD
H
L
,
Address
Data
01, S-1
01, S-2
FFFE FFFF
?
?
01, S
Reset address from the vector table
AD
L
ADH
?
?
?
?
?
Notes 1 : f(XIN) and f(φ) are in the relation : f(XIN) = 2·f (φ).
2 : A question mark (?) indicates an undefined state that
depends on the previous state.
32768 count of XIN
clock cycle (See note 3)
3 : Immediately after a reset, timer 3 and timer 4 are
connected by hardware. At this time, “FF16” is set
in timer 3 and “0716” is set to timer 4. Timer 3 counts down
with f(XIN)/16, and reset state is released by the timer 4
overflow signal.
Fig.8.13.2 Reset Sequence
Rev.1.00 Nov 01, 2002 page 92 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.14 CLOCK GENERATING CIRCUIT
(3) Low-speed Mode
This microcomputer has 2 built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance with
the resonator manufacturer’s recommended values. No external re-
sistor is needed between XIN and XOUT since a feed-back resistor
exists on-chip. However, an external feed-back resistor is needed
between XCIN and XCOUT. When using XCIN-XCOUT as sub-clock,
clear bits 5 and 6 of the OSD control register to “0.” To supply a clock
signal externally, input it to the XIN (XCIN) pin and make the XOUT
(XCOUT) pin open. When not using XCIN clock, connect the XCIN to
VSS and make the XCOUT pin open.
If the internal clock is generated from the sub-clock (XCIN), a low
power consumption operation can be realized by stopping only the
main clock XIN. To stop the main clock, set bit 6 (CM6) of the CPU
mode register (00FB16) to “1.” When the main clock XIN is restarted,
the program must allow enough time for oscillation to stabilize.
Note that in the low-power-consumption mode the XCIN-XCOUT
drivability can be reduced, allowing even lower power consumption.
To reduce the XCIN-XCOUT drivability, clear bit 5 (CM5) of the CPU
mode register (00FB16) to “0.” At reset, this bit is set to “1” and strong
drivability is selected to help the oscillation to start. When executing
an STP instruction, set this bit to “1” by software before initiating the
instruction.
The OSD clock can be chosen to be the data slicer clock (approx. 26
MHz) that is output from the data slicer.
After reset has completed, the internal clock φ is half the frequency of
XIN. Immediately after poweron, both the XIN and XCIN clock start
oscillating. To set the internal clock φ to low-speed operation mode,
set bit 7 of the CPU mode register to “1.”
Microcomputer
X
CIN
X
COUT
X
IN
XOUT
FILT
8.14.1 OSCILLATION CONTROL
(1) Stop Mode
Rf
Rd
The built-in clock generating circuit is shown in Figure 120. When the
STP instruction is executed, the internal clock f stops at HIGH. At the
same time, timers 3 and 4 are connected by hardware and “FF16” is
set in timer 3 and “0716” is set in timer 4. Select f(XIN)/16 or f(XCIN)/
16 as the timer 3 count source (set both bit 0 of timer mode register
2 and bit 6 at address 00C716 to “0” before the execution of the STP
instruction). Moreover, set the timer 3 and timer 4 interrupt enable
bits to disabled (“0”) before execution of the STP instruction. The
oscillator restarts when an external interrupt is accepted. However,
the internal clock f keeps its HIGH level until timer 4 overflows, allow-
ing time for oscillation stabilization when a ceramic resonator or a
quartz-crystal oscillator is used.
0.01µF
C1
C
CIN
C
COUT
C
IN
COUT
Fig.8.14.1 Ceramic Resonator Circuit Example
Microcomputer
X
CIN
X
COUT
X
IN
XOUT
By settimg bit 7 of timer return setting register (address 00CC16) to
“1, ” an arbitrarary value can be set to timer 3 and timer 4.
Bit 7 of clock control register 3 (address 020216) can switch Port P10
pin and the CLKCONT. When CLKCONT pin is selected, “H” is output
normally. When an extenal interrupt is recieved in the STP state, the
CLKCONT pin goes back to “H” output.
Open
Open
External oscillation
circuit or external
pulse
External oscillation
circuit
Vcc
Vss
Vcc
Vss
(2) Wait Mode
When the WIT instruction is executed, the internal clock φ stops in
the HIGH level but the oscillator continues running. This wait state is
released at reset or when an interrupt is accepted (See note). Since
the oscillator does not stop, the next instruction can be executed
immediately.
Fig.8.14.2 External Clock Input Circuit Example
Note: In the wait mode, the following interrupts are invalid.
• VSYNC interrupt
• OSD interrupt
• All timer interrupts using external clock input from port pin as count
source
• All timer interrupts using f(XIN)/2 or f(XCIN)/2 as count source
• All timer interrupts using f(XIN)/4096 or f(XCIN)/4096 as count source
• f(XIN)/4096 interrupt
• Multi-master I2C-BUS interface interrupt
• Data slicer interrupt
• A-D conversion interrupt
Rev.1.00 Nov 01, 2002 page 93 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Clock control register 3
b7 b6 b5 b4 b3 b2 b1 b0
Clock control register 3 (CC3) [Address 021216
]
0
0
0
0
0 0
B
Name
Functions
After reset
W
W
R
R
0
0 to
4
Fix these bits to "0"
0: 0V–VCC
1: 0V–About 0.6VCC
5
R
R,G,B,OUT Output amplitude
level selection bit (CC35)
0
W
6
7
R
R
0
0
W
W
Fix this bit to "0"
P10
function-selection bit
(Note)
(CC37)
0: Clock control signal
1: P10 I/O
Note: When used as the clock control signal, set the Port 1 Direction Register
(address 00C316) bit 0 to 1.
Fig.8.14.3 Clock Control Register 3
Rev.1.00 Nov 01, 2002 page 94 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
XCIN
XCOUT
OSC1 clock selection
bits (See notes 1, 4)
Timer 3 count
stop bit (See notes 1, 2)
Timer 4 count
stop bit (See notes 1, 2)
XIN
XOUT
“1”
“1”
“0”
Timer 3
Timer 4
1/8
1/2
“0”
Internal system clock
selection bit (See notes 1, 3)
Timer 3
count source selection bit (See notes 1, 2)
Timing φ
(Internal clock)
Main clock (XIN–XOUT) stop bit (See notes 1, 3)
Internal system clock selection bit
(See notes 1, 3)
Q
S
R
S
Q
Q
S
R
Reset
WIT
instruction
R
STP instruction
STP instruction
Reset
Interrupt disable flag I
Interrupt request
Notes 1 : The value at reset is “0.”
2 : Refer to timer mode register 2.
3 : Refer to the CPU mode register.
4 : Refer to the OSD control register.
Fig.8.14.4 Clock Generating Circuit Block Diagram
Rev.1.00 Nov 01, 2002 page 95 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
High-speed operation start
mode
Reset
STP instruction
WIT instruction
8 MHz oscillating
8 MHz oscillating
32 kHz oscillating
f(φ) = 4 MHz
8 MHz stopped
32 kHz stopped
φ is stopped (“H”)
32 kHz oscillating
φ is stopped (“H”)
Timer operating
Interrupt
Interrupt (See note 1)
External INT
External INT,
timer interrupt,
or SI/O interrupt
CM7 = 0
CM7 = 1
WIT instruction
Interrupt
STP instruction
8 MHz oscillating
32 kHz oscillating
φ is stopped (“H”)
Timer operating
(See note 3)
8 MHz oscillating
32 kHz oscillating
f(φ) = 16kHz
8 MHz stopped
32 kHz stopped
φ is stopped (“H”)
Interrupt (See note 2)
CM6 = 0
The program must
allow time for 8 MHz
oscillation to stabilize
CM6 = 1
STP instruction
WIT instruction
Interrupt
8 MHz stopped
32 kHz oscillating
φ is stopped (“H”)
Timer operating
(See note 3)
8 MHz stopped
32 kHz stopped
φ = stopped (“H”)
8 MHz stopped
32 kHz oscillating
f(φ) = 16 kHz
Interrupt (See note 2)
CPU mode register
(Address : 00FB16
)
CM6 : Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
CM7 : Internal system clock selection bit
0 : XIN-XOUT selected (high-speed mode)
1 : XCIN-XCOUT selected (low-speed mode)
The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. The φ indicates the internal clock.
Notes 1: When the STP state is ended, a delay of approximately 8 ms is automatically generated by timer 3 and timer 4.
2: The delay after the STP state ends is approximately 2s.
3: When the internal clock φ divided by 8 is used as the timer count source, the frequency of the count source is 2 kHz.
Fig.8.14.5 State Transitions of System Clock
Rev.1.00 Nov 01, 2002 page 96 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.15 OSD CLOCK GENERATING CIRCUIT
When generate OSD clock based on main clock, connect capacity to
FILT pin.
In order to generate normally oscillation frequency for OSD shown in
Table 8.15.1, be sure to set the main clock f (XIN) to 8MHz. Then, set
up not any values other than these.
Set bit 0 of the clock control register 1 (address 00CD16) to operate
OSD clock generating circuit “0.” Clock control register 1 (address
00CD16) is shown in Fig.8.15.3. Then, clock frequency for OSD is set
up by the clock frequency register (address 021016).
Clock frequency setting register is shown in Fig.8.15.2.
Table.8.15.1 OSD Clock frequency
Clock frequency
setting register
(address 021016
0C
0D
)
OSD clock
frequency
26 MHz
28 MHz
FLIT
C1
Fig.8.15.1 Display Oscillation Circuit
Clock frequency set register
b7 b6 b5 b4 b3 b2 b1 b0
Clock frequency set register(CFS) [Address 021016
]
BFunctions
Name
After reset
R
R
W
W
Clock frequency (Note)
0 to
7
Clock frequency bit
(CFS 0 to 7)
0E
Setting value(Limitation) Frequency(MHz)
0C
0D
26
28
Note: Do not set other than the values shown above to CFS.
Then, must to use at f(XIN) = 8 MHz.
Fig.8.15.2 Clock Frequency Register
Clock control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
0
0
0
Clock control register 1 (CC1) [Address 00CD16
]
BFunctions
Name
W
R
After reset
0
W
R
System clock generating
circuit control bit (CC10)
0: Operation
1: Stop
0
W
0
R
1 to
7
Fix these bits to "0"
Fig.8.15.3 Clock Control Register 1
Rev.1.00 Nov 01, 2002 page 97 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.16 AUTO-CLEAR CIRCUIT
When a power source is supplied, the auto-clear function will oper-
8.17 ADDRESSING MODE
The memory access is reinforced with 17 kinds of addressing modes.
ate by connecting the following circuit to the RESET pin.
Refer to SERIES 740 <Software> User’s Manual for details.
8.18 MACHINE INSTRUCTIONS
There are 71 machine instructions. Refer to SERIES 740 <Software>
User’s Manual for details.
Circuit example 1
9. TECHNICAL NOTES
• The divide ratio of the timer is 1/(n+1).
Vcc
RESET
•
Even though the BBC and BBS instructions are executed imme-
diately after the interrupt request bits are modified (by the pro-
gram), those instructions are only valid for the contents before
the modification. At least one instruction cycle is needed (such as
an NOP) between the modification of the interrupt request bits
and the execution of the BBC and BBS instructions.
After the ADC and SBC instructions are executed (in the decimal
mode), one instruction cycle (such as an NOP) is needed before
the SEC, CLC, or CLD instruction is executed.
Vss
•
Circuit example 2
•
•
An NOP instruction is needed immediately after the execution of
a PLP instruction.
Vcc
RESET
In order to avoid noise and latch-up, connect a bypass capacitor
(≈ 0.1µF) directly between the VCC pin–VSS pin and the VCC pin–
CNVSS pin, using a thick wire.
Vss
•
Characteristic value, margin of operation, etc. of versions with
built-in EPROM and built-in mask ROM may differ from each other
within the limits of the electrical characteristics in terms of manu-
facturing process, built-in ROM, difference of a layout pattern,
etc.
Note : Make the level change from “L” to “H” at the point at
which the power source voltage exceeds the specified
voltage.
Carry out and check an examination equivalent to the system
evaluation examination carried out on the EPROM version when
replacing it with the mask ROM version.
Fig.8.16.1 Auto-clear Circuit Example
Rev.1.00 Nov 01, 2002 page 98 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
10. ABSOLUTE MAXIMUM RATINGS
Symbol
Parametear
Conditions
Ratings
–0.3 to 6
Unit
V
VCC
Power source voltage VCC
VI
VI
Input voltage
Input voltage
CNVSS
–0.3 to 6
V
All voltages are based
on VSS.
P00–P07, P10–P16, P20–P27,
______
–0.3–VCC + 0.3
V
P30, P31, P50, P51, RESET, CVIN
Output transistors are
cut off.
VO
Output voltage P06, P07, P10–P16, P20–P27,
P30, P31, P52–P55
–0.3–VCC + 0.3
0 to 1 (See note 1)
0 to 2 (See note 2)
V
IOH
IOL1
Circuit current P10–P16, P20–P27, P30, P31,
P52–P55,
mA
mA
Circuit current P00–P07, P10–P15, P16, P20–P23
P52–P55,
IOL2
IOL4
Pd
Circuit current P11–P14, P30, P31
Circuit current P24–P27
Power dissipation
0 to 6 (See note 2)
0 to 10 (See note 3)
550
mA
mA
mW
°C
Ta = 25 °C
Topr
Tstg
Operating temperature
–10 to 70
Storage temperature
–40 to 125
°C
11. RECOMMENDED OPERATING CONDITIONS (Ta = –10 °C to 70 °C, VCC = 5 V ± 10 %, unless otherwise noted)
Limits
Symbol
Unit
Parametear
Min.
4.5
Typ.
5.0
Max.
5.5
V
V
VCC
Power source voltage (See note 4)
Power source voltage
VSS
0
0
0
VIH1
HIGH Input voltage
P00–P07, P10–P16, P20–P27, P30, P31, P50, P51,
0.8VCC
VCC
V
______
RESET
VIH2
HIGH Input voltage
SCL1, SCL2, SCL3, SDA1, SDA2 , SDA3
0.7VCC
VCC
0.4VCC
0.3VCC
V
V
V
2
(When using I C-BUS)
VIL1
VIL2
LOW Input voltage
LOW Input voltage
P00
–
P07, P10
–
P16, P20
–
P27, P30, P31
0
0
SCL1, SCL2, SCL3, SDA1, SDA2, SDA3
2
______
(When using I C-BUS)
VIL3
LOW Input voltage (See note 6)
P50, P51,RESET, TIM2, TIM3, INT1,
0
0.2VCC
V
INT2, INT3, SIN, SCLK
IOH
HIGH average output current (See note1)
HIGH average output current (See note2)
P10
P0
–
P16, P20
P0 , P1 , P1
P14, P30, P31
P27
–
P27, P30, P31, P52
–
P55
P5
1
2
mA
mA
IOL1
IOL2
0
–
7
0
5
, P1 , P2 P2 , P5
6
0
–
3
2
–
5
LOW average output current (See note 2) P11
LOW average output current (See note 3) P24
–
–
6
mA
IOL3
10
8.1
mA
f(XIN)
Oscillation frequency (for CPU operation)
(See note 5)
XIN
7.9
29
8.0
32
MHz
f(XCIN)
fhs1
fhs2
fhs3
fhs4
VI
Oscillation frequency (for sub-clock operation) XCIN
35
100
kHz
kHz
MHz
kHz
kHz
V
Input frequency
TIM2, TIM3, INT1, INT2, INT3
Input frequency
SCLK
1
Input frequency
SCL1, SCL2
447.5
16.206
2.5
Input frequency
Horizontal sync. signal of video signal
CVIN
15.262
1.5
15.734
2.0
Input amplitude video signal
Rev.1.00 Nov 01, 2002 page 99 of 136
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M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
12. ELECTRIC CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, T
a
= –10 °C to 70 °C, unless otherwise noted)
Limits
Unit
Test
Symbol
Parametear
Test conditions
Min.
Typ.
Max.
circuit
OSD OFF
Data slicer OFF
15
30
VCC = 5.5V,
f(XIN) = 8 MHz
mA
OSD ON
Data slicer ON
30
60
45
VCC = 5.5V, f(XIN) = 0,
f(XCIN) = 32kHz,
µA
200
System operation
Wait mode
OSD OFF, Data slicer OFF,
Low-power dissipation mode set
1
2
3
Power source current
ICC
(CM5 = “0”, CM6 = “1”)
VCC = 5.5 V, f(XIN) = 8 MHz
mA
µA
1
25
2
100
VCC = 5.5 V, f(XIN) = 0,
f(XCIN) = 32 kHz,
Low-power dissipation mode set
(CM5 = “0”, CM6 = “1”)
Stop mode
VCC = 5.5V, f(XIN) = 0,
f(XCIN) = 0
1
10
2.4
HIGH output voltage P10–P16, P20–P27,
P30, P31, P52–P55,
VCC = 4.5 V
IOH = –0.5 mA
VOH
VOL
V
V
LOW output voltage P00–P07, P10,
P15, P16, P20–P23,
VCC = 4.5 V
IOL = 0.5 mA
0.4
3.0
P52–P55
LOW output voltage P24– P27
VCC = 4.5 V
IOL = 10.0 mA
LOW output voltage P11–P14, P30, P32
VCC = 4.5 V
VCC = 5.0 V
IOL = 3 mA
IOL = 6 mA
0.4
0.6
1.3
Hysteresis (See note 6)
0.5
VT+ –VT–
V
____________
RESET, P50, P51, INT1, INT2,
INT3, TIM2, TIM3, SIN, SCLK, SCL1,
SCL2, SCL3, SDA1, SDA2, SDA3
HIGH input leak current
4
4
5
VCC = 5.5 V
VI = 5.5 V
µA
µA
5
5
IIZH
IIZL
P00–P07, P10–P16, P20–P27,
P30, P31, _R__E___S__E___T_, P50, P51,
HIGH input leak current
VCC = 5.5 V
VI = 0 V
P00–P07, P10–P16, P20–P27, P30,
P31, P50, P51, _R__E__S___E__T__
2
RBS
I C-BUS • BUS switch connection resistor
130
Ω
VCC = 4.5 V
(between SCL1 and SCL2, SDA1 and SDA2)
Notes 1: The total current that flows out of the IC must be 20 mA or less.
2: The total input current to IC (IOL1 + IOL2) must be 30 mA or less.
3: The total average input current for ports P24–P27 and AVCC–VSS to IC must be 20 mA or less.
4: Connect 0.1 µF or more capacitor externally between the power source pins VCC–VSS so as to reduce power source noise.
Also connect 0.1 µF or more capacitor externally between the pins VCC–CNVSS.
5: P06, P07, P16, P23, P24, P25 have hysteresis when used as interrupt input pins or timer input pins. P11–P14, P30, P31 have hysteresis when used as multi-
master I2C-BUS interface ports. P20–P22 have hysteresis when used as serial I/O pins.
6: Pin names in each parameter are described as below.
(1) Dedicated pins: dedicated pin names.
(2) Double-/triple-function ports
• Same limits: I/O port name.
• Functions other than ports vary from I/O port limits: function pin name.
Rev.1.00 Nov 01, 2002 page 100 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
+
Power source voltage
Icc
4.5 V
Vcc
1
2
A
Vcc
XIN
8.00 MHz
XOUT
Each output pin
OH
OH
I
V
V
or
or
Vss
Vss
OL
OL
V
I
OH
Using ceramic oscillator, it changes into a state of
operation and measure the current.
After setting each output pin to HIGH level when measuring V
OL
and to LOW level when measuring V , each pin is measured.
5.5 V
3
4
5.0 V
Vcc
IZH
Vcc
I
or
IZL
I
A
Each input pin
Each input pin
Vss
5.5 V
or
Vss
0 V
5
4.5V
Vcc
BS
I
SCL1 or SDA1
A
BS
R
SCL2 or SDA2
BS
V
Vss
BS
R
BS BS
= V /I
Fig.12.1 Measurement Circuits
Rev.1.00 Nov 01, 2002 page 101 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
13. A-D CONVERTER CHARACTERISTICS
(VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
Max.
7
—
—
—
Resolution
bits
LSB
LSB
LSB
LSB
Non-linearity error
±1.5
±0.9
2
Differencial non-linearity error
Zero transition error
V0T
VFST
IOL (SUM) = 0 mA
Full-scale transition error
–2
2
14. MULTI-MASTER I C-BUS BUS LINE CHARACTERISTICS
Standard clock mode High-speed clock mode
Symbol
Parameter
Unit
Min.
4.7
4.0
4.7
Max.
Min.
1.3
Max.
tBUF
Bus free time
µs
µs
µs
ns
µs
µs
ns
ns
µs
µs
tHD; STA
tLOW
Hold time for START condition
LOW period of SCL clock
0.6
1.3
tR
Rising time of both SCL and SDA signals
Data hold time
1000
300
20+0.1Cb
0
300
0.9
tHD; DAT
tHIGH
0
HIGH period of SCL clock
4.0
0.6
tF
Falling time of both SCL and SDA signals
Data set-up time
20+0.1Cb
100
300
tSU; DAT
tSU; STA
tSU; STO
250
4.7
4.0
Set-up time for repeated START condition
Set-up time for STOP condition
0.6
0.6
Note: Cb = total capacitance of 1 bus line
SDA
tSU;STO
tHD;STA
tBUF
tLOW
tR
tF
Sr
P
P
S
SCL
S : Start condition
Sr : Restart condition
P : Stop condition
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
2
Fig.14.1 Definition Diagram of Timing on Multi-master I C-BUS
Rev.1.00 Nov 01, 2002 page 102 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
15. PROM PROGRAMMING METHOD
16. DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM product:
• Mask ROM Order Confirmation Form
• Mark Specification Form
The built-in PROM of the One Time PROM version (blank) and the
built-in EPROM version can be read or programmed with a general-
purpose PROM programmer using a special programming adapter.
• Data to be written to ROM, in EPROM form (three identical copies)
or FDK
Product
Name of Programming Adapter
PCA7450FP
M37151EFFP
When using EPROM:
Three sets of 32-pin DIP Type 27C101
The PROM of the One Time PROM version (blank) is not tested or
screened in the assembly process nor any following processes. To
ensure proper operation after programming, the procedure shown in
Figure 15.1 is recommended to verify programming.
Programming with
PROM programmer
Screening (Caution)
(150°C for 40 hours)
Verification with
PROM programmer
Functional check in target device
Caution : The screening temperature is far higher
than the storage temperature. Never
expose to 150°C exceeding 100 hours.
Fig. 15.1 Programming and Testing of One Time PROM Version
Rev.1.00 Nov 01, 2002 page 103 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
17. ONE TIME PROM VERSION M37151EFFP MARKING
M37151EFFP
XXXXXXX
XXXXXXX is lot number
Rev.1.00 Nov 01, 2002 page 104 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
18. APPENDIX
Pin Configuration (TOP VIEW)
1
42
P1
P1
P1
P1
P5
P5
P5
P5
P5
P5
2
3
4
6
0
1
2
3
4
5
/SCL2
/SDA1
/SDA2
/AD8/TIM2
/HSYNC
/VSYNC
/B
P1
1/SCL1
2
3
41
40
39
P00/PWM0
P01/PWM1
4
P02/PWM2
5
P0
3
/PWM3/AD1
/PWM4/AD2
38
37
6
P04
P0
/INT2/AD4
P0 /INT1
/SCLK/AD5
/SOUT/AD6
P2 /SIN/AD7
5/AD3
7
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
8
/G
P0
6
9
/R
7
10
11
12
13
14
15
16
17
18
19
20
21
P2
0
/OUT
CLKCONT/P1
0
P2
1
P30
P31
P15
/SDA3
2
/SCL3
P2
3
/TIM3
/TIM2
P2
4
10KΩ
P2
5/INT3
P2
6/XCIN
RESET
CVIN
P27/XCOUT
CNVSS
VHOLD
XIN
HLF
FLIT
XOUT
VSS
VCC
Outline 42P2R
Rev.1.00 Nov 01, 2002 page 105 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Memory Map
ꢀ M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
000016
1000016
M37151M6-
XXXFP
RAM
M37151MF-XXXFP,
M37151EFFP
RAM
Zero page
00BF16
00C016
00FF16
010016
SFR1 area
(1024 bytes)
(2048 bytes)
M37151MB-XXXFP
01FF
02001166
RAM
Not used
SFR2 area
Not used
(1152 bytes)
020F16
M37151MA/MC-
030016
032016
XXXFP
RAM
ROM correction function
Vector 1: address 030016
Vector 2: address 032016
053F16
05BF16
06FF16
(1472 bytes)
Not used
Not used
OSD RAM
(128 bytes)
OSD ROM
(10K bytes)
(See note)
080016
087F16
1140016
13BFF16
090016
0B3F16
M37151MF-XXXFP,
M37151EFFP
ROM
(60K bytes)
Not used
Not used
M37151MC-XXXFP
ROM
(48K bytes)
M37151MA-XXXFP
100016
ROM
(40K bytes)
400016
600016
800016
M37151M8-XXXFP
A00016
ROM
(32K bytes)
FF0016
FFDE16
1FFFF16
M37151M6-XXXFP
ROM
(24K bytes)
Special page
Interrupt vector area
FFFF16
Rev.1.00 Nov 01, 2002 page 106 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Memory Map of Special Function Register (SFR)
ꢀꢀSFR1 Area (addresses C016 to DF16)
<Bit allocation>
<State immediately after reset>
:
0
1
?
: “0” immediately after reset
: “1” immediately after reset
Function bit
Name
:
: No function bit
: Indeterminate immediately
after reset
0
1
: Fix this bit to “0”
(do not write “1”)
: Fix this bit to “1”
(do not write “0”)
Bit allocation
State immediately after reset
Address Register
b7
b0 b7
b0
?
C016
C116
C216
C316
C416
C516
C616
C716
C816
C916
CA16
CB16
CC16
CD16
CE16
CF16
D016
D116
D216
D316
D416
D516
D616
D716
D816
D916
DA16
DB16
DC16
DD16
DE16
DF16
Port P0(P0)
0016
Port P0 direction register (D0)
0
?
?
0
0
1
?
0
?
?
0
?
0
?
1
Port P1(P1)
0
0
0
Port P1 direction register (D1)
Port P2(P2)
?
0016
Port P2 direction register (D2)
Port P3(P3)
BSEL21 BSEL20
P31 P30
0
0
?
0
0
0
0
0
0
0
?
0
?
0
T2SC T3SC
OUTS P31D P30D
0
0
1
0016
?
Port P3 direction register (D3)
0
0
0
0
0
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
1
0
0
?
0
?
Port P5(P5)
1
PF5 PF4 PF3 PF2
0
0
OSD port control register (PF)
Timer return set register (TMS)
TMS
0
0016
0016
?
1
0
0
0
0
0
0
0
0
CC10
Clock control register 1 (CC1)
Caption data register 3 (CD3)
CDL27 CDL26 CDL25 CDL24 CDL23 CDL22 CDL21 CDL20
CDH27 CDH26 CDH25 CDH24 CDH23 CDH22 CDH21 CDH20
?
Caption data register 4 (CD4)
OSD control register (OC)
OC7
0
0
OC4 OC3 OC2 OC1 OC0
0016
0016
?
HP6 HP5 HP4 HP3 HP2 HP1 HP0
Horizontal position register (HP)
Block control register 1(BC1)
Block control register 2(BC2)
Vertical position register 1(VP1)
Vertical position register 2(VP2)
Window register 1(WN1)
BC17 BC16 BC15 BC14 BC13 BC12 BC11 BC10
BC27 BC26 BC25 BC24 BC23 BC22 BC21 BC20
VP17 VP16 VP15 VP14 VP13 VP12 VP11 VP10
?
?
VP27 VP26 VP25 VP24 VP23 VP22 VP21 VP20
WN17 WN16 WN15 WN14 WN13 WN12 WN11 WN10
WN27 WN26 WN25 WN24 WN23 WN22 WN21 WN20
?
?
?
Window register 2(WN2)
PC6 PC5
PC3 PC2 PC1 PC0
RC3 RC2 RC1 RC0
4016
0016
?
0
0
0
I/O polarity control register (PC)
Raster color register (RC)
RC7
0
0
0
0
0
OC21 OC20
0
0
0
0
?
0
0
0
0
OSD control register 2(OC2)
INT3 INT2 INT1
0016
0016
0016
0016
Interrupt input polarity control register (RE)
0016
0016
0016
Rev.1.00 Nov 01, 2002 page 107 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
ꢀ SFR1 Area (addresses E016 to FF16
)
<Bit allocation>
:
<State immediately after reset>
: “0” immediately after reset
: “1” immediately after reset
0
1
?
Function bit
Name
:
: No function bit
: Indeterminate immediately
after reset
0
1
: Fix this bit to “0”
(do not write “1”)
: Fix this bit to “1”
(do not write “0”)
Bit allocation
State immediately after reset
Address
Register
b7
0
b0 b7
b0
DSC12 DSC11 DSC10
Data slicer control register 1 (DSC1)
Data slicer control register 2 (DSC2)
Caption data register 1 (CD1)
Caption data register 2 (CD2)
Clock run-in detect register (CRD)
Data clock position register (DPS)
Caption position register (CPS)
Data slicer test register 2
0016
E016
E116
E216
E316
1
0
1
0
0
DSC25 DSC24 DSC23
DSC20
1
?
0
?
0
?
?
0
?
CDL17 CDL16 CDL15 CDL14 CDL13 CDL12 CDL11 CDL10
CDH17 CDH16 CDH15 CDH14 CDH13 CDH12 CDH11 CDH10
CRD7 CRD6 CRD5 CRD4 CRD3
0016
0016
0016
0916
E416
E516
E616
DPS7 DPS6 DPS5 DPS4 DPS3
1
0
0
CPS7 CPS6 CPS5 CPS4 CPS3 CPS2 CPS1 CPS0
0
0
?
0
0
0
0
0
0
0016
0016
0016
E716
E816
E916
EA16
EB16
Data slicer test register 1
HC5 HC4 HC3 HC2 HC1 HC0
Synchronous signal counter register (HC)
Serial I/O register (SIO)
?
SM6 SM5
SM3 SM2 SM1 SM0
Serial I/O mode register (SM)
0016
?
0
0
ADC14
ADC12 ADC11 ADC10
0
0
0
0
EC16 A-D control register 1 (AD1)
0
0
ADC26 ADC25 ADC24 ADC23 ADC22 ADC21 ADC20
0016
0716
A-D control register 2 (AD2)
Timer 5 (T5)
ED16
EE16
EF16
F016
Timer 6 (T6)
FF16
FF16
0716
FF16
0716
Timer 1 (T1)
Timer 2 (T2)
F116
F216
F316
Timer 3 (T3)
Timer 4 (T4)
TM17 TM16 TM15 TM14 TM13 TM12 TM11 TM10
TM27 TM26 TM25 TM24 TM23 TM22 TM21 TM20
0016
F416 Timer mode register 1 (TM1)
Timer mode register 2 (TM2)
2
F516
0016
?
0016
D7 D6 D5 D4 D3 D2 D1 D0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
F616 I C data shift register (S0)
2
F716
F816
I C address register (S0D)
2
MST TRX BB PIN AL AAS AD0 LRB
10BIT
0
0
0
1
0
0
0
?
I C status register (S1)
BSEL1 BSEL0
ALS ESO BC2 BC1 BC0
CCR4 CCR3 CCR2 CCR1 CCR0
CM2
2
0016
SAD
FAST
MODE
I C control register (S1D)
F916
FA16
FB16
FC16
FD16
FE16
FF16
ACK
ACK
2
0016
3C16
0016
0016
0016
0016
BIT
I C clock control register (S2)
CM7 CM6 CM5
1
1
0
0
CPU mode register (CPUM)
VSCR OSDR TM4R TM3R TM2R TM1R
IN3R
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
TM56R
DSR
IN1R
IICR IN2R CKR S1R
0
VSCE OSDE TM4E TM3E TM2E TM1E
IICE IN2E CKE S1E DSE IN1E
IN3E
TM56C TM56E
Rev.1.00 Nov 01, 2002 page 108 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
ꢀSFR2 Area (addresses 20016 to 20F16)
<Bit allocation>
<State immediately after reset>
:
:
0
1
?
: “0” immediately after reset
: “1” immediately after reset
Function bit
Name
: No function bit
: Indeterminate immediately
after reset
0
1
: Fix this bit to “0”
(do not write “1”)
: Fix this bit to “1”
(do not write “0”)
State immediately after reset
Register
Bit allocation
Address
b0
b0
b7
b7
?
?
?
?
?
?
?
?
20016
20116
20216
20316
PWM0 register (PWM0)
PWM1 register (PWM1)
PWM2 register (PWM2)
PWM3 register (PWM3)
20416 PWM4 register (PWM4)
20516
20616
0016
0016
PM13
20716
20816
20916
PWM mode register 1 (PM1)
PWM mode register 2 (PM2)
PM10
?
?
?
?
0
?
?
0
PM24 PM23 PM22 PM21 PM20
0
0
0
0016
0016
0016
0016
0016
20A16
20B16
20C16
ROM correction address 1 (high-order)
ROM correction address 1 (low-order)
ROM correction address 2 (high-order)
20D16
20E16
ROM correction address 2 (low-order)
ROM correction enable register (RCR)
RC1 RC0
0016
?
20F16
210
0
0
0
0
1
1
1
0
Clock frequency set register (CFS)
Clock control register 2(CC2)
211
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0016
0016
CC37
CC35
212 Clock control register 3(CC3)
Rev.1.00 Nov 01, 2002 page 109 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
<
State immediately after reset>
<
Bit allocation
:
>
: “0” immediately after reset
: “1” immediately after reset
0
1
?
Function bit
:
:
Name
No function bit
: Indeterminate immediately
after reset
: Fix to this bit to “0”
(do not write to “1”)
0
1
: Fix to this bit to “1”
(do not write to “0”)
Register
Bit allocation
State immediately after reset
b0
b0
b7
N
b7
Processor status register (PS)
V
T
B
D
I
Z
C
?
?
?
?
?
1
?
?
Program counter (PC
Program counter (PC
H)
Contents of address FFFF16
Contents of address FFFE16
L
)
Rev.1.00 Nov 01, 2002 page 110 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Structure of Register
The figure of each register structure describes its functions, contents
at reset, and attributes as follows:
<Example>
Bit position
Bit attributes(Note 2)
CPU Mode Register
(Note 1)
Values immediately after reset release
b7b6 b5b4b3 b2b1b0
1 1 0 0
CPU mode register (CPUM) (CM) [Address 00FB16
]
B
Name
Functions
R W
R W
After re
0
Processor mode bits b1 b0
(CM0, CM1)
0, 1
0 0: Single-chip mode
0 1:
1 0: Not available
1 1:
0: 0 page
1: 1 page
Stack page selection
bit (See note) (CM2)
2
1
R W
3, 4 Fix these bits to “1.”
1
1
R W
R W
5
Nothing is assigned. This bit is write disable bit.
When this bit is read out, the value is “1.”
Clock switch bits
(CM6, CM7)
b7 b6
6, 7
0
R W
0 0: f(XIN) = 8 MHz
0 1: f(XIN) = 12 MHz
1 0: f(XIN) = 16 MHz
1 1: Do not set
: Bit in which nothing is assigned
Notes 1: Values immediately after reset release
0 ••••••••••••••••••“0” after reset release
1 ••••••••••••••••••“1” after reset release
Indeterminate•••Indeterminate after reset
release
2: Bit attributes••••••The attributes of control register bits are classified into 3 types : read-only, write-only
and read and write. In the figure, these attributes are represented as follows :
R••••••Read
W••••••Write
W
R
–
••••••Read enabled
••••••Read disabled
••••••Write enabled
–
••••••Write disabled
ꢀ ••••••“0” can be set by software, but “1”
cannot be set.
Rev.1.00 Nov 01, 2002 page 111 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Address 00C116, 00C516
Port Pi Direction Register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (Di) (i=0, 2) [Addresses 00C116, 00C516
]
B
0
Name
After reset
0
R
R
Functions
W
W
0 : Port Pi
1 : Port Pi
0
0
input mode
output mode
Port Pi direction register
1
2
3
0
0
0
0
0
0
0
0 : Port Pi
1 : Port Pi
1
1
input mode
output mode
R
R
R
R
R
R
R
W
W
W
W
W
W
W
0 : Port Pi
1 : Port Pi
2
2
input mode
output mode
0 : Port Pi
1 : Port Pi
3
3
input mode
output mode
0 : Port Pi
1 : Port Pi
4
4
input mode
output mode
4
5
0 : Port Pi
1 : Port Pi
5
5
input mode
output mode
0 : Port Pi
1 : Port Pi
6
6
input mode
output mode
6
7
0 : Port Pi
1 : Port Pi
7
7
input mode
output mode
Address 00C216
Port P1 register
b7 b6 b5 b4 b3 b2 b1 b0
0
Port P1 register (P1) [Address 00C216
]
B
Name
Functions
After reset
R
R
W
W
0
1
Port P1 register
Port P10 data
Port P11 data
Indeterminate
Indeterminate
R
W
2
3
4
5
R
R
R
R
R
R
W
W
W
Port P12 data
Port P13 data
Port P14 data
Port P15 data
Port P16 data
Indeterminate
Indeterminate
Indeterminate
0
W
W
W
6
7
Indeterminate
Indeterminate
Fix this bit to "0"
Rev.1.00 Nov 01, 2002 page 112 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Address 00C316
Port P1 direction register
b7 b6 b5 b4 b3 b2 b1 b0
0
Port P1 direction register (D1) [Address 00C316]
B
0
Name
Functions
After reset R
W
W
0 : Port P10 input mode (note)
1 : Port P10 output mode
1
0
0
R
R
R
Port P1 direction register
W
W
1
2
3
4
5
6
7
0 : Port P11 input mode
1 : Port P11 output mode
0 : Port P12 input mode
1 : Port P12 output mode
0 : Port P13 input mode
1 : Port P13 output mode
0
0
R
R
R
W
W
W
0 : Port P14 input mode
1 : Port P14 output mode
0 : Port P15 input mode
1 : Port P15 output mode
1
0
0
0 : Port P16 input mode
1 : Port P16 output mode
R
W
R W
Fix this bit to "0"
Note: When using P10 as a general-purpose port, set the Clock Control Register 3 (address 021216) bit 7 to 1.
When using P10 as a clock control signal, refer to 8.14.1 oscillation control.
P10 becomes clock control signal output and “H” output setting immediately after reset release , and P16
becomes “L” output setting after reset release.
Address 00C616
Port P3 register
b7 b6 b5 b4 b3 b2 b1 b0
Port P3 register (P3) [Address 00C616
]
B
0
1
Name
Functions
data
After reset
Indeterminate
Indeterminate
0
R
R
R
W
W
W
Port P3 register
Port P3
0
1
Port P3
data
Switch bit of I2C-BUS
interface and port P3
R W
2
0: Port P30, Port P31
1: I2CBUS (SDA3,SCL3)
(BSEL20)
(See note)
SCL3/P3 -SCL1/P1
1
1
3
R
R
0
0
W
–
0: Cutting
SDA3/P3 -SDA1/P13
0
1: Connection
Connection control bit (BSEL21)
Nothing is assigned. This bit is write disable bit.
When this bit is read out, the value is "0."
4 to
7
Notes
•
For the ports used as the Multi-master I2C-BUS interface, set their direction registers to 1.
• To use SCL3 and SDA3, set the I2C Control Register (address 00F916) bits 6–7 to 0.
Rev.1.00 Nov 01, 2002 page 113 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Address 00C716
Port P3 direction register
b7 b6 b5 b4 b3 b2 b1 b0
0
Port P3 direction register (D3) [Address 00C716
]
B
0
Name
Functions
After reset
0
R
R
W
W
0 : Port P3
0
0
input
Port P3 direction register
(See note 1)
1 : Port P3
output
1
0 : Port P3
1
1
input
0
0
R
R
W
W
1 : Port P3
output
Output amplitude level selection bit 0 : 2 value output
(See note 2)
2
3
(OUTS)
1 : 3 value output
Fix this bit to "0."
0
0
W
–
R
R
R
4, 5
6
Nothing is assigned fix these bits
When this bit are read out, the value are "0."
Timer 3 (T3SC)
0
0
W
W
Refer to explanation of a timer
Timer 2 (T2SC)
0 : P2
1 : P1
4
6
input
input
7
R
Notes 1: When using the port as the I2C-BUS interface, set the Port P3 Direction Register to 1.
2: Use the Clock Control Register 3 (address 021216) bit 5 to select the binary
output level of OUT.
Address 00CA16
Port P5 register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
Port P5 register (P5) [Address 00CA16]
B
Name
Functions
After reset
R
R
W
W
Fix these bits to "0."
0, 1
Indeterminate
Port P5 register
Port P5
Port P5
Port P5
Port P5
2
3
4
5
data
data
data
data
2
3
4
5
R W
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
R
R
W
W
R W
6
7
Fix these bits to "0."
–
W
Indeterminate R W
Rev.1.00 Nov 01, 2002 page 114 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Address 00CB16
OSD Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0
OSD port control register (PF) [Address 00CB16
]
1 0
0 0
R
R
B
Name
Functions
After reset
0
W
—
0, 1
Fix these bits to “0.”
2
3
4
Port P5
selection bit (PF2)
2
output signal
0 : B signal output
1 : Port P5 output
0
0
0
0
R
R
R
R
W
W
W
W
2
Port P5
3
output signal
0 : G signal output
1 : Port P5 output
selection bit (PF3)
3
0 : R signal output
1 : Port P5 output
Port P54 output signal
4
selection bit (PF4)
Port P5 output signal
5
0 : OUT signal output
1 : Port P5 output
5
6
7
selection bit (PF5)
5
Fix this bit to “0.”
—
R
W
W
Indeterminate
0
Fix this bit to “1.”
Address 00CC16
Timer return setting register
b7 b6 b5 b4 b3 b2 b1 b0
1
1
0
0
0
0
0
Timer return setting register (TMS) [Address 00CC16
]
B
Name
Functions
After reset
R
W
0 to
4
Fix these bits to "0."
0
R W
Fix these bits to "1."
0
0
R W
R W
5, 6
7
STOP mode return selection bit
(TMS)
0: Timer Count "07FF16"
1: Timer Count Variable
Rev.1.00 Nov 01, 2002 page 115 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Address 00CD16
Clock control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
0
0
0
Clock control register 1 (CC1) [Address 00CD16]
B
0
Name
Functions
0: Operation
W
W
R
R
After reset
0
System clock generating
circuit control bit (CC10)
1: Stop
W
0
R
1 to
7
Fix these bits to "0"
Address 00D016
OSD Control Register
b7 b6 b5b4 b3 b2b1 b0
0 0
OSD control register (OC) [Address 00D016
]
Functions
Name
After reset R
W
B
0
0 : All-blocks display off
1 : All-blocks display on
OSD control bit
(OC0) (See note 1)
0
R W
R W
R W
R W
Automatic solid space 0 : OFF
0
0
0
1
2
3
1 : ON
control bit (OC1)
Window control bit
(OC2)
0 : OFF
1 : ON
CC mode clock
0 : Data slicer clock
selection bit (OC3)
1 : Internal oscillating clock f(osc)
4
OSD mode clock
selection bit (OC4)
0
R W
0 : Data slicer clock
1 : Internal oscillating clock f(osc)
R W
R W
5, 6 Fix these bits to “0.”
0
0
0 : Divide ratio by the block
control register
1 : Pre-divide ratios = ✕✕1
for blocks 1 and 2
Pre-divide ratio
7
selection bit (OC7)
(See note 2)
Notes 1:Even this bit is switched during display, the display screen
remains unchanged until a rising (falling) of the next VSYNC
2:This bit's priority is higher than BCi4 of Block Control
Register i setting.
Rev.1.00 Nov 01, 2002 page 116 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Address 00D116
Horizontal Position Register
b7 b6 b5b4 b3 b2b1 b0
Horizontal position register (HP) [Address 00D116
]
B
0
Name
Functions
After reset R W
Horizontal display start position
4Tosc ✕ n
Horizontal display start
0
R W
to position control bits
6
(n: setting value, Tosc: OSD oscillation cycle)
(HP0 to HP6)
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
7
0
R —
Note: The setting value synchronizes with the V SYNC
.
Address 00D216, 00D316
Block Control register i
b7 b6 b5b4 b3 b2b1 b0
Block control register i (BCi) (i=1, 2) [Addresses 00D216 and 00D316
]
After reset
B
Name
Functions
R W
R W
b1 b0
Indeterminate
0, 1 Display mode
selection bits
(BCi0, BCi1)
0 0: Display OFF
0 1: CC mode
1 0: OSD mode (Border OFF)
1 1: OSD mode (Border ON)
(See note 1)
b4 b3 b2 Pre-divide Ratio Dot Size
Indeterminate
Indeterminate
2, 3 Dot size selection
bits (BCi2, BCi3)
R W
R W
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
0
1
✕ 2
4
Pre-divide ratio
selection bit (BCi4)
✕ 3
0: 2 value output control
1: 3 value output control
(notes 3)
5
6
OUToutput control bit
(BCi5)
Indeterminate
Indeterminate
R W
R W
Vertical display start
position control bit
(BCi6)
BC16: Block 1
BC26: Block 1
BC17: Window top boundary
BC27: Window bottom boundary
Indeterminate
7
Window top/bottom
boundary control bit
(BCi7)
R W
Notes 1: Tc is OSD clock cycle divided in pre-divide circuit.
2: H is HSYNC
3: Refer to the corresponding figure 8.11.18.
.
Rev.1.00 Nov 01, 2002 page 117 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Address 00D416, 00D516
Vertical Position Register i
b7 b6 b5 b4 b3 b2 b1 b0
Vertical position register i (VPi) (i = 1 and 2) [Addresses 00D416, 00D516
]
After reset
Name
B
Functions
R
R
W
W
Vertical display start
position control bits
(VPi0 to VPi7)
Vertical display start position =
Inderterminate
0
to
7
TH
5 (BCi6 ✕ 162 + n)
(n: setting value, TH: HSYNC cycle,
(See note)
BCi6: bit 6 of block control register i)
Notes 1: Set values except “0016” to VPi when BCi6 is “0.”
2: When OS21 of OSD control register 2 = “0”, TH = 1HSYNC
,
and OS21 of OSD control register 2 = “1”, TH = 2HSYNC
.
Address 00D616
Window Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Window register 1 (WN1) [Address 00D616]
After reset
Name
B
Functions
R
R
W
W
Window top border position =
TH 5 (BC17 ✕ 162 + n)
(n: setting value, TH: HSYNC cycle,
Inderterminate
Window top boundary
control bits
(WN10 to WN17)
0
to
7
BC17: bit 7 of block control register 1)
Notes 1: Set values except “0016” to WN1 when BC17 is “0.”
2: Set values fit for the following condition: WN1 < WN2.
3: When OC21 of OSD control register 2 is “0”, TH is 1 HSYNC.
And when “1”, TH is 2 HSYNC.
Address 00D716
Window Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Window register 2 (WN2) [Address 00D716]
After reset
Name
B
Functions
R
R
W
W
Window bottom border position =
Inderterminate
Window bottom boundary
control bits
(WN20 to WN27)
0
to
7
TH
5 (BC27 ✕✕162 + n)
(n: setting value, TH: HSYNC cycle,
BC27: bit 7 of block control register 2)
Notes 1: Set values fit for the following condition: WN1 < WN2.
2: When OC21 of OSD control register 2 is “0”, T
And when “1”, T
H
is 1 HSYNC.
H
is 2 HSYNC.
Rev.1.00 Nov 01, 2002 page 118 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Address 00D816
I/O Polarity Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
I/O polarity control register (PC) [Address 00D816
]
After reset
0
B
0
Name
Functions
R
R
W
W
H
SYNC input polarity
switch bit (PC0)
0 : Positive polarity input
1 : Negative polarity input
1
2
3
5
0 : Positive polarity input
1 : Negative polarity input
0
0
0
0
R
R
R
R
W
W
W
W
V
SYNC input polarity
switch bit (PC1)
0 : Positive polarity output
1 : Negative polarity output
R, G, B output polarity
switch bit (PC2)
OUT1 output polarity
switch bit (PC3)
0 : Positive polarity output
1 : Negative polarity output
Display dot line selection
bit (PC5) (See note)
0 : “
” at even field
” at odd field
” at even field
” at odd field
“
1 : “
“
6
Field determination flag
(PC6)
0 : Even field
1 : Odd field
1
0
R
R
—
W
4, 7
Fix these bits to “0.”
Note: Refer to the corresponding figure. 8.11.15
Address 00D916
Raster Color Register
b7 b6 b5b4 b3 b2b1 b0
0 0 0
Raster color register (RC) [Address 00D916]
After reset
Functions
Name
R
W
B
0
0 : No output
1 : Output
0
R W
R W
R W
R W
Raster color R
control bit (RC0)
Raster color G
control bit (RC1)
0 : No output
1 : Output
0
0
0
1
2
3
Raster color B
control bit (RC2)
0 : No output
1 : Output
Raster color OUT
control bit (RC3)
0 : No output
1 : Output
4
R W
R W
Fix these bits to “0.”
0
0
to
6
7
Port function
selection bit (RC7)
0 : XCIN,
XCOUT
1 : P26, P27
Rev.1.00 Nov 01, 2002 page 119 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Address 00DB16
OSD Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
OSD control register (OC2) [Address 00DB16
]
0
0
0
0
Functions
After reset
0
R
R
W
W
B
Name
0: 1HSYNC (normal scan)
1: 2HSYNC (by scan)
Vertical character dot size
(OC20)
0
0: Counts one time by 1HSYNC
1: Counts two time by 1HSYNC
.
(normal scan)
(by scan)
Vertical start position count
selection bit (OC21)
1
0
0
R
R
W
W
.
Fix this bit to "0."
2
3
4
Nothing is assigned. This bit is write disable bit.
When this bit is read out, the value is "0."
0
R
–
–
–
Nothing is assigned. This bit is write disable bit.
When this bit is read out, the value is "0."
Inderterminate
5 to Fix these bits to "0."
7
0
R
W
Address 00DC16
Interrupt Input Polarity Register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt input polarity register (RE) [Address 00DC16
]
B
0
Name
Functions
After reset
0
R
R
W
W
INT1 polarity switch bit
(INT1)
0 : Positive polarity
1 : Negative polarity
0
0
0
R
R
R
W
W
—
1
2
INT2 polarity switch bit
(INT2)
0 : Positive polarity
1 : Negative polarity
INT3 polarity switch bit
(INT3)
0 : Positive polarity
1 : Negative polarity
3
to
7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
Rev.1.00 Nov 01, 2002 page 120 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Address 00E016
Data Slicer Control Register 1
b7b6b5b4b3b2b1b0
0 1 1 0 0
Data slicer control register 1(DSC1) [Address 00E016
]
B
0
Name
Functions
0: Stopped
1: Operating
After reset
R
R
W
W
0
Data slicer and timing signal
generating circuit control bit (DSC10)
1
2
0: F2
1: F1
0
0
0
R
R
R
W
W
W
Selection bit of data slice reference
voltage generating field (DSC11)
0: Video signal
1: HSYNC signal
Reference clock source
selection bit (DSC12)
3, 4
Fix these bits to “0.”
5, 6
7
0
0
R
R
W
W
Fix these bits to “1.”
Fix this bit to “0.”
Definition of fields 1 (F1) and 2 (F2)
sep
H
F2:
sep
H
F1:
sep
V
sep
V
Rev.1.00 Nov 01, 2002 page 121 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Data Slicer Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
1
Data slicer control register 2 (DSC2) [Address 00E116]
B
1
Name
Functions
After reset
R
R
W
—
0: Data is not latched yet
and a clock-run-in is not
determined.
1: Data is latched and a
clock-run-in is determined.
Indeterminate
Caption data latch
completion flag 1
(DSC20)
1
2
0
Fix this bit to “1.”
Test bit
R
R
W
—
—
W
0
Indeterminate
Read-only
0: F2
1: F1
Indeterminate R
Field determination
flag(DSC23)
0: Method (1)
1: Method (2)
0
R
Vertical synchronous signal
(Vsep) generating method
selection bit (DSC24)
4
5
0: Match
1: Mismatch
Indeterminate R
—
V-pulse shape
determination flag (DSC25)
0
R
R
6
7
W
—
Fix this bit to “0.”
Test bit
Indeterminate
Read-only
Definition of fields 1 (F1) and 2 (F2)
Hsep
Vsep
Hsep
Vsep
F2:
F1:
Address 00E416
Clock Run-in Detect Register
b7 b6 b5 b4 b3 b2 b1 b0
Clock run-in detect register (CRD) [Address 00E416
]
R
R
After reset
0
W
—
B
Name
Test bits
Functions
0
to
2
Read-only
3
Clock run-in detection
Number of reference clocks to
be counted in one clock run-in
pulse period.
0
R
—
to bit(CRD3 to CRD7)
7
Rev.1.00 Nov 01, 2002 page 122 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Data Clock Position Register
b7 b6 b5 b4 b3 b2 b1 b0
0
1
0
Data clock position register (DPS) [Address 00E516
]
R
R
W
W
B
0
Name
Functions
After reset
1
Fix this bit to “0.”
1
Fix this bit to “1.”
Fix this bit to “0.”
0
R
W
2
3
0
1
R
R
W
W
Data clock position set
bits (DPS3 to DPS7)
4
to
7
0
Caption Position Register
b7 b6 b5 b4 b3 b2 b1 b0
Caption Position Register (CPS) [Address 00E616
]
R W
Name
Functions
After reset
0
B
0
to
4
R W
Caption position
bits(CPS0 to CPS4)
5
0: Data is not latched yet and a
clock-run-in is not determined.
1: Data is latched and a
Indeterminate
R
R
—
W
Caption data latch
completion flag 2
(CPS5)
clock-run-in is determined.
6, 7
Refer to the corresponding
Table (Table 8.10.1).
0
Slice line mode
specification bits
(in 1 field) (CPS6, CPS7)
Address 00E916
Sync Pulse Counter Register
b7 b6 b5 b4 b3 b2 b1 b0
Sync pulse counter register (HC) [Address 00E916
]
R
W
—
Name
Functions
After reset
B
0
to
4
Count value (HC0 to HC4)
0
R
5
Count source (HC5)
0: HSYNC signal
1: Composite sync signal
0
0
R
W
—
R
6, 7 Nothing is assigned. These bits are write disable bits.
“0.”
When these bits are read out, the values are
Rev.1.00 Nov 01, 2002 page 123 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Address 00EB16
Serial I/O Mode Register
b7b6 b5b4b3 b2b1b0
0
0
Serial I/O mode register (SM) [Address 00EB16
]
After reset
B
Functions
Name
R W
0
R W
b1 b0
0, 1
Internal synchronous
clock selection bits
(SM0, SM1)
0 0: f(XIN)/8 or f(XCIN)/8
0 1: f(XIN)/16 or f(XCIN)/16
1 0: f(XIN)/32 or f(XCIN)/32
1 1: f(XIN)/64 or f(XCIN)/64
0
0
R W
R W
2
3
0: External clock
1: Internal clock
Synchronous clock
selection bit (SM2)
0: P20, P21
Port function
1: SCLK, SOUT
selection bit (SM3)
0
0
R W
R W
Fix this bit to “0.”
4
5
6
7
0: LSB first
1: MSB first
Transfer direction
selection bit (SM5)
0: Input signal from SIN pin
1: Input signal from SOUT pin
Transfer clock input
pin selection bit (SM6)
0
0
R W
R W
Fix this bit to “0.”
Address 00EC16
A-D Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register 1 (AD1) [Address 00EC16
]
B
Name
Functions
After reset R W
0
to
2
Analog input pin selection
bits
(ADC10 to ADC12)
b2 b1 b0
0
R W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : AD1
1 : AD2
0 : AD3
1 : AD4
0 : AD5
1 : AD6
0 : AD7
1 : AD8
3
4
This bit is a write disable bit.
When this bit is read out, the value is “0.”
0
—
R
0: Input voltage < reference voltage
1: Input voltage > reference voltage
Storage bit of comparison
result (ADC14)
R —
Indeterminate
0
5
to
7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
—
R
Rev.1.00 Nov 01, 2002 page 124 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Address 00ED16
A-D Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register 2 (AD2) [Address 00ED16
]
B
Name
Functions
After reset
0
R
R
W
W
b6 b5 b4 b3 b2 b1 b0
0
to
6
D-A converter set bits
(ADC20 to ADC25)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
: 1/256Vcc
: 3/256Vcc
: 5/256Vcc
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
: 251/256Vcc
: 253/256Vcc
: 255/256Vcc
Nothing is assigned. This bit is a write disable bit.
When these bits are reed out, the values are “ 0.”
0
R
—
7
Address 00F416
Timer Mode Register 1
b7b6 b5b4b3 b2b1b0
Timer mode register 1 (TM1) [Address 00F4 16
]
After reset
B
0
Name
Functions
0: f(XIN)/16 or f(XCIN)/16 (See note)
1: Count source selected by bit 5 of TM1
R W
Timer 1 count source
selection bit 1 (TM10)
0
0
R W
0: Count source selected by bit 4 of TM1
1: External clock from TIM2 pin
R W
1
Timer 2 count source
selection bit 1 (TM11)
Timer 1 count
stop bit (TM12)
2
3
4
0: Count start
1: Count stop
0
0
0
R W
R W
R W
Timer 2 count stop
bit (TM13)
0: Count start
1: Count stop
Timer 2 count source
selection bit 2
(TM14)
0: f(XIN)/16 or f(XCIN)/16 (See note)
1: Timer 1 overflow
5
Timer 1 count source
selection bit 2 (TM15)
0: f(XIN)/4096 or f(XCIN)/4096 (See note)
1: External clock from TIM2 pin
0
R W
6
7
Timer 5 count source
selection bit 2 (TM16)
0: Timer 2 overflow
1: Timer 4 overflow
0
0
R W
R W
Timer 6 internal count 0: f(XIN)/16 or f(XCIN)/16 (See note)
source selection bit
(TM17)
1: Timer 5 overflow
Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Rev.1.00 Nov 01, 2002 page 125 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Address 00F516
Timer Mode Register 2
b7b6 b5b4b3 b2b1b0
Timer mode register 2 (TM2) [Address 00F516
]
After reset
B
0
Name
Functions
R W
R W
Timer 3 count source
selection bit (TM20)
0
(b6 at address 00C716
)
b0
0
1
0
1
0 : f(XIN)/16 or f(XCIN)/16 (See note)
0 : f(XCIN
)
1 :
1 :
External clock from TIM3 pin
b4 b1
1, 4
Timer 4 count source
selection bits
(TM21, TM24)
0
R W
0
0
1
1
0 : Timer 3 overflow signal
1 : f(XIN)/16 or f(XCIN)/16 (See note)
0 : f(XIN)/2 or f(XCIN)/2 (See note)
1 : f(XCIN
)
Timer 3 count
stop bit (TM22)
2
3
0: Count start
1: Count stop
0
0
R W
R W
Timer 4 count stop bit
(TM23)
0: Count start
1: Count stop
Timer 5 count stop bit
(TM25)
5
6
0: Count start
1: Count stop
0
0
R W
R W
Timer 6 count stop bit
(TM26)
0: Count start
1: Count stop
Timer 5 count source
selection bit 1
(TM27)
7
0: f(XIN)/16 or f(XCIN)/16 (See note)
1: Count source selected by bit 6
of TM1
0
R W
Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Address 00F616
2
I C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0
2
I C data shift register 1(S0) [Address 00F616
]
B
Name
Functions
After reset
R
R
W
W
0
to
7
D0 to D7 This is an 8-bit shift register to store
receive data and write transmit data.
Indeterminate
2
Note : To write data into the I C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
Rev.1.00 Nov 01, 2002 page 126 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Address 00F716
2
I C Address Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C address register (S0D) [Address 00F716]
After reset
0
B
0
Name
Functions
R W
R —
<Only in 10-bit addressing (in slave) mode>
The last significant bit of address data is
compared.
Read/write bit
(RBW)
0: Wait the first byte of slave address after
START condition
(read state)
1: Wait the first byte of slave address after
(write state)
RESTART condition
<In both modes>
(SAD0 to SAD6) The address data is compared.
R
W
Slave address
0
1
to
7
Address 00F816
2
I C Status Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register (S1) [Address 00F816
]
After reset
B
Name
Functions
W
R
0
Last receive bit (LRB)
(See note)
0 : Last bit = “0 ”
1 : Last bit = “1 ”
Indeterminate
R —
R —
R —
(See note)
1
2
General call detecting flag
(AD0) (See note)
0 : No general call detected
1 : General call detected
0
0
(See note)
Slave address comparison
flag (AAS) (See note)
0 : Address mismatch
1 : Address match
(See note)
(See note)
3
4
5
Arbitration lost detecting flag 0 : Not detected
(AL) (See note)
0
1
0
0
R —
R W
R W
R W
1 : Detected
I2C-BUS interface interrupt
request bit (PIN)
0 : Interrupt request issued
1 : No interrupt request issued
Bus busy flag (BB)
0 : Bus free
1 : Bus busy
6, 7 Communication mode
specification bits
b7 b6
0
0
1
1
0 : Slave recieve mode
1 : Slave transmit mode
0 : Master recieve mode
1 : Master transmit mode
(TRX, MST)
Note : These bits and flags can be read out, but cannnot be written.
Rev.1.00 Nov 01, 2002 page 127 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Address 00F916
2
I C Control Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C control register (S1D) [Address 00F916
]
After reset
0
B
Name
Functions
R W
Bit counter
(Number of transmit/recieve
b2 b1 b0
0
to
2
R W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : 8
bits)
1 : 7
0 : 6
1 : 5
0 : 4
1 : 3
0 : 2
1 : 1
(BC0 to BC2)
3
4
5
I2C-BUS interface use
enable bit (ESO)
0
0
0
0
0 : Disabled
1 : Enabled
R W
R W
R W
R W
Data format selection
bit(ALS)
0 : Addressing mode
1 : Free data format
Addressing format selection
bit (10BIT SAD)
0 : 7-bit addressing format
1 : 10-bit addressing format
b7 b6 Connection port (See note)
6, 7 Connection control bits
between I2C-BUS interface
and ports
0
0
1
1
0: None
1: SCL1, SDA1
0: SCL2, SDA2
1: SCL1, SDA1
SCL2, SDA2
(BSEL0, BSEL1)
Note: • Set the corresponding direction register to "1" to use the port as multi-master I2C-BUS interface.
• To use SCL1, SDA1, SCL2 and SDA2, set the port P3 Register (address 00C616) bit 2 to 0.
Rev.1.00 Nov 01, 2002 page 128 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Address 00FA16
2
I C Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0
2
I C clock control register (S2) [Address 00FA16
]
After reset
B
Functions
R W
R W
Name
Setup value
of CCR4–
CCR0
Standard
clock
mode
High speed
clock mode
0
to
4
SCL frequency control
bits
(CCR0 to CCR4)
0
Setup disabled Setup disabled
00 to 02
Setup disabled
333
03
04
05
06
Setup disabled
250
400 (See note)
166
100
83.3
500/CCR value 1000/CCR value
17.2
16.6
16.1
34.5
33.3
32.3
1D
1E
1F
(φ = 4 MHz, unit : kHz)
0
5
SCL mode
specification bit
(FAST MODE)
0: Standard clock mode
1: High-speed clock mode
R W
6
7
ACK bit
(ACK BIT)
0: ACK is returned.
1: ACK is not returned.
0
0
R W
R W
ACK clock bit
(ACK)
0: No ACK clock
1: ACK clock
Note. At 400kHz in the high-speed clock mode, the duty is as below.
“0” period : “1” period = 3 : 2
In the other cases, the duty is as below.
“0” period : “1” period = 1 : 1
Rev.1.00 Nov 01, 2002 page 129 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Address 00FB16
CPU Mode Register
b7b6 b5b4b3 b2b1b0
1 1
0 0
CPU mode register (CM) [Address 00FB16
]
Functions
After reset
0
B
Name
R W
R W
b1 b0
Processor mode bits
(CM0, CM1)
0, 1
0 0: Single-chip mode
0 1:
1 0:
1 1:
Not available
0: 0 page
1: 1 page
Stack page selection
bit (CM2) (See note)
2
1
R W
Fix these bits to “1.”
1
1
R W
R W
3, 4
5
0: LOW drive
1: HIGH drive
X
COUT drivability
selection bit (CM5)
6
7
0
0
R W
R W
0: Oscillating
1: Stopped
Main Clock (XIN–XOUT
stop bit (CM6)
)
Internal system clock 0: XIN selected
(high-speed mode)
1: XCIN–XCOUT selected
(low-speed mode)
selection bit
(CM7)
Note. This bit is set to “1” after the reset release.
Address 00FC16
Interrupt Request Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address 00FC16
]
B
0
Name
Functions
Afrer reset R
W
0
0 : No interrupt request issued
1 : Interrupt request issued
Timer 1 interrupt request
bit (TM1R)
✕
R
1
2
3
4
5
6
7
Timer 2 interrupt request 0 : No interrupt request issued
bit (TM2R) 1 : Interrupt request issued
✕
0
0
0
R
Timer 3 interrupt request 0 : No interrupt request issued
bit (TM3R) 1 : Interrupt request issued
✕
✕
✕
R
R
R
Timer 4 interrupt request 0 : No interrupt request issued
bit (TM4R)
1 : Interrupt request issued
OSD interrupt
request bit (OSDR)
0 : No interrupt request issued
1 : Interrupt request issued
0
0
0
0
VSYNC interrupt request 0 : No interrupt request issued
✕
✕
—
R
R
R
bit (VSCR)
1 : Interrupt request issued
INT3 external interrupt
request bit (IN3R)
0 : No interrupt request issued
1 : Interrupt request issued
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
✕: “0” can be set by software, but “1” cannot be set.
Rev.1.00 Nov 01, 2002 page 130 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Address 00FD16
Interrupt Request Register 2
b7b6 b5b4b3 b2b1b0
0
Interrupt request register 2 (IREQ2) [Address 00FD16
]
After reset
B
0
Name
Functions
R W
INT1 external interrupt
request bit (IN1R)
Data slicer interrupt
request bit (DSR)
Serial I/O interrupt
request bit (SIR)
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
✕
✕
✕
0
0
0
0
R
R
R
R
1
2
3
4
✕
f(XIN
)/4096 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
request bit (CKR)
INT2 external interrupt
request bit (IN2R)
✕
✕
0
0
R
R
2C-BUS
0 : No interrupt request issued
Multi-master I
5
6
interrupt request bit (IICR) 1 : Interrupt request issued
Timer 5 • 6 interrupt
request bit (TM56R)
✕
0 : No interrupt request issued
1 : Interrupt request issued
0
0
R
7
Fix this bit to “0.”
R W
✕: “0” can be set by software, but “1” cannot be set.
Address 00FE16
Interrupt Control Register 1
b7b6 b5b4b3 b2b1b0
Interrupt control register 1 (ICON1) [Address 00FE16
]
Name
After reset
0
B
0
Functions
R W
Timer 1 interrupt
enable bit (TM1E)
0 : Interrupt disabled
1 : Interrupt enabled
R W
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
1
2
3
4
Timer 2 interrupt
enable bit (TM2E)
Timer 3 interrupt
enable bit (TM3E)
Timer 4 interrupt
enable bit (TM4E)
R W
0
R W
R W
R W
0
0
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
OSD interrupt enable bit
(OSDE)
V
SYNC interrupt enable 0 : Interrupt disabled
5
6
7
R W
R W
R —
0
0
1 : Interrupt enabled
bit (VSCE)
0 : Interrupt disabled
1 : Interrupt enabled
INT3 external interrupt
enable bit (IN3E)
Nothing is assigned. This bit is a write disable
bit. When this bit is read out, the value is “0.”
0
Rev.1.00 Nov 01, 2002 page 131 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Address 00FF16
Interrupt Control Register 2
b7b6 b5b4b3 b2b1b0
Interrupt control register 2 (ICON2) [Address 00FF16]
After reset
0
B
0
Name
Functions
R W
R W
INT1 external interrupt
enable bit (IN1E)
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Data slicer interrupt
enable bit (DSE)
1
2
3
4
0
R W
Serial I/O interrupt
enable bit (SIE)
0
0
0
R W
R W
R W
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
f(XIN
)/4096 interrupt
enable bit (CKE)
INT2 external interrupt
enable bit (IN2E)
I2
Multi-master C-BUS
5
0 : Interrupt disabled
1 : Interrupt enabled
0
R W
interface interrupt enable
bit (IICE)
0
0
R W
R W
Timer 5 • 6 interrupt
enable bit (TM56E
Timer 5 • 6 interrupt
switch bit (TM56C)
0 : Interrupt disabled
1 : Interrupt enabled
6
7
)
0 : Timer 5
1 : Timer 6
Address 020816
PWM Mode Register 1
b7b6 b5b4b3 b2b1b0
PWM mode register 1 (PM1) [Address 020816
]
After reset
R W
B
0
Name
Functions
PWM counts source
selection bit (PM10)
0 : Count source supply
1 : Count source stop
W
0
R
1, 2
3
—
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
Indeterminate
0
R
PWM output polarity
selection bit (PM13)
0 : Positive polarity
1 : Negative polarity
R W
4
to
7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
—
R
Indeterminate
Rev.1.00 Nov 01, 2002 page 132 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Address 020916
PWM Mode Register 2
b7b6 b5b4b3 b2b1b0
0 0 0
PWM mode register 2 (PM2) [Address 020916
]
B
0
Name
Functions
output
1 : PWM0 output
0 : P0 output
1 : PWM1 output
After reset R W
0 : P0
0
P0
0
/PWM0 output
0
R W
selection bit (PM20)
P0 /PWM1 output
selection bit (PM21)
P0 /PWM2 output
selection bit (PM22)
P0 /PWM3 output
selection bit (PM23)
1
2
3
4
1
1
0
0
0
R W
R W
R W
2
0 : P02 output
1 : PWM2 output
3
0 : P0 output
3
1 : PWM3 output
P0 /PWM4 output
selection bit (PM24)
4
0
0
R W
R W
0 : P0 output
4
1 : PWM4 output
Fix these bits to “0.”
5 to
7
Address 020E16
ROM Correction Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
ROM correction enable register (RCR) [Address 020E 16
]
After reset
0
B
Name
Functions
R W
R W
0
Vector 1 enable bit (RC0)
0: Disabled
1: Enabled
1
Vector 2 enable bit (RC1)
0: Disabled
1: Enabled
0
0
R W
R —
Nothing is assigned. These bits are write disable bits. When
these bits are read out, the values are “0.”
2
to
7
Rev.1.00 Nov 01, 2002 page 133 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Address 021016
Clock frequency set register
b7 b6 b5 b4 b3 b2 b1 b0
Clock frequency set register(CFS) [Address 021016
]
B
Name
Functions
After reset
R
R
W
W
Clock frequency (Note)
0 to
7
Clock frequency bit
(CFS 0 to 7)
0E
Setting value(Limitation) Frequency(MHz)
0C
0D
26
28
Note: Do not set other than the values shown above to CFS.
Then, must to use at f(XIN) = 8 MHz.
Address 021116
Clock control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
1
0
0
0
1
0
0
Clock control register 2 (CC2) [Address 021116
]
B
Name
0,1 Fix these bits to "0"
Fix this bit to "1"
Functions
After reset
W
R
0
0
R W
R W
2
3 to Fix these bits to "0"
5
0
R W
6
7
Fix this bit to "1"
Fix this bit to "0"
0
0
R W
R W
Rev.1.00 Nov 01, 2002 page 134 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Address 021216
Clock control register 3
b7 b6 b5 b4 b3 b2 b1 b0
Clock control register 3 (CC3) [Address 021216
]
0
0
0
0
0 0
B
Name
Functions
After reset
W
W
R
R
0
0 to
4
Fix these bits to "0"
0: 0V–VCC
1: 0V–About 0.6VCC
5
R
R,G,B,OUT Output amplitude
level selection bit (CC35)
0
W
6
7
R
R
0
0
W
W
Fix this bit to "0"
P10
function-selection bit
(Note)
(CC37)
0: Clock control signal
1: P10 I/O
Note: When used as the clock control signal, set the Port 1 Direction Register
(address 00C316) bit 0 to 1.
Rev.1.00 Nov 01, 2002 page 135 of 136
REJ03B0129-0100Z
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
19. PACKAGE OUTLINE
42P2R-A/E
Plastic 42pin 450mil SSOP
EIAJ Package Code
SSOP42-P-450-0.80
JEDEC Code
–
Weight(g)
0.63
Lead Material
Alloy 42
e
b
2
42
22
Recommended Mount Pad
Dimension in Millimeters
F
Symbol
Min
–
0.05
–
0.25
0.13
17.3
8.2
–
11.63
0.3
–
–
–
–
0°
–
–
1.27
Nom
–
–
Max
2.4
–
A
A
A
1
21
1
2
A
2.0
0.3
0.15
17.5
8.4
0.8
11.93
0.5
1.765
0.75
–
–
D
G
b
0.4
0.2
17.7
8.6
–
12.23
0.7
–
c
D
E
e
H
L
A
2
A1
e
b
E
y
L1
z
Z
y
–
1
0.9
0.15
10°
–
–
–
–
–
c
z
b2
0.5
11.43
–
Z
1
Detail G
Detail F
e1
I
2
Rev.1.00 Nov 01, 2002 page 136 of 136
REJ03B0129-0100Z
REVISION HISTORY
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
Rev.
Date
Description
Summary
Page
1.00 Nov 01, 2002
–
First edition issued
A - 1
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology (Shanghai) Co., Ltd.
Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
© 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
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