M34513M8-XXXFP [RENESAS]
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER; 单片4位微机的CMOS
| 型号： | M34513M8-XXXFP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| 文件： | 总97页 (文件大小：1262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
DESCRIPTION
ꢀTimers
The 4513/4514 Group is a 4-bit single-chip microcomputer de-
signed with CMOS technology. Its CPU is that of the 4500 series
using a simple, high-speed instruction set. The computer is
equipped with serial I/O, four 8-bit timers (each timer has a reload
register), and 10-bit A-D converter.
Timer 1...................................... 8-bit timer with a reload register
Timer 2...................................... 8-bit timer with a reload register
Timer 3...................................... 8-bit timer with a reload register
Timer 4...................................... 8-bit timer with a reload register
ꢀInterrupt ........................................................................ 8 sources
ꢀSerial I/O....................................................................... 8 bit-wide
ꢀA-D converter .................. 10-bit successive comparison method
ꢀVoltage comparator ........................................................2 circuits
ꢀWatchdog timer ................................................................. 16 bits
ꢀVoltage drop detection circuit
The various microcomputers in the 4513/4514 Group include varia-
tions of the built-in memory type and package as shown in the
table below.
FEATURES
ꢀMinimum instruction execution time ................................ 0.75 µs
(at 4.0 MHz oscillation frequency, in high-speed mode, VDD = 4.0
V to 5.5 V)
ꢀClock generating circuit (ceramic resonator)
ꢀLED drive directly enabled (port D)
ꢀSupply voltage
APPLICATION
Electrical household appliance, consumer electronic products, of-
• Middle-speed mode
...... 2.5 V to 5.5 V (at 4.2 MHz oscillation frequency, for Mask
ROM version and One Time PROM version)
...... 2.0 V to 5.5 V (at 3.0 MHz oscillation frequency, for Mask
ROM version)
fice automation equipment, etc.
(Operation voltage of A-D conversion: 2.7 V to 5.5 V)
• High-speed mode
...... 4.0 V to 5.5 V (at 4.2 MHz oscillation frequency, for Mask
ROM version and One Time PROM version)
...... 2.5 V to 5.5 V (at 2.0 MHz oscillation frequency, for Mask
ROM version and One Time PROM version)
...... 2.0 V to 5.5 V (at 1.5 MHz oscillation frequency, for Mask
ROM version)
(Operation voltage of A-D conversion: 2.7 V to 5.5 V)
ROM (PROM) size
RAM size
(ꢀ 4 bits)
Product
Package
ROM type
(ꢀ 10 bits)
M34513M2-XXXSP/FP
M34513M4-XXXSP/FP
M34513E4SP/FP (Note)
M34513M6-XXXFP
M34513M8-XXXFP
M34513E8FP (Note)
M34514M6-XXXFP
M34514M8-XXXFP
M34514E8FP (Note)
2048 words
4096 words
4096 words
6144 words
8192 words
8192 words
6144 words
8192 words
8192 words
SP: 32P4B FP: 32P6U-A
SP: 32P4B FP: 32P6U-A
SP: 32P4B FP: 32P6U-A
32P6U-A
Mask ROM
Mask ROM
128 words
256 words
256 words
384 words
384 words
384 words
384 words
384 words
384 words
One Time PROM
Mask ROM
32P6U-A
Mask ROM
32P6U-A
One Time PROM
Mask ROM
42P2R-A
42P2R-A
Mask ROM
42P2R-A
One Time PROM
Note: shipped in blank
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW) 4513 Group
1
2
32
D
D
D
D
D
D
0
1
2
3
4
5
P1
3
2
1
0
3
2
1
0
31 P1
3
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P1
P1
P0
P0
P0
P0
4
5
6
7
D
6
/CNTR0
8
D
7/CNTR1
9
AIN3/CMP1+
AIN2/CMP1-
AIN1/CMP0+
AIN0/CMP0-
P2
P2
P2
0/SCK
10
11
12
13
14
15
16
1
/SOUT
2
/SIN
RESET
CNVSS
P3
1
0
/INT1
/INT0
P3
X
OUT
IN
SS
VDCE
X
V
VDD
Outline 32P4B
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
D
D
D
3
4
5
0
1
P0
P0
P0
2
1
0
M34513Mx-XXXFP
M34513ExFP
D
D
6
7
/CNTR
/CNTR
AIN3/CMP1+
AIN2/CMP1-
AIN1/CMP0+
AIN0/CMP0-
P2
P2
P2
0
/SCK
/SOUT
/SIN
1
2
P31/INT1
Outline 32P6U-A
2
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW) 4514 Group
1
42
41
40
39
38
P1
P1
P1
P0
P0
P0
P0
2
1
0
3
2
1
0
P1
D
D
D
D
D
D
3
0
1
2
3
4
5
2
3
4
5
6
37
36
35
34
7
8
P4
P4
P4
3
2
1
0
/AIN7
/AIN6
/AIN5
/AIN4
D
6
7
/CNTR0
/CNTR1
9
D
33
10
11
P5
P5
P5
P5
0
1
2
3
32 P4
31
30
A
IN3/CMP1+
IN2/CMP1-
IN1/CMP0+
IN0/CMP0-
12
13
14
15
A
29
28
27
26
25
A
P20/SCK
A
P2
1
/SOUT
P3
3
2
16
17
P2
2
/SIN
P3
RESET
CNVSS
P3
1
/INT1
/INT0
18
X
OUT 19
P3
0
24
23
20
21
X
IN
VDCE
22
V
DD
V
SS
Outline 42P2R-A
3
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
BLOCK DIAGRAM (4513 Group)
4
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
BLOCK DIAGRAM (4514 Group)
5
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PERFORMANCE OVERVIEW
Parameter
Function
4513 Group
4514 Group
Number of
123
128
basic instructions
Minimum instruction execution time
0.75 µs (at 4.0 MHz oscillation frequency, in high-speed mode)
2048 words ꢀ 10 bits
4096 words ꢀ 10 bits
6144 words ꢀ 10 bits
8192 words ꢀ 10 bits
6144 words ꢀ 10 bits
8192 words ꢀ 10 bits
128 words ꢀ 4 bits
ROM
M34513M2
Memory sizes
M34513M4/E4
M34513M6
M34513M8/E8
M34514M6
M34514M8/E8
M34513M2
RAM
M34513M4/E4
M34513M6
256 words ꢀ 4 bits
384 words ꢀ 4 bits
M34513M8/E8
M34514M6
384 words ꢀ 4 bits
384 words ꢀ 4 bits
M34514M8/E8
384 words ꢀ 4 bits
D0–D7
I/O (Input is
examined by
skip decision)
Input/Output
ports
Eight independent I/O ports;
ports D6 and D7 are also used as CNTR0 and CNTR1, respectively.
P00–P03 I/O
4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both
functions can be switched by software.
P10–P13 I/O
4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both
functions can be switched by software.
P20–P22 Input
P30–P33 I/O
3-bit input port; ports P20, P21 and P22 are also used as SCK, SOUT and SIN, respectively.
4-bit I/O port (2-bit I/O port for the 4513 Group); ports P30 and P31 are also used as INT0 and
INT1, respectively. The 4513 Group does not have ports P32, P33.
P40–P43 I/O
P50–P53 I/O
CNTR0 I/O
CNTR1 I/O
4-bit I/O port; The 4513 Group does not have this port.
4-bit I/O port with a direction register; The 4513 Group does not have this port.
1-bit I/O; CNTR0 pin is also used as port D6.
1-bit I/O; CNTR1 pin is also used as port D7.
1-bit input; INT0 pin is also used as port P30 and equipped with a key-on wakeup function.
1-bit input; INT1 pin is also used as port P31 and equipped with a key-on wakeup function.
8-bit programmable timer with a reload register.
8-bit programmable timer with a reload register is also used as an event counter.
8-bit programmable timer with a reload register.
8-bit programmable timer with a reload register is also used as an event counter.
10-bit wide, This is equipped with an 8-bit comparator function.
2 circuits (CMP0, CMP1)
INT0
Input
Input
INT1
Timer 1
Timer 2
Timer 3
Timer 4
Timers
A-D converter
Voltage comparator
Serial I/O
8-bit ꢀ 1
Sources
Nesting
Interrupt
8 (two for external, four for timer, one for A-D, and one for serial I/O)
1 level
Subroutine nesting
Device structure
8 levels
CMOS silicon gate
4513 Group
4514 Group
Package
32-pin plastic molded SDIP (32P4B)/LQFP(32P6U-A)
42-pin plastic molded SSOP (42P2R-A)
Operating temperature range
Supply voltage
–20 °C to 85 °C
2.0 V to 5.5 V for Mask ROM version, 2.5 V to 5.5 V for One Time PROM version (Refer to the
electrical characteristics because the supply voltage depends on the oscillation frequency.)
Active mode
Power
1.8 mA (at VDD = 5.0 V, 4.0 MHz oscillation frequency, in middle- speed mode, output transis-
tors in the cut-off state)
dissipation
(typical value)
3.0 mA (at VDD = 5.0 V, 4.0 MHz oscillation frequency, in high-speed mode, output transistors
in the cut-off state)
RAM back-up mode
0.1 µA (at room temperature, VDD = 5 V, output transistors in the cut-off state)
6
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Name
Function
Pin
Input/Output
Power supply
Ground
Connected to a plus power supply.
VDD
VSS
—
—
Connected to a 0 V power supply.
Voltage drop detec-
tion circuit enable
VDCE pin is used to control the operation/stop of the voltage drop detection circuit.
When “H” level is input to this pin, the circuit is operating. When “L” level is inpu to
this pin, the circuit is stopped.
VDCE
Input
CNVSS
RESET
CNVSS
Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly.
—
Reset input
An N-channel open-drain I/O pin for a system reset. When the watchdog timer
causes the system to be reset or system reset is performed by the voltage drop de-
tection circuit, the RESET pin outputs “L” level.
I/O
XIN
System clock input
System clock output
I/O pins of the system clock generating circuit. XIN and XOUT can be connected to
ceramic resonator. A feedback resistor is built-in between them.
Input
Output
I/O
XOUT
D0–D7
Each pin of port D has an independent 1-bit wide I/O function. Each pin has an out-
put latch. For input use, set the latch of the specified bit to “1.” The output structure
is N-channel open-drain.
I/O port D
(Input is examined
by skip decision.)
Ports D6 and D7 are also used as CNTR0 and CNTR1, respectively.
P00–P03
I/O port P0
Each of ports P0 and P1 serves as a 4-bit I/O port, and it can be used as inputs
when the output latch is set to “1.” The output structure is N-channel open-drain.
Every pin of the ports has a key-on wakeup function and a pull-up function. Both
functions can be switched by software.
I/O
I/O
P10–P13
P20–P22
I/O port P1
Input port P2
3-bit input port. Ports P20, P21 and P22 are also used as SCK, SOUT and SIN, re-
spectively.
Input
I/O
P30–P33
P40–P43
P50–P53
I/O port P3
I/O port P4
I/O port P5
4-bit I/O port (2-bit I/O port for the 4513 Group). For input use, set the latch of the
specified bit to “1.” The output structure is N-channel open-drain. Ports P30 and
P31 are also used as INT0 and INT1, respectively.
The 4513 Group does not have ports P32, P33.
I/O
I/O
4-bit I/O port. For input use, set the latch of the specified bit to “1.” The output
structure is N-channel open-drain. Ports P40–P43 are also used as analog input
pins AIN4–AIN7, respectively.
The 4513 Group does not have port P4.
4-bit I/O port. Each pin has a direction register and an independent 1-bit wide I/O
function. For input use, set the direction register to “0.” For output use, set the di-
rection regiser to “1.” The output structure is CMOS.
The 4513 Group does not have port P5.
AIN0–AIN7
CNTR0
Analog input
Input
I/O
Analog input pins for A-D converter. AIN0–AIN3 are also used as voltage compara-
tor input pins and AIN4–AIN7 are also used as port P4.
The 4513 Group does not have AIN4–AIN7.
Timer input/output
Timer input/output
CNTR0 pin has the function to input the clock for the timer 2 event counter, and to
output the timer 1 underflow signal divided by 2.
CNTR0 pin is also used as port D6.
CNTR1
I/O
CNTR1 pin has the function to input the clock for the timer 4 event counter, and to
output the timer 3 underflow signal divided by 2.
CNTR1 pin is also used as port D7.
INT0, INT1 Interrupt input
Input
INT0, INT1 pins accept external interrupts. They also accept the input signal to re-
turn the system from the RAM back-up state.
INT0, INT1 pins are also used as ports P30 and P31, respectively.
SIN
Serial data input
Serial data output
Input
Output
I/O
SIN pin is used to input serial data signals by software.
SIN pin is also used as port P22.
SOUT
SCK
SOUT pin is used to output serial data signals by software.
SOUT pin is also used as port P21.
Serial I/O clock
input/output
SCK pin is used to input and output synchronous clock signals for serial data trans-
fer by software.
SCK pin is also used as port P20.
CMP0-
CMP0+
Voltage comparator
input
Input
Input
CMP0-, CMP0+ pins are used as the voltage comparator input pin when the volt-
age comparator function is selected by software.
CMP0-, CMP0+ pins are also used as AIN0 and AIN1.
CMP1-
CMP1+
Voltage comparator
input
CMP1-, CMP1+ pins are used as the voltage comparator input pin when the volt-
age comparator function is selected by software.
CMP1-, CMP1+ pins are also used as AIN2 and AIN3.
7
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MULTIFUNCTION
Pin
CNTR0
CNTR1
SCK
Pin
Multifunction
Multifunction
Pin
Pin
CMP0-
CMP0+
CMP1-
CMP1+
AIN4
Multifunction
CMP0-
Multifunction
D6
D7
CNTR0
CNTR1
SCK
D6
D7
AIN0
AIN0
AIN1
AIN2
AIN3
P40
P41
P42
P43
CMP0+
CMP1-
CMP1+
AIN4
AIN1
AIN2
AIN3
P40
P41
P42
P43
P20
P21
P22
P30
P31
P20
P21
P22
P30
P31
SOUT
SIN
SOUT
SIN
INT0
INT0
INT1
AIN5
AIN5
INT1
AIN6
AIN6
AIN7
AIN7
Notes 1: Pins except above have just single function.
2: The input of D6, D7, P20–P22, CMP0-, CMP0+, CMP1-, CMP1+ and the input/output of P30, P31, P40–P43 can be used even when CNTR0, CNTR1,
SCK, SOUT, SIN, INT0, INT1, and AIN0–AIN7 are selected.
3: The 4513 Group does not have P40/AIN4–P43/AIN7.
CONNECTIONS OF UNUSED PINS
Notes 1: After system is released from reset, port P5 is in an input mode (di-
rection register FR0 = 00002)
Connection
Open (when using an external clock).
Connect to VSS.
Pin
XOUT
2: When the P00–P03 and P10–P13 are connected to VSS, turn off
their pull-up transistors (register PU0i=“0”) and also invalidate the
key-on wakeup functions (register K0i=“0”) by software. When
these pins are connected to VSS while the key-on wakeup func-
tions are left valid, the system fails to return from RAM back-up
state. When these pins are open, turn on their pull-up transistors
(register PU0i=“1”) by software, or set the output latch to “0.”
Be sure to select the key-on wakeup functions and the pull-up
functions with every two pins. If only one of the two pins for the
key-on wakeup function is used, turn on their pull-up transistors by
software and also disconnect the other pin. (i = 0, 1, 2, or 3.)
VDCE
D0–D5
Connect to VSS, or set the output latch to
“0” and open.
D6/CNTR0
D7/CNTR1
Connect to VSS.
P20/SCK
P21/SOUT
P22/SIN
P30/INT0
P31/INT1
P32, P33
Connect to VSS, or set the output latch to
“0” and open.
(Note when the output latch is set to “0” and pins are open)
✕ After system is released from reset, port is in a high-impedance state un-
til it is set the output latch to “0” by software. Accordingly, the voltage
level of pins is undefined and the excess of the supply current may occur
while the port is in a high-impedance state.
✕ To set the output latch periodically by software is recommended because
value of output latch may change by noise or a program run away
(caused by noise).
P40/AIN4–P43/AIN7
Connect to VSS, or set the output latch to
“0” and open.
P50–P53 (Note 1)
When the input mode is selected by soft-
ware, pull-up to VDD through a resistor or
pull-down to VDD.
When selecting the output mode, open.
AIN0/CMP0-
AIN1/CMP0+
AIN2/CMP1-
AIN3/CMP1+
Connect to VSS.
(Note when connecting to VSS and VDD)
✕✕Connect the unused pins to VSS and VDD using the thickest wire at the
shortest distance against noise.
P00–P03
P10–P13
Open or connect to VSS (Note 2)
Open or connect to VSS (Note 2)
8
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PORT FUNCTION
Input
Output
I/O
unit
Control
instructions registers
Control
Port
Pin
Output structure
Remark
I/O
(8)
1
SD, RD
SZD
CLD
Port D
D0–D5
D6/CNTR0
D7/CNTR1
N-channel open-drain
W6
I/O
(4)
4
OP0A
IAP0
PU0, K0
PU0, K0
Port P0
Port P1
Port P2
P00–P03
N-channel open-drain
N-channel open-drain
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
I/O
(4)
4
OP1A
IAP1
P10–P13
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
Input
(3)
3
4
IAP2
J1
P20/SCK
P21/SOUT
P22/SIN
I/O
(4)
OP3A
IAP3
I1, I2
Port P3
(Note 1)
P30/INT0
P31/INT1
P32, P33
N-channel open-drain
Built-in key-on wakeup
function
(P30/INT0, P31/INT1)
I/O
(4)
4
4
OP4A
IAP4
Q2
Port P4
(Note 2)
P40/AIN4
–P43/AIN7
N-channel open-drain
CMOS
I/O
(4)
OP5A
IAP5
FR0
Port P5
(Note 2)
P50–P53
Notes 1: The 4513 Group does not have P32 and P33.
2: The 4513 Group does not have these ports.
DEFINITION OF CLOCK AND CYCLE
✕✕System clock
The system clock is the basic clock for controlling this product.
The system clock is selected by the bit 3 of the clock control reg-
ister MR.
Table Selection of system clock
Register MR
System clock
MR3
0
1
f(XIN)
f(XIN)/2
Note: f(XIN)/2 is selected after system is released from reset.
✕✕Instruction clock
The instruction clock is a signal derived by dividing the system
clock by 3. The one instruction clock cycle generates the one
machine cycle.
✕✕Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
9
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PORT BLOCK DIAGRAMS
K00
Pull-up transistor
PU0
Key-on wakeup input
0
IAP0 instruction
D
Register A
Ai
P00,P01
T
Q
OP0A instruction
K01
Pull-up transistor
PU0
Key-on wakeup input
1
IAP0 instruction
D
P02,P03
Register A
Ai
Q
T
OP0A instruction
K02
Pull-up transistor
PU0
Key-on wakeup input
2
IAP1 instruction
D
P10,P11
Register A
Ai
T
Q
OP1A instruction
K03
Pull-up transistor
Key-on wakeup input
PU0
3
IAP1 instruction
D
Register A
Ai
P12,P13
T
OP1A instruction
Q
This symbol represents a parasitic diode on the port.
•i represents 0, 1, 2, or 3.
•
10
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PORT BLOCK DIAGRAMS (continued)
IAP2 instruction
Register A
Synchronous clock input for serial transfer
J1
1
P20/SCK
0
Synchronous clock output for serial transfer
J1
1
0
IAP2 instruction
Register A
J1
0
1
P21/SOUT
1
Serial data output
Serial data input
IAP2 instruction
Register A
P22/SIN
Key-on wakeup input
External interrupt circuit
IAP3 instruction
Register A
Ai
P30/INT0,P31/INT1
D
T
OP3A instruction
Q
IAP3 instruction
Register A
Ai
P32,P33
D
OP3A instruction
T
Q
This symbol represents a parasitic diode on the port.
•
• Applied potential to ports P2
0
—P2
2
must be VDD
.
• i represents 0, 1, 2, or 3.
• The 4513 Group does not have ports P3
2, P33.
11
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PORT BLOCK DIAGRAMS (continued)
Q1
Decoder
Analog input
A
IN0/CMP0-
-
Q30
+
Q32
CMP0
Q1
Decoder
AIN1/CMP0+
Analog input
Q1
Decoder
Analog input
AIN2/CMP1-
-
Q31
+
Q33
CMP1
Q1
Decoder
AIN3/CMP1+
Analog input
IAP4 instruction
P40/AIN4–P43/AIN7
Register A
Q1
Ai
D
OP4A instruction
T
Q
Decoder
Analog input
This symbol represents a parasitic diode on the port.
•
• i represents 0, 1, 2, or 3.
• The 4513 Group does not have port P4.
12
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PORT BLOCK DIAGRAMS (continued)
Direction register FR0i
Ai
D
T
Q
P50–P53
OP5A instruction
Register A
IAP5 instruction
Skip decision
(SZD instruction)
Register Y
Decoder
CLD instruction
D0–D5
S
R
SD instruction
RD instruction
Q
(SZD instruction)
Skip decision
Clock input for timer 2 event count
Decoder
Register Y
CLD instruction
S
W6
0
D6/CNTR0
SD instruction
RD instruction
0
R
Q
1
Timer 1 underflow signal divided by 2 or
signal of AND operation between
timer 1 underflow signal divided by 2 and
timer 2 underflow signal divided by 2
Skip decision
(SZD instruction)
Clock input for timer 4 event count
Decoder
CLD instruction
Register Y
S
W6
2
D7/CNTR1
SD instruction
RD instruction
R
0
Q
Timer 3 underflow signal divided by 2 or
signal of AND operation between
1
timer 3 underflow signal divided by 2 and
timer 4 underflow signal divided by 2
This symbol represents a parasitic diode on the port.
•
• Applied potential to ports D
• i represents 0, 1, 2, or 3.
0–D7 must be 12 V.
• The 4513 Group does not have port P5.
13
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
I1
2
One-sided edge
detection circuit
I11
Falling
0
0
External 0
EXF0
P30/INT0
interrupt
1
1
Both edges
detection circuit
Rising
Wakeup
Skip
SNZI0
I2
2
One-sided edge
detection circuit
I21
Falling
0
0
External 1
interrupt
EXF1
P31/INT1
1
1
Both edges
detection circuit
Rising
Wakeup
Skip
SNZI1
This symbol represents a parasitic diode on the port.
External interrupt circuit structure
14
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
FUNCTION BLOCK OPERATIONS
CPU
<Carry>
(CY)
(1) Arithmetic logic unit (ALU)
(M(DP))
The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-
bit data addition, comparison, AND operation, OR operation, and
bit manipulation.
Addition
ALU
(A)
<Result>
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer, ex-
change, and I/O operation.
Fig. 1 AMC instruction execution example
Carry flag CY is a 1-bit flag that is set to “1” when there is a carry
with the AMC instruction (Figure 1).
<Set>
SC instruction
<Clear>
RC instruction
It is unchanged with both A n instruction and AM instruction. The
value of A0 is stored in carry flag CY with the RAR instruction (Fig-
ure 2).
Carry flag CY can be set to “1” with the SC instruction and cleared
to “0” with the RC instruction.
CY
A3
A2
A1 A0
(3) Registers B and E
<Rotation>
RAR instruction
Register B is a 4-bit register used for temporary storage of 4-bit
data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data transfer
with register B used as the high-order 4 bits and register A as the
low-order 4 bits (Figure 3).
A0
CY A
3
A2 A1
Fig. 2 RAR instruction execution example
TAB instruction
Register B
(4) Register D
Register D is a 3-bit register.
Register A
B
3
B
2
B
1
B
0
A
3
A
2
A
1
A0
It is used to store a 7-bit ROM address together with register A and
is used as a pointer within the specified page when the TABP p,
BLA p, or BMLA p instruction is executed (Figure 4).
TEAB instruction
Register E E
7 E6 E5 E4 E3 E2
E
1
E
0
TABE instruction
A
3 A2 A1 A0
B
3 B2 B1 B0
TBA instruction
Register B
Register A
Fig. 3 Registers A, B and register E
TABP p instruction
ROM
8
4
0
Specifying address
Low-order 4bits
PCH
PCL
Register A (4)
Register B (4)
p6
p5
p
4
p
3
p
2
p1
p0
A
3 A2 A1 A0
DR2DR1DR0
Middle-order 4 bits
The contents of The contents of
register D register A
Immediate field
value p
Fig. 4 TABP p instruction execution example
15
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(5) Stack registers (SKS) and stack pointer (SP)
Stack registers (SKs) are used to temporarily store the contents of
program counter (PC) just before branching until returning to the
original routine when;
Program counter (PC)
Executing BM
Executing RT
instruction
instruction
• branching to an interrupt service routine (referred to as an inter-
rupt service routine),
SK
0
(SP) = 0
(SP) = 1
(SP) = 2
SK
1
2
• performing a subroutine call, or
SK
• executing the table reference instruction (TABP p).
Stack registers (SKs) are eight identical registers, so that subrou-
tines can be nested up to 8 levels. However, one of stack registers
is used respectively when using an interrupt service routine and
when executing a table reference instruction. Accordingly, be care-
ful not to over the stack when performing these operations
together. The contents of registers SKs are destroyed when 8 lev-
els are exceeded.
SK
SK
SK
SK
SK
3
4
5
6
7
(SP) = 3
(SP) = 4
(SP) = 5
(SP) = 6
(SP) = 7
Stack pointer (SP) points “7” at reset or
returning from RAM back-up mode. It points “0”
by executing the first BM instruction, and the
contents of program counter is stored in SK0.
When the BM instruction is executed after eight
The register SK nesting level is pointed automatically by 3-bit
stack pointer (SP). The contents of the stack pointer (SP) can be
transferred to register A with the TASP instruction.
Figure 5 shows the stack registers (SKs) structure.
Figure 6 shows the example of operation at subroutine call.
stack registers are used ((SP) = 7), (SP) = 0
and the contents of SK0 is destroyed.
Fig. 5 Stack registers (SKs) structure
(6) Interrupt stack register (SDP)
Interrupt stack register (SDP) is a 1-stage register. When an inter-
rupt occurs, this register (SDP) is used to temporarily store the
contents of data pointer, carry flag, skip flag, register A, and regis-
ter B just before an interrupt until returning to the original routine.
Unlike the stack registers (SKs), this register (SDP) is not used
when executing the subroutine call instruction and the table refer-
ence instruction.
(SP) ← 0
(SK0) ← 000116
(PC) ← SUB1
Main program
Address
Subroutine
SUB1 :
(7) Skip flag
000016 NOP
NOP
·
·
·
Skip flag controls skip decision for the conditional skip instructions
and continuous described skip instructions. When an interrupt oc-
curs, the contents of skip flag is stored automatically in the interrupt
stack register (SDP) and the skip condition is retained.
000116 BM SUB1
000216 NOP
RT
(PC) ← (SK
(SP) ← 7
0)
Returning to the BM instruction execution
address with the RT instruction, and the BM
instruction becomes the NOP instruction.
Note :
Fig. 6 Example of operation at subroutine call
16
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Program counter
(8) Program counter (PC)
Program counter (PC) is used to specify a ROM address (page and
address). It determines a sequence in which instructions stored in
ROM are read. It is a binary counter that increments the number of
instruction bytes each time an instruction is executed. However,
the value changes to a specified address when branch instructions,
subroutine call instructions, return instructions, or the table refer-
ence instruction (TABP p) is executed.
p6
p
5
p4
p3
p2
p1
p0
a6 a5 a4 a3 a2 a1 a0
PC
H
PC
L
Specifying page
Specifying address
Program counter consists of PCH (most significant bit to bit 7)
which specifies to a ROM page and PCL (bits 6 to 0) which speci-
fies an address within a page. After it reaches the last address
(address 127) of a page, it specifies address 0 of the next page
(Figure 7).
Fig. 7 Program counter (PC) structure
Data pointer (DP)
Make sure that the PCH does not specify after the last page of the
built-in ROM.
Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and consists
of registers Z, X, and Y. Register Z specifies a RAM file group, reg-
ister X specifies a file, and register Y specifies a RAM digit (Figure
8).
Specifying
RAM digit
Register Y (4)
Register X (4)
Specifying RAM file
Register Y is also used to specify the port D bit position.
When using port D, set the port D bit position to register Y certainly
and execute the SD, RD, or SZD instruction (Figure 9).
Register Z (2)
Specifying RAM file group
Fig. 8 Data pointer (DP) structure
Specifying bit position
Set
D6
D5
D4
D0
D7
0
1
0
1
1
Port D output latch
Register Y (4)
Fig. 9 SD instruction execution example
17
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PROGRAM MEMOY (ROM)
9
8
7
6
5
4
3
2
1
0
The program memory is a mask ROM. 1 word of ROM is composed
of 10 bits. ROM is separated every 128 words by the unit of page
(addresses 0 to 127). Table 1 shows the ROM size and pages. Fig-
ure 10 shows the ROM map of M34514M8/E8.
000016
Page 0
Page 1
Page 2
Page 3
007
F
00801166
Interrupt address page
Subroutine special page
00FF
01001166
Table 1 ROM size and pages
017
F
01801166
ROM size
Product
M34513M2
Pages
(✕ 10 bits)
2048 words
4096 words
6144 words
8192 words
6144 words
8192 words
16 (0 to 15)
32 (0 to 31)
48 (0 to 47)
64 (0 to 63)
48 (0 to 47)
64 (0 to 63)
M34513M4/E4
M34513M6
0FFF16
Page 31
Page 63
M34513M8/E8
M34514M6
M34514M8/E8
1
FFF16
A part of page 1 (addresses 008016 to 00FF16) is reserved for in-
terrupt addresses (Figure 11). When an interrupt occurs, the
address (interrupt address) corresponding to each interrupt is set
in the program counter, and the instruction at the interrupt address
is executed. When using an interrupt service routine, write the in-
struction generating the branch to that routine at an interrupt
address.
Fig. 10 ROM map of M34514M8/E8
9 8
7
6
5
4
3
2
1 0
008016 External 0 interrupt address
Page 2 (addresses 010016 to 017F16) is the special page for sub-
routine calls. Subroutines written in this page can be called from
any page with the 1-word instruction (BM). Subroutines extending
from page 2 to another page can also be called with the BM in-
struction when it starts on page 2.
008216 External 1 interrupt address
Timer 1 interrupt address
008416
008616
Timer 2 interrupt address
Timer 3 interrupt address
ROM pattern (bits 7 to 0) of all addresses can be used as data ar-
eas with the TABP p instruction.
008816
008A16
Timer 4 interrupt address
A-D interrupt address
008C16
008E16
Serial I/O interrupt address
00FF16
Fig. 11 Page 1 (addresses 008016 to 00FF16) structure
18
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
DATA MEMORY (RAM)
Table 2 RAM size
1 word of RAM is composed of 4 bits, but 1-bit manipulation (with
the SB j, RB j, and SZB j instructions) is enabled for the entire
memory area. A RAM address is specified by a data pointer. The
data pointer consists of registers Z, X, and Y. Set a value to the
data pointer certainly when executing an instruction to access
RAM.
Product
M34513M2
RAM size
128 words ✕ 4 bits (512 bits)
256 words ✕ 4 bits (1024 bits)
384 words ✕ 4 bits (1536 bits)
384 words ✕ 4 bits (1536 bits)
384 words ✕ 4 bits (1536 bits)
384 words ✕ 4 bits (1536 bits)
M34513M4/E4
M34513M6
M34513M8/E8
M34514M6
Table 2 shows the RAM size. Figure 12 shows the RAM map.
M34514M8/E8
RAM 384 words ✕ 4 bits (1536 bits)
Register Z
0
1
4 5
4 5
6 7
0 1
2
3
6 7
15 0 1 2 3
Register X
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
M34513M6
M34513M8/E8
M34514M6
Z=0, X=0 to 15
Z=1, X=0 to 7
384 words
M34514M8/E8
256 words
M34513M4/E4 Z=0, X=0 to 15
Z=0, X=0 to 7
128 words
M34513M2
Fig. 12 RAM map
19
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Table 3 Interrupt sources
INTERRUPT FUNCTION
Priority
level
Interrupt
address
The interrupt type is a vectored interrupt branching to an individual
address (interrupt address) according to each interrupt source. An
interrupt occurs when the following 3 conditions are satisfied.
• An interrupt activated condition is satisfied (request flag = “1”)
• Interrupt enable bit is enabled (“1”)
Interrupt name
Activated condition
1
2
3
4
5
6
7
8
External 0 interrupt Level change of
INT0 pin
Address 0
in page 1
External 1 interrupt
Timer 1 interrupt
Timer 2 interrupt
Timer 3 interrupt
Timer 4 interrupt
A-D interrupt
Address 2
in page 1
Level change of
INT1 pin
• Interrupt enable flag is enabled (INTE = “1”)
Timer 1 underflow
Timer 2 underflow
Timer 3 underflow
Timer 4 underflow
Address 4
in page 1
Table 3 shows interrupt sources. (Refer to each interrupt request
flag for details of activated conditions.)
Address 6
in page 1
Address 8
in page 1
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every inter-
rupt enable/disable. Interrupts are enabled when INTE flag is set to
“1” with the EI instruction and disabled when INTE flag is cleared to
“0” with the DI instruction. When any interrupt occurs, the INTE flag
is automatically cleared to “0,” so that other interrupts are disabled
until the EI instruction is executed.
Address A
in page 1
Completion of
A-D conversion
Address C
in page 1
Serial I/O interrupt
Address E
in page 1
Completion of
serial I/O transfer
(2) Interrupt enable bit
Use an interrupt enable bit of interrupt control registers V1 and V2
to select the corresponding interrupt or skip instruction.
Table 4 shows the interrupt request flag, interrupt enable bit and
skip instruction.
Table 4 Interrupt request flag, interrupt enable bit and skip in-
struction
Request flag Skip instruction Enable bit
Interrupt name
External 0 interrupt
External 1 interrupt
Timer 1 interrupt
Timer 2 interrupt
Timer 3 interrupt
Timer 4 interrupt
A-D interrupt
EXF0
EXF1
T1F
SNZ0
SNZ1
V10
V11
V12
V13
V20
V21
V22
V23
Table 5 shows the interrupt enable bit function.
SNZT1
SNZT2
SNZT3
SNZT4
SNZAD
SNZSI
(3) Interrupt request flag
T2F
When the activated condition for each interrupt is satisfied, the cor-
responding interrupt request flag is set to “1.” Each interrupt
request flag is cleared to “0” when either;
T3F
T4F
• an interrupt occurs, or
ADF
SIOF
• the next instruction is skipped with a skip instruction.
Each interrupt request flag is set when the activated condition is
satisfied even if the interrupt is disabled by the INTE flag or its in-
terrupt enable bit. Once set, the interrupt request flag retains set
until a clear condition is satisfied.
Serial I/O interrupt
Table 5 Interrupt enable bit function
Occurrence of interrupt
Interrupt enable bit
Skip instruction
Invalid
Enabled
Disabled
1
0
Accordingly, an interrupt occurs when the interrupt disable state is
released while the interrupt request flag is set.
Valid
If more than one interrupt request flag is set when the interrupt dis-
able state is released, the interrupt priority level is as follows
shown in Table 3.
20
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as
follows (Figure 14).
• Program counter (PC)
............................................................... Each interrupt address
• Program counter (PC)
• Stack register (SK)
An interrupt address is set in program counter. The address to be
executed when returning to the main routine is automatically
stored in the stack register (SK).
The address of main routine to be
.............................................
executed when returning
• Interrupt enable flag (INTE)
• Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag
.................................................................. 0 (Interrupt disabled)
Only the request flag for the current interrupt source is cleared to
“0.”
• Interrupt request flag (only the flag for the current interrupt
source) ................................................................................... 0
• Data pointer, carry flag, skip flag, registers A and B
The contents of these registers and flags are stored automati-
cally in the interrupt stack register (SDP).
• Data pointer, carry flag, registers A and B, skip flag
........ Stored in the interrupt stack register (SDP) automatically
(5) Interrupt processing
Fig. 14 Internal state when interrupt occurs
When an interrupt occurs, a program at an interrupt address is ex-
ecuted after branching a data store sequence to stack register.
Write the branch instruction to an interrupt service routine at an in-
terrupt address.
INT0 pin
Address 0
in page 1
(L→H or
H→L input)
EXF0
Use the RTI instruction to return from an interrupt service routine.
Interrupt enabled by executing the EI instruction is performed after
executing 1 instruction (just after the next instruction is executed).
Accordingly, when the EI instruction is executed just before the RTI
instruction, interrupts are enabled after returning the main routine.
(Refer to Figure 13)
V10
V11
V12
INT1 pin
Address 2
in page 1
(L→H or
H→L input)
EXF1
T1F
Timer 1
underflow
Address 4
in page 1
Main
routine
Address 6
in page 1
Timer 2
underflow
T2F
T3F
V1
3
Interrupt
service routine
Address 8
in page 1
Timer 3
underflow
V2
V2
0
1
Interrupt
occurs
Address A
in page 1
Timer 4
underflow
•
T4F
•
•
•
Address C
in page 1
Completion of
A-D conversion
ADF
V2
2
EI
RTI
Interrupt is
enabled
Address E
in page 1
Completion of
serial I/O transfer
INTE
SIOF
V2
3
Request flag
(state retained)
Enable
bit
Enable
flag
Activated
condition
Fig. 15 Interrupt system diagram
: Interrupt enabled state
: Interrupt disabled state
Fig. 13 Program example of interrupt processing
21
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(6) Interrupt control registers
• Interrupt control register V2
• Interrupt control register V1
Interrupt enable bits of timer 3, timer 4, A-D and serial I/O are as-
signed to register V2. Set the contents of this register through
register A with the TV2A instruction. The TAV2 instruction can be
used to transfer the contents of register V2 to register A.
Interrupt enable bits of external 0, external 1, timer 1 and timer 2
are assigned to register V1. Set the contents of this register
through register A with the TV1A instruction. The TAV1 instruction
can be used to transfer the contents of register V1 to register A.
Table 6 Interrupt control registers
Interrupt control register V1
Timer 2 interrupt enable bit
at reset : 00002
at RAM back-up : 00002
R/W
0
1
0
1
0
1
0
1
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
Interrupt disabled (SNZ1 instruction is valid)
Interrupt enabled (SNZ1 instruction is invalid)
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
V13
V12
V11
V10
Timer 1 interrupt enable bit
External 1 interrupt enable bit
External 0 interrupt enable bit
Interrupt control register V2
Serial I/O interrupt enable bit
A-D interrupt enable bit
at RAM back-up : 00002
at reset : 00002
R/W
0
1
0
1
0
1
0
1
Interrupt disabled (SNZSI instruction is valid)
Interrupt enabled (SNZSI instruction is invalid)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid)
Interrupt disabled (SNZT4 instruction is valid)
Interrupt enabled (SNZT4 instruction is invalid)
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
V23
V22
V21
V20
Timer 4 interrupt enable bit
Timer 3 interrupt enable bit
Note: “R” represents read enabled, and “W” represents write enabled.
22
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(7) Interrupt sequence
curs after 3 machine cycles only when the three interrupt condi-
tions are satisfied on execution of other than one-cycle instructions
(Refer to Figure 16).
Interrupts only occur when the respective INTE flag, interrupt en-
able bits (V10–V13 and V20–V23), and interrupt request flag are
“1.” The interrupt actually occurs 2 to 3 machine cycles after the
cycle in which all three conditions are satisfied. The interrupt oc-
When an interrupt request flag is set after its interrupt is enabled (Note 1)
f (XIN) (middle-speed mode)
f (XIN) (high-speed mode)
1 machine cycle
T2
T3
T2
T3
T2
T3
T2
T3
T2
T3
T1
T1
T1
T1
T1
System clock
EI instruction
execution cycle
Interrupt enable
flag (INTE)
Interrupt disabled state
Interrupt enabled state
Retaining level of system
clock for 4 periods or more
is necessary.
INT0, INT1
External
interrupt
EXF0, EXF1
Interrupt activated
condition is satisfied.
Timer 1,
Timer 2,
Timer 3,
Timer 4,
A-D, and
Serial I/O
interrupts
T1F, T2F, T3F,
T4F, ADF,SIOF
The program starts from
the interrupt address.
Flag cleared
2 to 3 machine cycles
(Notes 2, 3)
Notes 1: The 4513/4514 Group operates in the middle-speed mode after system is released from reset.
2: The address is stacked to the last cycle.
3: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.
Fig. 16 Interrupt sequence
23
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
EXTERNAL INTERRUPTS
The 4513/4514 Group has two external interrupts (external 0 and
external 1). An external interrupt request occurs when a valid
waveform is input to an interrupt input pin (edge detection).
The external interrupts can be controlled with the interrupt control
registers I1 and I2.
Table 7 External interrupt activated conditions
Valid waveform
selection bit
Name
Input pin
P30/INT0
Activated condition
I11
I12
External 0 interrupt
When the next waveform is input to P30/INT0 pin
• Falling waveform (“H”→“L”)
• Rising waveform (“L”→“H”)
• Both rising and falling waveforms
When the next waveform is input to P31/INT1 pin
• Falling waveform (“H”→“L”)
I21
I22
External 1 interrupt
P31/INT1
• Rising waveform (“L”→“H”)
• Both rising and falling waveforms
I1
2
One-sided edge
detection circuit
I11
Falling
0
0
External 0
interrupt
EXF0
P30/INT0
1
1
Both edges
detection circuit
Rising
Wakeup
Skip
SNZI0
I2
2
One-sided edge
detection circuit
I21
Falling
0
0
External 1
interrupt
EXF1
P31/INT1
1
1
Both edges
detection circuit
Rising
Wakeup
Skip
SNZI1
This symbol represents a parasitic diode on the port.
Fig. 17 External interrupt circuit structure
24
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(1) External 0 interrupt request flag (EXF0)
External 0 interrupt request flag (EXF0) is set to “1” when a valid
waveform is input to P30/INT0 pin.
(2) External 1 interrupt request flag (EXF1)
External 1 interrupt request flag (EXF1) is set to “1” when a valid
waveform is input to P31/INT1 pin.
The valid waveforms causing the interrupt must be retained at their
level for 4 clock cycles or more of the system clock (Refer to Figure
16).
The valid waveforms causing the interrupt must be retained at their
level for 4 clock cycles or more of the system clock (Refer to Figure
16).
The state of EXF0 flag can be examined with the skip instruction
(SNZ0). Use the interrupt control register V1 to select the interrupt
or the skip instruction. The EXF0 flag is cleared to “0” when an in-
terrupt occurs or when the next instruction is skipped with the skip
instruction.
The state of EXF1 flag can be examined with the skip instruction
(SNZ1). Use the interrupt control register V1 to select the interrupt
or the skip instruction. The EXF1 flag is cleared to “0” when an in-
terrupt occurs or when the next instruction is skipped with the skip
instruction.
The P30/INT0 pin need not be selected the external interrupt input
INT0 function or the normal I/O port P30 function. However, the
EXF0 flag is set to “1” when a valid waveform is input even if it is
used as an I/O port P30.
The P31/INT1 pin need not be selected the external interrupt input
INT1 function or the normal I/O port P31 function. However, the
EXF1 flag is set to “1” when a valid waveform is input even if it is
used as an I/O port P31.
• External 0 interrupt activated condition
• External 1 interrupt activated condition
External 0 interrupt activated condition is satisfied when a valid
waveform is input to P30/INT0 pin.
External 1 interrupt activated condition is satisfied when a valid
waveform is input to P31/INT1 pin.
The valid waveform can be selected from rising waveform, falling
waveform or both rising and falling waveforms. An example of
how to use the external 0 interrupt is as follows.
The valid waveform can be selected from rising waveform, falling
waveform or both rising and falling waveforms. An example of
how to use the external 1 interrupt is as follows.
➀ Select the valid waveform with the bits 1 and 2 of register I1.
➀ Clear the EXF0 flag to “0” with the SNZ0 instruction.
➀ Set the NOP instruction for the case when a skip is performed
with the SNZ0 instruction.
➀ Select the valid waveform with the bits 1 and 2 of register I2.
➀ Clear the EXF1 flag to “0” with the SNZ1 instruction.
➀ Set the NOP instruction for the case when a skip is performed
with the SNZ1 instruction.
➀ Set both the external 0 interrupt enable bit (V10) and the INTE
flag to “1.”
➀ Set both the external 1 interrupt enable bit (V11) and the INTE
flag to “1.”
The external 0 interrupt is now enabled. Now when a valid wave-
form is input to the P30/INT0 pin, the EXF0 flag is set to “1” and the
external 0 interrupt occurs.
The external 1 interrupt is now enabled. Now when a valid wave-
form is input to the P31/INT1 pin, the EXF1 flag is set to “1” and the
external 1 interrupt occurs.
25
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
• Interrupt control register I2
(3) External interrupt control registers
• Interrupt control register I1
Register I2 controls the valid waveform for the external 1 inter-
rupt. Set the contents of this register through register A with the
TI2A instruction. The TAI2 instruction can be used to transfer the
contents of register I2 to register A.
Register I1 controls the valid waveform for the external 0 inter-
rupt. Set the contents of this register through register A with the
TI1A instruction. The TAI1 instruction can be used to transfer the
contents of register I1 to register A.
Table 8 External interrupt control registers
Interrupt control register I1
Not used
at reset : 00002
at RAM back-up : state retained
R/W
0
1
I13
I12
This bit has no function, but read/write is enabled.
Falling waveform (“L” level of INT0 pin is recognized with the SNZI0
0
1
Interrupt valid waveform for INT0 pin/
return level selection bit (Note 2)
instruction)/“L” level
Rising waveform (“H” level of INT0 pin is recognized with the SNZI0
instruction)/“H” level
One-sided edge detected
Both edges detected
Disabled
0
1
0
1
I11
I10
INT0 pin edge detection circuit control bit
INT0 pin
timer 1 control enable bit
Enabled
Interrupt control register I2
Not used
at reset : 00002
at RAM back-up : state retained
R/W
0
1
I23
I22
This bit has no function, but read/write is enabled.
Falling waveform (“L” level of INT1 pin is recognized with the SNZI1
0
1
instruction)/“L” level
Interrupt valid waveform for INT1 pin/
return level selection bit (Note 3)
Rising waveform (“H” level of INT1 pin is recognized with the SNZI1
instruction)/“H” level
One-sided edge detected
Both edges detected
Disabled
0
1
0
1
I21
I20
INT1 pin edge detection circuit control bit
INT1 pin
Enabled
timer 3 control enable bit
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction.
3: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.
26
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
TIMERS
• Fixed dividing frequency timer
The 4513/4514 Group has the programmable timers.
The fixed dividing frequency timer has the fixed frequency divid-
ing ratio (n). An interrupt request flag is set to “1” after every n
count of a count pulse.
• Programmable timer
The programmable timer has a reload register and enables the
frequency dividing ratio to be set. It is decremented from a setting
value n. When it underflows (count to n + 1), a timer interrupt re-
quest flag is set to “1,” new data is loaded from the reload
register, and count continues (auto-reload function).
FF16
n : Counter initial value
Count starts
Reload
Reload
n
1st underflow
2nd underflow
0016
Time
n+1 count
n+1 count
“1”
Timer interrupt
request flag
“0”
An interrupt occurs or
a skip instruction is executed.
Fig. 18 Auto-reload function
27
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
The 4513/4514 Group timer consists of the following circuits.
• Prescaler : frequency divider
• Timer 1 : 8-bit programmable timer
• Timer 2 : 8-bit programmable timer
• Timer 3 : 8-bit programmable timer
• Timer 4 : 8-bit programmable timer
(Timers 1 to 4 have the interrupt function, respectively)
• 16-bit timer
Prescaler and timers 1 to 4 can be controlled with the timer control
registers W1 to W6. The 16-bit timer is a free counter which is not
controlled with the control register.
Each function is described below.
Table 9 Function related timers
Frequency
dividing ratio
Control
register
Circuit
Count source
Use of output signal
Structure
Prescaler
Timer 1
• Instruction clock
4, 16
• Timer 1, 2, 3 and 4 count sources
• Timer 2 count source
• CNTR0 output
W1
W1
W6
Frequency divider
8-bit programmable
binary down counter
(link to P30/INT0 input)
8-bit programmable
binary down counter
• Prescaler output (ORCLK) 1 to 256
• Timer 1 interrupt
Timer 2
• Timer 1 underflow
1 to 256
• Timer 3 count source
• Timer 2 interrupt
W2
W6
• Prescaler output (ORCLK)
• CNTR0 input
• CNTR0 output
• 16-bit timer underflow
• Timer 2 underflow
Timer 3
Timer 4
8-bit programmable
binary down counter
(link to P31/INT1 input)
8-bit programmable
binary down counter
1 to 256
1 to 256
65536
• Timer 4 count source
• Timer 3 interrupt
• CNTR1 output
W3
W6
• Prescaler output (ORCLK)
• Timer 3 underflow
• Prescaler output (ORCLK)
• CNTR1 input
• Timer 4 interrupt
• CNTR1 output
W4
W6
16-bit timer 16-bit fixed dividing
frequency
• Instruction clock
• Watchdog timer
(The 15th bit is counted twice)
• Timer 2 count source
(16-bit timer underflow)
28
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Instruction clock
W1
Prescaler
3
W12
Divistion circuit
(divided by 2)
MR
3
0
0
1/4
Internal clock
generating circuit
(divided by 3)
1
0
1
1
1/16
X
IN
ORCLK
I1
2
I1
0
1
Falling One-sided edge
detection circuit
(Note 1)
W1
0
0
Q
P30/INT0
S
1
1
Both edges
detection circuit
1
0
Rising
I10
R
W1
1
(Note 3)
0
Timer 1
interrupt
T1F
Timer 1 (8)
Reload register R1 (8)
1
T1AB
T1AB
(TR1AB)
(TAB1)
Register B
Register A
Timer 1 underflow signal
3(Note 3)
W2
1,W20
W2
00
0
Timer 2
interrupt
01
Timer 2 (8)
T2F
1
10Not available
11
Reload register R2 (8)
(T2AB)
(TAB2)
Register B
Register A
I2
2
Timer 2 underflow signal
I2
1
0
Falling
One-sided edge
detection circuit
(Note 2)
0
W32
Q
P31/INT1
S
1
1
Both edges
detection circuit
1
0
Rising
I20
R
W3
00
1,W30
W33(Note 3)
0
01
T3F
Timer 3
interrupt
Timer 3 (8)
1
10Not available
11Not available
Reload register R3 (8)
T3AB
T3AB
(TR3AB)
(TAB3)
Register B
Register A
Timer 3 underflow signal
Timer 4 (8)
W4
00
1,W40
W43(Note 3)
0
1
01
Timer 4
interrupt
T4F
Not available
Not available
10
11
Reload register R4 (8)
(T4AB)
(TAB4)
Register B
Register A
Data is set automatically from each reload
register when timer 1, 2, 3, or 4 underflows
(auto-reload function)
16-bit timer (WDT)
1 - - - - - - - - - - - 15 16
Instruction clock
Notes 1: Timer 1 count start synchronous circuit is set
System reset
by the valid edge of P3
bits 1 (I1 ) and 2 (I1 ) of register I1.
2: Timer 3 count start synchronous circuit is set
by the valid edge of P3 /INT1 pin selected by
bits 1 (I2 ) and 2 (I2 ) of register I2.
3: Count source is stopped by clearing to “0.”
0/INT0 pin selected by
S
WRST instruction
Reset signal
WDF1 WDF2
1
2
WEF
Q
R
1
1
2
Fig. 19 Timers structure
29
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Table 10 Timer control registers
Timer control register W1
Prescaler control bit
at reset : 00002
Stop (state initialized)
Operating
at RAM back-up : 00002
R/W
0
1
0
1
0
1
0
1
W13
W12
W11
W10
Instruction clock divided by 4
Instruction clock divided by 16
Stop (state retained)
Prescaler dividing ratio selection bit
Timer 1 control bit
Operating
Count start synchronous circuit not selected
Count start synchronous circuit selected
Timer 1 count start synchronous circuit
control bit
Timer control register W2
Timer 2 control bit
at reset : 00002
at RAM back-up : state retained
R/W
0
1
0
1
Stop (state retained)
Operating
W23
W22
Not used
This bit has no function, but read/write is enabled.
W21
Count source
Timer 1 underflow signal
Prescaler output
W20
W21
W20
0
0
1
1
0
1
0
1
Timer 2 count source selection bits
CNTR0 input
16 bit timer (WDT) underflow signal
Timer control register W3
Timer 3 control bit
at reset : 00002
at RAM back-up : state retained
R/W
R/W
R/W
0
Stop (state retained)
Operating
W33
W32
1
0
1
Count start synchronous circuit not selected
Count start synchronous circuit selected
Count source
Timer 3 count start synchronous circuit
control bit
W31 W30
W31
W30
0
0
1
1
0
1
0
1
Timer 2 underflow signal
Prescaler output
Timer 3 count source selection bits
Not available
Not available
Timer control register W4
Timer 4 control bit
at reset : 00002
at RAM back-up : state retained
0
1
0
1
Stop (state retained)
Operating
W43
W42
Not used
This bit has no function, but read/write is enabled.
W41
Count source
Timer 3 underflow signal
Prescaler output
W40
W41
W40
0
0
1
1
0
1
0
1
Timer 4 count source selection bits
CNTR1 input
Not available
Timer control register W6
CNTR1 output control bit
at reset : 00002
at RAM back-up : state retained
0
Timer 3 underflow signal output divided by 2
W63
W62
W61
W60
1
0
1
0
1
0
1
CNTR1 output control by timer 4 underflow signal divided by 2
D7(I/O)/CNTR1 input
D7/CNTR1 function selection bit
CNTR0 output control bit
CNTR1 (I/O)/D7(input)
Timer 1 underflow signal output divided by 2
CNTR0 output control by timer 2 underflow signal divided by 2
D6(I/O)/CNTR0 input
D6/CNTR0 output control bit
CNTR0 (I/O)/D6(input)
Note: “R” represents read enabled, and “W” represents write enabled.
30
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(1) Timer control registers
(4) Timer 1 (interrupt function)
• Timer control register W1
Timer 1 is an 8-bit binary down counter with the timer 1 reload reg-
ister (R1). Data can be set simultaneously in timer 1 and the reload
register (R1) with the T1AB instruction. Data can be written to re-
load register (R1) with the TR1AB instruction.
Register W1 controls the count operation of timer 1, the selection
of count start synchronous circuit, and the frequency dividing ra-
tio and count operation of prescaler. Set the contents of this
register through register A with the TW1A instruction. The TAW1
instruction can be used to transfer the contents of register W1 to
register A.
When writing data to reload register R1 with the TR1AB instruction,
the downcount after the underflow is started from the setting value
of reload register R1.
• Timer control register W2
Timer 1 starts counting after the following process;
➀ set data in timer 1, and
Register W2 controls the count operation and count source of
timer 2. Set the contents of this register through register A with
the TW2A instruction. The TAW2 instruction can be used to trans-
fer the contents of register W2 to register A.
➀ set the bit 1 of register W1 to “1.”
However, P30/INT0 pin input can be used as the start trigger for
timer 1 count operation by setting the bit 0 of register W1 to “1.”
When a value set in timer 1 is n, timer 1 divides the count source
signal by n + 1 (n = 0 to 255).
• Timer control register W3
Register W3 controls the count operation and count source of
timer 3 and the selection of count start synchronous circuit. Set
the contents of this register through register A with the TW3A in-
struction. The TAW3 instruction can be used to transfer the
contents of register W3 to register A.
Once count is started, when timer 1 underflows (the next count
pulse is input after the contents of timer 1 becomes “0”), the timer
1 interrupt request flag (T1F) is set to “1,” new data is loaded from
reload register R1, and count continues (auto-reload function).
Data can be read from timer 1 with the TAB1 instruction. When
reading the data, stop the counter and then execute the TAB1 in-
struction. Timer 1 underflow signal divided by 2 can be output from
D6/CNTR0 pin.
• Timer control register W4
Register W4 controls the count operation and count source of
timer 4. Set the contents of this register through register A with
the TW4A instruction. The TAW4 instruction can be used to trans-
fer the contents of register W4 to register A.
• Timer control register W6
(5) Timer 2 (interrupt function)
Register W6 controls the D6/CNTR0 pin and D7/CNTR1 func-
tions, the selection and operation of the CNTR0 and CNTR1
output. Set the contents of this register through register A with
the TW6A instruction. The TAW6 instruction can be used to trans-
fer the contents of register W6 to register A.
Timer 2 is an 8-bit binary down counter with the timer 2 reload reg-
ister (R2). Data can be set simultaneously in timer 2 and the reload
register (R2) with the T2AB instruction.
Timer 2 starts counting after the following process;
➀ set data in timer 2,
➀ select the count source with the bits 0 and 1 of register W2, and
➀ set the bit 3 of register W2 to “1.”
(2) Precautions
Note the following for the use of timers.
When a value set in timer 2 is n, timer 2 divides the count source
signal by n + 1 (n = 0 to 255).
• Prescaler
Stop the prescaler operation to change its frequency dividing ra-
tio.
Once count is started, when timer 2 underflows (the next count
pulse is input after the contents of timer 2 becomes “0”), the timer
2 interrupt request flag (T2F) is set to “1,” new data is loaded from
reload register R2, and count continues (auto-reload function).
Data can be read from timer 2 with the TAB2 instruction. When
reading the data, stop the counter and then execute the TAB2 in-
struction. The output from D6/CNTR0 pin by timer 2 underflow
signal divided by 2 can be controlled.
• Count source
Stop timer 1, 2, 3, or 4 counting to change its count source.
• Reading the count value
Stop timer 1, 2, 3, or 4 counting and then execute the TAB1,
TAB2, TAB3, or TAB4 instruction to read its data.
• Writing to reload registers R1 and R3
When writing data to reload registers R1 or R3 while timer 1 or
timer 3 is operating, avoid a timing when timer 1 or timer 3
underflows.
(3) Prescaler
Prescaler is a frequency divider. Its frequency dividing ratio can be
selected. The count source of prescaler is the instruction clock.
Use the bit 2 of register W1 to select the prescaler dividing ratio
and the bit 3 to start and stop its operation. Prescaler is initialized,
and the output signal (ORCLK) stops when the bit 3 of register W1
is cleared to “0.”
31
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(6) Timer 3 (interrupt function)
(9) Timer I/O pin (D6/CNTR0, D7/CNTR1)
D6/CNTR0 pin has functions to input the timer 2 count source, and
to output the timer 1 and timer 2 underflow signals divided by 2. D7/
CNTR1 pin has functions to input the timer 4 count source, and to
output the timer 3 and timer 4 underflow signals divided by 2.
The selection of D6/CNTR0 pin function can be controlled with the
bit 0 of register W6. The selection of D7/CNTR1 pin function can be
controlled with the bit 2 of register W6.
Timer 3 is an 8-bit binary down counter with the timer 3 reload reg-
ister (R3). Data can be set simultaneously in timer 3 and the reload
register (R3) with the T3AB instruction. Data can be written to re-
load register (R3) with the TR3AB instruction.
When writing data to reload register R3 with the TR3AB instruction,
the downcount after the underflow is started from the setting value
of reload register R3.
Timer 3 starts counting after the following process;
➀ set data in timer 3,
The following signals can be selected for the CNTR0 output signal
with the bit 1 of register W6.
➀ select the count source with the bits 0 and 1 of register W3, and
➀ set the bit 3 of register W3 to “1.”
• timer 1 underflow signal divided by 2
• the signal of AND operation between timer 1 underflow signal di-
vided by 2 and timer 2 underflow signal divide by 2
The following signals can be selected for the CNTR1 output signal
with the bit 3 of register W6.
However, P31/INT1 pin input can be used as the start trigger for
timer 3 count operation by setting the bit 2 of register W3 to “1.”
When a value set in timer 3 is n, timer 3 divides the count source
signal by n + 1 (n = 0 to 255).
• timer 3 underflow signal divided by 2
Once count is started, when timer 3 underflows (the next count
pulse is input after the contents of timer 3 becomes “0”), the timer
3 interrupt request flag (T3F) is set to “1,” new data is loaded from
reload register R3, and count continues (auto-reload function).
Data can be read from timer 3 with the TAB3 instruction. When
reading the data, stop the counter and then execute the TAB3 in-
struction. Timer 3 underflow signal divided by 2 can be output from
D7/CNTR1 pin.
• the signal of AND operation between timer 3 underflow signal di-
vided by 2 and timer 4 underflow signal divide by 2
Timer 2 counts the rising waveform of CNTR0 input when the
CNTR0 input is selected as the count source.
Timer 4 counts the rising waveform of CNTR1 input when the
CNTR1 input is selected as the count source.
(10) Count start synchronous circuit (timer 1
and 3)
Each of timer 1 and timer 3 has the count start synchronous circuit
which synchronizes P30/INT0 pin and P31/INT1 pin, respectively,
and can start the timer count operation.
(7) Timer 4 (interrupt function)
Timer 4 is an 8-bit binary down counter with the timer 4 reload reg-
ister (R4). Data can be set simultaneously in timer 4 and the reload
register (R4) with the T4AB instruction.
Timer 1 count start synchronous circuit function is selected by set-
ting the bit 0 of register W1 to “1.” The control by P30/INT0 pin input
can be performed by setting the bit 0 of register I1 to “1.”
The count start synchronous circuit is set by level change (“H”→“L”
or “L”→“H”) of P30/INT0 pin input. This valid waveform is selected
by bits 1 (I11) and 2 (I12) of register I1 as follows;
Timer 4 starts counting after the following process;
➀ set data in timer 4,
➀ select the count source with the bits 0 and 1 of register W4, and
➀ set the bit 3 of register W4 to “1.”
When a value set in timer 4 is n, timer 4 divides the count source
signal by n + 1 (n = 0 to 255).
• I11 = “0”: Synchronized with one-sided edge (falling or rising)
• I11 = “1”: Synchronized with both edges (both falling and rising)
When register I11=“0” (synchronized with the one-sided edge), the ris-
ing or falling waveform can be selected by bit 2 of register I1;
• I12 = “0”: Falling waveform
Once count is started, when timer 4 underflows (the next count
pulse is input after the contents of timer 4 becomes “0”), the timer
4 interrupt request flag (T4F) is set to “1,” new data is loaded from
reload register R4, and count continues (auto-reload function).
Data can be read from timer 4 with the TAB4 instruction. When
reading the data, stop the counter and then execute the TAB4 in-
struction. The output from D7/CNTR1 pin by timer 4 underflow
signal divided by 2 can be controlled.
• I12 = “1”: Rising waveform
Timer 3 count start synchronous circuit function is selected by set-
ting the bit 2 of register W3 to “1.” The control by P31/INT1 pin input
can be performed by setting the bit 0 of register I2 to “1.”
The count start synchronous circuit is set by level change (“H”→“L”
or “L”→“H”) of P31/INT1 pin input. This valid waveform is selected
by bits 1 (I21) and 2 (I22) of register I2 as follows;
(8) Timer interrupt request flags (T1F, T2F,
T3F, and T4F)
Each timer interrupt request flag is set to “1” when each timer
underflows. The state of these flags can be examined with the skip
instructions (SNZT1, SNZT2, SNZT3, and SNZT4).
Use the interrupt control registers V1, V2 to select an interrupt or a
skip instruction.
• I21 = “0”: Synchronized with one-sided edge (falling or rising)
• I21 = “1”: Synchronized with both edges (both falling and rising)
When register I21=“0” (synchronized with the one-sided edge), the ris-
ing or falling waveform can be selected by bit 2 of register I2;
• I22 = “0”: Falling waveform
An interrupt request flag is cleared to “0” when an interrupt occurs
or when the next instruction is skipped with a skip instruction.
• I22 = “1”: Rising waveform
When timer 1 and timer 3 count start synchronous circuits are
used, the count start synchronous circuits are set, the count source
is input to each timer by inputting valid waveform to P30/INT0 pin
and P31/INT1 pin. Once set, the count start synchronous circuit is
cleared by clearing the bit I10 or I20 to “0” or reset.
32
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
When the count value of timer WDT reaches “BFFF16” or “3FFF16,”
the WDF1 flag is set to “1.” If the WRST instruction is never ex-
ecuted while timer WDT counts 32767, WDF2 flag is set to “1,” and
the RESET pin outputs “L” level to reset the microcomputer. Ex-
ecute the WRST instruction at each period of 32766 machine cycle
or less by software when using watchdog timer to keep the micro-
computer operating normally.
Watchdog timer provides a method to reset the system when a pro-
gram runs wild. Watchdog timer consists of a 16-bit timer (WDT),
watchdog timer enable flag (WEF), and watchdog timer flags
(WDF1, WDF2).
The timer WDT downcounts the instruction clocks as the count
source. The underflow signal is generated when the count value
reaches “000016.” This underflow signal can be used as the timer 2
count source.
To prevent the WDT stopping in the event of misoperation, WEF
flag is designed not to initialize once the WRST instruction has
been executed. Note also that, if the WRST instruction is never ex-
ecuted, the watchdog timer does not start.
When the WRST instruction is executed after system is released
from reset, the WEF flag is set to “1”. At this time, the watchdog
timer starts operating.
FFFF16
The value of timer (WDT)
0000 16
BFFF16
3FFF16
WEF flag
WDF1 flag
WDF2 flag
RESET pin output
WRST
instruction
executed
WRST
instruction
executed
System reset
Fig. 20 Watchdog timer function
The contents of WEF, WDF1 and WDF2 flags and timer WDT are
initialized at the RAM back-up mode.
•
•
•
•
•
•
If WDF2 flag is set to “1” at the same time that the microcomputer
enters the RAM back-up state, system reset may be performed.
When using the watchdog timer and the RAM back-up mode, ini-
tialize the WDF1 flag with the WRST instruction just before the
microcomputer enters the RAM back-up state (refer to Figure 21)
WRST
; WDF1 flag reset
EPOF
POF
; POF instruction enabled
Oscillation
stop
(RAM back-up state)
Fig. 21 Program example to enter the RAM back-up mode
when using the watchdog timer
33
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
SERIAL I/O
Table 11 Serial I/O pins
The 4513/4514 Group has a built-in clock synchronous serial I/O
which can serially transmit or receive 8-bit data.
Serial I/O consists of;
Pin
Pin function when selecting serial I/O
Clock I/O (SCK)
P20/SCK
P21/SOUT
P22/SIN
Serial data output (SOUT)
Serial data input (SIN)
• serial I/O register SI
• serial I/O mode register J1
Note: Input ports P20–P22 can be used regardless of register J1.
• serial I/O transmission/reception completion flag (SIOF)
• serial I/O counter
Registers A and B are used to perform data transfer with internal
CPU, and the serial I/O pins are used for external data transfer.
The pin functions of the serial I/O pins can be set with the register
J1.
Division circuit
(divided by 2)
MR
3
1
0
Internal clock
generation circuit
(divided by 3)
Instruction clock
XIN
J12
Serial I/O mode register J1
1
J13
J12
J11
J10
1/4
1/8
0
Synchronous
circuit
Serial I/O interrupt
SIOF
Serial I/O counter (3)
S
CK
P20/SCK
S
OUT
IN
P2
1
/SOUT
S
P2
2
/SIN
MSB
LSB
Serial I/O register SI (8)
TSIAB
TABSI
J10
Register B (4)
J11
Register A (4)
Note: The output structure of SCK and SOUT pins is N-channel open-drain.
Fig. 22 Serial I/O structure
Table 12 Serial I/O mode register
Serial I/O mode register J1
at reset : 00002
R/W
at RAM back-up : state retained
0
1
0
1
0
1
0
1
J13
J12
J11
J10
This bit has no function, but read/write is enabled.
Not used
Serial I/O internal clock dividing ratio
selection bit
Instruction clock signal divided by 8
Instruction clock signal divided by 4
Input ports P20, P21, P22 selected
Serial I/O port selection bit
Serial I/O ports SCK, SOUT, SIN/input ports P20, P21, P22 selected
External clock
Serial I/O synchronous clock selection bit
Internal clock (instruction clock divided by 4 or 8)
Note: “R” represents read enabled, and “W” represents write enabled.
34
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
When transmitting (D
7–D0
: transfer data)
When receiving
S
IN pin
SOUT pin
Serial I/O register (SI)
Serial I/O register (SI)
S
OUT pin
SIN pin
D
7
D
6
D
5
D
4
D
3
D
2
2
D
1
D
0
D7
D
6
7
D5
D6
D7
D4
D5
D6
D3
D4
D5
D
D1
D2
D3
D0
D1
D2
Transfer data to be set
Transfer started
D
D
3
4
D0
D
D
1
7
D
0
6
D
D
D5 D4 D3 D2 D1 D0
Transfer completed
Fig. 23 Serial I/O register state when transferring
(1) Serial I/O register SI
(3) Serial I/O start instruction (SST)
Serial I/O register SI is the 8-bit data transfer serial/parallel conver-
sion register. Data can be set to register SI through registers A and
B with the TSIAB instruction. The contents of register A is transmit-
ted to the low-order 4 bits of register SI, and the contents of
register B is transmitted to the high-order 4 bits of register SI.
During transmission, each bit data is transmitted LSB first from the
lowermost bit (bit 0) of register SI, and during reception, each bit
data is received LSB first to register SI starting from the topmost bit
(bit 7).
When the SST instruction is executed, the SIOF flag is cleared to
“0” and then serial I/O transmission/reception is started.
(4) Serial I/O mode register J1
Register J1 controls the synchronous clock, P20/SCK, P21/SOUT
and P22/SIN pin function. Set the contents of this register through
register A with the TJ1A instruction. The TAJ1 instruction can be
used to transfer the contents of register J1 to register A.
When register SI is used as a work register without using serial I/O,
pull up the SCK pin or set the pin function to an input port P20.
(2) Serial I/O transmission/reception
completion flag (SIOF)
Serial I/O transmission/reception completion flag (SIOF) is set to
“1” when serial data transmission or reception completes. The
state of SIOF flag can be examined with the skip instruction
(SNZSI). Use the interrupt control register V2 to select the inter-
rupt or the skip instruction.
The SIOF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
35
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(5) How to use serial I/O
Figure 24 shows the serial I/O connection example. Serial I/O inter-
wiring between each pin with a resistor. Figure 25 shows the data
transfer timing and Table 13 shows the data transfer sequence.
rupt is not used in this example. In the actual wiring, pull up the
Slave (external clock)
Master (clock control)
SRDY signal
D5
D5
SCK
SOUT
SIN
SCK
SIN
SOUT
(Bit 0)
1
(Bit 0)
0
(Bit 3)
(Bit 3)
1
1
Serial I/O mode register J1
✕
✕
Serial I/O mode register J1
✕
✕
Internal clock selected as
a synchronous clock
External clock selected as
a synchronous clock
Serial I/O port
SCK,SOUT,SIN
Serial I/O port
SCK,SOUT,SIN
Instruction clock divided by
8 or 4 selected as a transfer
clock
This bit is not valid
when J10=“0”
(Bit 3)
0
(Bit 0)
(Bit 3)
0
(Bit 0)
Interrupt control register V2
Interrupt control register V2
✕
✕
✕
✕
✕
✕
Serial I/O interrupt enable bit
(SNZSI instruction is valid)
Serial I/O interrupt enable bit
(SNZSI instruction is valid)
✕ : Set an arbitrary value.
Fig. 24 Serial I/O connection example
36
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Master
M3
M4
M5
M6
M7
S
OUT
M7
’
M0
M1
M2
SIN
S7
’
S0
S1
S2
S3
S4
S5
S6
S7
SST instruction
SCK
Slave
SST instruction
SRDY signal
S0
S1
S2
S3
S4
S5
S6
S7
S
OUT
S7’
SIN
M7
’
M0
M1
M2
M3
M4
M5
M6
M7
M0–M7
: the contents of master serial I/O
S0
–S : the contents of slave serial I/O register
7
Rising of SCK : serial input Falling of SCK : serial output
Fig. 25 Timing of serial I/O data transfer
37
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Table 13 Processing sequence of data transfer from master to slave
Master (transmission)
Slave (reception)
[Initial setting]
[Initial setting]
• Setting serial I/O mode register J1, and interrupt control register V2 shown in
• Setting the serial I/O mode register J1 and inter-
Figure 24.
rupt control register V2 shown in Figure 24.
TJ1A and TV2A instructions
TJ1A and TV2A instructions
• Setting the port transmitted the reception enable signal (SRDY) and outputting
“H” level (reception impossible).
• Setting the port received the reception enable
signal (SRDY) to the input mode.
(Port D5 is used in this example)
SD instruction
(Port D5 is used in this example)
SD instruction
*[Reception enable state]
* [Transmission enable state]
• Storing transmission data to serial I/O register SI. • The SIOF flag is cleared to “0.”
TSIAB instruction
SST instruction
• “L” level (reception possible) is output from port D5.
RD instruction
[Reception]
[Transmission]
•Check port D5 is “L” level.
SZD instruction
•Serial transfer starts.
SST instruction
•Check transmission completes.
SNZSI instruction
• Check reception completes.
SNZSI instruction
•Wait (timing when continuously transferring)
• “H” level is output from port D5.
SD instruction
[Data processing]
1-byte data is serially transferred on this process. Subsequently, data
can be transferred continuously by repeating the process from *.
When an external clock is selected as a synchronous clock, the
clock is not controlled internally. Control the clock externally be-
cause serial transfer is performed as long as clock is externally
input. (Unlike an internal clock, an external clock is not stopped
when serial transfer is completed.) However, the SIOF flag is set to
“1” when the clock is counted 8 times after executing the SST in-
struction. Be sure to set the initial level of the external clock to “H.”
38
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
A-D CONVERTER
Table 14 A-D converter characteristics
Parameter
Conversion format
Resolution
Characteristics
Successive comparison method
10 bits
The 4513/4514 Group has a built-in A-D conversion circuit that
performs conversion by 10-bit successive comparison method.
Table 14 shows the characteristics of this A-D converter. This A-
D converter can also be used as an 8-bit comparator to compare
analog voltages input from the analog input pin with preset val-
ues.
Relative accuracy
Linearity error: ±2LSB
Non-linearity error: ±0.9LSB
Conversion speed
Analog input pin
46.5 µs (High-speed mode at 4.0 MHz
oscillation frequency)
4 for 4513 Group
8 for 4514 Group
Register B (4)
Register A (4)
4
8
4
8
4
4
TAQ2
TQ2A
TAQ1
TQ1A
IAP4
(P4 P4
2
0
—
3)
Q23 Q22 Q21 Q20
Q13
Q12 Q11 Q10
TALA
TABAD
TADAB
Instruction clock
OP4A
(P4 P4
1/6
0
—
3)
3
Q23
0
ADF
(1)
A-D control circuit
(Note 3)
IN0/CMP0-
A-D interrupt
1
A
A
IN1/CMP0+
IN2/CMP1-
IN3/CMP1+
1
Successive comparison
register (AD) (10)
Comparator
A
0
A
Q2
3
Q2
3
8
10
P4
P4
P4
0
1
2
/AIN4
/AIN5
/AIN6
10
1
0
1
0
1
DAC
operation
signal
Q23
P43/AIN7
8
8
8
DA converter
(Note 1)
V
DD
VSS
Comparator register (8)
(Note 2)
Notes 1: This switch is turned ON only when A-D converter is operating and generates the comparison voltage.
2: Writing/reading data to the comparator register is possible only in the comparator mode (Q2 =1).
The value of the comparator register is retained even when the mode is switched to the A-D conversion
mode (Q2 =0) because it is separated from the successive comparison register (AD). Also, the resolution in
the comparator mode is 8 bits because the comparator register consists of 8 bits.
3: The 4513 Group does not have ports P4 /AIN4–P4 /AIN7 and the IAP4 and OP4A instructions.
3
3
0
3
Fig. 26 A-D conversion circuit structure
39
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Table 15 A-D control registers
at reset : 00002
A-D control register Q1
at RAM back-up : state retained
R/W
0
1
Not used
This bit has no function, but read/write is enabled.
Q13
Q12
Q12Q11Q10
Selected pins
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AIN0
AIN1
AIN2
Q11
Q10
Analog input pin selection bits (Note 2)
AIN3
AIN4 (Not available for the 4513 Group)
AIN5 (Not available for the 4513 Group)
AIN6 (Not available for the 4513 Group)
AIN7 (Not available for the 4513 Group)
A-D control register Q2
at reset : 00002
at RAM back-up : state retained
R/W
0
1
0
1
0
1
0
1
A-D conversion mode
Comparator mode
Q23
Q22
Q21
Q20
A-D operation mode selection bit
P43/AIN7 and P42/AIN6 pin function selec-
tion bit (Not used for the 4513 Group)
P41/AIN5 pin function selection bit
(Not used for the 4513 Group)
P43, P42
(read/write enabled for the 4513 Group)
AIN7, AIN6/P43, P42 (read/write enabled for the 4513 Group)
P41
(read/write enabled for the 4513 Group)
(read/write enabled for the 4513 Group)
(read/write enabled for the 4513 Group)
(read/write enabled for the 4513 Group)
AIN5/P41
P40
P40/AIN4 pin function selection bit
(Not used for the 4513 Group)
AIN4/P40
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Select AIN4–AIN7 with register Q1 after setting register Q2.
(1) Operating at A-D conversion mode
The A-D conversion mode is set by setting the bit 3 of register Q2 to “0.”
(4) A-D conversion start instruction (ADST)
A-D conversion starts when the ADST instruction is executed. The
conversion result is automatically stored in the register AD.
(2) Successive comparison register AD
Register AD stores the A-D conversion result of an analog input in
10-bit digital data format. The contents of the high-order 8 bits of
this register can be stored in register B and register A with the
TABAD instruction. The contents of the low-order 2 bits of this reg-
ister can be stored into the high-order 2 bits of register A with the
TALA instruction. However, do not execute this instruction during A-
D conversion.
(5) A-D control register Q1
Register Q1 is used to select one of analog input pins. The 4513
Group does not have AIN4–AIN7. Accordingly, do not select these
pins with register Q1.
(6) A-D control register Q2
Register Q2 is used to select the pin function of P40/AIN4, P41/
AIN5, P42/AIN6, and P43/AIN7. The A-D conversion mode is se-
lected when the bit 3 of register Q2 is “0,” and the comparator
mode is selected when the bit 3 of register Q2 is “1.” After set this
register, select the analog input with register Q1.
When the contents of register AD is n, the logic value of the com-
parison voltage Vref generated from the built-in DA converter can
be obtained with the reference voltage VDD by the following for-
mula:
Even when register Q2 is used to set the pins for analog input,
P40/AIN4–P43/AIN7 continue to function as P40–P43 I/O. Accord-
ingly, when any of them are used as I/O port P4 and others are
used as analog input pins, make sure to set the outputs of pins that
are set for analog input to “1.” Also, for the port input, the port input
function of the pin functions as analog input is undefined.
Logic value of comparison voltage Vref
VDD
Vref =
✕ n
1024
n: The value of register AD (n = 0 to 1023)
(3) A-D conversion completion flag (ADF)
A-D conversion completion flag (ADF) is set to “1” when A-D con-
version completes. The state of ADF flag can be examined with the
skip instruction (SNZAD). Use the interrupt control register V2 to
select the interrupt or the skip instruction.
The ADF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
40
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(7) Operation description
The 4513/4514 Group repeats this operation to the lowermost bit of
the register AD to convert an analog value to a digital value. A-D
conversion stops after 62 machine cycles (46.5 µs when f(XIN) =
4.0 MHz in high-speed mode) from the start, and the conversion re-
sult is stored in the register AD. An A-D interrupt activated condition
is satisfied and the ADF flag is set to “1” as soon as A-D conversion
completes (Figure 27).
A-D conversion is started with the A-D conversion start instruction
(ADST). The internal operation during A-D conversion is as follows:
✕ When A-D conversion starts, the register AD is cleared to
“00016.”
✕ Next, the topmost bit of the register AD is set to “1,” and the
comparison voltage Vref is compared with the analog input volt-
age VIN.
✕ When the comparison result is Vref < VIN, the topmost bit of the
register AD remains set to “1.” When the comparison result is
Vref > VIN, it is cleared to “0.”
Table 16 Change of successive comparison register AD during A-D conversion
Comparison voltage (Vref) value
VDD
At starting conversion
1st comparison
Change of successive comparison register AD
-------------
VDD
2
-----
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
-------------
-------------
VDD
2
-----
✕1
✕1
2nd comparison
3rd comparison
±
-------------
4
VDD
4
-------------
VDD
2
VDD
8
-----
✕2
±
±
±
±
-------------
A-D conversion result
After 10th comparison
completes
VDD
2
VDD
-------------
-----
✕1
✕2
✕3
✕8
✕9
✕A
1024
-------------
✕2: 2nd comparison result
✕8: 8th comparison result
✕A: 10th comparison result
✕1: 1st comparison result
✕3: 3rd comparison result
✕9: 9th comparison result
41
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(8) A-D conversion timing chart
Figure 27 shows the A-D conversion timing chart.
ADST instruction
62 machine cycles
A-D conversion
completion flag (ADF)
DAC operation signal
Fig. 27 A-D conversion timing chart
(9) How to use A-D conversion
How to use A-D conversion is explained using as example in which
the analog input from P40/AIN4 pin is A-D converted, and the high-
order 4 bits of the converted data are stored in address M(Z, X, Y)
= (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1),
and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM.
The A-D interrupt is not used in this example.
✕ After selecting the AIN4 pin function with the bit 0 of the register
Q2, select AIN4 pin and A-D conversion mode with the register
Q1 (refer to Figure 28).
(Bit 3)
(Bit 0)
A-D control register Q2
0
✕
✕
1
✕ Execute the ADST instruction and start A-D conversion.
✕ Examine the state of ADF flag with the SNZAD instruction to de-
termine the end of A-D conversion.
AIN4 function selected
A-D conversion mode
✕ Transfer the low-order 2 bits of converted data to the high-order
2 bits of register A (TALA instruction).
(Bit 3)
(Bit 0)
✕ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2).
✕ Transfer the high-order 8 bits of converted data to registers A
and B (TABAD instruction).
✕
1
0
0
A-D control register Q1
AIN4 pin selected
✕ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1).
✕ Transfer the contents of register B to register A, and then, store
into M(Z, X, Y) = (0, 0, 0).
✕✕: Set an arbitrary value
Fig. 28 Setting registers
42
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(10) Operation at comparator mode
The A-D converter is set to comparator mode by setting bit 3 of the
register Q2 to “1.”
(12) Comparison result store flag (ADF)
In comparator mode, the ADF flag, which shows completion of A-D
conversion, stores the results of comparing the analog input volt-
age with the comparison voltage. When the analog input voltage is
lower than the comparison voltage, the ADF flag is set to “1.” The
state of ADF flag can be examined with the skip instruction
(SNZAD). Use the interrupt control register V2 to select the inter-
rupt or the skip instruction.
Below, the operation at comparator mode is described.
(11) Comparator register
In comparator mode, the built-in DA comparator is connected to the
comparator register as a register for setting comparison voltages.
The contents of register B is stored in the high-order 4 bits of the
comparator register and the contents of register A is stored in the
low-order 4 bits of the comparator register with the TADAB instruc-
tion.
The ADF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
(13) Comparator operation start instruction
(ADST instruction)
When changing from A-D conversion mode to comparator mode,
the result of A-D conversion (register AD) is undefined.
However, because the comparator register is separated from regis-
ter AD, the value is retained even when changing from comparator
mode to A-D conversion mode. Note that the comparator register
can be written and read at only comparator mode.
In comparator mode, executing ADST starts the comparator oper-
ating.
The comparator stops 8 machine cycles after it has started (6 µs at
f(XIN) = 4.0 MHz in high-speed mode). When the analog input volt-
age is lower than the comparison voltage, the ADF flag is set to “1.”
If the value in the comparator register is n, the logic value of com-
parison voltage Vref generated by the built-in DA converter can be
determined from the following formula:
(14) Notes for the use of A-D conversion 1
Note the following when using the analog input pins also for I/O
port P4 functions:
Logic value of comparison voltage Vref
• Even when P40/AIN4–P43/AIN7 are set to pins for analog input,
they continue to function as P40–P43 I/O. Accordingly, when any
of them are used as I/O port P4 and others are used as analog
input pins, make sure to set the outputs of pins that are set for
analog input to “1.” Also, the port input function of the pin func-
tions as an analog input is undefined.
VDD
Vref =
✕ n
256
n: The value of register AD (n = 0 to 255)
• TALA instruction
When the TALA instruction is executed, the low-order 2 bits of
register AD is transferred to the high-order 2 bits of register A, si-
multaneously, the low-order 2 bits of register A is “0.”
ADST instruction
8 machine cycles
Comparison result
store flag(ADF)
DAC operation signal
Comparator operation completed.
(The value of ADF is determined)
Fig. 29 Comparator operation timing chart
43
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(15) Notes for the use of A-D conversion 2
Do not change the operating mode (both A-D conversion mode and
comparator mode) of A-D converter with bit 3 of register Q2 while
A-D converter is operating.
(16) Definition of A-D converter accuracy
The A-D conversion accuracy is defined below (refer to Figure 30).
• Relative accuracy
When the operating mode of A-D converter is changed from the
comparator mode to A-D conversion mode with the bit 3 of register
Q2, note the following;
✕ Zero transition voltage (V0T)
This means an analog input voltage when the actual A-D con-
version output data changes from “0” to “1.”
✕ Full-scale transition voltage (VFST)
• Clear bit 2 of register V2 to “0” to change the operating mode of
the A-D converter from the comparator mode to A-D conversion
mode with the bit 3 of register Q2.
This means an analog input voltage when the actual A-D con-
version output data changes from “1023” to ”1022.”
✕ Linearity error
• The A-D conversion completion flag (ADF) may be set when the
operating mode of the A-D converter is changed from the com-
parator mode to the A-D conversion mode. Accordingly, set a
value to register Q2, and execute the SNZAD instruction to clear
the ADF flag.
This means a deviation from the line between V0T and VFST of
a converted value between V0T and VFST.
✕ Differential non-linearity error
This means a deviation from the input potential difference re-
quired to change a converter value between V0T and VFST by 1
LSB at the relative accuracy.
• Absolute accuracy
This means a deviation from the ideal characteristics between 0
to VDD of actual A-D conversion characteristics.
Output data
Full-scale transition voltage (VFST)
1023
1022
b–a
a
Differential non-linearity error =
c
[LSB]
Linearity error =
[LSB]
a
b
a
n+1
n
Actual A-D conversion
characteristics
c
a: 1LSB by relative accuracy
b: Vn+1–Vn
c: Difference between ideal Vn
and actual Vn
Ideal line of A-D conversion
between V0–V1022
1
0
Vn
Vn+1
V0
V1
V1022
VDD
Analog voltage
Zero transition voltage (V0T)
Fig. 30 Definition of A-D conversion accuracy
Vn: Analog input voltage when the output data changes from “n” to “n+1” (n = 0 to 1022)
VFST–V0T
• 1LSB at relative accuracy →
(V)
1022
VDD
• 1LSB at absolute accuracy →
(V)
1024
44
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
VOLTAGE COMPARATOR
Table 17 Voltage comparator characteristics
Parameter Characteristics
Voltage comparator function 2 circuits (CMP0, CMP1)
The 4513/4514 Group has 2 voltage comparator circuits that
perform comparison of voltage between 2 pins. Table 17 shows
the characteristics of this voltage comparison.
Input pin
CMP0-, CMP0+
(also used as AIN0, AIN1)
CMP1-, CMP1+
(also used as AIN2, AIN3)
3.0 V to 5.5 V
Supply voltage
Input voltage
0.3 VDD to 0.7 VDD
Typ. 20 mV, Max.100 mV
Max. 20 µs
Comparison check error
Response time
CMP0–/AIN0
–
CMP0
+
CMP0+/AIN1
–
CMP1–/AIN2
CMP1
+
CMP1+/AIN3
Q33
Q32
Q31
Q3
Voltage comparator control register Q3 (4)
0
TQ3A
TAQ3
Register A (4)
Note: Bits 0 and 1 of register Q3 can be only read.
Fig. 31 Voltage comparator structure
45
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Table 18 Voltage comparator control register Q3
at reset : 00002
R/W
Voltage comparator control register Q3 (Note 2)
at RAM back-up : state retained
0
1
0
1
0
1
0
1
Voltage comparator (CMP1) invalid
Voltage comparator (CMP1) valid
Voltage comparator (CMP0) invalid
Voltage comparator (CMP0) valid
CMP1- > CMP1+
Q33
Q32
Q31
Q30
Voltage comparator (CMP1) control bit
Voltage comparator (CMP0) control bit
CMP1 comparison result store bit
CMP0 comparison result store bit
CMP1- < CMP1+
CMP0- > CMP0+
CMP0- < CMP0+
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Bits 0 and 1 of register Q3 can be only read.
(1) Voltage comparator control register Q3
Register Q3 controls the function of the voltage comparator.
The function of the voltage comparator CMP0 becomes valid by
setting bit 2 of register Q3 to “1,” and becomes invalid by setting bit
2 of register Q3 to ”0.” The comparison result of the voltage com-
parator CMP0 is stored into bit 0 of register Q3.
(3) Precautions
When the voltage comparator is used, note the following;
• Voltage comparator function
When the voltage comparator function is valid with the voltage
comparator control register Q3, it is operating even in the RAM
back-up mode. Accordingly, be careful about such state because
it causes the increase of the operation current in the RAM back-
up mode.
The function of the voltage comparator CMP1 becomes valid by
setting bit 3 of register Q3 to “1,” and becomes invalid by setting bit
3 of register Q3 to ”0.” The comparison result of the voltage com-
parator CMP1 is stored into bit 1 of register Q3.
In order to reduce the operation current in the RAM back-up
mode, invalidate (bits 2 and 3 of register Q3 = “0”) the voltage
comparator function by software before the POF instruction is
executed.
(2) Operation description of voltage
comparator
The voltage comparator function becomes valid by setting each
control bit of register Q3 to “1” and compares the voltage of the in-
put pin. The comparison result is stored into each comparison
result store bit of register Q3.
Also, while the voltage comparator function is valid, current is al-
ways consumed by voltage comparator. On the system required
for the low-power dissipation, invalidate the voltage comparator
by software when it is unused.
The comparison result is as follows;
• Register Q3
• When CMP0- > CMP0+, Q30 = “0”
Bits 0 and 1 of register Q3 can be only read. Note that they can-
not be written.
When CMP0- < CMP0+, Q30 = “1”
• When CMP1- > CMP1+, Q31 = “0”
When CMP1- < CMP1+, Q31 = “1”
• Reading the comparison result of voltage comparator
Read the voltage comparator comparison result from register Q3
after the voltage comparator response time (max. 20 µs) is
passed from the voltage comparator function becomes valid.
46
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
RESET FUNCTION
System reset is performed by applying “L” level to RESET pin for
1 machine cycle or more when the following condition is satisfied;
the value of supply voltage is the minimum value or more of the
recommended operating conditions.
Then when “H” level is applied to RESET pin, software starts from
address 0 in page 0.
f(XIN
)
(Note)
is counted 16892 to
RESET
f(XIN
)
Software starts
(address 0 in page 0)
16895 times.
Note: It depends on the internal state of the microcomputer
when reset is performed.
Fig. 32 Reset release timing
Reset input
f(XIN
)
is counted 16892 to
1 machine cycle or more
16895 times.
0.85VDD
Software starts
(address 0 in page 0)
RESET
0.3VDD
(Note)
Note: Keep the value of supply voltage to the minimum value
or more of the recommended operating conditions.
Fig. 33 RESET pin input waveform and reset operation
47
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(1) Power-on reset
Reset can be performed automatically at power on (power-on re-
set) by connecting resistors, a diode, and a capacitor to RESET
pin. Connect RESET pin and the external circuit at the shortest dis-
tance.
V
DD
VDD
RESET pin voltage
Internal reset signal
RESET pin
(Note)
Reset state
Voltage drop detection circuit
Watchdog timer output
Internal reset signal
WEF
Reset released
Power-on
Note:
Applied potential to RESET pin must be VDD or less.
This symbol represents a parasitic diode.
Fig. 34 Power-on reset circuit example
(2) Internal state at reset
Table 19 shows port state at reset, and Figure 35 shows internal
state at reset (they are the same after system is released from re-
set). The contents of timers, registers, flags and RAM except
shown in Figure 35 are undefined, so set the initial value to them.
Table 19 Port state at reset
State
Name
Function
D0–D5
D0–D5
High impedance (Note)
D6/CNTR0, D7/CNTR1
P00–P03
D6, D7
P00–P03
P10–P13
P20–P22
P30, P31
P32, P33
P40–P43
P50–P53
High impedance (Notes 1, 2)
High impedance
P10–P13
P20/SCK, P21/SOUT, P22/SIN
P30/INT0, P31/INT1
P32, P33 (Note 4)
P40/AIN4–P43/AIN7 (Note 4)
P50–P53 (Note 4)
High impedance (Note 1)
High impedance (Note 1)
High impedance (Note 3)
Notes 1: Output latch is set to “1.”
2: Pull-up transistor is turned OFF.
3: After system is released from reset, port P5 is in the input mode. (Direction register FR0 = 00002)
4: The 4513 Group does not have these ports.
48
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
• Program counter (PC) ............................................................................00000
Address 0 in page 0 is set to program counter.
0
0
0
0
0
0
0
0
0
• Interrupt enable flag (INTE)..................................................................................................
• Power down flag (P) .............................................................................................................
• External 0 interrupt request flag (EXF0) ..............................................................................
• External 1 interrupt request flag (EXF1) ..............................................................................
0
(Interrupt disabled)
0
0
0
• Interrupt control register V1................................................................................
0
0
0
0
(Interrupt disabled)
(Interrupt disabled)
• Interrupt control register V2................................................................................000
• Interrupt control register I1 .................................................................................000
• Interrupt control register I2 .................................................................................000
• Timer 1 interrupt request flag (T1F) .....................................................................................
• Timer 2 interrupt request flag (T2F) .....................................................................................
• Timer 3 interrupt request flag (T3F) .....................................................................................
• Timer 4 interrupt request flag (T4F) .....................................................................................
• Watchdog timer flags (WDF1, WDF2)..................................................................................
• Watchdog timer enable flag (WEF) ......................................................................................
0
0
0
0
0
0
0
0
0
• Timer control register W1 ...................................................................................
0
0
0
0
(Prescaler and timer 1 stopped)
(Timer 2 stopped)
• Timer control register W2 ...................................................................................000
• Timer control register W3 ...................................................................................
0
0
0
0
0
(Timer 3 stopped)
• Timer control register W4 ...................................................................................000
• Timer control register W6 ...................................................................................000
• Clock control register MR ...................................................................................100
• Serial I/O transmission/reception completion flag (SIOF) ...................................................
0
(Timer 4 stopped)
0
0
0
(External clock selected and serial
I/O port not selected)
• Serial I/O mode register J1 ................................................................................
0
0
0
0
✕
✕
• Serial I/O register SI ..................................................................✕✕✕✕✕
• A-D conversion completion flag (ADF) .................................................................................
• A-D control register Q1 .......................................................................................000
• A-D control register Q2 .......................................................................................000
✕
0
0
0
• Voltage comparator control register Q3 .............................................................
0
0
0
0
✕
✕ ✕ ✕
• Successive comparison register AD ............................✕✕✕✕✕
• Comparator register...................................................................✕✕✕✕✕✕✕
• Key-on wakeup control register K0 ....................................................................000
• Pull-up control register PU0 ...............................................................................000
• Direction register FR0 ........................................................................................000
• Carry flag (CY) ......................................................................................................................
✕
✕
0
0
0
(Port P5: input mode)
0
• Register A ...........................................................................................................
0
0
0
0
• Register B ...........................................................................................................000
• Register D .................................................................................................................✕✕
0
✕
✕
0
✕
✕
• Register E ..................................................................................✕✕✕✕✕
• Register X ...........................................................................................................000
• Register Y ...........................................................................................................
0
0
0
0
• Register Z ........................................................................................................................✕
• Stack pointer (SP) ....................................................................................................11
✕
1
“✕” represents undefined.
Fig. 35 Internal state at reset
49
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
VOLTAGE DROP DETECTION CIRCUIT
The built-in voltage drop detection circuit is designed to detect a
drop in voltage and to reset the microcomputer if the supply voltage
drops below a set value.
RESET pin
Internal reset signal
Voltage drop detection circuit
Watchdog timer output
WEF
Note: The output structure of RESET pin is N-channel open-drain.
Fig. 36 Voltage drop detection reset circuit
V
DD
V
RST (detection voltage)
Voltage drop detection
circuit output
The microcomputer starts
operation after f(XIN) is counted
16892 to 16895 times.
RESET pin
Notes 1: Pull-up RESET pin externally.
2: Refer to the voltage drop detection circuit in the electrical characteristics
for the rating value of VRST (detection voltage).
Fig. 37 Voltage drop detection circuit operation waveform
50
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
RAM BACK-UP MODE
Table 20 Functions and states retained at RAM back-up
The 4513/4514 Group has the RAM back-up mode.
When the EPOF and POF instructions are executed continuously,
system enters the RAM back-up state. The POF instruction is
equal to the NOP instruction when the EPOF instruction is not ex-
ecuted before the POF instruction.
Function
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
RAM back-up
✕
O
Port level
O
As oscillation stops retaining RAM, the function of reset circuit and
states at RAM back-up mode, current dissipation can be reduced
without losing the contents of RAM. Table 20 shows the function
and states retained at RAM back-up. Figure 38 shows the state
transition.
Timer control register W1
✕
O
Timer control registers W2 to W4, W6
Clock control register MR
✕
✕
Interrupt control registers V1, V2
Interrupt control registers I1, I2
Timer 1 function
O
✕
(1) Identification of the start condition
(Note 3)
Timer 2 function
Warm start (return from the RAM back-up state) or cold start (re-
turn from the normal reset state) can be identified by examining the
state of the power down flag (P) with the SNZP instruction.
Timer 3 function
(Note 3)
(Note 3)
Timer 4 function
A-D conversion function
✕
O
(2) Warm start condition
A-D control registers Q1, Q2
Voltage comparator function
Voltage comparator control register Q3
Serial I/O function
When the external wakeup signal is input after the system enters
the RAM back-up state by executing the EPOF and POF instruc-
tions continuously, the CPU starts executing the program from
address 0 in page 0. In this case, the P flag is “1.”
O (Note 5)
O
✕
Serial I/O mode register J1
Pull-up control register PU0
Key-on wakeup control register K0
Direction register FR0
O
O
O
(3) Cold start condition
The CPU starts executing the program from address 0 in page 0
O
when;
✕
External 0 interrupt request flag (EXF0)
External 1 interrupt request flag (EXF1)
Timer 1 interrupt request flag (T1F)
Timer 2 interrupt request flag (T2F)
Timer 3 interrupt request flag (T3F)
Timer 4 interrupt request flag (T4F)
Watchdog timer flags (WDF1, WDF2)
Watchdog timer enable flag (WEF)
16-bit timer (WDT)
• reset pulse is input to RESET pin, or
• reset by watchdog timer is performed, or
• voltage drop detection circuit detects the voltage drop.
In this case, the P flag is “0.”
✕
✕
(Note 3)
(Note 3)
(Note 3)
✕ (Note 4)
✕ (Note 4)
✕ (Note 4)
✕
A-D conversion completion flag (ADF)
Serial I/O transmission/reception completion flag
(SIOF)
✕
✕
Interrupt enable flag (INTE)
Notes 1:“O” represents that the function can be retained, and “✕” repre-
sents that the function is initialized.
Registers and flags other than the above are undefined at RAM
back-up, and set an initial value after returning.
2: The stack pointer (SP) points the level of the stack register and is
initialized to “7” at RAM back-up.
3: The state of the timer is undefined.
4: Initialize the watchdog timer with the WRST instruction, and then
execute the POF instruction.
5: The state is retained when the voltage comparator function is se-
lected with the voltage comparator control register Q3.
51
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(4) Return signal
An external wakeup signal is used to return from the RAM back-up
mode because the oscillation is stopped. Table 21 shows the return
condition for each return source.
(5) Ports P0 and P1 control registers
• Key-on wakeup control register K0
Register K0 controls the ports P0 and P1 key-on wakeup func-
tion. Set the contents of this register through register A with the
TK0A instruction. In addition, the TAK0 instruction can be used to
transfer the contents of register K0 to register A.
• Pull-up control register PU0
Register PU0 controls the ON/OFF of the ports P0 and P1 pull-up
transistor. Set the contents of this register through register A with
the TPU0A instruction. In addition, the TAPU0 instruction can be
used to transfer the contents of register PU0 to register A.
Table 21 Return source and return condition
Remarks
Return source
Ports P0, P1
Return condition
Set the port using the key-on wakeup function selected with register K0 to
“H” level before going into the RAM back-up state because the port P0
shares the falling edge detection circuit with port P1.
Return by an external falling
edge input (“H”→“L”).
Select the return level (“L” level or “H” level) with the bit 2 of register I1 ac-
cording to the external state before going into the RAM back-up state.
Return by an external “H” level or
“L” level input.
The EXF0 flag is not set.
Port P30/INT0
Port P31/INT1
Select the return level (“L” level or “H” level) with the bit 2 of register I2 ac-
cording to the external state before going into the RAM back-up state.
Return by an external “H” level or
“L” level input.
The EXF1 flag is not set.
52
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
A
B
POF instruction
is executed
(Stabilizing time a )
f(XIN) stop
Reset
f(XIN) oscillation
Return input
(RAM back-up
mode)
(Stabilizing time a )
Stabilizing time a : Time required to stabilize the f(XIN) oscillation is automatically generated by hardware.
Fig. 38 State transition
Power down flag P
POF instruction
S
Q
Software start
Reset input or
voltage drop detection
circuit output
Yes
P = “1”
?
R
No
✕ Set source • • • • • • • POF instruction is executed
✕ Clear source• • • • • •Reset input
Warm start
Cold start
Fig. 39 Set source and clear source of the P flag
Fig. 40 Start condition identified example using the SNZP in-
struction
53
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Table 22 Key-on wakeup control register, pull-up control register, and interrupt control register
Key-on wakeup control register K0
at reset : 00002
at RAM back-up : state retained
R/W
R/W
R/W
Pins P12 and P13 key-on wakeup
control bit
0
1
0
1
0
1
0
1
Key-on wakeup not used
K03
K02
K01
K00
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Pins P10 and P11 key-on wakeup
control bit
Pins P02 and P03 key-on wakeup
control bit
Pins P00 and P01 key-on wakeup
control bit
Pull-up control register PU0
at reset : 00002
at RAM back-up : state retained
Pins P12 and P13 pull-up transistor
control bit
0
1
0
1
0
1
0
1
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
PU03
PU02
PU01
PU00
Pins P10 and P11 pull-up transistor
control bit
Pins P02 and P03 pull-up transistor
control bit
Pins P00 and P01 pull-up transistor
control bit
Interrupt control register I1
Not used
at RAM back-up : state retained
at reset : 00002
0
1
I13
I12
This bit has no function, but read/write is enabled.
Falling waveform (“L” level of INT0 pin is recognized with the SNZI0
0
1
Interrupt valid waveform for INT0 pin/
return level selection bit (Note 2)
instruction)/“L” level
Rising waveform (“H” level of INT0 pin is recognized with the SNZI0
instruction)/“H” level
One-sided edge detected
Both edges detected
Disabled
0
1
0
1
I11
I10
INT0 pin edge detection circuit control bit
INT0 pin
timer 1 control enable bit
Enabled
Interrupt control register I2
Not used
at reset : 00002
at RAM back-up : state retained
R/W
0
1
I23
I22
This bit has no function, but read/write is enabled.
Falling waveform (“L” level of INT1 pin is recognized with the SNZI1
0
1
instruction)/“L” level
Interrupt valid waveform for INT1 pin/
return level selection bit (Note 3)
Rising waveform (“H” level of INT1 pin is recognized with the SNZI1
instruction)/“H” level
One-sided edge detected
Both edges detected
Disabled
0
1
0
1
I21
I20
INT1 pin edge detection circuit control bit
INT1 pin
Enabled
timer 3 control enable bit
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction.
3: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.
54
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
• Control circuit to switch the middle-speed mode and high-speed
mode
CLOCK CONTROL
The clock control circuit consists of the following circuits.
• Control circuit to return from the RAM back-up state
• System clock generating circuit
• Control circuit to stop the clock oscillation
System clock
MR3
Division circuit
(divided by 2)
Internal clock
generation circuit
(divided by 3)
1
Instruction clock
Counter
X
IN
Oscillation
circuit
0
X
OUT
Wait time (Note)
control circuit
Software
start signal
RESET
Key-on wake up control register
POF instruction
R
S
K00,K01,K02,K03
Q
Ports P0
Ports P0
Ports P1
Ports P1
0, P0
2, P0
0, P1
2, P1
1
3
1
3
Multi-
plexer
Falling detected
I1
2
“L” level
0
P3
0
/INT
/INT
0
1
“H” level
I2
2
“L” level
0
P31
1
1
“H” level
Note: The wait time control circuit is used to generate the time required to stabilize the f(XIN) oscillation.
Fig. 41 Clock control circuit structure
Table 23 Clock control register MR
Clock control register MR
System clock selection bit
Not used
at reset : 10002
f(XIN) (high-speed mode)
at RAM back-up : 10002
R/W
0
1
0
1
0
1
0
1
MR3
MR2
MR1
MR0
f(XIN)/2 (middle-speed mode)
This bit has no function, but read/write is enabled.
Not used
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
Not used
Note : “R” represents read enabled, and “W” represents write enabled.
55
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Clock signal f(XIN) is obtained by externally connecting a ceramic
resonator.
4513/4514
Note: Externally connect
a
Connect this external circuit to pins XIN and XOUT at the shortest
distance. A feedback resistor is built in between pins XIN and XOUT.
When an external clock signal is input, connect the clock source to
XIN and leave XOUT open. When using an external clock, the maxi-
mum value of external clock oscillating frequency is shown in Table
24.
damping resistor Rd de-
pending on the oscillation
frequency.
(A feedback resistor is
built-in.)
Use the resonator manu-
facturer’s recommended
value because constants
such as capacitance de-
pend on the resonator.
X
IN
XOUT
Rd
CIN
COUT
Fig. 42 Ceramic resonator external circuit
4513/4514
VDD
VSS
XIN
XOUT
External oscillation circuit
Fig. 43 External clock input circuit
Table 24 Maximum value of external clock oscillation frequency
Supply voltage
Oscillation frequency (duty ratio)
Middle-speed mode
High-speed mode
VDD = 2.0 V to 5.5 V
VDD = 4.0 V to 5.5 V
VDD = 2.5 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 2.5 V to 5.5 V
VDD = 4.0 V to 5.5 V
VDD = 2.5 V to 5.5 V
3.0 MHz (40 % to 60 %)
3.0 MHz (40 % to 60 %)
1.0 MHz (40 % to 60 %)
0.8 MHz (40 % to 60 %)
3.0 MHz (40 % to 60 %)
3.0 MHz (40 % to 60 %)
1.0 MHz (40 % to 60 %)
Mask ROM version
Middle-speed mode
High-speed mode
One Time PROM version
ROM ORDERING METHOD
1.Mask ROM Order Confirmation Form
✕
✕
2.Mark Specification Form
3.Data to be written to ROM, in EPROM form (three identical cop-
ies) or one floppy disk.
✕For the mask ROM confirmation and the mark specifications, re-
fer to the “Mitsubishi MCU Technical Information” Homepage
(http://www.infomicom.maec.co.jp/indexe.htm).
56
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
LIST OF PRECAUTIONS
✕P31/INT1 pin
When the interrupt valid waveform of P31/INT1 pin is changed
with the bit 2 of register I2 in software, be careful about the fol-
lowing notes.
✕Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• Clear the bit 1 of register V1 to “0” before the interrupt valid wave-
form of P31/INT1 pin is changed with the bit 2 of register I2 (refer
to Figure 45✕).
• connect a bypass capacitor (approx. 0.1 µF) between pins VDD
and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use relatively thick wire.
• Depending on the input state of the P31/INT1 pin, the external 1
interrupt request flag (EXF1) may be set when the interrupt valid
waveform is changed. Accordingly, clear bit 2 of register I2 and
execute the SNZ1 instruction to clear the EXF1 flag after execut-
ing at least one instruction (refer to Figure 45✕).
In the One Time PROM version, CNVSS pin is also used as VPP
pin. Accordingly, when using this pin, connect this pin to VSS
through a resistor about 5 kΩ in series at the shortest distance.
✕Prescaler
Stop the prescaler operation to change its frequency dividing ra-
tio.
.
.
.
LA
8
; (✕✕0✕2)
TV1A
; The SNZ1 instruction is valid ...........✕
✕Timer count source
LA
8
Stop timer 1, 2, 3, or 4 counting to change its count source.
TI2A
NOP
SNZ1
NOP
; Change of the interrupt valid waveform
........................................................... ✕
; The SNZ1 instruction is executed
✕Reading the count value
Stop timer 1, 2, 3, or 4 counting and then execute the TAB1,
TAB2, TAB3, or TAB4 instruction to read its data.
.
.
.
✕ : this bit is not related to the setting of INT1.
✕Writing to reload registers R1 and R3
When writing data to reload registers R1 or R3 while timer 1 or
timer 3 is operating, avoid a timing when timer 1 or timer 3
underflows.
Fig. 45 External 1 interrupt program example
✕One Time PROM version
The operating power voltage of the One Time PROM version is
2.5 V to 5.5 V.
✕P30/INT0 pin
When the interrupt valid waveform of the P30/INT0 pin is
changed with the bit 2 of register I1 in software, be careful about
the following notes.
✕Multifunction
The input of D6, D7, P20–P22, I/O of P30 and P31, input of CMP0-,
CMP0+, CMP1-, CMP1+, and I/O of P40–P43 can be used even
when CNTR0, CNTR1, SCK, SOUT, SIN, INT0, INT1, AIN0–AIN3
and AIN4–AIN7 are selected.
• Clear the bit 0 of register V1 to “0” before the interrupt valid wave-
form of P30/INT0 pin is changed with the bit 2 of register I1 (refer
to Figure 44✕).
• Depending on the input state of the P30/INT0 pin, the external 0
interrupt request flag (EXF0) may be set when the interrupt valid
waveform is changed. Accordingly, clear bit 2 of register I1, and
execute the SNZ0 instruction to clear the EXF0 flag after execut-
ing at least one instruction (refer to Figure 44✕)
.
.
.
LA
4
4
; (✕✕✕02)
TV1A
LA
; The SNZ0 instruction is valid ...........✕
;
TI1A
NOP
SNZ0
NOP
; Interrupt valid waveform is changed
........................................................... ✕
; The SNZ0 instruction is executed
.
.
.
✕ : this bit is not related to the setting of INT0 pin.
Fig. 44 External 0 interrupt program example
57
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
✕ A-D converter-1
When the operating mode of the A-D converter is changed from
the comparator mode to the A-D conversion mode with the bit 3
of register Q2 in a program, be careful about the following notes.
• Clear the bit 2 of register V2 to “0” to change the operating mode
of the A-D converter from the comparator mode to the A-D con-
version mode with the bit 3 of register Q2 (refer to Figure 46✕).
• The A-D conversion completion flag (ADF) may be set when the
operating mode of the A-D converter is changed from the com-
parator mode to the A-D conversion mode. Accordingly, set a
value to register Q2, and execute the SNZAD instruction to clear
the ADF flag.
Sensor
AIN
Apply the voltage withiin the specifications
to an analog input pin.
Fig. 47 Analog input external circuit example-1
Do not change the operating mode (both A-D conversion mode
and comparator mode) of A-D converter with the bit 3 of register
Q2 during operating the A-D converter.
.
.
.
About 1kΩ
LA
8
0
; (✕0✕✕2)
Sensor
AIN
TV2A
LA
; The SNZAD instruction is valid........✕
; (0✕✕✕2)
TQ2A
; Change of the operating mode of the A-D
converter from the comparator mode to the
A-D conversion mode
SNZAD
NOP
Fig. 48 Analog input external circuit example-2
.
.
.
12
POF instruction
✕: this bit is not related to the change of the
Execute the POF instruction immediately after executing the
EPOF instruction to enter the RAM back-up.
operating mode of the A-D conversion.
Note that system cannot enter the RAM back-up state when ex-
ecuting only the POF instruction.
Fig. 46 A-D converter operating mode program example
11
Be sure to disable interrupts by executing the DI instruction be-
fore executing the EPOF instruction.
A-D converter-2
Each analog input pin is equipped with a capacitor which is used
to compare the analog voltage. Accordingly, when the analog
voltage is input from the circuit with high-impedance and, charge/
discharge noise is generated and the sufficient A-D accuracy
may not be obtained. Therefore, reduce the impedance or, con-
nect a capacitor (0.01 µF to 1 µF) to analog input pins (Figure
47).
13
Analog input pins
Note the following when using the analog input pins also for I/O
port P4 functions:
• Even when P40/AIN4–P43/AIN7 are set to pins for analog input,
they continue to function as P40–P43 I/O. Accordingly, when any
of them are used as I/O port P4 and others are used as analog
input pins, make sure to set the outputs of pins that are set for
analog input to “1.” Also, the port input function of the pin func-
tions as an analog input is undefined.
When the overvoltage applied to the A-D conversion circuit may
occur, connect an external circuit in order to keep the voltage
within the rated range as shown the Figure 48. In addition, test
the application products sufficiently.
• TALA instruction
When the TALA instruction is executed, the low-order 2 bits of
register AD is transferred to the high-order 2 bits of register A, si-
multaneously, the low-order 2 bits of register A is “0.”
14
Program counter
Make sure that the PCH does not specify after the last page of
the built-in ROM.
15
Port P3
In the 4513 Group, when the IAP3 instruction is executed, note
that the high-order 2 bits of register A is undefined.
58
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
16
Voltage comparator function
When the voltage comparator function is valid with the voltage
comparator control register Q3, it is operating even in the RAM
back-up mode. Accordingly, be careful about such state because
it causes the increase of the operation current in the RAM back-
up mode.
In order to reduce the operation current in the RAM back-up
mode, invalidate (bits 2 and 3 of register Q3 = “0”) the voltage
comparator function by software before the POF instruction is ex-
ecuted.
Also, while the voltage comparator function is valid, current is al-
ways consumed by voltage comparator. On the system required
for the low-power dissipation, invalidate the voltage comparator
when it is unused by software.
17
Register Q3
Bits 0 and 1 of register Q3 can be only read. Note that they can-
not be written.
18
Reading the comparison result of voltage comparator
Read the voltage comparator comparison result from register Q3
after the voltage comparator response time (max. 20 µs) is
passed from the voltage comparator function become valid.
59
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
SYMBOL
The symbols shown below are used in the following instruction function table and instruction list.
Contents
Symbol
Symbol
T1F
Contents
Timer 1 interrupt request flag
Timer 2 interrupt request flag
Timer 3 interrupt request flag
Timer 4 interrupt request flag
Watchdog timer flag
Register A (4 bits)
Register B (4 bits)
Register D (3 bits)
Register E (8 bits)
A
B
T2F
DR
E
T3F
T4F
A-D control register Q1 (4 bits)
A-D control register Q2 (4 bits)
Voltage comparator control register Q3 (4 bits)
Successive comparison register AD (10 bits)
Serial I/O mode register J1 (4 bits)
Serial I/O register SI (8 bits)
Interrupt control register V1 (4 bits)
Interrupt control register V2 (4 bits)
Interrupt control register I1 (4 bits)
Interrupt control register I2 (4 bits)
Timer control register W1 (4 bits)
Timer control register W2 (4 bits)
Timer control register W3 (4 bits)
Timer control register W4 (4 bits)
Timer control register W6 (4 bits)
Clock control register MR (4 bits)
Key-on wakeup control register K0 (4 bits)
Pull-up control register PU0 (4 bits)
Direction register FR0 (4 bits)
Register X (4 bits)
Q1
Q2
Q3
AD
J1
WDF1
WEF
INTE
EXF0
EXF1
P
Watchdog timer enable flag
Interrupt enable flag
External 0 interrupt request flag
External 1 interrupt request flag
Power down flag
SI
V1
V2
I1
ADF
SIOF
A-D conversion completion flag
Serial I/O transmission/reception completion flag
I2
D
Port D (8 bits)
Port P0 (4 bits)
Port P1 (4 bits)
Port P2 (3 bits)
Port P3 (4 bits)
Port P4 (4 bits)
Port P5 (4 bits)
W1
W2
W3
W4
W6
MR
K0
PU0
FR0
X
P0
P1
P2
P3
P4
P5
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Hexadecimal constant
Hexadecimal constant
Hexadecimal constant
Binary notation of hexadecimal variable A
(same for others)
x
y
z
Register Y (4 bits)
Y
p
Z
Register Z (2 bits)
n
Data pointer (10 bits)
DP
i
(It consists of registers X, Y, and Z)
Program counter (14 bits)
High-order 7 bits of program counter
Low-order 7 bits of program counter
Stack register (14 bits ✕ 8)
Stack pointer (3 bits)
j
PC
PCH
PCL
SK
SP
CY
R1
R2
R3
R4
T1
A3A2A1A0
Direction of data movement
←
↔
Data exchange between a register and memory
Decision of state shown before “?”
Carry flag
?
Timer 1 reload register
( )
—
Contents of registers and memories
Timer 2 reload register
Negate, Flag unchanged after executing instruction
RAM address pointed by the data pointer
Label indicating address a6 a5 a4 a3 a2 a1 a0
Label indicating address a6 a5 a4 a3 a2 a1 a0
in page p5 p4 p3 p2 p1 p0
Timer 3 reload register
M(DP)
a
Timer 4 reload register
Timer 1
p, a
T2
Timer 2
Timer 3
Hex. C + Hex. number x (also same for others)
T3
C
+
x
Timer 4
T4
Note :The 4513/4514 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accord-
ingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction
is skipped.
60
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
LIST OF INSTRUCTION FUNCTION
Group-
ing
Group-
ing
Group-
ing
Mnemonic
Function
Mnemonic
XAMI j
Function
Mnemonic
SB j
Function
(Mj(DP)) ← 1
TAB
(A) ← (B)
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
j = 0 to 3
TBA
TAY
(B) ← (A)
(A) ← (Y)
(Y) ← (A)
(Y) ← (Y) + 1
RB j
(Mj(DP)) ← 0
j = 0 to 3
TMA j
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
SZB j
(Mj(DP)) = 0 ?
j = 0 to 3
TYA
TEAB
(E7–E4) ← (B)
(E3–E0) ← (A)
LA n
(A) ← n
SEAM
SEA n
(A) = (M(DP)) ?
n = 0 to 15
(B) ← (E7–E4)
(A) ← (E3–E0)
(A) = n ?
TABE
TABP p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
n = 0 to 15
TDA
TAD
(DR2–DR0) ← (A2–A0)
B a
(PCL) ← a6–a0
(PCL) ← (DR2–DR0,
A3–A0)
(A2–A0) ← (DR2–DR0)
(A3) ← 0
BL p, a
(PCH) ← p
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
(PCL) ← a6–a0
TAZ
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
BLA p
BM a
(PCH) ← p
(PCL) ← (DR2–DR0,
A3–A0)
TAX
(A) ← (X)
AM
(A) ← (A) + (M(DP))
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
TASP
(A2–A0) ← (SP2–SP0)
(A3) ← 0
AMC
(A) ← (A) + (M(DP)) +
(CY)
(CY) ← Carry
(PCL) ← a6–a0
(X) ← x, x = 0 to 15
(Y) ← y, y = 0 to 15
LXY x, y
A n
(A) ← (A) + n
BML p, a (SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
n = 0 to 15
(Z) ← z, z = 0 to 3
(Y) ← (Y) + 1
LZ z
INY
AND
OR
(A) ← (A) AND (M(DP))
(A) ← (A) OR (M(DP))
(CY) ← 1
(PCL) ← a6–a0
BMLA p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
DEY
TAM j
(Y) ← (Y) – 1
SC
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(PCL) ← (DR2–DR0,
A3–A0)
RC
(CY) ← 0
SZC
CMA
RAR
(CY) = 0 ?
RTI
RT
(PC) ← (SK(SP))
(SP) ← (SP) – 1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAM j
(A) ← (A)
(PC) ← (SK(SP))
(SP) ← (SP) – 1
→ CY → A3A2A1A0
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAMD j
RTS
(PC) ← (SK(SP))
(SP) ← (SP) – 1
(Y) ← (Y) – 1
61
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
LIST OF INSTRUCTION FUNCTION (continued)
Group-
ing
Group-
ing
Group-
ing
Mnemonic
Function
Mnemonic
Function
(A) ← (W4)
Mnemonic
SNZT1
Function
(T1F) = 1 ?
DI
(INTE) ← 0
TAW4
After skipping
EI
(INTE) ← 1
TW4A
TAW6
TW6A
TAB1
(W4) ← (A)
(A) ← (W6)
(W6) ← (A)
(T1F) ← 0
SNZ0
(EXF0) = 1 ?
After skipping
(EXF0) ← 0
SNZT2
SNZT3
SNZT4
(T2F) = 1 ?
After skipping
(T2F) ← 0
SNZ1
(EXF1) = 1 ?
After skipping
(EXF1) ← 0
(B) ← (T17–T14)
(A) ← (T13–T10)
(T3F) = 1 ?
After skipping
(T3F) ← 0
T1AB
(R17–R14) ← (B)
(T17–T14) ← (B)
(R13–R10) ← (A)
(T13–T10) ← (A)
SNZI0
SNZI1
I12 = 1 : (INT0) = “H” ?
I12 = 0 : (INT0) = “L” ?
(T4F) = 1 ?
After skipping
(T4F) ← 0
I22 = 1 : (INT1) = “H” ?
I22 = 0 : (INT1) = “L” ?
TAB2
T2AB
(B) ← (T27–T24)
(A) ← (T23–T20)
IAP0
OP0A
IAP1
OP1A
IAP2
(A) ← (P0)
(P0) ← (A)
(A) ← (P1)
(P1) ← (A)
TAV1
TV1A
TAV2
TV2A
TAI1
(A) ← (V1)
(V1) ← (A)
(A) ← (V2)
(V2) ← (A)
(A) ← (I1)
(I1) ← (A)
(A) ← (I2)
(I2) ← (A)
(A) ← (W1)
(W1) ← (A)
(A) ← (W2)
(W2) ← (A)
(A) ← (W3)
(W3) ← (A)
(R27–R24) ← (B)
(T27–T24) ← (B)
(R23–R20) ← (A)
(T23–T20) ← (A)
TAB3
T3AB
(B) ← (T37–T34)
(A) ← (T33–T30)
(A2–A0) ← (P22–P20)
(A3) ← 0
(R37–R34) ← (B)
(T37–T34) ← (B)
(R33–R30) ← (A)
(T33–T30) ← (A)
IAP3
(A) ← (P3)
(P3) ← (A)
(A) ← (P4)
(P4) ← (A)
(A) ← (P5)
(P5) ← (A)
(D) ← 1
TI1A
OP3A
IAP4*
OP4A*
IAP5*
OP5A*
CLD
TAI2
TI2A
TAB4
T4AB
(B) ← (T47–T44)
(A) ← (T43–T40)
TAW1
TW1A
TAW2
TW2A
TAW3
TW3A
(R47–R44) ← (B)
(T47–T44) ← (B)
(R43–R40) ← (A)
(T43–T40) ← (A)
TR1AB
TR3AB
(R17–R14) ← (B)
(R13–R10) ← (A)
RD
(D(Y)) ← 0
(Y) = 0 to 7
(R37–R34) ← (B)
(R33–R30) ← (A)
SD
(D(Y)) ← 1
(Y) = 0 to 7
SZD
(D(Y)) = 0 ?
(Y) = 0 to 7
*: The 4513 Group does not have these instructions.
62
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
LIST OF INSTRUCTION FUNCTION (continued)
Group-
ing
Group-
ing
Mnemonic
Function
Mnemonic
Function
TK0A
(K0) ← (A)
TABAD
(A) ← (AD5–AD2)
(B) ← (AD9–AD6)
However, in the com-
parator mode,
TAK0
(A) ← (K0)
(A) ← (AD3–AD0)
(B) ← (AD7–AD4)
TPU0A
TAPU0
TFR0A*
TABSI
(PU0) ← (A)
(A) ← (PU0)
(FR0) ← (A)
(A) ← (AD1, AD0, 0, 0)
TALA
(AD3–AD0) ← (A)
(AD7–AD4) ← (B)
TADAB
(A) ← (SI3–SI0)
(B) ← (SI7–SI4)
TAQ1
TQ1A
ADST
(A) ← (Q1)
(Q1) ← (A)
TSIAB
(SI3–SI0) ← (A)
(SI7–SI4) ← (B)
(ADF) ← 0
TAJ1
TJ1A
SST
(A) ← (J1)
(J1) ← (A)
A-D conversion starting
(ADF) = 1 ?
After skipping
(ADF) ← 0
SNZAD
(SIOF) ← 0
Serial I/O starting
(A) ← (Q2)
TAQ2
TQ2A
NOP
SNZSI
(SIOF) = 1 ?
After skipping
(SIOF) ← 0
(Q2) ← (A)
(PC) ← (PC) + 1
RAM back-up
POF instruction valid
(P) = 1 ?
POF
EPOF
SNZP
WRST
TAMR
TMRA
TAQ3
TQ3A
(WDF1) ← 0, (WEF) ← 1
(A) ← (MR)
(MR) ← (A)
(A) ← (Q3)
(Q33, Q32) ← (A3, A2)
(Q31) ← (CMP1 com-
parison result)
(Q30) ← (CMP0 com-
parison result)
*: The 4513 Group does not have these instructions.
63
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
INSTRUCTION CODE TABLE (for 4513 Group)
010000 011000
001100
0C
D9–D4 000000000001000010000011000100000101000110 000111001000001001001010001011
001101001110 001111
010111 011111
0F 10–17 18–1F
Hex.
00
NOP BLA
01
02
03
04
–
05
06
07
08
09
0A
0B
0D
0E
D3–D0
0000
notation
SZB
0
A
0
LA TABP TABP TABP
0
TABP
48*
0
BMLA
TASP
TAD
TAX
TAZ
BML BML*** BL BL*** BM
BML BML*** BL BL*** BM
BML BML*** BL BL*** BM
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
32**
16***
0
SZB
1
TABP
33**
A
1
LA TABP TABP
17***
TABP
49*
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
–
CLD
–
–
–
1
1
SZB
2
TABP
A
2
LA TABP TABP
2
TABP
18*** 34**
50*
POF
–
–
2
SZB
3
TABP
35**
A
3
LA TABP TABP
19***
TABP
51*
BML
BML*** BL BL*** BM
SNZP INY
–
–
–
3
3
TABP
A
4
LA TABP TABP
4
TABP
52*
SZD
SEAn
SEAM
–
DI
EI
RD
SD
–
RT TAV1
RTS TAV2
BML BML*** BL BL*** BM
BML BML*** BL BL*** BM
BML BML*** BL BL*** BM
BML BML*** BL BL*** BM
4
20*** 36**
A
5
LA TABP TABP TABP
5
TABP
53*
–
37**
21***
5
TABP
38**
A
6
LA TABP TABP
22***
TABP
54*
RC
–
RTI
–
–
6
6
A
7
LA TABP TABP TABP
7
TABP
55*
SC DEY
–
–
39**
23***
7
LZ
0
TABP
40**
A
8
LA TABP TABP
24***
TABP
56*
–
BML
BML*** BL BL*** BM
–
–
AND
OR
SNZ0
SNZ1
SNZI0
SNZI1
–
–
8
8
LZ
1
TABP
A
9
LA TABP TABP
9
TABP
57*
TDA
TABE
–
–
–
BML BML*** BL BL*** BM
BML BML*** BL BL*** BM
BML BML*** BL BL*** BM
BML BML*** BL BL*** BM
9
25*** 41**
LZ
2
A
10
LA TABP TABP TABP
TABP
58*
AM TEAB
AMC
TYA CMA
RAR
TBA TAB
TAY
42**
10 26***
10
LA TABP TABP
11
LA TABP TABP TABP
12
LA TABP TABP
13 13 29***
LZ
3
TABP
A
11
TABP
11 27*** 43**
59*
–
EPOF
RB
0
SB
0
A
12
TABP
60*
–
44**
12 28***
RB
1
SB
1
TABP
45**
A
13
TABP
61*
–
BML
BML*** BL BL*** BM
–
–
RB
2
SB
2
A
14
LA TABP TABP TABP
14
TABP
14 30*** 46**
62*
–
TV2A
TV1A
BML BML*** BL BL*** BM
BML BML*** BL BL*** BM
RB
3
SB
3
TABP
47**
15 31***
A
15
LA TABP TABP
15
TABP
63*
SZC
–
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order
4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal representa-
tion of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is
shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
The second word
10 paaa aaaa
10 paaa aaaa
10 pp00 pppp
10 pp00 pppp
00 0111 nnnn
00 0010 1011
• *, **, and *** cannot be used in the M34513M2-XXXSP/FP.
• * and ** cannot be used in the M34513M4-XXXSP/FP.
• * and ** cannot be used in the M34513E4FP.
BL
BML
BLA
BMLA
SEA
SZD
• * cannot be used in the M34513M6-XXXFP.
64
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
INSTRUCTION CODE TABLE (continued) (for 4513 Group)
110000
101100
2C
D9–D4 100000100001100010100011100100 100101100110 100111101000101001101010101011
101101101110 101111
111111
Hex.
20
–
21
22
23
24
–
25
TAW6 IAP0 TAB1 SNZT1
IAP1 TAB2 SNZT2
26
27
28
29
2A
2B
2D
2E
2F 30–3F
D3–D0
0000
notation
TMA
0
TAM XAM XAMI XAMD
0
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
0
TW3A OP0A T1AB
TW4A OP1A T2AB
–
WRST
0
0
0
TMA TAM XAM XAMI XAMD
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
–
–
–
–
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
1
1
1
1
TMA
2
TAM XAM XAMI XAMD
2
TJ1A
–
–
–
T3AB TAJ1 TAMR IAP2 TAB3 SNZT3
TW6A OP3A T4AB TAI1 IAP3 TAB4 SNZT4
–
2
2
2
TMA
3
TAM XAM XAMI XAMD
3
–
–
3
3
3
TMA
4
TAM XAM XAMI XAMD
4
TQ1A
TQ2A
–
–
–
–
TAQ1 TAI2
TAQ2
TAQ3 TAK0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
4
4
4
TMA
5
TAM XAM XAMI XAMD
5
–
–
–
–
–
–
5
5
5
TMA
6
TAM XAM XAMI XAMD
6
TQ3A TMRA
–
–
–
–
6
6
6
TMA
7
TAM XAM XAMI XAMD
7
–
TI1A
–
–
–
TAPU0
SNZAD
–
7
7
7
TMA TAM XAM XAMI XAMD
–
TI2A
–
TSIAB
–
–
–
–
–
–
–
–
TABSI SNZSI
–
8
8
8
8
8
TMA
9
TAM XAM XAMI XAMD
9
–
–
–
TADAB TALA
TABAD
–
–
–
–
–
–
–
–
9
9
9
TMA
10
TAM XAM XAMI XAMD
10 10 10 10
TAM XAM XAMI XAMD
11 11 11 11
TAM XAM XAMI XAMD
12 12 12 12
TAM XAM XAMI XAMD
13 13 13 13
TAM XAM XAMI XAMD
14 14 14 14
–
–
–
–
–
–
–
–
–
–
–
–
–
TMA
11
–
–
TK0A
–
TR3AB TAW1
TMA
12
–
–
–
–
–
–
TAW2
TAW3
TAW4
–
–
TMA
13
–
TPU0A
–
–
–
TMA
14
TW1A
TW2A
–
–
SST
ADST
TMA TAM XAM XAMI XAMD
15
TR1AB
15
15
15
15
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-
order 4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal
representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of
each instruction is shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
The second word
BL
10 paaa aaaa
10 paaa aaaa
10 pp00 pppp
10 pp00 pppp
00 0111 nnnn
00 0010 1011
BML
BLA
BMLA
SEA
SZD
65
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
INSTRUCTION CODE TABLE (for 4514 Group)
010000 011000
001100
0C
D9–D4 000000000001000010000011000100000101000110 000111001000001001001010001011
Hex.
001101001110 001111
010111 011111
00
01
02
03
04
05
TASP
TAD
TAX
TAZ
06
07
08
09
0A
0B
0D
0E
0F 10–17 18–1F
D3–D0
notation
A
0
LA TABP TABP TABP TABP
SZB
0
0000
0
NOP BLA
BMLA
–
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
0
0
16
LA TABP TABP TABP TABP
17 33 49*
LA TABP TABP TABP TABP
18 34 50*
LA TABP TABP TABP TABP
19 35 51*
LA TABP TABP TABP TABP
20 36 52*
LA TABP TABP TABP TABP
21 37 53*
LA TABP TABP TABP TABP
22 38 54*
LA TABP TABP TABP TABP
23 39 55*
LA TABP TABP TABP TABP
24 40 56*
LA TABP TABP TABP TABP
25 41 57*
LA TABP TABP TABP TABP
10 10 26 42 58*
LA TABP TABP TABP TABP
11 11 27 43 59*
LA TABP TABP TABP TABP
12 12 28 44 60*
LA TABP TABP TABP TABP
13 13 29 45 61*
LA TABP TABP TABP TABP
14 14 30 46 62*
LA TABP TABP TABP TABP
15 15 31 47 63*
32
48*
A
1
SZB
1
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
–
CLD
–
–
–
1
1
A
2
SZB
2
POF
–
–
2
2
A
3
SZB
3
SNZP INY
–
–
–
3
3
A
4
SZD
SEAn
SEAM
–
DI
EI
RD
SD
–
RT TAV1
RTS TAV2
4
4
A
5
–
5
5
A
6
RC
–
RTI
–
–
6
6
A
7
SC DEY
–
–
7
7
LZ
0
A
8
–
–
–
AND
OR
SNZ0
SNZ1
SNZI0
SNZI1
–
–
8
8
LZ
1
A
9
TDA
TABE
–
–
–
9
9
LZ
2
A
10
AM TEAB
AMC
TYA CMA
RAR
TBA TAB
TAY
LZ
3
A
11
–
EPOF
RB
0
SB
0
A
12
–
RB
1
A
13
SB
1
–
–
–
RB
2
A
14
SB
2
–
TV2A
TV1A
RB
3
A
15
SB
3
SZC
–
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order
4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal representa-
tion of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is
shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
The second word
• * cannot be used in the M34514M6-XXXFP.
BL
10 paaa aaaa
10 paaa aaaa
10 pp00 pppp
10 pp00 pppp
00 0111 nnnn
00 0010 1011
BML
BLA
BMLA
SEA
SZD
66
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
INSTRUCTION CODE TABLE (continued) (for 4514 Group)
110000
101100
2C
D9–D4 100000100001100010100011100100100101100110 100111101000101001101010101011
Hex.
101101101110 101111
111111
20
21
22
23
24
25
TAW6 IAP0 TAB1 SNZT1
IAP1 TAB2 SNZT2
26
27
28
29
2A
2B
2D
2E
2F 30–3F
D3–D0
notation
TMA
0
TAM XAM XAMI XAMD
0
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
0
–
TW3A OP0A T1AB
TW4A OP1A T2AB
–
–
WRST
0000
0
0
0
TMA
1
TAM XAM XAMI XAMD
1
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
1
1
TMA TAM XAM XAMI XAMD
TJ1A
–
–
–
T3AB TAJ1 TAMR IAP2 TAB3 SNZT3
–
2
2
2
2
2
TMA
3
TAM XAM XAMI XAMD
3
TW6A OP3A T4AB TAI1 IAP3 TAB4 SNZT4
–
–
3
3
3
TMA
4
TAM XAM XAMI XAMD
4
TQ1A
TQ2A
–
–
OP4A
–
–
–
–
TAQ1 TAI2 IAP4
–
–
–
–
–
–
4
4
4
TMA
5
TAM XAM XAMI XAMD
5
OP5A
TAQ2
–
IAP5
–
–
–
5
5
5
TMA
6
TAM XAM XAMI XAMD
6
TQ3A TMRA
–
–
TAQ3 TAK0
–
–
–
–
–
–
–
–
–
–
–
6
6
6
TMA TAM XAM XAMI XAMD
–
TI1A
–
–
TAPU0
SNZAD
–
7
7
7
7
7
TMA
8
TAM XAM XAMI XAMD
8
–
TI2A TFR0ATSIAB
–
–
–
–
–
–
–
–
TABSI SNZSI
–
8
8
8
TMA
9
TAM XAM XAMI XAMD
9
–
–
–
TADAB TALA
TABAD
–
–
–
–
–
–
–
–
9
9
9
TMA
10
TAM XAM XAMI XAMD
10 10 10 10
TAM XAM XAMI XAMD
11 11 11 11
TAM XAM XAMI XAMD
12 12 12 12
TAM XAM XAMI XAMD
13 13 13 13
–
–
–
–
–
–
–
–
–
–
–
–
–
TMA
11
–
–
TK0A
–
TR3AB TAW1
TMA
12
–
–
–
–
–
–
TAW2
TAW3
TAW4
–
–
TMA
13
–
TPU0A
–
–
–
TMA TAM XAM XAMI XAMD
TW1A
TW2A
–
–
SST
ADST
14
14
TAM XAM XAMI XAMD
15 15 15 15
14
14
14
TMA
15
TR1AB
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-
order 4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal
representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of
each instruction is shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
The second word
BL
10 paaa aaaa
10 paaa aaaa
10 pp00 pppp
10 pp00 pppp
00 0111 nnnn
00 0010 1011
BML
BLA
BMLA
SEA
SZD
67
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MACHINE INSTRUCTIONS
Instruction code
Parameter
Function
Mnemonic
Hexadecimal
notation
Type of
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions
TAB
TBA
TAY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
0
0
1
0
0
0
0
0
0
0
1
0
1
0
1
E
E
F
C
A
1
1
1
1
1
1
1
1
1
1
(A) ← (B)
(B) ← (A)
(A) ← (Y)
(Y) ← (A)
TYA
TEAB
(E7–E4) ← (B)
(E3–E0) ← (A)
TABE
0
0
0
0
1
0
1
0
1
0
0
2
A
1
1
(B) ← (E7–E4)
(A) ← (E3–E0)
TDA
TAD
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
1
0
0
2
5
9
1
1
1
1
1
(DR2–DR0) ← (A2–A0)
(A2–A0) ← (DR2–DR0)
(A3) ← 0
TAZ
0
0
0
1
0
1
0
0
1
1
0
5
3
1
1
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
TAX
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
0
0
0
0
5
5
2
0
1
1
1
1
(A) ← (X)
TASP
(A2–A0) ← (SP2–SP0)
(A3) ← 0
LXY x, y
1
1
x3 x2 x1 x0 y3 y2 y1 y0
3
x
y
1
1
(X) ← x, x = 0 to 15
(Y) ← y, y = 0 to 15
LZ z
INY
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
1
z1 z0
0
0
0
4
1
1
8
+z
1
1
1
1
1
1
(Z) ← z, z = 0 to 3
(Y) ← (Y) + 1
1
1
1
1
3
7
DEY
(Y) ← (Y) – 1
TAM j
1
1
1
0
0
0
1
1
1
1
1
1
0
0
1
0
1
1
j
j
j
j
j
j
j
j
j
j
j
j
2
2
2
C j
D j
1
1
1
1
1
1
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAM j
XAMD j
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
F
j
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
XAMI j
TMA j
1
1
0
0
1
1
1
0
1
1
0
1
j
j
j
j
j
j
j
j
2
2
E j
1
1
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
B j
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
68
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Skip condition
Datailed description
–
–
–
–
–
–
–
–
–
–
Transfers the contents of register B to register A.
Transfers the contents of register A to register B.
Transfers the contents of register Y to register A.
Transfers the contents of register A to register Y.
Transfers the contents of registers A and B to register E.
–
–
Transfers the contents of register E to registers A and B.
–
–
–
–
Transfers the contents of register A to register D.
Transfers the contents of register D to register A.
–
–
Transfers the contents of register Z to register A.
Transfers the contents of register X to register A.
–
–
–
–
Transfers the contents of stack pointer (SP) to register A.
Continuous
description
–
Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y.
When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
–
–
–
–
Loads the value z in the immediate field to register Z.
(Y) = 0
(Y) = 15
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next in-
struction is skipped.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped.
–
–
–
–
–
After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between reg-
ister X and the value j in the immediate field, and stores the result in register X.
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per-
formed between register X and the value j in the immediate field, and stores the result in register X.
(Y) = 15
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per-
formed between register X and the value j in the immediate field, and stores the result in register X.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped.
(Y) = 0
–
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per-
formed between register X and the value j in the immediate field, and stores the result in register X. Adds 1
to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction
is skipped.
–
After transferring the contents of register A to M(DP), an exclusive OR operation is performed between reg-
ister X and the value j in the immediate field, and stores the result in register X.
69
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MACHINE INSTRUCTIONS (continued)
Instruction code
Parameter
Function
Mnemonic
Hexadecimal
notation
Type of
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions
LA n
0
0
0
0
0
1
1
0
1
1
n
n
n
n
0
7
n
1
1
1
3
(A) ← n
n = 0 to 15
TABP p
p5 p4 p3 p2 p1 p0
0
8
p
(SP) ← (SP) + 1
+p
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
(SP) ← (SP) – 1 (Note)
AM
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
n
0
0
n
1
1
n
0
1
n
0
0
0
0
0
6
A
B
n
1
1
1
1
1
1
(A) ← (A) + (M(DP))
AMC
A n
(A) ← (A) + (M(DP)) +(CY)
(CY) ← Carry
(A) ← (A) + n
n = 0 to 15
AND
OR
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
0
0
1
1
8
9
1
1
1
1
(A) ← (A) AND (M(DP))
(A) ← (A) OR (M(DP))
SC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
2
1
1
7
1
1
1
1
1
1
1
1
1
1
(CY) ← 1
RC
6
(CY) ← 0
SZC
CMA
RAR
F
C
D
(CY) = 0 ?
(A) ← (A)
→ CY → A3A2A1A0
SB j
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
1
1
0
1
1
0
j
j
j
j
j
j
0
0
0
5
4
2
C
+j
1
1
1
1
1
1
(Mj(DP)) ← 1
j = 0 to 3
RB j
SZB j
C
+j
(Mj(DP)) ← 0
j = 0 to 3
j
(Mj(DP)) = 0 ?
j = 0 to 3
SEAM
SEA n
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
0
0
n
1
1
n
1
0
n
0
1
n
0
0
0
2
2
7
6
5
n
1
2
1
2
(A) = (M(DP)) ?
(A) = n ?
n = 0 to 15
Note :p is 0 to 15 for M34513M2, p is 0 to 31 for M34513M4/E4, p is 0 to 47 for M34513M6 and M34514M6, and p is 0 to 63 for M34513M8/E8 and
M34514M8/E8.
70
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Skip condition
Datailed description
Continuous
description
–
–
Loads the value n in the immediate field to register A.
When the LA instructions are continuously coded and executed, only the first LA instruction is executed and
other LA instructions coded continuously are skipped.
–
Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in ad-
dress (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p.
When this instruction is executed, 1 stage of stack register is used.
–
–
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY re-
mains unchanged.
–
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY.
Overflow = 0
–
Adds the value n in the immediate field to register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no overflow as the result of operation.
–
–
–
–
Takes the AND operation between the contents of register A and the contents of M(DP), and stores the re-
sult in register A.
Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result
in register A.
–
1
0
–
–
Sets (1) to carry flag CY.
–
Clears (0) to carry flag CY.
(CY) = 0
Skips the next instruction when the contents of carry flag CY is “0.”
Stores the one’s complement for register A’s contents in register A.
–
–
0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.
–
–
–
–
–
Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
(Mj(DP)) = 0
j = 0 to 3
Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of
M(DP) is “0.”
(A) = (M(DP))
(A) = n
–
–
Skips the next instruction when the contents of register A is equal to the contents of M(DP).
Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
71
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MACHINE INSTRUCTIONS (continued)
Instruction code
Parameter
Function
Mnemonic
Hexadecimal
notation
Type of
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions
B a
0
0
1
1
0
0
1
1
a6 a5 a4 a3 a2 a1 a0
1
0
2
8
+a
a
1
2
1
2
(PCL) ← a6–a0
BL p, a
1
1
p4 p3 p2 p1 p0
E p
+p
(PCH) ← p
(PCL) ← a6–a0
(Note)
p5 a6 a5 a4 a3 a2 a1 a0
p
a
+a
BLA p
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
2
1
p
0
p
2
1
2
2
1
2
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
(Note)
p5 p4
p3 p2 p1 p0
BM a
0
1
0
1
a6 a5 a4 a3 a2 a1 a0
1
a
a
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
(PCL) ← a6–a0
BML p, a
0
1
0
0
1
0
p4 p3 p2 p1 p0
0
2
C p
+p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← a6–a0
(Note)
p5 a6 a5 a4 a3 a2 a1 a0
p
+a
a
BMLA p
0
1
0
0
0
0
1
0
1
0
0
0
0
0
0
2
3
p
0
p
2
1
2
1
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0,A3–A0)
(Note)
p5 p4
p3 p2 p1 p0
RTI
0
0
0
1
0
0
0
1
1
0
0
4
6
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RT
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
4
4
4
5
1
1
2
2
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RTS
(PC) ← (SK(SP))
(SP) ← (SP) – 1
DI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
3
4
5
8
1
1
1
1
1
1
(INTE) ← 0
(INTE) ← 1
EI
SNZ0
(EXF0) = 1 ?
After skipping
(EXF0) ← 0
SNZ1
0
0
0
0
1
1
1
0
0
1
0
3
9
1
1
(EXF1) = 1 ?
After skipping
(EXF1) ← 0
Note :p is 0 to 15 for M34513M2, p is 0 to 31 for M34513M4/E4, p is 0 to 47 for M34513M6 and M34514M6, and p is 0 to 63 for M34513M8/E8 and
M34514M8/E8.
72
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Skip condition
Datailed description
–
–
–
–
Branch within a page : Branches to address a in the identical page.
Branch out of a page : Branches to address a in page p.
–
–
–
–
–
–
Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in
page p.
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
Call the subroutine : Calls the subroutine at address a in page p.
–
–
–
–
Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D
and A in page p.
Returns from interrupt service routine to main routine.
Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous de-
scription of the LA/LXY instruction, register A and register B to the states just before interrupt.
–
–
–
Returns from subroutine to the routine called the subroutine.
Skip at uncondition
Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
–
–
–
–
Clears (0) to the interrupt enable flag INTE, and disables the interrupt.
Sets (1) to the interrupt enable flag INTE, and enables the interrupt.
–
(EXF0) = 1
Skips the next instruction when the contents of EXF0 flag is “1.”
After skipping, clears (0) to the EXF0 flag.
(EXF1) = 1
–
Skips the next instruction when the contents of EXF1 flag is “1.”
After skipping, clears (0) to the EXF1 flag.
73
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MACHINE INSTRUCTIONS (continued)
Instruction code
Parameter
Function
Mnemonic
Hexadecimal
notation
Type of
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions
SNZI0
SNZI1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
3
A
1
1
1
1
I12 = 1 : (INT0) = “H” ?
I12 = 0 : (INT0) = “L” ?
I22 = 1 : (INT1) = “H” ?
I22 = 0 : (INT1) = “L” ?
0
0
0
0
1
1
0
3
B
TAV1
TV1A
TAV2
TV2A
TAI1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
1
1
1
0
1
0
1
0
0
0
1
1
1
1
1
1
0
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
1
0
1
0
0
0
0
1
0
1
1
1
0
0
1
1
0
1
0
0
1
0
0
1
0
1
1
0
1
1
0
0
1
0
0
1
1
0
0
1
0
1
0
0
0
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
5
3
5
3
5
1
5
1
4
0
4
0
4
1
4
1
5
1
4
F
5
E
3
7
4
8
B
E
C
F
D
0
E
1
0
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(A) ← (V1)
(V1) ← (A)
(A) ← (V2)
(V2) ← (A)
(A) ← (I1)
TI1A
(I1) ← (A)
TAI2
(A) ← (I2)
TI2A
(I2) ← (A)
TAW1
TW1A
TAW2
TW2A
TAW3
TW3A
TAW4
TW4A
TAW6
TW6A
(A) ← (W1)
(W1) ← (A)
(A) ← (W2)
(W2) ← (A)
(A) ← (W3)
(W3) ← (A)
(A) ← (W4)
(W4) ← (A)
(A) ← (W6)
(W6) ← (A)
74
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Skip condition
Datailed description
(INT0) = “H”
However, I12 = 1
–
–
–
–
When bit 2 (I12) of register I1 is “1” : Skips the next instruction when the level of INT0 pin is “H.”
When bit 2 (I12) of register I1 is “0” : Skips the next instruction when the level of INT0 pin is “L.”
When bit 2 (I22) of register I2 is “1” : Skips the next instruction when the level of INT1 pin is “H.”
When bit 2 (I22) of register I2 is “0” : Skips the next instruction when the level of INT1 pin is “L.”
(INT0) = “L”
However, I12 = 0
(INT1) = “H”
However, I22 = 1
(INT1) = “L”
However, I22 = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Transfers the contents of interrupt control register V1 to register A.
Transfers the contents of register A to interrupt control register V1.
Transfers the contents of interrupt control register V2 to register A.
Transfers the contents of register A to interrupt control register V2.
Transfers the contents of interrupt control register I1 to register A.
Transfers the contents of register A to interrupt control register I1.
Transfers the contents of interrupt control register I2 to register A.
Transfers the contents of register A to interrupt control register I2.
Transfers the contents of timer control register W1 to register A.
Transfers the contents of register A to timer control register W1.
Transfers the contents of timer control register W2 to register A.
Transfers the contents of register A to timer control register W2.
Transfers the contents of timer control register W3 to register A.
Transfers the contents of register A to timer control register W3.
Transfers the contents of timer control register W4 to register A.
Transfers the contents of register A to timer control register W4.
Transfers the contents of timer control register W6 to register A.
Transfers the contents of register A to timer control register W6.
75
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MACHINE INSTRUCTIONS (continued)
Instruction code
Parameter
Function
Mnemonic
Hexadecimal
notation
Type of
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions
TAB1
T1AB
1
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
2
2
7
3
0
0
1
1
1
1
(B) ← (T17–T14)
(A) ← (T13–T10)
(R17–R14) ← (B)
(T17–T14) ← (B)
(R13–R10) ← (A)
(T13–T10) ← (A)
TAB2
T2AB
1
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
0
1
1
2
2
7
3
1
1
1
1
1
1
(B) ← (T27–T24)
(A) ← (T23–T20)
(R27–R24) ← (B)
(T27–T24) ← (B)
(R23–R20) ← (A)
(T23–T20) ← (A)
TAB3
T3AB
1
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
1
1
0
0
2
2
7
3
2
2
1
1
1
1
(B) ← (T37–T34)
(A) ← (T33–T30)
(R37–R34) ← (B)
(T37–T34) ← (B)
(R33–R30) ← (A)
(T33–T30) ← (A)
TAB4
T4AB
1
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
1
1
1
1
2
2
7
3
3
3
1
1
1
1
(B) ← (T47–T44)
(A) ← (T43–T40)
(R47–R44) ← (B)
(T47–T44) ← (B)
(R43–R40) ← (A)
(T43–T40) ← (A)
TR1AB
TR3AB
SNZT1
1
1
1
0
0
0
0
0
1
0
0
0
1
1
0
1
1
0
1
1
0
1
0
0
1
1
0
1
1
0
2
2
2
3
3
8
F
B
0
1
1
1
1
1
1
(R17–R14) ← (B)
(R13–R10) ← (A)
(R37–R34) ← (B)
(R33–R30) ← (A)
(T1F) = 1 ?
After skipping
(T1F) ← 0
SNZT2
SNZT3
SNZT4
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
2
2
2
8
8
8
1
2
3
1
1
1
1
1
1
(T2F) = 1 ?
After skipping
(T2F) ← 0
(T3F) = 1 ?
After skipping
(T3F) ← 0
(T4F) = 1 ?
After skipping
(T4F) ← 0
76
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Skip condition
Datailed description
–
–
–
–
Transfers the contents of timer 1 to registers A and B.
Transfers the contents of registers A and B to timer 1 and timer 1 reload register.
–
–
–
–
Transfers the contents of timer 2 to registers A and B.
Transfers the contents of registers A and B to timer 2 and timer 2 reload register.
–
–
–
–
Transfers the contents of timer 3 to registers A and B.
Transfers the contents of registers A and B to timer 3 and timer 3 reload register.
–
–
–
–
Transfers the contents of timer 4 to registers A and B.
Transfers the contents of registers A and B to timer 4 and timer 4 reload register.
–
–
–
–
–
Transfers the contents of registers A and B to timer 1 reload register.
Transfers the contents of registers A and B to timer 3 reload register.
(T1F) = 1
Skips the next instruction when the contents of T1F flag is “1.”
After skipping, clears (0) to T1F flag.
(T2F) =1
(T3F) = 1
(T4F) = 1
–
–
–
Skips the next instruction when the contents of T2F flag is “1.”
After skipping, clears (0) to T2F flag.
Skips the next instruction when the contents of T3F flag is “1.”
After skipping, clears (0) to T3F flag.
Skips the next instruction when the contents of T4F flag is “1.”
After skipping, clears (0) to T4F flag.
77
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MACHINE INSTRUCTIONS (continued)
Instruction code
Parameter
Function
Mnemonic
Hexadecimal
notation
Type of
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions
IAP0
OP0A
IAP1
OP1A
IAP2
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
2
2
2
2
2
6
2
6
2
6
0
0
1
1
2
1
1
1
1
1
1
1
1
1
1
(A) ← (P0)
(P0) ← (A)
(A) ← (P1)
(P1) ← (A)
(A2–A0) ← (P22–P20)
(A3) ← 0
IAP3
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
0
2
2
2
2
2
2
0
0
6
2
6
2
6
2
1
1
3
3
4
4
5
5
1
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(A) ← (P3)
(P3) ← (A)
(A) ← (P4)
(P4) ← (A)
(A) ← (P5)
(P5) ← (A)
(D) ← 1
OP3A
IAP4*
OP4A*
IAP5*
OP5A*
CLD
RD
(D(Y)) ← 0
(Y) = 0 to 7
SD
0
0
0
0
0
1
0
1
0
1
0
1
5
1
2
1
2
(D(Y)) ← 1
(Y) = 0 to 7
SZD
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
1
0
1
0
0
2
2
4
(D(Y)) = 0 ?
(Y) = 0 to 7
B
TK0A
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
1
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
1
0
1
0
1
0
1
1
0
2
2
2
2
2
1
5
2
5
2
B
6
D
7
8
1
1
1
1
1
1
1
1
1
1
(K0) ← (A)
(A) ← (K0)
(PU0) ← (A)
(A) ← (PU0)
(FR0) ← (A)
TAK0
TPU0A
TAPU0
TFR0A*
*: The 4513 Group does not have these instructions.
78
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Skip condition
Datailed description
–
–
–
–
–
–
–
–
–
–
Transfers the input of port P0 to register A.
Outputs the contents of register A to port P0.
Transfers the input of port P1 to register A.
Outputs the contents of register A to port P1.
Transfers the input of port P2 to register A.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Transfers the input of port P3 to register A.
Outputs the contents of register A to port P3.
Transfers the input of port P4 to register A.
Outputs the contents of register A to port P4.
Transfers the input of port P5 to register A.
Outputs the contents of register A to port P5.
Sets (1) to port D.
Clears (0) to a bit of port D specified by register Y.
–
–
–
Sets (1) to a bit of port D specified by register Y.
(D(Y)) = 0
Skips the next instruction when a bit of port D specified by register Y is “0.”
(Y) = 0 to 7
–
–
–
–
–
–
–
–
–
–
Transfers the contents of register A to key-on wakeup control register K0.
Transfers the contents of key-on wakeup control register K0 to register A.
Transfers the contents of register A to pull-up control register PU0.
Transfers the contents of pull-up control register PU0 to register A.
Transfers the contents of register A to direction register FR0.
79
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MACHINE INSTRUCTIONS (continued)
Instruction code
Parameter
Function
Mnemonic
Hexadecimal
notation
Type of
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions
TABSI
TSIAB
1
1
0
0
0
0
1
0
1
1
1
1
1
1
0
0
0
0
0
0
2
2
7
3
8
8
1
1
1
1
(A) ← (SI3–SI0)
(B) ← (SI7–SI4)
(SI3–SI0) ← (A)
(SI7–SI4) ← (B)
TAJ1
TJ1A
SST
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
1
1
1
1
0
0
0
2
2
2
4
0
9
2
2
E
1
1
1
1
1
1
(A) ← (J1)
(J1) ← (A)
(SIOF) ← 0
Serial I/O starting
SNZSI
1
1
0
0
1
0
0
1
0
1
0
1
1
1
0
0
0
0
0
1
2
2
8
7
8
9
1
1
1
1
(SIOF) = 1 ?
After skipping
(SIOF) ← 0
TABAD
(A) ← (AD5–AD2)
(B) ← (AD9–AD6)
However, in the comparator mode,
(A) ← (AD3–AD0)
(B) ← (AD7–AD4)
TALA
1
1
0
0
0
0
1
0
0
1
0
1
1
1
0
0
0
0
1
1
2
2
4
3
9
9
1
1
1
1
(A) ← (AD1, AD0, 0, 0)
TADAB
(AD3–AD0) ← (A)
(AD7–AD4) ← (B)
TAQ1
TQ1A
ADST
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
1
0
0
1
0
0
1
2
2
2
4
0
9
4
4
F
1
1
1
1
1
1
(A) ← (Q1)
(Q1) ← (A)
(ADF) ← 0
A-D conversion starting
SNZAD
1
0
1
0
0
0
0
1
1
1
2
8
7
1
1
(ADF) = 1 ?
After skipping
(ADF) ← 0
TAQ2
TQ2A
NOP
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
2
2
0
0
0
0
2
4
0
0
0
5
0
5
5
0
2
B
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(A) ← (Q2)
(Q2) ← (A)
(PC) ← (PC) + 1
RAM back-up
POF instruction valid
(P) = 1 ?
POF
EPOF
SNZP
WRST
A 0
(WDF1) ← 0
(WEF) ← 1
TAMR
TMRA
TAQ3
TQ3A
1
1
1
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
2
2
2
2
5
1
4
0
2
6
6
6
1
1
1
1
1
1
1
1
(A) ← (MR)
(MR) ← (A)
(A) ← (Q3)
(Q33, Q32) ← (A3, A2)
(Q31) ← (CMP1 comparison result)
(Q30) ← (CMP0 comparison result)
80
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Skip condition
Datailed description
–
–
–
–
Transfers the contents of serial I/O register SI to registers A and B.
Transfers the contents of registers A and B to serial I/O register SI.
–
–
–
–
–
–
Transfers the contents of serial I/O mode register J1 to register A.
Transfers the contents of register A to serial I/O mode register J1.
Clears (0) to SIOF flag and starts serial I/O.
(SIOF) = 1
–
–
Skips the next instruction when the contents of SIOF flag is “1.”
After skipping, clears (0) to SIOF flag.
–
Transfers the high-order 8 bits of the contents of register AD to registers A and B.
–
–
–
–
Transfers the low-order 2 bits of the contents of register AD to the high-order 2 bits of the contents of regis-
ter A. Simultaneously, the low-order 2 bits of the contents of the register A is “0.”
Transfers the contents of registers A and B to the comparator register at the comparator mode.
–
–
–
–
–
–
Transfers the contents of the A-D control register Q1 to register A.
Transfers the contents of register A to the A-D control register Q1.
Clears the ADF flag, and the A-D conversion at the A-D conversion mode or the comparator operation at the
comparator mode is started.
(ADF) = 1
–
Skips the next instruction when the contents of ADF flag is “1”.
After skipping, clears (0) the contents of ADF flag.
–
–
–
–
–
–
–
–
Transfers the contents of the A-D control register Q2 to register A.
Transfers the contents of register A to the A-D control register Q2.
No operation
–
–
–
Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction.
Makes the immediate POF instruction valid by executing the EPOF instruction.
Skips the next instruction when P flag is “1”. After skipping, P flag remains unchanged.
Operates the watchdog timer and initializes the watchdog timer flag WDF1.
–
(P) = 1
–
–
–
–
–
–
–
–
–
Transfers the contents of the clock control register MR to register A.
Transfers the contents of register A to the clock control register MR.
Transfers the contents of the voltage comparator control register Q3 to register A.
Transfers the contents of the high-order 2 bits of register A to the high-order 2 bits of voltage comparator
control register Q3, and the comparison result of the voltage comparator is transferred to the low-order 2 bits
of the register Q3.
81
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
CONTROL REGISTERS
Interrupt control register V1
at reset : 00002
at RAM back-up : 00002
R/W
0
1
0
1
0
1
0
1
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
Interrupt disabled (SNZ1 instruction is valid)
Interrupt enabled (SNZ1 instruction is invalid)
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
V13
V12
V11
V10
Timer 2 interrupt enable bit
Timer 1 interrupt enable bit
External 1 interrupt enable bit
External 0 interrupt enable bit
Interrupt control register V2
Serial I/O interrupt enable bit
A-D interrupt enable bit
at RAM back-up : 00002
at reset : 00002
R/W
0
1
0
1
0
1
0
1
Interrupt disabled (SNZSI instruction is valid)
Interrupt enabled (SNZSI instruction is invalid)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid)
Interrupt disabled (SNZT4 instruction is valid)
Interrupt enabled (SNZT4 instruction is invalid)
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
V23
V22
V21
V20
Timer 4 interrupt enable bit
Timer 3 interrupt enable bit
Interrupt control register I1
Not used
at reset : 00002
at RAM back-up : state retained
R/W
0
1
I13
I12
This bit has no function, but read/write is enabled.
Falling waveform (“L” level of INT0 pin is recognized with the SNZI0
0
1
Interrupt valid waveform for INT0 pin/
return level selection bit (Note 2)
instruction)/“L” level
Rising waveform (“H” level of INT0 pin is recognized with the SNZI0
instruction)/“H” level
One-sided edge detected
Both edges detected
Disabled
0
1
0
1
I11
I10
INT0 pin edge detection circuit control bit
INT0 pin
timer 1 control enable bit
Enabled
Interrupt control register I2
Not used
at reset : 00002
at RAM back-up : state retained
R/W
0
1
I23
I22
This bit has no function, but read/write is enabled.
Falling waveform (“L” level of INT1 pin is recognized with the SNZI1
0
1
instruction)/“L” level
Interrupt valid waveform for INT1 pin/
return level selection bit (Note 3)
Rising waveform (“H” level of INT1 pin is recognized with the SNZI1
instruction)/“H” level
One-sided edge detected
Both edges detected
Disabled
0
1
0
1
I21
I20
INT1 pin edge detection circuit control bit
INT1 pin
Enabled
timer 3 control enable bit
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction.
3: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.
82
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Timer control register W1
Prescaler control bit
at reset : 00002
at RAM back-up : 00002
R/W
Stop (state initialized)
Operating
0
1
0
1
0
1
0
1
W13
W12
W11
W10
Instruction clock divided by 4
Instruction clock divided by 16
Stop (state retained)
Prescaler dividing ratio selection bit
Timer 1 control bit
Operating
Count start synchronous circuit not selected
Count start synchronous circuit selected
Timer 1 count start synchronous circuit
control bit
Timer control register W2
Timer 2 control bit
at reset : 00002
at RAM back-up : state retained
R/W
0
Stop (state retained)
Operating
W23
W22
1
0
1
Not used
This bit has no function, but read/write is enabled.
W21
Count source
Timer 1 underflow signal
Prescaler output
W20
W21
W20
0
0
1
1
0
1
0
1
Timer 2 count source selection bits
CNTR0 input
16 bit timer (WDT) underflow signal
Timer control register W3
Timer 3 control bit
at RAM back-up : state retained
Stop (state retained)
Operating
R/W
R/W
R/W
at reset : 00002
0
1
0
1
W33
W32
Count start synchronous circuit not selected
Count start synchronous circuit selected
Count source
Timer 3 count start synchronous circuit
control bit
W31
W30
W31
W30
0
0
1
1
Timer 2 underflow signal
Prescaler output
0
1
0
1
Timer 3 count source selection bits
Not available
Not available
Timer control register W4
Timer 4 control bit
at reset : 00002
at RAM back-up : state retained
0
Stop (state retained)
Operating
W43
W42
1
0
1
Not used
This bit has no function, but read/write is enabled.
W41
Count source
Timer 3 underflow signal
Prescaler output
W40
W41
W40
0
0
1
1
0
1
0
1
Timer 4 count source selection bits
CNTR1 input
Not available
Timer control register W6
CNTR1 output control bit
at reset : 00002
at RAM back-up : state retained
0
Timer 3 underflow signal output divided by 2
W63
W62
W61
W60
1
0
1
0
1
0
1
CNTR1 output control by timer 4 underflow signal divided by 2
D7(I/O)/CNTR1 input
D7/CNTR1 function selection bit
CNTR0 output control bit
CNTR1 (I/O)/D7(input)
Timer 1 underflow signal output divided by 2
CNTR0 output control by timer 2 underflow signal divided by 2
D6(I/O)/CNTR0 input
D6/CNTR0 output control bit
CNTR0 (I/O)/D6(input)
Note: “R” represents read enabled, and “W” represents write enabled.
83
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Serial I/O mode register J1
Not used
at reset : 00002
R/W
at RAM back-up : state retained
0
1
0
1
0
1
0
1
J13
J12
J11
J10
This bit has no function, but read/write is enabled.
Instruction clock signal divided by 8
Instruction clock signal divided by 4
Input ports P20, P21, P22 selected
Serial I/O internal clock dividing ratio
selection bit
Serial I/O port selection bit
Serial I/O ports SCK, SOUT, SIN/input ports P20, P21, P22 selected
External clock
Serial I/O synchronous clock selection bit
A-D control register Q1
Note used
Internal clock (instruction clock divided by 4 or 8)
at reset : 00002
at RAM back-up : state retained
R/W
0
Q13
Q12
This bit has no function, but read/write is enabled.
1
Q12
0
Selected pins
Q11Q10
AIN0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
AIN1
0
AIN2
Q11
Q10
0
Analog input pin selection bits (Note 2)
AIN3
1
AIN4 (Not available for the 4513 Group)
AIN5 (Not available for the 4513 Group)
AIN6 (Not available for the 4513 Group)
AIN7 (Not available for the 4513 Group)
1
1
1
A-D control register Q2
at reset : 00002
at RAM back-up : state retained
R/W
R/W
R/W
0
1
0
1
0
1
0
1
A-D conversion mode
Comparator mode
A-D operation mode selection bit
Q23
Q22
Q21
Q20
P43/AIN7 and P42/AIN6 pin function selec-
tion bit (Not used for the 4513 Group)
P41/AIN5 pin function selection bit
(Not used for the 4513 Group)
P43, P42
(read/write enabled for the 4513 Group)
AIN7, AIN6/P43, P42 (read/write enabled for the 4513 Group)
P41
(read/write enabled for the 4513 Group)
(read/write enabled for the 4513 Group)
(read/write enabled for the 4513 Group)
(read/write enabled for the 4513 Group)
AIN5/P41
P40
P40/AIN4 pin function selection bit
(Not used for the 4513 Group)
AIN4/P40
Comparator control register Q3 (Note 3)
Voltage comparator (CMP1) control bit
Voltage comparator (CMP0) control bit
CMP1 comparison result store bit
CMP0 comparison reslut store bit
Clock control register MR
System clock selection bit
Not used
at reset : 00002
at RAM back-up : state retained
0
1
0
1
0
1
0
1
Voltage comparator (CMP1) invalid
Voltage comparator (CMP1) valid
Voltage comparator (CMP0) invalid
Voltage comparator (CMP0) valid
CMP1- > CMP1+
Q33
Q32
Q31
Q30
CMP1- < CMP1+
CMP0- > CMP0+
CMP0- < CMP0+
at reset : 10002
at RAM back-up : 10002
0
1
0
1
0
1
0
1
f(XIN) (high-speed mode)
MR3
MR2
MR1
MR0
f(XIN)/2 (middle-speed mode)
This bit has no function, but read/write is enabled.
Not used
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
Not used
Notes 1: “R” represents read enabled, “W” represents write enabled.
2: Select AIN4–AIN7 with register Q1 after setting register Q2.
3: Bits 0 and 1 of register Q3 can be only read.
84
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Key-on wakeup control register K0
at reset : 00002
at RAM back-up : state retained
R/W
R/W
W
Pins P12 and P13 key-on wakeup
control bit
0
1
0
1
0
1
0
1
Key-on wakeup not used
K03
K02
K01
K00
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Pins P10 and P11 key-on wakeup
control bit
Pins P02 and P03 key-on wakeup
control bit
Pins P00 and P01 key-on wakeup
control bit
Pull-up control register PU0
at reset : 00002
at RAM back-up : state retained
Pins P12 and P13 pull-up transistor
control bit
0
1
0
1
0
1
0
1
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
PU03
PU02
PU01
PU00
Pins P10 and P11 pull-up transistor
control bit
Pins P02 and P03 pull-up transistor
control bit
Pins P00 and P01 pull-up transistor
control bit
Direction register FR0 (Note 2)
Port P53 input/output control bit
Port P52 input/output control bit
Port P51 input/output control bit
Port P50 input/output control bit
at reset : 00002
at RAM back-up : state retained
0
1
0
1
0
1
0
1
Port P53 input
Port P53 output
Port P52 input
Port P52 output
Port P51 input
Port P51 output
Port P50 input
Port P50 output
FR03
FR02
FR01
FR00
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: The 4513 Group does not have the direction register FR0.
85
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
BUILT-IN PROM VERSION
In addition to the mask ROM versions, the 4513/4514 Group has
programmable ROM version software compatible with mask ROM.
The built-in PROM of One Time PROM version can be written to
and not be erased.
The built-in PROM versions have functions similar to those of the
mask ROM versions, but they have PROM mode that enables writ-
ing to built-in PROM.
Table 25 shows the product of built-in PROM version. Figure 49
and 50 show the pin configurations of built-in PROM versions.
Table 25 Product of built-in PROM version
PROM size
(✕✕10 bits)
4096 words
8192 words
8192 words
RAM size
(✕✕ 4 bits)
256 words
384 words
384 words
Product
Package
ROM type
M34513E4SP/FP
M34513E8FP
M34514E8FP
SP: 32P4B FP: 32P6U-A
32P6B-A
One Time PROM version
[shipped in blank]
42P2R-A
1
42
41
40
39
38
P1
P1
P1
P0
P0
P0
P0
2
1
0
3
2
1
0
P1
D
D
D
D
D
D
3
0
1
2
3
4
5
1
2
32
D0
D1
P13
P12
P11
P10
P03
P02
P01
P00
2
3
4
5
6
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
3
D2
4
D3
5
D4
37
36
35
34
6
D5
7
8
7
D6/CNTR0
D7/CNTR1
P20/SCK
P21/SOUT
P22/SIN
RESET
CNVSS
XOUT
P4
P4
P4
3
2
1
0
/AIN7
/AIN6
/AIN5
/AIN4
D
6
7
/CNTR0
/CNTR1
8
9
D
9
AIN3/CMP1+
AIN2/CMP1-
AIN1/CMP0+
AIN0/CMP0-
P31/INT1
P30/INT0
VDCE
33
10
11
P50
P51
P52
P53
10
11
12
13
14
15
16
32 P4
31
30
A
IN3/CMP1+
IN2/CMP1-
IN1/CMP0+
IN0/CMP0-
12
13
14
15
A
29
28
27
26
25
A
P20/SCK
A
XIN
P2
P2
RESET
1
/SOUT
P3
3
2
16
17
VSS
VDD
2
/SIN
P3
P3
1
/INT1
/INT0
Outline 32P4B
CNVSS 18
OUT 19
X
P3
0
24
23
20
21
X
IN
VDCE
22
V
DD
V
SS
Outline 42P2R-A
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
D3
P02
D4
D5
P01
P00
D6/CNTR0
D7/CNTR1
P20/SCK
P21/SOUT
P22/SIN
AIN3/CMP1+
AIN2/CMP1-
AIN1/CMP0+
AIN0/CMP0-
P31/INT1
M34513ExFP
Fig. 50 Pin configuration of built-in PROM version of 4514 Group
Outline 32P6U-A
Fig. 49 Pin configuration of built-in PROM version of 4513 Group
86
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(1) PROM mode
Table 26 Programming adapters
Microcomputer
The built-in PROM version has a PROM mode in addition to a nor-
mal operation mode. The PROM mode is used to write to and read
from the built-in PROM.
Programming adapter
PCA7442SP
M34513E4SP
M34513E4FP, M34513E8FP
M34514E8FP
PCA7442FP
In the PROM mode, the programming adapter can be used with a
general-purpose PROM programmer to write to or read from the
built-in PROM as if it were M5M27C256K. Programming adapters
are listed in Table 26.Contact addresses at the end of this sheet for
the appropriate PROM programmer.
PCA7441
Address
000016
1
1
1
1
D
4
D
3
D2
D1
D0
1
1
• Writing and reading of built-in PROM
Programming voltage is 12.5 V. Write the program in the PROM
of the built-in PROM version as shown in Figure 51.
Low-order 5 bits
1FFF16
(2) Notes on handling
➀A high-voltage is used for writing. Take care that overvoltage is
not applied. Take care especially at turning on the power.
➀For the One Time PROM version shipped in blank, Mitsubishi
Electric corp. does not perform PROM writing test and screening
in the assembly process and following processes. In order to im-
prove reliability after writing, performing writing and test
according to the flow shown in Figure 52 before using is recom-
mended (Products shipped in blank: PROM contents is not
written in factory when shipped).
400016
5FFF16
D3
D2
D1
D0
D4
High-order 5 bits
7FFF16
Set “FF16” to the shaded area.
Fig. 51 PROM memory map
Writing with PROM programmer
Screening (Leave at 150 °C for 40 hours) (Note)
Verify test with PROM programmer
Function test in target device
Note:
Since the screening temperature is higher
than storage temperature, never expose the
microcomputer to 150 °C exceeding 100
hours.
Fig. 52 Flow of writing and test of the product shipped in blank
87
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Unit
Parameter
Symbol
Conditions
Ratings
V
Supply voltage
VDD
–0.3 to 7.0
Input voltage P0, P1, P2, P3, P4, P5, RESET,
XIN, VDCE
V
VI
–0.3 to VDD+0.3
V
V
V
V
V
Input voltage D0–D7
VI
–0.3 to 13
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to 13
–0.3 to VDD+0.3
300
Input voltage AIN0–AIN7
Output voltage P0, P1, P3, P4, P5, RESET
Output voltage D0–D7
VI
VO
VO
VO
Output transistors in cut-off state
Output voltage XOUT
Package: 42P2R
mW
Power dissipation
Pd
Ta = 25 °C
300
Package: 32P6U
Package: 32P4B
1100
°C
°C
Operating temperature range
Storage temperature range
Topr
Tstg
–20 to 85
–40 to 125
88
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
RECOMMENDED OPERATING CONDITIONS 1
(Mask ROM version:Ta = –20 °C to 85 °C, VDD = 2.0 V to 5.5 V, unless otherwise noted)
(One Time PROM version:Ta = –20 °C to 85 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Conditions
Unit
Min.
2.5
2.0
4.0
2.5
2.0
Max.
5.5
5.5
5.5
5.5
5.5
f(XIN) ≤ 4.2 MHz
f(XIN) ≤ 3.0 MHz
f(XIN) ≤ 4.2 MHz
f(XIN) ≤ 2.0 MHz
f(XIN) ≤ 1.5 MHz
Mask ROM version
Middle-speed mode
Mask ROM version
High-speed mode
VDD
Supply voltage
V
One Time PROM version
Middle-speed mode
2.5
f(XIN) ≤ 4.2 MHz
5.5
4.0
2.5
1.8
2.0
f(XIN) ≤ 4.2 MHz
f(XIN) ≤ 2.0 MHz
5.5
5.5
One Time PROM version
High-speed mode
Mask ROM version
RAM back-up voltage
(at RAM back-up mode)
Supply voltage
VRAM
V
One Time PROM version
0
VSS
VIH
VIH
VIH
VIH
VIL
VIL
VIL
V
V
V
V
V
V
V
V
0.8VDD
0.8VDD
0.85VDD
0.85VDD
0
VDD
12
P0, P1, P2, P3, P4, P5, XIN, VDCE
D0–D7
“H” level input voltage
“H” level input voltage
“H” level input voltage
“H” level input voltage
“L” level input voltage
“L” level input voltage
“L” level input voltage
VDD
RESET
VDD
CNTR0, CNTR1, SIN, SCK, INT0, INT1
P0, P1, P2, P3, P4, P5, D0–D7, XIN, VDCE
RESET
0.2VDD
0.3VDD
0.15VDD
0
0
CNTR0, CNTR1, SIN, SCK, INT0, INT1
–20
VDD = 5.0 V
IOH(peak)
IOH(avg)
IOL(peak)
IOL(peak)
IOL(peak)
IOL(peak)
IOL(avg)
IOL(avg)
IOL(avg)
P5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
“H” level peak output current
“H” level average output current
“L” level peak output current
“L” level peak output current
“L” level peak output current
“L” level peak output current
“L” level average output current
“L” level average output current
“L” level average output current
VDD = 3.0 V
–10
–10
VDD = 5.0 V
P5 (Note)
VDD = 3.0 V
–5
VDD = 5.0 V
P3, RESET
10
4
VDD = 3.0 V
VDD = 5.0 V
40
30
24
12
24
12
5
D6, D7
VDD = 3.0 V
VDD = 5.0 V
D0–D5
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
P0, P1, P4, P5, SCK,
SOUT
P3, RESET (Note)
D6, D7 (Note)
D0–D5 (Note)
2
30
15
15
7
P0, P1, P4, P5, SCK,
SOUT (Note)
12
6
IOL(avg)
ΣIOH(avg)
ΣIOL(avg)
“L” level average output current
“H” level total average current
“L” level total average current
P5
–30
P5, D, RESET, SCK, SOUT
P0, P1, P3, P4
80
80
mA
Note: The average output current (IOH, IOL) is the average value during 100 ms.
89
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
RECOMMENDED OPERATING CONDITIONS 2
(Mask ROM version:Ta = –20 °C to 85 °C, VDD = 2.0 V to 5.5 V, unless otherwise noted)
(One Time PROM version:Ta = –20 °C to 85 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Conditions
VDD = 2.5 V to 5.5 V
Unit
Max.
4.2
Min.
Mask ROM version
Middle-speed mode
One Time PROM version
Middle-speed mode
VDD = 2.0 V to 5.5 V
3.0
VDD = 2.5 V to 5.5 V
4.2
Oscillation frequency
f(XIN)
(with a ceramic resonator)
VDD = 4.0 V to 5.5 V
VDD = 2.5 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 4.0 V to 5.5 V
VDD = 2.5 V to 5.5 V
4.2 MHz
Mask ROM version
High-speed mode
2.0
1.5
4.2
2.0
One Time PROM version
High-speed mode
Mask ROM version
VDD = 2.0 V to 5.5 V
VDD = 2.5 V to 5.5 V
3.0
3.0
Middle-speed mode
One Time PROM version
Middle-speed mode
Oscillation frequency
VDD = 4.0 V to 5.5 V
VDD = 2.5 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 4.0 V to 5.5 V
VDD = 2.5 V to 5.5 V
VDD = 4.0 V to 5.5 V
VDD = 2.5 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 4.0 V to 5.5 V
VDD = 2.5 V to 5.5 V
VDD = 4.0 V to 5.5 V
VDD = 2.5 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 4.0 V to 5.5 V
VDD = 2.5 V to 5.5 V
VDD = 4.0 V to 5.5 V
VDD = 2.5 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 4.0 V to 5.5 V
VDD = 2.5 V to 5.5 V
VDD = 4.0 V to 5.5 V
VDD = 2.5 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 4.0 V to 5.5 V
VDD = 2.5 V to 5.5 V
3.0 MHz
f(XIN)
Mask ROM version
High-speed mode
(with external clock input)
1.0
0.8
3.0
1.0
One Time PROM version
High-speed mode
1.5
3.0
4.0
1.5
3.0
750
1.5
2.0
750
1.5
1.5
3.0
4.0
1.5
3.0
750
1.5
2.0
750
1.5
Mask ROM version
Middle-speed mode
µs
One Time PROM version
Middle-speed mode
Serial I/O external clock period
tw(SCK)
ns
(“H” and “L” pulse width)
Mask ROM version
High-speed mode
µs
One Time PROM version
High-speed mode
ns
µs
Mask ROM version
Middle-speed mode
µs
One Time PROM version
Middle-speed mode
Timer external input period
tw(CNTR)
ns
(“H” and “L” pulse width)
Mask ROM version
High-speed mode
µs
One Time PROM version
High-speed mode
ns
µs
90
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
(Mask ROM version:Ta = –20 °C to 85 °C, VDD = 2.0 V to 5.5 V, unless otherwise noted)
(One Time PROM version:Ta = –20 °C to 85 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
IOH = –10 mA
Unit
V
Min.
3
Max.
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VOH
“H” level output voltage P5
IOH = –5 mA
IOL = 12 mA
IOL = 6 mA
IOL = 5 mA
IOL = 2 mA
IOL = 30 mA
IOL = 10 mA
IOL = 15 mA
IOL = 5 mA
IOL = 15 mA
IOL = 3 mA
2
2
0.9
2
VOL
VOL
“L” level output voltage P0, P1, P4, P5
“L” level output voltage P3, RESET
V
V
0.9
2
VDD = 5 V
VDD = 3 V
V
0.9
2
VOL
VOL
“L” level output voltage D6, D7
“L” level output voltage D0–D5
V
0.9
2
VDD = 5 V
V
VDD = 3 V
0.9
“H” level input current
VI = VDD, port P4 selected,
port P5: input state
VI = 12 V
IIH
IIH
IIL
IIL
µA
µA
µA
µA
1
1
P0, P1, P2, P3, P4, P5, RESET, VDCE
“H” level input current D0–D7
“L” level input current
VI = 0 V No pull-up of ports P0 and P1,
port P4 selected, port P5: input state
VI = 0 V
–1
–1
P0, P1, P2, P3, P4, P5, RESET, VDCE
“L” level input current D0–D7
VDD = 5 V
1.8
0.5
0.9
0.2
3.0
0.6
0.9
0.3
0.1
5.5
1.5
2.7
0.6
9.0
1.8
2.7
0.9
1
f(XIN) = 4.0 MHz
Middle-speed mode
VDD = 3 V
f(XIN) = 400 kHz
f(XIN) = 4.0 MHz
f(XIN) = 400 kHz
f(XIN) = 4.0 MHz
f(XIN) = 400 kHz
f(XIN) = 2.0 MHz
f(XIN) = 400 kHz
Middle-speed mode
VDD = 5 V
at active mode
Supply current
mA
High-speed mode
VDD = 3 V
IDD
High-speed mode
Ta = 25 °C
at RAM back-up mode
Pull-up resistor value
VDD = 5 V
10
µA
VDD = 3 V
6
VDD = 5 V
50
100
0.3
0.3
1.5
0.6
20
40
125
250
VI = 0 V
kΩ
V
RPU
VDD = 3 V
VDD = 5 V
Hysteresis INT0, INT1, CNTR0, CNTR1,
SIN, SCK
VT+ – VT–
VT+ – VT–
VDD = 3 V
VDD = 5 V
Hysteresis RESET
V
VDD = 3 V
91
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
A-D CONVERTER RECOMMENDED OPERATING CONDITIONS
(Comparator mode included, Ta = –20 °C to 85 °C, unless otherwise noted)
Limits
Typ.
Unit
Symbol
Parameter
Supply voltage
Conditions
Max.
5.5
Min.
2.7
0
V
VDD
VIA
V
Analog input voltage
VDD
MHz
MHz
Middle-speed mode, VDD ≥ 2.7 V
High-speed mode, VDD ≥ 2.7 V
0.8
0.4
f(XIN)
Oscillation frequency
A-D CONVERTER CHARACTERISTICS
(Ta = –20 °C to 85 °C, unless otherwise noted)
Limits
Typ.
Unit
bits
Symbol
Test conditions
Parameter
Resolution
Max.
10
Min.
–
–
Ta = 25 °C, VDD = 2.7 V to 5.5 V
Ta = –25 °C to 85 ° C, VDD = 3.0 V to 5.5 V
Ta = 25 °C, VDD = 2.7 V to 5.5 V
Ta = –25 °C to 85 ° C, VDD = 3.0 V to 5.5 V
VDD = 5.12 V
LSB
Linearity error
±2
LSB
mV
mV
mA
–
Differential non-linearity error
Zero transition voltage
Full-scale transition voltage
A–D operating current
±0.9
5
3
20
15
0
V0T
VFST
IADD
VDD = 3.072 V
0
VDD = 5.12 V
5115
3069
0.7
0.2
5125
3075
2.0
0.4
93.0
46.5
8
5105
3060
VDD = 3.072 V
f(XIN) = 0.4 MHz to 4.0 MHz
f(XIN) = 0.4 MHz to 2.0 MHz
VDD = 5.0 V
VDD = 3.0 V
f(XIN) = 4.0 MHz, Middle-speed mode
f(XIN) = 4.0 MHz, High-speed mode
Comparator mode
µs
A-D conversion time
Comparator resolution
Comparator error (Note)
TCONV
bits
mV
–
–
–
VDD = 5.12 V
±20
±15
12
VDD = 3.072 V
f(XIN) = 4.0 MHz, Middle-speed mode
f(XIN) = 4.0 MHz, High-speed mode
µs
Comparator comparison time
6
Note: As for the error from the ideal value in the comparator mode, when the contents of the comparator register is n, the logic value of the comparison volt-
age Vref which is generated by the built-in DA converter can be obtained by the following formula.
Logic value of comparison voltage Vref
VDD
Vref =
➀ n
256
n = Value of register AD (n = 0 to 255)
VOLTAGE DROP DETECTION CIRCUIT CHARACTERISTICS
(Ta = –20 °C to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
VRST
Parameter
Test conditions
Unit
V
Min.
2.7
Max.
4.1
Detection voltage
Ta = 25 °C
3.3
3.5
50
3.7
Operation current of voltage
drop detection circuit
VDD = 5.0 V
IRST
µA
100
92
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
VOLTAGE COMPARATOR RECOMMENDED OPERATING CONDITIONS
(Ta = –20 °C to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Supply voltage
Conditions
Unit
Min.
3.0
Max.
5.5
VDD
V
V
VINCMP
tCMP
VDD = 3.0 V to 5.5 V
VDD = 3.0 V to 5.5 V
Voltage comparator input voltage
Voltage comparator response time
0.3VDD
0.7VDD
20
µs
VOLTAGE COMPARATOR CHARACTERISTICS
(Ta = –20 °C to 85 °C, VDD = 3.0 V to 5.5 V, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
Max.
100
50
CMP0- > CMP0+, CMP0- < CMP0+
CMP1- > CMP1+, CMP1- < CMP1+
VDD = 5.0 V
–
Comparison decision voltage error
Voltage comparator operation current
mV
20
15
ICMP
µA
BASIC TIMING DIAGRAM
Machine cycle
Mi
Mi+1
Parameter
Clock
Pin name
X
IN
System clock = f(XIN
)
XIN
System clock = f(XIN)/2
Port D output
Port D input
D
D
0
0
–D
7
7
–D
P0
P1
P3
P4
P5
0
0
0
0
0
–P0
–P1
–P3
–P4
–P5
3
3
3
3
3
Ports P0, P1, P3,
P4, P5 output
P0
P1
P2
P3
P4
P5
0
–P0
3
Ports P0, P1, P2, P3,
P4, P5 input
0
–P1
3
0
0
0
0
–P2
–P3
–P4
–P5
2
3
3
3
Interrupt input
INT0,INT1
93
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
MMP
32P4B
Plastic 32pin 400mil SDIP
EIAJ Package Code
SDIP32-P-400-1.78
JEDEC Code
–
Weight(g)
2.2
Lead Material
Alloy 42/Cu Alloy
32
17
1
16
D
Dimension in Millimeters
Symbol
Min
–
Nom
–
Max
5.08
–
A
A
1
0.51
–
–
3.8
A
2
–
b
0.35
0.9
0.63
0.22
27.8
8.75
–
–
3.0
0°
0.45
1.0
0.73
0.27
28.0
8.9
1.778
10.16
–
0.55
1.3
1.03
0.34
28.2
9.05
–
–
–
15°
b1
b2
c
D
E
e
e1
e
b1
b
b2
SEATING PLANE
L
–
MMP
32P6U-A
Plastic 32pin 7✕7mm body LQFP
EIAJ Package Code
LQFP32-P-0707-0.80
JEDEC Code
Weight(g)
Lead Material
Cu Alloy
–
MD
HD
D
32
25
I
2
1
24
Recommended Mount Pad
Dimension in Millimeters
Symbol
Min
–
0
Nom
–
Max
1.7
0.2
–
0.45
0.175
7.1
7.1
–
9.2
9.2
0.7
–
0.75
–
A
A
A
b
c
D
E
e
H
H
1
2
0.1
1.4
0.37
0.125
7.0
7.0
0.8
9.0
9.0
0.5
1.0
0.6
0.25
–
–
–
0.5
–
7.4
7.4
–
0.32
0.105
6.9
6.9
–
8.8
8.8
0.3
–
0.45
–
–
–
0°
8
17
9
16
A
D
E
L
L
1
L1
e
F
Lp
A3
x
0.2
0.1
10°
–
–
–
y
L
b
Lp
b2
–
1.0
–
x
M
I
2
y
Detail F
M
M
D
E
–
–
94
MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MMP
42P2R-A
Plastic 42pin 450mil SSOP
EIAJ Package Code
JEDEC Code
Weight(g)
0.63
Lead Material
Alloy 42/Cu Alloy
e
b2
SSOP42-P-450-0.80
–
42
22
Recommended Mount Pad
Dimension in Millimeters
F
Symbol
Min
–
0.05
–
0.35
0.13
17.3
8.2
–
11.63
0.3
–
–
–
–
0°
–
–
1.27
Nom
–
–
Max
2.4
–
A
A
A
1
21
1
2
A
2.0
0.4
0.15
17.5
8.4
0.8
11.93
0.5
1.765
0.75
–
–
D
G
b
0.5
0.2
17.7
8.6
–
12.23
0.7
–
c
D
E
e
H
L
A
2
A1
e
b
E
y
L1
z
–
Z
1
0.9
0.15
10°
–
–
–
y
–
–
c
z
b2
0.5
11.43
–
Z
1
Detail G
Detail F
e1
I
2
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•
•
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property
rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by
Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision
on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric
Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical,
aerospace, nuclear, or undersea repeater use.
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© 2001 MITSUBISHI ELECTRIC CORP.
Printed in Japan (ROD) II
New publication, effective July. 2001.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
4513/4514 GROUP DATA SHEET
Rev.
Rev.
date
Revision Description
No.
1.0 First Edition
980807
010724
1.1 Page 1: APPLICATION revised, Table “Under development” eliminated.
Pages 10 to 14: PORT BLOCK DIAGRAMS revised.
Page 24: Fig. 17 revised.
Page 28: Table 9 Timer 1 structure and Timer 3 structure revised.
Page 29: Fig. 19 revised.
Page 32: (10) Count start synchronous circuit (timer 1 and 3) revised.
Page 38: Table 13 Slave (reception); line 6; received → transmitted
Page 39: Fig. 26 AIN8 → AIN4, AIN9 → AIN5, AIN10 → AIN6, AIN11 → AIN7
Page 56: ROM ORDERING METHOD revised.
Mask ROM Order Confirmation Form, Mark Specification Form eliminated.
As for Mask ROM Order Confirmation Form and Mark Specification Form, refer to
http://www.infomicom.maec.co.jp/rom/efram/romtopf.htm
32P6B-A package is changed to 32P6U-A package.
Pages 94 and 95: All packages renewed.
(1/1)
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