M30245_06 [RENESAS]
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES; 瑞萨16位单片机M16C族/ M16C / 20系列
| 型号： | M30245_06 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES |
| 文件： | 总367页 (文件大小：3129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
REJ09B0340-0200
M30245 Group
User's Manual
16
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Technology Corp. without notice. Please review the latest information published
by Renesas Technology Corp. through various means, including the Renesas Technology
Corp. website (http://www.renesas.com).
Rev. 2.00
Revision date: Oct 16, 2006
www.renesas.com
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the
products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General
Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description
in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.
The input pins of CMOS products are generally in the high-impedance state. In operation with an
unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an
associated shoot-through current flows internally, and malfunctions occur due to the false
recognition of the pin state as an input signal become possible. Unused pins should be handled as
described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register settings and pins
are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states of pins are
not guaranteed from the moment when power is supplied until the reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function
are not guaranteed from the moment when power is supplied until the power reaches the level at
which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do not access
these addresses; the correct operation of LSI is not guaranteed if they are accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become stable.
When switching the clock signal during program execution, wait until the target clock signal has
stabilized.
When the clock signal is generated with an external resonator (or from an external oscillator) during
a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover,
when switching to a clock signal produced with an external resonator (or by an external oscillator)
while program execution is in progress, wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number, confirm that the
change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different type numbers may differ
because of the differences in internal memory capacity and layout pattern. When changing to
products of different type numbers, implement a system-evaluation test for each of the products.
How to Use This Manual
This user's manual is written for the M30245 group.
The reader of this manual is expected to have the basic knowledge of electric and logic
circuits and microcomputers.
This manual explains a function of the following kind.
• M30245M8-XXXGP
• M30245MC-XXXGP
• M30245FCGP
These products have similar features except for the memories, which differ from one product to
another. Be careful when writing a program, as the memories have different capacities.
RAM Size
(Byte)
Flash memory version:M30245FCGP
10K
Mask ROM version:M30245MC-XXXGP
5K
Mask ROM version:M30245M8-XXXGP
64K
ROM Size
(Byte)
128K
The figure of each register configuration describes its functions and attributes as follows :
*1
XXX register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
XXX
Address
XXX
When reset
0016
0
*2
R W
Bit name
XXX select bit
Function
Bit symbol
XXX0
b1 b0
0 0 : XXX
0 1 : XXX
1 0 : Must not be set
1 1 : XXX
XXX1
Nothing is assigned.
In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate.
Reserved bit
XXX4
Must always be set to "0"
Function varies with each operation mode
XXX5
XXX6
XXX7
*3
XXX flag
*1
*2
Blank: Set to “0” or “1” according to intended use
0:
1:
X:
Set to “0”
Set to “1”
Nothing is assigned
R:
Read
O.....Possible to read
X.....Impossible to read
–.....Nothing is assigned
Write
W:
O.....Possible to write
X.....Written value is invalid
When write, value can be "0" or "1"
–.....Nothing is assigned
*3
Terms to use here are explained as follows.
• Nothing is assigned
Nothing is assigned to the bit concerned. When write, set “0” for new function in
future plan.
• Must not be set
Not select. The operation at having selected is not guaranteed.
• Reserved bit
Reserved bit. Set the specified value.
• Function varies with each operation mode
Bit function changes according to the mode of peripheral functions.
• Always set to “0” in A mode.
Set the corresponding bit to “0” in A mode.
• Invalid in A mode
The bit concerned has no function in A mode. Set the specified value.
• Valid when bit A=“0”
When bit A is “1”, the bit concerned has no function. When bit A is “0”, the bit concerned has function.
Table of Contents
Chapter 1. Hardware ............................................................ 1
Chapter 2. Peripheral Functions Usage ............................. 3
2.1 Protect ............................................................................................................................. 4
2.1.1 Overview ..................................................................................................................................................4
2.1.2 Protect Operation....................................................................................................................................5
2.2 Timer A ............................................................................................................................ 6
2.2.1 Overview ..................................................................................................................................................6
2.2.2 Operation of Timer A (timer mode) ......................................................................................................12
2.2.3 Operation of Timer A (timer mode, gate function selected) .............................................................. 14
2.2.4 Operation of Timer A (timer mode, pulse output function selected)................................................ 16
2.2.5 Operation of Timer A (event counter mode, reload type selected) ..................................................18
2.2.6 Operation of Timer A (event counter mode, free run type selected)................................................ 20
2.2.7 Operation of timer A (two-phase pulse signal process in event counter mode,
normal mode selected) ........................................................................................................................22
2.2.8 Operation of timer A (two-phase pulse signal process in event counter mode,
multiply-by-4 mode selected)..............................................................................................................24
2.2.9 Operation of Timer A (one-shot timer mode)...................................................................................... 26
2.2.10 Operation of Timer A (pulse width modulation mode, 16-bit PWM mode selected) ..................... 28
2.2.11 Operation of Timer A (pulse width modulation mode, 8-bit PWM mode selected) ....................... 31
2.2.12 Precautions for Timer A (timer mode) ...............................................................................................34
2.2.13 Precautions for Timer A (event counter mode) ................................................................................ 35
2.2.14 Precautions for Timer A (one-shot timer mode)............................................................................... 37
2.2.15 Precautions for Timer A (pulse width modulation mode) ...............................................................38
2.3 Clock-Synchronous Serial I/O ..................................................................................... 39
2.3.1 Overview ................................................................................................................................................39
2.3.2 Operation of Serial I/O (transmission in clock-synchronous serial I/O mode) ............................... 45
2.3.3 Operation of Serial I/O (reception in clock-synchronous serial I/O mode) ..................................... 49
2.3.4 Precautions for Serial I/O (in clock-synchronous serial I/O mode)..................................................53
2.4 Clock-Asynchronous Serial I/O (UART) ..................................................................... 55
2.4.1 Overview ................................................................................................................................................55
2.4.2 Operation of Serial I/O (transmission in UART mode) ...................................................................... 64
2.4.3 Operation of Serial I/O (reception in UART mode).............................................................................68
2.4.4 Serial I/O Precautions (UART Mode) ...................................................................................................72
2.4.5 Operation of Serial I/O (transmission used for SIM interface).......................................................... 73
2.4.6 Operation of Serial I/O (reception used for SIM interface) ................................................................77
2.4.7 Clock Signals in used for the SIM Interface .......................................................................................81
2.5 Serial Interface Special Function ................................................................................ 85
2.5.1 Overview ................................................................................................................................................85
2.5.2 Operation of Serial Interface Special Function (transmission in master mode
without delay) .......................................................................................................................................94
A-1
2.5.3 Operation of Serial Interface Special Function (reception in master mode with
clock delay)...........................................................................................................................................98
2.5.4 Operation of Serial Interface Special Function (transmission in slave mode............................... 102
without delay) ......................................................................................................................................102
2.5.5 Operation of Serial Interface Special Function (reception in slave mode with.............................106
clock delay) .........................................................................................................................................106
2.6 Serial sound interface ................................................................................................ 110
2.6.1 Overview .............................................................................................................................................. 110
2.6.2 Example of Serial Sound Interface operation .................................................................................. 116
2.6.3 Precautions for Serial Sound Interface.............................................................................................120
2.7 Frequency synthesizer (PLL) .................................................................................... 121
2.7.1 Overview ..............................................................................................................................................121
2.7.2 Operation of frequency synthesizer..................................................................................................124
2.7.3 Precautions for Frequency synthesizer............................................................................................126
2.8 USB function ............................................................................................................... 127
2.8.1 Overview ..............................................................................................................................................127
2.8.2 USB function control ..........................................................................................................................139
2.8.3 USB Interrupt.......................................................................................................................................150
2.8.4 USB Operation (Suspend/Resume Function)...................................................................................161
2.8.5 USB Operation (Endpoint 0) ..............................................................................................................169
2.8.6 USB Operation (Endpoints 1 to 4 Receive) ......................................................................................182
2.8.7 USB Operation (Endpoints 1 to 4 Transmit) .....................................................................................193
2.8.8 USB Operation (Interface with DMAC Transfer) ...............................................................................207
2.8.9 Precautions for USB ...........................................................................................................................210
2.9 A/D Converter.............................................................................................................. 213
2.9.1 Overview ..............................................................................................................................................213
2.9.2 Operation of A/D converter (one-shot mode) ...................................................................................218
2.9.3 Operation of A/D Converter (in one-shot mode, an external trigger selected) .............................220
2.9.4 Operation of A/D Converter (in repeat mode)...................................................................................222
2.9.5 Operation of A/D Converter (in single sweep mode) .......................................................................224
2.9.6 Operation of A/D Converter (in repeat sweep mode 0)....................................................................226
2.9.7 Operation of A/D Converter (in repeat sweep mode 1)....................................................................228
2.9.8 Precautions for A/D Converter...........................................................................................................230
2.9.9 Method of A/D Conversion (10-bit mode) .........................................................................................231
2.9.10 Method of A/D Conversion (8-bit mode) .........................................................................................233
2.9.11 Absolute Accuracy and Differential Non-Linearity Error...............................................................235
2.9.12 Internal Equivalent Circuit of Analog Input ....................................................................................237
2.9.13 Sensor’s Output Impedance under A/D Conversion (reference value)........................................238
2.10 DMAC Usage ............................................................................................................. 240
2.10.1 Overview of the DMAC usage ..........................................................................................................240
2.10.2 Operation of DMAC (one-shot transfer mode) ...............................................................................245
2.10.3 Operation of DMAC (repeated transfer mode) ...............................................................................247
2.11 CRC Calculation Circuit ........................................................................................... 249
2.11.1 Overview ............................................................................................................................................249
2.11.2 Operation of CRC Calculation Circuit .............................................................................................251
2.11.3 SFR Access Snoop Function ...........................................................................................................252
2.12 Watchdog Timer........................................................................................................ 253
A-2
2.12.1 Overview ............................................................................................................................................253
2.12.2 Operation of Watchdog Timer (Watchdog timer interrupt) ...........................................................256
2.13 Address Match Interrupt Usage .............................................................................. 258
2.13.1 Overview of the address match interrupt usage............................................................................258
2.13.2 Operation of Address Match Interrupt ............................................................................................260
2.14 Key-Input Interrupt Usage ....................................................................................... 262
2.14.1 Overview of the key-input interrupt usage .....................................................................................262
2.14.2 Operation of Key-Input Interrupt .....................................................................................................265
2.15 Multiple interrupts Usage ........................................................................................ 267
2.15.1 Overview of the Multiple interrupts usage .....................................................................................267
2.15.2 Multiple Interrupts Operation...........................................................................................................272
2.16 Power Control Usage ............................................................................................... 274
2.16.1 Overview of the power control usage .............................................................................................274
2.16.2 Stop Mode Set-Up .............................................................................................................................280
2.16.3 Wait Mode Set-Up..............................................................................................................................281
2.16.4 Precautions in Power Control..........................................................................................................282
2.17 Programmable I/O Ports Usage............................................................................... 284
2.17.1 Overview of the programmable I/O ports usage ............................................................................284
Chapter 3. Examples of Peripheral Functions
Applications................................................... 293
3.1 Long-Period Timers.................................................................................................... 295
3.2 Variable-Period Variable-Duty PWM Output ............................................................. 299
3.3 Buzzer Output ............................................................................................................. 303
3.4 Solution for External Interrupt Pins Shortage ......................................................... 305
3.5 Memory to Memory DMA Transfer ............................................................................ 307
3.7 Buzzer Output ............................................................................................................. 311
3.6 CRC Calculation SFR Access Snoop Function in Clock Synchronous
Serial Data Transmit................................................................................................... 311
3.7 Transfer from USB FIFO to Serial Sound Interface ................................................. 316
3.8 Controlling Power Using Stop Mode ........................................................................ 321
3.9 Controlling Power Using Wait Mode......................................................................... 325
Chapter 4. External Buses............................................... 329
4.1 Overview of External Buses ...................................................................................... 330
4.2 Data Access ................................................................................................................ 331
4.2.1 Data Bus Width ...................................................................................................................................331
4.2.2 Chip Selects and Address Bus ..........................................................................................................332
4.2.3 R/W Modes...........................................................................................................................................333
4.3 Connection Examples ................................................................................................ 334
4.3.1 16-bit Memory to 16-bit Width Data Bus Connection Example ......................................................334
4.3.2 8-bit Memory to 16-bit Width Data Bus Connection Example ........................................................335
A-3
4.3.3 8-bit Memory to 8-bit Width Data Bus Connection Example ..........................................................337
4.3.4 Two 8-bit and 16-Bit Memory to 16-Bit Width Data Bus Connection Example ..............................338
4.3.5 Chip Selects and Address Bus ..........................................................................................................339
4.4 Connectable Memories .............................................................................................. 340
4.4.1 Operation Frequency and Access Time............................................................................................340
4.4.2 Connecting Low-Speed Memory .......................................................................................................343
4.4.3 Connectable Memories.......................................................................................................................346
__________
__________
4.5 Releasing an External Bus (HOLD input and HLDA output)................................... 347
4.6 Precautions for External Bus .................................................................................... 349
Chapter 5. Standard Characteristics .............................. 351
5.1 DC Standard Characteristics ..................................................................................... 352
5.1.1 Port Standard Characteristics ...........................................................................................................352
5.1.2 VCC-ICC Characteristics ....................................................................................................................354
A-4
Chapter 1
Hardware
See M30245 group datasheet.
Chapter 2
Peripheral Functions Usage
M30245 Group
2. Protect
2.1 Protect
2.1.1 Overview
'Protect' is a function that causes a value held in a register to be unchanged even when a program runs
away. The following is an overview of the protect function:
(1) Registers affected by the protect function
The registers affected by the protect function are:
(a) System clock control registers 0, 1 (addresses 000616 and 000716)
(b) Processor mode registers 0, 1 (addresses 000416 and 000516)
(c) Frequency synthesizer-related registers (address 03DB16 to 03DF16)
The values in registers (a) through (c) cannot be changed in write-protect state. To change values in
the registers, put the individual registers in write-enabled state.
(2) Protect register
Figure 2.1.1 shows protect register.
Protect register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PRCR
Address
000A16
When reset
XXXXX000
0
2
Bit symbol
PRC0
Bit name
Function
0 : Write-inhibited
1 : Write-enabled
R W
Enables writing to system clock
control registers 0 and 1 (addresses
000616 and 000716) and frequency
synthesizer registers (addresses
03DB16 to 03DF16
)
0 : Write-inhibited
1 : Write-enabled
PRC1
Enables writing to processor mode
registers 0 and 1 (addresses 000416
and 000516
)
Reserved
Must always be set to “0”
Nothing is assigned.
When write, set “0”. When read, their contents are indeterminate.
Figure 2.1.1. Protect register
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2. Protect
2.1.2 Protect Operation
The following explains the protect operation. Figure 2.1.2 shows the set-up procedure.
(1) Setting “1” in the write-enable bit of system clock control registers 0 and 1 and frequency
synthesizer-related registers causes system clock control register 0 and 1 and frequency
synthesizer-related registers to be in write-enabled state.
Operation
(2) The contents of system clock control register 0 and 1 and these of frequency synthesizer-
related registers are changed.
(3) Setting “0” in PRC0 causes system clock control register 0 and 1 and frequency synthesizer-
related registers to be in write-inhibited state.
(4) To change the contents of processor mode register 0 and that of processor mode register 1,
follow the same steps as in dealing with system clock control registers and frequency synthe-
sizer-related registers.
(1) Clearing the protect (set to write-enabled state)
b7
b0
1
Protect register [Address 000A16
PRCR
]
0
Enables writing to system clock control registers 0 and 1 (addresses 000616 and
000716 and frequency synthesizer-related registers (address 03DB16 to 03DF16
1 : Write-enabled
)
)
(2) Setting system clock control register i (i = 0, 1)
(3) Setting the protect (set to write-inhibited state)
b7
b0
0
Protect register [Address 000A16
PRCR
]
0
Enables writing to system clock control registers 0 and 1 (addresses 000616 and
000716 and frequency synthesizer-related registers (address 03DB16 to 03DF16
0 : Write-inhibited
)
)
Figure 2.1.2. Set-up procedure for protect function
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M30245 Group
2. Timer A
2.2 Timer A
2.2.1 Overview
The following is an overview for timer A, a 16-bit timer.
(1) Mode
Timer A operates in one of the four modes:
(a) Timer mode
In this mode, the internal count source is counted. Two functions can be selected: the pulse output
function that reverses output from a port every time an overflow occurs, or the gate function which
controls the count start/stop according to the input signal from a port.
(b) Event counter mode
This mode counts the pulses from the outside and the number of overflows in other timers. The free-
run type, in which nothing is reloaded from the reload register, can be selected when an underflow
occurs. The pulse output function can also be selected. Please refer to the timer mode explanation
for details, as the operation is identical.
Furthermore, Timer A has a two-phase pulse signal processing function which generates an up
count or down count in the event counter mode, depending on the phase of the two input signals.
The normal mode or 4-multiplication mode can be selected depending on the phase detective
method.
(c) One-shot timer mode
In this mode, the timer is started by the trigger and stops when the timer goes to “0”. The trigger can
be selected from the following 2 types: an overflow of the timer, or a software trigger. The pulse
output function can also be selected. Please refer to the timer mode explanation for details, as the
operation is identical.
(d) Pulse width modulation (PWM) mode
In this mode, the arbitrary pulses are successively output. Either a 16-bit fixed-period PWM mode or
8-bit variable-period mode can be selected. The trigger for initiating output can also be selected.
Please refer to the one-shot timer mode explanation for details, as the operation is identical.
(2) Count source
The internal count source can be selected from f1, f8, f32, and fC32. Clocks f1, f8, and f32 are derived by
dividing the CPU's main clock by 1, 8, and 32 respectively. Clock fC32 is derived by dividing the CPU's
secondary clock by 32.
Rev.2.00 Oct 16, 2006 page 6 of 354
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M30245 Group
2. Timer A
(3) Frequency division ratio
In timer mode or pulse width modulation mode, [the value set in the timer register + 1] becomes the
frequency division ratio. In event counter mode, [the set value + 1] becomes the frequency division
ratio when a down count is performed, or [FFFF16 - the set value + 1] becomes the frequency division
ratio when an up count is performed. In one-shot timer mode, the value set in the timer register be-
comes the frequency division ratio.
The counter overflows (or underflows) when a count source equal to a frequency division ratio is input,
and an interrupt occurs. For the pulse output function, the output from the port varies (the value in the
port register does not vary).
(4) Reading the timer
Either in timer mode or in event counter mode, reading the timer register takes out the count at that
moment. Read it in 16-bit units. The data either in one-shot timer mode or in pulse width modulation
mode is indeterminate.
(5) Writing to the timer
To write to the timer register when a count is in progress, the value is written only to the reload register.
When writing to the timer register when a count is stopped, the value is written both to the reload
register and to the counter. Write a value in 16-bit units.
(6) Relation between the input/output to/from the timer and the direction register
With the output function of the timer, pulses are output regardless of the contents of the port direction
register. To input an external signal to the timer, set the port direction register to input.
(7) Pins related to timer A
(a) TA0IN, TA1IN, TA2IN, TA3IN, TA4IN
Input pins to timer A.
(b) TA0OUT, TA1OUT, TA2OUT, TA3OUT, TA4OUT
Output pins from timer A. They become input pins to
timer A when event counter mode is active.
(8) Registers related to timer A
Figure 2.2.1 shows the memory map of timer A-related registers. Figures 2.2.2 through 2.2.5 show
timer A-related registers.
Rev.2.00 Oct 16, 2006 page 7 of 354
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M30245 Group
2. Timer A
Timer A1 interrupt control register (TA1IC)
004516
004716
005416
005716
Timer A2 interrupt control register (TA2IC)
Timer A0 interrupt control register (TA0IC)
Timer A3 interrupt control register (TA3IC)
Timer A4 interrupt control register (TA4IC)
005916
038016
038116
038216
038316
038416
Count start flag (TABSR)
Clock prescaler reset flag (CPSRF)
One-shot start flag (ONSF)
Trigger select register (TRGSR)
Up-down flag (UDF)
038616
038716
038816
038916
Timer A0 (TA0)
Timer A1 (TA1)
038A16
038B16
Timer A2 (TA2)
Timer A3 (TA3)
Timer A4 (TA4)
038C16
038D16
038E16
038F16
Timer A0 mode register (TA0MR)
Timer A1 mode register (TA1MR)
Timer A2 mode register (TA2MR)
Timer A3 mode register (TA3MR)
039616
039716
039816
039916
039A16 Timer A4 mode register (TA4MR)
Figure 2.2.1. Memory map of timer A-related registers
Timer Ai mode register (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
039616 to 039A16
When reset
0016
TAiMR (i=0 to 4)
Bit Symbol
Bit Name
Function
R
O
W
O
b1 b0
Operation mode
select bit
TMOD0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : PWM mode
TMOD1
MR0
O
O
O
O
O
O
MR1
MR2
MR3
TCK0
TCK1
Function varies with each mode
operation
O
O
O
O
O
O
O
O
Function varies with each mode
operation
Count source select bit
Figure 2.2.2. Timer A-related registers (1)
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2. Timer A
Timer Ai register (i = 0 to 4) (Note 1)
Address
Symbol
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
TA0
TA1
TA2
TA3
TA4
038716, 038616
038916, 038816
038B16, 038A16
038D16, 038C16
038F16, 038E16
(b15
b7
b8)
b0 b7
b0
Mode
Values that can be set
R
W
O
Function
Timer mode
O
16-bit counter (set to divide ratio)
000016 to FFFF16
Event counter
mode
000016 to FFFF16
000016 to FFFF16
16-bit counter (set to divide ratio) (Note 2)
O
O
One-shot
timer mode
16-bit counter (set to one-shot width)
(Note 6)
(Note 3)
(Note 3)
X
X
O
O
16-bit PWM (set to PWM pulse "H" width)
(Note 4, 7)
000016 to FFFF16
16-bit PWM
8-bit PWM
Low-order bits: 8-bit prescaler
(set to PWM period) (Notes 5, 7)
High-order bits : 8-bit PWM
0016 to FE16 (Both high-order and
low-order addresses) (Note 3)
X
O
(set to PWM pulse "H" width) (Notes 5, 7)
Note 1 : Read and write data in 16-bit units.
Note 2 : Counts pulses from an external source of timer overflow.
Note 3 : Use MOV instruction to write to this register.
Note 4 : When setting value is n, PWM period and “H” width of PWM pulses are:
PWM period : (216- 1)/fi
PWM pulse “H” width : n/fi
Note 5 : When setting value of high-order address is n and setting value of low-
order address is m, PWM period and “H” width of PWM pulse are:
PWM period : (28- 1) X (m + 1)/fi
PWM pulse “H” width : (m + 1)n/fi
Note 6 : When the Timer Ai register is set to “000016”, the counter does not
operate and the Timer Ai interrupt request is not generated. When the
pulse is se to output, the pulse does not output from the TAiOUT pin.
Note 7 : When the Timer Ai register is set to “000016”, the pulse width modulator
does not operate and the output level of the TAiOUT pin remains “L”
level, therefore the Timer Ai interrupt request is not generated. This also
occurs in the 8-bit pulse width modulator mode when the significant 8
high-order bits in the Timer Ai register are set to “0016”
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TABSR
Address
038016
When reset
XXX000002
Function
R
O
O
O
O
O
W
O
O
O
O
O
Bit Symbol
TA0S
Bit Name
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
0 : Stops counting
1 : Starts counting
TA1S
TA2S
TA3S
TA4S
Nothing is assigned. Write “0” when writing to these bits.
The contents are indeterminate if read.
_
_
Figure 2.2.3. Timer A-related registers (2)
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2. Timer A
Up/down flag (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UDF
Address
038416
When reset
0016
R
O
O
O
O
O
W
O
O
O
O
O
Bit Symbol
TA0UD
TA1UD
TA2UD
TA3UD
TA4UD
Bit Name
Function
Timer A0 up/down flag
Timer A1 up/down flag
Timer A2 up/down flag
Timer A3 up/down flag
Timer A4 up/down flag
0 : Down count
1 : Up count
This specification becomes valid
when the up/down flag content is
selected for up/down switching cause
Timer A2 two-phase pulse
signal processing select bit
_
_
_
0 : Disabled
1 : Enabled
O
O
O
TA2P
TA3P
Timer A3 two-phase pulse
signal processing select bit
When not using the two-phase pulse
signal processing function, set the
select bit to “0”
Timer A4 two-phase pulse
signal processing select bit
TA4P
Note : Use MOV instruction to write to this register
Trigger select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRGSR
Address
038316
When reset
0016
R
O
W
O
Function
Bit Symbol
TA1TGL
Bit Name
b1 b0
0 0 : Input on TA1IN is selected (Note)
0 1 : Invalid
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
Timer A1 event/trigger
select bit
O
O
O
O
O
O
TA1TGH
TA2TGL
b3 b2
0 0 : Input on TA2IN is selected (Note)
0 1 : Invalid
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
Timer A2 event/trigger
select bit
TA2TGH
b5 b4
TA3TGL
TA3TGH
0 0 : Input on TA3IN is selected (Note)
0 1 : Invalid
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
O
O
Timer A3 event/trigger
select bit
O
O
O
O
b7 b6
TA4TGL
TA4TGH
0 0 : Input on TA4IN is selected (Note)
0 1 : Invalid
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
Timer A4 event/trigger
select bit
O
O
Note: Set the corresponding port direction register to “0”.
Figure 2.2.4. Timer A-related registers (3)
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2. Timer A
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Address
038116
When reset
0XXXXXXX
2
Bit Symbol
Bit Name
Function
R W
Nothing is assigned. Write "0" when writing to these bits.
The contents are indeterminate if read.
0 : No effect
_ _
Clock prescaler reset flag
CPSR
O
O
1 : Reset
(The value is “0” when read)
One-shot start flag
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
ONSF
Address
038216
When reset
0016
Bit Symbol
Bit Name
Function
R
O
W
O
Timer A0 one-shot start flag
TA0OS
TA1OS
TA2OS
TA3OS
0 : Invalid
1 : Timer start (Note 1)
O
O
O
O
O
O
O
O
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Timer A3 one-shot start flag
TA4OS
Timer A4 one-shot start flag
Always set to “0”
O
O
O
O
O
O
Reserved
b1 b0
TA0TGL
TA0TGH
0 0 : Input on TA0IN is selected (Notes 2, 3)
0 1 : Invalid
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
Timer A0 event/trigger
select bit
Note 1 : The value is “0” when read.
Note 2 : Set the corresponding pin's port direction register to “0”.
Note 3 : To start count in one-shot timer mode, do not use an extrenal trigger input.
Figure 2.2.5. Timer A-related registers (4)
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2. Timer A
2.2.2 Operation of Timer A (timer mode)
In timer mode, choose functions from those listed in Table 2.2.1. Operations of the circled items are
described below. Figure 2.2.6 shows the operation timing, and Figure 2.2.7 shows the set-up procedure.
Table 2.2.1. Choosed functions
Item
Set-up
Internal count source (f1 / f8 / f32 / fc32)
Count source
O
O
Pulse output function
No pulses output
Pulses output
Gate function
O
No gate function
Performs count only for the period in which the TAiIN pin is at “L” level
Performs count only for the period in which the TAiIN pin is at “H” level
Operation (1) Setting the count start flag to “1” causes the counter to perform a down count on the count
source.
(2) If an underflow occurs, the content of the reload register is reloaded, and the count continues.
At this time, the timer Ai interrupt request bit goes to “1”.
(3) Setting the count start flag to “0” causes the counter to hold its value and to stop.
n = reload register content
FFFF16
(1) Start count
(2) Underflow
(3) Stop count
n
Start count again
000016
Time
Set to “1” by software
Cleared to “0” by
software
Set to “1” by software
“1”
“0”
Count start flag
Cleared to “0” when interrupt request is accepted, or cleared by software
Timer Ai interrupt
request bit
“1”
“0”
Figure 2.2.6. Operation timing of timer mode
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2. Timer A
Selecting timer mode and functions
b7
b0
0
Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16
TAiMR (i=0 to 4)
]
0
0
0
0
Selection of timer mode
Pulse output function select bit
0 : Pulse is not output (TAi OUT pin is a normal port pin)
Gate function select bit
b4 b3
0 0 :
0 1 :
Gate function not available (TAiIN pin is a normal port pin)
0 (Must always be “0” in timer mode)
Count source select bit
b7 b6
Count source period
Count
source
b7 b6
f(XIN) : 16MH
Z
f(XcIN) : 32.768kH
Z
0 0 : f
0 1 : f
1
8
0
0
1
1
0
1
0
1
f1
62.5ns
1 0 : f32
1 1 : fC32
f8
500ns
2µs
f32
fC32
976.56µs
Setting divide ratio
Timer A0 register [Address 038716, 038616] TA0
Timer A1 register [Address 038916, 038816] TA1
Timer A2 register [Address 038B16, 038A16] TA2
Timer A3 register [Address 038D16, 038C16] TA3
Timer A4 register [Address 038F16, 038E16] TA4
(b15)
b7
(b8)
b0 b7
b0
Can be set to 000016 to FFFF16
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by
dividing the XCIN by 32.)
b7
b0
Clock prescaler reset flag [Address 038116
CPSRF
]
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7
b0
Count start flag [Address 038016
TABSR
]
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Start count
Figure 2.2.7. Set-up procedure of timer mode
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2. Timer A
2.2.3 Operation of Timer A (timer mode, gate function selected)
In timer mode, choose functions from those listed in Table 2.2.2. Operations of the circled items are
described below. Figure 2.2.8 shows the operation timing, and Figure 2.2.9 shows the set-up procedure.
Table 2.2.2. Choosed functions
Item
Set-up
Count source
O
O
Internal count source(f1 / f8 / f32 / fc32)
No pulses output
Pulse output function
Pulses output
Gate function
No gate function
Performs count only for the period in which the TAiIN pin is at “L” level
Performs count only for the period in which the TAiIN pin is at “H” level
O
Operation
(1) When the count start flag is set to “1” and the TAiIN pin inputs at “H” level, the counter per-
forms a down count on the count source.
(2) When the TAiIN pin inputs at “L” level, the counter holds its value and stops.
(3) If an underflow occurs, the content of the reload register is reloaded and the count continues.
At this time, the timer Ai interrupt request bit goes to “1”.
(4) Setting the count start flag to “0” causes the counter to hold its value and to stop.
Note
•
Make the pulse width of the signal input to the TAiIN pin not less than two cycles of the count source.
n = reload register content
FFFF16
n
(1) Start count
(3) Underflow
(2) Stop count
(4) Stop count
Start count again.
000016
Time
Cleared to “0” by software
Set to “1” by software
Set to “1” by software
“1”
“0”
Count start flag
“H”
“L”
TAiIN pin
input signal
Cleared to “0” when interrupt request is accepted, or cleared by software
Timer Ai interrupt
request bit
“1”
“0”
Figure 2.2.8. Operation timing of timer mode, gate function selected
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2. Timer A
Selecting timer mode and functions
b7
b0
0
Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16
TAiMR (i=0 to 4)
]
0
1
1
0
0
Selection of timer mode
Pulse output function select bit
0 : Pulse is not output (TAi OUT pin is a normal port pin)
Gate function select bit
b4 b3
1 1 : Timer counts only when TAiIN pin is held “H” (Note)
0 (Must always be “0” in timer mode)
Count source select bit
b7 b6
Count source period
Count
source
b7 b6
0 0 : f
0 1 : f
1 0 : f32
1 1 : fC32
1
8
f(XIN) : 16MH
Z
f(XcIN) : 32.768kH
Z
0
0
1
1
0
1
0
1
f
1
62.5ns
f
8
500ns
2µs
f
f
32
Note: Set the corresponding port direction register to “0”.
C32
976.56µs
Setting divide ratio
Timer A0 register [Address 038716, 038616] TA0
Timer A1 register [Address 038916, 038816] TA1
Timer A2 register [Address 038B16, 038A16] TA2
Timer A3 register [Address 038D16, 038C16] TA3
Timer A4 register [Address 038F16, 038E16] TA4
(b15)
b7
(b8)
b0 b7
b0
Can be set to 000016 to FFFF16
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by
dividing the XCIN by 32.)
b7
b0
Clock prescaler reset flag [Address 038116
CPSRF
]
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7
b0
Count start flag [Address 038016
TABSR
]
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Start count
Figure 2.2.9. Set-up procedure of timer mode, gate function selected
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2. Timer A
2.2.4 Operation of Timer A (timer mode, pulse output function selected)
In timer mode, choose functions from those listed in Table 2.2.3. Operations of the circled items are
described below. Figure 2.2.10 shows the operation timing, and Figures 2.2.11 shows the set-up proce-
dure.
Table 2.2.3. Choosed functions
Item
Set-up
Count source
O
Internal count source(f
No pulses output
Pulses output
1 / f8 / f32 / fc32)
Pulse output function
O
O
Gate function
No gate function
Performs count only for the period in which the TAiIN pin is at “L” level
Performs count only for the period in which the TAiIN pin is at “H” level
Operation (1) Setting the count start flag to “1” causes the counter to perform a down count on the count
source.
(2) If an underflow occurs, the content of the reload register is reloaded and the count continues.
At this time, the timer Ai interrupt request bit goes to “1”. Also, the output polarity of the
TAiOUT pin reverses.
(3) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the
TAiOUT pin outputs an “L” level.
n = reload register content
(2) Underflow
(3) Stop count
FFFF16
(1) Start count
n
Start count again
000016
Time
Cleared to “0” by
software
Set to “1” by software
Set to “1” by software
“1”
“0”
Count start flag
Pulse output from
TAiOUT pin
“H”
“L”
Cleared to “0” when interrupt request is accepted, or cleared by software
Timer Ai interrupt
request bit
“1”
“0”
Figure 2.2.10. Operation timing of timer mode, pulse output function selected
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2. Timer A
Selecting timer mode and functions
b7
b0
0
Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16
TAiMR (i=0 to 4)
]
1
0
0
0
Selection of timer mode
Pulse output function select bit
1 : Pulse is output (TAi OUT pin is a pulse output pin) (Note)
Gate function select bit
b4 b3
0 0 :
0 1 :
Gate function not available (TAiIN pin is a normal port pin)
0 (Must always be “0” in timer mode)
Count source period
Count source select bit
b7 b6
Count
source
b7 b6
f(XIN) : 16MH
Z
f(XcIN) : 32.768kH
Z
0 0 : f
0 1 : f
1
8
0
0
1
1
0
1
0
1
f
1
62.5ns
f
8
500ns
2µs
1 0 : f32
1 1 : fC32
f
f
32
Note: The setting of the corresponding port register and
the direction register are invalid.
C32
976.56µs
Setting divide ratio
Timer A0 register [Address 038716, 038616] TA0
Timer A1 register [Address 038916, 038816] TA1
Timer A2 register [Address 038B16, 038A16] TA2
Timer A3 register [Address 038D16, 038C16] TA3
Timer A4 register [Address 038F16, 038E16] TA4
(b15)
b7
(b8)
b0 b7
b0
Can be set to 000016 to FFFF16
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by
dividing the XCIN by 32.)
b7
b0
Clock prescaler reset flag [Address 038116
CPSRF
]
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7
b0
Count start flag [Address 038016
]
TABSR
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Start count
Figure 2.2.11. Set-up procedure of timer mode, pulse output function selected
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2. Timer A
2.2.5 Operation of Timer A (event counter mode, reload type selected)
In event counter mode, choose functions from those listed in Table 2.2.4. Operations of the circled items
are described below. Figure 2.2.12 shows the operation timing, and Figure 2.2.13 shows the set-up
procedure.
Table 2.2.4. Choosed functions
Item
Set-up
Item
Set-up
Count source
Pulse output function
O
O
No pulses output
Pulses output
Input signal to TAiIN
(counting falling edges)
O
Count operation type
Reload type
Input signal to TAiIN
(counting rising edges)
Free-run type
Factor for switching
between up and
down
O
Content of up/down flag
Input signal to TAiOUT
TAj overflow
Note: j = i – 1, but j = 4 when i = 0.
(1) Setting the count start flag to “1” causes the counter to count the falling edges of the count
source.
Operation
(2) If an underflow occurs, the content of the reload register is reloaded, and the count continues.
At this time, the timer Ai interrupt request bit goes to “1”.
(3) If switching from an up count to a down count or vice versa while a count is in progress, the
switch takes effect from the next effective edge of the count source.
(4) Setting the count start flag to “0” causes the counter to hold its value and to stop.
(5) If an overflow occurs, the content of the reload register is reloaded, and the count continues.
At this time, the timer Ai interrupt request bit goes to “1”.
n = reload register content
(5) Overflow
FFFF16
n
(3) Switch count
(1) Start count
(2) Underflow
(4) Stop count
Start count again
000016
Time
Cleared to “0” by
software
Set to “1” by software
Set to “1” by software
“1”
Count start flag
“0”
Set to “1” by software
“1”
“0”
Up/down flag
Cleared to “0” when interrupt request is accepted, or cleared by software
Timer Ai interrupt
request bit
“1”
“0”
Figure 2.2.12. Operation timing of event counter mode, reload type selected
Rev.2.00 Oct 16, 2006 page 18 of 354
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2. Timer A
Selecting event counter mode and functions
b7
b0
1
Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16
TAiMR (i=0 to 4)
]
0
0
0
0
0
0
Selection of event counter mode
Pulse output function select bit
0 : Pulse is not output (TAi OUT pin is a normal port pin)
Count polarity select bit
0 : Counts external signal's falling edge
Up/down switching cause select bit
0 : Up/down flag's content
0 (Must always be “0” in event counter mode)
Count operation type select bit
0 : Reload type
Invalid in event counter mode (i = 0, 1)
Invalid when not using two-phase pulse signal processing(i = 2 to 4)
Setting up/down flag
b7
0
b0
Up/down flag [Address 038416
UDF
]
0
0
Timer A0 up/down flag
0 : Down count
Timer A1 up/down flag
0 : Down count
Timer A2 up/down flag
0 : Down count
Timer A3 up/down flag
0 : Down count
Timer A4 up/down flag
0 : Down count
When not using the 2-phase pulse signal processing function, set the select bit to “0”.
Setting one-shot start flag and trigger select register
b7
b0
b7
b0
Trigger select register [Address 038316
TRGSR
]
One-shot start flag [Address 038216
ONSF
]
0
Timer A0 event/trigger select bit
b7 b6
Timer A1 event/trigger select bit
b1 b0
0 0 : Input on TA1IN is selected (Note)
0 0 : Input on TA0IN is selected (Note)
Timer A2 event/trigger select bit
b3 b2
0 0 : Input on TA2IN is selected (Note)
Timer A3 event/trigger select bit
b5 b4
0 0 : Input on TA3IN is selected (Note)
Timer A4 event/trigger select bit
b7 b6
Note: Set the corresponding port direction register to “0”.
0 0 : Input on TA4IN is selected (Note)
Timer A0 register [Address 038716, 038616] TA0
Timer A1 register [Address 038916, 038816] TA1
Timer A2 register [Address 038B16, 038A16] TA2
Timer A3 register [Address 038D16, 038C16] TA3
Timer A4 register [Address 038F16, 038E16] TA4
Setting divide ratio
(b15)
b7
(b8)
b0 b7
b0
Can be set to 000016 to FFFF16
Setting count start flag
b7
b0
Count start flag [Address 038016
TABSR
]
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Start count
Figure 2.2.13. Set-up procedure of event counter mode, reload type selected
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2. Timer A
2.2.6 Operation of Timer A (event counter mode, free run type selected)
In event counter mode, choose functions from those listed in Table 2.2.5. Operations of the circled items
are described below. Figure 2.2.14 shows the operation timing, and Figure 2.2.15 shows the set-up
procedure.
Table 2.2.5. Choosed functions
Item
Set-up
Item
Set-up
Count source
Pulse output function
O
No pulses output
Pulses output
Input signal to TAiIN
(counting falling edges)
O
Count operation type
Reload type
Input signal to TAiIN
(counting rising edges)
O
O
Free-run type
Factor for switching
between up and
down
Content of up/down flag
Input signal to TAiOUT
TAj overflow
Note: j = i – 1, but j = 4 when i = 0
(1) Setting the count start flag to “1” causes the counter to count the falling edges of the count
source.
Operation
(2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count
continues. At this time, the timer Ai interrupt request bit goes to “1”.
(3) If switching from an up count to a down count or vice versa while a count is in progress, the
switch takes effect from the next effective edge of the count source.
(4) Even if an overflow occurs, the content of the reload register is not reloaded, but the count
continues. At this time, the timer Ai interrupt request bit goes to “1”.
n = reload register content
(3) Switch count
(2) Underflow
(4)
Overflow
FFFF16
(1) Start count
n
(Note)
000016
Time
Set to “1” by software
“1”
“0”
Count start flag
Up/down flag
Set to “1” by software
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Timer Ai interrupt
request bit
“1”
“0”
Note: First set to “Reload type” operation. Once the first counting pulse has occurred, the timer may be changed to “Free-Run type”.
Figure 2.2.14. Operation timing of event counter mode, free run type selected
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2. Timer A
Selecting event counter mode and functions
b7
b0
1
Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16
TAiMR (i=0 to 4)
]
0
1
0
0
0
0
Selection of event counter mode
Pulse output function select bit
0 : Pulse is not output (TAi OUT pin is a normal port pin)
Count polarity select bit
0 : Counts external signal's falling edge
Up/down switching cause select bit
0 : Up/down flag's content
0 (Must always be “0” in event counter mode)
Count operation type select bit (Note 1)
1 : Free-run type
Invalid in event counter mode (i = 0, 1)
Invalid when not using two-phase pulse signal processing(i = 2 to 4)
Note 1: First set to “Reload type” operation. Once the first counting pulse has occurred, the timer may be changed to “Free-Run type”.
Setting up/down flag
b7
b0
Up/down flag [Address 038416
UDF
]
0
0
0
Timer A0 up/down flag
0 : Down count
Timer A1 up/down flag
0 : Down count
Timer A2 up/down flag
0 : Down count
Timer A3 up/down flag
0 : Down count
Timer A4 up/down flag
0 : Down count
When not using the two-phase pulse signal processing function, set the select bit to “0”.
Setting one-shot start flag and trigger select register
b7
b0
b7
b0
Trigger select register [Address 038316
TRGSR
]
One-shot start flag [Address 038216
ONSF
]
Timer A0 event/trigger select bit
b7 b6
Timer A1 event/trigger select bit
b1 b0
0 0 : Input on TA1IN is selected (Note 2)
0 0 : Input on TA0IN is selected (Note 2)
Timer A2 event/trigger select bit
b3 b2
0 0 : Input on TA2IN is selected (Note 2)
Timer A3 event/trigger select bit
b5 b4
0 0 : Input on TA3IN is selected (Note 2)
Timer A4 event/trigger select bit
b7 b6
0 0 : Input on TA4IN is selected (Note 2)
Note 2: Set the corresponding port direction register to “0”.
Timer A0 register [Address 038716, 038616] TA0
Timer A1 register [Address 038916, 038816] TA1
Timer A2 register [Address 038B16, 038A16] TA2
Timer A3 register [Address 038D16, 038C16] TA3
Timer A4 register [Address 038F16, 038E16] TA4
Setting divide ratio
(b15)
b7
(b8)
b0 b7
b0
Can be set to 000016 to FFFF16
Setting count start flag
b7
b0
Count start flag [Address 038016
TABSR
]
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Start count
Figure 2.2.15. Set-up procedure of event counter mode, free run type selected
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2. Timer A
2.2.7 Operation of timer A (two-phase pulse signal process in event counter mode,
normal mode selected)
In processing two-phase pulse signals in event counter mode, choose functions from those listed in Table
2.2.6. Operations of the circled items are described below. Figure 2.2.16 shows the operation timing, and
Figure 2.2.17 shows the set-up procedure.
Table 2.2.6. Choosed functions
Item
Set-up
Count operation type
Reload type
O
O
Free run type
Normal processing
4-multiplication processing
Two-phase pulses
process (Note)
Note: Timer A3 alone can be selected. Timer A2 is solely used for normal processes, and timer A4 is solely used for 4
multiplication processes.
Operation (1) Setting the count start flag to “1” causes the counter to count effective edges of the count
source.
(2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count
continues. At this time, the timer Ai interrupt request bit goes to “1”.
(3) Even if an overflow occurs, the content of the reload register is not reloaded, but the count
continues. At this time, the timer Ai interrupt request bit goes to “1”.
Note
• The up count or down count conditions are as follows:
If a rising edge is present at the TAiIN pin when the input signal level to the TAiOUT pin is “H”,
an up count is performed.
If a falling edge is present at the TAiIN pin when the input signal level to the TAiOUT pin is “H”,
a down count is performed.
• Set TAiIN pin and TAiOUT pin's port direction register to “0”.
(1) Start count
“H”
TAiOUT
“L”
“H”
“L”
TAiIN
(2) Underflow
(3)
Overflow
FFFF16
000016
“1”
(Note)
Time
Set to “1” by software
Count start flag
“0”
“1”
“0”
Timer Ai interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleared by software
Note 1: First set to “Reload type” operation. Once the first counting pulse has occurred, the timer may be changed to “Free-Run type”.
Figure 2.2.16. Operation timing of two-phase pulse signal process in event counter mode, normal mode selected
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2. Timer A
Selecting event counter mode and functions
b7
0
b0
1
Timer Ai mode register (i=2, 3) [Address 039816, 039916
TAiMR (i=2, 3)
]
1
0
1
0
0
0
Selection of event counter mode
0 (Must always be “0” when using two-phase pulse signal processing)
0 (Must always be “0” when using two-phase pulse signal processing)
1 (Must always be “1” when using two-phase pulse signal processing)
0 (Must always be “0” when using two-phase pulse signal processing)
Count operation type select bit (Note 1)
1 : Free-run type
Two-phase pulse signal processing operation select bit
0 : Normal processing operation
Note 1: First set to “Reload type” operation. Once the first counting pulse has occurred,
the timer may be changed to “Free-Run type”.
Two-phase pulse signal processing select bit
b7
b0
Up/down flag [Address 038416
UDF
]
Timer A2 two-phase pulse signal processing select bit
1 : Two-phase pulse signal processing enabled
Timer A3 two-phase pulse signal processing select bit
1 : Two-phase pulse signal processing enabled
Setting trigger select register
b7
b0
Trigger select register [Address 038316
TRGSR
]
Timer A2 event/trigger select bit
b3 b2
0 0 : Input on TA2IN is selected (Note 2)
Timer A3 event/trigger select bit
b5 b4
0 0 : Input on TA3IN is selected (Note 2)
Note 2: Set the corresponding port direction register to “0”.
Setting divide ratio
(b15)
b7
(b8)
b0 b7
b0
Timer A2 register [Address 038B16, 038A16] TA2
Timer A3 register [Address 038D16, 038C16] TA3
Can be set to 000016 to FFFF16
Setting count start flag
b7
b0
Count start flag [Address 038016
TABSR
]
Timer A2 count start flag
Timer A3 count start flag
Start count
Figure 2.2.17. Set-up procedure of two-phase pulse signal process in event counter mode, normal mode selected
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2. Timer A
2.2.8 Operation of timer A (two-phase pulse signal process in event counter mode,
multiply-by-4 mode selected)
In processing two-phase pulse signals in event counter mode, choose functions from those listed in Table
2.2.7. Operations of the circled items are described below. Figure 2.2.18 shows the operation timing, and
Figure 2.2.19 shows the set-up procedure.
Table 2.2.7. Choosed functions
Item
Set-up
Reload type
Free run type
Item
Set-up
Count operation type
Normal processing
Processing two- phase
pulses (Note)
O
O
4-multiplication processing
Note: Timer A3 alone can be selected. Timer A2 is solely used for normal processes, and timer A4 is solely used for 4-
multiplication processes.
Operation
(1) Setting the count start flag to “1” causes the counter to count effective edges of the count source.
(2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count
continues. At this time, the interrupt request bit goes to “1”.
(3) Even if an overflow occurs, the content of the reload register is not reloaded, but the count
continues. At this time, the interrupt request bit goes to “1”.
Note
• The up count or down count conditions are as follows:
Table 2.2.8. The up count or down count conditions
Input signal to the
TAiOUT pin
Input signal to the
TAiIN pin
Input signal to the
TAiOUT pin
Input signal to the
TAiIN pin
“H” level
“L” level
Rising
Rising
Falling
“H” level
“L” level
Rising
Falling
Rising
Up count
Down
count
“L” level
“H” level
“H” level
“L” level
Falling
Falling
• Set TAiIN pin and TAiOUT pin's port direction register to “0”.
(1) Start count
“H”
OUT “L”
TAi
“H”
TAi
IN “L”
FFFF16
(Note)
000016
Time
Set to “1” by software
(2) Underflow
(3) Overflow
“1”
Count start flag
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Timer Ai interrupt
request bit
“1”
“0”
Note: First set to “Reload type” operation. Once the first counting pulse has occurred, the timer may be changed to “Free-Run type”.
Figure 2.2.18. Operation timing of two-phase pulse signal process in event counter mode, multiply-by-4 mode selected
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2. Timer A
Selecting event counter mode and functions
b7
1
b0
1
Timer Ai mode register (i= 3, 4) [Address 039916, 039A16
TAiMR (i= 3, 4)
]
1
0
1
0
0
0
Selection of event counter mode
0 (Must always be “0” when using two-phase pulse signal processing)
0 (Must always be “0” when using two-phase pulse signal processing)
1 (Must always be “1” when using two-phase pulse signal processing)
0 (Must always be “0” when using two-phase pulse signal processing)
Count operation type select bit (Note 1)
1 : Free-run type
Two-phase pulse signal processing operation select bit
1 : Multiply-by-4 processing operation
Note 1: First set to “Reload type” operation. Once the first counting pulse has occurred,
the timer may be changed to “Free-Run type”.
Two-phase pulse signal processing select bit
b7
b0
Up/down flag [Address 038416
UDF
]
Timer A3 two-phase pulse signal processing select bit
1 : Two-phase pulse signal processing enabled
Timer A4 two-phase pulse signal processing select bit
1 : Two-phase pulse signal processing enabled
Setting trigger select register
b7
b0
Trigger select register [Address 038316
TRGSR
]
Timer A3 event/trigger select bit
b5 b4
0 0 : Input on TA3IN is selected (Note 2)
Timer A4 event/trigger select bit
b7 b6
0 0 : Input on TA4IN is selected (Note 2)
Note 2: Set the corresponding port direction register to “0”.
Setting divide ratio
(b15)
b7
(b8)
b0 b7
b0
Timer A3 register [Address 038D16, 038C16] TA3
Timer A4 register [Address 038F16, 038E16] TA4
Can be set to 000016 to FFFF16
Setting count start flag
b7
b0
Count start flag [Address 038016
TABSR
]
Timer A3 count start flag
Timer A4 count start flag
Start count
Figure 2.2.19. Set-up procedure of two-phase pulse signal process in event counter mode,
multiply-by-4 mode selected
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2. Timer A
2.2.9 Operation of Timer A (one-shot timer mode)
In one-shot timer mode, choose functions from those listed in Table 2.2.9. Operations of the circled items
are described below. Figure 2.2.20 shows the operation timing, and Figures 2.2.21 shows the set-up
procedure.
Table 2.2.9. Choosed functions
Item
Set-up
Count source
O
O
Internal count source (f1 / f8 / f32 / fc32)
No pulses output
Pulse output function
Pulses output
Count start condition
External trigger input (falling edge of input signal to the TAiIN pin)
External trigger input (rising edge of input signal to the TAiIN pin)
Timer overflow (TAj/TAk overflow)
O
Writing “1” to the one-shot start flag
Note: j = i – 1, but j = 4 when i = 0; k = i + 1, but k = 0 when i = 4.
Operation
(1) Setting the one-shot start flag to “1” with the count start flag set to “1” causes the counter to
perform a down count on the count source. At this time, the TAiOUT pin outputs an “H” level.
(2) The instant the value of the counter becomes “000016”, the TAiOUT pin outputs an “L” level,
and the counter reloads the content of the reload register and stops counting. At this time, the
timer Ai interrupt request bit goes to “1”.
(3) If a trigger occurs while a count is in progress, the counter reloads the value in the reload
register again and continues counting. The reload timing is in step with the next count source
input after the trigger.
(4) Setting the count start flag to “0” causes the counter to stop and to reload the content of the
reload register. Also, the TAiOUT pin outputs an “L” level. At this time, the timer Ai interrupt
request bit goes to “1”.
n = reload register content
(2) Stop count
FFFF16
(3) Start count
(4) Stop count
Reload
(1) Start count
Start count
n
Reload
Reload
000116
Cleared to “0” by software
Time
Set to “1” by software
“1”
“0”
Count start flag
Write signal to
one-shot start flag
1 / f
i
X (n)
1 / fi X (n+1)
“H”
“L”
One-shot pulse output
from TAiOUT pin
“1”
“0”
Timer Ai interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleared by software
Figure 2.2.20. Operation timing of one-shot mode
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2. Timer A
Selecting one-shot timer mode and functions
b7
b0
Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16
TAiMR (i=0 to 4)
]
0
0
1
1
0
Selection of one-shot timer mode
Pulse output function select bit
1 : Pulse is output
External trigger select bit
When internal trigger is selected, this bit can be “1” or “0”
Trigger select bit
0 : When the one-shot start flag is set “1”
0 (Must always be “0” in one-shot timer mode)
Count source select bit
b7 b6
Count source period
f(XIN):16MHz f(XCIN):32.768kHz
62.5ns
Count
source
b7 b6
0 0 : f
0 1 : f
1
8
0
0
f
1
8
0
1
1
1
0
1
f
500ns
2µs
1 0 : f32
1 1 : fC32
f
f
32
C32
976.56µs
(Please refer to the notes on the one-shot timer mode of Timer A.)
Clearing timer Ai interrupt request bit
b7
b0
Timer Ai interrupt control register
0
[Addresses 005416, 004516, 004716, 005716, 005916
]
TAiIC (i=0 to 4)
Interrupt request bit
Setting one-shot timer's time
Timer A0 register [Address 038716, 038616
Timer A1 register [Address 038916, 038816
Timer A2 register [Address 038B16, 038A16
Timer A3 register [Address 038D16, 038C16
Timer A4 register [Address 038F16, 038E16
Can be set to 000116 to FFFF16
]
]
]
TA0
TA1
TA2
TA3
TA4
(b15
b7
(b8)
b0 b7
b0
]
]
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fc32
by dividing the XCIN by 32.)
b7
b0
Clock prescaler reset flag [Address 038116
CPSRF
]
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is "0")
Setting count start flag
b7
b0
Count start flag [Address 038016
TABSR
]
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Setting one-shot start flag
b7
b0
One-shot start flag [Address 038216
ONSF
]
0
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Timer A3 one-shot start flag
Timer A4 one-shot start flag
Start count
Figure 2.2.21. Set-up procedure of one-shot mode
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2. Timer A
2.2.10 Operation of Timer A (pulse width modulation mode, 16-bit PWM mode selected)
In pulse width modulation mode, choose functions from those listed in Table 2.2.10. Operations of the
circled items are described below. Figure 2.2.22 shows the operation timing, and Figures 2.2.23 and
2.2.24 show the set-up procedure.
Table 2.2.10. Choosed functions
Item
Count source
PWM mode
Set-up
1 / f8 / f32 / fc32)
O
O
Internal count source (f
16-bit PWM
8-bit PWM
Count start condition
External trigger input (falling edge of input signal to the TAiIN pin)
External trigger input (rising edge of input signal to the TAiIN pin)
Timer overflow (TAj/TAk overflow)
O
Note: j = i – 1, but j = 4 when i = 0; k = i + 1, but k = 0 when i = 4.
Operation
(1) If the TAiIN pin input level changes from “L” to “H” with the count start flag set to “1”, the counter
performs a down count on the count source. Also, the TAiOUT pin outputs an “H” level.
(2) The TAiOUT pin output level changes from “H” to “L” when a set time period elapses. At this
time, the timer Ai interrupt request bit goes to “1”.
(3) The counter reloads the content of the reload register every time PWM pulses are output for
one cycle, and continues counting.
(4) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the
TAiOUT outputs an “L” level.
16
Note
• The period of PWM pulses becomes (2 – 1)/fi, and the “H” level pulse width becomes n/fi. If
the timer Ai register is set to “000016”, the pulse width modulator does not work, and the the
TAiOUT pin output level remains at “L”.
(fi : frequency of the count source f1, f8, f32, fC32; n : value of the timer)
• Set TAiIN pin's port direction register to “0”.
Conditions: Reload register = 000316, external trigger (rising edge of TAiIN pin input signal) is selected
1 / f
X (216 –1)
i
Count source
“H”
“L”
TAiIN pin
input signal
Trigger is not generated by this signal
Set to “1” by software
Cleared to “0”
by software
“1”
“0”
Count start flag
(1) Start count
(2) Output level “H” to “L”
1 / f X n
(3) One period is complete
(4) Stop count
i
“H”
“L”
PWM pulse output
from TAiOUT pin
Cleared to “0” when interrupt request is
accepted, or cleared by software
“1”
“0”
Timer Ai interrupt
request bit
Note: n = 000016 to FFFE16
Figure 2.2.22. Operation timing of pulse width modulation mode, 16-bit PWM mode selected
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2. Timer A
Selecting PWM mode and functions
b7
b0
1 1
Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16
TAiMR (i=0 to 4)
]
1
0 1 1
Selection of PWM mode
1 (Must always be “1” in PWM mode)
External trigger select bit
1 : Rising edge of TAiIN pin's input signal (Note 1)
Trigger select bit
1 : Selected by event/trigger select register
16/8-bit PWM mode select bit
0 : Functions as a 16-bit pulse width modulator
Count source select bit
b7 b6
Count source period
f(XIN):16MHz f(XCIN):32.768kHz
62.5ns
Count
source
b7 b6
0 0 : f
0 1 : f
1
8
0
0
f
1
8
1 0 : f32
1 1 : fC32
0
1
1
1
0
1
f
500ns
2µs
f
f
32
Note 1: Set the corresponding port direction
register to “0”.
C32
976.56µs
(Please refer to the notes on the pulse width modulation mode of Timer A.)
Clearing timer Ai interrupt request bit
b7
b0
Timer Ai interrupt control register
0
[Addresses 005416, 004516, 004716, 005716, 005916
]
TAiIC (i=0 to 4)
Interrupt request bit
Setting event/trigger select bit
b7
b0
b7
b0
Trigger select register
One-shot start flag
[Address 038316
TRGSR
]
0
[Address 038216
ONSF
]
Timer A1 event/trigger select bit
b1 b0
0 0 : Input on TA1IN is selected (Note 2)
Timer A0 event/trigger select bit
b7 b6
0 0 : Input on TA0IN is selected (Note)
Timer A2 event/trigger select bit
b3 b2
0 0 : Input on TA2IN is selected (Note 2)
Timer A3 event/trigger select bit
b5 b4
0 0 : Input on TA3IN is selected (Note 2)
Timer A4 event/trigger select bit
b7 b6
0 0 : Input on TA4IN is selected (Note 2)
Note 2: Set the corresponding port direction register to “0”.
Setting PWM's pulse's “H” level width
(b15
b7
(b8)
Timer A0 register [Address 038716, 038616
Timer A1 register [Address 038916, 038816
]
]
]
TA0
TA1
TA2
b0 b7
b0
Timer A2 register [Address 038B16, 038A16
Timer A3 register [Address 038D16, 038C16] TA3
Timer A4 register [Address 038F16, 038E16
] TA4
Can be set to 000116 to FFFF16
Continued to the next page
Figure 2.2.23. Set-up procedure of pulse width modulation mode, 16-bit PWM mode selected (1)
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2. Timer A
Continued from the previous page
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fc32
by dividing the XCIN by 32.)
b7
b0
Clock prescaler reset flag [Address 038116
CPSRF
]
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is "0")
Setting count start flag
b7
b0
Count start flag [Address 038016
TABSR
]
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Start count
Figure 2.2.24. Set-up procedure of pulse width modulation mode, 16-bit PWM mode selected (2)
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2. Timer A
2.2.11 Operation of Timer A (pulse width modulation mode, 8-bit PWM mode selected)
In pulse width modulation mode, choose functions from those listed in Table 2.2.11. Operations of the
circled items are described below. Figure 2.2.25 shows the operation timing, and Figures 2.2.26 and
2.2.27 show the set-up procedure.
Table 2.2.11. Choosed functions
Item
Count source
PWM mode
Set-up
O
Internal count source (f1 / f8 / f32 / fc32)
16-bit PWM
O
O
8-bit PWM
Count start condition
External trigger input (falling edge of input signal to the TAiIN pin)
External trigger input (rising edge of input signal to the TAiIN pin)
Timer overflow (TAj/TAk overflow)
Note: j = i – 1, but j = 4 when i = 0; k = i + 1, but k = 0 when i = 4.
Operation
(1) If the TAiIN pin input level changes from “H” to “L” with the count start flag set to “1”, the counter
performs a down count on the count source. Also, the TAiOUT pin outputs an “H” level.
(2) The TAiOUT pin output level changes from “H” to “L” when a set time period elapses. At this
time, the timer Ai interrupt request bit goes to “1”.
(3) The counter reloads the content of the reload register every time PWM pulses are output for
one cycle, and continues counting.
(4) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the
TAiOUT pin outputs an “L” level.
8
Note
• The period of PWM pulses becomes (m + 1) X (2 – 1) / fi, and the “H” level pulse width
becomes n X (m + 1) / fi. If “0016” is set in the eight higher-order bits of the timer Ai register, the
pulse width modulator does not work, and the the TAiOUT pin output level remains at “L”.
(fi : frequency of the count source f1, f8, f32, fc32; n : value of the timer)
• When a trigger is generated, the TAiout pin outputs “L” level of same amplitude as “H” level of
the set PWM pulse, after which it starts PWM pulse output.
• Set TAiIN pin's port direction register to “0”.
Conditions:
Reload register high-order 8 bits = 0216
Reload register low-order 8 bits = 0216
External trigger (falling edge of TAiIN pin input signal) is selected
(4) Stop count
1 / fi X (m + 1) X (28 – 1)
Count source (Note 1)
Count start flag
“1”
“0”
(1) Start count
(2) Output level “H” to “L”
(3)
One period is
complete
“H”
TAiIN pin input
“L”
“H”
“L”
1 / fi X (m+1)
Underflow signal of 8-bit
prescaler (Note 2)
“H”
PWM pulse output from
TAiOUT pin
1 / fi X (m + 1) X n
“L”
“1”
Cleared to “0” when interrupt request
is accepted, or cleared by software
Timer Ai interrupt
request bit
“0”
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 0016 to FE16; n = 0016 to FE16
.
Figure 2.2.25. Operation timing of pulse width modulation mode, with 8-bit PWM mode selected
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2. Timer A
Selecting PWM mode and functions
b7
b0
1 1
Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16
TAiMR (i=0 to 4)
]
1 1 0 1
Selection of PWM mode
1 (Must always be “1” in PWM mode)
External trigger select bit
0 : Falling edge of TAiIN pin's input signal (Note)
Trigger select bit
1 : Selected by event/trigger select register
16/8-bit PWM mode select bit
1 : Functions as a 8-bit pulse width modulator
Count source select bit
b7 b6
Count source period
f(XIN):16MHz f(XCIN):32.768kHz
62.5ns
Count
source
b7 b6
0 0 : f
0 1 : f
1 0 : f32
1 1 : fC32
1
8
0
0
f
1
8
0
1
1
1
0
1
f
500ns
2µs
f
f
32
Note 1: Set the corresponding port direction
register to “0”.
C32
976.56µs
(Please refer to the notes on the pulse width modulation mode of Timer A.)
Clearing timer Ai interrupt request bit
b7
b0
Timer Ai interrupt control register
0
[Addresses 005416, 004516, 004716, 005716, 005916
]
TAiIC (i=0 to 4)
Interrupt request bit
Setting event/trigger select bit
b7
b0
b7
b0
Trigger select register
One-shot start flag
[Address 038316
TRGSR
]
0
[Address 038216
ONSF
]
Timer A1 event/trigger select bit
b1 b0
0 0 : Input on TA1IN is selected (Note 2)
Timer A0 event/trigger select bit
0b70b6: Input on TA0IN is selected (Note)
Timer A2 event/trigger select bit
b3 b2
0 0 : Input on TA2IN is selected (Note 2)
Timer A3 event/trigger select bit
b5 b4
0 0 : Input on TA3IN is selected (Note 2)
Timer A4 event/trigger select bit
b7 b6
0 0 : Input on TA4IN is selected (Note 2)
Note 2: Set the corresponding port direction register to “0”.
Setting PWM's pulse's “H” level width
(b15
b7
(b8)
Timer A0 register [Address 038716, 038616
Timer A1 register [Address 038916, 038816
]
]
]
TA0
TA1
TA2
b0 b7
b0
Timer A2 register [Address 038B16, 038A16
Timer A3 register [Address 038D16, 038C16] TA3
Timer A4 register [Address 038F16, 038E16
] TA4
Can be set to 000116 to FFFF16
Continued to the next page
Figure 2.2.26. Set-up procedure of pulse width modulation mode, 8-bit PWM mode selected (1)
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2. Timer A
Continued from the previous page
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fc32
by dividing the XCIN by 32.)
b7
b0
Clock prescaler reset flag [Address 038116
CPSRF
]
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset (When read, the value is "0")
Setting count start flag
b7
b0
Count start flag [Address 038016
TABSR
]
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Start count
Figure 2.2.27. Set-up procedure of pulse width modulation mode, 8-bit PWM mode selected (2)
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2. Timer A
2.2.12 Precautions for Timer A (timer mode)
(1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the
flag to “1”.
(2) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing,
the value of the counter. Reading the timer Ai register with the reload timing shown in Figure
2.2.28 gets “FFFF16”. Reading the timer Ai register after setting a value in the timer Ai regis-
ter with a count halted but before the counter starts counting gets a proper value.
Reload
2
2
1
1
0
n
n – 1
Counter value (Hex.)
Read value (Hex.)
0
FFFF n – 1
Time
n = reload register content
Figure 2.2.28. Reading timer Ai register
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2. Timer A
2.2.13 Precautions for Timer A (event counter mode)
(1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the
flag to “1”.
(2) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing,
the value of the counter. Reading the timer Ai register with the reload timing shown in Figure
2.2.29 gets “FFFF16” by underflow or “000016” by overflow. Reading the timer Ai register after
setting a value in the timer Ai register with a count halted but before the counter starts count-
ing gets a proper value.
(3) Please note the standards for the differences between the 2 pulses used in the two-phase
pulse signals input signals to the TAiIN pin and TAiOUT pin (i = 2, 3, 4), as shown in Figure
2.2.30.
(4) When free run type is selected, if count is stopped, set a value in the timer Ai register again.
(1) Down count
(2) Up count
Reload
Reload
Counter value
(Hex.)
Counter value
(Hex.)
n
n – 1
2
2
1
1
0
0
n
n + 1
FFFE FFFF
FFFD
Read value
(Hex.)
Read value
(Hex.)
n – 1
n + 1
Time
FFFD FFFE FFFF
0000
FFFF
Time
n = reload register content
n = reload register content
Figure 2.2.29. Reading timer Ai register
Vcc = 5V, f(XIN) = 20MHz
T1
T1
(Min.)
T2, T3
(Min.)
TA2IN
TA3IN
TA4IN
800ns
200ns
Vcc = 3V, f(XIN) = 10MHz
TA2OUT
TA3OUT
TA4OUT
T1
T2, T3
(Min.)
(Min.)
T2
T3
2µs
500ns
Figure 2.2.30. Standard of 2-phase pulses
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2. Timer A
(5) In the case of using as “Free-Run type”, the timer register contents may be unknown when counting
begins. If the timer register is set before counting has started, then the starting value will be unknown.
• In the case where the up/down count will not be changed.
Enable the “Reload” function and write to the timer register before counting begins. Rewrite
the value to the timer register immediately after counting has started. If counting up, rewrite
“000016” to the timer register. If counting down, rewrite “FFFF16” to the timer register. This
will cause the same operation as “Free-Run type” mode.
• In the case where the up/down count has changed.
First set to “Reload type” operation. Once the first counting pulse has occurred, the timer
may be changed to “Free-Run type”.
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2. Timer A
2.2.14 Precautions for Timer A (one-shot timer mode)
(1) At reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the flag
to “1”.
(2) Setting the count start flag to “0” while a count is in progress causes as follows:
• The counter stops counting and a content of reload register is reloaded.
• The TAiOUT pin outputs “L” level.
• The interrupt request generated and the timer Ai interrupt request bit goes to “1”.
(3) The timer Ai interrupt request bit goes to “1” if the timer's operation mode is set using any of
the following procedures:
• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to
“0” after the above listed changes have been made.
(4) If a trigger occurs while a count is in progress, after the counter performs one down count
following the reoccurrence of a trigger, the reload register contents are reloaded, and the
count continues. To generate a trigger while a count is in progress, generate the second
trigger after an elapse longer than one cycle of the timer's count source after the previous
trigger occurred.
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2. Timer A
2.2.15 Precautions for Timer A (pulse width modulation mode)
(1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the
flag to “1”.
(2) The timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compli-
ance with any of the following procedures:
• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to
“0” after the above listed changes have been made.
(3) Setting the count start flag to “0” while PWM pulses are being output causes the counter to
stop counting. If the TAiOUT pin is outputting an “H” level in this instance, the output level
goes to “L”, and the timer Ai interrupt request bit goes to “1”. If the TAiOUT pin is outputting an
“L” level in this instance, the level does not change, and the timer Ai interrupt request is not
generated.
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2. Clock-Synchronous Serial I/O
2.3 Clock-Synchronous Serial I/O
2.3.1 Overview
Clock-synchronous serial I/O carries out 8-bit data communications in synchronization with the clock. The
following is an overview of the clock-synchronous serial I/O.
(1) Transmission/reception format
8-bit data
(2) Transfer rate
If the internal clock is selected as the transfer clock, the divide-by-2 frequency, resulting from the bit
rate generator division, becomes the transfer rate. The bit rate generator count source can be se-
lected from the following: f1, f8, and f32. Clocks f1, f8, and f32 are derived by dividing the CPU’s main
clock by 1, 8, and 32 respectively.
Furthermore, if an external clock is selected as the transfer clock, the clock frequency input to the CLK
pin becomes the transfer rate.
(3) Error detection
Only overrun errors can be detected. Overrun error is an error that occurs if the serial interface starts
receiving the next data item before reading the contents of the UARTi receive buffer register and
receives the 7th bit of the next data.
(4) How to deal with an error
• When receiving data, read an error flag and reception data simultaneously to determine which error
has occurred. If the data read is erroneous, initialize the error flag and the UARTi receive buffer
register, then receive the data again.
To initialize the UARTi receive buffer register
1. Set the receive enable bit to “0” (disable reception).
2. Set the serial I/O mode select bit to “0002” (invalid serial I/O).
3. Set the serial I/O mode select bit.
4. Set the receive enable bit to “1” again (enable reception).
• To transmit data again due to an error such as staggered serial clock caused by noise, set the UARTi
transmit buffer register again, then transmit the data again.
To set the UARTi transmit buffer register again
1. Set the serial I/O mode select bits to “0002” (invalidate serial I/O).
2. Set the serial I/O mode select bits again.
3. Set the transmit enable bit to “1” (enable transmission), then set transmission data in the UARTi
transmit buffer register.
(5) Function selection
For clock-synchronous serial I/O, the following functions can be selected:
_______ _______
(a) CTS/RTS function
_______
In the CTS function, an external IC can start transmission/reception by inputting an “L” level to the
_______
_______
CTS pin. The CTS pin input level is detected when transmission/reception starts. Therefore, if the
level is set to “H” during transmission/reception, it will stop from the next data.
_______
_______
_______
The RTS function informs an external IC that RTS is reception-ready and has changed to “L”. RTS
goes back to “H” at the first falling edge of the transfer clock.
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2. Clock-Synchronous Serial I/O
_______ _______
The clock-synchronous serial I/O has three types of CTS/RTS functions to choose from:
_______ _______
_______ _______
• CTS/RTS functions disabled
CTS/RTS pin is a programmable I/O port.
_______
_______ _______
_______
• CTS function only enabled
CTS/RTS pin performs the CTS function.
_______ _______ _______
_______
• RTS function only enabled
CTS/RTS pin performs the RTS function.
(b) Function for choosing CLK polarity
This function switches the polarity of the transfer clock. The following operations are available:
• Data is input at the falling edge of the transfer clock, and is output at the rising edge.
• Data is input at the rising edge of the transfer clock, and is output at the falling edge.
(c) Function for choosing which bit to transmit/receive first
This function is to choose whether to transmit/receive data from bit 0 or from bit 7. Choose either of
the following:
• LSB first
• MSB first
Data is transmitted/receivec from bit 0.
Data is transmitted/received from bit 7.
(d) Function for choosing continuous receive mode
Continuous receive mode is a mode in which reading the receive buffer register makes the reception-
enabled status ready. In this mode, there is no need to write dummy data to the transmit buffer
register so as to make the reception-enabled status ready. But at the time of starting reception, read
the receive buffer register into a dummy manner.
• Normal mode
Writing dummy data to the transmit buffer register makes the
reception enabled status ready.
• Continuous receive mode
Reading the reception buffer register makes the reception-enabled
status ready.
(e) Data logic select function
This function is to reverse data when writing to transmit buffer register or reading from receive buffer register.
(f) Function for choosing a transmission interrupt factor
The timing to generate a transmission interrupt can be selected from the following: the instant the
transmission buffer is emptied or the instant the transmission register is emptied. When transmis-
sion buffer empty timing is selected, an interrupt occurs when transmitted data is moved from the
transmission buffer to the transmission register. Therefore, data can be transmitted in succession.
When transmission register empty timing is selected, an interrupt occurs when data transmission is
complete.
(g) TxD, RxD I/O polarity reverse function
This function is to reverse a polarity of TxD port output level and a polarity of RxD port input level.
Following are some examples in which various functions (a) through (g) are selected:
_______
• Transmission Operation WITH: CTS function, transmission at falling edge of transfer clock, LSB
First, interrupt at instant transmission buffer is emptied
_______ _______
• Transmission Operation WITH: CTS/RTS function disabled, transmission at falling edge of transfer
clock, LSB First, interrupt at instant transmission is completed
________
•
Reception Operation WITH: RTS function, reception at falling edge of transfer clock, LSB First, suc-
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2. Clock-Synchronous Serial I/O
cessive reception mode disabled
(6) Input to the serial I/O and the direction register
To input an external signal to the serial I/O, slect the function select register A to I/O port and set the
direction register to input.
(7) Pins related to the serial I/O
_______ ________ ________
_______
_______
• CTS0, CTS1, CTS2, CTS3 pins Input pins for the CTS function
________
________
________ _______
_______
• RTS0, RTS1, RTS2, RTS3 pins Output pins for the RTS function
• CLK0, CLK1, CLK2, CLK3 pins
• RxD0, RxD1, RxD2, RxD3 pins
• TxD0, TxD1, TxD2, TxD3 pins
Input/output pins for the transfer clock
Input pins for data
Output pins for data (Note)
Note: Since TxD2 pin is N-channel open drain, this pin needs pull-up resistor.
(8) Registers related to the serial I/O
Figure 2.3.1 shows the memory map of serial I/O-related registers, and Figures 2.3.2 to 2.3.4 show
serial I/O-related registers.
004216 UART2 receive/ACK interrupt control register (S2RIC)
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
UART1 transmit / receive mode register (U1MR)
UART1 bit rate generator (U1BRG)
004816
004A16
UART1 receive/ACK/SSI1 interrupt control register (S1RIC)
UART0 receive/ACK/SSI0 interrupt control register (S0RIC)
UART1 transmit buffer register (U1TB)
UART1 transmit / receive control register 0 (U1C0)
UART1 transmit / receive control register 1 (U1C1)
UART3 transmit/NACK interrupt control register (S3TIC)
UART2 transmit/NACK interrupt control register (S2TIC)
004D16
004F16
005116
005316
005516
UART1 receive buffer register (U1RB)
03A816
03A916
03AA16
03AB16
03AC16
UART0 transmit / receive mode register (U0MR)
UART0 bit rate generator (U0BRG)
UART1 transmit/NACK/SSI1 interrupt control register (S1TIC)
UART0 transmit/NACK/SSI0 interrupt control register (S0TIC)
UART3 receive/ACK interrupt control register (S3RIC)
UART0 transmit buffer register (U0TB)
UART0 transmit / receive control register 0 (U0C0)
UART0 transmit / receive control register 1 (U0C1)
03AD16
03AE16
03AF16
UART0 receive buffer register (U0RB)
UART3 transmit / receive mode register (U3MR)
UART3 bit rate generator (U3BRG)
032816
032916
032A16
032B16
UART3 transmit buffer register (U3TB)
UART3 transmit / receive control register 0 (U3C0)
UART3 transmit / receive control register 1 (U3C1)
032C16
032D16
032E16
032F16
UART3 receive buffer register (U3RB)
0338
0339
033A
033B
16 UART2 transmit / receive mode register (U2MR)
16
UART2 bit rate generator (U2BRG)
16
UART2 transmit buffer register (U2TB)
16
033C
033D
UART2 transmit / receive control register 0 (U2C0)
UART2 transmit / receive control register 1 (U2C1)
16
16
16
033E
UART2 receive buffer register (U2RB)
Figure 2.3.1. Memory map of serial I/O-related registers
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2. Clock-Synchronous Serial I/O
UARTi transmit buffer register (i= 0 to 3) (Note)
b15
(b7)
b8
(b0)b7
Symbol
U0TB
U1TB
U2TB
U3TB
Address
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
b0
03AB16, 03AA16
036B16, 036A16
033B16, 033A16
032B16, 032A16
Function
(UART mode)
Function
Bit Symbol
R W
(clock synchronous serial I/O mode)
Transmit data
Transmit data
Transmit data (9th bit)
Nothing is assigned. Write “0” when writing to these bits.
The values are indeterminate when read.
Note: Use MOV instruction to write to this register.
UARTi receive buffer register (i= 0 to 3)
Symbol
Address
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
b15
(b7)
b8
(b0)b7
b0
U0RB
U1RB
U2RB
U3RB
03AF16, 03AE16
036F16, 036E16
033F16, 033E16
032F16, 032E16
Function
(clock synchronous
serial I/O mode)
Function
(UART mode)
Bit Name
Bit Symbol
R W
Receive data
Receive data
Receive data (9th bit)
Nothing is assigned. Write “0” when writing to these bits.
The values are indeterminate when read.
Arbitration lost
0 : Not detected
detecting flag (Note 1) 1 : Detected
Invalid
ABT
OER
FER
PER
SUM
0 : No overrun error
1 : Overrun error
Overrun error flag
(Note 2)
0 : No overrun error
1 : Overrun error
0 : No framing error
1 : Framing error
Framing error flag
(Note 2)
Invalid
Invalid
Invalid
Parity error flag
(Note 2)
0 : No parity error
1 : Parity error
Error sum flag
(Note 2)
0 : No error
1 : Error
Note 1: Always write “0”.
Note 2: Bits 15 to 12 are set to “00002” when the serial I/O mode select bit (bits 0 to 2 at
addresses 03A816, 036816, 033816, 032816) are set to “0002” or the receive enable
bit is set to “0”. Bit 15 is set to “0” when all of bits 14 to 12 are set to “0”.
Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer
register (addresses 03AE16, 036E16, 033E16, 032E16) is read.
Figure 2.3.2. Serial I/O-related registers (1)
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2. Clock-Synchronous Serial I/O
UARTi bit rate generator (o=0 to 3) (Note 1, 2)
Symbol
U0BRG
U1BRG
U2BRG
U3BRG
Address
03A916
036916
033916
032916
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
b7
b0
R W
Function
Values that can be set
0016 to FF16
Assuming that set value = n, BRGi divides the count source by
n + 1
Note 1: Use MOV instruction to write to this register.
Note 2: Write a value to this register while transmit/receive halts.
UARTi transmit/receive mode register (i = 0 to 3)
Symbol
U0MR
U1MR
U2MR
U3MR
Address
03A816
036816
033816
032816
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
0016
0016
0016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
b2 b1 b0
Must be fixed to 001
b2 b1 b0
SMD0
SMD1
Serial I/O mode select bit
(Note 3)
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Serial I/O mode
0 1 1 : I2C mode
Inhibited except in cases
listed above
Inhibited except in cases
listed above
SMD2
Internal/external clock
select bit
0 : Internal clock
1 : External clock (Note 1)
0 : Internal clock
1 : External clock (Note 1)
CKDIR
STPS
0 : One stop bit
1 : Two stop bits
Stop bit length select bit
Invalid
Valid when bit 6 = “1”
0 : Odd parity
PRY
Odd/even parity select bit Invalid
1 : Even parity
0 : Parity disabled
1 : Parity enabled
PRYE
SLEP
Parity enable bit
Invalid
TxD, RxD input/output
polarity switch bit (Note 2)
0 : Normal
1 : Reversed
Note 1: When I2C bus interface mode is selected, set the port direction register for the corresponding port
(SCLi) to 0, or the port direction register to 1 and the port data register to 1. When a mode other than
serial I/O mode is selected, set the port direction register for the corresponding port (CLKi) to 0.
Note 2: Normally set to “0”.
Note 3: Set the RxDi pin's port direction register to “0” when receiving.
Figure 2.3.3. Serial I/O-related registers (2)
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2. Clock-Synchronous Serial I/O
UARTi transmit/receive control register 0 (i=0 to 3)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC0 (i=0 to 3)
Address
When reset
0816
03AC16, 036C16, 033C16, 032C16
,
Function
(During clock synchronous
serial I/O mode)
b1 b0
Bit
symbol
Function
R W
Bit name
(During UART mode)
b1 b0
CLK0
BRG count source
select bit
0 0 : f
1
8
is selected
is selected
0 0 : f
1
8
is selected
is selected
0 1 : f
0 1 : f
1 0 : f32 is selected
1 1 : Inhibited
1 0 : f32 is selected
1 1 : Inhibited
CLK1
CRS
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 4)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 4)
CTS/RTS function
select bit
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
TXEPT Transmit register empty
flag
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
CRD
CTS/RTS disable bit
Data output select bit
0 : TxDi/SDAi and SCLi pin is CMOS 0 : TxDi/SDAi and SCLi pin is CMOS
NCH
(Note 2)
output
output
1 : TxDi/SDAi and SCLi pin is
N-channel open drain output
1 : TxDi/SDAi and SCLi pin is
N-channel open drain output
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
Set to “0”
CKPOL CLK polarity select bit
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
Transfer format select bit
UFORM
0 : LSB first
1 : MSB first
0 : LSB first
1 : MSB first
(Note 3)
Note 1: Set the corresponding port direction register to “0”.
Note 2: UART2 transfer pin (TxD : P7 and SCL2: P7 ) is N-channel open drain output.
It cannot be set to CMOS output.
2
0
1
Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.
Note 4: The corresponding port register and port direction register are invalid.
UARTi transmit/receive control register 1 (i= 0 to 3)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC1 (i=0 to 3)
Address
When reset
0216
03AD16, 036D16, 033D16, 032D16
Function
(clock synchronous
serial I/O mode)
Function
(UART mode)
Bit Symbol
Bit Name
R W
0 : Transmit disabled
1 : Transmit enabled
Transmit enable
bit
TE
TI
Transmit buffer
empty flag
0 : Data present in transmit buffer register
1 : No data present in transmit buffer register
0 : Receive disabled
1 : Receive enabled
Receive enable
bit
RE
0 : Data packet in receive buffer register
1 : No data packet in receive buffer register
Receive
complete flag
RI
UARTi transmit
interrupt cause
select bit
0 : Transmit buffer empty (TI =1)
1 : Transmit buffer completed ( TXEPT =1)
UiIRS
0 : Continuous receive
UARTi continuous
receive mode
enable bit
mode disabled
1 : Continuous receive
mode enabled
Set to “0”
UiRRM
0 : No reverse
1 : Reverse
Data logic
select bit
UiLCH
UiERE
Set to “0”
The value is
indeterminate when read.
0 : Output disabled
1 : Output enabled
(Note 1)
Error signal
output enable bit
Note 1: When disabling the error signal output, set the UiERE bit to “0” after setting the
UiMR register.
Figure 2.3.4. Serial I/O-related registers (3)
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2. Clock-Synchronous Serial I/O
2.3.2 Operation of Serial I/O (transmission in clock-synchronous serial I/O mode)
In transmitting data in clock-synchronous serial I/O mode, choose functions from those listed in Table
2.3.1. Operations of the circled items are described below. Figure 2.3.5 shows the operation timing, and
Figures 2.3.6 and 2.3.7 show the set-up procedures.
Table 2.3.1. Choosed functions
Item
Set-up
Item
Set-up
LSB first
Transfer clock
source
O
O
Internal clock (f
1
/ f8
/ f32
)
Transfer clock
O
O
O
O
External clock (CLKi pin)
CTS function enabled
CTS function disabled
MSB first
CTS function
CLK polarity
Transmission buffer empty
Transmission complete
Transmission
interrupt factor
Output transmission data at
the falling edge of the
transfer clock
No reverse
Reverse
Data logic select
function
O
Output transmission data at
the rising edge of the
transfer clock
No reverse
Reverse
T
X
D, R
XD I/O
polarity reverse bit
Operation
(1) Setting the transmit enable bit to “1” and writing transmission data to the UARTi transmit
buffer register makes data transmissible status ready.
________
_______
(2) When input to the CTSi pin goes to “L” level, transmission starts (the CTSi pin must be
controlled on the reception side).
(3) In synchronization with the first falling edge of the transfer clock, transmission data held in the
UARTi transmit buffer register is transmitted to the UARTi transmit register. At this time, the
UARTi transmit interrupt request bit goes to “1”. Also, the first bit of the transmission data is
transmitted from the TxDi pin. Then the data is transmitted bit by bit from the lower order in
synchronization with the falling edges.
(4) When transmission of 1-byte data is completed, the transmit register empty flag goes to “1”,
which indicates that transmission is completed. The transfer clock stops at “H” level.
(5) If the next transmission data is set in the UARTi transmit buffer register while transmission is
in progress (before the eighth bit has been transmitted), the data is transmitted in succession.
Rev.2.00 Oct 16, 2006 page 45 of 354
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2. Clock-Synchronous Serial I/O
Example of wiring
(Note)
Microcomputer
Receiver side IC
CLK
CLKi
Di
TX
RXD
CTSi
Port
Note : Since TXD2 pin is N-channel open drain,
this pin needs pull-up resistance.
Example of operation
(1) Transmission enabled
(4) Transmission is complete
(5) Transmit next data
(2) Confirming CTS
Tc
(3) Start transmission
Transfer clock
“1”
“0”
Transmit
enable bit (TE)
Data is set to UARTi transmit buffer register
“1”
“0”
Transmit
buffer empty
flag (Tl)
Transferred from UARTi transmit buffer register to UARTi transmit register
“H”
“L”
CTSi
TCLK
Stopped pulsing because
transfer enable bit = “0”
Stopped pulsing because CTSi = “H”
CLKi
TxDi
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Transmit register
empty flag
(TXEPT)
“1”
“0”
“1”
“0”
Transmit
interrupt request
bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRGi count source (f
n: value set to BRGi
1, f8, f32)
• CTS function is selected.
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
Figure 2.3.5. Operation timing of transmission in clock-synchronous serial I/O mode
Rev.2.00 Oct 16, 2006 page 46 of 354
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2. Clock-Synchronous Serial I/O
Setting UARTi transmit/receive mode register (i=0 to 3)
b7
0
b0
UARTi transmit/receive mode register
0 0 0 1 UiMR [Address 03A816, 36816, 033816, 32816
]
Must be fixed to “001” (Serial I/O mode)
Internal/external clock select bit
0 : Internal clock
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
T
X
D, R
XD I/O polarity reverse bit
Usually set to “0”
Setting UARTi transmit/receive control register 0 (i=0 to 3)
b7
b0
UARTi transmit/receive control register 0
UiC0 [Address 03AC16, 36C16, 033C16, 32C16
0
0
0 0
]
BRG count source select bit
b1 b0
0 0 : f
0 1 : f
1
8
is selected
is selected
1 0 : f32 is selected
1 1 : Inhibited
CTS/RTS function select bit
(Valid when bit 4 = “0”)
0 : CTS function is selected (Note 1)
Transmit register empty flag
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
CTS/RTS disable bit
0 : CTS/RTS function enabled
Data output select bit (Note 2)
0 : TxDi/SDAi and SCLi pin is CMOS output
1 : TxDi/SDAi and SCLi pin is N-channel open drain output
CLK polarity select bit
0 : Transmission data is output at falling edge
of transfer clock and reception data is input
at rising edge
Transfer format select bit
0 : LSB first
Note 1: Set the corresponding port direction register to “0”.
Note 2: UART2 transfer pin (TxD : P7 and SCL : P7 ) is N-channel open drain output.
It cannot be set to CMOS output.
2
0
2
1
Setting UART transmit/receive control register 1 (i=0 to 3)
b7
0
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
0
0
]
UARTi transmit interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
Data logic select bit
0 : No reverse
Set to “0” in clock synchronous serial I/O mode
Continued to the next page
Figure 2.3.6. Set-up procedure of transmission in clock-synchronous serial I/O mode (1)
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2. Clock-Synchronous Serial I/O
Continued from the previous page
Setting UARTi bit rate generator (i = 0 to 3)
b7
b0
UARTi bit rate generator [Address 03A916, 036916, 033916, 032916,]
UiBRG (i = 0 to 3)
Can be set to 0016 to FF16 (Note)
Note: Use MOV instruction to write to this register.
Write to UARTi bit rate generator when transmission/reception is halted.
Transmission enabled
b7
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
1
]
Transmit enable bit
1 : Transmission enabled
Writing transmit data (Note)
(b15
b7
(b8)
b0
UART0 transmit buffer register [Address 03AB16, 03AA16] U0TB
UART1 transmit buffer register [Address 036B16, 036A16] U1TB
UART2 transmit buffer register [Address 033B16, 033A16] U2TB
UART3 transmit buffer register [Address 032B16, 032A16] U3TB
b7
b0
Setting transmission data
Setting transmission data (9th bit)
Note: Use MOV instruction to write to this register.
When CTSi input level = “L”
Start transmission
Checking the status of UARTi transmit /receive control register (i = 0 to 3)
b7
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
]
Transmit buffer empty flag
0 : Data present in transmit buffer register
1 : No data present in transmit buffer register (Writing next transmit data enabled)
When transmitting continuously
Writing next transmit data (Note)
(b15)
b7
(b8)
b0
UART0 transmit buffer register [Address 03AB16, 03AA16] U0TB
UART1 transmit buffer register [Address 036B16, 036A16] U1TB
UART2 transmit buffer register [Address 033B16, 033A16] U2TB
UART3 transmit buffer register [Address 032B16, 032A16] U3TB
b7
b0
Setting transmission data
Setting transmission data (9th bit)
Note: Use MOV instruction to write to this register.
Transmission is complete
Figure 2.3.7. Set-up procedure of transmission in clock-synchronous serial I/O mode (2)
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2. Clock-Synchronous Serial I/O
2.3.3 Operation of Serial I/O (reception in clock-synchronous serial I/O mode)
In receiving data in clock-synchronous serial I/O mode, choose functions from those listed in Table 2.3.2.
Operations of the circled items are described below. Figure 2.3.8 shows the operation timing, and Figures
2.3.9 and 2.3.10 show the set-up procedures.
Table 2.3.2. Choosed functions
Item
Set-up
Item
Set-up
LSB first
Transfer clock
source
O
O
Internal clock (f
1
/ f8
/ f32
)
Transfer clock
O
O
O
O
External clock (CLKi pin)
RTS function enabled
RTS function disabled
MSB first
Disabled
Enabled
RTS function
CLK polarity
Continuous receive
mode
Output transmission data at
the falling edge of the
transfer clock
No reverse
Reverse
Data logic select
function
O
Output transmission data at
the rising edge of the
transfer clock
No reverse
Reverse
T
X
D, R
XD I/O
polarity reverse bit
Operation (1) Writing dummy data to the UARTi transmit buffer register, setting the receive enable bit to “1”,
and the transmit enable bit to “1”, makes the data receivable status ready. At this time, the
________
output from the RTSi pin goes to “L” level, which informs the transmission side that the data
receivable status is ready (output the transfer clock from the IC on the transmission side after
_______
checking that the RTS output has gone to “L” level).
(2) In synchronization with the first rising edge of the transfer clock, the input signal to the RxDi
pin is stored in the highest bit of the UARTi receive register. Then, data is taken in by shifting
right the content of the UARTi reception data in synchronization with the rising edges of the
transfer clock.
(3) When 1-byte data lines up in the UARTi receive register, the content of the UARTi receive
register is transmitted to the UARTi receive buffer register. The transfer clock stops at “H”
level. At this time, the receive complete flag and the UARTi receive interrupt request bit goes
to “1”.
(4) The receive complete flag goes to “0” when the lower-order byte of the UARTi buffer register
is read.
• Set CLKi and RxDi pins' port direction register to “0”.
Note
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2. Clock-Synchronous Serial I/O
Example of wiring
Microcomputer
Transmitter side IC
CLK
CLKi
Di
RTSi
RX
TXD
Port
Example of operation
“1”
Receive enable
bit (RE)
“0”
“1”
“0”
“1”
Transmit enable
bit (TE)
Dummy data is set in UARTi transmit buffer register
Transmit buffer
empty flag (Tl)
“0”
Transferred from UARTi transmit register to UARTi transmit buffer register
“H”
RTSi
CLKi
RxDi
“L”
Even if the reception is completed, RTS does not change.
RTS becomes "L" when the RI bit changes from "1" to "0".
1 / fEXT
Reception data is taken in
D1
D
4
D5
D6
D
1
D3
D4
D6
D7
D0
D2
D3
D0
D2
D5
Transferred from UARTi receive register
to UARTi receive buffer register
Read out from UARTi receive buffer register
“1”
“0”
Receive complete
flag (Rl)
“1”
“0”
Receive interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
“1”
“0”
Overrun error flag
(OER)
Shown in ( ) are bit symbols.
Make sure that the following conditions are met when
the CLKi pin input =“H” before data reception
• Transmit enable bit → “1”
The above timing applies to the following settings:
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = “0”.
• Receive enable bit → “1”
• Dummy data write to UARTi transmit buffer register
f
EXT: frequency of external clock
Figure 2.3.8. Operation timing of reception in clock-synchronous serial I/O mode
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2. Clock-Synchronous Serial I/O
Setting UARTi transmit/receive mode register (i=0 to 3)
b7
0
b0
UARTi transmit/receive mode register
1 0 0 1 UiMR [Address 03A816, 36816, 033816, 32816]
Must be fixed to “001” (Serial I/O mode)
Set the RxDi pin's port direction register to “0” when receiving.
Internal/external clock select bit
1 : External clock (Note)
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
TXD, RXD I/O polarity reverse bit
Usually set to “0”
Note: Set the corresponding port direction register to “0”.
Setting UARTi transmit/receive control register (i=0 to 3)
b7
b0 UARTi transmit/receive control register 0
UiC0 [Address 03AC16, 36C16, 033C16, 32C16]
0 0
0
1
BRG count source select bit
b1 b0
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
CTS/RTS function select bit
(Valid when bit 4 = “0”)
1 : RTS function is selected
Transmit register empty flag
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
CTS/RTS disable bit
0 : CTS/RTS function enabled
Data output select bit (Note)
0 : TxDi/SDAi and SCLi pin is CMOS output
1 : TxDi/SDAi and SCLi pin is N-channel open drain output
CLK polarity select bit
0 : Transmission data is output at falling edge
of transfer clock and reception data is input
at rising edge
Transfer format select bit
0 : LSB first
Note: UART2 transfer pin (TxD2: P70 and SCL2: P71) is N-channel open drain output.
It cannot be set to CMOS output.
Setting UART transmit/receive control register 1 (i=0 to 3)
b7
0
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16]
0 0
UARTi continuous receive mode enable bit
0 : Continuous receive mode disabled
Data logic select bit
0 : No reverse
Set to “0” in clock synchronous serial I/O mode
Continued to the next page
Figure 2.3.9. Set-up procedure of reception in clock-synchronous serial I/O mode (1)
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2. Clock-Synchronous Serial I/O
Continued from the previous page
Reception enabled
b7
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
]
1
1
Transmit enable bit
1 : Transmission enabled
Receive enable bit
1 : Reception enabled (Note)
Writing dummy data (Note)
UART0 transmit buffer register [Address 03AB16, 03AA16] U0TB
UART1 transmit buffer register [Address 036B16, 036A16] U1TB
UART2 transmit buffer register [Address 033B16, 033A16] U2TB
UART3 transmit buffer register [Address 032B16, 032A16] U3TB
b7
b0 b7
b0
Setting dummy data
Note: Use MOV instruction to write to this register.
Start reception
Checking completion of data reception
b7
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
]
Receive complete flag
0 : No data present in receive buffer register
1 : Data present in receive buffer register
Checking error
UART0 receive buffer register [Address 03AF16, 03AE16] U0RB
UART1 receive buffer register [Address 036F16, 036E16] U1RB
UART2 receive buffer register [Address 033F16, 033E16] U2RB
UART3 receive buffer register [Address 032F16, 032E16] U3RB
(b15)
b7
(b8)
b7
b0
b0
Overrun error flag
0 : No overrun error
1 : Overrun error found
Processing after reading out received data
Figure 2.3.10. Set-up procedure of reception in clock-synchronous serial I/O mode (2)
Rev.2.00 Oct 16, 2006 page 52 of 354
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2. Clock-Synchronous Serial I/O
2.3.4 Precautions for Serial I/O (in clock-synchronous serial I/O mode)
Transmission/reception
_______
________
(1) With an external clock selected, and choosing the RTS function, the output level of the RTSi
pin goes to “L” when the data-receivable status becomes ready, which informs the transmis-
________
sion side that the reception has become ready. The output level of the RTSi pin goes to “H”
________
________
when reception starts. So if the RTSi pin is connected to the CTSi pin on the transmission
side, the circuit can transmission and reception data with consistent timing. With the internal
_______
clock, the RTS function has no effect. Figure 2.3.11 shows an example of wiring.
Transmitter side IC
Receiver side IC
TxD
i
TxD
i
RxD
i
RxD
i
CLK
i
CLK
i
i
CTS
i
RTS
Figure 2.3.11. Example of wiring
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Transmission
2. Clock-Synchronous Serial I/O
(1) With an external clock selected, perform the following set-up procedure with the CLKi pin
input level = “H” if the CLK polarity select bit = “0” or with the CLKi pin input level = “L” if the
CLK polarity select bit = “1”:
1. Set the transmit enable bit (to “1”)
2. Write transmission data to the UARTi transmit buffer register
________
_______
3. “L” level input to the CTSi pin (when the CTS function is selected)
Reception
(1) In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock.
Fix settings for transmission even when using the device only for reception. Dummy data is
output to the outside from the TxDi pin (transmission pin) when receiving data.
(2) With the internal clock selected, setting the transmit enable bit to “1” (transmission-enabled
status) and setting dummy data in the UARTi transmission buffer register generates a shift
clock.
With the external clock selected, a shift clock is generated when the transmit enable bit is set
to “1”, dummy data is set in the UARTi transmit buffer register, and the external clock is input
to the CLKi pin.
(3) When receiving data in succession, an overrun error occurs if the serial interface starts re-
ceiving the next data item while the receive complete flag is 1 (before reading the contents of
the UARTi receive buffer register) and receives the 7th bit of the next data item, and then the
overrun error flag is set to “1”. In this instance, the next data is written to the UARTi receive
buffer register, so handle with this problem by writing programs on transmission side and
reception side so that the previous data is transmitted again.
If an overrun error occurs, the UARTi receive interrupt request bit does not go to “1”.
(4) To receive data in succession, set dummy data in the lower-order byte of the UARTi transmit
buffer register every time reception is made. In continuous receive mode, when the receive
buffer is read out,the unit simultaneously goes to a receive enable state without having to set
dummy data back to the transmit buffer register again.
(5) With an external clock selected, perform the following set-up procedure with the CLKi pin
input level = “H” if the CLK polarity select bit = “0” or with the CLKi pin input level = “L” if the
CLK polarity select bit = “1”:
1. Set receive enable bit (to “1”)
2. Set transmit enable bit (to “1”)
3. Write dummy data to the UARTi transmit buffer register
________
(6) Output from the RTS pin goes to “L” level as soon as the receive enable bit is set to “1”. This
is not related to the content of the transmit buffer empty flag or the content of the transmit
enable bit. Output from the RTS pin goes to “H” level when reception starts, and goes to “L”
level when reception is completed. This is not related to the content of the transmit buffer
empty flag or the content of the receive complete flag.
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2. UART
2.4 Clock-Asynchronous Serial I/O (UART)
2.4.1 Overview
UART handles communications by means of character-by-character synchronization. The transmission
side and the reception side are independent of each other, so full-duplex communication is possible. The
following is an overview of the clock-asynchronous serial I/O.
(1) Transmission/reception format
Figure 2.4.1 shows the transmission/reception format, and Table 2.4.1 shows the names and func-
tions of transmission data.
Transfer data length : 7 bits
Transfer data length : 8 bits
Transfer data length : 9 bits
1ST – 7DATA
1ST – 7DATA
1ST – 7DATA – 1PAR – 1SP
1ST – 7DATA – 1PAR – 2SP
1SP
2SP
1ST – 8DATA
1ST – 8DATA
1ST – 8DATA – 1PAR – 1SP
1ST – 8DATA – 1PAR – 2SP
1SP
2SP
1ST – 9DATA
1ST – 9DATA
1SP
2SP
1ST – 9DATA – 1PAR – 1SP
1ST – 9DATA – 1PAR – 2SP
ST
: Start bit
DATA : Character bit (Transfer data)
PAR : Parity bit
SP
: Stop bit
Figure 2.4.1. Transmission/reception format
Table 2.4.1. Transmission data names and functions
Name
Function
A 1-bit “L” signal to be added immediately before character bits.
This bit signals the start of data transmission.
ST (start bit)
DATA (character bits) Transmission data set in the UARTi transmit buffer register.
PAR (parity bit)
SP (stop bit)
A signal to be added immediately after character bits so as to increase data
reliability. The level of this signal so varies that the total number of 1's in
character bits and this bit always becomes even or odd depending on which
parity is chosen, even or odd.
Either 1-bit or 2-bit “H” signal to be added immediately after character bits (after
the parity bit if parity is checked). This / they signals the end of data
transmission.
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2. UART
(2) Transfer rate
The divide-by-16 frequency, resulting from division in the bit rate generator (BRG), becomes the trans-
fer rate. The count source for the transfer rate register can be selected from f1, f8, f32, and the input
from the CLK pin. Clocks f1, f8, f32 are derived by dividing the CPU’s main clock by 1, 8, and 32
respectively.
Table 2.4.2. Example of baud rate setting
System clock : 16MHz
System clock : 7.3728MHz
BRG's set value : n Actual time (bps)
95 (5F16
47 (2F16
23 (1716
95 (5F16
Baud rate
(bps)
BRG's
count source
BRG's set value : n Actual time (bps)
f
f
f
f
f
f
f
f
f
8
600
1200
207 (CF16
103 (6716
51 (3316
207 (CF16
103 (6716
68 (4416
51 (3316
34 (2216
33 (2116
)
)
)
)
)
)
)
)
)
601
1202
)
600
1200
8
8
1
1
1
1
1
1
)
2400
2404
)
2400
4800
4808
)
4800
9600
9615
47 (2F16
31 (1F16
23 (1716
15 (F16
)
)
)
)
9600
14400
19200
28800
31250
14493
19231
28571
31250
14400
19200
28800
(3) An error detection
In UART mode, detected errors are shown in Table 2.4.3.
Table 2.4.3. Error detection
Type of error
Overrun error
Description
When the flag turns on
How to clear the flag
• This error occurs when the
serial interface starts receiving
the next data item before
reading the contents of the
UARTi receive buffer register
and receives the bit preceding
the final stop bit of the next
data item.
• Set the serial I/O mode select
bits to “0002”.
• Set the receive enable bit to
“0”.
• The contents of the UARTi
receive buffer register are
undefined.
• The UARTi receive interrupt
request bit does not go to “1”.
The error is detected
when data is
transferred from the
UARTi receive register
to the UARTi receive
buffer register.
• This error occurs when the
stop bit falls short of the set
number of stop bits.
Framing error
Parity error
• Set the serial I/O mode select
bits to ”0002”.
• Set the receive enable bit to
“0”.
• Read the lower-order byte of
the UARTi receive buffer
register.
• With parity enabled, this error
occurs when the total number
of 1's in character bits and the
parity bit is different from the
specified number.
Error-sum flag
• This flag turns on when any
error (overrun, framing, or
parity) is detected.
• When all error (overrun,
framing, and parity) are
removed, the flag is cleared.
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2. UART
(4) How to deal with an error
When receiving data, read an error flag and reception data simultaneously to determine which error
has occurred. If the data read is erroneous, initialize the error flag and the UARTi receive buffer
register, then receive the data again.
To initialize the UARTi receive buffer register
1. Set the receive enable bit to “0” (disable reception).
2. Set the receive enable bit to “1” again (enable reception).
To transmit data again due to an error on the reception side, set the UARTi transmit buffer register
again, then transmit the data again.
To set the UARTi transmit buffer register again
1. Set the serial I/O mode select bits to “0002” (invalidate serial I/O).
2. Set the serial I/O mode select bits again.
3. Set the transmit enable bit to “1” (enable transmission), then set transmission data in the UARTi
transmit buffer register.
(5) Functions selection
In operating UART, the following functions can be used:
_______ _______
(a) CTS/RTS function
_______
CTS function is a function in which an external IC can start transmission/reception by means of
_______
_______
inputting an “L” level to the CTS pin. The CTS pin input level is detected when transmission/reception
starts, so if the level is gone to“ H” while transmission/reception is in progress, transmission/recep-
tion stops at the next data.
_______
_______
RTS function is a function to inform an external IC that RTS pin output level has changed to “L” when
_______
reception is ready. RTS regoes to “H” at the first falling edge of the transfer clock.
_______ _______
When using clock-asynchronous serial I/O, choose one of three types of CTS/RTS functions.
_______ _______
_______ _______
• CTS/RTS functions disabled
CTS/RTS pin is a programmable I/O port.
_______
_______ _______
_______
• CTS function only enabled
CTS/RTS pin performs the CTS function.
_______ _______ _______
_______
• RTS function only enabled
CTS/RTS pin performs the RTS function.
(b) Data logic select function
This function is to reverse data when writing to transmit buffer register or reading from receive buffer
register.
(c) LSB/MSB first select function
This function is to choose whether to transmit/receive data from bit 0 or bit 7. This is valid when the
transfer data length is 8 bits long.
Choose either of the following:
• LSB first Data is transmitted/received from bit 0.
• MSB first Data is transmitted/received from bit 7.
(d) TxD, RxD I/O polarity reverse function
This function is to reverse a polarity of TxD port output level and a polarity of RxD port input level.
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2. UART
(e) Bus collision detection function
This function is to sample the output level of the TxD pin and the input level of the RxD pin; if their
values are different, then an interrupt request occurs.
The following examples are described in section 2.4.2 and 2.4.3.
_______
• Transmission WITH: CTS function, WITHOUT: other functions
_______
• Reception WITH: RTS function, WITHOUT: other functions
Also, the SIM interface is used by adding some extra settings in clock-asynchronous serial I/O mode.
Direct or inverse format is selected by connecting SIM card.
The following examples are described in section 2.4.4 and 2.4.5.
• Transmission WITH: direct format
• Reception WITH: direct format
(6) Input to the serial I/O and the direction register
To input an external signal to the serial I/O, set the direction register of the relevant port to input.
(7) Pins related to the serial I/O
_________ _________ __________ _________
_______
• CTS0, CTS1, CTS2, CTS3 pins
:Input pins for the CTS function
_________ _________ _________ _________
_______
• RTS0, RTS1, RTS2, RTS3 pins
• CLK0, CLK1, CLK2, CLK3 pins
• RxD0, RxD1, RxD2, RxD3 pins
• TxD0, TxD1, TxD2, TxD3 pins
:Output pins for the RTS function
:Input pins for the transfer clock
:Input pins for data
:Output pins for data (Note)
Note: Since TxD2 pin is N-channel open drain, this pin needs pull-up resistor.
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2. UART
(8) Registers related to the serial I/O
Figure 2.4.2 shows the memory map of serial I/O-related registers, and Figures 2.4.3 to 2.4.6 show
UARTi-related registers.
004216
004316
UART2 receive/ACK interrupt control register (S2RIC)
UART1/3 Bus collision interrupt control register (S13BCNIC)
035F
16
Interrupt cause select register (IFSR)
004816 UART1 receive/ACK/SSI1 interrupt control register (S1RIC)
004916
004A16
UART0/2 Bus collision interrupt control register (S02BCNIC)
UART0 receive/ACK/SSI0 interrupt control register (S0RIC)
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
UART1 transmit / receive mode register (U1MR)
UART1 bit rate generator (U1BRG)
UART1 transmit buffer register (U1TB)
004D16 UART3 transmit/NACK interrupt control register (S3TIC)
004F16 UART2 transmit/NACK interrupt control register (S2TIC)
UART1 transmit / receive control register 0 (U1C0)
UART1 transmit / receive control register 1 (U1C1)
UART1 receive buffer register (U1RB)
005116
005316
005516
UART1 transmit/NACK/SSI1 interrupt control register (S1TIC)
UART0 transmit/NACK/SSI0 interrupt control register (S0TIC)
UART3 receive/ACK interrupt control register (S3RIC)
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
UART0 transmit / receive mode register (U0MR)
UART0 bit rate generator (U0BRG)
UART0 transmit buffer register (U0TB)
032816 UART3 transmit / receive mode register (U3MR)
UART0 transmit / receive control register 0 (U0C0)
UART0 transmit / receive control register 1 (U0C1)
032916
UART3 bit rate generator (U3BRG)
032A16
UART3 transmit buffer register (U3TB)
032B16
UART0 receive buffer register (U0RB)
UART3 transmit / receive control register 0 (U3C0)
UART3 transmit / receive control register 1 (U3C1)
032C16
032D16
032E16
032F16
UART3 receive buffer register (U3RB)
0338
0339
16
UART2 transmit / receive mode register (U2MR)
UART2 bit rate generator (U2BRG)
16
033A
033B
16
UART2 transmit buffer register (U2TB)
16
033C
033D
UART2 transmit / receive control register 0 (U2C0)
UART2 transmit / receive control register 1 (U2C1)
16
16
16
033E
UART2 receive buffer register (U2RB)
Figure 2.4.2. Memory map of UARTi-related registers
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2. UART
UARTi transmit buffer register (i= 0 to 3) (Note)
b15
(b7)
b8
(b0)b7
Symbol
U0TB
U1TB
U2TB
U3TB
Address
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
b0
03AB16, 03AA16
036B16, 036A16
033B16, 033A16
032B16, 032A16
Function
(UART mode)
Function
Bit Symbol
R W
(clock synchronous serial I/O mode)
Transmit data
Transmit data
Transmit data (9th bit)
Nothing is assigned. Write “0” when writing to these bits.
The values are indeterminate when read.
Note: Use MOV instruction to write to this register.
UARTi receive buffer register (i= 0 to 3)
Symbol
Address
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
b15
(b7)
b8
(b0)b7
b0
U0RB
U1RB
U2RB
U3RB
03AF16, 03AE16
036F16, 036E16
033F16, 033E16
032F16, 032E16
Function
(clock synchronous
serial I/O mode)
Function
(UART mode)
Bit Name
Bit Symbol
R W
Receive data
Receive data
Receive data (9th bit)
Nothing is assigned. Write “0” when writing to these bits.
The values are indeterminate when read.
Arbitration lost
detecting flag (Note 1) 1 : Detected
0 : Not detected
Invalid
ABT
OER
FER
PER
SUM
0 : No overrun error
1 : Overrun error
Overrun error flag
(Note 2)
0 : No overrun error
1 : Overrun error
0 : No framing error
1 : Framing error
Framing error flag
(Note 2)
Invalid
Invalid
Invalid
Parity error flag
(Note 2)
0 : No parity error
1 : Parity error
Error sum flag
(Note 2)
0 : No error
1 : Error
Note 1: Always write “0”.
Note 2: Bits 15 to 12 are set to “0000
2
” when the serial I/O mode select bit (bits 0 to 2 at
” or the receive enable
addresses 03A816, 036816, 033816, 032816) are set to “000
2
bit is set to “0”. Bit 15 is set to “0” when all of bits 14 to 12 are set to “0”.
Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer
register (addresses 03AE16, 036E16, 033E16, 032E16) is read.
Figure 2.4.3. UARTi-related registers (1)
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2. UART
UARTi bit rate generator (o=0 to 3) (Note 1, 2)
Symbol
U0BRG
U1BRG
U2BRG
U3BRG
Address
03A916
036916
033916
032916
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
b7
b0
R W
Function
Values that can be set
0016 to FF16
Assuming that set value = n, BRGi divides the count source by
n + 1
Note 1: Use MOV instruction to write to this register.
Note 2: Write a value to this register while transmit/receive halts.
UARTi transmit/receive mode register (i = 0 to 3)
Symbol
U0MR
U1MR
U2MR
U3MR
Address
03A816
036816
033816
032816
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
0016
0016
0016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
b2 b1 b0
Must be fixed to 001
b2 b1 b0
SMD0
SMD1
Serial I/O mode select bit
(Note 3)
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Serial I/O mode
0 1 1 : I2C mode
Inhibited except in cases
listed above
Inhibited except in cases
listed above
SMD2
Internal/external clock
select bit
0 : Internal clock
1 : External clock (Note 1)
0 : Internal clock
1 : External clock (Note 1)
CKDIR
STPS
0 : One stop bit
1 : Two stop bits
Stop bit length select bit
Invalid
Valid when bit 6 = “1”
0 : Odd parity
PRY
Odd/even parity select bit Invalid
1 : Even parity
0 : Parity disabled
1 : Parity enabled
PRYE
SLEP
Parity enable bit
Invalid
TxD, RxD input/output
polarity switch bit (Note 2)
0 : Normal
1 : Reversed
Note 1: When I2C bus interface mode is selected, set the port direction register for the corresponding port
(SCLi) to 0, or the port direction register to 1 and the port data register to 1. When a mode other than
serial I/O mode is selected, set the port direction register for the corresponding port (CLKi) to 0.
Note 2: Normally set to “0”.
Note 3: Set the RxDi pin's port direction register to “0” when receiving.
Figure 2.4.4. UARTi-related registers (2)
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2. UART
UARTi transmit/receive control register 0 (i=0 to 3)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC0 (i=0 to 3)
Address
When reset
0816
03AC16, 036C16, 033C16, 032C16
,
Function
(During clock synchronous
serial I/O mode)
b1 b0
Bit
symbol
Function
(During UART mode)
R W
Bit name
b1 b0
CLK0
BRG count source
select bit
0 0 : f
0 1 : f
1
8
is selected
is selected
0 0 : f
0 1 : f
1
8
is selected
is selected
1 0 : f32 is selected
1 1 : Inhibited
1 0 : f32 is selected
1 1 : Inhibited
CLK1
CRS
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 4)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 4)
CTS/RTS function
select bit
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
TXEPT Transmit register empty
flag
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
CRD
CTS/RTS disable bit
Data output select bit
0 : TxDi/SDAi and SCLi pin is CMOS 0 : TxDi/SDAi and SCLi pin is CMOS
NCH
(Note 2)
output
output
1 : TxDi/SDAi and SCLi pin is
N-channel open drain output
1 : TxDi/SDAi and SCLi pin is
N-channel open drain output
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
Set to “0”
CKPOL CLK polarity select bit
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
Transfer format select bit
UFORM
0 : LSB first
1 : MSB first
0 : LSB first
1 : MSB first
(Note 3)
Note 1: Set the corresponding port direction register to “0”.
Note 2: UART2 transfer pin (TxD : P7 and SCL2: P7 ) is N-channel open drain output.
It cannot be set to CMOS output.
2
0
1
Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.
Note 4: The corresponding port register and port direction register are invalid.
UARTi transmit/receive control register 1 (i= 0 to 3)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC1 (i=0 to 3)
Address
When reset
0216
03AD16, 036D16, 033D16, 032D16
Function
(clock synchronous
serial I/O mode)
Function
(UART mode)
Bit Symbol
Bit Name
R W
0 : Transmit disabled
1 : Transmit enabled
Transmit enable
bit
TE
TI
Transmit buffer
empty flag
0 : Data present in transmit buffer register
1 : No data present in transmit buffer register
0 : Receive disabled
1 : Receive enabled
Receive enable
bit
RE
0 : Data packet in receive buffer register
1 : No data packet in receive buffer register
Receive
complete flag
RI
UARTi transmit
interrupt cause
select bit
0 : Transmit buffer empty (TI =1)
1 : Transmit buffer completed ( TXEPT =1)
UiIRS
0 : Continuous receive
UARTi continuous
receive mode
enable bit
mode disabled
1 : Continuous receive
mode enabled
Set to “0”
UiRRM
0 : No reverse
1 : Reverse
Data logic
select bit
UiLCH
UiERE
Set to “0”
The value is
indeterminate when read.
0 : Output disabled
1 : Output enabled
(Note 1)
Error signal
output enable bit
Note 1: When disabling the error signal output, set the UiERE bit to “0” after setting the
UiMR register.
Figure 2.4.5. UARTi-related registers (3)
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2. UART
Interrupt request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR
Address
035F16,
When reset
0016
Bit Symbol
Bit name
Function
R W
INT0 interrupt polarity
swiching bit
0 : One edge
1 : Two edges
IFSR0
IFSR1
IFSR2
INT1 interrupt polarity
swiching bit
0 : One edge
1 : Two edges
INT2 interrupt polarity
swiching bit
0 : One edge
1 : Two edges
Nothing is assigned.
Write “0” when writing to this bit. The value is indeterminate when read.
0 : UART0 Bus collision /
Start/stop condition detection /
Trouble error detection
1 : UART2 Bus collision /
Start/stop condition detection /
Trouble error detection
Bus collision interrupt
request cause select bit 0
IFSR6
IFSR7
Bus collision interrupt
request cause select bit 1
0 : UART1 Bus collision /
Start/stop condition detection /
Trouble error detection
1 : UART3 Bus collision /
Start/stop condition detection /
Trouble error detection
Figure 2.4.6. UARTi-related registers (4)
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2. UART
2.4.2 Operation of Serial I/O (transmission in UART mode)
In transmitting data in UART mode, choose functions from those listed in Table 2.4.4. Operations of the
circled items are described below. Figure 2.4.7 shows the operation timing, and Figures 2.4.8 and 2.4.9
show the set-up procedures.
Table 2.4.4. Choosed functions
Item
Set-up
Item
Set-up
No reverse
Data logic select
function
Transfer clock
source
O
O
O
O
Internal clock (f1 / f8 / f32)
External clock (CLKi pin)
CTS function enabled
Reverse
No reverse
TXD, RXD I/O
polarity reverse bit
CTS function
Reverse
CTS function disabled
Transmission
interrupt factor
Bus collision
detection function
Transmission buffer empty
Not selected
Selected
O
O
Transmission complete
Operation
(1) Setting the transmit enable bit to “1” and writing transmission data to the UARTi transmit
buffer register readies the data transmissible status.
________
________
(2) When input to the CTSi pin goes to “L”, transmission starts (the CTSi pin needs to be con-
trolled on the reception side).
(3) Transmission data held in the UARTi transmit buffer register is transmitted to the UARTi
transmit register. At this time, the first bit (the start bit) of the transmission data is transmitted
from the TxDi pin. Then, data is transmitted, bit by bit, in sequence: LSB, ····, MSB, parity bit,
and stop bit(s).
(4) When the stop bit(s) is (are) transmitted, the transmit register empty flag goes to “1”, which
indicates that transmission is completed. At this time, the UARTi transmit interrupt request bit
goes to “1”. The transfer clock stops at “H” level.
(5) If the transmission condition of the next data is ready when transmission is completed, a start
bit is generated following to stop bit(s), and the next data is transmitted.
_______
Note
• Set CTSi pin's port direction register to “0”.
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2. UART
Example of wiring
(Note)
Microcomputer
Receiver side IC
TX
Di
RXD
CTSi
Port
Note: Since T
XD
2
pin is N-channel open drain,
this pin needs pull-up resistance.
Example of operation
When confirming stop bit, stopped transfer clock once because CTS = “H”
Started transfer clock again to start transmitting immediately after confirming CTS = “L”
Tc
Transfer clock
(1) Transmission enabled
(2) Confirme CTS
(4) Confirme stop bit
(5) Start transmission
(3) Start transmission
“1”
“0”
“1”
Transmit
enable bit (TE)
Data is set in UARTi transmit buffer register
Transmit buffer
empty flag (Tl)
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
“H”
“L”
CTSi
Stopped pulsing because transfer enable bit = “0”
Parity Stop
Start
bit
bit
bit
TxDi
ST
D0
D1
ST
D0
D1
D2
D3
D4
D5
D7
P
ST
D0
D1
D2
D3
D4
D5
D7
P
D6
SP
D6
SP
Transmit
register empty
flag (TXEPT)
“1”
“0”
Transmit
interrupt request
bit (IR)
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f
1
, f8, f32)
• One stop bit.
f
EXT : frequency of BRGi count source (external clock)
• CTS function is selected.
• Transmit interrupt cause select bit = “1”.
n : value set to BRGi
Figure 2.4.7. Operation timing of transmission in UART mode
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2. UART
Setting UARTi transmit/receive mode register (i=0 to 3)
b7
b0
UARTi transmit/receive mode register
UiMR [Address 03A816, 36816, 033816, 32816
0 1 0 0 0 1 0 1
]
Serial I/O mode select bit
b2 b1 b0
1 0 1 : Transfer data 8 bits long
Internal/external clock select bit
0 : Internal clock
Stop bit length select bit
0 : One stop bit
Odd/even parity select bit(Valid when bit 6 = “1”)
0 : Odd parity
Parity enable bit
1 : Parity enabled
TX
D, RXD I/O polarity reverse bit
Usually set to “0”
Setting UARTi transmit/receive control register 0 (i=0 to 3)
b7
0 0
b0 UARTi transmit/receive control register 0
UiC0 [Address 03AC16, 36C16, 033C16, 32C16
]
0
0
BRG count source select bit
b1 b0
0 0 : f
0 1 : f
1
8
is selected
is selected
1 0 : f32 is selected
1 1 : Inhibited
CTS/RTS function select bit
(Valid when bit 4 = “0”)
0 : CTS function is selected (Note 1)
Transmit register empty flag
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
CTS/RTS disable bit
0 : CTS/RTS function enabled
Data output select bit (Note 2)
0 : TxDi/SDAi and SCLi pin is CMOS output
1 : TxDi/SDAi and SCLi pin is N-channel open drain output
Must be fixed to "0" in UART mode
Transfer format select bit
0 : LSB first
Note 1: Set the corresponding port direction register to “0”.
Note 2: UART2 transfer pin (TxD2: P7 and SCL2: P7 ) is N-channel open drain output.
It cannot be set to CMOS output.
0
1
Setting UART transmit/receive control register 1 (i=0 to 3)
b7
0
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
0
0
]
Must be fixed to "0" in UART mode
Data logic select bit
0 : No reverse
Error signal output enable bit (in UART mode)
0 : Output disabled
Continued to the next page
Figure 2.4.8. Set-up procedure of transmission in UART mode (1)
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2. UART
Continued from the previous page
Setting UARTi bit rate generator (i = 0 to 3)
b7
b0
UARTi bit rate generator [Address 03A916, 036916, 033916, 032916,]
UiBRG (i = 0 to 3)
Can be set to 0016 to FF16 (Note)
Note: Use MOV instruction to write to this register.
Write to UARTi bit rate generator when transmission/reception is halted.
Transmission enabled
b7
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
1
]
Transmit enable bit
1 : Transmission enabled
Writing transmit data (Note)
(b15
b7
(b8)
b0
UART0 transmit buffer register [Address 03AB16, 03AA16] U0TB
UART1 transmit buffer register [Address 036B16, 036A16] U1TB
UART2 transmit buffer register [Address 033B16, 033A16] U2TB
UART3 transmit buffer register [Address 032B16, 032A16] U3TB
b7
b0
Setting transmission data
Setting transmission data (9th bit)
Note: Use MOV instruction to write to this register.
When CTSi input level = “L”
Start transmission
Checking the status of UARTi transmit buffer register (i = 0 to 3)
b7
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
]
Transmit buffer empty flag
0 : Data present in transmit buffer register
1 : No data present in transmit buffer register (Writing next transmit data enabled)
When transmitting continuously
Writing next transmit data (Note)
(b15)
b7
(b8)
b0
UART0 transmit buffer register [Address 03AB16, 03AA16] U0TB
UART1 transmit buffer register [Address 036B16, 036A16] U1TB
UART2 transmit buffer register [Address 033B16, 033A16] U2TB
UART3 transmit buffer register [Address 032B16, 032A16] U3TB
b7
b0
Setting transmission data
Note: Use MOV instruction to write to this register.
Transmission is complete
Figure 2.4.9. Set-up procedure of transmission in UART mode (2)
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2. UART
2.4.3 Operation of Serial I/O (reception in UART mode)
In receiving data in UART mode, choose functions from those listed in Table 2.4.5. Operations of the
circled items are described below. Figure 2.4.10 shows the operation timing, and Figures 2.4.11 and
2.4.12 show the set-up procedures.
Table 2.4.5. Choosed functions
Item
Set-up
Item
D I/O
Set-up
No reverse
Transfer clock
source
O
O
O
Internal clock (f1 / f8 / f32)
O
O
TXD, RX
polarity reverse bit
External clock (CLKi pin)
Reverse
Bus collision
detection function
RTS function
RTS function enabled
RTS function disabled
No reverse
Not selected
Selected
Data logic select
function
Reverse
Operation
(1) Setting the receive enable bit to “1” readies data-receivable status. At this time, output from
________
the RTSi pin goes to “L” level to inform the transmission side that the receivable status is
ready.
(2) When the first bit (the start bit) of reception data is received from the RxDi pin, output from the
_______
RTS goes to “H” level. Then, data is received, bit by bit, in sequence: LSB, ····, MSB, and stop
bit(s).
(3) When the stop bit(s) is (are) received, the content of the UARTi receive register is transmitted
to the UARTi receive buffer register. At this time, the receive complete flag goes to “1” to
indicate that the reception is completed, the UARTi receive interrupt request bit goes to “1”,
_______
and output from the RTS pin goes to “L” level.
(4) The receive complete flag goes to “0” when the lower-order byte of the UARTi buffer register
is read.
Note
• Set RxDi pin's port direction register to “0”.
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2. UART
Example of wiring
Microcomputer
Transmitter side IC
RXDi
RTSi
TXD
Port
Example of operation
(4) Data is
read
(1) Reception enabled
(2) Start reception
(3) Receiving is
completed
BRGi's count
source
“1”
“0”
Receive enable
bit
Start bit
Sampled “L”
RxD
i
D
1
D7
D0
Stop bit
Receive data taken in
Transfer clock
Reception started when transfer
clock is generated by falling edge
of start bit
Transferred from UARTi receive register
to UARTi receive buffer register
Receive
complete flag
“1”
“0”
“H”
“L”
RTS
i
Becomes “L” by reading the receive buffer
Receive interrupt
request bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Timing of transfer data 8 bits long applies to the following settings :
•Transfer data length is 8 bits.
•Parity is disabled.
•One stop bit
•RTS function is selected.
Figure 2.4.10. Operation timing of reception in UART mode
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2. UART
Setting UARTi transmit/receive mode register (i=0 to 3)
b7
b0
UARTi transmit/receive mode register
UiMR [Address 03A816, 36816, 033816, 32816]
0 0
0 0 1 0 1
Serial I/O mode select bit (Note)
b2 b1 b0
1 0 1 : Transfer data 8 bits long
Internal/external clock select bit
0 : Internal clock
Stop bit length select bit
0 : One stop bit
Valid when bit 6 = “1”
Parity enable bit
0 : Parity disabled
TXD, RXD I/O polarity reverse bit
Usually set to “0”
Note: Set the RxDi pin's port direction register to “0” when receiving.
Setting UARTi transmit/receive control register 0 (i=0 to 3)
b7
b0 UARTi transmit/receive control register 0
UiC0 [Address 03AC16, 36C16, 033C16, 32C16]
0 0 0 0
1
BRG count source select bit
b1 b0
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
CTS/RTS function select bit
(Valid when bit 4 = “0”)
1 : RTS function is selected
Transmit register empty flag
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
CTS/RTS disable bit
0 : CTS/RTS function enabled
Data output select bit (Note)
0 : TxDi/SDAi and SCLi pin is CMOS output
1 : TxDi/SDAi and SCLi pin is N-channel open drain output
Must be fixed to “0” in UART mode
Transfer format select bit
0 : LSB first
Note: UART2 transfer pin (TxD2: P70 and SCL2: P71) is N-channel open drain output.
It cannot be set to CMOS output.
Setting UART transmit/receive control register 1 (i=0 to 3)
b7
0
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16]
0
0
Must be fixed to “0” in UART mode
Data logic select bit
0 : No reverse
Error signal output enable bit (in UART mode)
0 : Output disabled
Continued to the next page
Figure 2.4.11. Set-up procedure of reception in UART mode (1)
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2. UART
Continued from the previous page
Setting UARTi bit rate generator (i = 0 to 3)
b7
b0
UARTi bit rate generator [Address 03A916, 036916, 033916, 032916,]
UiBRG (i = 0 to 3)
Can be set to 0016 to FF16 (Note)
Note: Use MOV instruction to write to this register.
Write to UARTi bit rate generator when transmission/reception is halted.
Reception enabled
b7
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
]
1
Receive enable bit
1 : Reception enabled (Note)
Note: Set RXD pin's port direction register to “0”.
Start reception
Checking completion of data reception
b7
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
]
Receive complete flag
0 : No data present in receive buffer register
1 : Data present in receive buffer register
Checking error
(b15)
b7
(b8)
b0
UART0 receive buffer register [Address 03AF16, 03AE16] U0RB
UART1 receive buffer register [Address 036F16, 036E16] U1RB
UART2 receive buffer register [Address 033F16, 033E16] U2RB
UART3 receive buffer register [Address 032F16, 032E16] U3RB
b7
b0
Received data
Invalid in UART mode
Overrun error flag
0 : No overrun error
1 : Overrun error found
Framing error flag
0 : No framing error
1 : Framing error found
Parity error flag
0 : No parity error
1 : Parity error found
Error sum flag
0 : No error
1 : Error found
Processing after reading out received data
Figure 2.4.12. Set-up procedure of reception in UART mode (2)
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2. UART
2.4.4 Serial I/O Precautions (UART Mode)
Description When the level of the CLKi and CTSi pins goes to “H” (Note 1), if the UiMR register is set to
any of the following, the UiERE bit in the UiC1 register is set to “1” (parity error signal output
enabled). When the PRYE bit in the UiMR register is set to “1” while the UiERE bit is “1”
(parity error signal output enabled), the TXDi pin outputs “L” level if a parity error occurs
while receiving data. To prevent this, set the UiERE bit after setting the UiMR register.
• Change the setting of bits SMD2 to SMD0 from “0002” (serial I/O disabled) to “1012”
(UART mode transfer data length 8 bits).
• Change the setting of bits SMD2 to SMD0 from “0012” (clock synchronous serial I/O mode)
to “1002” (UART mode transfer data length 7 bits).
• Change the setting of bits SMD2 to SMD0 from “0012” (clock synchronous serial I/O mode)
to “1012” (UART mode transfer data length 8 bits).
• Change the setting of bits SMD2 to SMD0 from “0012” (clock synchronous serial I/O mode)
to “1102” (UART mode transfer data length 9 bits).
2
• Change the setting of bits SMD2 to SMD0 from “0102” (I C mode) to “1012” (UART mode
transfer data length 8 bits).
Note 1: If the pins are not used as CLKi or CTSi, these conditions apply when the pin level
goes to “H”.
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2. SIM interface
2.4.5 Operation of Serial I/O (transmission used for SIM interface)
In transmitting data in UARTi (i=0 to 3) mode (used for SIM interface), choose functions from those listed
in Table 2.4.6. Operations of the circled items are described below. Figure 2.4.13 shows the operation
timing, and Figures 2.4.14 and 2.4.15 show the set-up procedures.
Table 2.4.6. Choosed functions
Item
Set-up
Item
Set-up
Transfer data
format
Transfer clock
source
Direct format
Internal clock (f1/f8/f32)
O
O
Inverse format
External clock (CLKi pin)
Operation (1) Setting the transmit enable bit and receive enable bit to “1” and writing transmission data to
the UARTi (i=0 to 3) transmit buffer register readies the data transmissible status. Set UARTi
(i=0 to 3) transfer interrupt for being enabled.
(2) Transmission data held in the UARTi (i=0 to 3) transmit buffer register is transmitted to the
UARTi (i=0 to 3) transmit register. At this time, the first bit (the start bit) of the transmission
data is transmitted from the TxDi (i=0 to 3) pin. Then, data is transmitted, bit by bit, in se-
quence: LSB, ····, MSB, parity bit, and stop bit(s).
(3) When the stop bit(s) is (are) transmitted, the transmit register empty flag goes to “1”, which
indicates that transmission is completed. At this time, the UARTi (i=0 to 3) transmit interrupt
request bit goes to “1”. The transfer clock stops at “H” level.
(4) If the transmission condition of the next data is ready when transmission is completed, a start
bit is generated following to stop bit(s), and the next data is transmitted.
(5) If a parity error occurs, an L is output from the SIM card, and the RxDi (i=0 to 3) terminal turns
to "L" level. Check the RxDi (i=0 to 3) terminal's level within the UARTi (i=0 to 3) transmission
interrupt routine, and if it is found to be at the "L" level, then handle the error.
Note
• The parity error level is determined within a UARTi (i=0 to 3) transmission interrupt. When a
transmission interrupt request occurs, set the priority level of the transmission interrupt higher
than those of other interrupts so that the interrupt routine can be immediately carried out.
Either in the main routine or in an interrupt routine, the interrupt inhibition time has to be made
as short as possible.
• Set the RxDi (i=0 to 3) pin's port direction register to input.
• Select N-channel open drain output for TxDi pin with data output select bit of UARTi (i=0 to 3)
transmit/receive control register 0.
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2. SIM interface
Example of wiring
(Note1)
Microcomputer
SIM card
TxDi
RxDi
Note1: TxDi pin is N-channel open drain and needs a pull-up resistance.
Note2: i=0 to 3
Example of operation (when direct format)
(1) Transmission enabled
(3) Confirm stop bit
(4) Start transmission
(5) Dispose
parity error
(2) Start transmission
Tc
Transfer clock
“1”
Transmit
(Note 1)
enable bit (TE)
“0”
“1”
Data is set in UARTi transmit buffer register
Transmit buffer
empty flag (Tl)
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
Parity Stop
Start
bit
bit
bit
T
X
D
i
(Note 2)
ST
D
0
D
2
D
3
D
7
P
ST
D
0
D
2
D
3
D
7
P
D
1
1
D
4
D
5
D
6
SP
D
1
D
4
D
5
D6
SP
RXDi (Note 2)
Since a parity error occurred, the
“L” level returns from SIM card
Signal line level
(Note 2)
SP
ST
D
0
D
D2
D3
D
4
D7
P
ST
D0
D1
D2
D3
D4
D7
P
D5
D6
SP
D5
D6
Detects the level
using an interrupt
routine
Detects the level
using an interrupt
routine
Transmit buffer
empty flag
(TEXPT)
“1”
“0”
“1”
“0”
Transmit
interrupt request
bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
fi : frequency of BRGi count source (f1, f8, f32)
f
EXT : frequency of BRGi count source (external clock)
n : value set to BRGi
• Transmit interrupt cause select bit = “1”.
Note 1: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Note 2: TxD and RxD are connected in the manner of wired OR as shown in the connection diagram. Therefore, the signal levels of
TxDi and RxDi should be the same, but the output signals are shown separately for ease of understanding. Also, the signal
level resulting from connecting TxD and RxD is shown as a signal line level.
Note 3: i = 0 to 3
i
i
i
i
Figure 2.4.13. Operation timing of transmission in UART mode (used for SIM interface)
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2. SIM interface
Setting UARTi transmit/receive mode register (i=0 to 3)
b7
b0
UARTi transmit/receive mode register
UiMR [Address 03A816, 36816, 033816, 32816
0 1 1 0 0 1 0 1
]
Serial I/O mode select bit
b2 b1 b0
1 0 1 : Transfer data 8 bits long
Internal/external clock select bit
0 : Internal clock
Stop bit length select bit
0 : One stop bit
Odd/even parity select bit(Valid when bit 6 = “1”)
Must be “1” (even parity) in direct format
Parity enable bit
1 : Parity enabled
TX
D, RXD I/O polarity reverse bit
Usually set to “0”
Setting UARTi transmit/receive control register 0 (i=0 to 3)
b7
b0
UARTi transmit/receive control register 0
UiC0 [Address 03AC16, 36C16, 033C16, 32C16
0 0 1 1
]
BRG count source select bit
b1 b0
0 0 : f
1
8
is selected
is selected
0 1 : f
1 0 : f32 is selected
1 1 : Inhibited
Valid when bit 4 = “0”
Transmit register empty flag
0 : Data present in transmit register (during transmission)
1 : No data present in transmit register (transmission completed)
CTS/RTS disable bit
1 : CTS/RTS function disabled
Data output select bit
1 : TxDi/SDAi and SCLi pin is N-channel open drain output
Must be fixed to “0” in UART mode
Transfer format select bit
Must be “0” (LSB first) in direct format
Setting UART transmit/receive control register 1 (i=0 to 3)
b7
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
1 0 0 1
]
UARTi transmit interrupt cause select bit
1 : Transmission completed (TXEPT = 1)
Must be fixed to “0” in UART mode
Data logic select bit
Must be “0” (no reverse) in direct format
Error signal output enable bit (in UART mode)
1 : Output enabled
Continued to the next page
Figure 2.4.14. Set-up procedure of transmission in UART mode (used for SIM interface) (1)
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2. SIM interface
Continued from the previous page
Setting UARTi bit rate generator (i = 0 to 3)
b7
b0
UARTi bit rate generator [Address 03A916, 036916, 033916, 032916,]
UiBRG (i = 0 to 3)
Can be set to 0016 to FF16 (Note)
Note: Use MOV instruction to write to this register.
Write to UARTi bit rate generator when transmission/reception is halted.
Transmission enabled
b7
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
]
1
1
Transmit enable bit
1 : Transmission enabled
Receive enable bit
1 : Reception enabled (Note)
Note: Set RXD pin's port direction register to “0”.
Writing transmit data (Note)
(b15
b7
(b8)
b0
UART0 transmit buffer register [Address 03AB16, 03AA16] U0TB
UART1 transmit buffer register [Address 036B16, 036A16] U1TB
UART2 transmit buffer register [Address 033B16, 033A16] U2TB
UART3 transmit buffer register [Address 032B16, 032A16] U3TB
b7
b0
Setting transmission data
Note: Use MOV instruction to write to this register.
UARTi transmit interrupt
Confirm RxDi pin level
b7
b0
b7
b0
Port P7 register [Address 03ED16
P7
]
Port P6 register [Address 03EC16
P6
]
Port P7
0 : “L” level
1 : “H” level
1
register (RxD
2
pin)
Port P6
0 : “L” level
1 : “H” level
Port P66 register (RxD
0 : “L” level
1 : “H” level
2
register (RxD
0
pin)
pin)
Port P75 register (RxD3
0 : “L” level
1 : “H” level
pin)
1
REIT instruction
Figure 2.4.15. Set-up procedure of transmission in UART mode (used for SIM interface) (2)
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2. SIM interface
2.4.6 Operation of Serial I/O (reception used for SIM interface)
In receiving data in UARTi (i=0 to 3) mode (used for SIM interface), choose functions from those listed in
Table 2.4.7. Operations of the circled items are described below. Figure 2.4.16 shows the operation
timing, and Figures 2.4.17 to 2.4.18 show the set-up procedures.
Table 2.4.7. Choosed functions
Item
Set-up
Item
Set-up
Direct format
Internal clock (f1/f8/f32)
Transfer data
format
Transfer clock
source
O
O
Inverse format
External clock (CLKi pin)
Operation (1) Setting the transmit enable bit and receive enable bit to “1” readies data-receivable status.
(2) When the first bit (the start bit) of reception data is received from the RxDi (i=0 to 3) pin, data
is received, bit by bit, in sequence: LSB, ····, MSB, and stop bit(s).
(3) When the stop bit(s) is (are) received, the content of the UARTi (i=0 to 3) receive register is
transmitted to the UARTi (i=0 to 3) receive buffer register.
At this time, the receive complete flag goes to “1” to indicate that the reception is completed,
and the UARTi (i=0 to 3) receive interrupt request bit goes to “1”.
(4) The receive complete flag goes to “0” when the lower-order byte of the UARTi (i=0 to 3) buffer
register is read.
(5) When the parity error is occurred, TXDi (i=0 to 3) pin goes to “L” level.
Note
• Set the RxDi and CLKi pins' port direction register to “0”.
• Select N-channel open drain output for TxDi (i=0 to 3) pin with data output select bit of UARTi
(i=0 to 3) transmit/receive control register 0.
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2. SIM interface
Example of wiring
(Note)
Microcomputer
SIM card
TxD
i
RxD
i
i
CLK
External clock
Note1: TxDi pin is N-channel open drain and needs a pull-up resistance.
Note2: i=0 to 3
Example of operation (when inversed format)
(1) Reception enabled
(2) Start reception
Tc
(3) Receiving is completed
(4) Data is read
(5) Parity error occurred
Transfer clock
“1”
Receive enable
bit(RE)
“0”
Parity
bit
Stop
bit
Start
bit
R
X
D
i
(Note)
(Note)
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
ST D0
D2 D3
D7
P
P
SP
D1
D4 D5 D6
TXDi
Since a parity error occurred, the
“L” level returns from TxD
i
SP
Signal line level
(Note)
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
“1”
“0”
Receive
complete flag(RI)
Read to receive buffer
“1”
“0”
Receive interrupt
request bit(IR)
Read to receive buffer
Cleared to “0” when interrupt request is accepted, or cleared by software
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
fi : frequency of BRGi count source (f1, f8, f32)
f
EXT : frequency of BRGi count source (external clock)
n : value set to BRGi
• Transmit interrupt cause select bit = “1”.
Note : TxD
become the same signal from the logical standpoint, but the output signals turn complex, so they are shown separately. Also,
the signal level resulting from connecting TxD and RxD is shown as a signal line level.
i and RxDi are connected in the manner of wired OR as shown in the connection diagram. So TxDi and RxDi ought to
i
i
Figure 2.4.16. Operation timing of reception in UART mode (used for SIM interface)
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2. SIM interface
Setting UARTi transmit/receive mode register (i=0 to 3)
b7
b0
UARTi transmit/receive mode register
UiMR [Address 03A816, 36816, 033816, 32816
0 1 0 0 1 1 0 1
]
Serial I/O mode select bit (Note 1)
b2 b1 b0
1 0 1 : Transfer data 8 bits long
Internal/external clock select bit
1 : External clock (Note 2)
Stop bit length select bit
0 : One stop bit
Odd/even parity select bit(Valid when bit 6 = “1”)
Must be "0" (odd parity) in inverse format
Parity enable bit
1 : Parity enabled
TX
D, RXD I/O polarity reverse bit
Usually set to “0”
Note 1: Set the RxDi pin's port direction register to “0” when receiving.
2: Set the corresponding port direction register to “0”.
Setting UARTi transmit/receive control register 0 (i=0 to 3)
b7
b0
UARTi transmit/receive control register 0
UiC0 [Address 03AC16, 36C16, 033C16, 32C16
1 0 1 1
]
BRG count source select bit
b1 b0
0 0 : f
1
8
is selected
is selected
0 1 : f
1 0 : f32 is selected
1 1 : Inhibited
Valid when bit 4 = “0”
Transmit register empty flag
0 : Data present in transmit register (during transmission)
1 : No data present in transmit register (transmission completed)
CTS/RTS disable bit
1 : CTS/RTS function disabled
Data output select bit
1 : TxDi/SDAi and SCLi pin is N-channel open drain output
Must be fixed to “0” in UART mode
Transfer format select bit
Must be “1” (MSB first) in inverse format
Setting UART transmit/receive control register 1 (i=0 to 3)
b7
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
1
1 0 1
]
UARTi transmit interrupt cause select bit
1 : Transmission completed (TXEPT = 1)
Must be fixed to “0” in UART mode
Data logic select bit
Must be “1” (reverse) in inverse format
Error signal output enable bit (in UART mode)
1 : Output enabled
Continued to the next page
Figure 2.4.17. Set-up procedure of reception in UART mode (used for SIM interface) (1)
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2. SIM interface
Continued from the previous page
Setting UARTi bit rate generator (i = 0 to 3)
b7
b0
UARTi bit rate generator [Address 03A916, 036916, 033916, 032916,]
UiBRG (i = 0 to 3)
Can be set to 0016 to FF16 (Note)
Note: Use MOV instruction to write to this register.
Write to UARTi bit rate generator when transmission/reception is halted.
Reception enabled
b7
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
]
1
1
Transmit enable bit
1 : Transmission enabled
Receive enable bit
1 : Reception enabled (Note)
Note: Set RXD pin's port direction register to “0”.
Start reception
Checking completion of data reception
b7
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
]
Receive complete flag
0 : No data present in receive buffer register
1 : Data present in receive buffer register
Checking error
(b15)
b7
(b8)
b0
UART0 receive buffer register [Address 03AF16, 03AE16] U0RB
UART1 receive buffer register [Address 036F16, 036E16] U1RB
UART2 receive buffer register [Address 033F16, 033E16] U2RB
UART3 receive buffer register [Address 032F16, 032E16] U3RB
b7
b0
Received data
Invalid in UART mode
Overrun error flag
0 : No overrun error
1 : Overrun error found
Framing error flag
0 : No framing error
1 : Framing error found
Parity error flag
0 : No parity error
1 : Parity error found
Error sum flag
0 : No error
1 : Error found
Processing after reading out received data
Figure 2.4.18. Set-up procedure of reception in UART mode (used for SIM interface)(2)
Rev.2.00 Oct 16, 2006 page 80 of 354
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M30245 Group
2. SIM interface
2.4.7 Clock Signals in used for the SIM Interface
In conforming to the SIM interface, the UART clock signal within the SIM card needs to conform to the
UARTi (i=0 to 3) clock signal within the microprocessor. Two examples are given here as means of
generating a UARTi clock signal within the microprocessor.
* In the case of setting a value equal to or less than (1/256 X 1/16) in the division rate of UARTi clock
Choose f1 for the UART’s source clock signal and set an optional value in the bit rate generator.
* In the case of setting a value equal to or greater than (1/256 X 1/16) in the division rate of UARTi clock
Set the bit rate generator to “0”, turn the source clock signal to timer output and set an optional value
in the timer.
Let F be the clock signal within the SIM card and D be the bit rate adjustment factor, then the formula for
the UART clock signal becomes as follows. Figure 2.4.19 shows an example of connection.
• In the case of setting a value equal to or less than (1/256 X 1/16) in the division rate of UARTi clock
UARTi clock signal within microprocessor = UART clock within SIM card
1
1
1
1
f1 x
x
= f1
x
x flip-flop x
F/D
Bit rate generator + 1
16
Timer Aj counter + 1
Let XIN = 16 MHz, timer Aj counter = 1, F = 372, and D = 1, then the value to be set in the bit rate
generator becomes
1
1
1
2
1
1
16 x
x
=16 X
x
x
1 + 1
372/1
16
Bit rate generator + 1
Bit rate generator = 92
Table 2.4.8 shows an example of setting in the UARTi bit rate generator.
• In the case of setting a value equal to or greater than (1/256 X 1/16) in the division rate of UARTi clock
UARTi clock signal within microprocessor = UART clock within SIM card
1
1
1
f1 x
x
x
x
flip-flop
Timer Ak counter + 1
Bit rate generator + 1
16
1
1
= f1 x
x flip-flop x
F/D
Timer Aj counterr + 1
Let XIN= 16 MHz, timer Aj counter = 3, bit rate generator = 0, F = 1860, and D = 1, then the value to be
set in the timer Ak counter becomes
1
1
2
1
1
1
2
1
1
16 x
x
x
x
=16 x
x
x
0 + 1
16
Timer Ak counter + 1
1860/1
3 + 1
Timer Ak counter = 464
Table 2.4.9 shows an example of setting in the timer Ak counter.
Rev.2.00 Oct 16, 2006 page 81 of 354
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M30245 Group
2. SIM interface
Clock generator
M30245
XIN
SIM CARD
TAjOUT
TAkOUT
CLK
flip-flop
flip-flop
Timer Aj counter
Timer Ak counter
SIM card
internal clock
frequency
1
F/D
division ratio
f1
External clock
CLKi
UART clock
Bit rate generator
1/16
UART
UARTi clock
RxDi
TxDi
UART
Note : i=0 to 3
Figure 2.4.19. Example of connection
Rev.2.00 Oct 16, 2006 page 82 of 354
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M30245 Group
2. SIM interface
Table 2.4.8. UARTi bit rate adjustment factor (i=0 to 3)
UARTi bit
rate
generator
set value
UARTi bit
SIM card
internal clock
F(Hz)
SIM card
internal clock
F(Hz)
rate
generator
set value
Bit rate
D
Bit rate
D
F/D
F/D
1116
372
558
744
1
2
4
8
372
186
93
92
1116
1488
1860
1
2
4
8
558
279
16
1/2
1/4
1/8
1/16
1/32
1/64
1
16
1/2
1/4
1/8
1/16
1/32
1/64
1
744
185
371
2232
4464
8928
17856
35712
71424
1488
744
278
557
1488
2976
5952
11904
23808
558
743
1115
2231
4463
8927
1487
2975
5951
2
279
2
185
92
4
4
372
8
8
186
16
16
93
1/2
1/4
1/8
1/16
1/32
1/64
1
1116
2232
4464
8928
17856
35712
744
278
557
1/2
1/4
1/8
1/16
1/32
1/64
1
2976
5952
11904
23808
47616
95232
1860
930
371
743
1115
2231
4463
8927
185
1487
2975
5951
11903
2
372
92
2
4
186
4
465
8
93
8
16
16
1/2
1/4
1/8
1/16
1/32
1/64
1488
2976
371
743
1/2
1/4
1/8
1/16
1/32
3720
7440
464
929
5952
1487
2975
5951
11903
14880
29760
59520
1859
3719
7439
14879
11904
23808
47616
1/64 119040
Combination impossible to deal with due to the current specifications of M30245
Combination in which the F/D itself does not become an integer
Setting example under the following conditions.
f(XIN)=16 MHz
Timer Ak counter set value = 1
Rev.2.00 Oct 16, 2006 page 83 of 354
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M30245 Group
2. SIM interface
Table 2.4.9. TimerAi register adjustment factor
SIM card
internal clock
F(Hz)
SIM card
internal clock
F(Hz)
Bit rate
D
Timer Ai
value
Timer Aj
value
Bit rate
D
F/D
372
F/D
1116
372
558
744
1
2
4
8
92
1116
1488
1860
1
2
4
8
278
186
93
558
279
16
1/2
1/4
1/8
1/16
1/32
1/64
1
16
1/2
1/4
1/8
1/16
1/32
1/64
1
744
1488
2976
5952
11904
23808
558
185
371
2232
4464
8928
17856
35712
71424
1488
744
557
1115
2231
4463
8927
17855
371
743
1487
2975
5951
2
279
2
185
4
4
372
92
8
8
186
16
16
93
1/2
1/4
1/8
1/16
1/32
1/64
1
1116
2232
4464
8928
17856
35712
744
278
557
1/2
1/4
1/8
1/16
1/32
1/64
1
2976
5952
11904
23808
47616
95232
1860
930
743
1487
2975
5951
11903
23807
464
1115
2231
4463
8927
185
2
372
92
2
4
186
4
465
8
93
8
16
16
1/2
1/4
1/8
1/16
1/32
1/64
1488
2976
371
743
1/2
1/4
1/8
1/16
1/32
3720
7440
929
1859
5952
1487
2975
5951
11903
14880
29760
59520
3719
11904
23808
47616
7439
14879
29759
1/64 119040
Combination impossible to deal with due to the current specifications of M30245
Combination in which the F/D itself does not become an integer
Setting example under the following conditions.
f(XIN)=16 MHz
Timer Aj counter set value = 3, UARTi bit rate generator set value = 0
Rev.2.00 Oct 16, 2006 page 84 of 354
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M30245 Group
2. Serial Interface Special Function
2.5 Serial Interface Special Function
2.5.1 Overview
_____
Serial interface special function can control communications on the serial bus using SSi input pins. The
following is an overview of the serial interface special function.
(1) Transmission/reception format
8-bit data
(2) Transfer rate
If the internal clock is selected as the transfer clock, the divide-by-2 frequency, resulting from the bit
rate generator division, becomes the transfer rate. The bit rate generator count source can be se-
lected from the following: f1, f8, and f32. Clocks f1, f8, and f32 are derived by dividing the CPU’s main
clock by 1, 8, and 32 respectively.
Furthermore, if an external clock is selected as the transfer clock, the clock frequency input to the CLK
pin becomes the transfer rate.
(3) Error detection
Fault error can be detected in the master mode.
_____
When an “L” signal is input to an SSi pin in the multiple master system, it is judged there is another
master existed, and the TxDi, RxDi and CLKi pins all become high impedance. Moreover, the fault
error interrupt request bit becomes "1" and a fault error interrupt is generated.
(4) How to deal with an error
When the fault error flag is set to “0”, output is restored to the clock output and data output pins. In the
_____
_____
master mode, if an SSi input pin is H level, “0” can be written for the fault error flag. When an SSi input
pin is L level, “0” cannot be written for the fault error flag. In the slave mode, the “0” can be written for
_____
the fault error flag regardless of the input to the SSi input pins.
(5) Function selection
For serial interface special function, the following functions can be selected:
(a) Function for choosing CLK polarity
This function switches the CLK polarity of the transfer clock. The following operations are available:
• Data is input at the falling edge of the transfer clock, and is output at the rising edge.
• Data is input at the rising edge of the transfer clock, and is output at the falling edge.
(b) Function for setting clock phase
This function switches the phase of the transfer clock. Choose either of the following:
•Without clock delay
•With clock delay
(c) Function for setting serial input pin
This function switches the serial bus control privilege between the master mode and slave mode.
Choose either of the following:
• Master mode
• Slave mode
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M30245 Group
2. Serial Interface Special Function
Following are some examples in which various functions (a) through (c) are selected:
• Transmission Operation WITH: outputting transmission data at falling edge of transfer clock, no
clock delay, master mode
• Reception Operation WITH: inputting reception data at rising edge of transfer clock, clock delay,
master mode
• Transmission Operation WITH: outputting transmission data at falling edge of transfer clock, no
clock delay, slave mode
• Reception Operation WITH: inputting reception data at rising edge of transfer clock, clock delay,
slave mode
(6) Input to the serial interface special function and the direction register
To input an external signal to the serial interface special function, set the direction register of the
relevant port to input.
(7) Pins related to the serial interface special function
• CLK0, CLK1, CLK2, CLK3 pins
Input/output pins for the transfer clock
• RxD0/SRxD0, RxD1/SRxD1, RxD2/SRxD2, RxD3/SRxD3 pins
Input pins for data
• TxD0/STxD0, TxD1/STxD1, TxD2/STxD2, TxD3/STxD3 pins
Output pins for data
(8) Registers related to the serial I/O
Figure 2.5.1 shows the memory map of serial interface special function-related registers, and Figures
2.5.2 to 2.5.7 show serial interface special function-related registers.
Rev.2.00 Oct 16, 2006 page 86 of 354
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2. Serial Interface Special Function
004216
004316
UART2 receive/ACK interrupt control register (S2RIC)
UART1/3 Bus collision interrupt control register (S13BCNIC)
035F
16
Interrupt cause select register (IFSR)
004816
004916
004A16
UART1 receive/ACK/SSI1 interrupt control register (S1RIC)
UART0/2 Bus collision interrupt control register (S02BCNIC)
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
UART1 special mode register 4 (U1SMR4)
UART1 special mode register 3 (U1SMR3)
UART0 receive/ACK/SSI0 interrupt control register (S0RIC)
UART1 special mode register 2 (U1SMR2)
UART1 special mode register 1 (U1SMR)
UART1 transmit / receive mode register (U1MR)
004D16
004F16
005116
005316
005516
UART3 transmit/NACK interrupt control register (S3TIC)
UART2 transmit/NACK interrupt control register (S2TIC)
UART1 bit rate generator (U1BRG)
UART1 transmit buffer register (U1TB)
UART1 transmit / receive control register 0 (U1C0)
UART1 transmit / receive control register 1 (U1C1)
UART1 transmit/NACK/SSI1 interrupt control register (S1TIC)
UART0 transmit/NACK/SSI0 interrupt control register (S0TIC)
UART3 receive/ACK interrupt control register (S3RIC)
UART1 receive buffer register (U1RB)
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
UART0 special mode register 4 (U0SMR4)
UART0 special mode register 3 (U0SMR3)
032416
032516
032616
032716
032816
032916
032A16
032B16
UART3 special mode register 4 (U3SMR4)
UART3 special mode register 3 (U3SMR3)
UART0 special mode register 2 (U0SMR2)
UART0 special mode register 1 (U0SMR)
UART0 transmit / receive mode register (U0MR)
UART3 special mode register 2 (U3SMR2)
UART3 special mode register 1 (U3SMR)
UART3 transmit / receive mode register (U3MR)
UART0 bit rate generator (U0BRG)
UART0 transmit buffer register (U0TB)
UART3 bit rate generator (U3BRG)
UART3 transmit buffer register (U3TB)
UART0 transmit / receive control register 0 (U0C0)
UART0 transmit / receive control register 1 (U0C1)
UART3 transmit / receive control register 0 (U3C0)
UART3 transmit / receive control register 1 (U3C1)
032C16
032D16
UART0 receive buffer register (U0RB)
032E16
032F16
UART3 receive buffer register (U3RB)
0334
16
UART2 special mode register 4 (U2SMR4)
UART2 special mode register 3 (U2SMR3)
0335
0336
0337
0338
0339
16
16
16
16
16
UART2 special mode register 2 (U2SMR2)
UART2 special mode register 1 (U2SMR)
UART2 transmit / receive mode register (U2MR)
UART2 bit rate generator (U2BRG)
UART2 transmit buffer register (U2TB)
033A
033B
16
16
033C
033D
UART2 transmit / receive control register 0 (U2C0)
UART2 transmit / receive control register 1 (U2C1)
16
16
16
033E
UART2 receive buffer register (U2RB)
Figure 2.5.1. Memory map of serial interface special function-related registers
Rev.2.00 Oct 16, 2006 page 87 of 354
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M30245 Group
2. Serial Interface Special Function
UARTi transmit buffer register (i= 0 to 3) (Note)
b15
(b7)
b8
(b0)b7
Symbol
U0TB
U1TB
U2TB
U3TB
Address
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
b0
03AB16, 03AA16
036B16, 036A16
033B16, 033A16
032B16, 032A16
Function
(UART mode)
Function
Bit Symbol
R W
(clock synchronous serial I/O mode)
Transmit data
Transmit data
Transmit data (9th bit)
Nothing is assigned. Write “0” when writing to these bits.
The values are indeterminate when read.
Note: Use MOV instruction to write to this register.
UARTi receive buffer register (i= 0 to 3)
Symbol
Address
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
b15
(b7)
b8
(b0)b7
b0
U0RB
U1RB
U2RB
U3RB
03AF16, 03AE16
036F16, 036E16
033F16, 033E16
032F16, 032E16
Function
(clock synchronous
serial I/O mode)
Function
(UART mode)
Bit Name
Bit Symbol
R W
Receive data
Receive data
Receive data (9th bit)
Nothing is assigned. Write “0” when writing to these bits.
The values are indeterminate when read.
Arbitration lost
0 : Not detected
detecting flag (Note 1) 1 : Detected
Invalid
ABT
OER
FER
PER
SUM
0 : No overrun error
1 : Overrun error
Overrun error flag
(Note 2)
0 : No overrun error
1 : Overrun error
0 : No framing error
1 : Framing error
Framing error flag
(Note 2)
Invalid
Invalid
Invalid
Parity error flag
(Note 2)
0 : No parity error
1 : Parity error
Error sum flag
(Note 2)
0 : No error
1 : Error
Note 1: Always write “0”.
Note 2: Bits 15 to 12 are set to “0000
2
” when the serial I/O mode select bit (bits 0 to 2 at
” or the receive enable
addresses 03A816, 036816, 033816, 032816) are set to “000
2
bit is set to “0”. Bit 15 is set to “0” when all of bits 14 to 12 are set to “0”.
Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer
register (addresses 03AE16, 036E16, 033E16, 032E16) is read.
Figure 2.5.2. Serial interface special function-related registers (1)
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M30245 Group
2. Serial Interface Special Function
UARTi bit rate generator (o=0 to 3) (Note 1, 2)
Symbol
U0BRG
U1BRG
U2BRG
U3BRG
Address
03A916
036916
033916
032916
When reset
b7
b0
Indeterminate
Indeterminate
Indeterminate
Indeterminate
R W
Function
Values that can be set
0016 to FF16
Assuming that set value = n, BRGi divides the count source by
n + 1
Note 1: Use MOV instruction to write to this register.
Note 2: Write a value to this register while transmit/receive halts.
UARTi transmit/receive mode register (i = 0 to 3)
Symbol
U0MR
U1MR
U2MR
U3MR
Address
03A816
036816
033816
032816
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
0016
0016
0016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
b2 b1 b0
Must be fixed to 001
b2 b1 b0
SMD0
SMD1
Serial I/O mode select bit
(Note 3)
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Serial I/O mode
0 1 1 : I2C mode
Inhibited except in cases
listed above
Inhibited except in cases
listed above
SMD2
Internal/external clock
select bit
0 : Internal clock
1 : External clock (Note 1)
0 : Internal clock
1 : External clock (Note 1)
CKDIR
STPS
0 : One stop bit
1 : Two stop bits
Stop bit length select bit
Invalid
Valid when bit 6 = “1”
0 : Odd parity
PRY
Odd/even parity select bit Invalid
1 : Even parity
0 : Parity disabled
1 : Parity enabled
PRYE
SLEP
Parity enable bit
Invalid
TxD, RxD input/output
polarity switch bit (Note 2)
0 : Normal
1 : Reversed
Note 1: When I2C bus interface mode is selected, set the port direction register for the corresponding port
(SCLi) to 0, or the port direction register to 1 and the port data register to 1. When a mode other than
serial I/O mode is selected, set the port direction register for the corresponding port (CLKi) to 0.
Note 2: Normally set to “0”.
Note 3: Set the RxDi pin's port direction register to “0” when receiving.
Figure 2.5.3. Serial interface special function-related registers (2)
Rev.2.00 Oct 16, 2006 page 89 of 354
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M30245 Group
2. Serial Interface Special Function
UARTi transmit/receive control register 0 (i=0 to 3)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC0 (i=0 to 3)
Address
When reset
0816
03AC16, 036C16, 033C16, 032C16
,
Function
(During clock synchronous
serial I/O mode)
b1 b0
Bit
symbol
Function
R W
Bit name
(During UART mode)
b1 b0
CLK0
BRG count source
select bit
0 0 : f
0 1 : f
1
8
is selected
is selected
0 0 : f
0 1 : f
1
8
is selected
is selected
1 0 : f32 is selected
1 1 : Inhibited
1 0 : f32 is selected
1 1 : Inhibited
CLK1
CRS
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 4)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 4)
CTS/RTS function
select bit
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
TXEPT Transmit register empty
flag
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
CRD
CTS/RTS disable bit
Data output select bit
0 : TxDi/SDAi and SCLi pin is CMOS 0 : TxDi/SDAi and SCLi pin is CMOS
NCH
(Note 2)
output
output
1 : TxDi/SDAi and SCLi pin is
N-channel open drain output
1 : TxDi/SDAi and SCLi pin is
N-channel open drain output
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
Set to “0”
CKPOL CLK polarity select bit
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
Transfer format select bit
UFORM
0 : LSB first
1 : MSB first
0 : LSB first
1 : MSB first
(Note 3)
Note 1: Set the corresponding port direction register to “0”.
Note 2: UART2 transfer pin (TxD : P7 and SCL2: P7 ) is N-channel open drain output.
It cannot be set to CMOS output.
2
0
1
Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.
Note 4: The corresponding port register and port direction register are invalid.
UARTi transmit/receive control register 1 (i= 0 to 3)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC1 (i=0 to 3)
Address
When reset
0216
03AD16, 036D16, 033D16, 032D16
Function
(clock synchronous
serial I/O mode)
Function
(UART mode)
Bit Symbol
Bit Name
R W
0 : Transmit disabled
1 : Transmit enabled
Transmit enable
bit
TE
TI
Transmit buffer
empty flag
0 : Data present in transmit buffer register
1 : No data present in transmit buffer register
0 : Receive disabled
1 : Receive enabled
Receive enable
bit
RE
0 : Data packet in receive buffer register
1 : No data packet in receive buffer register
Receive
complete flag
RI
UARTi transmit
interrupt cause
select bit
0 : Transmit buffer empty (TI =1)
1 : Transmit buffer completed ( TXEPT =1)
UiIRS
0 : Continuous receive
UARTi continuous
receive mode
enable bit
mode disabled
1 : Continuous receive
mode enabled
Set to “0”
UiRRM
0 : No reverse
1 : Reverse
Data logic
select bit
UiLCH
UiERE
Set to “0”
The value is
indeterminate when read.
0 : Output disabled
1 : Output enabled
(Note 1)
Error signal
output enable bit
Note 1: When disabling the error signal output, set the UiERE bit to “0” after setting the
UiMR register.
Figure 2.5.4. Serial interface special function-related registers (3)
Rev.2.00 Oct 16, 2006 page 90 of 354
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M30245 Group
2. Serial Interface Special Function
UARTi special mode register 1 (i= 0 to 3)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiSMR (i=0 to 3)
Address
03A716, 036716, 033716, 032716
When reset
0016
Function
(clock synchronous
serial I/O mode)
Function
R W
Bit Symbol
Bit Name
(UART mode)
I2C mode
select bit
0 : Normal mode
1 : I2C mode
Set to “0”
IICM
Arbitration lost
detecting flag
control bit
0 : Update per bit
1 : Update per byte
Set to “0”
Set to “0”
ABC
BBS
0 : STOP detected
1 : START detected
Bus busy flag
SCLL sync output 0 : Disabled
Set to “0”
LSYN
enable bit
1 : Enabled
(Note 1)
0 : Rising edge of
transfer clock
1 : Timer Ai underflow
signal (Note 2)
Bus collision
detect sampling Set to “0”
clock select bit
ABSCS
Auto-clear
function select bit
of transmit enable
bit
0 : No auto clear function
1 : Auto clear when bus
collision occurs
Set to “0”
ACSE
SSS
Transmit start
condition select
bit
0 : Ordinary
1 : Falling edge of RxDi
Set to “0”
Nothing is assigned. Write "0" when writing to this bit.
The values are indeterminate when read.
Note 1: Only “0“ may be written
Note 2: UART0 Timer A3 underflow signal, UART1: Timer A4 underlfow signal,
UART2 :Timer A0 underflow signal.
UARTi special mode register 2 (i= 0 to 3)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
UiSMR2 (i=0 to 3) 03A616, 036616, 033616, 032616
R W
Bit Symbol
Bit Name
Function
0 : NACK/ACK interrupt (DMA source-ACK)
Transfer to receive buffer at the rising edge
of last bit of receive clock.
Receive interrupt occurs at the rising edge
of last bit of receive clock.
1 : UART transfer/receive interrupt (DMA
source-UART receive)
I2C mode
select bit 2
IICM2
Transfer to receive buffer at the falling edge
of last bit of receive clock.
Receive interrupt occurs at the falling edge
of last bit of receive clock
0 : Disable
1 : Enable
Clock synchronous bit
SCL wait output bit
CSC
0 : Disable
1 : Enable
SWC
(Note 1)
0 : Disable
1 : Enable
SDA output stop bit
UARTi initialize bit
ALS
STC
0 : Disable
1 : Enable
(Note 1)
(Note 1)
SCL Wait
output bit 2
0 : UARTi clock
1 : 0 output
SWC2
SDHI
SDA output
inhibit bit
0 : Disabled
1 : Enabled (high impedance)
Nothing is assigned. Write "0" when writing to this bit.
The values are indeterminate when read.
Note 1: These bits are unavailable when SCLi is external clock.
Figure 2.5.5. Serial interface special function-related registers (4)
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UARTi special mode register 3 (i= 0 to 3)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
UiSMR3 (i=0 to 3) 03A516, 036516, 033516, 032516
Bit Symbol
Bit Name
Function
R W
0 : SS function disabled
1 : SS function enabled
SS port function
enable bit (Note 1)
SSE
CKPH
DINC
NODC
0 : No clock delay
1 : Clock delay
Clock phase set bit
0 : Select TxDi and RxDi (master mode)
1 : Select STxDi and SRxDi (slave mode)
Serial input port
set bit
0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
Clock output
select bit
0 : No fault error
1 : Fault error (Note 2)
Fault error flag
ERR
DL0
DL1
DL2
b7 b6 b5
SDA (TxDi) digital
delay time set bit
(Notes 3,4)
0 0 0 : No delay
0 0 1 : 1 to 2-cycle of UiBRG count source
0 1 0 : 2 to 3-cycle of UiBRG count source
0 1 1 : 3 to 4-cycle of UiBRG count source
1 0 0 : 4 to 5-cycle of UiBRG count source
1 0 1 : 5 to 6-cycle of UiBRG count source
1 1 0 : 6 to 7-cycle of UiBRG count source
1 1 1 : 7 to 8-cycle of UiBRG count source
Note 1: Set SS function after setting CTS/RTS disable bit (bit 4 of UARTi transfer/receive
control register 0) to “1”
Note 2: Only “0” may be written.
Note 3: These bits are used for SDAi (TxDi) output digital delay when using UARTi for I2C
interface. Otherwis set to “000”.
Note 4: The amount of delay varies with the load on SCLi and SDAi pins.
When external clock is selected, delay is increased by approximately 100ns.
Figure 2.5.6. Serial interface special function-related registers (5)
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UARTi special mode register 4 (i= 0 to 3)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
UiSMR4 (i=0 to 3) 03A416, 036416, 033416, 032416
Bit Symbol
Bit Name
Function
R W
Start condition
generate bit (Note 1)
0 : Clear
1 : Start
STAREQ
RSTAREQ
STPREQ
STSPSEL
0 : Clear
1 : Start
Restart condition
generate bit (Note 1)
0 : Clear
1 : Start
Stop condition
generate bit (Note 1)
SCL, SDA output
select bit
0 : Ordinal block
1 : Start/stop condition generate block
0 : ACK
1 : NACK
ACKD
ACKC
SCLHI
SWC9
ACK data bit
0 : SI/O data output
1 : ACKD output
ACK data output
enable bit
0 : Disabled
1 : Enabled
SCL output stop
enable bit
0 : SCL “L” hold disabled
1 : SCL “L” hold enabled (Note 2)
SCL wait output bit 3
Note 1: These bits automatically become “0” when a start condition is generated.
Note 2: This bit is unavailable when SCLi is external clock.
Interrupt request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR
Address
035F16
When reset
0016
,
Bit Symbol
Bit name
Function
R W
INT0 interrupt polarity
swiching bit
0 : One edge
1 : Two edges
IFSR0
IFSR1
IFSR2
INT1 interrupt polarity
swiching bit
0 : One edge
1 : Two edges
INT2 interrupt polarity
swiching bit
0 : One edge
1 : Two edges
Nothing is assigned.
Write “0” when writing to this bit. The value is indeterminate when read.
0 : UART0 Bus collision /
Start/stop condition detection /
Trouble error detection
1 : UART2 Bus collision /
Start/stop condition detection /
Trouble error detection
Bus collision interrupt
request cause select bit 0
IFSR6
IFSR7
Bus collision interrupt
request cause select bit 1
0 : UART1 Bus collision /
Start/stop condition detection /
Trouble error detection
1 : UART3 Bus collision /
Start/stop condition detection /
Trouble error detection
Figure 2.5.7. Serial interface special function-related registers (6)
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2.5.2 Operation of Serial Interface Special Function (transmission in master mode
without delay)
In transmitting data in serial interface special function master mode, choose functions from those listed in
Table 2.5.1. Operations of the circled items are described below. Figure 2.5.8 shows the operation timing,
and Figures 2.5.9 and 2.5.10 show the set-up procedures.
Table 2.5.1. Choosed functions
Item
Set-up
Item
Set-up
Transfer clock
source
O
O
Internal clock (f1 / f8 / f32)
External clock (CLKi pin)
SSi function disabled
SSi function enabled
Without clock delay
With clock delay
SSi port function
enable
O
O
Output transmission data at
the falling edge of the
transfer clock
CLK polarity
Clock phase set
Output transmission data at
the rising edge of the
transfer clock
Serial input port set
TXDi, RXDi selected
(master mode)
O
O
Transmission buffer empty
Transmission complete
Transmission
interrupt factor
STXDi, SRXDi selected
(slave mode)
____
Operation (1) Set an SS port of the receiver side IC to output "L" level.
(2) Setting the transmit enable bit to “1” and writing transmission data to the UARTi transmit
buffer register makes data transmissible status ready.
(3) In synchronization with the first falling edge of the transfer clock, transmission data held in the
UARTi transmit buffer register is transmitted to the UARTi transmit register. At this time, the
UARTi transmit interrupt request bit goes to “1”. Also, the first bit of the transmission data is
transmitted from the TxDi pin. Then the data is transmitted bit by bit from the lower order in
synchronization with the falling edges.
(4) When transmission of 1-byte data is completed, the transmit register empty flag goes to “1”,
which indicates that transmission is completed. The transfer clock stops at “L” level.
(5) If the next transmission data is set in the UARTi transmit buffer register while transmission is
in progress (before the eighth bit has been transmitted), the data is transmitted in succession.
_____
Note
• Set SSi pin to "H" level. If "L" level is input to the pin, a fault error will be generated.
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Example of wiring
Microcomputer
Receiver side IC
Port
SSi
SS
CLKi
CLK
TXDi
SRXD
Example of operation
(1) Output "L" at the receiver side IC
(2) Transmission enabled
(4) Transmission is complete
(5) Transmit next data
Tc
(3) Start transmission
Transfer clock
Port
“H”
“L”
“1”
“0”
Transmit
enable bit (TE)
Data is set to UARTi transmit buffer register
“1”
“0”
Transmit
buffer empty
flag (Tl)
Transferred from UARTi transmit buffer register to UARTi transmit register
TCLK
CLKi
TxDi
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Transmit register
empty flag
(TXEPT)
“1”
“0”
“1”
“0”
Transmit
interrupt request
bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRGi count source (f
n: value set to BRGi
1, f8, f32)
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
Figure 2.5.8. Operation timing of transmission in serial interface special function master mode, without clock delay
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Setting UARTi transmit/receive mode register (i=0 to 3)
b7
0
b0
0 0 0 1
UARTi transmit/receive mode register
UiMR [Address 03A816, 36816, 033816, 32816
]
Must be fixed to “001”
Internal/external clock select bit
0 : Internal clock
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
T
X
D, R
XD I/O polarity reverse bit
Usually set to “0”
Setting UARTi transmit/receive control register 0 (i=0 to 3)
b7
b0
UARTi transmit/receive control register 0
UiC0 [Address 03AC16, 36C16, 033C16, 32C16
1
0
0 0
]
BRG count source select bit
b1 b0
0 0 : f
1
8
is selected
is selected
0 1 : f
1 0 : f32 is selected
1 1 : Inhibited
CTS/RTS function select bit
(Valid when bit 4 = “0”)
0 : CTS function is selected (Note 1)
Transmit register empty flag
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
CTS/RTS disable bit
1 : CTS/RTS function disabled
Data output select bit (Note 2)
0 : TxDi/SDAi and SCLi pin is CMOS output
1 : TxDi/SDAi and SCLi pin is N-channel open drain output
CLK polarity select bit
0 : Transmission data is output at falling edge
of transfer clock and reception data is input
at rising edge
Transfer format select bit
0 : LSB first
Note 1: Set the corresponding port direction register to “0”.
Note 2: UART2 transfer pin (TxD : P7 and SCL : P7 ) is N-channel open drain output.
It cannot be set to CMOS output.
2
0
2
1
Setting UARTi special mode register 3 (i=0 to 3)
b7
b0
UARTi special mode register 3
0 0 1
UiSMR3 [Address 03A516, 36516, 033516, 32516
]
SS port function enable bit
1 : SS function enable
Clock phase set bit
0 : Without clock delay
Serial input port set bit
0 : Select TxDi and RxDi
(Master mode)
Continued to the next page
Figure 2.5.9. Set-up procedure of transmission in serial interface special function master mode, without clock delay (1)
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Continued from the previous page
Setting UARTi transmit/receive control register 1 (i=0 to 3)
b7
0
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16]
0
0
UARTi transmit interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
Data logic select bit
0 : No reverse
Set to “0” in clock synchronous serial I/O mode.
Setting UARTi bit rate generator (i = 0 to 3)
b7
b0
UARTi bit rate generator [Address 03A916, 036916, 033916, 032916,]
UiBRG (i = 0 to 3)
Can be set to 0016 to FF16 (Note)
Note: Use MOV instruction to write to this register.
Write to UARTi bit rate generator when transmission/reception is halted.
Output an "L" to SS port on the receiver side IC
Transmission enabled
b7
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
1
]
Transmit enable bit
1 : Transmission enabled
Writing transmit data (Note)
UART0 transmit buffer register [Address 03AB16, 03AA16] U0TB
UART1 transmit buffer register [Address 036B16, 036A16] U1TB
UART2 transmit buffer register [Address 033B16, 033A16] U2TB
UART3 transmit buffer register [Address 032B16, 032A16] U3TB
(b15
b7
(b8)
b0
b7
b0
Setting transmission data
Note: Use MOV instruction to write to this register.
Start transmission
Checking the status of UARTi transmit buffer register (i = 0 to 3)
b7
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
]
Transmit buffer empty flag
0 : Data present in transmit buffer register
1 : No data present in transmit buffer register
(Writing next transmit data enabled)
When transmitting continuously
Writing next transmit data (Note)
(b15)
b7
(b8)
b0
UART0 transmit buffer register [Address 03AB16, 03AA16] U0TB
UART1 transmit buffer register [Address 036B16, 036A16] U1TB
UART2 transmit buffer register [Address 033B16, 033A16] U2TB
UART3 transmit buffer register [Address 032B16, 032A16] U3TB
b7
b0
Setting transmission data
Note: Use MOV instruction to write to this register.
Transmission is complete
Output an "H" to the SS port on the receiver side IC
Figure 2.5.10. Set-up procedure of transmission in serial interface special function master mode, without clock delay (2)
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2.5.3 Operation of Serial Interface Special Function (reception in master mode with
clock delay)
In receiving data in serial interface special function master mode, choose functions from those listed in
Table 2.5.2. Operations of the circled items are described below. Figure 2.5.11 shows the operation
timing, and Figures 2.5.12 and 2.5.13 show the set-up procedures.
Table 2.5.2. Choosed functions
Item
Set-up
Item
Set-up
O
O
Internal clock (f1 / f8 / f32)
Transfer clock
source
SSi function disabled
SSi function enabled
Without clock delay
With clock delay
SSi port function
enable
O
External clock (CLKi pin)
Output reception data at
the rising edge of the
transfer clock
CLK polarity
Clock phase set
O
O
Output reception data at
the falling edge of the
transfer clock
Serial input port set
TX
Di, R
XDi selected
(master mode)
O
Disabled
Enabled
Continuous receive
mode
ST
XDi, SRXDi selected
(slave mode)
____
Operation (1) Set an SS port of the transmitter side IC to output “L” level.
(2) Writing dummy data to the UARTi transmit buffer register, setting the receive enable bit to “1”,
and the transmit enable bit to “1”, makes the data receivable status ready.
(3) In synchronization with the first rising edge of the transfer clock, the input signal to the RxDi
pin is stored in the highest bit of the UARTi receive register. Then, data is taken in by shifting
right the content of the UARTi reception data in synchronization with the rising edges of the
transfer clock.
(4) When 1-byte data lines up in the UARTi receive register, the content of the UARTi receive
register is transmitted to the UARTi receive buffer register. At this time, the receive complete
flag and the UARTi receive interrupt request bit goes to “1”.
(5) The receive complete flag goes to “0” when the lower-order byte of the UARTi buffer register
is read.
Note
• Set RxDi pins' port direction register to “0”.
_____
• Set SSi pin to “H” level. If “L” level is input to the pin, a fault error will be generated.
Rev.2.00 Oct 16, 2006 page 98 of 354
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2. Serial Interface Special Function
Example of wiring
Microcomputer
Port
Transmitter side IC
SSi
SS
CLKi
CLK
STXD
RXDi
Example of operation
(1) Output "L" on the transmitter side IC
(2) Reception enabled
(4) Reception is complete
(5) Read of reception data
(3) Start reception
Tc
Transfer clock
Port
“H”
“L”
“1”
“0”
Receive enable
bit (RE)
“1”
“0”
Transmit
enable bit (TE)
Dummy data is set in UARTi transmit buffer register
TCLK
“1”
“0”
Transmit buffer
empty flag (Tl)
Transferred from UARTi transmit buffer register to UARTi transmit register
CLKi
RxDi
Reception data is taken in
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D
2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Transferred from UARTi receive register
to UARTi receive buffer register
Read out from UARTi receive buffer register
“1”
“0”
Receive complete
flag (Rl)
“1”
“0”
Receive interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRGi count source (f
n: value set to BRGi
1, f8, f32)
• CLK polarity select bit = “0”.
Figure 2.5.11. Operation timing of reception in serial interface special function master mode, with clock delay
Rev.2.00 Oct 16, 2006 page 99 of 354
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2. Serial Interface Special Function
Setting UARTi transmit/receive mode register (i=0 to 3)
b7
b0
UARTi transmit/receive mode register
UiMR [Address 03A816, 36816, 033816, 32816]
0 0 0 1
0
Must be fixed to “001” (Note)
Internal/external clock select bit
0 : Internal clock
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
TXD, RXD I/O polarity reverse bit
Usually set to “0”
Note: Set the RxDi pin's port direction register to “0” when receiving.
Setting UARTi transmit/receive control register (i=0 to 3)
b7
0 0
b0
UARTi transmit/receive control register 0
UiC0 [Address 03AC16, 36C16, 033C16, 32C16]
1
0
BRG count source select bit
b1 b0
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
CTS/RTS function select bit
(Valid when bit 4 = “0”)
0 : CTS function is selected (Note 1)
Transmit register empty flag
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
CTS/RTS disable bit
1 : CTS/RTS function disabled
Data output select bit (Note 2)
0 : TxDi/SDAi and SCLi pin is CMOS output
1 : TxDi/SDAi and SCLi pin is N-channel open drain output
CLK polarity select bit
0 : Transmission data is output at falling edge
of transfer clock and reception data is input
at rising edge
Transfer format select bit
0 : LSB first
Note 1: Set the corresponding port direction register to “0”.
Note 2: UART2 transfer pin (TxD2: P70) is N-channel open drain output.
It cannot be set to CMOS output.
Setting UARTi special mode register 3 (i=0 to 3)
b7
b0
0 1 1
UARTi special mode register 3
UiSMR3 [Address 03A516, 36516, 033516, 32516]
SS port function enable bit
1 : SS function enable
Clock phase set bit
1 : With clock delay
Serial input port set bit
0 : Select TxDi and RxDi
(Master mode)
Continued to the next page
Figure 2.5.12. Set-up procedure of reception in serial interface special function master mode, with clock delay (1)
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Continued from the previous page
Setting UARTi transmit/receive control register 1 (i=0 to 3)
b7
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
0
0
0 0
]
UARTi transmit interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
UARTi continuous receive mode enable bit
0 : Continuous receive mode disabled
Data logic select bit
0 : No reverse
Set to “0” in clock synchronous serial I/O mode.
Setting UARTi bit rate generator (i =0 to 3)
b7
b0
UARTi bit rate generator [Address 03A916, 036916, 033916, 032916,]
UiBRG (i = 0 to 3)
Can be set to 0016 to FF16 (Note)
Note: Use MOV instruction to write to this register.
Write to UARTi bit rate generator when transmission/reception is halted.
Output an “L” to SS port on the transmitter side IC
Reception enabled
b7
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
1
1
]
Transmit enable bit
1 : Transmission enabled
Reception enable bit
1 : Reception enabled
Writing dummy data (Note)
UART0 transmit buffer register [Address 03AB16, 03AA16] U0TB
UART1 transmit buffer register [Address 036B16, 036A16] U1TB
UART2 transmit buffer register [Address 033B16, 033A16] U2TB
UART3 transmit buffer register [Address 032B16, 032A16] U3TB
(b15
b7
(b8)
b0
b7
b0
Setting dummy data
Note: Use MOV instruction to write to this register.
Start reception
Checking completion of data reception
b7
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
]
Receive complete flag
0 : No data present in receive buffer register
1 : Data present in receive buffer register
Checking error
UART0 receive buffer register [Address 03AF16, 03AE16] U0RB
UART1 receive buffer register [Address 036F16, 036E16] U1RB
UART2 receive buffer register [Address 033F16, 033E16] U2RB
UART3 receive buffer register [Address 032F16, 032E16] U3RB
(b15)
b7
(b8)
b0
b7
b0
Overrun error flag
0: No overrun error
1: Overrun error found
Processing after reading out received data
Output “H” to the SS port on the transmitter side IC
Figure 2.5.13. Set-up procedure of reception in serial interface special function master mode, with clock delay (2)
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2.5.4 Operation of Serial Interface Special Function (transmission in slave mode
without delay)
In transmitting data in serial interface special function slave mode, choose functions from those listed in
Table 2.5.3. Operations of the circled items are described below. Figure 2.5.14 shows the operation
timing, and Figures 2.5.15 and 2.5.16 show the set-up procedures.
Table 2.5.3. Choosed functions
Item
Set-up
Item
Set-up
Internal clock (f1 / f8 / f32)
Transfer clock
source
SSi function disabled
SSi function enabled
Without clock delay
With clock delay
SSi port function
enable
O
O
O
O
External clock (CLKi pin)
Output transmission data at
the falling edge of the
transfer clock
CLK polarity
Clock phase set
Output transmission data at
the rising edge of the
transfer clock
Serial input port set
T
X
Di, R
XDi selected
(master mode)
O
Transmission buffer empty
Transmission complete
Transmission
interrupt factor
ST
XDi, SRXDi selected
O
(slave mode)
____
Operation (1) Input "L" level to an SSi port by the output from the receiver side IC's port.
(2) Setting the transmit enable bit to “1” and writing transmission data to the UARTi transmit
buffer register makes data transmissible status ready.
(3) In synchronization with the first falling edge of the transfer clock, transmission data held in the
UARTi transmit buffer register is transmitted to the UARTi transmit register. At this time, the
UARTi transmit interrupt request bit goes to “1”. Also, the first bit of the transmission data is
transmitted from the STxDi pin. Then the data is transmitted bit by bit from the lower order in
synchronization with the falling edges.
(4) When transmission of 1-byte data is completed, the transmit register empty flag goes to “1”,
which indicates that transmission is completed.
(5) If the next transmission data is set in the UARTi transmit buffer register while transmission is
in progress (before the eighth bit has been transmitted), the data is transmitted in succession.
Note
• Set CLKi pin's port direction register to “0”.
Rev.2.00 Oct 16, 2006 page 102 of 354
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2. Serial Interface Special Function
Example of wiring
Microcomputer
Receiver side IC
Port
SSi
CLKi
ST Di
CLK
RXD
X
Example of operation
(1) Set SSi port to "L" with the output from the receiver side IC port
(4) Transmission is complete
(5) Transmit next data
(2) Transmission enabled
(3) Start transmission
“1”
“0”
Transfer clock
(TE)
Transfer data is set to UARTi transmit buffer register
“1”
“0”
Transmit buffer
empty flag (TI)
Transferred from UARTi transmit butter register to transmit register
“H”
“L”
SSi
1 / fEXT
CLKi
Indeter-
minate
D0
D1
D2
D3
D4
D5
D0
D1
D2
D4
D5
D
D6
D7
D3
6
D7
STxDi
“1”
Transmit register
empty flag
(TXEPT)
“0”
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• External clock is selected.
• CLK polarity select bit = “0”.
Make sure that the following conditions are met when
the CLKi pin input =“H” before data reception
• Transmit enable bit →“1”
• Transmit data written to UARTi transmit buffer register
fEXT: frequency of external clock
Figure 2.5.14. Operation timing of transmission in serial interface special function slave mode, without clock delay
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2. Serial Interface Special Function
Setting UARTi transmit/receive mode register (i=0 to 3)
b7
b0
UARTi transmit/receive mode register
UiMR [Address 03A816, 36816, 033816, 32816
1 0 0 1
0
]
Must be fixed to “001”
Internal/external clock select bit
1 : External clock (Note)
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
T
X
D, R
Usually set to “0”
Note: Set the corresponding port direction register to “0”.
XD I/O polarity reverse bit
Setting UARTi transmit/receive control register (i=0 to 3)
b7
0 0
b0
UARTi transmit/receive control register 0
UiC0 [Address 03AC16, 36C16, 033C16, 32C16
1
0
]
BRG count source select bit
b1 b0
0 0 : f
1
8
is selected
is selected
0 1 : f
1 0 : f32 is selected
1 1 : Inhibited
CTS/RTS function select bit
(Valid when bit 4 = “0”)
0 : CTS function is selected (Note 1)
Transmit register empty flag
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
CTS/RTS disable bit
1 : CTS/RTS function disabled
Data output select bit (Note 2)
0 : TxDi/SDAi and SCLi pin is CMOS output
1 : TxDi/SDAi and SCLi pin is N-channel open drain output
CLK polarity select bit
0 : Transmission data is output at falling edge
of transfer clock and reception data is input
at rising edge
Transfer format select bit
0 : LSB first
Note 1: Set the corresponding port direction register to “0”.
Note 2: UART2 transfer pin (TxD2: P7 and SCL2: P7 ) is N-channel open drain output.
It cannot be set to CMOS output.
0
1
Setting UARTi special mode register 3 (i=0 to 3)
b7
b0
UARTi special mode register 3
UiSMR3 [Address 03A516, 36516, 033516, 32516
1 0 1
]
SS port function enable bit
1 : SS function enable
Clock phase set bit
0 : No clock delay
Serial input port set bit
1 : Select STxDi and SRxDi
(Slave mode)
Continued to the next page
Figure 2.5.15. Set-up procedure of transmission in serial interface special function slave mode, without clock delay (1)
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Continued from the previous page
Setting UARTi transmit/receive control register 1 (i=0 to 3)
b7
0
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16]
0
0
UARTi transmit interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
Data logic select bit
0 : No reverse
Set to “0” in clock synchronous I/O mode
Transmission enabled
b7
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
1
]
Transmit enable bit
1 : Transmission enabled
Writing transmit data (Note)
UART0 transmit buffer register [Address 03AB16, 03AA16] U0TB
UART1 transmit buffer register [Address 036B16, 036A16] U1TB
UART2 transmit buffer register [Address 033B16, 033A16] U2TB
UART3 transmit buffer register [Address 032B16, 032A16] U3TB
(b15
b7
(b8)
b0
b7
b0
Setting transmission data
Note: Use MOV instruction to write to this register.
Start transmission
Checking the status of UARTi transmit buffer register (i = 0 to 3)
b7
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
]
Transmit buffer empty flag
0 : Data present in transmit buffer register
1 : No data present in transmit buffer register
(Writing next transmit data enabled)
When transmitting continuously
Writing next transmit data (Note)
(b15)
b7
(b8)
b0
UART0 transmit buffer register [Address 03AB16, 03AA16] U0TB
UART1 transmit buffer register [Address 036B16, 036A16] U1TB
UART2 transmit buffer register [Address 033B16, 033A16] U2TB
UART3 transmit buffer register [Address 032B16, 032A16] U3TB
b7
b0
Setting transmission data
Note: Use MOV instruction to write to this register.
Transmission is complete
Figure 2.5.16. Set-up procedure of transmission in serial interface special function slave mode, without clock delay (2)
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2. Serial Interface Special Function
2.5.5 Operation of Serial Interface Special Function (reception in slave mode with
clock delay)
In receiving data in serial interface special function slave mode, choose functions from those listed in
Table 2.5.4. Operations of the circled items are described below. Figure 2.5.17 shows the operation
timing, and Figures 2.5.18 and 2.5.19 show the set-up procedures.
Table 2.5.4. Choosed functions
Item
Set-up
Item
Set-up
Internal clock (f1 / f8 / f32)
Transfer clock
source
SSi function disabled
SSi function enabled
Without clock delay
With clock delay
SSi port function
enable
O
O
O
O
External clock (CLKi pin)
Output reception data at
the rising edge of the
transfer clock
CLK polarity
Clock phase set
Output reception data at
the falling edge of the
transfer clock
Serial input port set
T
X
Di, R
XDi selected
(master mode)
O
Disabled
Enabled
Continuous receive
mode
ST
XDi, SRXDi selected
O
(slave mode)
____
Operation (1) An SSi port is input "L" level which outputs from the transmitter side IC port.
(2) Writing dummy data to the UARTi transmit buffer register, setting the receive enable bit to “1”,
and the transmit enable bit to “1”, makes the data receivable status ready.
(3) In synchronization with the first rising edge of the transfer clock, the input signal to the SRxDi
pin is stored in the highest bit of the UARTi receive register. Then, data is taken in by shifting
right the content of the UARTi reception data in synchronization with the rising edges of the
transfer clock.
(4) When 1-byte data lines up in the UARTi receive register, the content of the UARTi receive
register is transmitted to the UARTi receive buffer register. At this time, the receive complete
flag and the UARTi receive interrupt request bit goes to “1”.
(5) The receive complete flag goes to “0” when the lower-order byte of the UARTi buffer register
is read.
Note
• Set CLKi and SRxDi pins' port direction register to “0”.
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2. Serial Interface Special Function
Example of wiring
Microcomputer
Transmistter side IC
Port
SSi
CLKi
SR Di
CLK
TXD
X
Example of operation
(1) Set SSi port to "L" by the output from the transmitter side IC port
(4) Reception is complete
(5) Read of reception data
(2) Reception enabled
(3) Start reception
“1”
“0”
Receive enable
bit (RE)
“1”
“0”
Transmit enable
bit (TE)
Dummy data is set in UARTi transmit buffer register
“1”
“0”
“H”
Transmit buffer
empty flag (Tl)
Transferred from UARTi transmit buffer register to UARTi transmit register
SSi
“L”
1 / fEXT
CLKi
SRxDi
Reception data is taken in
D0
D1
D2
D3
D4
D5
D0
D1
D2
D4
D5
D
D6
D7
D3
6
D7
Transferred from UARTi receive register
to UARTi receive buffer register
Read out from UARTi receive buffer register
“1”
“0”
Receive complete
flag (Rl)
“1”
“0”
Receive interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• External clock is selected.
• CLK polarity select bit = “0”.
Make sure that the following conditions are met when
the CLKi pin input =“H” before data reception
• Transmit enable bit → “1”
• Receive enable bit → “1”
• Dummy data write to UARTi transmit buffer register
fEXT: frequency of external clock
Figure 2.5.17. Operation timing of reception in serial interface special function slave mode, with clock delay
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2. Serial Interface Special Function
Setting UARTi transmit/receive mode register (i=0 to 3)
b7
b0
UARTi transmit/receive mode register
UiMR [Address 03A816, 36816, 033816, 32816
1 0 0 1
0
]
Must be fixed to “001” (Note 1)
Internal/external clock select bit
1 : External clock (Note 2)
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
TX
D, R
XD I/O polarity reverse bit
Usually set to “0”
Note 1: Set the RxDi pin's port direction register to “0” when receiving.
Note 2: Set the corresponding port direction register to “0”.
Setting UARTi transmit/receive control register (i=0 to 3)
b7
0 0
b0
UARTi transmit/receive control register 0
UiC0 [Address 03AC16, 36C16, 033C16, 32C16
1
0
]
BRG count source select bit
b1 b0
0 0 : f
1
8
is selected
is selected
0 1 : f
1 0 : f32 is selected
1 1 : Inhibited
CTS/RTS function select bit
(Valid when bit 4 = “0”)
0 : CTS function is selected (Note 1)
Transmit register empty flag
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
CTS/RTS disable bit
1 : CTS/RTS function disabled
Data output select bit (Note 2)
0 : TxDi pin is CMOS output
1 : TxDi pin is N-channel open-drain output
CLK polarity select bit
0 : Transmission data is output at falling edge
of transfer clock and reception data is input
at rising edge
Transfer format select bit
0 : LSB first
Note 1: Set the corresponding port direction register to “0”.
Note 2: UART2 transfer pin (TxD : P7 ) is N-channel open drain output.
It cannot be set to CMOS output.
2
0
Setting UARTi special mode register 3 (i=0 to 3)
b7
b0
UARTi special mode register 3
UiSMR3 [Address 03A516, 36516, 033516, 32516
1 1 1
]
SS port function enable bit
1 : SS function enable
Clock phase set bit
1 : With clock delay
Serial input port set bit
1 : Select STxDi and SRxDi
(Slave mode)
Continued to the next page
Figure 2.5.18. Set-up procedure of reception in serial interface special function slave mode, with clock delay (1)
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Continued from the previous page
Setting UARTi transmit/receive control register 1 (i=0 to 3)
b7
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
0 0 0
]
UARTi continuous receive mode enable bit
0 : Continuous receive mode disabled
Data logic select bit
0 : No reverse
Set to “0” in clock synchronous I/O mode
Reception enabled
b7
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
1
1
]
Transmit enable bit
1 : Transmission enabled
Reception enable bit
1 : Reception enabled
Writing dummy data (Note)
UART0 transmit buffer register [Address 03AB16, 03AA16] U0TB
UART1 transmit buffer register [Address 036B16, 036A16] U1TB
UART2 transmit buffer register [Address 033B16, 033A16] U2TB
UART3 transmit buffer register [Address 032B16, 032A16] U3TB
(b15
b7
(b8)
b0
b7
b0
Setting dummy data
Note: Use MOV instruction to write to this register.
Start reception
Checking completion of data reception
b7
b0
UARTi transmit/receive control register 1
UiC1 [Address 03AD16, 36D16, 033D16, 32D16
]
Receive complete flag
0 : No data present in receive buffer register
1 : Data present in receive buffer register
Checking error
UART0 receive buffer register [Address 03AF16, 03AE16] U0RB
UART1 receive buffer register [Address 036F16, 036E16] U1RB
UART2 receive buffer register [Address 033F16, 033E16] U2RB
UART3 receive buffer register [Address 032F16, 032E16] U3RB
(b15)
b7
(b8)
b0
b7
b0
Overrun error flag
0: No overrun error
1: Overrun error found
Processing after reading out received data
Figure 2.5.19. Set-up procedure of reception in serial interface special function slave mode, with clock delay (2)
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2. Serial sound interface
2.6 Serial sound interface
2.6.1 Overview
The Serial Sound Interface (SSI) is a synchronous serial data interface used primary for transferring
digital audio data. The bus of the 30245 Serial Sound Interface has four lines:
• Continuous serial clock (SCK)
• Word (channel) select (WS)
• Serial data out (XMIT)
• Serial data in (RX)
A basic Serial Sound Interface-based communication system has two Serial Sound Interfaces and a
master controller, which generates both SCK and WS. The Serial Sound Interface that generates the
control signals (SCK and WS) operates as a master, and the Serial Sound Interface that receives the
external control signals operates as slave. The 30245 Sound Serial Interface can operate only as a slave.
The transmitter/receiver must change channels on every WS transition. Through separate transmit and
receive pins, simultaneous transmit and receive can be performed in synchronization with the same SCK
and WS signals.
The following is an overview of the Serial Sound Interface.
ꢀ Transmission/reception format
The data path is designed to work with the data format of the USB audio class device specifications.
The transmitter/receiver must change channels on every WS transition. The number of SCKs within a
WS high/low period is set as the channel width. The channel width can be selected from among 16
bits, 24 bits, and 32 bits using channel width select bits 0 and 1 (bits 4 and 5 of the SSIiMR0 register).
If the number of SCKs exceeds the channel width, the receiver will stop receiving data until the next
WS edge and the transmitter continues to transmit “0”. However, if the number of the SCKs falls short
of the channel data width, both the transmitter and the receiver will immediately switch to transmit and
receive, respectively, of the next channel data item.
ꢀ Select function
In the Serial Sound Interface function, the following features can be selected.
(1) Rate feedback function
When used with the USB interface, the Serial Sound Interface can count the number of WSs or SCKs
per USB frame. The count value is loaded into the serial sound interface xRF register (x = 0 or 1) on
the falling edge of each SOF pulse generated by the USB core. The SOF pulse is a frame delimiter
used in USB communication. The value read from the register is the count from the immediately
preceding USB frame.
(2) Channel width selection function
Channel widths of 32, 24 and 16 bits can be used to transmit and receive data. The width can be
selected by the channel width select bits 0 and 1 in serial sound interface mode register 0.
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(3) LSB/MSB first select function
This function is to choose whether to transmit/receive data from bit 1 or bit 7. This is valid when the
transfer data length is 8 bits long.
Choose either of the following:
• LSB first
• MSB first
Data is transmitted/received from bit 0.
Data is transmitted/received from bit 7.
(4) Multiple receive format select function
If the number of SCKs in a WS high/low period is less than the channel width, the data can be placed
either MSB or LSB justified.
(5) SCK polarity select function
This function selects whether transmit and receive data are synchronized to the rising or falling edge
of WS. This is selected by the SCK polarity bit in the serial sound interface x mode register 1.
(6) WS polarity select function
This function is to transmit/receive data synchronized to the rising edge or the falling edge of WS.
This is selected by the WS polarity select bit in the Serial Sound Interface x mode register 1.
(7) WS delay select function
Either of the following modes may be selected for the channel change timing:
• Normal WS mode
WS transitions one SCK period before a channel change. (The channel changes one SCK period
after WS transitions.)
• Delayed WS mode
WS transitions concurrently with a channel change.
ꢀ Input to the Serial Sound Interface function and the corresponding direction register
When inputting an external signal to the Serial Sound Interface, set the corresponding port's direction
register as input.
ꢀ Serial Sound Interface function-related pins
(1)
(2)
(3)
(4)
SCLK0 and SCLK1pins
WS0 and WS1pins
RX0 and RX1pins
Transfer clock input
Channel clock input
Data input
XMIT0 and XMIT1pins
Data output
ꢀ Serial Sound Interface function-related register
Figure 2.6.1 shows a memory map of the frequency synthesizer-related registers. Figures 2.6.2 and
2.6.3 show the configuration of Serial Sound Interface function related-registers, respectively.
Set the port's direction register appropriately and disable the clock synchronous serial and the UART
which share the port.
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2. Serial sound interface
031016
Serial Sound Interface 0 mode register 0 (SS0MR0)
031116
031216
031316
031416
031516
031616
031716
031816
031916
031A16
Serial Sound Interface 0 mode register 1 (SS0MR1)
Reserved
Reserved
Serial Sound Interface 0 transmit buffer register (SS0TXB)
Serial Sound Interface 0 receive buffer register (SS0RXB)
Serial Sound Interface 0 RF register (SS0RF)
Reserved
037016
037116
037216
037316
037416
037516
037616
037716
037816
037916
Serial Sound Interface 1 mode register 0 (SSI1MR0)
Serial Sound Interface 1 mode register 1 (SSI1MR1)
Reserved
Reserved
Serial Sound Interface 1 transmit buffer register (SSI1TXB)
Serial Sound Interface 1 receive buffer register (SSI1RXB)
Serial Sound Interface 1 RF register (SSI1RF)
Figure 2.6.1. Memory map of Serial Sound Interface function-related registers
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2. Serial sound interface
Serial Sound Interface x transmit buffer register
Symbol
SSIxTXB (x = 0,1)
Address
031516, 031416
037516, 037416
When reset
000016
(b15)
b7
(b8)
b0
b7
b0
Function
R
O
W
O
Transmit data (Note 1)
Note 1: For byte access, write data to addresses 031416 and 037416 only.
(Do not access to addresses 031516 and 037516.)
Serial Sound Interface x receive buffer register
Symbol
SSIxRXB (x = 0,1)
When reset
000016
(b15)
b7
Address
031716, 031616
037716, 037616
(b8)
b0
b7
b0
Function
R
O
W
O
Receive data (Note 1)
Note 1: For byte access, write data to addresses 031616 and 037616
(Do not access to addresses 031716 and 037716.)
.
Serial Sound Interface x RF register
(b15)
(b8)
Address
031916, 031816
037916, 037816
Symbol
SSIxRF (x= 0,1)
When reset
000016
b0
b7
b7
b0
R
O
W
X
Function
Rate feedback counter value
Figure 2.6.2. Serial Sound Interface function-related registers (1)
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2. Serial sound interface
Serial Sound Interface x mode register 0
Symbol
SSIxMR0 (x = 0,1)
Address
When reset
0016
031016, 037016
b6
b7
b5 b4 b3 b2 b1 b0
R
O
W
Bit symbol
Bit name
Function
0 : Disable
SSIEN
XMTEN
RXEN
Serial Sound Interface enable bit
Transmitter enable bit
O
1 : Enable
0 : Disable
1 : Enable
O
O
O
O
O
O
0 : Disable
1 : Enable
Receiver enable bit
0 : Disable
1 : Enable
RFBEN
CWID0
CWID1
RFMT0
RFMT1
Rate feedback counter enable bit
Channel width select bit 0
Channel width select bit 1
Receiver format select bit 0
Receiver format select bit 1
b5 b4
O
O
0 0 : 32 bit
0 1 : 24 bit
1 0 : Disable
1 1 : 16 bit
O
O
O
O
0: LSB first
1: MSB first
0 : LSB justified
1 : MSB justified
O
O
Serial Sound Interface x mode register 1
Symbol
SSIxMR1 (x = 0,1)
Address
031116, 037116
When reset
0016
b6
b7
b5 b4 b3 b2 b1 b0
0
0 0
R
O
O
W
Bit symbol
Bit name
Function
0: LSB first
XMTFMT
Transmitter format
O
O
1: MSB first
Reserved bit
Always set to “0”.
0 : SCK
1 : WS
O
O
O
O
O
O
Rate feedback counter source
SCK polarity select bit
WS polarity select bit
WS delay select bit
RFBSRC
SCKP
0: Falling edge
1: Rising edge
0: Falling edge
1: Rising edge
WSP
0: Delayed WS
1: Normal WS
WSDLY
Reserved bit
O
O
O
O
Always set to “0”.
Figure 2.6.3. Serial Sound Interface function-related registers (2)
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2. Serial sound interface
In the case of the USB audio class, the following stream is output.
Audio stream (PCM) from the PC to the M30245 USB FIFO
For 16-bit data
Fifth byte
Fourth byte
e1 e0
LSB
First byte
Third byte
Second byte
c1 c0
LSB
f1 f0
LSB
f7
MSB
e7
MSB
b1 b0
LSB
b7
MSB
d1 d0
LSB
d7
MSB
c7
MSB
Left Low (LL)
Right High (RH)
Left Low (LL)
Right Low (RL)
Left High (LH)
LSB first transmit/receive
RH RL LH LL RH RL LH LL RH RL LH LL
LSB
USB FIFO data setup
FIFO data
M30245 FIFO address
First byte LL
Second byte LH
15141312 11 10 9
8
8
8
8
8
8
7
7
7
7
7
7
6
6
6
6
6
6
5
4
3
2
1
1
1
0
0
0
0
0
0
0
Third byte RL
Fourth byte RH
1
15141312 11 10 9
5 4 3 2
Fifth byte LL
Sixth byte LH
15141312 11 10 9
5 4 3 2
2
Seventh byte RL
Eighth byte RH
15141312 11 10 9
5
4
3
2
1
1
3
Ninth byte LL
Tenth byte LH
4
15141312 11 10 9
5 4 3 2
Eleventh byte RL
Twelfth byte RH
5
15141312 11 10 9
5 4 3 2 1
MSB
LSB
For 16-bit data
LSB
b0
MSB LSB
b7 b0
MSB
b7
b7 b0
Left Buffer
b7 b0
Right Buffer
Byte 0
OPERATION
Byte 1
Byte 0
Byte 1
First Word Write
Second Word Write
Third Word Write
Fourth Word Write
Second byte
Sixth byte
First byte
Third byte
Seventh byte
Fourth byte
Eighth byte
Fifth byte
LL: b0 to b7 RL: b0 to b7
LH: b8 to b15 RH: b8 to b15
Just as 16 bits, the data width is expanded to output data for 24 bits and 32 bits .
For 24-bit data
LSB
b0
LSB
MSB
b7 b0
MSB
b7
b7 b0
b7 b0
Right Buffer
b7 b0
b7 b0
Left Buffer
Byte 1
OPERATION
Byte 2
Byte 2
Byte 0
Byte 0
Byte 1
First Word Write
Second Word Write
Third Word Write
Fourth Word Write
First byte (LL) Second byte (LM)
Third byte (LH) Fourth byte (RL)
Fifth byte (LM)
Sixth byte (LH)
Seventh byte
Eighth byte
LL: b0 to b7
RL: b0 to b7
LM: b8 to b15
LH: b16 to b23
RM: b8 to b15
RH: b16 to b23
For 32-bit data
LSB
b0
LSB
MSB
b7 b0
MSB
b7
b7 b0
b7 b0
Right Buffer
b7 b0
b7 b0
b7 b0
Left Buffer
b7 b0
OPERATION
Byte 3
First byte (LL)
Byte 0
Byte 2
Second byte (LML)
Byte 1
Byte 0
Byte 3
Byte 2
Byte 1
First Word Write
Second Word Write
Third Word Write
Fourth Word Write
Fourth byte (LH)
Third byte (LMH)
Fifth byte (RL)
Sixth byte (RML)
Eighth byte (RH)
Seventh byte (RMH)
LL: b0 to b7
RL: b0 to b7
LML: b8 to b15
LMH: b16 to b23
LH: b24 to b31
RML: b8 to b15
RHH: b16 to b23
RH: b24 to b31
Figure 2.6.4. Example of Audio stream (PCM) from the PC to the M30245 USB FIFO
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2. Serial sound interface
2.6.2 Example of Serial Sound Interface operation
When using Serial Sound Interface (SSI), the DMA is recommended for reading and writing data quickly
from the receive buffer to the transmit buffer. A programming example using DMA is shown below Figure
2.6.5 shows an example of Serial Sound Interface transmit timing, and Figure 2.6.6 shows an example of
Serial Sound Interface receive timing.
/***** Serial Sound Interface initialization routine *****************************************************
Serial Sound Interface is initialized by disabling.
The DMA to use is also initialized.
In this example, one DMA is used for each Serial Sound Interface input and output.
*************************************************************************************************************/
ssi1mr1 = 0x00;
ssi1mr0 = 0x00;
dm0sl = 0x00;
dm0con = 0x00;
dm1sl = 0x00;
dm1con = 0x00;
/* SSI STOP */
/* SSI STOP */
/* DMA0 STOP */
/* DMA0 STOP */
/* DMA1 STOP */
/* DMA1 STOP */
/***** Setting example **********************************************************************************
Audio transmission can be set before or after audio reception
The DMA to use is set.
DMA0 = audio data transmission and DMA1= audio data reception
*************************************************************************************************************/
dm0ic = 0x06;
dm0sl = 0x0e;
sar0 = (unsigned long)&txb_buffer;
dar0 = (unsigned long)&ssi1txb;
tcr0 = txb_counter;
/* DMA completion interrupt enabled */
/* DMA0 factor = SSI 1 transmit */
/* source address: buffer RAM, etc. */
/* destination address: SSI 1 transmit buffer */
/* DMA0 transfer cycle setting */
dm1ic = 0x06;
dm1sl = 0x0a;
/* DMA completion interrupt enabled */
/* DMA1 factor = SSI 1 receive */
sar1 = (unsigned long)&ssi1rxb;
dar1 = (unsigned long)&rxb_buffer;
tcr1 = rxb_counter;
/* source address: SSI 1 receive */
/* destination address: buffer RAM, etc. */
/* DMA1 transfer cycle setting */
/***** Activation processing routine ********************************************************************
DMA activation. DMA0 can be activated before or after DMA1.
*************************************************************************************************************/
dm0con = 0x18;
dm1con = 0x28;
/* DMA0 start [16bit, SRC = inc, single] */
/* DMA1 start [16bit, DES = inc, single] */
/*******Serial Sound Interface is stopped at this point.
Serial Sound Interface is enabled and audio data transmission/reception starts.***********/
(Continued to the next page.)
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2. Serial sound interface
(Continued from the previous page.)
/***** Serial Sound Interface activation routine for 16 bits *******************************************/
#ifdef OUT_Q_BIT_NO_16
ssi1mr0 = 0x01;
ssi1mr0 = 0xf1;
ssi1mr1 = 0x21;
ssi1mr0 = 0xf7;
/* SSIEN = 1 */
/* 16bit / MSB justified */
/* SCK neg, WS neg
MSB first normal */
/* 16bit / Tx enable, Rx enable MSB justified */
#endif
/***** Serial Sound Interface activation routine for 24 bits ******************************************/
#ifdef OUT_Q_BIT_NO_24
ssi1mr0 = 0x01;
ssi1mr0 = 0xd1;
ssi1mr1 = 0x21;
ssi1mr0 = 0xd7;
/* SSIEN = 1 */
/* 24bit / MSB justified */
/* SCK neg, WS neg
MSB first normal */
/* 24bit / Tx enable, Rx enable MSB justified */
#endif
/***** Serial Sound Interface activation routine for 32 bits *******************************************/
#ifdef OUT_Q_BIT_NO_32
ssi1mr0 = 0x01;
ssi1mr0 = 0xc1;
ssi1mr1 = 0x21;
ssi1mr0 = 0xc7;
/* SSIEN = 1 */
/* 32bit / MSB justified */
/* SCK neg, WS neg
MSB first normal */
/* 32bit / Tx enable, Rx enable MSB justified */
#endif
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2. Serial sound interface
Serial Sound Interface timing (1)
Fs = 48 kHz or 44.1kHz
WS
XMTEN
WSDLY = 1
SCK = Min 64 × Fs (2.8MHz)/ Max192 × Fs(9.2MHz)
SCK
SCKP = 1, WSP = 0
SCKP = 0, WSP = 0
SCKP = 1, WSP = 1
SCKP = 0, WSP = 1
XMTFMT = 0:MSB first, XMTFMT = 1:LSB first
Serial Sound Interface timing (2)
Fs = 48 kHz or 44.1kHz
WS
WSDLY = 0
XMTEN
SCK = Min 64 × Fs (2.8MHz)/ Max192 × Fs(9.2MHz)
SCKP = 1, WSP = 0
SCKP = 0, WSP = 0
SCKP = 1, WSP = 1
SCKP = 0, WSP = 1
XMTFMT = 0:MSB first, XMTFMT = 1:LSB first
Figure 2.6.5. Example of Serial Sound Interface transmit timing
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2. Serial sound interface
Serial Sound Interface timing (3)
Fs = 48 kHz or 44.1kHz
WS
RXEN
SCK = Min 64 × Fs (2.8MHz)/ Max192 × Fs(9.2MHz)
SCK
SCKP = 1, WSP = 0
SCKP = 0, WSP = 0
SCKP = 1, WSP = 1
SCKP = 0, WSP = 1
RFMT1 = 0:MSB first, RFMT1 = 1:LSB first
Serial Sound Interface timing (4)
Fs = 48 kHz or 44.1kHz
WS
RXEN
SCK = Min 64 × Fs (2.8MHz)/ Max192 × Fs(9.2MHz)
SCKP = 1, WSP = 0
SCKP = 0, WSP = 0
SCKP = 1, WSP = 1
SCKP = 0, WSP = 1
RFMT0 = 0:MSB first, RFMT0 = 1:LSB first
Figure 2.6.6. Example of Serial Sound Interface receive timing
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2. Serial sound interface
2.6.3 Precautions for Serial Sound Interface
Description For flash memory version SSI transmission data must be latched as the following timing by
a receiver.
• SCKP=0 (falling edge) : within 3 BCLK cycles from the rising edge of SCK
• SCKP=1 (rising edge) : within 3 BCLK cycles from the falling edge of SCK
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2. Frequency synthesizer (PLL)
2.7 Frequency synthesizer (PLL)
This paragraph explains the registers setting method and the notes related to the frequency synthesizer
(PLL circuit).
2.7.1 Overview
The frequency synthesizer generates the 48MHz clock that is necessary for the USB block and the fSYN
clock. These clocks are a multiple of the external input standard clock f(XIN). Figure 2.7.1 shows the
frequency synthesizer circuit block diagram.
f
USB
EN
USBC5
f
VCO
LS
f
SYN
Frequency
Divider
f
PIN
f(XIN
)
Frequency
Multiplier
Prescaler
FSCCR0
8 Bit
FSD
FSM
FSP
FSC
)
FSCCR
(03DB16)
(03DD16
)
(03DF16)
(03DC16
(03DE16
)
Data Bus
Figure 2.7.1. Frequency synthesizer circuit block diagram
(1) Related Registers
Figure 2.7.2 shows a memory location diagram for the frequency synthesizer related registers; Fig-
ures 2.7.3 and 2.7.4 show the composition of the frequency synthesizer related registers.
000A16
Protect register (PRCR)
03DB16
03DC16
03DD16
03DE16
03DF16
Frequency synthesizer clock control register (FSCCR)
Frequency synthesizer control register (FSC)
Frequency synthesizer multiply register (FSM)
Frequency synthesizer prescaler register (FSP)
Frequency synthesizer divide register (FSD)
Figure 2.7.2. Memory map of frequency synthesizer related registers
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2. Frequency synthesizer (PLL)
Frequency Synthesizer Control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FSC
Address
03DC16
When reset
01100000
0 0
2
Bit Symbol
FSE
Bit Name
Function
0 : Disabled
R
W
O
O
Frequency synthesizer enable bit
1 : Enabled
b2 b1
VCO0
0 0 : Lowest gain
0 1 : Low gain
1 0 : High gain (Note 1)
1 1 : Highest gain
O
O
O
O
VCO gain control bit
VC01
Reserved bit
CHG0
Must always be set to “0”
b6 b5
O
O
O
0 0 : Disabled
O
O
0 1 : Low current
1 0 : Medium current (Note 1)
1 1 : High current
LPF current control bit (Note 2)
O
O
CHG1
LS
0 : Unlocked
1 : Locked
Frequency synthesizer lock status bit
O
Note 1: Recommended.
Note 2: Bits 6 and 5 are set to (bit 6,bit 5)=(1,1) at reset. When using the frequency synthesizer,
we recommend to set to (bit 6,bit 5)=(1,0).
Frequency Synthesizer Clock Control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FSCCR
Address
03DB16
When reset
000000002
0 0 0
0 0
0
Bit Symbol
Bit Name
Function
R
W
O
0 : Xin
1 : fSYN
O
Clock source selection
FSCCR0
Reserved
FCCR4
O
O
O
O
Must always be set to “0”
0 : Normal
1 : Divide-by-3
Divide-by-3 option
Reserved
O
O
Must always be set to “0”
Figure 2.7.3. Frequency synthesizer registers (1)
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2. Frequency synthesizer (PLL)
Frequency Synthesizer Prescaler Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FSP
Address
03DE16
When reset
11111111
2
Bit Symbol
FSP
Bit Name
Function
Generates fPIN
R
O
W
O
Frequency synthesizer
prescaler value
fPIN =f(XIN)/2(n + 1)
n: FSP value
Frequency Synthesizer Multiply Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FSM
Address
03DD16
When reset
111111112
Bit Symbol
FSM
Bit Name
Function
Generates fVCO by multiplying fPIN
R
O
W
Frequency synthesizer
multiplier value
O
fVCO = fPIN X 2(n + 1)
n: FSM value
Frequency Synthesizer Divide Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
03DF16
When reset
111111112
FSD
Bit Symbol
FSD
Bit Name
Function
R
O
W
O
Frequency synthesizer
divider value
Generates fSYN by dividing fVCO
fSYN =fVCO/2(m + 1)
m: FSD value
Figure 2.7.4. Frequency synthesizer registers (2)
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2. Frequency synthesizer (PLL)
2.7.2 Operation of frequency synthesizer
The following explains how to setup after hardware reset. Table 2.7.1 to 2.7.3 show frequency synthe-
sizer related registers setting examples.
Operation
(1) Cancel the protect register.
(2) Set the frequency synthesizer related registers to generate the 48MHz clock that is necessary
for the fUSB.
(3) Enable the frequency synthesizer by setting frequency synthesizer control register.
(4) The protect register should be set to write disabled. A 3ms wait is necessary.
(5) The frequency synthesizer locked status bit should be checked. It is necessary to recheck
after a wait of 0.1ms if it is “0” (unlocked).
(6) Enable USB clock.
(7) After waiting four cycles of the φ or greater, the USB enable bit should be set to “1”.
A minimum delay of 250ns is needed before performing any other USB related registers read/
write operations.
ꢀPrescaler
Clock f(XIN) is prescaled down by the frequency synthesizer prescaler register (FSP) to generate fPIN.
When the frequency synthesizer prescaler register is set at 255, the prescaler is disabled and fPIN =
f(XIN). Table 2.7.1 shows some examples of how the frequency synthesizer prescaler register is set.
fPIN = f(XIN) / 2(n+1) n: FSP value
Note: The value of fPIN should not be set below 1 MHz.
Table 2.7.1. Example of setting the frequency synthesizer prescaler register (FSP)
FSP Value
Dec (Hex)
fX(IN)
f
PIN
12 MH
Z
255 (FF16
)
12.00 MH
16.00 MH
12.00 MH
16.00 MH
12.00 MH
12.00 MH
12.00 MH
Z
Z
Z
Z
Z
Z
Z
1 MH
1 MH
2 MH
2 MH
3 MH
6 MH
Z
7 (0716
5 (0516
3 (0316
2 (0216
1 (0116
0 (0016
)
)
)
)
)
)
Z
Z
Z
Z
Z
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2. Frequency synthesizer (PLL)
ꢀFrequency Multiplier
fVCO is generated via the Frequency Synthesizer Mul-tiply register (FSM: address 03DD16). When the
Frequency Multiply register is set to 255, multiplication is disabled and fVCO = fPIN. The value of n
should be set so that fVCO becomes 48MHz. Table 2.7.2 shows some examples of how the frequency
synthesizer multiply register is set.
fVCO = fPIN X 2(n+1) n: FSM value
Table 2.7.2. Example of Setting the Frequency Multiply Register (FSM)
FSM Value
f
VCO
f
PIN
Dec (Hex)
23 (1716
1 MH
2 MH
4 MH
6 MH
8 MH
Z
Z
Z
Z
Z
48 MH
48 MH
48 MH
48 MH
48 MH
48 MH
Z
Z
Z
Z
Z
Z
)
11 (0B16
)
5 (0516
3 (0316
2 (0216
1 (0116
)
)
)
)
12 MH
Z
ꢀFrequency Divider
Clock fSYN is a divided down version of fVCO. fSYN is generated via the frequency synthesizer divide
register (FSD). When the frequency synthesizer divider register is set to 255, division is disabled and
fSYN = fVCO. Table 2.7.3 shows some examples of how the frequency synthesizer division register is
set.
fSYN = fVCO / 2(m+1) m: FSD value
Note 1: Set fSYN to 12MHz or lower.
Table 2.7.3. Example of Setting the frequency synthesizer divide register (FSD)
FSD Value
Dec (Hex)
f
SYN
f
VCO
12.00 MH
8.00 MH
Z
Z
1 (0116
2 (0216
2 (0216
3 (0316
)
)
)
)
48 MH
Z
16.00 MH (Note 1)
Z
6.00 MH
187.50 kH
Z
Z
127 (7F16
)
Note 1: fSYN=fVCO/(m+1) when FSCCR4=1 and m=2.
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2. Frequency synthesizer (PLL)
2.7.3 Precautions for Frequency synthesizer
(1) Bits 6 and 5 of frequency synthesizer control register are set to (bit6, bit5)=(1, 1) at reset. When using
the frequency synthesizer, we recommended to set to (bit6, bit5)=(1, 0).
(2) Set fSYN to 12 MHz or lower.
(3) The value of fPIN should not be set below 1 MHz.
(4) When the frequency synthesizer is enabled, do not use the output of the frequency synthesizer until
after a 2~5ms delay. That will stabilize the output. Also, after the frequency synthesizer has been
enabled, because the output is temporarily (2-5ms) unstable, the contents of none of the registers
should be changed.
(5) When using the frequency synthesizer, connect a low pass filter to the LPF terminal.
(6) The following setup for the frequency synthesizer should be done after hardware resest.
1. Cancel the protect register.
2. Set the frequency synthesizer related registers to generate the 48MHz clock that is necessary for
the fUSB.
3. Enable the frequency synthesizer by setting frequency synthesizer control register.
4. The protect register should be set to write disabled. A 3ms wait is necessary.
5. The frequency synthesizer locked status bit should be checked. It is necessary to recheck after a
wait of 0.1ms if it is “0” (unlocked).
6. Enable USB clock.
7. After waiting four cycles of the f or greater, the USB enable bit should be set to “1”.
A minimum delay of 250ns is needed before performing any other USB related registers read/write
operations.
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2. USB function
2.8 USB function
2.8.1 Overview
The USB function control unit of the M30245 group is compliant with USB2.0 specification and supports
Full-Speed transfer. USB2.0 specification defines the following four kinds of transfer types:
ꢀ Control Transfer
ꢀ Isochronous Transfer
ꢀ Interrupt Transfer
ꢀ Bulk Transfer
The USB function control unit is provided with 9 endpoints including endpoint 0, endpoints 1 to 4 OUT
(receive) and endpoints 1 to 4 IN (transmit), each of which having an FIFO. The endpoint 0 can apply only
to the control transfer (same in transfer form as the bulk transfer); while endpoints 1 to 4 IN/OUT can
apply to the bulk transfer, isochronous transfer and interrupt transfer. The size and the starting position of
endpoints 1 to 4 IN/OUT FIFO can be set according to the user's system (The size and the starting
position of endpoint 0 IN/OUT FIFO are fixed). Further, when the double buffer mode is enabled, the
buffer which has twice as much as the set size is available for the IN/OUT FIFO. When the continuous
receive/transmit mode is enabled, data can be transferred at a high speed (in bulk transfer).
The USB related interrupts include USB suspend interrupt, USB resume interrupt, USB reset interrupt,
USB endpoint 0 interrupt, USB function interrupt, and USB SOF interrupt. The USB function control unit
can control the state transition of the USB device based on these interrupt requests.
(1) Transfer Type
The USB specifications largely concern 2 types, including the one for the host side (PC/Hub) to control
the connected peripheral devices and the other for the peripheral device side (Device) which is con-
nected to the real machine. Further, depending on the number of data dealt with in the device, the
peripheral devices which require more data (concerning image, audio, etc.) at one time have the
communication specification with high transfer speed (12Mbps) called Full-Speed function, while the
peripheral devices (keyboard, mouse) which require less data have the communication specification
with low transfer speed (1.5Mbps) called Low-Speed function. Further, a communication specification
with even higher speed is available which is called Hi-Speed function (480Mbps).
These communication specifications are each determined by device class of the peripheral devices
and the transfer type to be used is determined for each peripheral device.
The M30245 group supports the following four kinds of transfer types:
ꢀ Control Transfer
This transfer is used for communication of request-response form (bi-directional) in aperiodic com-
munication which occurs suddenly. This is mainly used at the time of setup. As all the devices have
to be supported in the standard device request, control transfer is supported without any exception
for the devices compliant with USB.
ꢀ Bulk Transfer
This transfer is used to transfer the data which delay does not cause any problem in aperiodic com-
munication which occurs suddenly. This is used to transfer large quantities of data.
Hardware detects errors in order to guarantee transfer data. A request for retransmission is issued
by detecting of any error. For example, they include the output data from printer and image data of
scanner.
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2. USB function
ꢀ Interrupt Transfer
This transfer is used to notify the host of aperiodic and low-frequency data from the device. For
example, they include the notification of out of paper in printer and data concerning devices such as
the mouse and the keyboard.
ꢀ Isochronous Transfer
This transfer is used for continuous and periodic communication. Once the communication path is
established, a transfer rate is guaranteed with a limited delay. The maximum size of transfer data is
specified by the endpoint, which is read by the host as the configuration data of the device. Based on
this data, transfer within the frame is scheduled and the bus time required for transfer of the maxi-
mum size of data is secured with preference. Although the band width and the transfer rate of data
transfer are guaranteed, retransmission is not executed even if an error exists in the transfer. This is
used for streaming data such as animation and audio data which requires real time.
(2) Communication Protocol
Host CPU has the initiative for the entire USB communication. Even when data are transmitted to the
host from the device, the host gives the right of use to the device before data are transmitted. The
host, in order to process multiple transfers simultaneously, schedules each transfer in packet unit
within a frame of 1ms interval. The frames image is shown below:
1ms
1ms
printer/scanner
1ms
mouse
SOF
SOF mouse
Audio
SOF Audio
Audio
printer/scanner
printer/scanner
Isochronous trasnfer
Interrupt trasnfer
Bulk trasnfer
Figure 2.8.1. Frame image
ꢀ Packet
A packet is the unit in which the host CPU or the device secures a bus. In the USB, data are transmit-
ted/received in the packet unit.
A packet is a group of bit data strings (fields), which starts with the SOP (Start-of-Packet) as a part of
the SYNC (synchronous data) field. This is followed by the PID field which identifies a packet type
and, then, each data field of a frame number/ address/ data field, etc., finally ending with EOP (End-
of-Packet) which indicates the end of a packet. The packet types and formats are shown below:
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2. USB function
SOF Packet: Packet to start the frame to be issued from the host for every 1ms.
8 bits
PID
8 bits
Frame number
5 bits
CRC5
PID: SOF(0xA5)
Token Packet: Packet to be issued from the host at the time of transaction start.
8 bits 7 bits 4 bits 5 bits
ADDR
PID
ENDP CRC5
PID: OUT(0xE1),IN(0x69),SETUP(0x2D)
Data Packet: Packet to use at the time of data transfer.
8 bits
PID
16 bits
0 to 1034 bytes
DATA
CRC16
PID: DATA0(0xC3),DATA1(0x4B)
Hand Shake Packet: Packet to use at the transaction which controls flow.
8 bits
PID
PID: ACK(0xD2),NAK(0xA5),STALL(0x1E)
Note: In each packet, there are SOP as start of packet, and EOP as end of packet.
Figure 2.8.2. Kinds of packet
Table 2.8.1. List of USB packet recognitions
Process overview
PID type
Token
PID name
SETUP
IN
Reports the operation request to device by the host CPU
Requests the data transmit to device by the host CPU
Requests the data receive to device by the host CPU
Indicates the start of frame to device by the host CPU
OUT
SOF
Indicates that the sequence bit of transmit/receive data is even number
Indicates that the sequence bit of transmit/receive data is odd number
Reports that the transmit data was correctly completed
DATA
DATA0
DATA1
ACK
Handshake
Reports that the device is in the communication wait state
Reports that the communication was incorrectly completed
NAK
STALL
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2. USB function
ꢀ Transaction
A transaction is the unit in which the host CPU schedules one frame. Each transaction is config-
ured with packet, and the transaction types are determined according to the configuration pat-
tern. The transaction types and formats are shown below:
ꢀIN transaction
ꢀOUT transaction
(idle state)
ꢀSETUP transaction
(idle state)
(idle state)
SETUP
DATA0
ACK
IN
OUT
NAK STALL
DATA0/1
ACK
DATA0/1
ACK NAK STALL
(idle state)
(idle state)
(idle state)
ꢀIsochronous transaction (OUT)
(idle state)
ꢀIsochronous transaction (IN)
(idle state)
IN
OUT
DATA0
(idle state)
DATA0
(idle state)
Token packet issued by the host
Handshake packet issued by the host
Data packet issued by the host
Data packet issued by the device
Handshake packet issued by the device
Figure 2.8.3. Formats of transactions
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2. USB function
ꢀ Communication Sequence
The control transfer is used common to all devices at the time of setup, which consists of three kinds
of stages being combined for one processing. The control transfer starts with setup stage. According
to the content, data stage (control read transfer or control write transfer) is executed, followed by
status stage being executed to finally complete one processing. In control transfer, use of endpoint 0
has been specified.
The communication sequence of control transfer is shown in Figure 2.8.4.
Control trasnfer
ꢀControl Read
SETUP stage
DATA stage
IN
Status stage
OUT
SETUP
DATA0
DATA1/0
DATA1
Handshake
Handshake
Handshake
ꢀControl Write
SETUP stage
DATA stage
OUT
Status stage
IN
SETUP
DATA0
DATA1/0
DATA1
Handshake
Handshake
Handshake
ꢀNo-data Control
SETUP stage
Status stage
IN
SETUP
DATA0
DATA1
: Host issues
Handshake
Handshake
: Device issues
Figure 2.8.4. Control transfer communication sequence
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2. USB function
ꢀ Control Read Transfer
In setup stage, host notifies the device that it is control read transfer. Then, in data stage, data are
transmitted from the device to host through repetition of IN transaction. Finally, in status stage, OUT
transaction is executed (that the host transmits an empty packet of data length (0) to the device) to
complete the control read transfer.
ꢀ Control Write Transfer
In setup stage, host notifies the device that it is control write transfer. Then, in data stage, data are
transmitted from the host to device through repetition of OUT transaction. Finally, in status stage, IN
transaction is executed (that the device transmits an empty packet of data length (0) to the host) to
complete the control write transfer.
ꢀ No Control Data Transfer
In setup stage, host notifies the device that it is no control data transfer. Then, in status stage, IN
transaction is executed (that the device transmits an empty packet of data length (0) to the host) to
complete the no control data transfer.
The execution result of setup stage and data stage are notified to host CPU in status stage. For
details of response format of control transfers, refer to USB2.0 specification.
ꢀ Device Request
Concerning setup transaction in the setup stage of control transfer, format of its data phase has been
defined, which is called device request.
For standard (0) type, it is called standard device request, which is the basic device request to be
supported by all the USB devices.
For class (1) type, it is called class request. The USB implementers forum (USB IF) defines a device
class, and determines the configuration required in the class and the class request.
For each data format of the device request, refer to USB2.0 specification or the specification for each
class.
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2. USB function
(3) Bulk Transfer
ꢀ Bulk IN Transfer
In bulk IN transfer which data are transmitted from the device to the host CPU, IN transactions are
repeated. When transmit data are available in IN FIFO, the M30245 group issues a data packet to
the IN token. When, during the handshake phase of each transaction, the M30245 group has nor-
mally received ACK packet issued by the host PC, it toggles DATA0 and DATA1 of data packet on
next data phase. This serves to ensure handshake. The M30245 group executes the following re-
sponses when the data are not transmitted normally:
•When the received IN token is destroyed, response is not executed.
•When ACK handshake was not included in the transmit data, it is retransmitted on next IN token.
•When the M30245 group was stalling, STALL handshake is returned.
•When the transmit data are not available in IN FIFO, NAK handshake is returned.
ꢀ Bulk OUT Transfer
In bulk OUT transfer which data are transmitted from the host CPU to the device, OUT transactions
are repeated.
The M30245 group has normally received a data packet, and then returns ACK handshake. Normal
receiving is the status which is free of any bit stuffing error or CRC error and which data PID have
been correctly received. When, during the handshake phase of each transaction, the host PC has
normally received ACK packet issued by the M30245 group, it toggles DATA0 and DATA1 of data
packet on next data phase. This serves to ensure handshake. The M30245 group executes the
following responses when the data are not received normally:
•When the received OUT token is destroyed, response is not executed.
•When the M30245 group was stalling, STALL handshake is returned. Also, when the packet,
which is exceeding receivable data size, is transmitted, STALL handshake is returned.
•When inconsistency of the sequence bits is detected in the received data, ACK handshake is returned.
•When OUT FIFO of the M30245 group could not receive full data, NAK handshake is returned.
For details, refer to USB2.0 specification.
ꢀBulk OUT
ꢀBulk IN
(Idle state)
(Idle state)
OUT
IN
DATA0/1
DATA0/1
NAK
STALL
Data
error
ACK *1
ACK *1
STALL
NAK
: Host issues
: Device issues
(Idle state)
(Idle state)
*1: The data toggle bit is toggled at the next phase.
(DATA0 → DATA1 or DATA1→ DATA0)
Figure 2.8.5. Bulk transfer
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2. USB function
(4) Isochronous Transfer
ꢀ Isochronous IN Transfer
In isochronous IN transfer which data are transferred from the device to the host CPU, isochronous
(IN) transactions are repeated. Isochronous transaction does not have the handshake phase. The
data packet consists only of DATA0. Toggling with DATA1 is not performed. When transmit data is
available in IN FIFO, the M30245 group issues a data packet to the IN token. The M30245 group
executes the following responses when the data are not transmitted normally:
•When the received IN token is destroyed, the data are not issued.
•When the transmit data are not available in IN FIFO, an empty packet of data length (0) is issued.
ꢀ Isochronous OUT Transfer
In isochronous OUT transfer which data are transferred from the host CPU to the device, isochro-
nous (OUT) transactions are repeated. Isochronous transaction does not have the handshake
phase. The data packet consists only of DATA0. Toggling with DATA1 is not performed.
The M30245 group has received a data packet, indicates whether or not the data content is normal
by using a status flag. The M30245 group executes the following responses when the data are not
received normally:
•When the received OUT token is destroyed, the data are not received.
•When the received data are destroyed (bit stuffing error or CRC error occur), the data are received.
•When the packet, which is exceeding receivable data size, is transmitted, the data are not received.
•When OUT FIFO of the M30245 group could not receive the full data, the data are not received.
ꢀIsochronous OUT
ꢀIsochronous IN
(Idle state)
(Idle state)
IN
OUT
DATA0
DATA0
: Host issues
(Idle state)
(Idle state)
: Device issues
Figure 2.8.6. Isochronous transfer
(5) Interrupt Transfer
This transfer form is same as the bulk transfer. Refer to “(3) Bulk Transfer” of this manual.
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2. USB function
(6) Device State
The device has states and, transits between the states. The M30245 group does not execute state
transition on the hardware. Control it by the software based on requests of the related USB interrupt
request. The device state transition is shown in Figure 2.8.7.
A series of processes from bus connection to configuration is called “emulation”. Each state is ex-
plained as follows:
ꢀConnection State:
This is the state which the device has been connected to the bus.
ꢀPowered State:
This is the state where the hub has been completed the configuration and has been supplied power
to the bus.
ꢀDefault State:
This is the state where the reset signal has been received from the host CPU. It is responded as
default address (0). This is the unconfigured state (configuration 0).
ꢀAddress State:
This is the state which the SET_ADDRESS standard device request has been received and a device
address other than “0” has been assigned. This is the unconfigured state (Configuration 0).
ꢀConfigured State
This is the state which endpoint 0 has been received the SET_CONFIGURATION standard device
request and the device has been configured.
ꢀSuspend State
This is the state which inactive state followed 3ms or more.
If a bus active has been detected, the state shifts to the former one. In the M30245 group, when a bus
reset is detected in suspend state, detects bus active and shifts to the former state, then, detects the
bus reset.
(7) USB Related Registers Memory Mapping
The USB related registers memory mapping is shown in Figure 2.8.8. The list of USB related registers
items is shown in Table 2.8.2.
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2. USB function
Attached
state
Hub
Hub
Configured
Deconfigured
Suspend detected (USB suspend interrupt)
Powered
state
Suspend
state
Resume detected (USB resume interrupt)
USB bus reset detected
(USB reset interrupt)
USB bus reset detected
(USB reset interrupt)
Suspend detected (USB suspend interrupt)
Default
state
Suspend
state
Resume detected (USB resume interrupt)
Execute SetAddress (USB function interrupt)
(DeviceAddress=01h to 7Fh)
Suspend detected (USB suspend interrupt)
Suspend
state
Address
state
Resume detected (USB resume interrupt)
Execute SetConfiguration
Execute SetConfiguration
(USB function interrupt)
(Configuration Value≠0)
(USB function interrupt)
(Configuration Value=0)
Suspend detected (USB suspend interrupt)
Suspend
state
Configured
state
Resume detected
(USB resume interrupt)
Figure 2.8.7. Device state transition
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2. USB function
02B616
02B716
USB EP1 OUT control/status register (EP1OCS)
000C16
001F16
004616
USB control register (USBC)
02B816
02B916
02BA16
USB EP1 OUT max packet size register (EP1OMP)
USB EP1 OUT write count register (EP1WC)
USB Attach/Detach register (USBAD)
02BB16
02BC16
02BD16
02BE16
USB Endpoint 0 interrupt control register (EP0IC)
USB suspend interrupt control register (SUSPIC)
USB resume interrupt control register (RSMIC)
USB EP1 OUT FIFO configuration register (EP1OFC)
USB EP2 OUT control/status register (EP2OCS)
USB EP2 OUT max packet size register (EP2OMP)
005616
005816
02BF16
02C016
02C116
02C216
005A16
005B16
005C16
005D16
USB reset interrupt control register (RSTIC)
USB SOF interrupt control register (SOFIC)
USB Vbus detect interrupt control register (VBDIC)
USB function interrupt control register (USBFIC)
USB EP2 OUT write count register (EP2WC)
02C316
02C416
USB EP2 OUT FIFO configuration register (EP2OFC)
02C516
02C616
02C716
02C816
028016
028116
USB EP3 OUT control/status register (EP3OCS)
USB EP3 OUT max packet size register (EP3OMP)
USB address register (USBA)
028216
028316
USB power management register (USBPM)
USB interrupt status register (USBIS)
USB interrupt clear register (USBIC)
02C916
02CA16
USB EP3 OUT write count register (EP3WC)
USB EP3 OUT FIFO configuration register (EP3OFC)
USB EP4 OUT control/status register (EP4OCS)
USB EP4 OUT max packet size register (EP4OMP)
USB EP4 OUT write count register (EP4WC)
028416
028516
02CB16
02CC16
028616
028716
028816
02CD16
02CE16
USB interrupt enable register (USBIE)
02CF16
02D016
02D116
028916
028A16
028B16
028C16
028D16
USB frame number register (USBFN)
USB ISO control register (USBISOC)
02D216
02D316
02D416
02D516
USB EP4 OUT FIFO configuration register (EP4OFC)
028E16
028F16
029016
USB endpoint enable register (USBEPEN)
USB DMA0 request register (USBDMA0)
USB DMA1 request register (USBDMA1)
USB DMA2 request register (USBDMA2)
029116
029216
029316
029416
USB reserved
02D816
02D916
02DA16
02DB16
02DC16
02DD16
02DE16
02DF16
USB reserved
USB reserved
029516
029616
USB reserved
USB DMA3 request register (USBDMA3)
USB EP0 control/status register (EP0CS)
029716
029816
USB reserved
USB reserved
029916
029A16
USB reserved
USB reserved
USB EP0 max packet size register (EP0MP)
029B16
029C16
029D16
02E016
02E116
02E216
02E316
02E416
USB EP0 IN FIFO (EP0I)
USB EP0 OUT write count register (EP0WC)
USB EP1 IN control/status register (EP1ICS)
USB EP1 IN max packet size register (EP1IMP)
USB EP1 IN FIFO configuration register (EP1IFC)
029E16
029F16
USB EP0 OUT FIFO (EP0O)
02A016
02A116
USB EP1 IN FIFO (EP1I)
USB EP1 OUT FIFO (EP1O)
USB EP2 IN FIFO (EP2I)
USB EP2 OUT FIFO (EP2O)
02E516
02E616
02A216
02A316
02A416
02A516
02A616
02E716
02E816
02E916
USB EP2 IN control/status register (EP2ICS)
USB EP2 IN max packet size register (EP2IMP)
USB EP2 IN FIFO configuration register (EP2IFC)
02EA16
02EB16
02A716
02A816
02EC16
USB EP3 IN FIFO (EP3I)
USB EP3 OUT FIFO (EP3O)
USB E4 IN FIFO (EP4I)
02A916
02ED16
02EE16
02AA16
02AB16
USB EP3 IN control/status register (EP3ICS)
USB EP3 IN max packet size register (EP3IMP)
USB EP3 IN FIFO configuration register (EP3IFC)
02EF16
02F016
02AC16
02AD16
02F116
02F216
02AE16
02AF16
02B016
02B116
02B216
USB EP4 OUT FIFO (EP4O)
02F316
USB EP4 IN control/status register (EP4ICS)
USB EP4 IN max packet size register (EP4IMP)
USB EP4 IN FIFO configuration register (EP4IFC)
02B316
02B416
02B516
Figure 2.8.8. USB registers memory mapping
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2. USB function
Table 2.8.2. List of USB Related Registers Items
Section name
Register name
USB control register, USB Attach/Detach register,
USB endpoint enable register,
2.8.2 USB function control
USB endpoint x(x=0-4) IN FIFO data register,
USB endpoint x(x=0-4) OUT FIFO data register
USB function interrupt status register,
USB function interrupt clear register,
2.8.3 USB Interrupt
USB function interrupt enable register, USB frame number register
USB power management register
2.8.4 USB Operation
(Suspend/Resume Function)
2.8.5 USB Operation
(Endpoint 0)
USB address register,
USB endpoint 0 control and status register,
USB endpoint 0 MAXP register,
USB endpoint 0 OUT write count register
USB endpoint x(x=1-4) OUT control and status register,
USB endpoint x(x=1-4) OUT MAXP register,
USB endpoint x(x=1-4) OUT write count register,
USB endpoint x(x=1-4) OUT FIFO configuration register
USB ISO control register,
2.8.6 USB Operation
(Endpoint 1-4 reception)
2.8.7 USB Operation
USB endpoint x(x=1-4) IN control and status register,
USB endpoint x(x=1-4) IN MAXP register,
USB endpoint x(x=1-4) IN FIFO configuration register
USB DMAx(x=0-3) request register
(Endpoint 1-4 transmission)
2.8.8 USB Operation
(Interface of USB and DMAC transfer)
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2. USB function
2.8.2 USB function control
The USB function control unit needs to be enabled for using the USB function. The initialization procedure
of the USB function control unit is explained below:
(1) Related Registers
ꢀꢀ USB control register
This register is used to control each operation of the USB function control unit. When using the USB
function, be sure to set USB clock enable bit to “1” before USB enable bit is set to “1”. This register is
not affected by the USB reset signal. After the USB is enabled (USBC7 =“1”), a minimum 187.5 ns of
delay (three cycles of BCLK) is required before performing any other USB register read/write opera-
tions.
•USB clock enable bit
This bit is used to enable/disable the USB clock (fusb). This clock is supplied from frequency synthe-
sizer and is required for the USB operation. Set this bit to “1” when enabling the USB clock.
________
•USB SOF port select bit
This bit is used to enable/disable a SOF signal output on the P92 pin. Set this bit to “1” when using the
USB SOF signal. In this case, set the port P92 to output mode. When this bit is set to “1”, low pulse is
always output for about 166ns (2 cycles of the 12MHz USB clock) at start of the frame packet.
•USB enable bit
This bit is used to enable/disable the USB block. When this bit is set to “1”, USB function is enabled.
After setting “1” to this bit, wait for at least 250ns and, then, read or write the other USB related
register.
The configuration of USB control register is shown in Figure 2.8.9.
USB Control register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
Symbol
USBC
Address
000C16
When reset
0016
Function
Bit Name
R
W
O
Bit Symbol
Reserved
O
Must always be set to “0”
USB clock enable bit
USB SOF port select bit
USB enable bit
0 : Disable
1 : Enable
USBC5
USBC6
USBC7
O
O
O
O
0 : Disable (Note 1)
1 : Enable
O
O
0 : Disable (Note 2)
1 : Enable
Note 1: P9
2 is used as GPI/O pin.
Note 2: All USB internal registers are held at their default values.
Figure 2.8.9. USB control register
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2. USB function
ꢀ USB attach/detach register
This register is used to control attach/detach from the USB host without physically attaching/detaching
the USB cable.
•Port 90-Second bit
The port P90 operates as standard port when this bit is set to “0”. Connect a 1.5kΩ resistance
between the USB D+ pin and the Uvcc pin. (The timing of D+ line pull-up is depending on the Uvcc
pin.)
When this bit is set to “1”, the P90 has the USB attach/detach function, serving as the power supply
pin for pull-up to the D+ line. When using the USB attach/detach function, be sure to connect be-
tween the USB D+ pin and the P90/ATTACH pin via a 1.5kΩ pull-up resistance. Also, in either case,
be sure to connect the UVcc pin to the power source.
•Attach/detach bit
This bit is valid when port 90-Second bit is set to “1”. When this bit is set to “0”, supply of UVcc pin
voltage to P90 is stopped and the USB cable becomes a detach state artificially. When this bit is set
to “1”, the USB cable becomes a attach state artificially since the Uvcc pin voltage is supplied to the
P90 and D+ line is pulled up. After frequency synthesizer is stabilized, set “1” (attach state) to this bit.
•Vbus detect enable bit
This bit is used to enable Vbus detection by setting to “1”. When enabling the Vbus detection, con-
nect the Vbus pin of USB connector to a VbusDTCT pin.
When attach/detach bit is changed from “0” to “1” or from “1” to “0”, time required till the host recog-
nizes attach/detach varies according to board resistance factor/ capacity factor/ USB cable capacity of
the device, host's board characteristics, and processing speed. Perform sufficient evaluation through
controlling attach/detach bit in accordance with the actual user's system.
The configuration of USB attach/detach register is shown in Figure 2.8.10.
USB Attach/Detach Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
USBAD
Address
001F16
When reset
0016
0 0 0 0 0
Bit symbol
P90-second
Bit name
0-Second
Function
0 : Normal mode for Port 9
R W
0
Port 9
1 : Forces Port 90 to operate as pull up for D+.
Attach/
Detach
0 : ATTACH
1 : DETACH
Attach/Detach
Must always be set to “0”
Reserved
VBDT
0 : Disabled
1 : Enabled
Vbus detect enable
Figure 2.8.10. USB Attach/Detach register
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2. USB function
ꢀ USB endpoint enable register
Endpoints 1 to 4 are used to enable endpoint IN/OUT FIFOs for use. The endpoint 0 is always enabled
and cannot be disabled by software. All Endpoints 1 to 4 are disabled after reset.
The configuration of USB endpoint enable register is shown in Figure 2.8.11.
USB Endpoint Enable register
(b8)
b0
(b15)
b7
b7
b0
Symbol
USBEPEN
Address
028E16
When reset
000016
0
0
0
0
0
0
0
0
Bit Symbol
Bit Name
EP1 OUT enable
Function
R
O
W
O
EP1_OUT
EP1_IN
0 : Disabled
1 : Enabled
EP1 IN enable
EP2 OUT enable
EP2 IN enable
EP3 OUT enable
EP3 IN enable
EP4 OUT enable
EP2_OUT
EP2_IN
EP3_OUT
EP3_IN
EP4_OUT
EP4_IN
EP4 IN enable
Must always be “0”
Reserved
O
O
Figure 2.8.11. USB endpoint enable register
ꢀ USB endpoint x(x=0 to 4) IN FIFO data register
Endpoints 0 to 4 respectively have their IN FIFOs. At the time of transmission to the host PC, write the
transmit data in these registers. Access these registers in word cycle or byte cycle to the lower byte.
The configuration of USB x(x=0~4) IN FIFO data register is shown in Figure 2.8.12.
USB Endpoint x IN FIFO Data register
(b8)
b0
(b15)
b7
b7
b0
Address
02E016, 02E416, 02E816
02EC16, 02F016
Symbol
EPxI (x = 0 - 4)
When reset
N/A
,
R
X
W
O
Bit Symbol
DATA_15-0
Bit Name
EP0 IN FIFO Data
Function
Write transmit data to this register
Note 1: Data is undefined if this register is read.
Note 2: Write only to this register with a Word command or a Byte command to the lower 8 bits.
Do not write a byte of data to the upper 8 bits. (b8 - b15)
Figure 2.8.12. USB x(x=0~4) IN FIFO data register
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2. USB function
ꢀ USB endpoint x(x=0 to 4) OUT FIFO data register
Endpoints 0 to 4 respectively have their OUT FIFOs. When data are received from the host PC, read
the receive data from these registers. Access these registers in word cycle or byte cycle to the lower
byte.
The configuration of USB x(x=0~4) OUT FIFO data register is shown in Figure 2.8.13.
USB Endpoint x OUT FIFO Data register
(b8)
b0
(b15)
b7
b7
b0
Address
02E216, 02E616, 02EA16
02EE16, 02F216
Symbol
EPxO (x = 0 - 4)
When reset
N/A
,
R
O
W
X
Bit Symbol
DATA_15-0
Bit Name
EP0 OUT FIFO Data
Function
Read receive data
from this register
Note 1: Writing to this register might cause a system error.
Note 2: Read only from this register with a Word command or a Byte command to the lower 8
bits. Do not read a byte of data from the upper 8 bits. (b8 - b15)
Figure 2.8.13. USB x(x=0~4) OUT FIFO data register
The endpoint x IN/OUT FIFO mapping is shown in Figure 2.8.14.
Endpoint FIFO
64 bytes
64 bytes
This area is allocated for IN/OUT FIFOs of the endpoint 1 to 4.
The FIFO size and start position can be specified for every 64-byte by
USB EPx IN FIFO configuration register and USB EPx OUT FIFO configuration register.
3328 bytes
Endpoint 0
IN FIFO: 128 bytes,
OUT FIFO: 128 bytes
256 bytes
Figure 2.8.14. Endpoint x IN/OUT FIFO mapping
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2. USB function
(2) Enable of USB Function Control Unit
The initialization procedure of the USB function control unit of the M30245 group after hardware reset
is explained below. Further, for power supply being supplied from the USB, the total driving current
has to be controlled to keep equal to or below 100mA.
ꢀ Setting of the frequency synthesizer
1: Clear protect.
2: Set the frequency synthesizer related registers to generate 48MHz required for the fUSB.
3: Enable the frequency synthesizer by setting bit 0 in the frequency synthesizer control register to
“1”.
4: Disable protect.
5: Wait for 3ms to stabilize the frequency synthesizer.
6: Check frequency synthesizer lock status bit. If the frequency synthesizer is in unlock state, waiting
for 0.1ms and rechecking are repeated.
ꢀ Setting of the USB function control unit
7: Set the USBC5 to “1” to enable the USB clock.
8: Set the USB attach/detach register to “0316” (Port P90 is set as the power supply pin for pull-up to
the D+ line), and set the USBC7 to “1” to enable the USB block. For operation of the USB related
registers, a minimum 187.5ns of wait (three cycles of BCLK) is required.
Initialize the endpoint to be used after the USB function control unit being enabled.
The setting example of frequency synthesizer division is shown in Figure 2.8.15. The setup timing of
frequency synthesizer after hardware reset is shown in Figure 2.8.16. The initialization procedure of
frequency synthesizer and USB function control unit are shown in Figure 2.8.17 and Figure 2.8.18.
The initialization procedure of endpoint is shown in Figure 2.8.19 and Figure 2.8.20.
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2. USB function
FSD
FSP
1/1
FSM
ꢀ4
f
PIN
fVCO
fSYN
f(XIN
)
Invalid
(25516
12MHz
(FF16
)
(0116
)
)
fUSB
48MHz
FSP: Frequency synthesizer prescaler
FSM: Frequency synthesizer multiplier
FSD: Frequency synthesizer divider
Figure 2.8.15. Setting example of frequency synthesizer division
RESET
Enable frequency synthesizer
Wait for 3ms
FSE
Enable USB clock
LS
USBC5
USBC7
Enable USB function control unit
Figure 2.8.16. Setup timing of frequency synthesizer after hardware reset
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2. USB function
Initialization of USB FCU
Clearing the protect
b7
b0
Protect register [Address 000A16
PRCR
]
0
0
1
Enable bit for writing to system clock control registers 0 and 1
and frequency synthesizer related registers
1 : Write-enabled
Enable bit for writing to processor mode registers 0 and 1
0 : Write-inhibited
Reserved bit
Setting frequency synthesizer related registers
b7
b0
Frequency synthesizer prescaler
FSP [Address 03DE16
]
0016 to FF16 can be set
Frequency synthesizer
divider
FSD [Address 03DF16
b7
b0
b7
b0
Frequency synthesizer multiplier
FSM [Address 03DD16
0016 to FF16 can be set
]
]
0016 to FF16 can be set
Setting frequency synthesizer control register
b7
b0
Frequency synthesizer control register [Address 03DC16
FSC
]
1
1
0
0
0
0
0
Frequency Synthesizer enable bit
1 : Enabled
VCO gain control bit
b2 b1
0 0 : Lowest gain
0 1 : Low gain
1 0 : High gain (Recommended)
1 1 : Highest gain
Reserved bit
LPF current control bit (Note)
b6 b5
Note: If the time for locking frequency synthesizer
is needed, first, set to “11 ” (High current),
and set to “10 ” (Medium current)
after it locked.
2
0 0 : Disabled
0 1 : Low current
2
1 0 : Medium current (Recommended)
1 1 : High current
Setting the protect
b7
b0
Protect register [Address 000A16
PRCR
]
0
0
0
Enable bit for writing to system clock control registers 0 and 1
and frequency synthesizer related registers
0 : Write-inhibited
Enable bit for writing to processor mode registers 0 and 1
0 : Write-inhibited
Reserved bit
Wait for 3ms
Checking the frequency synthesizer locked status bit
It is necessary to recheck after a wait of 0.1ms if it is “0”.
b7
b0
Frequency synthesizer control register [Address 03DC16
]
1
0
0
FSC
Frequency synthesizer lock status bit
0 : Unlocked
1 : Locked (Frequency synthesizer stabilized)
Continued to the next page
Figure 2.8.17. Initialization procedure of frequency synthesizer and USB function control unit (1)
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2. USB function
Continued from the previous page
When using fSYN as a main clock
b7
b0
Frequency synthesizer clock control register [Address 03DB16
FSCCR
]
1
0
0
0
0
0
0
Clock source selection bit
1 : fSYN
Divide-by-3 option
0 : Normal
1 : Divide-by-3 (Note)
Note: When this bit is “1”, set FSD to “0216”.
USB clock enabled
b7
b0
USB control register [Address 000C16
USBC
]
1
0
0
0
0
0
USB clock enable bit
1 : Enable (Supply 48MHZ clock)
•When selecting ATTACH function: Set “0316
”
Selecting ATTACH/DETACH
•When ATTACH function disabled: Set “0016
”
b7
b0
USB Attach/Detach register [Address 001F16
USBAD
]
0
0
0
0
0
Port 9
0-Second
0 : Normal mode for Port 90
1 : Forces Port 9
Attach/Detach
0 : Detach
0 to operate as pull up for D+.
1 : Attach
Reserved bit
USB block enabled (Note)
b7
b0
USB control register [Address 000C16
USBC
]
1
1
0
0
0
0
0
USB enable bit
1 : USB blobk enabled
Note: After the USB block is enabled (USBC7 set to “1”), a minimum delay of 187.5ns is needed
before performing any other USB register read/write operations.
Figure 2.8.18. Initialization procedure of frequency synthesizer and USB function control unit (2)
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Initialization of Endpoint
Initialization of endpoint 0 (Control transfer)
(b15)
b7
(b8)
b0 b7
b0
USB endpoint 0 MAXP register [Address 029A16
EP0MP
]
0
0
0
0
0
0
0
0
0
Maximum packet size of endpoint 0 IN/OUT
Setting the size and start location of IN/OUT FIFO
(b15)
b7
(b8)
b0 b7
b0
USB Endpoint x IN FIFO configuration register
EPxIFC (x=1 to 4) [Address 02A216, 02A816, 02AE16, 02B416
0
0
0
0
]
IN FIFO buffer start number
Select the starting number for the EPx IN FIFO (in units of 64 bytes)
000000 : buffer starting location = 0
000001 : buffer starting location = 64
000010 : buffer starting location = 128
......
101111 : buffer starting location = 3008 (last starting number)
IN FIFO buffer size
Select the buffer size for the EPx IN FIFO (in units of 64 bytes)
0000 : buffer size = 64
0001 : buffer size = 128
0010 : buffer size = 192
......
1111 : buffer size = 1024 (largest buffer size)
Double buffer mode
0 : Double buffer mode disabled
1 : Double buffer mode enabled
Continuous transfer mode (Note)
0 : Continuous transfer disabled
1 : Continuous transfer enabled
(b15)
b7
(b8)
b0 b7
b0
USB Endpoint x OUT FIFO configuration register
EPxOFC (x=1 to 4) [Address 02BC16, 02C416, 02CC16, 02D416
0
0
0
0
]
OUT FIFO buffer start number
Select the starting number for the EPx OUT FIFO (in units of 64 bytes)
000000 : buffer starting location = 0
000001 : buffer starting location = 64
000010 : buffer starting location = 128
......
101111 : buffer starting location = 3008 (last starting number)
OUT FIFO buffer size
Select the buffer size for the EPx OUT FIFO (in units of 64 bytes)
0000 : buffer size = 64
0001 : buffer size = 128
0010 : buffer size = 192
......
1111 : buffer size = 1024 (largest buffer size)
Double buffer mode
0 : Double buffer mode disabled
1 : Double buffer mode enabled
Continuous transfer mode (Note)
0 : Continuous transfer disabled
1 : Continuous transfer enabled
Note: Valid when bulk tranfer.
Continued to the next page
Figure 2.8.19. Initialization procedure of endpoint (1)
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Continued from the previous page
Initialization of endpoint x (x=1 to 4) (Bulk tranfer/Interrupt transfer/Isochronous transfer)
(b15)
b7
(b8)
b0 b7
b0
USB endpoint x IN MAXP register
EPxIMP (x=1 to 4) [Address 02A016, 02A616, 02AC16, 02B216
0
0
0
0
0
0
0
0
0
0
0
]
Set the maximum packet size
(b15)
b7
(b8)
b0 b7
b0
USB endpoint x OUT MAXP register
EPxOMP (x=1 to 4) [Address 02B816, 02C016, 02C816, 02D016
0
]
Set the maximum packet size
(b15)
b7
(b8)
b0 b7
b0
USB endpoint enable register [Address 028E16
USBEPEN
]
0
0
0
0
0
0
0
0
Endpoint 1 OUT FIFO enable bit
0 : Disabled
1 : Enabled
Endpoint 1 IN FIFO enable bit
0 : Disabled
1 : Enabled
Endpoint 2 OUT FIFO enable bit
0 : Disabled
1 : Enabled
Endpoint 2 IN FIFO enable bit
0 : Disabled
1 : Enabled
Endpoint 3 OUT FIFO enable bit
0 : Disabled
1 : Enabled
Endpoint 3 IN FIFO enable bit
0 : Disabled
1 : Enabled
Endpoint 4 OUT FIFO enable bit
0 : Disabled
1 : Enabled
Endpoint 4 IN FIFO enable bit
0 : Disabled
1 : Enabled
(b15)
b7
(b8)
b0 b7
b0
USB Endpoint x IN control and status register
EPxICS (x = 1 - 4) [Address 029E16, 02A416, 02AA16, 02B016
0
0
0
0
0
]
INTPT bit (Note)
0 : Select non-rate feedback interrupt transfer
1 : Select rate feedback interrupt transfer
ISO bit
0 : Select non-isochronous endpoint
1 : Select isochronous endpoint
Note: When using the normal interrupt tranfer, set “0”.
(b15)
b7
(b8)
b0 b7
b0
USB Endpoint x OUT control and status register
EPxOCS (x = 1 - 4) [Address 02B616, 02BE16, 02C616, 02CE16
0
0
]
ISO bit
0 : Select non-isochronous endpoint
1 : Select isochronous endpoint
Only when using isochronous tranfer
Setting the USB ISO control register
(b15)
b7
(b8)
b0 b7
b0
USB ISO control register [Address 028C16
USBISOC
]
0
0
0
0
0
0
0
0
0
0
0
AUTO_FLUSH bit
0 : Hardware auto flush disabled
1 : Hardware auto flush enabled
ISO update bit
0 : ISO update disabled
1 : ISO update enabled
Artificial SOF enable bit
0 : Artificial SOF disabled
1 : Artificial SOF enabled
USB transmit/receive process
Figure 2.8.20. Initialization procedure of endpoint (1)
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(3) Disable of USB Function Control Unit
After the USB function control unit being enabled, if the system design requires to disable the USB
function, follow the procedure below:
1: Disable the USB clock by clearing USB enable bit (USBC7) to “0”.
2: Disable the USB clock by clearing USB clock enable bit (USBC5) to “0”.
3: Disable the frequency synthesizer by clearing frequency synthesizer enable bit (FSE) to “0”.
Normally, for system design which continues enabling the USB function, disabling the USB function
control unit is not required.
(4) Vbus Detection
During USB self-powered operation, the Vbus detect function is used to switch into bus power only
when the device is connected to the host PC and power supply is available from the Vbus, for minimiz-
ing battery consumption. To use the Vbus detect function, it is necessary that the VbusDTCT pin is
processed by hardware and the Vbus detect interrupt is set by software. The VbusDTCT pin is used
for the Vbus detect function. When operating the USB in self-powered mode, connect the Vbus line
from the USB connector to the VbusDTCT pin. For enable/disable of the Vbus detect function, set
Vbus detect enable bit (bit 7 at address 001F16) of USB attach/detach register to “1”. Set the interrupt
priority level by using USB Vbus detect interrupt control register (VBDIC: address 005C16). Each time
the USB host powers ON/OFF, a Vbus detect interrupt will be occurred. When a Vbus detect interrupt
is occurred, the Vbus detect state bit located in the port 9 data register (bit 1 at address 03F116) should
be read to determine if the Vbus is powered ON/OFF.
To avoid receiving a false Vbus detect interrupt at start-up, the Vbus detect should be enabled before
enabling the Vbus detect interrupt. Use the following procedure when enabling the Vbus detect func-
tion:
1: Enable a Vbus detect by setting “1” to Vbus detect enable bit (bit 7 at address 001F16).
2: Clear the Vbus detect interrupt request by setting “0” to Vbus detect interrupt request bit (bit 3 at
address 005C16).
3: Enable the Vbus detect interrupt by setting the Vbus detect interrupt priority level greater than
“0002” (bit 0 to 2 at address 005C16).
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2.8.3 USB Interrupt
The USB related interrupts include USB suspend interrupt, USB resume interrupt, USB reset interrupt,
USB endpoint 0 interrupt, USB function interrupt, and USB SOF interrupt.
(1) Related Registers
ꢀꢀ USB function interrupt status register
This register is used to judge the USB function interrupt factor. This is the read-only register which
indicates each interrupt request state of endpoint x(x=1~4) IN interrupt, endpoint x(x=1~4) OUT inter-
rupt, and error interrupt. On occurrence of an interrupt request, this is set to “1”. Each interrupt status
flag can be cleared to “0” by setting “1” to the corresponding bit of USB function interrupt clear register.
• Endpoint 1 IN Interrupt Status Flag
• Endpoint 2 IN Interrupt Status Flag
• Endpoint 3 IN Interrupt Status Flag
• Endpoint 4 IN Interrupt Status Flag
These flags indicate endpoint x(x=1~4) IN interrupt request state, respectively. These flags are set to
“1” at the corresponding endpoint that has been enabled by USB function interrupt enable register in
the following cases:
- The endpoint is enabled from a disabled state
- One buffer data is successfully transmitted
- Buffer flush has been executed by either AUTO_FLUSH or FLUSH bit (bit 6 at address EPxICS)
being set to “1” while buffer data exists in the IN FIFO.
• Endpoint 1 OUT Interrupt Status Flag
• Endpoint 2 OUT Interrupt Status Flag
• Endpoint 3 OUT Interrupt Status Flag
• Endpoint 4 OUT Interrupt Status Flag
These each indicate endpoint x(x=1~4) OUT interrupt request state. When a data is successfully
received, these flags are set to “1” at the corresponding endpoint.
• Error Interrupt Status Flag
This flag indicates that an error has been occurred at the endpoint x(x=0~4). This flag is set to “1” in
the following cases:
- The EP0CSR4 (FORCE_STALL) flag of endpoint 0 is set to “1”
- The EP0CSR5 (SETUP_END) flag of endpoint 0 is set to “1”
- The INxCSR2 (UNDER_RUN) flag of endpoint 1 to 4 IN is set to “1”
- The OUTxCSR2 (OVER_RUN) flag of endpoint 1 to 4 OUT is set to “1”
- The OUTxCSR3 (FORCE_STALL) flag of endpoint 1 to 4 OUT is set to “1”
- The OUTxCSR4 (DATA_ERR) flag of endpoint 1 to 4 OUT is set to “1”
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2. USB function
USB Interrupt Status register (Note)
(b8)
b0
(b15)
b7
b7
b0
Symbol
USBIS
Address
028416
When reset
000016
0
0
0
0
0
0 0
Bit Symbol
Bit Name
Function
R
O
W
INTST0
INTST1
INTST2
INTST3
INTST4
INTST5
INTST6
INTST7
INTST8
EP1 IN interrupt status flag
EP1 OUT interrupt status flag
EP2 IN interrupt status flag
EP2 OUT interrupt status flag
EP3 IN interrupt status flag
EP3 OUT interrupt status flag
0 : No interrupt request
1 : Interrupt request issued
ꢀ
EP4 IN interrupt status flag
EP4 OUT interrupt status flag
Error interrupt status flag
Must always be “0”
Reserved
O
ꢀ
Note: Read only
Figure 2.8.21. USB function interrupt status register
ꢀꢀ USB function interrupt clear register
This register is used to clear the USB function interrupt request factor.
The interrupt status flag corresponding to USB function interrupt status register is cleared to “0” by
setting “1” to the interrupt status clear flag.
The configuration of USB function interrupt status register is shown in Figure 2.8.22.
ꢀꢀ USB function interrupt enable register
This register is used to set the USB function interrupt request factor.
The USB function interrupt request occurs when the request of interrupt which set the enable bit to “1”
occurs.
The configuration of USB function interrupt enable register is shown in Figure 2.8.23.
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USB Function Interrupt Clear register
(b8)
b0
(b15)
b7
b7
b0
Symbol
USBIC
Address
028616
When reset
000016
0
0
0
0
0
0 0
Bit Symbol
Bit Name
Function
0 : No action
R
W
O
INTCL0
INTCL1
INTCL2
INTCL3
INTCL4
INTCL5
INTCL6
INTCL7
INTCL8
Clear EP1 IN interrupt status flag
Clear EP1 OUT interrupt status flag
Clear EP2 IN interrupt status flag
ꢀ
1 : Clear interrupt status flag
Clear EP2 OUT interrupt status flag
Clear EP3 IN interrupt status flag
Clear EP3 OUT interrupt status flag
Clear EP4 IN interrupt status flag
Clear EP4 OUT interrupt status flag
Clear error interrupt status flag
Must always be “0”
Reserved
ꢀ
O
Note: Write only
Figure 2.8.22. USB function interrupt clear register
USB Function Interrupt Enable register
(b8)
b0
(b15)
b7
b7
b0
Symbol
USBIE
Address
028816
When reset
01FF16
0
0
0
0
0
0 0
Bit Symbol
Bit Name
Function
R
W
INTEN0
INTEN1
INTEN2
INTEN3
INTEN4
INTEN5
INTEN6
INTEN7
INTEN8
EP1 IN interrupt enable bit
EP1 OUT interrupt enable bit
EP2 IN interrupt enable bit
EP2 OUT interrupt enable bit
EP3 IN interrupt enable bit
EP3 OUT interrupt enable bit
0 : Disabled
1 : Enabled
O O
EP4 IN interrupt enable bit
EP4 OUT interrupt enable bit
Error interrupt enable bit
Must always be “0”
Reserved
O O
Figure 2.8.23. USB function interrupt enable register
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ꢀꢀ USB frame number register
This register is used to contain 11-bit frame number of SOF token received from the host CPU. This is
the read-only register.
The configuration of USB frame number register is shown in Figure 2.8.24.
USB Frame Number register (Note)
(b8)
b0
(b15)
b7
b7
b0
Symbol
USBFN
Address
028A16
When reset
000016
0
0
0 0 0
Bit Symbol
FN10-0
Bit Name
SOF frame number bit
Function
R
W
11-bit frame number
issued with an SOF packet
O
O
X
X
Reserved
“0” when read
Note: Read only.
Figure 2.8.24. USB frame number register
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2. USB function
(2) USB Endpoint 0 Interrupt
In the endpoint 0 interrupt, the interrupt request occurs when the data transmit/receive of endpoint 0
are completed. Set the interrupt priority level by using USB endpoint 0 interrupt control register
(EP0IC: address 004616). The interrupt request bit of the EP0IC is set to “1” and the USB endpoint 0
interrupt occurs when one of the following events occur:
• A data is successfully received
• A data is successfully transmitted
• The DATA_END bit of the EP0CS register is cleared to “0”
• The SETUP_END flag of the EP0CS register is set to “1”
ꢀ Mask Function of Endpoint 0 Interrupt Factor
By setting the DATA_END_MASK bit of USB endpoint 0 control and status register, the M30245
group can control whether or not to clear the DATA_END flag as the endpoint 0 interrupt factor.
Clearing of the DATA_END flag is masked at the time of resetting. (The DATA_END flag is not
cleared as an endpoint 0 interrupt factor.)
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(3) USB Function Interrupt
The USB function interrupts include the endpoint x(x=1~4) IN interrupt, endpoint x(x=1~4) OUT inter-
rupt, and error interrupt. An interrupt request occurs on completion of data transmit/receive or on
occurrence of an error such as overrun/underrun, setting the status flag which is the factor of the
interrupt request inside USB function interrupt status register to “1”. When using the USB function
interrupt, set the interrupt priority level at USB function interrupt control register (address 005D16) and
the corresponding bit of USB function interrupt enable register to “1”.
The USB function interrupt involves multiple interrupt request factors. Therefore, during processing of
the USB function interrupt, an interrupt request may occur newly and the interrupt status flag can be
changed by it. When performing USB function interrupt processing, be sure to first save contents of
interrupt status register and to clear the status flag. Then, process the interrupt request that has
occurred when the interrupt process has been received based on the saved data value.
ꢀ Endpoint x(x=1~4) IN Interrupt
In the endpoint x(x=1~4) IN interrupt, when each USB endpoint x IN interrupt status flag
(INTST0,2,4,6) of the corresponding endpoints of USB function interrupt status register is set to “1”,
an interrupt request occurs. Each flag INTST0, 2, 4, 6 is set to “1” in one of the following cases:
• The corresponding bit of USB endpoint enable register (USBEPEN: address 028E16) is set to “1”.
(The endpoint is enabled from a disabled state.)
• A data is successfully transmitted
• AUTO FLUSH of hardware has been executed or FLUSH bit of corresponding USB endpoint x IN
control and status register (EPxICS: addresses 029E16, 02A416, 02AA16, 02B016) being set to
“1” while one or two packet data exist in the IN FIFO.
• The last ACK for control read transfer is destroyed.
ꢀ Endpoint x(x=1~4) OUT Interrupt
In the endpoint x(x=1~4) OUT interrupt, when each USB endpoint x OUT interrupt status flag
(INTST1,3,5,7) of the corresponding endpoints of USB function interrupt status register is set to “1”,
an interrupt request occurs. When a data is successfully received at the corresponding endpoint,
each flag INTST1, 3, 5, 7 is set to “1”.
ꢀ Error Interrupt
In the error interrupt, when the error interrupt status flag (INTST8) of USB function interrupt status
register is set to “1”, an interrupt request occurs. The INTST8 is set to “1” in one of the following
cases:
• The FORCE_STALL flag of endpoint 0 control and status register (EP0CS) is set to “1”.
• The SETUP_END flag of EP0CS is set to “1”.
• The UNDER_RUN flag of USB endpoint x IN control and status register (EPxICS: addresses 029E16,
02A416, 02AA16, 02B016) is set to “1”. (Due to delay in writing of data to FIFO, underrun has occurred
at any one of the IN endpoints that are used for isochronous transfer.)
• The OVER_RUN flag of USB endpoint x OUT control and status register (EPxOCS: addresses 02B616,
02BE16, 02C616, 02CE16) is set to “1”. (Due to delay in reading of data from FIFO, overrun has occurred
at any one of the OUT endpoints that are used for isochronous transfer.)
• The FORCE_STALL flag of EPxOCS is set to “1”.
• The DATA_ERR flag of EPxOCS is set to “1”.
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2. USB function
(4) USB Reset Interrupt
This interrupt is used for detection of the USB reset. This occurs when the USB function control unit
has received reset signal from the host CPU (or detected SE0 on the D+/D- line for at least 2.5µs). At
this time, all the USB internal registers are made into reset state. To resume communication, each
endpoint needs to be initialized. When using the USB reset interrupt, set the interrupt priority level at
USB reset interrupt control register (RSTIC: address 005A16).
(5) USB Suspend Interrupt
This interrupt is used for detection of inactivity on the USB bus line. The suspend status flag of USB
power management register (USBPM: address 028216) is set when the USB function control unit has
detected suspend signal on the USB bus line (or not detected any bus activity on the D+/D- line for at
least 3ms). Simultaneously, the USB suspend interrupt occurs.
When using the USB suspend interrupt, set the interrupt priority level at USB suspend interrupt control
register (SUSPIC: address 005616).
(6) USB Resume Interrupt
This interrupt is used for detection of activity on the USB bus line while the device is in suspend state.
When the USB function control unit has received resume signal on the USB bus line (or detected
activity on the D+/D- line), the interrupt request occurs, and the USB resume interrupt occurs by
setting “1” to resume interrupt request bit of USB resume interrupt control register (RSMIC: address
005816).
When using the USB suspend interrupt, set the interrupt priority level at the RSMIC.
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2. USB function
(7) USB SOF (Start of Frame) Interrupt
This interrupt is valid to control the isochronous transfer. When a valid SOF PID is detected, receive of
an SOF packet is recognized and an interrupt request occurs. The frame number (11 bits) of the SOF
packet received from the host is automatically stored in USB frame number register.
In isochronous transfer, P92 can be used as the SOF output pin by setting “1” to USB SOF port select
bit of USB control register. (Set P92 to output port.) Every time that the SOF signal is received from the
host, the P92 outputs “Low” for about 166ns (two cycles of the 12MHz USB clock.).
When using the USB SOF interrupt, set the interrupt priority level at USB SOF interrupt control register
(SOFIC: address 005B16).
ꢀ Artificial SOF Function
If the SOF packet from the host PC is destroyed due to any cause, and thus the SOF packet is not
correctly received within 1 ms of the start of the frame, a virtual SOF receive operation is performed
(and an USB SOF interrupt is generated). Even if the SOF packet is destroyed due to any cause, a
new frame can be formed by this function without waiting for the next SOF packet. This function
operates once to virtually receive an SOF packet after two SOF packets have been received cor-
rectly.
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2. USB function
(8) USB Function Interrupt Routine
This interrupt is used to control data flow. This occurs on completion of data transmit/receive or on
occurrence of an error such as overrun/underrun. When using the USB function interrupt, set the
interrupt priority level at USB function interrupt control register (address 005D16) and the correspond-
ing bit of USB function interrupt enable register to “1”.
The related registers are shown in Figure 2.8.25, and the USB function interrupt routine is shown in
Figure 2.8.26.
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2. USB function
USB function interrupt control register [Address 005D16
]
b7
b0
USBFIC
0
Interrupt priority level select bit
Interrupt request bit
0 : Interrupt not requested
USB function interrupt enable register [Address 028816
]
(b15)
b7
(b8)
b0 b7
b0
USBIE
0
0
0
0
0
0
0
EP1 IN interrupt enable bit
EP1 OUT interrupt enable bit
EP2 IN interrupt enable bit
EP2 OUT interrupt enable bit
EP3 IN interrupt enable bit
EP3 OUT interrupt enable bit
EP4 IN interrupt enable bit
EP4 OUT interrupt enable bit
Error interrupt enable bit
0 : Disabled
1 : Enabled
USB function interrupt status register [Address 028416
]
(b15)
b7
(b8)
b0 b7
b0
USBIS
0
0
0
0
0
0
0
EP1 IN interrupt status flag
EP1 OUT interrupt status flag
EP2 IN interrupt status flag
EP2 OUT interrupt status flag
EP3 IN interrupt status flag
EP3 OUT interrupt status flag
EP4 IN interrupt status flag
EP4 OUT interrupt status flag
Error interrupt status flag
0 : No interrupt request
1 : Interrupt request issued
USB function interrupt clear register [Address 028616
]
(b15)
b7
(b8)
b0 b7
b0
USBIC
0
0
0
0
0
0
0
Clear EP1 IN interrupt status flag
Clear EP1 OUT interrupt status flag
Clear EP2 IN interrupt status flag
Clear EP2 OUT interrupt status flag
Clear EP3 IN interrupt status flag
Clear EP3 OUT interrupt status flag
Clear EP4 IN interrupt status flag
Clear EP4 OUT interrupt status flag
Clear error interrupt status flag
0 : No action
1 : Clear interrupt status flag
Figure 2.8.25. USB function interrupt related registers
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USB function interrupt request detected
•Enables each interrupt by the USBIE (address 028816~028916
)
at initial routine
USBIS → Read one word and store it to RAM
RAM → Write one word to USBIC
•Clears USB interrupt status register 1, 2 by writing “1”
to the bit corresponding to the USBIC.
N
RAM,bit8=1?
Y
•Executes error handling of endpoint 0 to 4.
USB error
interrupt routine
RAM,bit1=1 or
RAM,bit3=1 or
RAM,bit5=1 or
RAM,bit7=1
N
Y
USB endpoint x OUT
interrupt routine
RAM,bit0=1 or
RAM,bit2=1 or
RAM,bit4=1 or
RAM,bit6=1
N
Y
USB endpoint x IN
interrupt routine
Completion of USB funxtion interrupt process
Figure 2.8.26. USB function interrupt processing routine
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2. USB function
2.8.4 USB Operation (Suspend/Resume Function)
The USB device has received the suspend signal from the host CPU following the power input state, and
then controls power supply and shifts the state into the suspend state.
And, by receiving the resume signal from the host CPU (or transmitting the resume signal to the host CPU
in the case of remote wakeup), it returns to the state before shifting into the suspend state and resumes
the USB communication.
This section explains how the M30245 group controls a shift into suspend state/recovery at the time of
resume in the state which the USB function control unit is enabled.
(1) Related Registers
ꢀꢀ USB power management register
This register is used to control the suspend/resume by the USB function control unit.
• USB Suspend Status Flag
When the USB function control unit does not detected any bus activity on D+/D- line for at least 3ms,
the USB suspend status flag is set. Simultaneously, the USB suspend interrupt request occurs. This
flag is automatically cleared in the following cases:
- The active signal from the host CPU has been detected on the USB's D+/D- line. (When the
resume signal has been received and, simultaneously, the USB resume interrupt request has oc-
curred.)
- Transmission of the resume signal to the host CPU has been completed. (After USB remote
wakeup bit being set to “1”, when clearing it to “0” to stop resume signal transmission.)
If the USB clock has been disabled during the suspend mode, this flag is not cleared until after the
USB clock is re-enabled.
• USB remote wakeup bit
When the USB suspend signal status flag is set to “1”, the USB function control unit transmits the
resume signal to the host CPU while setting “1” to USB remote wakeup bit.
Set USB remote wakeup bit to “1” in order to transmit the resume signal to the host CPU and to return
to the previous state (remote wakeup) in the USB suspend state. Retain this bit at “1” for min. 1ms to
max. 15ms before completing the resume signal transmission by clearing to “0”.
The configuration of USB power management register is shown in Figure 2.8.27.
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2. USB function
USB Power Management register
(b8)
b0
(b15)
b7
b7
b0
Symbol
USBPM
Address
028216
When reset
000016
0
0
0
0
0
0 0
0
0
0
0
0
0 0
Bit Symbol
Function
0 : Not in suspend state
Bit Name
R
O
W
ꢀ
SUSPEND Suspend state flag
(Note 2)
1 : In suspend state (Note 1)
0 : End remote wakeup signal
1 : Remote wakeup signaling (Note 3)
WAKEUP
Reserved
Remote wakeup
O
O
O
Must always be “0”
O
Note 1: This flag is cleared when WAKEUP=“1” or a resume signal is detected.
Note 2: Set “0” when writing.
Note 3: If SUSPEND="1", set this bit to “1” (keep this bit set for a minimum of 1ms and
a maximum of 15ms).
Figure 2.8.27. USB power management register
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2. USB function
(2) USB Suspend Function
In the M30245 group, the USB suspend status flag (SUSPEND) of USB power management register
(address 028216) is set to “1” when the suspend signal has been received from the host CPU (or not
detected any bus activity on the D+/D- line for at least 3ms). Simultaneously, the USB suspend inter-
rupt request occurs.
To shift into the USB suspend state, control the USB function control unit in the following procedure.
Further, for changes in frequency synthesizer control register (address 03DC16) or system clock con-
trol register1 (address 000716), clearing the corresponding bit of protect register (address 000A16) is
required.
ꢀꢀ USB Suspend Mode Control
1: Set USB clock enable bit of USB control register to “0”. Do not write to USB internal registers (other
than the USBC, USBAD, and frequency synthesizer related registers) when the USB clock has
been disabled in the suspend state.
2: During the bus power supply operation as a low-power device, control it to reduce the total driving
current to 500µA or below (or 2.5mA or below when remote wakeup has been enabled as a high-
power device by the host CPU). For details of the power control in suspend, refer to USB2.0
specification.
3: Set frequency synthesizer enable bit of frequency synthesizer control register to “0”.
4: Set the return interrupt from the USB suspend state. Set USB resume interrupt control register
(address 005816). (When remote wakeup has been enabled, enable interrupt control register of the
peripheral functions used in remote wakeup.)
5: Set I flag to “1”.
6: Stop the system clock by setting all clock stop control bit (bit 0 of CM1) to 1.
7: During the bus power supply operation, after setting the low-power consumption mode by dis-
abling interrupts that are not used in return from the USB suspend state, etc., execute the low-
power consumption mode.
Note: When the device is in self-powered operation, the above control is not required.
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2. USB function
(3) USB Resume Function
ꢀ Returning Routine from USB Suspend State
To return from the USB suspend state, the M30245 group uses the USB resume interrupt occurred by
receiving the resume signal from the host or the interrupt for remote wakeup for transmitting the
resume signal to the host.
- Returning by Resume Interrupt
When the resume signal is received from the host CPU during the USB suspend state (when de-
tected any bus activity on D+/D- line in suspend detect state), the USB resume interrupt request
occurs, setting “1” to interrupt request bit of USB resume interrupt control register (address 005816).
When the USB clock is operated, the USB suspend status flag is automatically set to “0” at this time.
For returning from the suspend state by the USB resume interrupt, follow the procedure below:
1: Return the USB function control unit. (Refer to the next page.)
2: Enable other functions as circumstances demand.
- Returning by Remote Wakeup
When clock operation is started by the remote wakeup interrupt (other than the USB resume inter-
rupt) during the USB suspend state, transmit the resume signal to the host CPU as follows:
1: Return the USB function control unit. (Refer to the next page.)
2: Set USB remote wakeup bit to “1” and transmit the resume signal to the host CPU. (Retain “1” for
min. 1ms to max. 15ms.)
3: Set USB remote wakeup bit to “0” and complete the resume signal transmission. The USB sus-
pend status flag is automatically cleared at this time.
Also, when returning from the stop mode, the main clock dividing ratio has been set to 8-dividing
mode, for which resetting is required. Wait for enough oscillation stabilization time before resetting
main clock division select bit of system clock control register 0 (address 000616). (For details, refer to
“Clock-Generating Circuit” of Chapter 1 “Hardware”.)
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2. USB function
- Returning Routine of USB Function Control Unit
To return from the USB suspend state to the previous state, perform return control of the USB function
control unit as follows.
Further, clearing the bit of protect register (address 000A16) is required for changes in frequency
synthesizer control register (address 03DC16).
1: Set frequency synthesizer enable bit of frequency synthesizer control register to “1”.
2: Wait for 3ms.
3: Check that frequency synthesizer lock status bit of frequency synthesizer control register is set to
“1”. When this bit has been set to “0”, wait for 0.1ms, and then, check again. Repeat the re-check
until the bit becomes “1”.
4: Set USB clock enable bit of USB control register to “1”.
Do not write to USB-related registers (other than the USBC, USBAD, and frequency synthesizer re-
lated registers) when the USB clock has been disabled in the suspend state.
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2. USB function
(4) USB Suspend Interrupt Request Processing Routine
When using the USB suspend interrupt, set USB suspend interrupt control register (address 005616).
In the USB suspend interrupt, when the USB suspend status flag (SUSPEND) of USB power manage-
ment register is set to “1”, the interrupt request occurs.
The USB suspend interrupt request processing routine is shown in Figure 2.8.28 and Figure 2.8.29.
Detection of USB suspend interrupt request
Setting USB control register
b7
b0
USB control register [Address 000C16
USBC
]
0
0
0
0
0
0
USB clock enable bit
0: Disable (48MHZ clock supply disabled
Clearing the protect
b7
b0
Protect register [Address 000A16
PRCR
]
1
0
Enable bit for writing to system clock control registers 0 and 1
and frequency synthesizer related registers
1 : Write-enabled
Setting frequency synthesizer control register
b7
b0
Frequency synthesizer control register [Address 03DC16
FSC
]
0
0
0
Frequency Synthesizer enable bit
0 : Disabled
Setting the interruppt for return from suspend mode (Note1, 2)
b7
b0
USB resume interrupt control register [Address 005816
RSMIC
]
0
Interrupt priority level select bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
Interrupt request bit
0 : Interrupt not requested
Note 1: Confirms that the interrupt enable flag (I) of flag register is set to “0” before setting the interrupt to
higher priority level than the USB suspend interrupt. The interrupt should be higher priority level than
the USB suspend interrupt when those event are returned from the suspend mode by process
(key input interrupt, etc.) other than the USB resume interrupt.
Note 2: When the interrupt is not used to clear the stop mode, the interrupt should be disabled by setting
the interrupt priority level to “0”.
Continued to the next page
Figure 2.8.28. USB suspend interrupt request processing routine (1)
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2. USB function
Continued from the previous page
Interrupt enable flag (I)
← “1”
Stop all clocks
b7
b0
System clock control register 1 [Address 000716
CM1
]
0
0
0
0
1
All clock stop control bit
1: All clocks off (stop mode)
Insert at least four NOPs following JMP.B instruction after the instruction that sets the all clock stop control bit to “1”
.
• Shift to stop mode
Wait for the interrupt for return from suspend state
Execute the interrupt process
for return from suspend state
the interrupt for return from suspend state occurs
(USB resume/remote wakeup)
Restore the settings changed for stop mode as required.
Interrupt enable flag
Protect disabled, etc.
← “0”
USB suspend interrupt request process is complete
Figure 2.8.29. USB suspend interrupt request processing routine (2)
(5) USB Resume Interrupt Request Processing Routine
When the resume signal is received from the host CPU during the USB suspend mode (when de-
tected any bus activity on D+/D- line in suspend detect state), the USB resume interrupt request
occurs. The USB suspend status flag is automatically set to “0” at this time.
The USB resume interrupt request processing routine is shown in Figure 2.8.30.
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2. USB function
Detection of USB resume interrupt request
Clearing the protect
b7
b0
Protect register [Address 000A16
PRCR
]
1
0
Enable bit for writing to system clock control registers 0 and 1
and frequency synthesizer related registers
1 : Write-enabled
Setting frequency synthesizer control register
b7
b0
Frequency synthesizer control register [Address 03DC16
FSC
]
0
0
1
Frequency Synthesizer enable bit
1 : Enabled
Clearing the protect
b7
b0
Protect register [Address 000A16
PRCR
]
0
0
Enable bit for writing to system clock control registers 0 and 1
and frequency synthesizer related registers
0 : Write-disabled
Wait for 2ms
Wait till the frequency synthesizer stabilized
b7
b0
Frequency synthesizer control register [Address 03DC16
FSC
]
1
0
0
Frequency synthesizer lock status bit
0 : Unlocked
1 : Locked (Frequency synthesizer stabilized)
Note: Check the frequency synthesizer lock status bit. It is necessary to recheck
after a wait of 0.1ms if it is “0”.
Setting USB control register
b7
b0
USB control register [Address 000C16
USBC
]
1
0
0
0
0
0
USB clock enable bit
1: Enable (Supply 48MHZ clock)
USB resume interrupt request process is complete
Figure 2.8.30. USB resume interrupt request processing routine
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2. USB function
2.8.5 USB Operation (Endpoint 0)
Endpoint 0 is used only for control transfer.
Endpoint 0 FIFO consists of total 256 bytes including IN (transmit) FIFO and OUT (receive) FIFO each
respectively of 128 bytes. The starting position is allocated from the 3072nd byte to the 3327th byte of the
endpoint FIFO. Both the endpoint 0 FIFO size and the starting position are fixed. The FIFO size to be
used is determined by the USB endpoint 0 maximum packet size.
The packet data received from the host CPU are written in endpoint 0 OUT FIFO. When a data receive
request is issued by the host CPU while data already exists in the OUT FIFO, responds with NAK auto-
matically. When packet data are transmitted to the host CPU, the transmit data are written in the endpoint
0 IN FIFO. When a data transmit request is issued by the host CPU before the data are written in IN FIFO,
responds with NAK automatically. A packet data can realize higher transmit/receive by enabling continu-
ous transfer.
When an error is detected in control transfer, responds with STALL automatically and the error detection
is reported. Based on the status of the endpoint 0 communication, data transmit/receive is controlled in
accordance with the device request which is received from the host CPU.
(1) Related Registers
USB address register
USB address register maintains 7 bits addresses of the USB function control unit that are allocated by
the host CPU. The USB function control unit of the M30245 group responds to the token packet for the
address retained in this register.
When the USB function control unit is in the initial state or has received a reset signal from the host
CPU, this register value is the default address “000016”. When the USB block has been disabled (bit 7
of USB control register is set to “0”), this register value is the address “000016”.
After receiving the SET_ADDRESS request from the host CPU, rewrite USB address register and
update the address.
For rewriting USB address register, follow the procedure below:
• When the device is in the default state (USB address register value is “000016”):
1: When USB address register has received the SET_ADDRESS request from the host CPU, store
the new address data in the USB address register.
2: When the status phase of the SET_ADDRESS request is completed , USB address register is
automatically rewritten into the address written in above-mentioned 1:. When the status phase is
not normally completed, USB address register is not rewritten.
• When the device is in the address state (USB address register value is other than “000016”):
1: When USB address register has received the SET_ADDRESS request from the host CPU, con-
firm that the status phase of SET_ADDRESS request completes.
2: Store the new address data in USB address register. USB address register is rewritten into the
new address data.
The configuration of USB address register is shown in Figure 2.8.31.
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2. USB function
USB Function Address register
(b8)
b0
(b15)
b7
b0
b7
Symbol
USBA
Address
028016
When reset
000016
0
0
0
0
0
0
0
0
0
Bit Symbol
FUNAD6-0
Reserved
Bit Name
Function address
Function
R
W
7-bit programmable
function address
O
O
O
O
Must always be “0”
Figure 2.8.31. USB address register
USB endpoint 0 control and status register
USB endpoint 0 control and status register consists of the bits concerning control information and
status information of endpoint 0.
• OUT_BUF_RDY Flag
This flag shows the status of OUT FIFO.
The OUT_BUF_RDY flag is set to “1” in the following cases:
- The setup packet is received.
- One data packet is received from the host CPU in the data phase.
Set the OUT_BUF_RDY flag to “0” by setting “1” to CLR_OUT_BUF_RDY bit after reading the
OUT FIFO.
• IN_BUF_RDY Flag
This flag shows the status of IN FIFO.
When this flag is set to “1”, shows that data to be transmitted to the host CPU exists in FIFO.
When transmission of the IN FIFO data is completed or when the SETUP_END flag is set to “1”, this
flag is cleared to “0”.
• SETUP Flag
When the setup packet is received from the host CPU, this flag is set to “1”.
The OUT_BUF_RDY flag is also set to “1” at this time.
This flag is cleared by setting “1” to CLR_SETUP bit.
• DATA_END Flag
This flag shows the status phase control of control transfer.
After the status phase is started or when a new SETUP packet is received, this flag is automatically
set to “0”.
When DATA_END_MASK bit is set to “1” (at the time of resetting), the DATA_END flag is always set
to “0”, and endpoint 0 interrupt factor does not occur by clearing the DATA_END flag to “0”.
• FORCE_STALL Flag
This flag shows the error occurrence in control transfer.
This flag is set to “1” for reporting an error when at least one of the following conditions occurs:
- IN token without SETUP stage is received.
- An incorrect data toggle is received in the STATUS stage. (DATA0 is used.)
- An incorrect data toggle is received in the SETUP stage. (DATA1 is used.)
- Data exceeding the one specified in the SETUP stage are required. (IN token is received after the
DATA_END flag is set.)
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- Data exceeding the one specified in the SETUP stage are required. (An OUT token is received
after the DATA_END flag is set.)
- Data exceeding the one specified are received in USB endpoint 0 MAXP register.
Except for when an incorrect data toggle is received in the SETUP stage, on occurrence of the above
condition, STALL is transmitted to the IN/OUT token with a problem. When an incorrect data toggle
is received in the SETUP stage, ACK is returned to the SETUP stage and STALL is returned to next
IN/OUT token.
The STALL handshake occurring by the above condition completes the control transfer in operation
by being transmitted to one transaction. The packet after STALL handshake is regarded as the start
of new control transfer. Set this flag to “0” by writing “1” to CLR_FORCE_STALL bit.
• SETUP_END flag
This flag shows the interrupt in control transfer.
This flag is set to “1” when at least one of the following conditions occurs:
- Transmission of the data which had amount of data set by setup phase during data phase process-
ing is completed. (The status phase is started before the DATA_END flag is set.)
- A new SETUP packet is received before status phase is completed.
When this flag is set to “1” and transmit data to the host CPU exists, IN_BUF_RDY bit is cleared to “0”
and the IN FIFO data is destroyed. Discontinue access to FIFO and process the preceding setup.
Also, when a new SETUP packet is received right after the SETUP_END flag is set to “1” (when the
next new SETUP packet is received before the data phase or the status phase is completed), the
SETUP flag and the OUT_BUT_RDY flag in addition to the SETUP_END flag are set to “1”, indicat-
ing that a new SETUP packet data exists in OUT FIFO.
Set the SETUP_END flag to “0” by writing “1” to CLR_SETUP_END bit.
• CLR_OUT_BUF_RDY bit
This bit controls clearing of the OUT_BUF_RDY flag.
This bit is set to “1” after reading the data packet from OUT FIFO. When this flag is written to “1”, the
OUT_BUF_RDY flag is cleared to “0”.
When the OUT_BUF_RDY flag is set to “1” by receiving the SETUP token, the USB function control
unit responds with NAK to the data request from the host CPU.
Until decoding of request data from the host CPU is completed, do not set this bit to “1” (nor the
OUT_BUF_RDY flag is set to “0”.)
• SET_IN_BUF_RDY bit
This bit controls setting of the IN_BUF_RDY flag to “1”.
Completion of one buffer data write is notified to the USB function control unit.
Set this bit to “1” after writing the data packet to IN FIFO. When this bit is written to “1”, the
IN_BUF_RDY flag is set to “1”.
• CLR_SETUP bit
This bit controls clearing of the SETUP flag.
Set this bit to “1” after decoding the SETUP packet. When this bit is written to “1”, the SETUP flag is
cleared to “0”.
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• SET_DATA_END bit
This bit controls setting of the DATA_END flag to “1”.
When the last data has been written in IN FIFO in the IN data phase or when the last data has been
read from OUT FIFO in the OUT data phase, set this bit to “1”. When this bit is set to “1”, the
DATA_END flag is set to “1”. At this time simultaneously, set the CLR_OUT_BUF_RDY bit or
SET_IN_BUF_RDY bit to “1”.
Completion of processing of the data which had amount of data set by setup phase is notified to the
USB function control unit, and the process shifts into status phase processing.
• CLR_FORCE_STALL bit
This bit controls clearing of the FORCE_STALL flag.
When this bit is written to “1”, the FORCE_STALL flag is cleared to “0”.
• SEND_STALL bit
This bit controls the STALL response to the host CPU.
To responds with STALL when an invalid request has received from the host CPU, set this bit to “1”
simultaneously as CLR_OUT_BUF_RDY bit is set to “1”.
When this bit is set to “1”, the USB function control unit transmits, to the host CPU, the STALL
handshake concerning all the IN/OUT transactions. When a new valid SETUP packet is received,
clear a data by writing “0” in this bit.
• DATA_END_MASK bit
This bit controls whether the DATA_END flag clear becomes an endpoint 0 interrupt factor.
When this bit is set to “1”, clearing the DATA_END flag does not become an endpoint 0 interrupt
factor. This bit is set to “1” at the time of reset.
The configuration of USB endpoint 0 control and status register is shown in Figure 2.8.32.
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USB Endpoint 0 Control and Status register
(b8)
b0
(b15)
b7
b7
b0
Address
029816
When reset
200016
Symbol
EP0CS
0
0
Bit Symbol
Function
R
O
W
X
Bit Name
0 : No setup packet or data set ready for unload
1 : Setup packet or data set ready for unload
OUT_BUF_RDY flag
IN_BUF_RDY flag
SETUP flag
EP0CSR0
EP0CSR1
EP0CSR2
EP0CSR3
EP0CSR4
EP0CSR5
EP0CSR6
EP0CSR7
EP0CSR8
EP0CSR9
EP0CSR10
EP0CSR11
EP0CSR12
EP0CSR13
0 : No data set ready for transmit
1 : Data set ready for transmit
O
X
0 : No setup packet ready for unload
1 : Data set ready for transmit
0 : DATA_END not set by CPU or DATA-END is set by CPU
then status phase starts
1 : DATA-END set by CPU
0 : No protocol violation detected
1 : Protocol violation detected
0 : No premature completion of control transfer
1 : Premature completion of control transfer
0 : No action
1 : Data set unloaded from the OUT buffer
O
O
X
X
DATA_END flag
FORCE_STALL flag
SETUP_END flag
CLR_OUT_BUF_RDY
SET_IN_BUF_RDY
CLR_SETUP
O
O
O
X
X
O
Note
0 : No action
O
O
Note
1 : Data set loaded in IN buffer (sets IN_BUF_RDY flag)
0 : No action
O
Note
O
1 : Clears SETUP flag
0 : No action
O
Note
O
SET_DATA_END
CLR_FORCE_STALL
CLR_SETUP_END
SEND_STALL
1 : Last data pcket transferred to/from buffer
0 : No action
O
O
O
Note
1 : Clears FORCE_STALL flag
0 : No action
O
Note
1 : Clears SETUP_END flag
0 : No EP0 STALL by CPU
1 : EP0 STALL by CPU
O
O
O
O
0 : Clearing DATA_END event causing EP0 interrupt is
DATA_END_MASK
unmasked
O
O
1 : Clearing DATA_END event causing EP0 interrupt is
masked
Reserved
Must always be “0”
Note: Always read a “0”.
Figure 2.8.32. USB endpoint 0 control and status register
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USB endpoint 0 MAXP register
This register indicates the IN/OUT maximum packet size of endpoint 0.
When a GET_DESCRIPTION request is received from the host CPU, write to this register to change
the IN/OUT maximum packet size value of endpoint 0.
Set the packet size value (8, 16 or 32 bytes) specified by control transfer. The default value is 8 bytes.
The configuration of USB endpoint 0 MAXP register is shown in Figure 2.8.33.
USB Endpoint 0 MAXP register
(b8)
b0
(b15)
b7
b7
b0
Symbol
EP0MP
Address
029A16
When reset
000816
0
0
0
0
0
0
0
0
0
Bit Symbol
Function
Bit Name
R
O
O
W
O
O
Set maximum packet size
of EP0 IN/OUT
EP0MP6-0
Reserved
Maximum packet size
Must always be “0”
Figure 2.8.33. USB endpoint 0 MAXP register
USB endpoint 0 OUT write count register
This register contains the number of bytes of the current data set in the OUT FIFO. When the USB
function control unit completes the data packet receive from the host CPU, set the value of this regis-
ter. When one buffer data receive completes, read this register and determine the number of bytes to
be read from OUT FIFO. This register value is not decremented even if the data is read from OUT
FIFO.
When CLR_OUT_BUF_RDY bit of the EP0CSR is set to “1”, this register value is cleared to “0”.
The configuration of USB endpoint 0 OUT write count register is shown in Figure 2.8.34.
USB Endpoint 0 Write Count register
(b8)
b0
(b15)
b7
b7
b0
Symbol
EP0WC
Address
029C16
When reset
000016
0
0
0
0
0
0
0
0
Bit Symbol
Bit Name
Receive byte count
Function
R
W
The number of bytes of the current
data set in EP0 OUT FIFO
EP0WC7-0
Reserved
O
O
X
O
Must always be “0”
Figure 2.8.34. USB endpoint 0 OUT write count register
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(2) Control Transfer: Endpoint 0 Receive
The endpoint 0 receives the packet data from the host CPU in the setup stage or the data stage by the
control write transfer. When the receive of a valid SETUP packet or a data packet completes, the
SETUP flag and the OUT_BUF_RDY flag are automatically set to “1”, and the number of bytes of
receive data are set in USB endpoint 0 OUT write count register (address 029C16). Read the data of
only amount equal to received byte count from the endpoint 0 OUT FIFO. Every time that one-byte
data is read from OUT FIFO, the internal write pointer is automatically decremented by “2” in word
access and by “1” in byte access. The contents of internal write pointer cannot be read.
When the data read from OUT FIFO is completed, simultaneously set “1” to CLR_OUT_BUF_RDY bit
and SET_DATA_END bit. (When the SETUP packet is received, clearing the SETUP flag by setting
“1” to CLR_SETUP bit is required.) Therefore, the OUT_BUF_RDY flag is cleared and the
DATA_END flag is set to “1”.
The USB function unit proceeds to the status phase process when the DATA_END flag is set to “1”.
When the status phase completes, the DATA_END flag is cleared to “0”.
Manage the stage of control transfer by software.
When the SETUP packet is received, the USB endpoint 0 interrupt occurs regardless of setting of
continuous transfer mode enable bit (The OUT_BUF_RDY flag and the SETUP flag are set to “1”).
Example of one packet data receive procedure
1: Check that one packet data is received in OUT FIFO.
2: Read the number of bytes of receive packet data from USB endpoint 0 OUT write count register.
Determine the amount of data to read from OUT FIFO.
3: Read the data of only amount equal to determined in the above-mentioned 2: from OUT FIFO. To
analyze the received data, the subsequent stage and operation are determined based on the read
data.
4: With CLR_OUT_BUF_RDY bit being set to “1”, the OUT_BUF_RDY flag is cleared to complete
fetch of the receive one packet, and manage the next stage control. At this time, when the SETUP
packet is received, the SETUP flag is also cleared by setting “1” to CLR_SETUP bit.
• For shifting into the status stage even if the next data to be received or transmitted does not
exist, simultaneously set CLR_OUT_BUF_RDYbit (and also CLR_SETUP bit for the SETUP
packet) and SET_DATA_END bit to “1”.
• For responding with STALL response to the next token, simultaneously set
CLR_OUT_BUF_RDY bit (and also CLR_SETUP bit for the SETUP packet) and SEND_STALL
bit to “1”.
• When the valid new SETUP packet is received after setting SEND_STALL bit, clear
SEND_STALL bit and set CLR_OUT_BUF_RDY bit to “1” (and also CLR_SETUP bit for the
SETUP packet).
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(3) Control Transfer: Endpoint 0 Transmit
The endpoint 0 transmits the packet data to the host CPU in the data stage by the control read after
completion of receive request analysis process in the setup stage.
Write one packet data to be transmitted in IN FIFO. Every time that one-byte data is written in IN FIFO,
the internal write pointer is automatically incremented by “2” in word access and by “1” in byte access.
The contents of internal write pointer cannot be read. When the data write in IN FIFO is completed, set
IN_BUF_RDY flag to “1” by setting “1” to SET_IN_BUF_RDY bit. When an empty packet (with 0 data
length) is transmitted, data is not written in IN FIFO and SET_IN_BUF_RDY bit is set to “1”.
At this time, one packet transmission is prepared and is transmitted by the USB function control unit in
the next IN token.
The IN_BUF_RDY flag is automatically set to “0”, when one packet data transmission is completed to
the host CPU (or on receiving ACK) or when the SETUP_END flag is set to “1”. After writing the last
data packet in IN FIFO, set SET_IN_BUF_RDY bit to “1” and, simultaneously set SET_DATA_END bit
to “1”. Both the IN_BUF_RDY flag and DATA_END flag are set to “1”. When the DATA_END flag
becomes “1” after completion of transmission of the last data packet, the USB function control unit
proceeds to the status phase processing.
When the status phase is completed, the DATA_END flag is cleared to “0”.
Manage the stage of control transfer by software.
Example of one packet data transmit procedure
1: Check that the packet data does not exist in IN FIFO (the IN_BUF_RDY flag is “0”) before writing
the data of the 2nd packet and after of data stage.
2: The data is written in IN FIFO based on the amount specified on the SETUP stage.
When an empty packet (with 0 data length) is transmitted, the data is not written in IN FIFO.
The subsequent stage and operation are determined.
3: With SET_IN_BUF_RDY bit being set to “1”, one packet transmission is prepared, and the next
stage control is managed.
• For shifting into the status stage even if the next data to be transmitted does not exist, simulta-
neously set SET_IN_BUF_RDY bit and SET_DATA_END bit.
• When the next empty packet is transmitted, set SET_IN_BUF_RDY bit to “1” and continue
transmitting processing.
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2. USB function
(4) Control Transfer: Example of Standard Device Request Receive
The control transfer includes the setup stage, data stage and status stage.
Which one of write transfer, read transfer and no data transfer is executed in the data stage is deter-
mined by the content of the setup data acquired in the setup stage.
Examples of the receive processing routine of the SET_ADDRESS request and the
GET_CONFIGURATION request are described.
For rewriting USB address register when the SET_ADDRESS request is received, follow the proce-
dure below:
When the device is in the default state (USB address register value is “0”):
1: When USB address register is received the SET_ADDRESS request from the host CPU, store the
new address data in the USB address register.
2: When the status phase of the SET_ADDRESS request is completed, USB address register is
rewritten into the address written in above-mentioned 1:. When the status phase is not normally
completed, USB address register is not rewritten.
When the device is in the address state (USB address register value is other than “0”):
1: When USB address registeris received the SET_ADDRESS request from the host CPU, confirm
that the status phase of SET_ADDRESS request completes.
2: Store the new address data in USB address register.
The USB function control unit applies this address to all the subsequent device accesses.
The SET_ADDRESS request is shown in Figure 2.8.35, the device address acquisition processing
routine of USB SET_ADDRESS request is shown in Figure 2.8.36 and Figure 2.8.37, the device
configuration notification processing routine of GET_CONFIGURATION request is shown in Figure
2.8.38 and Figure 2.8.39.
Describe these processing to endpoint 0 interrupt processing.
1st byte
8th byte
wlength
bmRequestType
00000000B
bRequest
wValue
windex
000016
SET_ADDRESS
(code: 0516)
Device address
000016
Lower Higher
Figure 2.8.35. SET_ADDRESS Request
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2. USB function
Receiving of endpoint 0 setup packet
Confirming of receive data
(b15)
b7
(b8)
b0 b7
b0
USB endpoint 0 control and status register
EP0CS [Address 029816
0
0
]
OUT_BUF_RDY flag (Note 1)
0 : Reading data packet is complete
1 : Data packet reception is compete
SETUP flag
0 : Data packet reception
1 : SETUP packet reception
Note 1: There is no receive data in FIFO 0 when this bit is set to “0”.
Reading of receive data
(b15)
b7
(b8)
b0 b7
b0
USB endpoint 0 OUT FIFO data register
EP0O [Address 02E216
]
The data equal to receive byte count are read (setup packet is 8-byte).
Store the receive data in user definition RAM.
≠
To processing routine of
other standard requests
bRequest: 0516
?
=
≠
≠
To processing of request invalid
Is a request valid?
Valid
=
Getting of new address
(continued on next page)
USB addrtess register:
0016
?
=
Getting of address (default state)
Setting of receive device address to USB address register (Note 2)
(b15)
b7
(b8)
b0 b7
b0
USB address register
USBA [Address 028016
0
0
0
0
0
0
0
0
0
]
Set the third byte (the lower of wValue) of reception data
Note 2: Only the lower 1-byte of the receive device address should be set.
Setting of USB endpoint 0 control and status reister. Continued on a status stage.
(b15)
b7
(b8)
b0 b7
USB endpoint 0 control and status register
EP0CS [Address 029816
b0
]
1
1
1
0
0
CLR_OUT_BUF_RDY bit
1 : Clear OUT_BUF_RDY flag
CLR_SETUP flag
1 : Clear SETUP flag
SET_DATA_END bit
1 : Set DATA_END flag to “1”
Waiting for completion of status phase
Completion of SET_ADDRESS request
Figure 2.8.36. Processing routine (1) for getting device address when receiving SET_ADDRESS request
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2. USB function
(continued from previous page)
Getting of new address (address state)
Setting of USB endpoint 0 control and status register
(b15)
b7
(b8)
b0 b7
b0
USB endpoint 0 control and status register
EP0CS [Address 029816
1
1
1
0
0
]
CLR_OUT_BUF_RDY bit
1 : Clear OUT_BUF_RDY flag
CLR_SETUP flag
1 : Clear SETUP flag
SET_DATA_END bit
1 : Set DATA_END flag to “1”
Waiting for completion of status phase (DATA_END flag: 1 → 0)
Setting of address to USB address register (Note 1)
(b15)
b7
(b8)
b0 b7
b0
USB address register
USBA [Address 028016
0
0
0
0
0
0
0
0
0
]
Set the third byte (the lower of wValue) of reception data
Note 1: Only the lower 1-byte of the receive device address should be set.
Completion of SET_ADDRESS request
Figure 2.8.37. Processing routine (2) for getting device address when receiving SET_ADDRESS request
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2. USB function
Receiving of endpoint 0 setup packet
Confirming of receive data
(b15)
b7
(b8)
b0 b7
USB endpoint 0 control and status register
EP0CS [Address 029816
b0
]
0
0
OUT_BUF_RDY flag (Note 1)
0 : Reading data packet is complete
1 : Data packet reception is compete
SETUP flag
0 : Data packet reception
1 : SETUP packet reception
Note 1: There is no receive data in FIFO 0 when this bit is set to “0”.
Reading of receive data
(b15)
b7
(b8)
b0 b7
b0
USB endpoint 0 OUT FIFO data register
EP0O [Address 02E216
]
The data equal to receive byte count are read (setup packet is 8-byte).
Store the receive data in user definition RAM.
≠
To processing routine of
other standard requests
bRequest: 0816
?
=
≠
To processing of request invalid
Is a request valid?
Valid
=
Setting of USB endpoint 0 control and status register. Continued on a status stage.
(b15)
b7
(b8)
b0 b7
USB endpoint 0 control and status register
EP0CS [Address 029816
b0
1
]
1
0
0
CLR_OUT_BUF_RDY bit
1 : Clear OUT_BUF_RDY flag
CLR_SETUP flag
1 : Clear SETUP flag
Writing of transmit data on data stage
(b15)
b7
(b8)
b0 b7
b0
USB endpoint 0 IN FIFO data register
EP0I [Address 02E016
]
Write the configuration value one byte
Continued on next page
Figure 2.8.38. Device configuration notification processing routine (1) when receiving
GET_CONFIGURATION request
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2. USB function
Continued from previous page
Setting of USB endpoint 0 control and status reister (Note 1)
(b15)
b7
(b8)
b0 b7
USB endpoint 0 control and status register
b0
1
0
0
1
EP0CS [Address 029816
]
SET_IN_BUF_RDY bit
1 : Set IN_BUF_RDY flag to “1”
SET_DATA_END bit
1 : Set DATA_END flag to “1”
Note 1: Set the SET_IN_BUF_RDY bit and the SET_DATA_END bit simultaneously.
The USB function control unit is shifted to status stage
after the data are transmitted on data stage.
Waiting for completion of status phase
Completion of GET_CONFIGURATION request
Figure 2.8.39. Device configuration notification processing routine (2) when receiving
GET_CONFIGURATION request
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2. USB function
2.8.6 USB Operation (Endpoints 1 to 4 Receive)
Endpoints 1 to 4 can apply to the isochronous transfer, bulk transfer and interrupt transfer.
The endpoints 1 to 4 respectively have their IN (transmit) FIFOs and OUT (receive) FIFOs.
For using the endpoints 1 to 4 OUT, enable each endpoint OUT FIFO by USB endpoint enable register
(address 028E16). The size and the starting location (every 64 bytes) of each endpoint x(x=1 to 4) OUT
FIFO can be set according to the user's system. The buffer size of OUT FIFO can be set to a maximum of
1024 bytes per 64 bytes for one endpoint. When the double buffer mode is enabled, the buffer which has
twice as much as the set size is available for the OUT FIFO. The size and starting location of FIFO, the
double buffer mode enable can be set by USB endpoint x OUT FIFO configuration register (EPxOFC).
When one buffer data is received from the host CPU, the data are written to the endpoint x OUT FIFO and
the number of bytes of receive packet data are stored in USB endpoint x OUT write count register. When
a data receive request from the host CPU occurs while data are already written and OUT FIFO cannot be
received, NAK is automatically transmitted in bulk transfer/interrupt transfer, and an overrun occurs in
isochronous transfer, not receiving the packet data.
The data receive from the host CPU is controlled based on the communication status of endpoints 1 to 4
OUT.
The default of endpoints 1 to 4 is bulk transfer. Each endpoint should be initialized in order to use other
transfer modes.
The receive of endpoints 1 to 4 can select the following functions:
Continuous Receive Mode
This function is used for receiving data from the host PC at a higher speed. This mode can be set only
for endpoints 1 to 4 OUT bulk transfer. With continuous transfer mode bit of the EPxOFC being set to
“1”, the continuous receive mode is enabled. The USB function control unit writes the receive data
from the host PC in OUT FIFO sequentially by the maximum packet size that is set in USB endpoint x
OUT MAXP register (EPxOMP). (When the last one packet is smaller than the size set in the
EPxOMP, it is received as a short packet.)
When continuous receive mode is enabled, the buffer size has to be equal to an integral multiple of the
EPxOMP. Further, the user's system has to be comprehended beforehand that the receive data from
the host PC are equal to the buffer size or includes a short packet.
AUTO_CLR Function
When receive data from OUT FIFO are read, both the OUT_BUF_STS0 and the OUT_BUF_STS1
flags are updated without CLR_OUT_BUF_RDY bit being set to “1”. The AUTO_CLR function is en-
abled by setting AUTO_CLR bit of the EPxOCS to “1”. The AUTO_CLR function is available both in
the continuous receive mode and in the continuous receive mode disable of endpoints 1 to 4 OUT (Not
available with endpoint 0).
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2. USB function
(1) Related Registers
USB endpoint x(x=1 to 4) OUT control and status register
•OUT_BUF_STS1, OUT_BUF_STS0 flags
These flags indicate OUT FIFO state.
At the time of reading the receive data from the host PC, read these flags to confirm the OUT FIFO
state. When the OUT_BUF_STS1 and the OUT_BUF_STS0 flags are respectively set to “002”, there
are no data in OUT FIFO. When they are respectively set to “102”, there are only one buffer data in
double buffer. (Invalid for single buffer.) When they are respectively set to “112”, there are one buffer
data in single buffer while there are two buffer data in double buffer. When they are respectively set
to “012”, it is invalid.
These flags are updated when one of the following events occurs:
- One valid buffer data is successfully received from the host.
- One buffer data is successfully fetched from OUT FIFO.
CLR_OUT_BUF_RDY bit is set to “1” after read of one receive data from OUT FIFO completes.
(When the AUTO_CLR function is enabled, these flags are updated without CLR_OUT_BUF_RDY
bit being set to “1”.)
- The OUT FIFO buffer data are flushed. (When FLUSH bit is set to “1”.)
•OVER_RUN flag
This flag indicates occurrence of an overrun in isochronous transfer. The bit is valid only in isochro-
nous transfer. When OUT FIFO is not empty and disables receiving at start of the OUT token from
the host CPU, occurrence of an overrun is recognized, setting this bit to “1”.
Clear this flag by writing “1” to CLR_OVER_RUN bit.
•FORCE_STALL flag
This flag indicates occurrence of a packet size error.
When the data packet, which size exceeds USB endpoint x OUT MAXP register value, is transmitted
from the host CPU, this flag becomes “1”. While this bit is set to “1”, the USB function control unit
does not receive packet data. If it is in bulk transfer, also, STALL handshake is transmitted to the host
CPU.
Clear this flag by writing “1” to CLR_FORCE_STALL bit.
•DATA_ERR flag
This flag indicates occurrence of data error in isochronous transfer. The bit is valid only in isochro-
nous transfer. If any bit stuffing error or CRC error is detected in the received packet, this flag be-
comes “1”.
Clear this flag by writing “1” to CLR_DATA_ERR bit.
•CLR_OUT_BUF_RDY bit
This bit controls OUT FIFO. Set this bit to “1” after one receive buffer data is read from OUT FIFO.
Completion of one buffer data fetch is notified to the USB function control unit and, simultaneously,
the OUT_BUF_STS0 and OUT_BUF_STS1 flags are updated.
When the AUTO_CLR function is enabled, this bit does not need to be set up.
•CLR_OVER_RUN bit
The OVER_RUN flag is cleared to “0” by setting “1” to this bit.
•CLR_FORCE_STALL bit
The FORCE_STALL flag is cleared to “0” by setting “1” to this bit.
•CLR_DATA_ERR bit
The DATA_ERR flag is cleared to “0” by setting “1” to this bit.
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2. USB function
•TOGGLE_INIT bit
This bit initializes data toggle sequence bit in bulk/interrupt transfer.
With this bit being set to “1”, the PID of the next packet to be received from the host CPU becomes
DATA0. When initialization of the data toggle sequence is requested from the host CPU at the time of
configuration, etc., set TOGGLE_INIT bit and initialize PID to DATA0 before starting the OUT end-
point communication.
At this time, the internal read/write counter of OUT FIFO is also initialized.
On completing PID initialization, this bit is automatically cleared to “0”.
•FLUSH bit
This bit controls the OUT FIFO packet.
With this bit being set to “1”, one buffer data received in OUT FIFO is flushed out from the OUT FIFO.
- When there is one buffer data in OUT FIFO, the OUT FIFO becomes empty.
At this time, the OUT_BUF_STS1 and OUT_BUF_STS0 flags are updated from “112”(“102”) to
“002”.
- When there are two buffer data in OUT FIFO, the older data is flushed out from the OUT FIFO.
At this time, the OUT_BUF_STS1 and OUT_BUF_STS0 flags are updated from “112” to “102” (This
indicates that one more buffer data is left inside the OUT FIFO).
The receive data may be destroyed if this bit is set to “1” during USB transfer.
Read the OUT_BUF_STS1 and OUT_BUF_STS0 flags and confirm that there are data in the OUT
FIFO, and then, set this bit to “1”.
On completing one buffer data destruction, this bit is automatically cleared to “0”.
•ISO bit
Set this bit to “1” in order to use an endpoint in isochronous transfer. Set this bit to “0” in order to use
an endpoint in bulk/interrupt transfer.
•SEND_STALL bit
This bit controls the STALL response to the host CPU in bulk transfer/interrupt transfer.
Set this bit to “1” when the OUT endpoint is in STALL state. While this bit is set to “1”, the USB
function control unit transmits the STALL handshake concerning all the OUT transactions to the host
CPU. When the OUT endpoint has returned from STALL state, clear this bit by writing “0”. The OUT
endpoint communication is resumed.
•AUTO_CLR bit
This bit controls setting of CLR_OUT_BUF_RDY bit.
With this bit being set to “1”, when one receive buffer data is read from OUT FIFO, the OUT_BUF_STS1
and OUT_BUF_STS0 flags are automatically updated without CLR_OUT_BUF_RDY bitbeing set to
“1”. With this bit being set to “0”, on completing one receive buffer data fetch from OUT FIFO,
CLR_OUT_BUF_RDY bit has to be set to “1” by software.
The configuration of USB endpoint x OUT control and status register is shown in Figure 2.8.40.
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2. USB function
USB Endpoint x OUT Control and Status register
(b8)
b0
(b15)
b7
Address
02B616, 02BE16
02C616, 02CE16
b7
b0
When reset
000016
Symbol
EPxOCS (x = 1 - 4)
,
0
0
Bit Symbol
OUTxCSR0
OUTxCSR1
Bit Name
Function
These two bits indicate the EPx OUT buffer status:
R
O
W
X
OUT_BUF_STS0 flag
OUT_BUF_STS1 flag
Bit1
0
Bit0
0 : No data set in the OUT buffer
1 : Single buffer mode: N/A
O
X
0
Double buffer mode: N/A
1
1
0 : Single buffer mode: N/A
Double buffer mode: one data set in the OUT buffer
1 : Single buffer mode: one data set in the OUT buffer
Double buffer mode: two data sets in the OUT buffer
OVER-RUN flag
OUTxCSR2
OUTxCSR3
OUTxCSR4
OUTxCSR5
OUTxCSR6
0 : No over run detected
1 : Over run detected
O X
FORCE_STALL flag
DATA_ERR flag
0 : No packet size larger than MAXP violation detected
1 : Packet size larger than MAXP violation detected
O
X
0 : No data error detected
1 : Data error detected
O
O
X
0 : No action
O
CLR_OUT_BUF_RDY
CLR_OVER_RUN
1 : Data set unloaded from the OUT buffer (updates status flags)
Note
0 : No action
1 : Clears OVER_RUN flag
O
O
Note
0 : No action
1 : Clears FORCE_STALL flag
O
Note
O
O
CLR_FORCE_STALL
CLR_DATA_ERR
OUTxCSR7
OUTxCSR8
0 : No action
1 : Clears DATA_ERR flag
O
Note
0 : No action
O
Note
O
TOGGLE_INIT
FLUSH
OUTxCSR9
1 : Initialize the next data PID as a DATA0 for reception
0 : No action
1 : Flush out one data set
O
Note
O
OUTxCSR10
0 : Select non-isochronous endpoint
1 : Select isochronous endpoint
O
O
O
O
ISO
OUTxCSR11
OUTxCSR12
0 : No STALL by CPU
1 : STALL by CPU
SEND_STALL
0 : AUTO_CLR disabled
1 : AUTO_CLR enabled
AUTO_CLR
OUTxCSR13
Reserved
O
O
O
O
Must always be set to “0”
Note: Always read a “0” when writing to this bit.
Figure 2.8.40. USB endpoint x(x=1 to 4) OUT control and status register
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2. USB function
USB endpoint x(x=1 to 4) OUT MAXP register
This register indicates endpoint x(x=1~4) OUT maximum packet size. The default value is 0 byte.
When the endpoint is initialized due to any reason such as that the request for setting the endpoint
(SET_DESCRIPTOR, SET_CONFIGURATION, SET_INTERFACE, etc.) is received from the host
CPU, change the endpoint x OUT maximum packet size value by writing in this register. Set a packet
size value specified for every transfer type to be used.
The configuration of USB endpoint x(x=1 to 4) OUT MAXP register is shown in Figure 2.8.41.
USB Endpoint x OUT MAXP register
(b8)
b0
(b15)
b7
b7
b0
Address
02B816, 02C016
Symbol
EPxOMP (x = 1 - 4)
When reset
000016
,
0
0
0
0
0
0
02C816, 02D016
Bit Name
Maximum packet size
Bit Symbol
Function
R
W
Set maximum packet size of
EPx OUT
OMAXP9-0
Reserved
O
O
O
O
Must always be “0”
Figure 2.8.41. USB endpoint x(x=1 to 4) OUT MAXP register
USB endpoint x(x=1 to 4) OUT write count register
This 11-bit register contains the number of bytes of one buffer data written in the endpoint x(x=1~4)
OUT FIFO. This register is for read-only. When the USB function control unit completes the data
packet receive from the host CPU, set the value of this register. When one buffer data receive com-
pletes, read this register and determine the byte count of the data to be read from OUT FIFO. This
register value is not decremented even if the data are read from USB endpoint x OUT FIFO register .
When this register is read while there are two buffer data in OUT FIFO in the double buffer mode, the
number of bytes of the packet data received at first is already stored. When CLR_OUT_BUF_RDY bit
is set to “1” after one buffer data is read from OUT FIFO, this register value is updated to the number
of bytes of buffer data subsequently received.
The configuration of USB endpoint x(x=1 to 4) OUT write count register is shown in Figure 2.8.42.
USB Endpoint x OUT Write Count register
(b8)
b0
(b15)
b7
b7
b0
Address
02BA16, 02C216
Symbol
EPxWC (x = 1 - 4)
When reset
000016
,
0
0 0 0 0
02CA16, 02D216
Bit Name
Receive byte count
Bit Symbol
Function
R
W
The byte count of receive one buffer
data in the EPx OUT FIFO is set.
WCNT10-0
Reserved
O
O
X
O
Must always be “0”
Figure 2.8.42. USB endpoint x(x=1 to 4) OUT write count register
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2. USB function
USB endpoint x(x=1 to 4) OUT FIFO configuration register
This register sets endpoint x(x=1~4) OUT FIFO.
•BUF_NUM
This bit sets the starting location of the endpoint x(x= 1~4) OUT FIFO per 64 bytes. For example,
when OUT FIFO is allocated, starting at the 320th byte, the set value is “0001012”.
•BUF_SIZ
This bit sets one buffer size of the endpoint x(x= 1~4) OUT FIFO per 64 bytes. For example, when
256 bytes is set, the set value is “01002”.
•DBL_BUF
With this bit being set to “1”, OUT FIFO of the corresponding endpoint is changed into double buffer
mode. The byte count for a valid OUT FIFO becomes twice as much as the value specified by the
BUF_SIZ at the time of double buffer. Set carefully not to overlap with the FIFO start position of other
endpoints.
•CONTINUE
This bit enables continuous transfer mode.
Set this bit to “1” when continuous transfer is enabled. The bit is valid only in bulk transfer.
The USB function control unit writes the receive data from the host PC in OUT FIFO sequentially by
one packet size (the maximum packet size set in the EPxOMP) and receives continuously until one
buffer full or a short packet is received.
When continuous receive mode is enabled, the BUF_SIZ has to be equal to an integral multiple of
the EPxOMP. Further, the user's system has to be comprehended beforehand that the receive data
from the host PC are equal to the buffer size or includes a short packet.
Pay attention to the following when setting the BUF_NUM/BUF_SIZ:
- Not exceed 3072 bytes in OUT FIFO starting location + OUT FIFO size.
- Not overlap Endpoint FIFOs each other.
USB Endpoint x OUT FIFO register
(b8)
b0
(b15)
b7
b7
b0
Address
02BC16, 02C416,
02CC16, 02D416
Symbol
EPxOFC (x = 1 - 4)
When reset
000016
0
0 0 0
R
O
W
O
Function
Bit Name
Bit Symbol
BUF_NUM
Select the starting number for the EPx OUT FIFO
(in units of 64 bytes)
000000 : buffer stating location = 0
000001 : buffer stating location = 64
000010 : buffer stating location = 128
......
FIFO buffer
start number
101111 : buffer stating location = 3008 (last starting number)
Select the buffer size for the EPx OUT FIFO
(in units of 64 bytes)
0000 : buffer stating location = 64
0001 : buffer stating location = 128
0010 : buffer stating location = 192
......
BUF_SIZ
DBL_BUF
FIFO buffer size
O
O
O
O
1111 : buffer stating location = 1024 (largest buffer size)
0 : Disabled
1 : Enabled
Double buffer mode
Continuous transfer
0 : Disabled (Note)
1 : Enabled
CONTINUE mode
O
O
O
O
Must always be “0”
Reserved
Note: Valid for bulk transfer type only
Figure 2.8.43. USB endpoint x(x=1 to 4) OUT FIFO configuration register
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2. USB function
(2) Bulk Transfer: Endpoints 1 to 4 Receive
Setting of Transfer Type
When endpoints 1 to 4 OUT are used for bulk transfer, ISO bit of USB endpoint x(x=1 to 4) OUT
control and status register is set to “0” for bulk transfer setting.
Also, for initialization of toggle sequence bit in bulk transfer, set TOGGLE_INIT bit to “1” and initialize
PID to DATA0.
Set by using USB endpoint x OUT FIFO configuration register in order to enable double buffer mode
and continuous receive mode.
Set AUTO_CLR bit of USB endpoint x OUT control and status register to “1” in order to use the
AUTO_CLR function.
Receive Operation
When one packet data (Note 1) is received in OUT FIFO, the OUT_BUF_STS1 and the OUT_BUF_STS0
flags of the corresponding EPxOCS are automatically updated. In single buffer mode (when double
buffer mode bit is “0”), these flags are updated from “002” to “112”. In double buffer mode, they are
updated as follows:
•When the first one packet data (Note 1) of the double buffer has been written to the OUT FIFO and
the second packet data (Note 1) is ready to be written, the OUT_BUF_STS1 and OUT_BUF_STS0
flags are updated from “002” to “102”.
•
When two packet data (Note 1) have been written in OUT FIFO, the OUT_BUF_STS1 and
OUT_BUF_STS0 flags are updated from “102” to “112”".
Note 1: In continuous transfer enable, read the description by substituting the underlined part with
“buffer data”. The USB function control unit writes the receive data from the host PC in OUT
FIFO sequentially by one packet size (the maximum packet size set in the EPxOMP), re-
ceives continuously until one buffer full or a short packet is received.
When the OUT token is received from the host CPU while SEND_STALL bit is set to “1”, STALL
response is automatically returned.
When there is a packet space in OUT FIFO, on receiving the OUT token from the host CPU in the
current data toggle sequence bit, the data are received and ACK response is returned. At this time,
the OUT FIFO status is updated (updates the OUT_BUF_STS1 and OUT_BUF_STS0 flags) and
data toggle sequence bit is toggled (DATA0 → DATA1 or DATA1 → DATA0). Further, the endpoint
x OUT interrupt request occurs.
When there is a packet space in OUT FIFO, on receiving the OUT token from the host CPU in the
toggle which is different from the current data toggle sequence bit, it is regarded that the ACK having
responded for the packet previously received has dropped and, therefore, the host CPU has trans-
mitted the same data. Only ACK response, therefore, is returned without receiving the data.
When the OUT token is received from the host CPU while there are already data in OUT FIFO and
packet data cannot be received, NAK response is automatically returned.
When a packet, which size exceeds the maximum packet size, is transmitted from the host CPU,
STALL response automatically is returned without receiving the data. At this time, the
FORCE_STALL flag is set to “1” and, when error interrupt has been enabled by USB function inter-
rupt enable register, an error interrupt request occurs (INTST8 is set to “1”).
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2. USB function
When an error is detected in bulk OUT transfer, a response is not returned without ACK and NAK
responses (Error checks such as CRC check and bit-justification, conforming to USB2.0 specifica-
tion, are automatically performed. So the error does not have to be controlled by software).
Fetch of Receive Data
On receiving one packet data (Note 2), the received packet data (Note 2) from OUT FIFO is read.
Fetch one packet data (Note 2) in the following procedure:
1: Confirm that there are receive data in the OUT FIFO by the statuses of the OUT_BUF_STS1 and
OUT_BUF_STS0 flags.
2: Determine the data byte count to be read from the OUT FIFO by reading USB endpoint x(x=1 to
4) OUT write count register .
3: Read the data byte count determined in the above 2: from the OUT FIFO.
Every time that 1(2)-byte data are read from the OUT FIFO, the internal write pointer is automati-
cally decremented by one(two). (Content of the internal write pointer cannot be read.)
4: Set CLR_OUT_BUF_RDY bit to “1” to complete one receive packet data fetch (Note 2).
At this time, the OUT FIFO status (OUT_BUF_STS1 and OUT_BUF_STS0 flags) are updated,
enabling a receive of the next one packet data (Note 2).
•In Single Buffer Mode
The OUT_BUF_STS1 and OUT_BUT_STS0 flags are updated from “112” (the OUT FIFO full) to
“002” (the OUT FIFO empty).
•In Double Buffer Mode
When there are one more packet data (Note 2) in the OUT FIFO, the OUT_BUF_STS1 and
OUT_BUF_STS1 flags are updated from “112” (the OUT FIFO full) to “102” (one data set in the
OUT FIFO). In this case, the second packet data (Note 2) can be continuously fetched.
When there are no data packet does in the OUT FIFO, the OUT_BUF_STS1 and
OUT_BUF_STS1 flags are updated from “102” (one data set in the OUT FIFO) to “002” (the OUT
FIFO empty).
When one packet data (Note 2) is read from the OUT FIFO while the AUTO_CLR function is en-
abled (AUTO_CLR bit is “1”), the OUT_BUF_STS1 and OUT_BUF_STS0 flags are automatically
updated without CLR_OUT_BUF_RDY bit being set to “1”.
Note 2: In continuous transfer enable, read the description by substituting the underlined part with
“buffer data”. On receiving one buffer full (data equal to byte count set in the BUF_SIZ) or a
short packet, one buffer data receive is completed. Also, the BUF_SIZ has to be equal to an
integral multiple of the EPxOMP.
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2. USB function
(3) Isochronous Transfer: Endpoints 1 to 4 Receive
Setting of Transfer Type
When endpoints 1 to 4 OUT are used for isochronous transfer, ISO bit of USB endpoint x(x=1 to 4)
OUT control and status register is set to “1” for isochronous transfer setting.
Receive Operation
When there is a packet space in OUT FIFO, on receiving the OUT token from the host CPU, the data
are received. At this time, the OUT FIFO status is updated, the endpoint x OUT interrupt request
occurs. When an error is detected in the received packet, simultaneously, the DATA_ERR flag is set
to “1”. (Error checks such as CRC check, conforming to USB2.0 specification, are automatically
performed.)
When the OUT token is received from the host CPU while there are already data in OUT FIFO and
packet data cannot be received, an overrun error occurs. At this time, the OVER_RUN flag is set to
“1”.
Further, when a packet, which size exceeds the maximum packet size, is transmitted from the host
CPU, the FORCE_STALL flag is set to “1” without receiving the data. While error interrupt has been
enabled by USB function interrupt enable register, an error interrupt request occurs when any one of
the OVER_RUN flag, FORCE_STALL flag or DATA_ERR flag is set to “1” (INTST8 is set to “1”).
Fetch of Receive Data
The fetch procedure of endpoint x OUT receive data in the isochronous transfer is same as the bulk
transfer.
Refer to “ Fetch of Receive Data” of “(2) Bulk Transfer: Endpoints 1 to 4 Receive”. (Although
continuous transfer is valid for the bulk transfer only.)
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2. USB function
(4) Interrupt Transfer: Endpoints 1 to 4 Receive
Setting of Transfer Type
When endpoints 1 to 4 OUT are used for interrupt transfer, ISO bit of USB endpoint x(x=1 to 4) OUT
control and status register is set to “0” for interrupt transfer setting.
Also, for initialization of toggle sequence bit in interrupt transfer, set TOGGLE_INIT bit to “1” and
initialize PID to DATA0.
Receive Operation
The endpoint x OUT receive operation in the interrupt transfer is same as the bulk transfer.
Refer to “ Receive Operation” of “(2) Bulk Transfer: Endpoints 1 to 4 Receive”.
Fetch of Receive Data
The fetch procedure of endpoint x OUT receive data in the interrupt transfer is same as the bulk
transfer.
Refer to “ Fetch of Receive Data” of “(2) Bulk Transfer: Endpoints 1 to 4 Receive”. (Although
continuous transfer is valid for the bulk transfer only.)
(5) Precautions for Receive
Read from OUT FIFO
Be sure to confirm the OUT_BUF_STS1 and OUT_BUF_STS0 flags states when reading data from
the OUT FIFO. Based on these flags states, judge whether there are receive data in the OUT FIFO.
Be sure to read the byte count of data specified by USB endpoint x OUT write count register value
before setting CLR_OUT_BUF_RDYbitto “1” when reading data from the OUT FIFO. If the
CLR_OUT_BUF_RDY bit is set to “1” during fetching of data from the OUT FIFO, the setting can
cause malfunction of the internal read pointer.
Table 2.8.3. Status on Endpoint 1 to 4 OUT FIFOs
Single buffer
[Specify OUT FIFO size
by the BUF_SIZ*1]
No data
Double buffer [OUT FIFO size =
(The number of bytes specified
by the BUF_SIZ*1 ) 2]
No data
OUT_BUF_STS0
0
OUT_BUF_STS1
0
Space equal to one buffer
Invalid
Space equal to two buffer
Invalid
1
0
0
1
Invalid
One data set in the OUT FIFO
Space equal to one buffer
Two data set in the OUT FIFO
No space in the OUT FIFO
1
1
One data set in the OUT FIFO
No space in the OUT FIFO
*1: Bits 6 to 9 of EPxOFC.
PID Initialization
When TOGGLE_INIT bit is set to “1”, the read/write counter inside the FIFO is initialized. To initialize
the PID, set TOGGLE_INIT bit to “1” when the OUT FIFO is empty (the OUT_BUF_STS0 and
OUT_BUF_STS1 flags are “002”).
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2. USB function
(6) USB Receive (Endpoints 1 to 4 OUT): Example
The endpoints 1 to 4 OUT packet fetching routine (in continuous transfer disable) is shown in Figure
2.8.44. In addition to packet fetch process, error flag (OVER_RUN, FORCE_STALL, DATA_ERR)
process is required for every transfer type.
Process of USB endpoint x OUT packet fetch
1. Confirming of whether one packet is received in the OUT FIFO:
check the OUT_BUF_STS0 and the OUT_BUF_STS1.
(b15)
b7
(b8)
b0 b7
b0
USB endpoint x OUT control and status register
EPxOCS (x = 1 - 4) [Address 02B616, 02BE16, 02C616, 02CE16]
0
0
OUT_BUF_STS0 flag
OUT_BUF_STS1 flag
b1 b0
0 0 : No data set in the OUT buffer
0 1 : Invalid
1 0 : Single buffer mode: Invalid
Double buffer mode: one data set in the OUT buffer
1 1 : Single buffer mode: one data set in the OUT buffer
Double buffer mode: two data set in the OUT buffer
No data set in the OUT FIFO
Data set in the OUT FIFO
2. Reading of the number of receive one packet data (Note 1) and
storing it in the RAM_CNT (user definition RAM).
(b15)
b7
(b8)
b0 b7
b0
USB endpoint x OUT write count register
EPxWC (x = 1 - 4) [Address 02BA16, 02C216, 02CA16, 02D216]
0
0
0
0
0
Read the number of bytes of reception data and
store it in the RAM_CNT
Note 1: The packet data is one buffer data in continuous transfer mode.
3. Reading of receive data equal to receive data count (RAM_CNT) from the OUT FIFO
and storing it in the RAM_DATA (user definition RAM).
(b15)
b7
(b8)
b0 b7
b0
USB endpoint x OUT FIFO data register
EPxO (x = 0 - 4) [Address 02E216, 02E616, 02EA16, 02EE16, 02F216]
Read the reception data and store it in the RAM_DATA
Note 2: Define the RAM_DATA equal to byte count required for receive.
4. Setting of the CLR_OUT_BUF_RDY bit to “1” and
completion (Note 4) of one packet data (Note 3) fetch.
(b15)
(b8)
b7
b0 b7
b0
USB endpoint x OUT control and status register
EPxOCS (x = 1 - 4) [Address 02B616, 02BE16, 02C616, 02CE16]
0
0
1
CLR_OUT_BUF_RDY bit
1 : Updates OUT_BUF_STS0, OUT_BUF_STS1 flags
Note 3: The packet data is one buffer data in continuous transfer mode.
Note 4: When the AUTO_CLR bit is set to “1”, the OUT_BU_STS0 and the OUT_BUF_STS1 flags are
automatically updated without setting “1” to the CLR_OUT_BUF_RDY bit when the data count equal to
one packet is read from the OUT FIFO.
Execution of the above 2, 3 and 4 when one more are set in the OUT FIFO
Completion of packet fetch
Figure 2.8.44. Endpoint 1 to 4 OUT packet fetching routine
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2. USB function
2.8.7 USB Operation (Endpoints 1 to 4 Transmit)
Endpoints 1 to 4 can apply to the isochronous transfer, bulk transfer and interrupt transfer.
The endpoints 1 to 4 respectively have their IN (transmit) FIFOs and OUT (receive) FIFOs.
For using the endpoints 1 to 4 IN, enable each endpoint IN FIFO by USB endpoint enable register (ad-
dress 028E16). The size and the starting location (every 64 bytes) of each endpoint x(x=1~4) IN FIFO can
be set according to the user's system. The buffer size of IN FIFO can be set to a maximum of 1024 bytes
per 64 bytes for one endpoint. When the double buffer mode is enabled, the buffer which has twice as
much as the set size is available for the IN FIFO. The size and starting location of FIFO, the double buffer
mode enable can be set by USB endpoint x IN FIFO configuration register(EPxIFC).
When packet data are transmitted to the host CPU, the data are written to the endpoint x IN FIFO. When
a data transmit request from the host CPU occurs before the data are written to IN FIFO, NAK is automati-
cally transmitted in bulk transfer and interrupt transfer, or an empty packet (with 0 data length) is auto-
matically transmitted in isochronous transfer.
The data transmitted to the host CPU is controlled based on the communication status of endpoints 1 to
4 IN. The default of endpoints 1 to 4 is bulk transfer. Each endpoint should be initialized in order to use
other transfer modes.
The transmit of endpoints 1 to 4 can select the following functions.
Continuous Transmit Mode
This function is used for transmitting data at a higher speed. This mode can be set only for endpoints
1 to 4 IN bulk transfer. With continuous tranfer mode bit of the EPxIFC being set to “1”, the continuous
transmit mode is enabled.
In continuous transmit mode, the USB function control unit, by dividing the data in IN FIFO into one
packet size (the maximum packet size set in the EPxIMP) units, transmits them one by one to the host
PC (When the last one packet is smaller than the size set in the EPxIMP, it is transmitted as a short
packet.) When continuous transmit mode is enabled, the IN FIFO size has to be equal to an integral
multiple of the maximum packet size.
AUTO_SET Function
With AUTO_SET bit of EPxICS being set to “1”, the AUTO_SET function is enabled. When transmit
data of the buffer size (specified in the BUF_SIZ) is written to the IN FIFO in AUTO_SET enable state,
the IN_BUF_STS0 and IN_BUF_STS1 flags are updated without SET_IN_BUF_RDY bit being set to
“1”. However, when a short packet (data whose size is smaller than the EPxIMP value in continuous
transfer disable or than the BUF_SIZ value in continuous transfer enable) has been written, the
IN_BUF_STS1, IN_BUF_STS0 flags are not automatically updated. In these cases, the completion of
data transmit ready is indicated by setting SET_IN_BUF_RDY bit to “1”. The AUTO_SET function is
useable both in continuous transmit mode and in continuous transmit mode disable of endpoints 1 to
4 IN (Not available with endpoint 0).
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2. USB function
(1) Related Registers
USB ISO control register
This register controls isochronous transfer of endpoints 1 to 4. This register setting is valid for all the
isochronous transfer IN endpoints that are used simultaneously.
•AUTO_FLUSH bit
This bit controls transmit packet data destruction in isochronous transfer. This bit can be used only
when setting “1” to both ISO_UPDATE bit and ISO bit. The bit is valid only for the IN endpoints 1 to
4 in isochronous transfer.
While ISO_UPDATE bit =“1”, AUTO_FLUSH bit =“1”, and ISO bit (INxCSR8)=“1”, the USB function
control unit, at the time of detecting SOF packet (on receiving from the host PC or on the artificial
SOF operation), automatically flushes old data packet inside the IN FIFO if both the IN_BUF_STS1
and the IN_BUF_STS0 flags are “1” (IN FIFO full state). In isochronous transfer for double buffer,
use the AUTO FLUSH function.
•ISO_UPDATE bit
This bit controls the transmit timing of packet data in isochronous transfer. The bit is valid only for the
IN endpoints 1 to 4 in isochronous transfer.
While ISO_UPDATE bit =“0” and ISO bit =“1”, the USB function control unit, at the time of receiving
of an IN token from the host CPU, transmits one packet of the IN FIFO data if SET_IN_BUF_RDY bit
of the corresponding endpoint has been set beforehand to “1”.
While ISO_UPDATE bit =“1” and ISO bit =“1”, a packet control internal signal is not output to the
transmit control circuit inside the USB function control unit even if SET_IN_BUF_RDY bit of the
corresponding endpoint is set to “1” (even if a data packet whose size is equal to the maximum
packet size is written to the IN FIFO when AUTO_SET function is enabled). Setting “1” to
SET_IN_BUF_RDY bit, which is the packet control signal, is delayed until the next SOF is received
so that transmission of the IN FIFO data packet is delayed. The USB function control unit, on detect-
ing that there are transmit packet data at the time of status updating of the IN FIFO, operates artifi-
cially as having no transmit packet data until the next SOF packet is detected. On detecting SOF
packet, one packet of data which has been set to the IN FIFO is transmitted to the IN token from the
host CPU.
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2. USB function
•Artificial SOF enable bit
This bit enables the artificial SOF function.
With this bit being set to “1”, when a SOF packet from the host PC has been destroyed due to any
cause and no valid SOF packet has been received even after 1ms from the preceding start of the
frame, the artificial SOF receive is operated. (And the USB SOF interrupt request, also, occurs.)
Therefore, even if the SOF packet is destroyed due to any cause, a new frame can be formed by this
function without waiting for the next SOF packet. The artificial SOF receive function is operated once
after the valid SOF packet is received twice.
•Artificial SOF status flag
This flag is the artificial SOF function status flag.
This flag is valid when the artificial SOF function has been enabled (Artificial SOF enable bit is “1”).
With this flag being set to “1”, an artificial SOF receive has occurred by the artificial SOF function.
This flag is cleared by setting “1” to CLR_ART_SOF bit .
•Artificial SOF status clear bit
Artificial SOF status flag is cleared to “0” by setting “1” to this bit.
The configuration of USB ISO control register is shown in Figure 2.8.45.
USB ISO Control register
(b8)
b0
(b15)
b7
b7
b0
Symbol
USBISOC
Address
028C16
When reset
000016
0
0
0
0
0
0
0
0
0 0 0
Function
Bit Symbol
Bit Name
Auto flush bit
R
O
W
O
0 : Hardware auto flush disabled
1 : Hardware auto flush enabled
AUTO_FL
0 : ISO update disabled
1 : ISO update enabled
ISO_UPD
ISO Update bit
O
O
O
O
O
X
0 : Artificial SOF disabled
1 : Artificial SOF enabled
ART_SOF_ENA
ART_SOF_SET
CLR_ART_SOF
Reserved
Artificial SOF enable bit
Artificial SOF set flag
Clear artificial SOF set flag
0 : Not generated by device (Note 1)
1 : Generated by the device
0 : No action
1 : Clear ART_SOF_SET flag
O
O
O
(Note 2)
Must always be “0”
O
Note 1: Read only.
Note 2: Always read “0”.
Figure 2.8.45. USB ISO control register
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2. USB function
USB endpoint x(x=1 to 4) IN control and status register
•IN_BUF_STS1, IN_BUF_STS0 flags
These flags indicate IN FIFO state.
At the time of writing the data to be transmitted to the host PC in IN FIFO, read these flags to confirm
the IN FIFO state.
They are respectively set to “112” at the time of resetting. When the corresponding endpoint be-
comes enable state from disable state, the IN_BUF_STS1 and the IN_BUF_STS0 flags are respec-
tively cleared to “002”, automatically. When they are “002”, there are no data in IN FIFO. When they
are respectively set to “012”, there are only one buffer data in double buffer (Invalid for single buffer) .
When they are respectively set to “112”, there are no space in IN FIFO. (There are one buffer data in
single buffer while there are two buffer data in double buffer.) When they are respectively set to “102”,
it is invalid.
These flags are updated when one of the following events occurs:
- One buffer data of IN FIFO is successfully transmitted to the host PC.
- One buffer data is successfully prepared in IN FIFO
SET_IN_BUF_RDY bit is set to “1” when writing of one transmit data to the IN FIFO completes. Or,
at the time of AUTO_SET enable, when the data count equal to the EPxIMP (or the BUF_SIZ in
continuous transfer enable) has been written in the FIFO. However, when a short packet has been
written at the time of AUTO_SET enable, these flags are not automatically updated. In such cases,
set SET_IN_BUF_RDY bit to “1” by software.
- One buffer data is flushed.
•UNDER_RUN flag
This flag indicates occurrence of an underrun in isochronous transfer. The bit is valid only in isochro-
nous IN transfer. When there are no data packet in IN FIFO at start of the IN token from the host
CPU, occurrence of an underrun is recognized and this flag is set to “1”. This flag is cleared to “0” by
setting “1” to CLR_UNDER_RUN bit .
•SET_IN_BUF_RDY bit
This bit controls IN FIFO. When there is a space in IN FIFO (when IN_BUF_STS1, IN_BUF_STS0=“002”
in single buffer, or IN_BUF_STS1, IN_BUF_STS0=“002” or “012” in double buffer enable), data can
be written in the IN FIFO. One transmit data is prepared by setting this bit to “1” after writing the
transmit data to the IN FIFO. (To transmit an empty packet, set this bit to “1” without writing any data.)
When this bit is set to “1”, the completion of one transmit data ready is notified to the USB function
control unit and, simultaneously, the IN FIFO status (IN_BUF_STS1, IN_BUF_STS0 flags) is up-
dated. In the AUTO_SET enable, when a short packet (data whose size is smaller than the EPxIMP
value in continuous transfer disable or the BUF_SIZ value in continuous transfer enable) has been
written, the IN_BUF_STS1 and IN_BUF_STS0 flags are not automatically updated. In this case, set
this bit to “1”.
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2. USB function
•CLR_UNDER_RUN bit
The UNDER_RUN flag is cleared to “0” by setting “1” to this bit.
•TOGGLE_INIT bit
This bit initializes data toggle bit required in bulk and interrupt transfer.
When initialization of the data toggle sequence is requested from the host CPU at the time of configu-
ration, etc., set this bit to “1” before starting the IN endpoint communication and initialize PID to
DATA0. At this time, the internal read/write pointer of IN FIFO is also initialized.
•FLUSH bit
This bit controls the IN FIFO packet.
Read the IN_BUF_STS1 and IN_BUF_STS0 flags and confirm that there are data in the IN FIFO,
and then, set this bit to “1”. When the IN FIFO is flushed, the IN_BUF_STS1 and IN_BUF_STS0 flags
are updated as follows:
- When there is one buffer data in IN FIFO, the IN FIFO becomes empty.
At this time, the IN_BUF_STS1 and IN_BUF_STS0 flags are updated to “002”.
- When two buffer data exist in IN FIFO, the older data is flushed.
At this time, the IN_BUF_STS1 and IN_BUF_STS0 flags are updated to “012”. (This indicates that
one more buffer data is left inside the IN FIFO.)
The transmit data may be destroyed if this bit is set to “1” during USB transfer.
On completing one buffer data flush, this bit is automatically cleared to “0”.
•INTPT bit
This bit controls transfer mode in interrupt transfer. Only when using the IN endpoint for the rate
feedback interrupt transfer, set this bit to “1”.
With this bit being set to “1”, when an IN token is received from the host CPU, IN FIFO data are
transmitted regardless of the IN_BUF_STS1 and IN_BUF_STS0 flag states or the data toggle.
Fix this bit at “0” for isochronous transfer, bulk transfer, and normal interrupt transfer.
•ISO bit
This bit controls isochronous transfer. With this bit being set to “1”, the IN endpoint is used for isoch-
ronous transfer. Fix this bit at “0” for bulk transfer and interrupt transfer.
•SEND_STALL bit
This bit controls the STALL response to the host CPU.
Set this bit to “1” when the IN endpoint is in STALL state. While this bit is set to “1”, the USB function
control unit transmits the STALL handshake concerning all the IN transactions to the host CPU.
When the IN endpoint has returned from STALL state, write “0” to clear this bit. The IN endpoint
communication is resumed.
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2. USB function
-AUTO_SET bit
This bit controls setting of SET_IN_BUF_RDY bit.
With this bit being set to “1”, when one data packet whose is equal to the maximum packet size
(EPxIMP set value) has been written to IN FIFO in continuous transmit disable, or, when data equal
to the buffer size (byte count set in the BUF_SIZ of the EPxIFC) have been written to IN FIFO in
continuous transmit enable, the IN_BUF_STS1 and IN_BUF_STS0 flags are updated without
SET_IN_BUF_RDY bit being set to “1”.
However, when a short packet (data whose size is smaller than the EPxIMP value in continuous
transfer disable or the BUF_SIZ value in continuous transfer enable) has been written,
IN_BUF_STS1 and IN_BUF_STS0 flags are not automatically updated. In such cases, set
SET_IN_BUF_RDY bit to “1” by software.
With this bit being set to “0”, set SET_IN_BUF_RDY bit to “1” by software after the transmit data are
written to IN FIFO.
The configuration of USB endpoint x (x=1 to 4) IN control and status register is shown in Figure 2.8.46.
USB Endpoint x IN Control and Status register
(b8)
b0
(b15)
b7
b7
b0
Symbol
EPxICS (x = 1 - 4)
Address
029E16, 02A416,
02AA16, 02B016
When reset
000316
0
0 0 0 0
Bit Symbol
Function
These two bits indicate the EPx IN buffer status
R
O
W
X
Bit Name
INxCSR0
INxCSR1
IN_BUF_STS0 flag
IN_BUF_STS1 flag
Bit1
0
Bit0
0 : No data set in the IN buffer
1 : Single buffer mode: N/A
O
X
0
Double buffer mode: one data set in the IN buffer
0 : Single buffer mode: N/A
Double buffer mode: N/A
1 : Single buffer mode: one data set in the IN buffer
Double buffer mode: two data sets in the IN buffer
1
1
INxCSR2
INxCSR3
INxCSR4
INxCSR5
UNDER-RUN flag
SET_IN_BUF_RDY
CLR_UNDER_RUN
TOGGLE_INT
0 : No underrun detected
1 : Underrun detected
O
O
x
0 : No action
O
1 : Data set loaded to the IN buffer (updates IN buffer status flags)
Note
0 : No action
1 : Clears UNDER_RUN flag
O
Note
O
0 : No action
O
Note
O
1 : Initialize the next data PID as a DATA0 for transmission
0 : No action
1 : Flush out one data set
O
O
O
Note
INxCSR6
INxCSR7
FLUSH
INTPT
0 : Select non-rate feedback interrupt transfer
1 : Select rate feedback interrupt transfer
O
0 : Select non-isochronous endpoint
1 : Select isochronous endpoint
INxCSR8
INxCSR9
ISO
O
O
O
O
0 : No STALL by CPU
1 : STALL by CPU
SEND_STALL
AUTO_SET
0 : AUTO_SET disabled
1 : AUTO_SET enabled
O
O
O
O
INxCSR10
Reserved
Must always be set to “0”
Note: Always read a “0”.
Figure 2.8.46. USB endpoint x(x=1 to 4) IN control and status register
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2. USB function
USB endpoint x(x=1 to 4) IN MAXP register
This register indicates endpoint x(x=1 to 4) IN maximum packet size. The default value is 0 byte.
When the endpoint is initialized due to any reason such as that the request for setting the endpoint
(SET_DESCRIPTOR, SET_CONFIGURATION, SET_INTERFACE, etc.) is received from the host
CPU, change the endpoint x IN maximum packet size value by writing in this register. Set a packet
size value specified for every transfer type to be used.
The configuration of USB endpoint x(x=1 to 4) IN MAXP register is shown in Figure 2.8.47.
USB Endpoint x IN MAXP register
(b8)
b0
(b15)
b7
b7
b0
Address
02A016, 02A616,
02AC16, 02B216
Symbol
EPxIMP ( x = 1 - 4)
When reset
000016
0
0
0
0
0
0
Bit Symbol
Bit Name
Function
R
W
Endpoint x IN
maximum packet size
Set the endpoint x IN
maximum packet size
IMAXP9-0
Reserved
O
O
O
O
Must always be set to “0”
Figure 2.8.47. USB endpoint x(x=1 to 4) IN MAXP register
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USB endpoint x(x=1 to 4) IN FIFO configuration register
This register sets endpoint x(x=1 to 4) IN FIFO.
•BUF_NUM
This bit sets the starting location of the endpoint x(x= 1 to 4) IN FIFO per 64 bytes. For example,
when IN FIFO is allocated, starting at the 320th byte, the set value is “0001012”.
•BUF_SIZ
This bit sets one buffer size of the endpoint x(x= 1 to 4) IN FIFO per 64 bytes. For example, when 256
bytes is set, the set value is “01002”.
•DBL_BUF
With this bit being set to “1”, IN FIFO of the corresponding endpoint is changed into double buffer
mode. The byte count for a valid IN FIFO becomes twice as much as the value specified by the
BUF_SIZ at the time of double buffer. Set carefully not to overlap with the FIFO start position of other
endpoints.
•CONTINUE
Set this bit to “1” when continuous transmit is enabled. The bit is valid only in bulk transfer.
The USB function control unit, by dividing one buffer data equal to the byte count set in the BUF_SIZ
in the IN FIFO into one packet size (the maximum packet size set in the EPxIMP) units, transmits
them one by one to the host PC. (When the last one packet is smaller than the size set in the
EPxIMP, it is transmitted as a short packet.) When continuous transmit mode is enabled, the value
set in the BUF_SIZ has to be equal to an integral multiple of the maximum packet size.
Pay attention to the following when setting this register:
- Not exceed 3072 bytes in IN FIFO starting location + IN FIFO size.
- Not overlap endpoint FIFOs each other.
The configuration of USB endpoint x(x=1 to 4) IN FIFO configuration register is shown in Figure
2.8.48.
USB Endpoint x IN FIFO register
(b8)
b0
(b15)
b7
b7
b0
Address
Symbol
EPxIFC (x = 1 - 4)
When reset
000016
02A216, 02A816,
0
0 0 0
02AE16, 02B416
R
O
W
O
Function
Bit Name
Bit Symbol
BUF_NUM
Select the starting number for the EPx IN FIFO
(in units of 64 bytes)
000000 : buffer stating location = 0
000001 : buffer stating location = 64
000010 : buffer stating location = 128
......
FIFO buffer
start number
101111 : buffer stating location = 3008 (last starting number)
Select the buffer size for the EPx IN FIFO
(in units of 64 bytes)
0000 : buffer stating location = 64
0001 : buffer stating location = 128
0010 : buffer stating location = 192
......
BUF_SIZ
DBL_BUF
FIFO buffer size
O
O
O
O
1111 : buffer stating location = 1024 (largest buffer size)
0 : Disabled
1 : Enabled
Double buffer mode
Continuous transfer
0 : Disabled
1 : Enabled (Note)
CONTINUE mode
O
O
O
O
Must always be set to “0”
Reserved
Note: Valid for bulk transfer type only.
Figure 2.8.48. USB endpoint x(x=1 to 4) IN FIFO configuration register
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2. USB function
(2) Bulk Transfer: Endpoints 1 to 4 Transmit
Setting of Transfer Type
When endpoints 1 to 4 IN are used for bulk transfer, both ISO bit and INTPT bit of USB endpoint x IN
control and status register are set to “0” for bulk transfer setting.
Also, for initialization of toggle sequence bit in bulk transfer, set TOGGLE_INIT bit to “1” and initialize
PID to DATA0.
In order to enable double buffer mode and continuous transmit mode, use USB endpoint x IN FIFO
configuration register for setting.
In order to use the AUTO_SET function, set AUTO_SET bit of USB endpoint x IN control and status
register to “1”.
Transmit Data Preparation
The transmit data has to be beforehand prepared in IN FIFO in order to transmit data. Prepare one
packet data (Note 1) to the IN FIFO in the following procedure:
1: Confirm that there is a packet space in the IN FIFO.
Read the IN_BUF_STS1 and IN_BUF_STS0 flags and confirm that they are either “002” (the IN
FIFO empty) or “012” (writable of second data in double buffer).
2: Write one packet data (Note 1) to be transmitted to the IN FIFO.
Every time 1-byte data are written to the IN FIFO, the internal write pointer is automatically
incremented by one. Contents of the internal write pointer cannot be read. For transmitting an
empty packet (with 0 data length), do not write data to the IN FIFO.
3: Set SET_IN_BUF_RDY bit to “1”.
At this time, the IN FIFO status is updated as follows (the IN_BUF_STS1 and IN_BUF_STS0 flags
are updated) and the transmit preparation is completed:
•In Single Buffer Mode
The IN_BUF_STS1 and IN_BUF_STS0 flags are updated from “002” (the IN FIFO empty) to
“112” (the IN FIFO full).
•In Double Buffer Mode
When the first packet data (Note 1) of double buffer is written while there is a space in IN FIFO,
the IN_BUF_STS0 and IN_BUF_STS1 flags are updated from “002” to “012”, indicating that the
second packet data (Note 1) is ready to be written to the IN FIFO. In this case, second packet
data can be continuously prepared.
When there is only the first packet data (Note 1) in the IN FIFO and second packet data (Note 1)
is written, the IN_BUF_STS0 and IN_BUF_STS1 flags are updated from “012” to “112”, indicating
that no more data can be written to the IN FIFO.
The USB function control unit transmits one packet data (Note 1) in the next IN token.
Note 1: In continuous transfer enable, read the description by substituting the underlined part with
“buffer data”. As for one buffer data, when SET_IN_BUF_RDY bit is set to “1” after data less
than the value set in the BUF_SIZ are written to IN FIFO, one buffer data transmit is pre-
pared. Also, the BUF_SIZ has to be equal to an integral multiple of the EPxIMP.
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2. USB function
While the AUTO_SET is enabled (AUTO_SET bit is “1”), when one data packet whose is equal to the
maximum packet size (EPxIMP set value) has been written to IN FIFO in continuous transmit dis-
able, or, when data equal to the buffer size (byte count set in the BUF_SIZ of the EPxIFC) has been
written to IN FIFO in continuous transmit enable, the IN_BUF_STS1 and IN_BUF_STS0 flags are
updated without SET_IN_BUF_RDY bit being set to “1”. However, when a short packet (data whose
size is smaller than the EPxIMP value in continuous transfer disable or the BUF_SIZ value in con-
tinuous transfer enable) has been written, the IN_BUF_STS1 and IN_BUF_STS0 flags are not auto-
matically updated. In such cases, set the SET_IN_BUF_RDY bit to “1” by software.
Transmit Operation
On completing transmitting of one packet data (Note 2) to the host, the IN_BUF_STS0 and IN_BUF_STS1
flags are automatically updated. In single buffer mode (when double buffer mode bit is “0”), these
flags are updated from “112” to “002”. In double buffer mode, they are updated as follows:
- While there are two packet data (Note 2) in IN FIFO, the IN_BUF_STS0 and IN_BUF_STS1 flags
are updated from “112” to “012” when one of the data is transmitted, indicating that one more
transmit data is left inside the IN FIFO.
- When there is one packet data (Note 2) in IN FIFO, the IN_BUF_STS0 and IN_BUF_STS0 flags
are updated from “012” to “002” when the data are transmitted, indicating that the IN FIFO becomes
empty.
Note 2: In continuous transfer enable, read the description by substituting the underlined part with
“buffer data”. The USB function control unit transmits the transmit data in sequence by one
packet size (the maximum packet size set in the EPxIMP). (When the last one packet is
smaller than the size set in the EPxIMP, it is received as a short packet.)
When IN token is received from the host CPU while SEND_STALL bit is set to “1”, STALL response
is automatically returned.
When IN token is received from the host CPU while there are no packet data in the IN FIFO, NAK
response automatically is returned.
When IN token is received from the host CPU while there are packet data in the IN FIFO, data are
transmitted by using the current data toggle sequence bit. On completing one packet data transmit
(on receiving ACK from the host CPU), the IN FIFO status is updated (the IN_BUF_STS1 and
IN_BUF_STS0 flags are updated) and data toggle sequence bit is toggled (DATA0 → DATA1, or
DATA1 → DATA0). At this time, the endpoint x IN interrupt request occurs. When one packet data
has been unsuccessfully transmitted (ACK not received from the host CPU), the data are re-trans-
mitted in the next IN token (the same data are transmitted in the same toggle).
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2. USB function
(3) Isochronous Transfer: Endpoints 1 to 4 Transmit
Type of Transmit Transfer
When endpoints 1 to 4 IN are used for isochronous transfer, ISO bit and INTPT bit of USB endpoint
x IN control and status register are respectively set to “1” and to “0”, for isochronous transfer setting.
Transmit Data Preparation
The endpoint x IN packet data preparation procedure in the isochronous transfer is same as the bulk
transfer.
Refer to “ Transmit Data Preparation” of “(2) Bulk Transfer: Endpoints 1 to 4 Transmit” (Continuous
transfer is valid for the bulk transfer only).
Transmit Operation
A packet whose PID is DATA0 is transmitted to the IN token from the host CPU.
When IN token is received from the host CPU while there are no data in IN FIFO, an empty packet
(with 0 data length) is automatically transmitted, an underrun error occurs, and the UNDER_RUN
flag is set to “1”.
When the UNDER_RUN flag is set to “1” while the error interrupt is enabled by USB function interrupt
enable register, an error interrupt request occurs (INTST8 is set to “1”).
When IN token is received from the host CPU while there are packet data in IN FIFO, data are
transmitted. At this time, the IN FIFO status is updated and the endpoint x IN interrupt request oc-
curs. In isochronous transfer, timing in which data are transmitted to the IN token from the host CPU
differs by setting of ISO_UPDATE bit. When ISO_UPDATE bit is set to “1”, setting “1” to
SET_IN_BUF_RDY bit, which is the packet control signal, is delayed until the next SOF packet is
received so that transmission of the IN FIFO data packet is delayed. At this time, whether there are
actual packet data or not, it is replied to the IN token that there are no packet data in the IN FIFO until
the next SOF packet is detected.
Also, for flushing the IN FIFO in isochronous IN transfer by using software, the AUTO FLUSH func-
tion is used.
While ISO_UPDATE bit =“1”, AUTO_FLUSH bit =“1”, and ISO bit (INxCSR8)=“1”, the USB function
control unit, at the time of detecting a SOF packet (from the host PC or on the artificial SOF), auto-
matically flushes old data packet inside the IN FIFO if both the IN_BUF_STS1 and the
IN_BUF_STS0 flags are “1” (IN FIFO full state). In isochronous transfer for double buffer, use the
AUTO FLUSH function.
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2. USB function
(4) Interrupt Transfer: Endpoints 1 to 4 Transmit
Setting of Transfer Type
Interrupt transfer setting has two kinds including the normal interrupt transfer and the rate feedback
interrupt transfer.
When endpoints 1 to 4 IN are used for the normal interrupt transfer, ISO bit and INTPT bit of USB
endpoint x IN control and status register are respectively to “0”.
When the isochronous device has the rate feedback function and endpoints 1 to 4 IN are used for
rate feedback interrupt transfer, not only ISO bit and INTPT bit of USB endpoint x IN control and
status register are respectively set to “0” and to “1” but also double buffer mode enable bit of USB
endpoint x IN FIFO configuration register is set to “0” so that single buffer is enabled.
Also, for initialization of toggle sequence bit in interrupt transfer, set TOGGLE_INIT bit to “1” and
initialize PID to DATA0.
Transmit Data Preparation
Normal Interrupt Transfer:
The endpoint x IN packet data preparation procedure in the normal interrupt transfer is same as the
bulk transfer.
Refer to “ Transmit Data Preparation“ of “(2) Bulk Transfer: Endpoints 1 to 4 Transmit” (Continu-
ous transfer is valid for the bulk transfer only).
Rate Feedback Interrupt Transfer:
In real application, transmit data to the host CPU has to be always prepared. Prepare one transmit
data to the IN FIFO in the following procedure:
For details of the following 1 and 2, refer to the single buffer mode parts in “ Transmit Data
Preparation (2, 3)” of “(2) Bulk Transfer: Endpoints 1 to 4 Transmit” (Continuous transfer is valid for
the bulk transfer only).
1: Write one packet data to be transmitted to the IN FIFO. At the time of writing the data, pay
attention to the timing so that an IN token is not received from the host. Every time 1-byte data
are written to the IN FIFO, the internal write pointer is automatically incremented by one. Con-
tents of the internal write pointer cannot be read. For transmitting an empty packet (with 0 data
length), do not write data to the IN FIFO.
2: Set SET_IN_BUF_RDY bit to “1” after writing of the data to the IN FIFO are completed.
At this time, the IN FIFO state is updated and one packet transmit is prepared. The USB function
control unit transmits this data to the IN token until next transmit data are updated.
Transmit Operation
Normal Interrupt Transfer:
The endpoint x IN transmit operation in the normal interrupt transfer is same as the bulk transfer.
Refer to “ Transmit Operation” of “(2) Bulk Transfer: Endpoints 1 to 4 Transmit”.
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2. USB function
Rate Feedback Interrupt Transfer:
In real application, rate feedback interrupt transfer always has data to be transmitted to the host.
Therefore, the device does not repond with NAK to the IN token from the host in this transfer. On
receiving IN token from the host CPU, the IN FIFO data are always transmitted in the current data
sequence bit regardless of the IN_BUF_STS0 and IN_BUF_STS1 values. Except this point, the
transmit operation is the same as the normal interrupt transfer.
When IN token is received from the host CPU while SEND_STALL bit being set to “1”, STALL
response is automatically returned. On receiving IN token from the host CPU, the IN FIFO data are
transmitted in the current data sequence bit . On completing one data transmit (on receiving ACK
from the host CPU), the IN FIFO status is updated, data toggle sequence bit is toggled (DATA0
→DATA1 or DATA1→DATA0), and the endpoint x IN interrupt request occurs. At this time, unlike
the normal interrupt transfer, the IN FIFO data are not deleted, which is retained until the next
packet data are updated. When one data transmit has not been unsuccessfully completed (an ACK
not received from the host CPU), the data are re-transmitted in the next IN token (the same data
are transmitted in the same toggle).
(5) Precautions for Transmit
Writing to IN FIFO
Be sure to confirm that there is a space in the IN FIFO before writing data to the IN FIFO in prepara-
tion for packet data to the IN FIFO.
The IN FIFO state is indicated by the IN_BUF_STS1 and the IN_BUF_STS0 flags. Based on these
flags states, determine the count of data packets set in the IN FIFO.
The IN FIFO status (IN_BUF_STS1 and IN_BUF_STS0 flags) is updated when transmit data are
prepared in the IN FIFO (SET_IN_BUF_RDY bit is set to “1”), when transmitting of one data to the
host CPU is completed, or when data inside the IN FIFO have been flushed (AUTO_FLUSH bit or
FLUSH bit has functioned.)
Table 2.8.4. Status on Endpoint 1 to 4 IN FIFOs
Double buffer [IN FIFO size =
(The number of bytes specified
by the BUF_SIZ*1) 2]
No data
Single buffer
[Specify IN FIFO size by the
BUF_SIZ*1]
IN_BUF_STS0
0
IN_BUF_STS1
0
No data
Space equal to two buffer
Invalid
Space equal to one buffer
Invalid
1
0
0
1
One data set in the IN FIFO
Space equal to one buffer
Two data set in the IN FIFO
No space in the IN FIFO
Invalid
1
1
One data set in the IN FIFO
No space in the IN FIFO
*1: Bits 6 to 9 of EPxIFC.
PID Initialization
When TOGGLE_INIT bit is set to “1”, the read/write counter inside the FIFO is initialized. To initialize
the PID, set TOGGLE_INIT bit to “1” in the IN FIFO is empty state (the IN_BUF_STS0 and
IN_BUF_STS1 flags are “002”).
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2. USB function
(6) USB Transmit (Endpoints 1 to 4 IN): Example
The endpoints 1 to 4 IN transmit packet prepare routine (continuous transfer disable) is shown in
Figure 2.8.49. In addition to packet prepare process, error process by the UNDER_RUN flag is re-
quired in isochronous transfer.
Process of USB endpoint x IN packet prepare
1. Confirming of whether there is a space which is equal to one packet in the IN FIFO:
check the IN_BUF_STS0 and the IN_BUF_STS1.
(b15)
b7
(b8)
b0 b7
b0
USB endpoint x IN control and status register
EPxICS (x = 1 - 4) [Address 029E16, 02A416, 02AA16, 02B016
0
0
0
0
0
]
IN_BUF_STS0 flag
IN_BUF_STS1 flag
b1 b0
0 0 : No data set in the IN buffer
0 1 : Single buffer mode: N/A
Double buffer mode: one data set in the IN buffer
1 0 : N/A
1 1 : Single buffer mode: one data set in the IN buffer
Double buffer mode: two data set in the IN buffer
IN FIFO full
There is a space in the IN FIFO.
2. Writing of the transmit data equal to one packet data (Note 1) to the IN FIFO.
(b15)
b7
(b8)
b0 b7
b0
USB endpoint x IN FIFO data register
EPxI (x = 0 - 4) [Address 02E016, 02E416, 02E816, 02EC16, 02F016
]
Setting of the transmit data
Note 1: The packet data is one buffer data in continuous transfer mode.
3. Setting of the SET_IN_BUF_RDY bit to “1” and completion of one packet data (Note 2) prepare.
(b15)
(b8)
b7
b0 b7
b0
USB endpoint x IN control and status register
EPxICS (x = 1 - 4) [Address 029E16, 02A416, 02AA16, 02B016
SET_IN_BUF_RDY bit
0
0
0
0
0
0
]
1 : Transmission data set loaded to the IN buffer
(updates IN_BUF_STS0, IN_BUF_STS1 flags)
Note 2: The packet data is one buffer data in continuous transfer mode.
Note 3: When the AUTO_SET bit is set to “1”, this bit is automatically set to “1” when the data count set by
maximum packet size register is written to the IN FIFO. When the AUTO_SET bit is set to “0” or the
AUTO_SET bit is set to “1” and it is a short packet (data packet which is smaller than maximum packet size),
this bit is set to “1” by software.
Execution of the above 2 and 3 again when the second
packet data is set on the double buffer mode.
Completion of packet data prepare
Figure 2.8.49. Endpoint 1 to 4 IN packet prepare routine
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2. USB function
2.8.8 USB Operation (Interface with DMAC Transfer)
The M30245 group can select a USB (USB0/USB1/USB2/USB3) as the DMA request factor. The USB0
corresponds to DMA0, USB1 to DMA1, USB2 to DMA2, and USB3 to DMA3. The DMA request factor
origin of USB0/USB1/USB2/USB3 is also set by setting any one of endpoints 1 to 4 IN/OUT factors to
USB DMAx(x=0 to 3) request register .
The DMA request factor of USB0/USB1/USB2/USB3 occurs, under particular conditions, not only on
occurrence of an interrupt request of each endpoint but also on write/read to/from IN/OUT FIFO.
(1) Related Registers
USB DMAx(x=0 to 3) request register
This register sets the DMA request factor origin of USB0/USB1/USB2/USB3. When, under particular
conditions, write/read to/from the FIFO of the endpoint selected by this register or an event such as
the endpoint's interrupt request occurs, a DMA request occurs. This register can be set “1” only to 1
bit. When multiple bits are simultaneously set to “1”, the setting becomes invalid. Other DMA related
registers also need to be set before a valid value is set; for example, “000112” (USB0/USB1/USB2/
USB3) is set to DMA request cause select bits (b4,b3,b2,b1,b0) of DMAx(x=0 to 3) request cause
select register (addresses 03B816, 03BA16, 03B016, 03B216).
The configuration of USB DMAx(x=0 to 3) request register is shown in Figure 2.8.50.
USB DMAx Request registers
(b8)
b0
(b15)
b7
b7
b0
Address
029016, 029216
029416, 029616
When reset
000016
Symbol
USBDMAx (x=0 to 3)
0
0
0
0
0
0
0
0
,
Bit Symbol
Function
Bit Name
R
O
W
O
Must always be set to “0”
Reserved
DMAxR1
DMAxR2
DMAxR3
DMAxR4
O
O
EP1 IN FIFO write request select bit
EP2 IN FIFO write request select bit
EP3 IN FIFO write request select bit
EP4 IN FIFO write request select bit
1 : Selected
0 : Not selected
Must always be set to “0”
O
O
O
O
Reserved
DMAxR6
EP1 OUT FIFO read request select bit
EP2 OUT FIFO read request select bit
EP3 OUT FIFO read request select bit
EP4 OUT FIFO read request select bit
1 : Selected
0 : Not selected
DMAxR7
DMAxR8
DMAxR9
Reserved
Must always be set to “0”
O
O
Figure 2.8.50. USB DMAx(x=0 to 3) request register
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2. USB function
(2) DMA Request by Endpoint x OUT
DMA Request Factors
When endpoint 1 to 4 OUT FIFO write request select bit is set to the DMA request factor origin of
USB0/USB1/USB2/USB3, the DMA request factor includes the following three kinds. On occurrence
of an event when all the specified conditions have been satisfied for each factor, the DMA request of
DMA0/DMA1/DMA2/DMA3 occurs.
•Factor 1
Conditions:
- DMA enable bit of DMAi control register is set to “1” (enable).
- Any one of endpoint x(x=1 to 4) OUT FIFO read request select bit in USB DMAx(x=0 to 3)
request register is set to “1”. The other bits are set to “0” (valid setting).
Event:
The OUT FIFO state of the endpoint x OUT which is set in USB DMAx(x=0 to 3) request register
has been updated, and the OUT_BUF_STS1 and OUT_BUF_STS0 flags are set to “112” at the
time of single buffer and “102” at the time of double buffer. (When data of one or more buffers are
received in OUT FIFO. At this time, when one packet receive is completed, the endpoint x OUT
interrupt request simultaneously occurs.)
•Factor 2
Conditions:
- DMA enable bit of DMAi control register is set to “1” (enable).
- The OUT_BUF_STS1 and OUT_BUF_STS0 flags of endpoint x OUT which is set in USB
DMAx(x=0 to 3) request register are set to “102” or “112”. (When data of one or more packets are
received in OUT FIFO.)
- There is no selection of USB DMAx(x=0 to 3) request register (“0016”).
Event:
Any one of endpoint x(x=1 to 4) OUT FIFO read request select bit in USB DMAx(x=0 to 3)
request register is set to “1”. The other bits are set to “0” (valid setting).
•Factor 3
Conditions:
- DMAenable bit of DMAi control register is set to “1” (enable).
- The OUT_BUF_STS1 and OUT_BUF_STS0 flags of endpoint x OUT which is set in USB
DMAx(x=0 to 3) request register are set to “102” or “112”. (When data of one or more packets are
received in OUT FIFO.)
- Any one of endpoint x(x=1 to 4) OUT FIFO read request select bit in USB DMAx(x=0 to 3)
request register is set to “1”. The other bits are set to “0” (valid setting).
Event:
1-byte (1-word) data is read from the endpoint x OUT FIFO which is set in USB DMAx(x=0 to 3)
request register .
Reading of Endpoint x OUT FIFO in DMA Transfer
The DMA request factor of USB0/USB1/USB2/USB3 corresponds to read from the endpoints 1 to 4
OUT FIFO (Factor 3). Therefore, with endpoint x OUT FIFO being specified to the DMA source pointer
and the transfer source address direction being fixed, when DMA transfer is executed by Factor 1
(Factor 2 or Factor 3), Factor 3 occurs. Therefore, when one buffer data (one packet data) is read from
OUT FIFO by DMA transfer, it is possible that the 1st byte (1st word) data is DMA transferred by
Factor 1 (Factor 2 or Factor 3) and the other data, starting from the 2nd byte (2nd word) up to the last
byte (last word), are DMA transferred by Factor 3.
For details of DMA transfer, refer to “Chapter 2. DMAC”.
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2. USB function
(3) DMA Request by Endpoint x IN
DMA Request Factor
When endpoint x(x=1 to 4) IN FIFO write request select bit is set to the DMA request factor origin of
USB0/USB1/USB2/USB3, the DMA request factor includes the following three kinds. On occurrence
of an event when all the specified conditions have been satisfied for each factor, the DMA request of
DMA0/DMA1/DMA2/DMA3 occurs.
•Factor 1
Conditions:
- DMA enable bit of DMAi control register is set to “1” (enable).
- Any oneendpoint x(x=1 to 4) IN FIFO write request select bit in USB DMAx(x=0 to 3) request
register is set to “1”. The other bits are set to “0” (valid setting).
Event:
The IN FIFO state of the endpoint x IN which is set in USB DMAx(x=0 to 3) request register has
been updated, and the IN_BUF_STS1 and IN_BUF_STS0 flags are set to “002” at the time of
single buffer and “012” at the time of double buffer. (When there are the space of one or more
packets in the IN FIFO. At this time, when one packet transfer is completed, the endpoint x IN
interrupt request simultaneously occurs.)
•Factor 2
Conditions:
- DMA enable bit of DMAi control register is set to “1” (enable).
- The IN_BUF_STS1 and IN_BUF_STS0 flags of endpoint x IN which is set in USB DMAx(x=0 to
3) request register are set to “002” or “012”. (When there are the space of one or more packets in
the IN FIFO.)
- There is no selection of USB DMAx(x=0 to 3) request register (“0016”).
Event:
Any one endpoint x(x=1 to 4) IN FIFO write request select bit in USB DMAx(x=0 to 3) request
register is set to “1”. The other bits are set to “0” (valid setting).
•Factor 3
Conditions:
- DMA enable bit of DMAi control register is set to “1” (enable).
- The IN_BUF_STS1 and IN_BUF_STS0 flags of endpoint x IN which is set in USB DMAx(x=0 to
3) request register are set to “002” or “012”. (When there are the space of one or more packets in
the IN FIFO.)
- Any one of endpoint x(x=1 to 4) IN FIFO write request select bit in USB DMAx(x=0 to 3) request
register is set to “1”. The other bits are set to “0” (valid setting).
Event:
1-byte (1-word) data is written in the endpoint x IN FIFO which is set in USB DMAx(x=0 to 3)
request register .
DMA Transfer to Endpoint x IN FIFO
The DMA request factor of USB0/USB1/USB2/USB3 corresponds to write in the endpoints 1~4 IN
FIFO (Factor 3). Therefore, with endpoint x IN FIFO being specified to the DMA destination pointer
and the transfer destination address direction being fixed, when DMA transfer is executed by Factor
1 (Factor 2 or Factor 3), Factor 3 occurs. Therefore, when one buffer data is written in IN FIFO by
DMA transfer, it is possible that the 1st byte (1st word) data is DMA transferred by Factor 1 (Factor 2
or Factor 3) and the other data, starting from the 2nd byte (2nd word) up to the last byte (last word),
are DMA transferred by Factor 3.
For details of DMA transfer, refer to “Chapter 2.10 DMAC”.
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2. USB function
2.8.9 Precautions for USB
(1) USB Communication
"In applications requiring high-reliability, we recommend providing the system with protective mea-
sures such as USB function initialization by software or USB reset by the host to prevent USB com-
munication from being terminated unexpectedly, for example due to external causes such as noise."
(2) Peripheral Circuit
The peripheral circuit block diagram is shown in Figure 2.8.51, the passive part of LPF pin is shown in
Figure 2.8.52 and the connection diagram of decoupling capacitor is shown in Figure 2.8.53.
•USB2.0 specification specifies the driver impedance 28~44Ω (See 7.1.1.1 “Full-speed (12Mb/s)
Driver Characteristics”). Connect a serial resistor (recommended value: 27~33Ω) to the USB D+ pin
and the USB D- pin to satisfy this specification. Also connect, if required, the capacitors between the
USB D+ pin/USB D- pin and the Vss pin. These capacitors control ringing or adjust the times of
rising/falling and the crossover point of D+/D-. As the numerical values and the configuration of the
peripheral components need to be adjusted according to differences in characteristic impedance and
layout of the mount printed circuit board. Therefore, fully evaluate on the system in use and observe
waveforms before adjusting the connection or disconnection and the values of the resistance and the
capacitor.
•When the USB Attach/Detach function is not used, connect the UVcc pin and the USB D+ pin via a
1.5kΩ resistance (D+ line pull-up timing depends on the UVCC pin).
When the USB Attach/Detach function is used, connect the P90/ATTACH pin and the USB D+ pin via
a 1.5kΩ resistance. Irrespective of use of the USB Attach/Detach function, connect the UVCC pin to
the power supply. In addition, the time required for the host PC to recognize the USB Attach/Detach
varies depending on the whole system state such as substrate resistance components, capacitance
components, USB cable capacitance, and substrate characteristics and processing speed of the
host. Fully evaluate on the system subject to actual use.
•Connect all the passive parts of the LPF pin as close to the LPF pin as possible.
•Connect an insulating connector (ferrite beads) between the AVss pin and the digital Vss, between
the AVcc pin and the digital Vcc. Also at this time, when an A/D converter is used, connect the Vref
pin to the AVcc pin.
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2. USB function
UVCC
USBC5
lock enable
Frequency synthesizer
XIN
enable
P90 control
enable
ATTACH
FSE
LS
Connect to ATTACH
or UVCC
USB Clock
(48MHz)
PORT90_ ATTACH/
SECOND
DETACH
USB
Transceiver
USB FCU
D+
D-
enable
USBC7
enable
USBC7
: The value of resistance and capacitor, and the configuration will
depened on the layout of printed circuit board.
Figure 2.8.51. Peripheral circuit block diagram
Ferrite Beads
AVcc
(80pin)
LPF pin
Vcc
Vss
680pF (10%)
C
C
0.1µF (10%)
AVss
AVSS pin
(77pin)
Decoupling
Capacitors
Figure 2.8.53. Decoupling capacitor
Figure 2.8.52. Passive part of LPF pin
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2. USB function
(3) Register, Bit
•When the USB reset interrupt request occurs, all the USB internal registers become reset state. To
resume communication, each endpoint needs to be initialized.
•All the USB related registers (16-bit registers) except USB endpoint x(x=0 to 4) IN FIFO data register
(EPxI), USB endpoint x(x=0 to 4) OUT FIFO data register (EPxO), USB control register (USBC), and
USB attach/detach register (USBAD) are available for word access and byte access. The EPxI and
the EpxO are only available for word access or byte access to the lower bytes. The USBC and the
USBAD of 8-bit registers are only available for byte access. After software reset, contents of all the
USB related registers are retained.
•While the USB clock is held disabled in suspend mode, writing in the USB internal registers (other
than USBC, USBAD, and frequency synthesizer-related registers) is disabled.
(4) Packet Data Destruction
•When FLUSH bit of endpoint x OUT control and status register (EPxOCS) is set to “1” during USB
transfer, the receive data may be destroyed. Be sure to set FLUSH bit of the EPxOCS to “1” only
when there are data in OUT FIFO (OUT_BUF_STS1 and OUT_BUF_STS0 are set to “102” or “112”).
•When FLUSH bit of USB endpoint x IN control and status register (EPxICS) is set to “1” during USB
transfer, the transmit data may be destroyed. Be sure to read the IN_BUF_STS1 and the
IN_BUF_STS0 flags and to confirm that there are data in IN FIFO before setting FLUSH bit of the
EPxICS to “1”.
In isochronous transfer, use AUTO_FLUSH bit (bit 0 of address 028C16).
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M30245 Group
2. A/D Converter
2.9 A/D Converter
2.9.1 Overview
The A/D converter used in the M30245 group operates on a successive conversion basis. The following
is an overview of the A/D converter.
(1) Mode
The A/D converter operates in one of five modes:
(a) One-shot mode
Carries out A/D conversion on input level of one specified pin only once.
(b) Repetition mode
Repeatedly carries out A/D conversion on input level of one specified pin.
(c) One-shot sweep mode
Carries out A/D conversion on input level of two or more specified pins only once.
(d) Repeated sweep mode 0
Repeatedly carries out A/D conversion on input level of two or more specified pins.
(e) Repeated sweep mode 1
Repeatedly carries out A/D conversion on input level of two or more specified pins. This mode is
different from the repeated sweep mode 0 in that weights can be assigned to specifing pins control
the number of conversion times.
(2) Operation clock
The operation clock can be selected from the following: fAD, divide-by-2 fAD, divide-by-3 fAD, and
divide-by-4 fAD. The fAD frequency is equal to that of the CPU’s main clock (fAD=f(XIN)). Set the opera-
tion clock to 10 MHz or lower. When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz
by dividing.
(3) Conversion time
Number of conversion for A/D convertor varies depending on resolution as given. Table 2.9.1 shows
relation between the A/D converter operation clock and conversion time.
Sample & Hold function selected:
33 φAD cycles for 10-bit resolution, or 28 φAD cycles for 8-bit resolution
No Sample & Hold function:
59 φAD cycles for 10-bit resolution, or 49 φAD cycles for 8-bit resolution
Table 2.9.1. Conversion time every operation clock
0
0
1
1
1
0
0
1
Frequency select bit 1
Frequency select bit 0
A/D converter's
operation clock
φAD = fAD/4
φAD = fAD
φAD = fAD/3
φAD = fAD/2
28 ꢀ φAD
33 ꢀ φAD
8-bit mode
10-bit mode
8-bit mode
10-bit mode
Min. conversion
cycles (Note 1)
Min. conversion
time (Note 2)
8.4µs
9.9µs
11.2µs
13.2µs
5.6µs
6.6µs
2.8µs
3.3µs
Note 1: The number of conversion cycles per one analog input pin.
Note 2: The conversion time per one analog input pin (when fAD = f(XIN) = 10 MHz)
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2. A/D Converter
(4) Functions selection
(a) Sample & Hold function
Sample & Hold function samples input voltage when A/D conversion starts and carries out A/D con-
version on the voltage sampled. When A/D conversion starts, input voltage is sampled for 3 cycles of
the operation clock. When the Sample & Hold function is selected, set the operation clock for A/D
conversion to 1 MHz or higher.
(b) 8-bit A/D to 10-bit A/D switching function
Either 8-bit resolution or 10-bit resolution can be selected. When 8-bit resolution is selected, the 8
higher-order bits of the 10-bit A/D are subjected to A/D conversion. The equations for 10-bit resolu-
tion and 8-bit resolution are given below:
10
10
10-bit resolution (Vref X n / 2 ) – (Vref X 0.5 / 2
)
(n = 1 to 1023), 0 (n = 0)
8
10
8-bit resolution (Vref X n / 2 ) – (Vref X 0.5 / 2
)
(n = 1 to 255), 0 (n = 0)
(c) A/D conversion by external trigger
The user can select software or an external pin input to start A/D conversion.
(d) Connecting or cutting Vref
Cutting Vref allows decrease of the current flowing into the A/D converter. To decrease the
microcomputer's power consumption, cut Vref. To carry out A/D conversion, start A/D conversion 1
µs or longer after connecting Vref.
(5) Input to A/D converter and the relation of direction register
To use the A/D converter, set the direction register of the relevant port to input.
(6) Pins related to A/D converter
(a) AN0 pin through AN7 pin
(b) AVcc pin
Input pins of the A/D converter
Power source pin of the analog section
Input pin of reference voltage
(c) VREF pin
(d) AVss pin
GND pin of the analog section
___________
(e) ADTRG pin
Trigger input pin of the A/D converter
(7) A/D converter related registers
Figure 2.9.1 shows the memory map of A/D converter-related registers, and Figures 2.9.2 and 2.9.3
show A/D converter-related registers.
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M30245 Group
2. A/D Converter
004B16
AD conversion interrupt control register (ADIC)
03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
AD register 0 (AD0)
AD register 1 (AD1)
AD register 2 (AD2)
AD register 3 (AD3)
AD register 4 (AD4)
AD register 5 (AD5)
AD register 6 (AD6)
AD register 7 (AD7)
03D416
03D516
03D616
03D716
03D816
AD control register 2 (ADCON2)
AD control register 0 (ADCON0)
AD control register 1 (ADCON1)
Figure 2.9.1. Memory map of A/D converter-related registers
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2. A/D Converter
AD control register 0 (Note 1)
b6
b7
b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
When reset
0016
Bit Name
Function
Bit Symbol
R
O
W
O
b2 b1 b0
CH0
CH1
0 0 0 : AN0
0 0 1 : AN1
0 1 0 : AN2
0 1 1 : AN3
1 0 0 : AN4
1 0 1 : AN5
1 1 0 : AN6
1 1 1 : AN7
b4 b3
O
O
O
O
Analog input pin select bit
CH2
(Note 2, 3)
(Note 2)
MD0
MD1
TRG
ADST
CKS0
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0
Repeat sweep mode 1
O
O
O
O
A/D operation mode
select bit 0
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
O
O
O
O
O
O
A/D conversion start flag
0 : A/D conversion disabled
1 : A/D conversion enabled
(Note 4)
Frequency select bit 0
(Note 5)
0 : fAD/3 or fAD/4 is selected
1 : fAD or fAD/2 is selected
Note 1: If the AD control regsiter 0 is rewritten during A/D conversion, the conversion result is indeterminate.
Note 2: When changing A/D operation mode, reset the analog input pin.
Note 3: This bit is disabled in single-sweep mode, repeat-sweep mode 0 and repeat-sweep mode 1.
Note 4: Set to “1” when ADTRG is selected.
Note 5: When f(XIN) exceeds 10 MHz, the φ AD frequency must be less than 10 MHz by dividing.
AD control register 1 (Note 1)
b6
b7
b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
0 0
Bit Name
Function
Bit Symbol
R
O
O
O
O
W
O
O
O
O
b1 b0
SCAN0
SCAN1
MD2
0 0 : AN0, AN1 (AN0)
A/D sweep pin select bit
0 1 : AN0 to AN3 (AN0, AN1)
1 0 : AN0 to AN5 (AN0 to AN2)
1 1 : AN0 to AN7 (AN0 to AN3)
(Note 2)
0 : Any mode other than repeat-sweep mode 1
1 : Repeat-sweep mode 1
A/D operation mode select bit 1
8/10-bit mode select bit
Frequency select bit 1(Note 3)
Vref connect bit
0 : 8-bit mode
1 : 10-bit mode
BITS
0 : fAD/2 or fAD/4 is selected
1 : fAD/1 or fAD/3 is selected
CKS1
O
O
O
O
0 : Vref not connected
1 : Vref connected
VCUT
Reserved
Must always be set to “0”
Note 1: If the AD control regsiter 1 is rewritten during A/D conversion, the conversion result is indeterminate.
Note 2: This bit is invalid in one-shot mode and repeat mode. Channels shown in parentheses are valid
when repeat-sweep mode 1 (bit 2 = “1”) is selected.
Note 3: When f(XIN) exceeds 10 MHz, the φ AD frequency must be less than 10 MHz by dividing.
Figure 2.9.2. AD converter-related registers (1)
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2. A/D Converter
AD control register 2 (Note)
b6
b7
b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
When reset
X00X0XX0
0 0
0
2
Bit Name
Function
Bit Symbol
R
W
0 : Without sample and hold
1 : With sample and hold
A/D conversion method
select bit
SMP
O
_
O
_
Nothing is assigned.
Write “0” when writing to these bits. The values are indeterminate when read.
Must always be set to "0"
Reserved
O
_
O
_
Nothing is assigned.
Write “0” when writing to this bit. The value is indeterminate when read.
Must always be set to "0"
Reserved
O
_
O
_
Nothing is assigned.
Write “0” when writing to this bit. The values are indeterminate when read.
Note: If the AD control regsiter 2 is rewritten during A/D conversion, the conversion result is indeterminate.
AD register i (i = 0 to 7)
Address
ADi (i = 0 to 2) 03C016 to 3C116, 03C216 to 3C316, 03C416 to 3C516
ADi (i = 3 to 5) 03C616 to 3C716, 03C816 to 3C916, 03CA16 to 3CB16 Indeterminate
Symbol
When reset
Indeterminate
(b8)
b0
(b15)
b7
b7
b0
ADi (i = 6 to 7) 03CC16 to 3CD16, 03CE16 to 3CF16
Indeterminate
Function
R
O
W
Eight low-order bits of A/D conversion results
During 10-bit mode:
During 8-bit mode:
Two high-order bits of A/D conversion results
The values are indeterminate when read
O
_
Nothing is assigned.
Write “0” when writing to these bits. The values are indeterminate when read.
_
Figure 2.9.3. A/D converter-related registers (2)
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2. A/D Converter
2.9.2 Operation of A/D converter (one-shot mode)
In one-shot mode, choose functions from those listed in Table 2.9.2. Operations of the circled items are
described below. Figure 2.9.4 shows the operation timing, and Figure 2.9.5 shows the set-up procedure.
Table 2.9.2. Choosed functions
Item
Set-up
Operation clock
φAD
Divided-by-4 fAD / divided-
by-3 fAD / divided-by-2 fAD / fAD
O
Resolution
O
O
8-bit / 10-bit
Analog input pin
One of AN0 pin to AN7 pin
Trigger for starting
A/D conversion
O
Software trigger
Trigger by ADTRG
Sample & Hold
Not activated
Activated
O
Operation
(1) Setting the A/D conversion start flag to “1” causes the A/D converter to begin operating.
(2) After A/D conversion is completed, the content of the successive comparison register (con-
version result) is transmitted to AD register i. At this time, the A/D conversion interrupt re-
quest bit goes to “1”. Also, the A/D conversion start flag goes to “0”, and the A/D converter
stops operating.
(1) Start A/D conversion
8-bit resolution : 28 φAD cycles
(2) A/D conversion is complete
10-bit resolution : 33 φAD cycles
φAD
Set to “1” by software
“1”
“0”
A/D conversion
start flag
AD register i
Result
“1”
“0”
A/D conversion
interrupt request
Cleared to “0” when interrupt request is accepted, or cleared by software
When φAD frequency is less than 1MH
Z
, sample and hold function cannot be selected.
Note:
Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution.
Figure 2.9.4. Operation timing of one-shot mode
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2. A/D Converter
Selecting Sample and hold
b7
b0
AD control register 2 [Address 03D416
ADCON2
]
0
0
0
1
A/D conversion method select bit
1 : With sample and hold
Must always be set to “0”
Setting AD control register 0 and AD control register 1
b7
b0
b7
0
b0
AD control register 1 [Address 03D716
ADCON1
]
AD control register 0 [Address 03D616
ADCON0
]
0
0
0
0
0
1
0
Analog input pin select bit (Note 1)
b2 b1 b0
Invalid in one-shot mode
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
0
1
2
3
4
5
6
7
is selected
is selected
is selected
is selected
is selected
is selected
is selected
is selected
A/D operation mode select bit 1 (Note 1)
0 (Must always be “0” in one-shot mode)
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
Frequency select bit 1 (Note 2)
0 : fAD/2 or fAD/4 is selected
1 : fAD or fAD/3 is selected
One-shot mode is selected (Note 1)
Trigger select bit
0 : Software trigger
Vref connect bit
1 : Vref connected
A/D conversion start flag
0 : A/D conversion disabled
Reserved bit
Frequency select bit 0 (Note 2)
0 : fAD/3 or fAD/4 is selected
1 : fAD or fAD/2 is selected
Note 1 : Rewrite to analog input pin select bit after changing A/D operation mode.
Note 2 : When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing and set øAD frequency to 10 MHz or lower.
Setting A/D conversion start flag
b7
b0
AD control register 0 [Address 03D616
]
ADCON0
1
A/D conversion start flag
1 : A/D conversion started
Start A/D conversion
Stop A/D conversion
AD register 0
AD register 1
AD register 2
AD register 3
AD register 4
AD register 5
AD register 6
AD register 7
[Address 03C116, 03C016
]
]
]
]
]
AD0
AD1
AD2
AD3
AD4
AD5
Reading conversion result
[Address 03C316, 03C216
[Address 03C516, 03C416
[Address 03C716, 03C616
[Address 03C916, 03C816
[Address 03CB16, 03CA16
[Address 03CD16, 03CC16] AD6
[Address 03CF16, 03CE16 AD7
(b15)
b7
(b8)
b0 b7
b0
]
]
Eight low-order bits of A/D conversion result
During 10-bit mode
Two high-order bits of A/D conversion result
During 8-bit mode
When read, the content is indeterminate
Figure 2.9.5. Set-up procedure of one-shot mode
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2. A/D Converter
2.9.3 Operation of A/D Converter (in one-shot mode, an external trigger selected)
In one-shot mode, choose functions from those listed in Table 2.9.3. Operations of the circled items are
described below. Figure 2.9.6 shows timing chart, and Figure 2.9.7 shows the set-up procedure.
Table 2.9.3. Choosed functions
Item
Set-up
Operation clock
φAD
Divided-by-4 fAD / divided-
by-3 fAD / divided-by-2 fAD / fAD
O
Resolution
O
O
8-bit / 10-bit
Analog input pin
One of AN0 pin to AN7 pin
Trigger for starting
A/D conversion
Software trigger
Trigger by ADTRG
O
O
Sample & Hold
Not activated
Activated
___________
Operation (1) If the level of the ADTRG changes from “H” to “L” with the A/D conversion start flag set to “1”,
the A/D converter begins operating.
(2) After A/D conversion is completed, the content of the successive comparison register (con-
version result) is transmitted to AD register i. At this time, the A/D conversion interrupt re-
quest bit goes to “1”. Also the A/D converter stops operating.
___________
(3) If the level of the ADTRG pin changes from “H” to “L”, the A/D converter carries out conversion
___________
from step (1) again. If the level of the ADTRG pin changes from “H” to “L” while conversion is
in progress, the A/D converter stops the A/D conversion in process, and carries out conver-
sion from step (1) again.
(1) Start A/D conversion
(2) A/D conversion is
complete
(3) Start A/D
conversion
8-bit resolution : 28 φAD cycles
10-bit resolution : 33 φAD cycles
φAD
Set to “1” by software
A/D
conversion
start flag
“1”
“0”
“H”
“L”
ADTRG
AD register i
Result
“1”
“0”
A/D conversion
interrupt request
Cleared to “0” when interrupt request is accepted, or cleared by software
When φAD frequency is less than 1MH
Z
, sample and hold function cannot be selected.
Note:
Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution.
Figure 2.9.6. Operation timing of one-shot mode, with an external trigger selected
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2. A/D Converter
Selecting Sample and hold
b7
b0
AD control register 2 [Address 03D416
ADCON2
]
0
0
0
1
A/D conversion method select bit
1 : With sample and hold
Must always be set to “0”
Setting AD control register 0 and AD control register 1
b7
b0
b7
0
b0
AD control register 1 [Address 03D716
ADCON1
]
AD control register 0 [Address 03D616
ADCON0
]
0
1
0
0
1
0 0
Analog input pin select bit (Note 1)
b2 b1 b0
Invalid in one-shot mode
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
0
1
2
3
4
5
6
7
is selected
is selected
is selected
is selected
is selected
is selected
is selected
is selected
A/D operation mode select bit 1 (Note 1)
0 (Must always be “0” in one-shot mode)
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
Frequency select bit 1 (Note 2)
0 : fAD/2 or fAD/4 is selected
1 : fAD or fAD/3 is selected
One-shot mode is selected (Note 1)
Trigger select bit
1 : ADTRG trigger
Vref connect bit
1 : Vref connected
A/D conversion start flag
0 : A/D conversion disabled
Reserved bit
Frequency select bit 0 (Note 2)
0 : fAD/3 or fAD/4 is selected
1 : fAD or fAD/2 is selected
Note 1 : Rewrite to analog input pin select bit after changing A/D operation mode.
Note 2 : When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing and set øAD frequency to 10 MHz or lower.
Setting A/D conversion start flag
b7
b0
AD control register 0 [Address 03D616
ADCON0
]
1
A/D conversion start flag
1 : A/D conversion started
When ADTRG pin level becomes from “H” to “L”
Start A/D conversion
AD register 0
AD register 1
AD register 2
AD register 3
AD register 4
AD register 5
AD register 6
AD register 7
[Address 03C116, 03C016
[Address 03C316, 03C216
[Address 03C516, 03C416
[Address 03C716, 03C616
[Address 03C916, 03C816
[Address 03CB16, 03CA16
[Address 03CD16, 03CC16
[Address 03CF16, 03CE16
]
]
]
]
]
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Reading conversion result
(b15)
b7
(b8)
b0 b7
b0
]
]
]
Eight low-order bits of A/D conversion result
During 10-bit mode
Two high-order bits of A/D conversion result
During 8-bit mode
When read, the content is indeterminate
Setting A/D conversion start flag
b7
b0
AD control register 0 [Address 03D616
ADCON0
]
0
A/D conversion start flag
0 : A/D conversion disabled
Stop A/D conversion
Figure 2.9.7. Set-up procedure of one-shot mode, with an external trigger selected
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2.9.4 Operation of A/D Converter (in repeat mode)
In repeat mode, choose functions from those listed in Table 2.9.4. Operations of the circled items are
described below. Figure 2.9.8 shows timing chart, and Figure 2.9.9 shows the set-up procedure.
Table 2.9.4. Choosed functions
Item
Set-up
Operation clock
φAD
Divided-by-4 fAD / divided-
by-3 fAD / divided-by-2 fAD / fAD
O
Resolution
O
O
8-bit / 10-bit
Analog input pin
One of AN0 pin to AN7 pin
Trigger for starting
A/D conversion
O
Software trigger
Trigger by ADTRG
Sample & Hold
Not activated
Activated
O
(1) Setting the A/D conversion start flag to “1” causes the A/D converter to start operating.
(2) After the first conversion is completed, the content of the successive comparison register
(conversion result) is transmitted to AD register i. The A/D conversion interrupt request bit
does not go to “1”.
Operation
(3) The A/D converter continues operating until the A/D conversion start flag is set to “0” by
software. The conversion result is transmitted to AD register i every time a conversion is
completed.
(1) Start A/D conversion
(2) Conversion result is transferred to the AD register
(3) A/D conversion
is complete
8-bit resolution : 28 φAD cycles
10-bit resolution : 33 φAD cycles
8-bit resolution : 28 φAD cycles
10-bit resolution : 33 φAD cycles
φAD
Set to “1” by software
Cleared to “0” by software
“1”
“0”
A/D conversion
start flag
AD register i
Result
Result
A/D conversion
Convert
Stop
Convert
Convert
Stop
Note:
When φAD frequency is less than 1MHz, sample and hold function cannot be selected.
Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles
for 10-bit resolution.
Figure 2.9.8. Operation timing of repeat mode
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Selecting Sample and hold
b7
b0
AD control register 2 [Address 03D416
ADCON2
]
0
0
0
1
A/D conversion method select bit
1 : With sample and hold
Must always be set to “0”
Setting AD control register 0 and AD control register 1
b7
b0
b7
0
b0
AD control register 1 [Address 03D716
ADCON1
]
AD control register 0 [Address 03D616
ADCON0
]
0
0
0 1
0
1
0
Analog input pin select bit (Note 1)
b2 b1 b0
Invalid in Repeat mode
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
0
1
2
3
4
5
6
7
is selected
is selected
is selected
is selected
is selected
is selected
is selected
is selected
A/D operation mode select bit 1 (Note 1)
0 (Must always be “0” in repeat mode)
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
Frequency select bit 1 (Note 2)
0 : fAD/2 or fAD/4 is selected
1 : fAD or fAD/3 is selected
Repeat mode is selected (Note 1)
Trigger select bit
0 : Software trigger
Vref connect bit
1 : Vref connected
A/D conversion start flag
0 : A/D conversion disabled
Reserved bit
Frequency select bit 0 (Note 2)
0 : fAD/3 or fAD/4 is selected
1 : fAD or fAD/2 is selected
Note 1 : Rewrite to analog input pin select bit after changing A/D operation mode.
Note 2 : When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing and set øAD frequency to 10 MHz or lower.
Setting A/D conversion start flag
b7
b0
AD control register 0 [Address 03D616
ADCON0
]
1
A/D conversion start flag
1 : A/D conversion started
Repeatedly carries out A/D conversion on pins
selected through the A/D input pin select bit.
Start A/D conversion
Transmitting conversion result to AD register i
AD register 0
AD register 1
AD register 2
AD register 3
AD register 4
AD register 5
AD register 6
AD register 7
[Address 03C116, 03C016
[Address 03C316, 03C216
[Address 03C516, 03C416
[Address 03C716, 03C616
[Address 03C916, 03C816
[Address 03CB16, 03CA16
[Address 03CD16, 03CC16
[Address 03CF16, 03CE16
]
]
]
]
]
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
(b15)
b7
(b8)
b0 b7
b0
]
]
]
Eight low-order bits of A/D conversion result
During 10-bit mode
Two high-order bits of A/D conversion result
During 8-bit mode
When read, the content is indeterminate
Setting A/D conversion start flag
b7
b0
AD control register 0 [Address 03D616
ADCON0
]
0
A/D conversion start flag
0 : A/D conversion disabled
Stop A/D conversion
Figure 2.9.9. Set-up procedure of repeat mode
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2.9.5 Operation of A/D Converter (in single sweep mode)
In single sweep mode, choose functions from those listed in Table 2.9.5. Operations of the circled items
are described below. Figure 2.9.10 shows timing chart, and Figure 2.9.11 shows the set-up procedure.
Table 2.9.5. Choosed functions
Item
Set-up
Item
Set-up
Divided-by-4 fAD / divided-
by-3 fAD / divided-by-2 fAD
/ fAD
Operation clock AD
Trigger for starting
A/D conversion
O
O
Software trigger
O
O
Trigger by ADTRG
Not activated
Resolution
8-bit / 10-bit
Sample & Hold
Analog input pin
Activated
AN
to AN
(6 pins) / AN
0
and AN
(4 pins) / AN
to AN
1 (2 pins) / AN0
3
0
to AN
5
O
0
7
(8 pins)
Operation (1) Setting the A/D conversion start flag to “1” causes the A/D converter to start the conversion on
voltage input to the AN0 pin.
(2) After the A/D conversion of voltage input to the AN0 pin is completed, the content of the
successive comparison register (conversion result) is transmitted to AD register 0. The A/D
converter converts all analog input pins selected by the user. The conversion result is trans-
mitted to AD register i corresponding to each pin, every time conversion on one pin is com-
pleted.
(3) When the A/D conversion on all the analog input pins selected is completed, the A/D conver-
sion interrupt request bit goes to “1”. At this time, the A/D conversion start flag goes to “0”.
The A/D converter stops operating.
(2)
After A/D conversion on AN
A/D converter begins converting all pins selected
0 pin is complete,
(1) Start A/D conversion
(3)
A/D conversion
is complete
8-bit resolution : 28 φAD cycles
10-bit resolution : 33 φAD cycles
8-bit resolution : 28 φAD cycles
10-bit resolution : 33 φAD cycles
φAD
Set to “1” by software
A/D conversion
start flag
“1”
“0”
AD register 0
AD register 1
Result
Result
AD register i
Result
A/D conversion “1”
interrupt request
bit
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Note: When φAD frequency is less than 1MH
Z
, sample and hold function cannot be selected.
Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution.
Figure 2.9.10. Operation timing of single sweep mode
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Selecting Sample and hold
b7
b0
AD control register 2 [Address 03D416
ADCON2
]
0
0
0
1
A/D conversion method select bit
1 : With sample and hold
Must always be set to “0”
Setting AD control register 0 and AD control register 1
b7
b0
b7
b0
AD control register 1 [Address 03D716
ADCON1
]
AD control register 0
[Address 03D616] ADCON0
0
0
1
0
0
0
1
0
Invalid in single sweep mode
A/D sweep pin select bit (Note 1)
b1 b0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
, AN1 (2 pins)
Single sweep mode is selected
(Note 1)
to AN
to AN
to AN
3
5
7
(4 pins)
(6 pins)
(8 pins)
Trigger select bit
0 : Software trigger
A/D operation mode select bit 1 (Note 1)
0 (Must always be “0” in Single sweep mode)
A/D conversion start flag
0 : A/D conversion disabled
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
Frequency select bit 0 (Note 2)
0 : fAD/3 or fAD/4 is selected
1 : fAD or fAD/2 is selected
Frequency select bit 1 (Note 2)
0 : fAD/2 or fAD/4 is selected
1 : fAD or fAD/3 is selected
Vref connect bit
1 : Vref connected
Reserved bit
Note 1 : Rewrite to analog input pin select bit after changing A/D operation mode.
Note 2 : When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing and set øAD frequency to 10 MHz or lower.
Setting A/D conversion start flag
b7
b0
AD control register 0 [Address 03D616
ADCON0
]
1
A/D conversion start flag
1 : A/D conversion started
Start A/D conversion
Stop A/D conversion
AD register 0
AD register 1
AD register 2
AD register 3
AD register 4
AD register 5
AD register 6
AD register 7
[Address 03C116, 03C016
]
]
]
]
]
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Reading conversion result
[Address 03C316, 03C216
[Address 03C516, 03C416
[Address 03C716, 03C616
[Address 03C916, 03C816
[Address 03CB16, 03CA16
[Address 03CD16, 03CC16
[Address 03CF16, 03CE16
(b15)
b7
(b8)
b0 b7
b0
]
]
]
Eight low-order bits of A/D conversion result
During 10-bit mode
Two high-order bits of A/D conversion result
During 8-bit mode
When read, the content is indeterminate
Figure 2.9.11. Set-up procedure of single sweep mode
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2.9.6 Operation of A/D Converter (in repeat sweep mode 0)
In repeat sweep 0 mode, choose functions from those listed in Table 2.9.6. Operations of the circled items
are described below. Figure 2.9.12 shows timing chart, and Figure 2.9.13 shows the set-up procedure.
Table 2.9.6. Choosed functions
Item
Set-up
Item
Set-up
Divided-by-4 fAD / divided-
by-3 fAD / divided-by-2 fAD
/ fAD
Operation clock AD
Trigger for starting
A/D conversion
O
O
Software trigger
O
O
Trigger by ADTRG
Not activated
Resolution
8-bit / 10-bit
Sample & Hold
Analog input pin
Activated
AN
to AN
(6 pins) / AN
0
and AN
(4 pins) / AN
to AN
1 (2 pins) / AN0
3
0
to AN
5
O
0
7
(8 pins)
Operation (1) Setting the A/D conversion start flag to “1” causes the A/D converter to start the conversion on
voltage input to the AN0 pin.
(2) After the A/D conversion of voltage input to the AN0 pin is completed, the content of the
successive comparison register (conversion result) is transmitted to AD register 0.
(3) The A/D converter converts all pins selected by the user. The conversion result is transmitted
to AD register i corresponding to each pin every time A/D conversion on the pin is completed.
The A/D conversion interrupt request bit does not go to “1”.
(4) The A/D converter continues operating until the A/D conversion start flag is set to “0” by
software.
(2) AN1 conversion begins after AN0
conversion is complete
(1) Start A/D conversion
(4)
A/D conversion
is complete
(3) Consecutive conversion
8-bit resolution : 28 φAD cycles
10-bit resolution : 33 φAD cycles
8-bit resolution : 28 φAD cycles
10-bit resolution : 33 φAD cycles
φAD
Cleared to “0” by software
Set to “1” by software.
A/D
conversion
start flag
“1”
“0”
AD register 0
Result
AD register 1
Result
AD register i
Result
Note:
When φAD frequency is less than 1MH
Z, sample and hold function cannot be selected.
Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution.
Figure 2.9.12. Operation timing of repeat sweep 0 mode
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Selecting Sample and hold
b7
b0
AD control register 2 [Address 03D416
ADCON2
]
0
0
0
1
A/D conversion method select bit
1 : With sample and hold
Must always be set to “0”
Setting AD control register 0 and AD control register 1
b7
0
b0
b7
b0
AD control register 1 [Address 03D716
ADCON1
]
AD control register 0
[Address 03D616] ADCON0
0
1
0
0
0
1
1
Invalid in Repeat mode
Invalid in repeat sweep mode 0
A/D operation mode select bit 1 (Note 1)
0 (Must always be “0” in repeat mode)
Repeat sweep mode 0 is selected
(Note 1)
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
Trigger select bit
0 : Software trigger
A/D conversion start flag
0 : A/D conversion disabled
Frequency select bit 1 (Note 2)
0 : fAD/2 or fAD/4 is selected
1 : fAD or fAD/3 is selected
Frequency select bit 0 (Note 2)
0 : fAD/3 or fAD/4 is selected
1 : fAD or fAD/2 is selected
Vref connect bit
1 : Vref connected
Reserved bit
Note 1 : Rewrite to analog input pin select bit after changing A/D operation mode.
Note 2 : When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing and set øAD frequency to 10 MHz or lower.
Setting A/D conversion start flag
b7
b0
AD control register 0 [Address 03D616
ADCON0
]
1
A/D conversion start flag
1 : A/D conversion started
Repeatedly carries out A/D conversion on pins
selected through the A/D sweep pin select bit.
Start A/D conversion
Transmitting conversion result to AD register i
AD register 0
AD register 1
AD register 2
AD register 3
AD register 4
AD register 5
AD register 6
AD register 7
[Address 03C116, 03C016
[Address 03C316, 03C216
[Address 03C516, 03C416
[Address 03C716, 03C616
[Address 03C916, 03C816
[Address 03CB16, 03CA16
[Address 03CD16, 03CC16
[Address 03CF16, 03CE16
]
]
]
]
]
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
(b15)
b7
(b8)
b0 b7
b0
]
]
]
Eight low-order bits of A/D conversion result
During 10-bit mode
Two high-order bits of A/D conversion result
During 8-bit mode
When read, the content is indeterminate
Setting A/D conversion start flag
b7
b0
AD control register 0 [Address 03D616
ADCON0
]
0
A/D conversion start flag
0 : A/D conversion disabled
Stop A/D conversion
Figure 2.9.13. Set-up procedure of repeat sweep 0 mode
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2.9.7 Operation of A/D Converter (in repeat sweep mode 1)
In repeat sweep 1 mode, choose functions from those listed in Table 2.9.7. Operations of the circled items are
described below. Figure 2.9.14 shows ANi pin's sweep sequence, Figure 2.9.15 shows timing chart, and Figure
2.9.16 shows the set-up procedure.
Table 2.9.7. Choosed functions
Item
Set-up
Item
Set-up
Divided-by-4 fAD / divided-
by-3 fAD / divided-by-2 fAD
/ fAD
Operation clock AD
Trigger for starting
A/D conversion
O
O
Software trigger
O
O
Trigger by ADTRG
Not activated
Resolution
8-bit / 10-bit
Sample & Hold
Analog input pin
Activated
An
pins) / AN
AN to AN
0
(1 pin) / AN
to AN
(4 pins)
0
and AN
2 (3 pins) /
1 (2
0
O
0
3
Operation (1) Setting the A/D conversion start flag to “1” causes the A/D converter to start the conversion on voltage
input to the AN0 pin.
(2) After the A/D conversion on voltage input to the AN0 pin is completed, the content of the successive
comparison register (conversion result) is transmitted to AD register 0.
(3) Every time the A/D converter carries out A/D conversion on a selected analog input pin, the A/D converter
carries out A/D conversion on only one unselected pin, and then the A/D converter carries out A/D conver-
sion from the AN0 pin again. The conversion result is transmitted to the corresponding AD register i every
time conversion on a pin is completed. The A/D conversion interrupt request bit does not go to “1”.
(4) The A/D converter continues operating until software goes the A/D conversion start flag to “0”.
When AN
0
is selected
When AN
0
, AN
1
are selected
Time
When AN
0
to AN
2
are selected
Time
When AN
0
to AN
3
are selected
Time
Time
0
1
0
2
0
0
4
0
5
0
0
0
1
0
0
0
1
0
1
0
0
1
0
1
0
1
0
1
0
.
.
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
0
.
.
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
.
.
.
.
.
1
.
.
.
2
2
2
3
3
3
3
4
4
4
4
5
5
5
6
6
6
6
7
7
7
7
Figure 2.9.14. ANi pin's sweep sequence in repeat sweep mode
Conversion result is
transfered to AD
conversion register 0
(2)
(3) Consecutive conversion
(1) Start AN0 pin
A/D conversion
(4)
A/D
conversion
is complete
8-bit resolution :
28 φAD cycles
10-bit resolution :
33 φAD cycles
8-bit resolution :
28 φAD cycles
10-bit resolution :
33 φAD cycles
8-bit resolution :
28 φAD cycles
8-bit resolution :
28 φAD cycles
10-bit resolution :
33 φAD cycles
10-bit resolution :
33 φAD cycles
φAD
Cleared to “0” by software
Set to “1” by software
A/D
conversion
start flag
“1”
“0”
Result
Result
AD register 0
AD register 1
AD register 2
Result
Result
Note: When φAD frequency is less than 1MHz, sample and hold function cannot be selected.
Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution.
Figure 2.9.15. Operation timing of repeat sweep 1 mode
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Selecting Sample and hold
b7
b0
AD control register 2 [Address 03D416
ADCON2
]
0
0
0
1
A/D conversion method select bit
1 : With sample and hold
Must always be set to “0”
Setting AD control register 0 and AD control register 1
b7
0
b0
b7
b0
AD control register 1 [Address 03D716
ADCON1
]
AD control register 0
[Address 03D616] ADCON0
0
1
1
0
0
1
1
Invalid in Repeat mode
Invalid in repeat sweep mode 0
A/D operation mode select bit 1 (Note 1)
1 (Must always be “1”
Repeat sweep mode 0 is selected
(Note 1)
in repeat sweep mode 1)
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
Trigger select bit
0 : Software trigger
A/D conversion start flag
0 : A/D conversion disabled
Frequency select bit 1 (Note 2)
0 : fAD/2 or fAD/4 is selected
1 : fAD or fAD/3 is selected
Frequency select bit 0 (Note 2)
0 : fAD/3 or fAD/4 is selected
1 : fAD or fAD/2 is selected
Vref connect bit
1 : Vref connected
Reserved bit
Note 1 : Rewrite to analog input pin select bit after changing A/D operation mode.
Note 2 : When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing and set øAD frequency to 10 MHz or lower.
Setting A/D conversion start flag
b7
b0
AD control register 0 [Address 03D616
ADCON0
]
1
A/D conversion start flag
1 : A/D conversion started
Converts non-selected pin after converting pins
selected through the A/D sweep pin select bit.
Start A/D conversion
Transmitting conversion result to AD register i
AD register 0
AD register 1
AD register 2
AD register 3
AD register 4
AD register 5
AD register 6
AD register 7
[Address 03C116, 03C016
[Address 03C316, 03C216
[Address 03C516, 03C416
[Address 03C716, 03C616
[Address 03C916, 03C816
[Address 03CB16, 03CA16
[Address 03CD16, 03CC16
[Address 03CF16, 03CE16
]
]
]
]
]
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
(b15)
b7
(b8)
b0 b7
b0
]
]
]
Eight low-order bits of A/D conversion result
During 10-bit mode
Two high-order bits of A/D conversion result
During 8-bit mode
When read, the content is indeterminate
Setting A/D conversion start flag
b7
b0
AD control register 0 [Address 03D616
ADCON0
]
0
A/D conversion start flag
0 : A/D conversion disabled
Stop A/D conversion
Figure 2.9.16. Set-up procedure of repeat sweep 1 mode
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2.9.8 Precautions for A/D Converter
(1) Write to each bit (except bit 6) of AD control register 0, to each bit of AD control register 1, and
to bit 0 of AD control register 2 when A/D conversion is stopped (before a trigger occurs).
In particular, when the Vref connection bit is changed from 0 to 1, start A/D conversion after
an elapse of 1 µs or longer.
(2) To reduce conversion error due to noise, connect a voltage to the AVcc pin and to the Vref pin from
an independent source. It is recommended to connect a capacitor between the AVss pin and the
AVcc pin, between the AVss pin and the Vref pin, and between the AVss pin and the analog input
pin (ANi). Figure 2.9.17 shows the an example of connecting the capacitors to these pins.
Microcomputer
VCC
AVCC
VREF
C1
C3
C2
AVSS
C1≥0.47 µF, C2≥0.47 µF, C3≥100 pF
(for reference)
Use thick and shortest possible wiring
to connect capacitors.
Note 1:
Note 2:
AN
i
Figure 2.9.17. Use of capacitors to reduce noice
(3) Set the direction register of the following ports to input: the port corresponding to a pin to be
used as an analog input pin and external trigger input pin (P93).
(4) Rewrite to analog input pin after changing A/D operation mode.
(5) When using the one-shot or single sweep mode
Confirm that A/D conversion is complete before reading the AD register.
(Note: When A/D conversion interrupt request bit is set, it shows that A/D conversion is completed.)
(6) When using the repeat mode or repeat sweep mode 0 or 1
Use the undivided main clock as the internal CPU clock.
(7) In using a key-input interrupt, none of the 8 pins (AN0 through AN7) can be used as an A/D
conversion port (if the A/D input voltage goes to “L” level, a key-input interrupt occurs).
(8) Use φAD under 10 MHz. When XIN is over 10 MHz, divide it.
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2.9.9 Method of A/D Conversion (10-bit mode)
(1) The A/D converter compares the reference voltage (Vref) generated internally based on the
contents of the successive comparison register with the analog input voltage (VIN) input from
the analog input pin. The comparison result is stored in the successive comparison register
and then VIN is converted to digital value (successive comparison method). If a trigger oc-
curs, the A/D converter carries out the following:
1. Fixes bit 9 of the successive comparison register.
Compares Vref with VIN: [In this instance, the contents of the successive comparison
register are “10000000002” (default).]
Bit 9 of the successive comparison register varies depending on the comparison re-
sult as follows.
If Vref < VIN, then “1” is assigned to bit 9.
If Vref > VIN, then “0” is assigned to bit 9.
2. Fixes bit 8 of the successive comparison register.
Sets bit 8 of the successive comparison register to “1”, then compares Vref with VIN.
Bit 8 of the successive comparison register varies depending on the comparison
result as follows:
If Vref < VIN, then “1” is assigned to bit 8.
If Vref > VIN, then “0” is assigned to bit 8.
3. Fixes bit 7 through bit 0 of the successive comparison register.
Carries out step 2 above on bit 7 through bit 0.
After bit 0 is fixed, the contents of the successive comparison register (conversion
result) are transmitted to AD register i.
Vref is generated based on the latest content of the successive comparison register. Table
2.9.8 shows the relationship of the successive comparison register contents and Vref. Table
2.9.9 shows how the successive comparison register and Vref vary while A/D conversion is in
progress. Figure 2.9.18 shows theoretical A/D conversion characteristics.
Table 2.9.8. Relationship of the successive comparison register contents and Vref
Successive approximation register : n
0
Vref (V)
0
V
1024
REF
VREF
2048
1 to1023
n
x
–
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Table 2.9.9. Variation of the successive comparison register and Vref while A/D conversion is in
progress (10-bit mode)
Successive approximation register
Vref change
b9
b0
V
REF
[V]
A/D converter stopped
1st comparison
2nd comparison
3rd comparison
1 0 0 0 0 0 0 0 0 0
2
V
V
REF
V
2048
REF
1 0 0 0 0 0 0 0 0 0
–
[V]
2
V
REF
n
9
= 1
= 0
+
REF
V
V
REF
V
2048
REF
4
[V]
n
9
9
1 0 0 0 0 0 0 0 0
1st comparison result
V
REF
–
n
9
–
2
4
4
±
V
REF
n
8
= 1
+
8
VREF
REF
V
REF
V
2048
REF
n
n8
1 0 0 0 0 0 0 0
2nd comparison result
±
±
–
[V]
V
REF
n8
= 0
–
2
4
8
8
V
REF
V
REF
V
REF
V
1024
REF
V
2048
REF
[V]
n
9
n
8
n
7
n
6
6
n
5
5
n
4
4
n3 n2 n1 1
10th comparison
± ...... ±
–
±
±
2
4
8
n
9
n
8
n
7
n
n
n
n3
n2
n1
n0
Conversion complete
This data transfers to the bit 0
to bit 9 of AD register i.
Result of A/D conversion
Theoretical A/D
conversion characteristic
3FF16
3FE16
00316
00216
Ideal A/D conversion
characteristic
00116
00016
V
1024
REF
V
1024
REF
V
1024
V
1024
REF
V
1024
REF
V
1024
REF x 3
x 1021
x 1022
REF x 1023
V
REF
0
x 1
x 2
V
1024
REF
Analog input voltage
x 0.5
Figure 2.9.18. Theoretical A/D conversion characteristics (10-bit mode)
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2. A/D Converter
2.9.10 Method of A/D Conversion (8-bit mode)
(1) In 8-bit mode, 8 higher-order bits of the 10-bit successive comparison register becomes A/D
conversion result. Hence, if compared to a result obtained by using an 8-bit A/D converter,
the voltage compared is different by 3 VREF/2048 (see what are underscored in Table
2.9.10), and differences in stepping points of output codes occur as shown in Figure 2.9.19.
Table 2.9.10. The comparison voltage in 8-bit mode compared to 8-bit A/D converter
8-bit mode
0
8-bit A/D converter
0
n = 0
Comparison
voltage
Vref
V
REF
28
V
REF
210
V
REF
28
V
REF
28
n = 1 to 255
n
n
–
–
x
x
x
x
0.5
0.5
Optimal conversion characteristics of 8-bit A/D converter (VREF = 5.12 V)
Output code
(Result of A/D conversion)
02
01
00
10
30
Analog input voltage (mV)
Optimal conversion characteristics in 8-bit mode (VREF = 5.12 V)
Output code
(Result of A/D conversion)
(Note)
8-bit
mode
10-bit
mode
10bit-mode
8bit-mode
09
08
07
06
05
04
03
02
02
01
01
00
00
17.5
37.5
Analog input voltage (mV)
Note: Differences in stepping points of output code for analog input voltage.
Figure 2.9.19. The level conversion characteristics of 8-bit mode and 8-bit A/D converter
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2. A/D Converter
Table 2.9.11. Variation of the successive comparison register and Vref while A/D conversion is in
progress (8-bit mode)
Successive approximation register
V
ref change
b9 b0
V
REF
[V]
1 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0
A/D converter stopped
1st comparison
2nd comparison
3rd comparison
2
V
REF
V
REF
[V]
–
±
±
2
2048
VREF
n9 = 1
+
4
V
REF
V
REF
VREF
2048
1 0 0 0 0 0 0 0 0
1st comparison result
n
9
[V]
–
VREF
n9 = 0
–
2
4
4
VREF
n8 = 1
+
V
REF
V
REF
V
REF
VREF
2048
8
1 0 0 0 0 0 0 0
2nd comparison result
n
9
n8
[V]
±
–
VREF
2
4
8
n8 = 0
–
8
V
REF
V
REF
V
REF
V
256
REF
V
2048
REF
1 0 0
n
9
9
n
8
n
7
n
6
n
5
n
4
n
3
3
8th comparison
[V]
±
±
± ...... ±
–
2
4
8
n
n
8
n
7
n6
n5
n4
n
n2
0 0
Conversion
complete
This data transfers to bit 0 to
bit 7 of AD register i.
Result of A/D conversion
Theoretical A/D conversion
characteristic of general 8-bit
A/D converter
FF16
FE16
0316
0216
Theoretical A/D conversion
characteristic in the 8-bit mode
0116
0016
V
256
REF
V
256
REF
V
256
REF
V
256
REF
V
256
REF
V
256
REF
x 4
V
REF
0
x 254
x 255
x 1
x 2
x 3
Analog input voltage
V
2048
REF
x 3
Figure 2.9.20. Theoretical A/D conversion characteristics (8-bit mode)
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2. A/D Converter
2.9.11 Absolute Accuracy and Differential Non-Linearity Error
• Absolute accuracy
Absolute accuracy is the difference between output code based on the theoretical A/D conversion
characteristics, and actual A/D conversion result. When measuring absolute accuracy, the voltage at
the middle point of the width of analog input voltage (1-LSB width), that can meet the expectation of
outputting an equal code based on the theoretical A/D conversion characteristics, is used as an ana-
log input voltage. For example, if 10-bit resolution is used and if VREF (reference voltage) = 5.12 V,
then 1-LSB width becomes 5 mV, and 0 mV, 5 mV, 10 mV, 15 mV, 20 mV, ···· are used as analog input
voltages. If analog input voltage is 25 mV, “absolute accuracy = ± 3LSB” refers to the fact that actual
A/D conversion falls on a range from “00216” to ”00816” though an output code, “00516”, can be ex-
pected from the theoretical A/D conversion characteristics. Zero error and full-scale error are included
in absolute accuracy.
Also, all the output codes for analog input voltage between VREF and AVcc becomes “3FF16”.
Output code
(result of A/D conversion)
00B16
00A16
00916
+3LSB
00816
00716
Theoretical A/D conversion
characteristic
00616
00516
00416
00316
00216
–3LSB
00116
00016
0
5
10 15
20
25
30
35
40
45
50
55
Analog input voltage (mV)
Figure 2.9.21. Absolute accuracy (10-bit resolution)
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2. A/D Converter
• Differential non-linearity error
Differential non-linearity error refers to the difference between 1-LSB width based on the theoretical A/
D conversion characteristics (an analog input width that can meet the expectation of outputting an
equal code) and an actually measured 1-LSB width (analog input voltage width that outputs an equal
code). If 10-bit resolution is used and if VREF (reference voltage) = 5.12 V, “differential non-linearity
error = ± 1LSB” refers to the fact that 1-LSB width actually measured falls on a range from 0 mV to 10
mV though 1-LSB width based on the theoretical A/D conversion characteristics is 5 mV.
Output code
(result of A/D conversion)
00916
1-LSB width for theoretical A/D
conversion characteristic
00816
00716
00616
00516
00416
00316
00216
00116
00016
Differential non-linear error
0
5
10
15
20
25 30
35
40
45
Analog input voltage (mV)
Figure 2.9.22. Differential non-linearity error (10-bit resolution)
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2. A/D Converter
2.9.12 Internal Equivalent Circuit of Analog Input
Figure 2.9.23 shows the internal equivalent circuit of analog input.
Vcc
Vcc Vss
AVcc
Parasitic
diode
ON resistor
approx. 0.6kΩ
ON resistor
approx. 2kΩ
Wiring resistor
approx. 0.2kΩ
C = Approx. 3.0pF
AN0
Analog input voltage
IN
AMP
SW1
V
SW2
ON resistor,
approx. 5k Ω
Parasitic
diode
Sampling
control signal
SW3
Vss
SW4
i ladder-type
switches
(i = 10)
i ladder-type
wiring resistors
(i = 10)
Chopper-type
amplifier
ON resistor
AVss
Ω
approx. 2k
AN i
ON resistor
approx. 0.2kΩ
SW1
AD successive conversion
register
b2 b1 b0
Reference control
signal
AD control register 0
Vref
Comparison voltage
V
REF
SW2'
Resistor
ladder
ON resistor
approx. 0.6kΩ
ADT/A/D conversion
interrupt request
AVss
Comparison reference voltage (Vref) generator
Sampling
Comparison
SW1 conducts only on the ports selected for analog input.
Connect to
Control signal
for SW2
SW2 and SW3 are open when A/D conversion is not in
progress; their status varies as shown by the waveforms in
the diagrams on the left.
Connect to
Connect to
Connect to
SW4 conducts only when A/D conversion is not in progress.
Control signal
for SW3
Warning: Use only as a standard for designing this data.
Mass production may cause some changes in device characteristics.
Figure 2.9.23. Internal equivalent circuit to analog input
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2. A/D Converter
2.9.13 Sensor’s Output Impedance under A/D Conversion (reference value)
To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 2.9.23 has to be
completed within a specified period of time. With T as the specified time, time T is the time that switches
SW2 and SW3 are connected to O in Figure 2.9.23. Let output impedance of sensor equivalent circuit be
R0, microcomputer’s internal resistance be R, precision (error) of the A/D converter be X, and the A/D
converter’s resolution be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode).
t
–
C (R0 + R)
Vc is generally VC = VIN {1 – e
}
X
Y
X
Y
And when t = T,
VC=VIN –
VIN=VIN(1 –
)
T
–
X
C (R0 + R)
e
=
Y
X
Y
T
C (R0 +R)
T
–
=ln
Hence, R0 = –
– R
X
Y
C • ln
With the model shown in Figure 2.9.24 as an example, when the difference between VIN and VC becomes
0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN-(0.1/1024) VIN in
time T. (0.1/1024) means that A/D precision drop due to insufficient capacitor charge is held to 0.1LSB at
time of A/D conversion in the 10-bit mode. Actual error however is the value of absolute precision added
to 0.1LSB. When f(XIN) = 10 MHz, T = 0.3 us in the A/D conversion mode with sample & hold. Output
impedance R0 for sufficiently charging capacitor C within time T is determined as follows.
T = 0.3 µs, R = 7.8 kΩ, C = 3 pF, X = 0.1, and Y = 1024 . Hence,
0.3 X 10-6
3
3
R0 = –
–7.8 X10
3.0 X 10
0.1
3.0 X 10 –12 • ln
1024
Thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the A/D con-
verter turns out to be approximately 3.0 kΩ. Tables 2.9.12 and 2.9.13 show output impedance values
based on the LSB values.
Microprocessor's inside
Sensor-equivalent circuit
R (7.8kΩ)
R0
VIN
C (3.0pF)
V
C
Figure 2.9.24 A circuit equivalent to the A/D conversion terminal
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2. A/D Converter
Table 2.9.12. Relation between output impedance and precision (error) of A/D converter (10-bit mode) Reference value
f(Xin)
(MHz)
10
Cycle
(µs)
0.1
Sampling time
(µs)
R
(k )
7.8
C
(pF)
3.0
Resolution
(LSB)
0.1
R0
(k )
3.0
4.5
5.3
5.9
6.4
6.8
7.2
7.5
7.8
8.1
0.4
0.9
1.3
1.7
2.0
2.2
2.4
2.6
2.8
0.3
(3 x cycle,
Sample & hold
bit is
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
0.3
0.5
0.7
0.9
1.1
1.3
1.5
enabled)
10
0.1
0.2
(2 x cycle,
Sample & hold
bit is
7.8
3.0
disabled)
1.7
1.9
Table 2.9.13. Relation between output impedance and precision (error) of A/D converter (8-bit mode) Reference value
f(Xin)
(MHz)
10
Cycle
(µs)
0.1
Sampling time
(µs)
R
(k )
7.8
C
(pF)
3.0
Resolution
(LSB)
0.1
R0
(k )
4.9
0.3
(3 x cycle,
Sample & hold
bit is
0.3
0.5
0.7
7.0
8.2
9.1
enabled)
0.9
9.9
1.1
1.3
1.5
1.7
1.9
0.1
10.5
11.1
11.7
12.1
12.6
0.7
10
0.1
0.2
(2 x cycle,
Sample & hold
bit is
7.8
3.0
0.3
2.1
0.5
2.9
0.7
3.5
disabled)
0.9
4.0
1.1
4.4
1.3
4.8
1.5
5.2
1.7
5.5
1.9
5.8
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2. DMAC
2.10 DMAC Usage
2.10.1 Overview of the DMAC usage
DMAC transfers one data item held in the source address to the destination address every time a transfer
request is generated. The following is an overview of the DMAC usage.
(1) Source address and destination address
Both the register which indicates a source and the register which indicates a destination comprise of
24 bits, so that each can cover a 1M bytes space. After transfer of one bit of data is completed, the
address in either the source register or the destination register can be incremented. However, both
registers cannot be incremented. The links between the source and destination are as follows:
(a) A fixed address from an arbitrary 1M bytes space
(b) An arbitrary 1M bytes space from a fixed address
(c) A fixed address from another fixed address
([002016 to 003F16 and 018016 to 019F16 ] cannot be accessed)
(2) The number of bits of data transferred
The number of bit of data indicated by the transfer counter is transferred. If a 16-bit transfer is se-
lected, up to 128K bytes can be transferred. If an 8-bit transfer is selected, up to 64K bytes can be
transferred. The transfer counter is decremented each time one bit of data is transferred, and a DMA
interrupt request occurs when the transfer counter underflows.
(3) DMA transfer factor
________
The DMA transfer factor can be selected from the following 31 factors: falling edge/two edges of INT0/
________ ________
INT1/INT2 pin, timer A0 interrupt request through timer A4 interrupt request, UART0 transmission/
NACK/SS interface 0 transmission interrupt request, UART0 reception/ACK/SS interface 0 reception
interrupt request, UART1 transmission/NACK/SS interface 1 transmission interrupt request, UART1
reception/ACK/SS interface 1 reception interrupt request, UART2 transmission/NACK interrupt re-
quest, UART2 reception/ACK interrupt request, UART3 transmission/NACK interrupt request, UART3
reception/ACK interrupt request, USB0/USB1/USB2/USB3 function interrupt request, A/D conversion
interrupt request, software trigger, and DMA trigger.
Software trigger is always enabled. When software trigger is selected, DMA transfer is generated by
writing “1” to software DMA interrupt request bit. When other factor is selected, DMA transfer is
generated by generating corresponding interrupt request.
(4) Channel priority
High to low priority: DMA0, DMA1, DMA2, DMA3
(5) Writing to a register
When writing to the source register or the destination register with DMA enabled, the content of the
register with a fixed address will change at the time of writing. Therefore, the user should not write to
a register with a fixed address when the DMA enable bit is set to “1”. The contents of the register with
‘forward direction’ selected, and the transfer counter, are changed when reloaded. A reload occurs
either when the transfer counter underflows, or when the DMA enable bit is re-enabled, after having
been disabled.
The reload register can be written to, as in normal conditions.
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2. DMAC
(6) Reading to a register
The reload register can be read to, as in normal conditions.
(7) Switching function
(a) Switching between one-shot transfer and repeated transfer
'One-shot transfer' refers to a mode in which DMA is disabled after the transfer counter underflows.
'Repeated transfer' refers to a mode in which a reload is carried out after the transfer counter under-
flows. The reload is carried out for the transfer counter and on the address pointer subjected to
forward direction.
The following examples are described in section 2.10.2 and 2.10.3.
• A fixed address from an arbitrary 1M byte space, one-shot transfer
• An arbitrary 1M byte space from a fixed address, repeated transfer
(8) Registers related to DMAC
Figure 2.10.1 shows the memory map of DMAC-related registers, and Figures 2.10.2 and 2.10.4 show
DMAC-related registers.
002016
018016
002116
002216
002316
002416
002516
002616
002716
002816
002916
DMA0 source pointer (SAR0)
DMA2 source pointer (SAR2)
018116
018216
018316
018416
018516
018616
018716
019816
018916
DMA0 destination pointer (DAR0)
DMA2 destination pointer (DAR2)
DMA0 transfer counter (TCR0)
DMA0 control register (DM0CON)
DMA2 transfer counter (TCR2)
DMA2 control register (DM2CON)
002C15
018C15
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
019016
019116
019216
019316
019416
019516
019616
019716
019816
019916
DMA1 source pointer (SAR1)
DMA3 source pointer (SAR3)
DMA1 destination pointer (DAR1)
DMA1 transfer counter (TCR1)
DMA3 destination pointer (DAR3)
DMA3 transfer counter (TCR3)
DMA3 control register (DM3CON)
003C16
004C16
004E16
005016
005216
DMA1 control register (DM1CON)
019C16
DMA0 interrupt control register (DM0IC)
03B016
03B116
03B216
DMA2 cause select register (DM2SL)
DMA3 cause select register (DM3SL)
DMA1 interrupt control register (DM1IC)
DMA2 interrupt control register (DM2IC)
DMA3 interrupt control register (DM3IC)
03B816
03B916
03BA16
DMA0 cause select register (DM0SL)
DMA1 cause select register (DM1SL)
Figure 2.10.1. Memory map of DMAC-related registers
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2. DMAC
DMA0 request cause select register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DM0SL
Address
03B816
When reset
0016
Bit Name
Function (Note 2)
R
O
W
O
Bit Symbol
b4 b3 b2 b1 b0
0 0 0 0 0 : DMA Disabled
0 0 0 0 1 : INT0 (falling edge)
0 0 0 1 0 : INT0 (two edges)
0 0 0 1 1 : USB0
0 0 1 0 0 : Timer A0
0 0 1 0 1 : Timer A1
0 0 1 1 0 : Timer A2
0 0 1 1 1 : Timer A3
0 1 0 0 0 : Timer A4
0 1 0 0 1 : UART0 receive/ACK/SSI0 receive
0 1 0 1 0 : UART1 receive/ACK/SSI1 receive
0 1 0 1 1 : UART2 receive/ACK
0 1 1 0 0 : UART3 receive/ACK
0 1 1 0 1 : UART0 transmit/NACK/SSI0 transmit
0 1 1 1 0 : UART1 transmit/NACK/SSI1 transmit
0 1 1 1 1 : UART2 transmit/NACK
1 0 0 0 0 : UART3 transmit/NACK
1 0 0 0 1 : A/D
1 0 0 1 0 : Disabled (Note 3)
1 0 0 1 1 : DMA1
1 0 1 0 0 : DMA2
1 0 1 0 1 : DMA3
1 0 1 1 0 : Disabled (Note 3)
1 0 1 1 1 : Disabled (Note 3)
DSEL0
DSEL1
DSEL2
DSEL3
DSEL4
DMA request
cause select bits
O
O
O
O
O
O
O
O
1 1 x
x x : Disabled (Note 3)
_
_
Nothing is assigned. Write “0” when writing to these bits. The value is “0” when read.
Software trigger is always enabled
Write “1” to trigger DSR bit.
Software DMA
request bit
O
O
DSR
Note 1: Software is always enabled.
Note 2: SSI=Serial sound interface
Note 3: This value should not be set.
DMA1 request cause select register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DM1SL
Address
03BA16
When reset
0016
Bit Name
Function (Note 2)
R
O
W
O
Bit Symbol
DSEL0
b4 b3 b2 b1 b0
0 0 0 0 0 : DMA Disabled
0 0 0 0 1 : INT1 (falling edge)
0 0 0 1 0 : INT1 (two edges)
0 0 0 1 1 : USB1
DMA request
cause select bits
0 0 1 0 0 : Timer A0
0 0 1 0 1 : Timer A1
0 0 1 1 0 : Timer A2
0 0 1 1 1 : Timer A3
0 1 0 0 0 : Timer A4
0 1 0 0 1 : UART0 receive/ACK/SSI0 receive
0 1 0 1 0 : UART1 receive/ACK/SSI1 receive
0 1 0 1 1 : UART2 receive/ACK
0 1 1 0 0 : UART3 receive/ACK
0 1 1 0 1 : UART0 transmit/NACK/SSI0 transmit
0 1 1 1 0 : UART1 transmit/NACK/SSI1 transmit
0 1 1 1 1 : UART2 transmit/NACK
1 0 0 0 0 : UART3 transmit/NACK
1 0 0 0 1 : A/D
1 0 0 1 0 : DMA0
1 0 0 1 1 : Disabled (Note 3)
1 0 1 0 0 : DMA2
1 0 1 0 1 : DMA3
1 0 1 1 0 : Disabled (Note 3)
1 0 1 1 1 : Disabled (Note 3)
O
O
O
O
DSEL1
DSEL2
DSEL3
DSEL4
O
O
O
O
1 1 x
x x : Disabled (Note 3)
_
_
Nothing is assigned. Write “0” when writing to these bits. The value is “0” when read.
Software trigger is always enabled
Write “1” to trigger DSR bit.
Software DMA
request bit
O
O
DSR
Note 1: Software is always enabled.
Note 2: SSI=Serial sound interface
Note 3: This value should not be set.
Figure 2.10.2. DMAC-related registers (1)
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2. DMAC
DMA2 request cause select register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DM2SL
Address
03B016
When reset
0016
Bit Name
Function (Note 2)
R
O
W
O
Bit Symbol
b4 b3 b2 b1 b0
0 0 0 0 0 : DMA Disabled
0 0 0 0 1 : INT2 (falling edge)
0 0 0 1 0 : INT2 (two edges)
0 0 0 1 1 : USB2
0 0 1 0 0 : Timer A0
0 0 1 0 1 : Timer A1
0 0 1 1 0 : Timer A2
0 0 1 1 1 : Timer A3
0 1 0 0 0 : Timer A4
0 1 0 0 1 : UART0 receive/ACK/SSI0 receive
0 1 0 1 0 : UART1 receive/ACK/SSI1 receive
0 1 0 1 1 : UART2 receive/ACK
0 1 1 0 0 : UART3 receive/ACK
0 1 1 0 1 : UART0 transmit/NACK/SSI0 transmit
0 1 1 1 0 : UART1 transmit/NACK/SSI1 transmit
0 1 1 1 1 : UART2 transmit/NACK
1 0 0 0 0 : UART3 transmit/NACK
1 0 0 0 1 : A/D
1 0 0 1 0 : DMA0
1 0 0 1 1 : DMA1
1 0 1 0 0 : Disabled (Note 3)
1 0 1 0 1 : DMA3
1 0 1 1 0 : Disabled (Note 3)
1 0 1 1 1 : Disabled (Note 3)
DSEL0
DSEL1
DSEL2
DSEL3
DSEL4
DMA request
cause select bits
O
O
O
O
O
O
O
O
1 1 x
x x : Disabled (Note 3)
_
_
Nothing is assigned. Write “0” when writing to these bits. The value is “0” when read.
Software trigger is always enabled
Write “1” to trigger DSR bit.
Software DMA
request bit
O
O
DSR
Note 1: Software is always enabled.
Note 2: SSI=Serial sound interface
Note 3: This value should not be set.
DMA3 request cause select register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DM3SL
Address
03B216
When reset
0016
Bit Name
Function (Note 2)
R
O
W
O
Bit Symbol
DSEL0
b4 b3 b2 b1 b0
0 0 0 0 0 : DMA Disabled
0 0 0 0 1 : INT0 (falling edge)
0 0 0 1 0 : INT0 (two edges)
0 0 0 1 1 : USB3
DMA request
cause select bits
0 0 1 0 0 : Timer A0
0 0 1 0 1 : Timer A1
0 0 1 1 0 : Timer A2
0 0 1 1 1 : Timer A3
0 1 0 0 0 : Timer A4
0 1 0 0 1 : UART0 receive/ACK/SSI0 receive
0 1 0 1 0 : UART1 receive/ACK/SSI1 receive
0 1 0 1 1 : UART2 receive/ACK
0 1 1 0 0 : UART3 receive/ACK
0 1 1 0 1 : UART0 transmit/NACK/SSI0 transmit
0 1 1 1 0 : UART1 transmit/NACK/SSI1 transmit
0 1 1 1 1 : UART2 transmit/NACK
1 0 0 0 0 : UART3 transmit/NACK
1 0 0 0 1 : A/D
1 0 0 1 0 : DMA0
1 0 0 1 1 : DMA1
1 0 1 0 0 : DMA2
1 0 1 0 1 : Disabled (Note 3)
1 0 1 1 0 : Disabled (Note 3)
1 0 1 1 1 : Disabled (Note 3)
O
O
O
O
DSEL1
DSEL2
DSEL3
DSEL4
O
O
O
O
1 1 x
x x : Disabled (Note 3)
_
_
Nothing is assigned. Write “0” when writing to these bits. The value is “0” when read.
Software trigger is always enabled
Write “1” to trigger DSR bit.
Software DMA
request bit
O
O
DSR
Note 1: Software is always enabled.
Note 2: SSI=Serial sound interface
Note 3: This value should not be set.
Figure 2.10.3. DMAC-related registers (2)
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2. DMAC
DMAi control register
b7 b6 b5 b4 b3 b2 b1 b0
Address
Symbol
When reset
002C16, 003C16
018C16, 019C16
,
DMiCON (i=0-3)
00000X00
2
Bit Name
Transfer unit select bit
Function
R
O
W
Bit Symbol
DMBIT
0 : 16 bits
1 : 8 bits
O
O
O
0 : Single transfer
1 : Repeat transfer
O
O
Repeat transfer mode select bit
DMA request bit (Note 1)
DMA enable bit
DMASL
DMAS
DMAE
DSD
0 : DMA not requested
1 : DMA requested
(Note 2)
0 : Disabled
1 : Enabled
O
O
O
O
Source address
direction select bit (Note 3)
0 : Fixed
1 : Forward
0 : Fixed
1 : Forward
Destination address
direction select bit (Note 3)
DAD
O
_
O
_
Nothing is assigned. Write “0” when writing to these bits. The value is “0” when read.
Note 1: DMA request can be cleared by resetting the bit.
Note 2: This bit can only be set to “0”.
Note 3: Source address direction select bit and destination address direction select bit cannot
be set to “1” simultaneously.
DMAi source pointer (i=0-3)
Symbol
Address
When reset
(b23)
b7
(b19)
b3
(b16)(b15)
b0b7
(b8)
b0b7
SAR0
SAR1
SAR2
SAR3
002216 to 002016
003216 to 003016
018216 to 018016
019216 to 019016
Indeterminate
Indeterminate
Indeterminate
Indeterminate
b0
Transfer address
specification
Function
R
W
Source pointer
stores the source address
0000016 to FFFFF16
O O
_ _
Nothing is assigned.
Write “0” when writing to these bits. The value is “0” when read.
DMAi destination pointer (i=0-3)
Symbol
Address
When reset
(b23)
b7
(b19)
b3
(b16)(b15)
b0b7
(b8)
b0b7
DAR0
DAR1
DAR2
DAR3
002616 to 002416
003616 to 003416
018616 to 018416
019616 to 019416
Indeterminate
Indeterminate
Indeterminate
Indeterminate
b0
Transfer address
Function
Destination pointer
stores the destination address
R
W
specification
0000016 to FFFFF16
O O
_ _
Nothing is assigned.
Write “0” when writing to these bits. The value is “0” when read.
DMAi transfer counter (i=0-3)
Symbol
Address
When reset
(b15)
b7
(b8)
b0b7
TCR0
TCR1
TCR2
TCR3
002916 to 002816
003916 to 003816
018916 to 018816
019816 to 019816
Indeterminate
Indeterminate
Indeterminate
Indeterminate
b0
Transfer count
specification
Function
R
W
Transfer counter
Set a value one less than the transfer count
0000016 to FFFFF16
O O
Figure 2.10.4. DMAC-related registers (3)
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2. DMAC
2.10.2 Operation of DMAC (one-shot transfer mode)
In one-shot transfer mode, choose functions from the items shown in Table 2.10.1. Operations of the
circled items are described below. Figure 2.10.5 shows an example of operation and Figure 2.10.6
shows the set-up procedure.
Table 2.10.1. Choosed functions
Item
Set-up
Fixed address from an arbitrary 1 M bytes space
Arbitrary 1 M bytes space from a fixed address
Fixed address from fixed address
8 bits
Transfer space
O
O
Unit of transfer
16 bits
Operation
(1) When software trigger is selected, setting software DMA request bit to “1” generates a DMA
transfer request signal.
(2) If DMAC is active, data transfer starts, and the contents of the address indicated by the DMAi
forward-direction address pointer are transferred to the address indicated by the DMAi desti-
nation pointer. When data transfer starts directly after DMAC becomes active, the value of
the DMAi transfer counter reload register is reloaded to the DMAi transfer counter, and the
value of the DMAi source pointer is reloaded by the DMAi forward-direction address pointer.
Each time a DMA transfer request signal is generated, 1 byte of data is transferred. The
DMAi transfer counter is down counted, and the DMAi forward-direction address pointer is up
counted.
(3) If the DMA transfer counter underflows, the DMA enable bit changes to “0” and DMA transfer
is completed. The DMA interrupt request bit changes to “1” simultaneously.
(1) Request signal for a DMA transfer occurs
(3) Underflow
(2) Data transfer begins
BCLK
Destination
Destination
Dummy
cycle
Dummy
cycle
Address bus
CPU use
Source
CPU use
CPU use
Source
RD signal
WR signal
Destination
Destination
Dummy
cycle
Dummy
cycle
CPU use
Source
CPU use
Source
CPU use
Data bus
Write signal to
software DMAi
request bit
DMAi
request bit
DMA transfer
counter
Indeterminate
0016
FF16
0116
DMAi
interrupt
request bit
Cleared to “0” when interrupt request is
accepted, or cleared by software
DMAi
enable bit
• In the case in which the number of transfer times is set to 2.
Figure 2.10.5. Example of operation of one-shot transfer mode
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2. DMAC
Setting DMAi request cause select register
b7
b0
DMAi request cause select register [Address 03B816, 03BA16, 03B016, 03B216
DMiSL(i = 0 to 3)
]
0
DMA request cause select bit
Software trigger is always enabled
Software DMA request bit
Set to “0”
Setting DMAi control register
b7
b0
DMAi control register [Address 002C16, 003C16, 018C16, 019C16
DMiCON(i = 0 to 3)
]
0
1
0
0
0
1
Transfer unit bit select bit
1 : 8 bits
Repeat transfer mode select bit
0 : Single transfer
DMA request bit
0 : DMA not requested
DMA enable bit
0 : Disabled
Source address direction select bit
1 : Forward (Bit 4 and bit 5 cannot be set to “1” simultaneously)
Destination address direction select bit
0 : Fixed (Bit 4 and bit 5 cannot be set to “1” simultaneously)
DMA0 source pointer [Address 002216 to 002016] SAR0
DMA1 source pointer [Address 003216 to 003016] SAR1
DMA2 source pointer [Address 018216 to 018016] SAR2
DMA3 source pointer [Address 019216 to 019016] SAR3
(b8)
Setting DMAi source pointer
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
b0 b7
b0
Source pointer
Stores the source address
DMA0 destination pointer [Address 002616 to 002416] DAR0
DMA1 destination pointer [Address 003616 to 003416] DAR1
DMA2 destination pointer [Address 018616 to 018416] DAR2
DMA3 destination pointer [Address 019616 to 019416] DAR3
Setting DMAi destination pointer
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Destination pointer
Stores the destination address
DMA0 transfer counter [Address 002916, 002816] TCR0
DMA1 transfer counter [Address 003916, 003816] TCR1
DMA2 transfer counter [Address 018916, 018816] TCR2
DMA3 transfer counter [Address 019916, 019816] TCR3
b0
Setting DMAi transfer counter
(b15)
b0
(b8)
b0
b7
Transfer counter
Set a value one less than the transfer count
Setting DMAi control register
b7
b0
DMAi control register [Address 002C16, 003C16, 018C16, 019C16
DMiCON(i = 0 to 3)
]
1
DMA enable bit
1 : Enabled
Note: Clear DMA request bit simultaneously again.
When software DMA request bit = “1”
Start DMA transmission
Figure 2.10.6. Set-up procedure of one-shot transfer mode
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2. DMAC
2.10.3 Operation of DMAC (repeated transfer mode)
In repeat transfer mode, choose functions from the items shown in Table 2.10.2. Operations of the circled
items are described below. Figure 2.10.7 shows an example of operation and Figure 2.10.8 shows the
set-up procedure.
Table 2.10.2. Choosed functions
Item
Set-up
Fixed address from an arbitrary 1 M bytes space
Arbitrary 1 M bytes space from a fixed address
Fixed address from fixed address
8 bits
Transfer space
O
Unit of transfer
16 bits
O
(1) When software trigger is selected, setting software DMA request bit to “1” generates a DMA
transfer request signal.
Operation
(2) If DMAC is active, data transfer starts, and the contents of the address indicated by the DMAi
forward-direction address pointer are transferred to the address indicated by the DMAi desti-
nation pointer. When data transfer starts directly after DMAC becomes active, the value of
the DMAi transfer counter reload register is reloaded to the DMAi transfer counter, and the
value of the DMAi source pointer is reloaded by the DMAi forward-direction address pointer.
Each time a DMA transfer request signal is generated, 2 byte of data is transferred. The
DMAi transfer counter is down counted, and the DMAi forward-direction address pointer is up
counted.
(3) Though DMAi transfer counter is underflowed, DMA enable bit is still “1”. The DMA interrupt
request bit changes to “1” simultaneously.
(4) After DMAi transfer counter is underflowed, when the next DMA request is generated, DMA
transfer is repeated from (1).
(1) Request signal for a DMA transfer occurs
(3) Underflow
(2) Data transfer begins
BCLK
Destination
Source
Dummy cycle
Destination
Source
Dummy cycle
CPU use
Destination
Source
Dummy cycle
CPU use
Address bus
CPU use
CPU use
RD signal
WR signal
Destination
Source
Destination
Source
Dummy cycle
Dummy cycle
CPU use
Dummy cycle
CPU use
Destination
Source
Data bus
CPU use
CPU use
Write signal to
software DMAi
request bit
DMAi
request bit
0116
0116
DMA transfer
counter
Indeterminate
0016
FF16
0016
DMAi
interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleared by software
“1”
DMAi
enable bit
• In the case in which the number of transfer times is set to 2.
Figure 2.10.7. Example of operation of repeated transfer mode
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2. DMAC
Setting DMAi request cause select register
b7
b0
DMAi request cause select register [Address 03B816, 03BA16, 03B016, 03B216
DMiSL(i = 0 to 3)
]
0
DMA request cause select bit
Software trigger is always enabled
Software DMA request bit
Set to “0”
Setting DMAi control register
b7
b0
DMAi control register [Address 002C16, 003C16, 018C16, 019C16
DMiCON(i = 0 to 3)
]
1
0
0
0
1
0
Transfer unit bit select bit
0
: 16 bits
Repeat transfer mode select bit
1 : Repeat transfer
DMA request bit
0 : DMA not requested
DMA enable bit
0 : Disabled
Source address direction select bit
0 : Fixed (Bit 4 and bit 5 cannot be set to “1” simultaneously)
Destination address direction select bit
1 : Forward (Bit 4 and bit 5 cannot be set to “1” simultaneously)
DMA0 source pointer [Address 002216 to 002016] SAR0
DMA1 source pointer [Address 003216 to 003016] SAR1
DMA2 source pointer [Address 018216 to 018016] SAR2
DMA3 source pointer [Address 019216 to 019016] SAR3
(b8)
Setting DMAi source pointer
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
b0 b7
b0
Source pointer
Stores the source address
DMA0 destination pointer [Address 002616 to 002416] DAR0
DMA1 destination pointer [Address 003616 to 003416] DAR1
DMA2 destination pointer [Address 018616 to 018416] DAR2
DMA3 destination pointer [Address 019616 to 019416] DAR3
Setting DMAi destination pointer
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Destination pointer
Stores the destination address
DMA0 transfer counter [Address 002916, 002816] TCR0
DMA1 transfer counter [Address 003916, 003816] TCR1
DMA2 transfer counter [Address 018916, 018816] TCR2
DMA3 transfer counter [Address 019916, 019816] TCR3
b0
Setting DMAi transfer counter
(b15)
b0
(b8)
b0
b7
Transfer counter
Set a value one less than the transfer count
Setting DMAi control register
b7
b0
DMAi control register [Address 002C16, 003C16, 018C16, 019C16
DMiCON(i = 0 to 3)
]
1
DMA enable bit
1 : Enabled
Note: Clear DMA request bit simultaneously again.
When software DMA request bit = “1”
Start DMA transmission
Figure 2.10.8. Set-up procedure of repeated transfer mode
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2. CRC Calculation Circuit
2.11 CRC Calculation Circuit
2.11.1 Overview
Cyclic Redundancy Check (CRC) is a method that compares CRC code formed from transmission data
by use of a polynomial generation with CRC check data so as to detect errors in transmission data. Using
the CRC calculation circuit allows generation of CRC code. The microcomputer uses a generator polyno-
16
12
5
16
15
2
mial of CRC_CCITT (X + X + X + 1) or CRC-16 (X + X + X + 1) to generte CRC code.
And, the CRC circuit includes the ability to snoop reads and writes to SFR addresses. This can be used
to accumulate the CRC value on a stream of data without using extra bandwidth to explicitly write data
into the CRCIN register.
(1) Registers related to CRC calculation circuit
Figure 2.11.1 shows the memory map of CRC-related registers, and Figure 2.11.2 shows CRC- re-
lated registers.
03B416
CRC snoop address register CRCSAR
03B516
03B616
CRC mode register CRCMR
03BC16
03BD16
03BE16
CRC data register CRCD
CRC input register CRCIN
Figure 2.11.1. Memory map of CRC-related registers
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2. CRC Calculation Circuit
CRC data register
(b15)
b7
(b8)
b0b7
Symbol
CRCD
Address
03BC16 to 03BD16
When reset
Indeterminate
b0
Values that can be set
000016 to FFFF16
Function
R
W
O O
CRC calculation result output
CRC input register
Symbol
CRCIN
Address
03BE16
When reset
Indeterminate
b7
b0
Values that can be set
0016 to FF16
Function
R
W
Data input
O O
CRC mode register
b0
b7
Address
03B616
When reset
Symbol
CRCMR
0016
Function
R
W
Bit symbol
CRCPS
Bit name
16
16
12
15
5
CRC mode polynomial
selection bit
0 : X +X +X +1 (CRC-CCITT)
1 : X +X +X +1 (CRC-16)
O
_
O
_
2
Nothing is assigned.
Write “0” when writing to this bit. The value is “0” if read.
0 : LSB first mode
1 : MSB first mode
CRC mode mode
selection bit
CRCMS
O
O
CRC snoop address register
(b15)
b7
(b8)
b0
b0
b7
Address
Symbol
When reset
00XXXX?? ????????2
03B516, 03B416
CRCSAR
Bit name
Function
SFR address to snoop (Note)
R
O
W
CRCSAR9-0
CRC Snoop address bits
O
_
Nothing is assigned.
Write “0” when writing to this bit. The value is indeterminate if read.
_
0 : Disabled
1 : Enabled
CRC Snoop on
read enable bit
O
O
O
O
CRCSR
CRCSW
CRC Snoop on
write enable bit
0 : Disabled
1 : Enabled
Note: Only USB, UART and SSI related registers can be snooped.
Figure 2.11.2. CRC-related registers
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2. CRC Calculation Circuit
2.11.2 Operation of CRC Calculation Circuit
The following describes the operation of the CRC calculation. Figure 2.11.3 shows an example of calcu-
lation using the CRC-CCITT.
Operation (1) Select CRC-CCITT or CRC-16, and LSB first or MSB first by bit 0 and bit 5 of CRC mode
register.
(2) The CRC calculation circuit sets an initial value in the CRC data register.
(3) Writing 1 byte data to the CRC input register generates CRC code based on the data register.
CRC code generation for 1 byte data finishes in two machine cycles.
(4) When several bytes of CRC calculation is performed in succession, write the following data in
the CRC input register continuously.
(5) The content of CRC data register after all data is written becomes CRC code.
b15
b0
b0
CRC data register CRCD
[03BD16, 03BC16
(1) Setting 000016
(2) Setting 0116
]
b7
CRC input register
2 cycles
CRCIN
[03BE16
]
After CRC calculation is complete
b15
b0
CRC data register
Stores CRC code
CRCD
[03BD16, 03BC16
118916
]
The code resulting from sending 0116 in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial,
16
12
5
16
(X + X + X + 1), becomes the remainder resulting from dividing (1000 0000) X by (1 0001 0000 0010 0001) in
conformity with the modulo-2 operation.
LSB
MSB
Modulo-2 operation is
operation that complies
with the law given below.
1000 1000
1 0001 0000 0010 0001
1000 0000 0000 0000 0000 0000
1000 1000 0001 0000 1
1000 0001 0000 1000 0
1000 1000 0001 0000 1
1001 0001 1000 1000
LSB
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 0
-1 = 1
MSB
9
8
1
1
Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000)
corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation
circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC
operation. Also switch between the MSB and LSB of the result as stored in CRC data.
b7
b0
CRC input register
CRCIN
[03BE16
(3) Setting 2316
]
After CRC calculation is complete
b15
b0
CRC data register
Stores CRC code
CRCD
[03BD16, 03BC16
0A4116
]
Figure 2.11.3. Calculation example using the CRC calculation circuit (when using CRC-CCITT)
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2. CRC Calculation Circuit
2.11.3 SFR Access Snoop Function
The CRC calculation circuit includes the ability to snoop write/read to/from the SFR addresses and to
execute CRC automatic calculation (SFR access snoop function). In order to execute CRC calculation for
data which have been written/read to/from the SFR, setting data to CRC input register again is not re-
quired. The target SFRs include USB-related registers, UART-related registers, and Serial Sound Inter-
face-related registers.
(1) The bit 1 of CRC mode register selects either CRC-CCITT or CRC-16, and the bit 7 selects
either LSB first or MSB first.
Operation
(2) The target SFR addresses are set to CRC snoop address register (bit 0 to 9 of CRCSAR).
Snooping of writing to the target SFR is enabled with CRC snoop on write enable bit (bit 15 of
CRCSAR), and snooping of reading from the target SFR is enabled with CRC snoop on read
enable bit (bit 14 of CRCSAR).
(3) The initial value 000016 is set to CRC data register.
(4) If writing into the target SFR is executed by either the CPU or DMA while “1” is set to CRC
snoop on write enable bit, the CRC calculation circuit will store the data written to the target
SFR in CRC input register, and executes CRC calculation. Similarly, if reading from the target
SFR by the CPU or DMA while “1” is set to CRC snoop on read enable bit, calculation circuit
will store the data read from the target SFR in CRC input register, and executes CRC calcu-
lation. The CRC calculation circuit can only calculate CRC codes on data 1-byte at a time.
Therefore, if a target SFR is accessed in a word (16-bit) bus cycle, only 1-byte data are stored
into CRC input register.
(5) When 1-byte data is stored in CRC input register, CRC codes are generated in CRC data
register based on the stored data and the content of CRC data register. Generation of CRC
codes for 1-byte of data is completed in two machine cycles.
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2. Watchdog Timer
2.12 Watchdog Timer
2.12.1 Overview
The watchdog timer can detect a runaway program using its 15-bit timer prescaler. The following is an
overview of the watchdog timer.
(1) Watchdog timer start procedure
When reset, the watchdog timer is in stopped state. Writing to the watchdog timer start register
initializes the watchdog timer to 7FFF16 and causes it to start performing a down count. The watchdog
timer, once started operating, cannot be stopped by any means other than stopping conditions.
(2) Watchdog timer stop conditions
The watchdog timer stops in any one of the following states:
(a) Period in which the CPU is in stopped state
(b) Period in which the CPU is in waiting state
(c) Period in which the microcomputer is in hold state
(3) Watchdog timer initialization
The watchdog timer is initialized to 7FFF16 in the cases given below, and begins a down count.
(a) When the watchdog timer writes to the watchdog timer start register while a count is in progress
(b) When the watchdog timer underflows
(4) Runaway detection
When the watchdog timer underflows, either a watchdog timer interrupt occurs or reset is selected
depending on the setting of the watchdog timer function select bit. In writing a program, write to the
watchdog timer start register before the watchdog timer underflows.
The watchdog timer interrupt occurs regardless of the status of the interrupt enable flag (I flag). In
processing a watchdog timer interrupt, set the software reset bit to “1” to reset software.
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2. Watchdog Timer
(5) Watchdog timer cycle
The watchdog timer cycle varies depending on the BCLK and the frequency division ratio of the
prescaler selected.
Table 2.12.1 shows the watchdog timer cycle.
Table 2.12.1. The watchdog timer cycle (f(XIN) = 16MHZ)
CM07
CM06
CM17
CM16
WDC7
0
Period
BCLK
Approx. 32.8ms (Note)
0
0
0
0
16MHz
1
0
Approx. 262.1ms (Note)
Approx. 65.5ms (Note)
0
0
0
0
0
0
0
1
1
1
0
1
8MHz
4MHz
1MHz
1
0
1
0
Approx. 524.3ms (Note)
Approx. 131.1ms (Note)
Approx. 1.049s (Note)
Approx. 524.3ms (Note)
1
Approx. 4.194s (Note)
Approx. 262.1ms (Note)
Approx. 2.097s (Note)
Approx. 2s (Note)
0
1
0
1
1
Invalid
Invalid
Invalid
Invalid
2MHz
32kHz
Invalid
Invalid
Note: An error due to the prescaler occurs.
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2. Watchdog Timer
(6) Registers related to the watchdog timer
Figure 2.12.1 shows the memory map of watchdog timer-related registers, and Figure 2.12.2 shows
watchdog timer-related registers.
000E16
Watchdog timer start register (WDTS)
000F16
001016
Watchdog timer control register (WDC)
Figure 2.12.1. Memory map of watchdog timer-related registers
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
WDC
Address
000F16
When reset
000XXXXX
0 0
2
Bit symbol
Bit name
Function
R W
High-order bit of Watchdog timer
Reserved bit
Must always be set to “0”
0 : Divided by 16
1 : Divided by 128
WDC7
Prescaler select bit
Watchdog timer start register
b7
b0
Symbol
WDTS
Address
000E16
When reset
Indeterminate
Function
R W
The Watchdog timer is initialized and starts counting after the first write instruction
to this register after reset. Writing any value to this register resets the counter to
7FFF16
.
Figure 2.12.2. Watchdog timer-related registers
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2. Watchdog Timer
2.12.2 Operation of Watchdog Timer (Watchdog timer interrupt)
The following is an operation of the watchdog timer using watchdog timer interrupt. Figure 2.12.3 shows
the operation timing, and Figure 2.12.4 shows the set-up procedure.
Operation (1) Writing to the watchdog timer start register initializes the watchdog timer to 7FFF16 and
causes it to start a down count.
(2) With a count in progress, writing to the watchdog timer start register again initializes the
watchdog timer to 7FFF16 and causes it to resume counting.
(3) Either executing the WAIT instruction or going to the stopped state causes the watchdog
timer to hold the count in progress and to stop counting. The watchdog timer resumes count-
ing after returning from the execution of the WAIT instruction or from the stopped state.
(4) If the watchdog timer underflows, it is initialized to 7FFF16 and continues counting. At this
time, a watchdog timer interrupt occurs.
(3)
In stopped state, or WAIT
instruction is executing, etc
(1) Start count
(4) Generate
watchdog timer
interrupt
(2) Write operation
7FFF16
000016
“H”
“L”
Write signal to the
watchdog timer
start register
Figure 2.12.3. Operation timing of watchdog timer (watchdog timer interrupt)
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2. Watchdog Timer
Setting watchdog timer control register
b7
b0
Watchdog timer control register [Address 000F16
WDC
]
0
0
Reserved bit
Must always be “0”
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
Setting watchdog timer start register
b7
b0
Watchdog timer start register [Address 000E16
WDTS
]
The watchdog timer is initialized and starts counting with a write instruction to
this register. The watchdog timer value is always initialized to “7FFF16
”
regardless of the value written.
Generating watchdog
timer interrupt
Cancel protect register
b7
b0
Protect register [Address 000A16
PRCR
]
0
1
Enables writing to processor mode register 0 and 1 (addresses 000416 and
000516
)
1: Write-enabled
Reserved bit
Software reset
b7
b0
Processor mode register 0 [Address 000416
PM0
]
1
Software reset bit
The device is reset when this bit is set to “1”.
The value of this bit is “0” when read.
Figure 2.12.4. Set-up procedure of watchdog timer interrupt (watchdog timer interrupt)
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2. Address Match Interrupt
2.13 Address Match Interrupt Usage
2.13.1 Overview of the address match interrupt usage
The address match interrupt is used for correcting a ROM or for a simplified debugging-purpose monitor.
When the external bus is used for 8 bits, the address match interrupt is not used to the external areas.
The following is an overview of the address match interrupt usage.
(1) Enabling/disabling the address match interrupt
The address match interrupt enable bit can be used to enable and disable an address match interrupt.
It is affected neither by the processor interrupt priority level (IPL) nor the interrupt enable flag (I flag).
(2) Timing of the address match interrupt
An interrupt occurs immediately before executing the instruction in the address indicated by the ad-
dress match interrupt register. Set the first address of the instruction in the address match interrupt
register. Setting a half address of an instruction or an address of tabulated data does not generate an
address match interrupt.
The first instruction of an interrupt routine does not generate an address match interrupt either.
(3) Returning from an address match interrupt
The address put in the stack when an address match interrupt occurs depends on the instruction not
yet executed (the instruction the address match interrupt register indicates). The return address is not
put in the stack. For this reason, to return from an address match interrupt, either rewrite the content
of the stack and use the REIT instruction or use the POP instruction to restore the stack to the state as
it was before the interrupt occurred and return by use of a jump instruction.
<Instructions whose address is added to by 2 when an address match interrupt occurs>
• 16-bit operation code instructions
• 8-bit operation code instructions given below
ADD.B:S
OR.B:S
#IMM8,dest
#IMM8,dest
SUB.B:S
#IMM8,dest
AND.B:S
STZ.B:S
#IMM8,dest
#IMM8,dest
MOV.B:S #IMM8,dest
STNZ.B:S #IMM8,dest
STZX.B:S #IMM81,#IMM82,dest
CMP.B:S
JMPS
#IMM8,dest
#IMM8
PUSHM
JSRS
src
POPM
dest
#IMM8
MOV.B:S #IMM,dest (However, dest = A0/A1)
<Instructions whose address is added to by 1 when an address match interrupt occurs>
• Instructions other than those listed above
Figure 2.13.1. Unexecuted instructions and corresponding stacked addresses
Figure 2.13.1 shows unexecuted instructions and corresponding the stacked addresses.
(4) How to determine an address match interrupt
Address match interrupts can be set at two different locations. However, both location will have the
same vector address. Therefore, it is necessary to determine which interrupt has occurred; address
match interrupt 0 or address match interrupt 1. Using the content of the stack, etc., determine which
interrupt has occurred according to the first part of the address match interrupt routine.
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2. Address Match Interrupt
(5) Registers related to the address match interrupt
Figure 2.13.2 shows the memory map of address match interrupt-related registers, and Figure 2.13.3
shows address match interrupt-related registers.
000916
Address match interrupt enable register (AIER)
001016
001116
001216
001316
Address match interrupt register 0 (RMAD0)
Address match interrupt register 1 (RMAD1)
001416
001516
001616
Figure 2.13.2. Memory map of address match interrupt-related registers
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AIER
Address
000916
When reset
XXXXXX00
2
Bit symbol
AIER0
Bit name
R W
Function
Address match interrupt 0
enable bit
0 : Interrupt disaled
1 : enabled
Address match interrupt 1
enable bit
0 : Interrupt disaled
1 : enabled
AIER1
Nothing is assigned. Write “0” when writing to these bits.
If read, the value is indeterminate.
Address match interrupt register i (i = 0, 1)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
Symbol
RMAD0
RMAD1
Address
001216 to 001016
001616 to 001416
When reset
X0000016
X0000016
b0
Function
Address setting register for address match interrupt
Values that can be set
R W
0000016 to FFFFF16
Nothing is assigned. Write “0” when writing to these bits.
If read, the value is indeterminate.
Figure 2.13.3. Address match interrupt-related registers
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2. Address Match Interrupt
2.13.2 Operation of Address Match Interrupt
The following is an operation of address match interrupt. Figure 2.13.4 shows the set-up procedure of
address match interrupt, and Figure 2.13.5 shows the overview of the address match interrupt handling
routine.
Operation (1) The address match interrupt handling routine sets an address to be used to cause the ad-
dress match interrupt register to generate an interrupt.
(2) Setting the address match enable flag to “1” enables an interrupt to occur.
(3) An address match interrupt occurs immediately before the instruction in the address indicated
by the address match interrupt register as a program is executed.
Setting address match interrupt register
Address match interrupt register 0 [Address 001216 to 001016
]
RMAD0
Address match interrupt register 1 [Address 001616 to 001416
RMAD1
]
(b23)
b7
(b20)(b19)
b4 b3
(b16) (b15)
b0 b7
(b8)
b0 b7
b0
Can be set to “0000016” to “FFFFF16
”
Setting address match interrupt enable register
b7
b0
Address match interrupt enable register [Address 000916
AIER
]
Address match interrupt 0 enable bit
1: Interrupt enabled
Address match interrupt 1 enable bit
1: Interrupt enabled
Figure 2.13.4. Set-up procedure of address match interrupt
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2. Address Match Interrupt
Address match interrupt routine
[1] Storing registers
[2] Determining the interrupt address
No
Address match 0?
Yes
No
Address match 1?
Address match 0 program
Yes
Address match 1 program
[3] Rewriting the stack
Restoring registers
REIT
Handling an error
Explanation:
[1]
Storing the contents of the registers holding the main program status to be kept.
[2] Determining the interrupt address
Determining which factor generated the interrupt.
[3] Rewriting the stack
Rewriting the return address.
Figure 2.13.5. Overview of the address match interrupt handling routine
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2. Key-Input Interrupt
2.14 Key-Input Interrupt Usage
2.14.1 Overview of the key-input interrupt usage
Key-input interrupt can be generated by a falling edge, rising edge or both edges input to any Port 10 pin.
It can also be used as a Key-on wake up function for canceling the wait mode or stop mode. It is possible
to select the edge of the Key input interrupt for P10 with bits 0 and 1 of key input mode register. This
register is also used to enable or disable Port 10 pins that are to be used for Key-input interrupts. Port 10
can be configured with pull-up resistors using the pull-up control resistor.
The following is an overview of the key-input interrupt usage:
(1) Enabling/disabling the key-input interrupt
The key-input interrupt can be enabled and disabled using the key-input mode register (03F916) and
the key-input interrupt register (004116). The key-input interrupt is affected by the interrupt priority
level (IPL) and the interrupt enable flag (I flag). A falling edge, rising edge or both edges input to any
Port 10 pin can be selected by P10 Key-input edge select bits (bit0 and bit1 of 03F916).
(2) Occurrence timing of the key-input interrupt
With key-input interrupt acceptance enabled, pins P100 through P107, which are set to input, become
_____
____
key-input interrupt pins (KI0 through KI7). A Key-input interrupt occurs when the selected edge is input
to a Key-input interrupt pin. At this moment, the level of other key-input interrupt pins must be “H”. No
interrupt occurs when the level of other key-input interrupt pins is “L”.
(3) How to determine a key-input interrupt
A key-input interrupt occurs when the selected edge is input to one of eight pins, but each pin has the
same vector address. Therefore, read the input level of Port P10 in the key-input interrupt routine to
determine the interrupted pin.
(4) Registers related to the key-input interrupt
Figure 2.14.1 shows the memory map of key-input interrupt-related registers, and Figure 2.14.2 and
2.14.3 show key-input interrupt-related registers.
004116
03F616
Key input interrupt control register (KUPIC)
Port P10 direction register (PD10)
Key-input mode register (KUPM)
Pull-up control register 2 (PUR2)
03F916
03FE16
Figure 2.14.1. Memory map of key-input interrupt-related registers
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2. Key-Input Interrupt
Key input interrupt control register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
KUPIC
Address
004116
When reset
XXXXX000
2
R
W
Bit symbol
ILVL0
Bit name
Function
Interrupt priority level
select bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
ILVL1
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1: Level 7
ILVL2
IR
Interrupt request bit
0 : Interrupt not requested
1 : Interrupt requested
(Note 2)
Nothing is assigned. Write “0” when writing to these bits.
The contents are indeterminate if read.
Note 1: To rewrite the interrupt control register, do so at a point that dose not generate the
interrupt request for that register. For details, see the precautions for interrupts.
Note 2: This bit can only be reset (=0), but cannot be set (=1).
Port P10 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD10
Address
03F616
When reset
0016
R
W
Bit symbol
Bit symbol
Bit symbol
0 : Imput mode
PD10_0
PD10_1
Port P10
0
1
direction register
direction register
Port P10
(Functions as an input port)
1 : Output mode
PD10_2
PD10_3
Port P10
Port P10
2
3
direction register
direction register
(Functions as an output port)
PD10_4
Port P10
Port P10
Port P10
Port P10
4
direction register
PD10_5
PD10_6
5
direction register
direction register
6
PD10_7
7
direction register
Figure 2.14.2. key-input interrupt-related registers (1)
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2. Key-Input Interrupt
Key-input mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
KUPM
Address
03F916
When reset
0016
Bit Symbol
KIS0
Bit Name
Function
R
W
b1 b0
P10 Key-input edge select 0
P10 Key-input edge select 1
0 0 : Falling edge
0 1 : Rising edges
1 0 : Two edge
1 1 : Reserved
O
O
O
O
KIS1
KIE0
KIE1
KIE2
KIE3
0 : Disabled
1 : Enabled
O
O
O
O
P10
0
and P10
1
Key-input enable bit
0 : Disabled
1 : Enabled
P10
2
and P10
3
Key-input enable bit
0 : Disabled
1 : Enabled
P10
4
and P10
5
Key-input enable bit
O
O
O
O
0 : Disabled
1 : Enabled
P106 and P107 Key-input enable bit
Nothing is assigned. Write “0” when writing to these bits.
The value is “0” if read.
_ _
Pull-up control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR2
Address
03FE16
When reset
0016
Bit symbol
Bit name
Function
R W
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
PU20
PU21
P8
P8
0
4
to P8
to P8
3
7
pull-up
pull-up
5)
(Except P8
P9 to P9
(Except P9
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
1 : Pulled high
PU22
0
3 pull-up
1
)
PU24
P10
0
to P10
3
pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
PU25
P10
4
to P10
7
pull-up
1 : Pulled high
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Figure 2.14.3. key-input interrupt-related registers (2)
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2. Key-Input Interrupt
2.14.2 Operation of Key-Input Interrupt
The following is an operation of key-input interrupt. Figure 2.14.4 shows an example of a circuit that uses
the key-input interrupt, Figure 2.14.5 shows an example of operation of key-input interrupt, and Figure
2.14.6 shows the setting procedure of key-input interrupt.
Operation (1) Set the direction register of the ports to be changed to key-input interrupt pins to input, and set
the pull-up function.
(2) Setting the key-input interrupt control register and setting the interrupt enable flag makes the
interrupt-enabled state ready.
_____
(3) If a falling edge is input to either KI0 through KI7, the key-input interrupt request bit goes to “1”.
VREF
P10
4
5
P10
P10
6
7
P10
I/O port
P100
/ KI0
P10
P10
P10
1
/ KI
/ KI
/ KI
1
2
3
2
3
Figure 2.14.4. Example of circuit using the key-input interrupt
(1) Enter to stop mode
(2) Cancel stop mode
(3) Key scan
Key matrix scan
(4) Enter to stop mode
P10
P10
P10
4
output
output
output
5
6
P10
7
output
to P10
P10
0
3
input
Key OFF
Key ON
Key OFF
Key ON
Key input
Key input
interrupt processing
Figure 2.14.5. Example of operation of key-input interrupt
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2. Key-Input Interrupt
Setting key input mode register
b7
b0
Key input mode register [Address 03F916
KUPM
]
1
0
0
1
0
0
P10 Key-input edge select bit 0
P10 Key-input edge select bit 1
b1 b0
0 0 : Falling edge
P10
0
and P10
1
Key-input enable bit
1 : Enabled
P10 and P10
1 : Enabled
P10 and P10
1 : Disabled
P10 and P10
1 : Disabled
2
3
Key-input enable bit
4
5
7
Key-input enable bit
Key-input enable bit
6
Setting port P10 direction register
b7
b0
Port P10 direction register [Address 03F616
PD10
]
1
1
1
1
0
0
0
0
0 : Input mode (Functions as an input port)
1 : Output mode (Functions as an output port)
Setting pull-up control register 2
b7
b0
Pull-up control register 2 [Address 03FE16
PUR2
]
1
P100 to P103
1 : Pulled high
Setting key input interrupt control register
b7
b0
Key input interrupt control register [Address 004116
KUPIC
]
0
Interrupt priority level select bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
Interrupt request bit
0 : Interrupt not requested
Figure 2.14.6. Set-up procedure of key-input interrupt
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2. Multiple Interrupts
2.15 Multiple interrupts Usage
2.15.1 Overview of the Multiple interrupts usage
The following is an overview of the multiple interrupts usage.
(1) Interrupt control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a non-maskable interrupt using the interrupt enable flag (I flag), interrupt priority
level selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or
absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level
select bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I
flag) and the IPL are located in the flag register (FLG).
Figure 2.15.1 shows the memory map of the interrupt control registers, and Figure 2.15.2 shows the
interrupt control registers.
004116
Key input interrupt control register (KUPIC)
UART2 receive/ACK interrupt control register (S2RIC)
004216
004316
UART1/3 Bus collision interrupt control register (S13BCNIC)
INT1 interrupt control register (INT1IC)
004416
004516
Timer A1 interrupt control register (TA1IC)
USB Endpoint 0 interrupt control register (EP0IC)
Timer A2 interrupt control register (TA2IC)
004616
004716
004816
004916
UART1 receive/ACK/SSI1 interrupt control register (S1RIC)
UART0/2 Bus collision interrupt control register (S02BCNIC)
UART0 receive/ACK/SSI0 interrupt control register (S0RIC)
004A16
004B16
AD conversion interrupt control register (ADIC)
DMA0 interrupt conrol register (DM0IC)
004C16
004D16
UART3 transmit/NACK interrupt control register (S3TIC)
DMA1 interrupt control register (DM1IC)
004E16
004F16
005016
UART2 transmit/NACK interrupt control register (S2TIC)
DMA2 interrupt control register (DM2IC)
UART1 transmit/NACK/SSI1 interrupt control register (S1TIC)
005116
005216
DMA3 interrupt control register (DM3IC)
005316
005416
UART0 transmit/NACK/SSI0 interrupt control register (S0TIC)
Timer A0 interrupt control register (TA0IC)
UART3 receive/ACK interrupt control register (S3RIC)
USB suspend interrupt control register (SUSPIC)
Timer A3 interrupt control register (TA3IC)
USB resume interrupt control register (RSMIC)
Timer A4 interrupt control register (TA4IC)
005516
005616
005716
005816
005916
005A16
005B16
005C16
USB reset interrupt control register (RSTIC)
USB SOF interrupt control register (SOFIC)
USB Vbus detect interrupt control register (VBDIC)
USB function interrupt control register (USBFIC)
005D16
005E16
005F16
INT2 interrupt control register (INT2IC)
INT0 interrupt control register (INT0IC)
Figure 2.15.1. Memory map of the interrupt control registers
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2. Multiple Interrupts
Interrupt control register (Note 1)
Symbol
S1TIC
DM3IC
S0TIC
TA0IC
S3RIC
SUSPIC
TA3IC
RSMIC
TA4IC
RSTIC
SOFIC
VBSIC
USBFIC
Address
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
When reset
Symbol
KUPIC
S2RIC
Address
004116
004216
When reset
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
2
2
2
2
2
2
2
2
2
2
2
2
2
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
2
2
2
2
2
2
2
2
2
2
2
2
2
S13BCNIC 004316
TA1IC
EP0IC
TA2IC
S0RIC
ADIC
DM0IC
S3TIC
DM1IC
S2TIC
DM2IC
004516
004616
004716
004A16
004B16
004C16
004D16
004E16
004F16
005016
b7 b6 b5 b4 b3 b2 b1 b0
R
W
Bit symbol
ILVL0
Bit name
Function
Interrupt priority level
select bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
ILVL1
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1: Level 7
ILVL2
IR
Interrupt request bit
0 : Interrupt not requested
1 : Interrupt requested
(Note 2)
Nothing is assigned. Write “0” when writing to these bits.
The contents are indeterminate if read.
When reset
Address
004416
004816
004916
005E16
005F16
Symbol
INT1IC
S1RIC
S02BCNIC
INT2IC
INT0IC
XX00X000
XX00X000
XX00X000
XX00X000
XX00X000
2
2
2
2
2
b7 b6 b5 b4 b3 b2 b1 b0
0
Bit symbol
ILVL0
Bit name
Function
W
R
Interrupt priority level
select bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
ILVL1
ILVL2
1 1 0 : Level 6
1 1 1: Level 7
IR
0 : Interrupt not requested
1 : Interrupt requested
Interrupt request bit
Polarity select bit
(Note 2)
(Note 3)
POL
0 : Selects falling edge
1 : Selects rising edge
Reserved bit
Always set to “0”
Nothing is assigned. Write “0” when writing to these bits.
The contents are indeterminate if read.
Note 1: To rewrite the interrupt control register, do so at a point that dose not generate the
interrupt request for that register. For details, see the precautions for interrupts.
Note 2: This bit can only be reset (=0), but cannot be set (=1).
Note 3: For S1RIC ( 004816 ) and S02BCNIC ( 004916), “0” should always be written.
Figure 2.15.2. Interrupt control registers
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(2) Interrupt Enable Flag (I flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting
this flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This
flag is set to “0” after reset.
The content is changed when the I flag is changed causes the acceptance of the interrupt request in
the following timing:
• When changing the I flag using the REIT instruction, the acceptance of the interrupt takes
effect as the REIT instruction is executed.
• When changing the I flag using one of the FCLR, FSET, POPC, and LDC instructions, the
acceptance of the interrupt is effective as the next instruction is executed.
When changed by REIT instruction
Determination whether or not to
accept interrupt request
Interrupt request generated
Time
Previous
instruction
REIT
Interrupt sequence
(If I flag is changed from 0 to 1 by REIT instruction)
When changed by FCLR, FSET, POPC, or LDC instruction
Interrupt request generated
Determination whether or not to
accept interrupt request
Time
Previous
FSET I
Next instruction
Interrupt sequence
instruction
(If I flag is changed from 0 to 1 by FSET instruction)
Figure 2.15.3. The timing of reflecting the change in the I flag to the interrupt
(3) Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware.
The interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
(4) Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component
bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is
compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher
than the IPL. Therefore, setting the interrupt priority level to “0” disables the interrupt.
Table 2.15.1 shows the settings of interrupt priority levels and Table 2.15.2 shows the interrupt levels
enabled, according to the contents of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = 1
· interrupt request bit = 1
· interrupt priority level > IPL
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The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL
are independent, and they are not affected by one another.
Table 2.15.1. Settings of interrupt priority levels Table 2.15.2. Interrupt levels enabled according
to the contents of the IPL
Interrupt priority
level select bit
Interrupt priority
level
Priority
order
IPL
Enabled interrupt priority levels
b2 b1 b0
IPL
2
IPL1
IPL0
Level 0 (interrupt disabled)
0
0
0
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
0
0
0
1
1
0
Low
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
High
When either the IPL or the interrupt priority level is changed, the new level is reflected to the interrupt
in the following timing:
• When changing the IPL using the REIT instruction, the reflection takes effect as of the instruction
that is executed in 2 clock cycles after the last clock cycle in volved in the REIT instruction.
• When changing the IPL using either the POPC, LDC or LDIPL instruction, the reflection takes
effect as of the instruction that is executed in 3 cycles after the last clock cycle involved in the
instruction used.
• When changing the interrupt priority level using the MOV or similar instruction, the reflection takes
effect as of the instruction that is executed in 2 clock cycles after the last clock cycle involved in
the instruction used.
(5) Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (check-
ing whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority
level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher
hardware priority is accepted.
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest
priority), watchdog timer interrupt, etc. are regulated by hardware.
Figure 2.15.4 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control
branches invariably to the interrupt routine.
Reset > _N__M___I_ > _D__B___C__ > Watchdog timer > Peripheral I/O > Single step > Address match
Figure 2.15.4. Hardware interrupts priorities
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2. Multiple Interrupts
(6) Interrupt resolution circuit
When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the
highest priority level. Figure 2.15.5 shows the circuit that judges the interrupt priority level.
Priority level of each interrupt
Level 0 (initial value)
High
INT2
Vbus detection
USB reset
USB resume
USB
suspend
USB EP0
INT1
INT0
USB function
USB SOF
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
DMA3
DMA2
DMA1
DMA0
Priority of peripheral I/O interrupts
(if priority levels are same)
UART0 reception/ACK
/SSI0 reception
UART1 reception/ACK
/SSI1 reception
UART2 reception/ACK
UART3 reception/ACK
UART0 transmission/NACK
/SSI0 transmission
UART1 transmission/NACK
/SSI1 transmission
UART2 transmission/NACK
UART3 transmission/NACK
A/D conversion
UART0/UART2 Bus collision detection,
Start/stop condition detection
UART1/UART3 Bus collision detection,
Start/stop condition detection
DMA0
Key input interrupt
Low
Processor interrupt priority level (IPL)
Interrupt enable flag (I flag)
Interrupt
request
accepted
Address match
Watchdog timer
DBC
NMI
Reset
Figure 2.15.5. Interrupts resolution circuit
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2.15.2 Multiple Interrupts Operation
The state when control branched to an interrupt routine is described below:
· The interrupt enable flag (I flag) is set to “0” (the interrupt is disabled).
· The interrupt request bit of the accepted interrupt is set to “0”.
· The processor interrupt priority level (IPL) is assigned to the same interrupt priority level as as
signed to the accepted interrupt.
Setting the interrupt enable flag (I flag) to “1” within an interrupt routine allows an interrupt request as-
signed a priority higher than the IPL to be accepted.
An interrupt request that is not accepted because of low priority will be held. If the condition following is
met when the REIT instruction returns the IPL and the interrupt priority is determined, then the interrupt
request being held is accepted.
Interrupt priority level of the interrupt request being held
>
Returned the IPL
Figure 2.15.6 shows the example of the multiple interrupts operation.
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2. Multiple Interrupts
Interrupt request
generated
Nesting
Main routine
I = 0
Reset
Time
IPL = 0
I = 1
Interrupt 1
Interrupt priority level = 3
Interrupt 1
I = 0
IPL = 3
I = 1
Multiple interrupts
Interrupt 2
Interrupt priority level = 5
Interrupt 2
I = 0
IPL = 5
Interrupt 3
REIT
I = 1
Interrupt priority level = 2
IPL = 3
Interrupt 3
REIT
I = 1
Not acknowledged because
of low interrupt priority
IPL = 0
Main routine instructions
are not executed.
Interrupt 3
I = 0
IPL = 2
REIT
I = 1
I : Interrupt enable flag
IPL = 0
IPL : Processor interrupt priority level
: Automatically executed.
: Be sure to set in software.
Figure 2.15.6. Example of the multiple interrupts operation
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2. Power Control
2.16 Power Control Usage
2.16.1 Overview of the power control usage
‘Power Control’ refers to the reduction of CPU power consumption by stopping the CPU and oscillators,
or decreasing the operation clock. The following is a description of the three available power control
modes:
(1) Modes
Power control is available in three modes.
(a) Normal operation mode
• High-speed mode
Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the BCLK
selected. Each peripheral function operates according to its assigned clock.
• Medium-speed mode
Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the
BCLK. The CPU operates according to the BCLK selected. Each peripheral function operates
according to its assigned clock.
• Low-speed mode
fC becomes the BCLK. The CPU operates according to the fc clock. The fC clock is supplied by the
secondary clock. Each peripheral function operates according to its assigned clock.
• Low power consumption mode
The main clock operating in low-speed mode is stopped. The CPU operates according to the fc
clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate
are those with the sub-clock selected as the count source.
(b) Wait mode
The CPU operation is stopped. The oscillators do not stop.
(c) Stop mode
All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three
modes listed here, is the most effective in decreasing power consumption.
Figure 2.16.1 is the state transition diagram of the above modes.
(2) Switching the driving capacity of the oscillation circuit
Both the main clock and the secondary clock have the ability to switch the driving capacity.
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Transition of stop mode, wait mode
Reset
All oscillators stopped
CPU operation stopped
WAIT
instruction
CM10 = “1”
Medium-speed mode
(divided-by-8 mode)
Stop mode
Wait mode
Interrupt
Interrupt
Interrupt
WAIT
instruction
All oscillators stopped
CPU operation stopped
High-speed/medium-
speed mode
CM10 = “1”
Stop mode
Wait mode
Interrupt
WAIT
instruction
All oscillators stopped
CPU operation stopped
CM10 = “1”
Low-speed/low power
dissipation mode
Stop mode
Wait mode
Interrupt
Interrupt
Normal mode
(Refer to the following for the transition of normal mode.)
Transition of normal mode
Main clock is oscillating
Sub clock is stopped
Medium-speed mode
(divided-by-8 mode)
CM06 = “1”
BCLK : f(XIN)/8
CM07 = “0” CM06 = “1”
CM07 = “0” (Note 1)
CM06 = “1”
CM04 = “1”
(Notes 1, 3)
Main clock is oscillating
Sub clock is oscillating
CM04 = “0”
Medium-speed mode
(divided-by-2 mode)
High-speed mode
Main clock is oscillating
Sub clock is oscillating
BCLK : f(XIN
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
)
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-8 mode)
Low-speed mode
CM07 = “0”
(Note 1, 3)
BCLK : f(XIN)/8
CM07 = “0”
CM06 = “1”
BCLK : f(XCIN
)
Medium-speed mode
(divided-by-4 mode)
Medium-speed mode
(divided-by-16 mode)
CM07 = “1”
CM07 = “1”
BCLK : f(XIN)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
(Note 2)
CM05 = “0”
CM05 = “1”
CM04 = “0”
CM04 = “1”
Main clock is oscillating
Sub clock is stopped
Main clock is stopped
Sub clock is oscillating
Low power dissipation mode
Medium-speed mode
(divided-by-2 mode)
High-speed mode
CM07 = “1” (Note 2)
CM05 = “1”
BCLK : f(XIN
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
)
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
BCLK : f(XCIN
)
CM07 = “1”
CM07 = “0” (Note 1)
CM06 = “0” (Note 3)
Medium-speed mode
(divided-by-4 mode)
Medium-speed mode
(divided-by-16 mode)
CM06 = “0”
(Notes 1,3)
BCLK : f(XIN)/4
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM06 after changing CM17 and CM16.
Note 4: Transit in accordance with arrow.
Figure 2.16.1. State transition diagram of power control mode
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(3) Returning from stop mode
The stop mode can be canceled by hardware reset, or by generating an interrupt request. If an inter-
rupt is to be used to cancel stop mode, that interrupt must first have been enabled and the priority level
of the interrupt not to be used for clearing must be set to level 0 before changing to stop mode.
If an interrupt is used to cancel stop mode, that interrupt routine is processed. If only a hardware reset
and NMI interrupt are used to cancel stop mode, the priority level of all interrupts must be set to level
0 before changing to stop mode.
When changing from high-speed/medium mode to stop mode and at reset, the main clock division
select bit 0 (bit 6 at address 000616) is set to “1”. When changing from low-speed/low power dissipa-
tion mode, the value before stop mode is retained.
(4) Returning form wait mode
The wait mode can be canceled by hardware reset, or by generating an interrupt request. If an inter-
rupt is to be used to cancel wait mode, that interrupt must first have been enabled and the priority level
of the interrupt not to be used for clearing must be set to level 0 before changing to wait mode.
If an interrupt is used to cancel wait mode, the microcomputer selects the clock used when the WAIT
instruction is executed for BCLK and restarts operating in that interrupt routine. If only a hardware
reset or NMI interrupt will be used to cancel wait mode, the priority level of all interrupts must be set to
level 0 before changing to stop mode.
Table 2.16.1 shows the interrupts that can be used for canceling stop mode and wait mode.
(5) BCLK in returning from wait mode or stop mode
(a) Returning from wait mode
The processor immediately returns to the BCLK, which was in use before entering wait mode.
(b) Returning from stop mode
CM06 is set to “1” when the device enters stop mode after selecting the main clock for BCLK. CM17
and CM16 do not change state. In this case, when restored from stop mode, the device starts oper-
ating in divided-by-8 mode.
When the device enters stop mode after selecting the subclock for BCLK, CM06, CM17, CM16, and
CM07 all do not change state. In this case, when restored from stop mode, the device starts operat-
ing in low-speed mode.
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Table 2.16.1. Interrupts available for clearing stop mode and wait mode
Wait mode
Interrupt for clearing
CM02 =1(Note 6),
Stop mode
CM02 = 0
Possible
CM07 = 0, CM05 = 0
Note 1
Note 1
Note 1
UART0/UART2 Bus collision detection,
Start/stop condition detection interrupt
UART1/UART3 Bus collision detection,
Start/stop condition detection interrupt
DMA0 interrupt
Possible
Note 1
Impossible
Impossible
Impossible
Impossible
Possible
Impossible
Impossible
Impossible
Impossible
Possible
Impossible
Impossible
Impossible
Impossible
Possible
DMA1 interrupt
DMA2 interrupt
DMA3 interrupt
Key input interrupt
Note 3
Impossible
Note 1
Impossible
Note 1
A/D interrupt
Possible
UART0 transmit/NACK
/SSI0 transmit interrupt (Note7)
UART0 receive/ACK
Possible
Possible
Possible
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
/SSI0 receive interrupt (Note 7)
UART1 transmit/NACK
/SSI1 transmit interrupt (Note7)
UART1 receive/ACK
/SSI1 receive interrupt (Note 7)
UART2 transmit/NACK interrupt (Note 7)
UART2 receive/ACK interrupt (Note 7)
UART3 transmit/NACK interrupt (Note 7)
UART3 receive/ACK interrupt (Note 7)
Timer A0 interrupt
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 2, Note 4
Note 2, Note 4
Note 2, Note 4
Note 2, Note 4
Note 2, Note 4
Possible
Note 2
Note 2
Timer A1 interrupt
Note 2
Timer A2 interrupt
Note 2
Timer A3 interrupt
Note 2
Timer A4 interrupt
Impossible
Note 5
USB suspend interrupt
USB resume interrupt
Possible
Possible
Impossible
Impossible
Possible
Impossible
Impossible
Possible
Possible
Possible
Possible
USB reset interrupt
Possible
USB SOF interrupt
Possible
USB Vbus detection interrupt
USB function interrupt
USB EP0 interrupt
Possible
Possible
Possible
INT0 interrupt
Possible
INT1 interrupt
Possible
INT2 interrupt
Possible
NMI interrupt
Note 1: Can be used when an external clock is selected.
Note 2: Can be used when the external signal is being counted in event counter mode.
Note 3: Can be used in one-shot mode and one-shot sweep mode.
Note 4: Can be used when count source is fC32
Note 5: Only when USB suspend mode.
.
Note 6: When the MCU running in low-speed or low power dissipation mode, do not enter wait mode with
CM02 is set to “1”.
Note 7: When I2C mode is selected, NACK/ACK, start/stop condition detection interrupt are selected, and when SS pin
is selected, trouble error interrupt is selected.
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(5) Sequence of returning from stop mode
Sequence of returning from stop mode is oscillation start-up time and interrupt sequence.
When interrupt is generated in stop mode, CM10 becomes “0” and clearing stop mode.
Starting oscillation and supplying BCLK execute the interrupt sequence as follow:
In the interrupt sequence, the processor carries out the following in sequence given:
(a) CPU gets the interrupt information (the interrupt number and interrupt request level) by read-
ing address 0000016. The interrupt request bit of the interrupt written in address 0000016 will
then be set to “0”.
(b) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt
sequence in the temporary register (Note) within the CPU.
(c) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer assignment
flag (U flag) to “0” (the U flag, however does not change if the INT instruction, in software
interrupt numbers 32 through 63, is executed)
(d) Saves the content of the temporary register (Note) within the CPU in the stack area.
(e) Saves the content of the program counter (PC) in the stack area.
(f) Sets the interrupt priority level of the accepted instruction in the IPL.
Note: This register cannot be utilized by the user.
After the interrupt sequence is completed, the processor resumes executing instruc-
tions from the first address of the interrupt routine.
Figure 2.16.2 shows the sequence of returning from stop mode.
Writing “1” to CM10
(all clock stop control bit)
Operated by divided-by-8 mode
BCLK
Address
00000
Indeterminate
SP-2
SP-4
vec
vec+2
PC
Address bus
Data bus
Interrupt
SP-2
SP-4
vec
vec+2
Indeterminate
information
contents contents contents contents
Indeterminate
RD
WR
INTi
Stop mode Oscillation start-up
Interrupt sequence approximately 20 cycle (13µ sec)
(Single-chip mode, f(XIN) = 16MHz)
Note: Shown above is the case where the main clock is selected for BCLK. If the sub-clock is selected for BCLK,
the sub-clock functions as BCLK when restored from stop mode, with the main clock's divide ratio
unchanged.
Figure 2.16.2. Sequence of returning from stop mode
(6) Registers related to power control
Figure 2.16.3 shows the memory map of power control-related registers, and Figure 2.16.4 shows
power control-related registers.
System clock control register 0 (CM0)
System clock control register 1 (CM1)
000616
000716
Figure 2.16.3. Memory map of power control-related registers
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System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM0
Address
000616
When reset
4816
0
0
Bit Symbol
Bit Name
Function
R
O
W
O
Always set to “0”
Reserved bit
WAIT peripheral function
clock stop bit
0 : Do not stop in wait mode
1 : Stop in wait mode (Note 8)
O
O
O
O
CM02
CM03
CM04
CM05
CM06
CM07
Xcin-Xcout drive capacity
select bit (Note 2)
0 : LOW
1 : HIGH
0 : I/O port
1 : Xcin-Xcout generation
Port Xc select bit
O
O
O
O
O
O
Main clock (Xin-Xout)
stop bit (Note 3, 4, 5)
0 : On
1 : Off
Main clock division select
bit 0 (Note 7)
0 : CM16 and CM17 valid
1 : Divide-by-8 mode
System clock select bit
(Note 6)
0 : Xin, Xout
1 : Xcin, Xcout
O
O
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: Changes to “1” when changing to stop mode and at a reset.
Note 3: When entering power saving mode, main clock stops using this bit. When returning from
stop mode and operating in XIN, set this bit to “0”. When main clock oscillation is operating
by itself, set system clock select bit (CM07) to “1” before setting this bit to “1”.
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is
acceptable.
Note 5: If this bit is set to “1”, XOUT becomes “H”. The built-in feedback resistor remains connected,
so XIN becomes pulled up to Xout (“H”) using the feedback resistor.
Note 6: Set port Xc select bit (CM04) to “1”, and stabilize the sub clock oscillating before setting to
this bit from “0” to “1”. Do not write to both bits at the same time. Also, set the main clock
stop bit (CM05) to “0”, and stabilize the main clock oscillating before setting this bit from
“1” to “0”.
Note 7: This bit changes to “1”, when changing from high-speed/medium mode to stop mode and at
reset. When shifting from low-speed/low power dissipation mode to stop mode, the value
before stop mode is retained.
Note 8: fC32 is not included. Do not set to “1” when using low-speed or low power dissipation mode.
Note 9: When the XCIN/XCOUT is used, set ports P8
6
and P8
7
as the input ports without pull-up.
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
000716
When reset
2016
0
0 0
0
CM1
Bit Symbol
CM10
Bit Name
Function
R
O
W
O
All clock stop control bit
(Note 4)
0 : Clock on
1 : All clocks off (stop mode)
Always set to “0”
Reserved bit
CM15
O
O
O
O
O
O
0 : LOW
1 : HIGH
Xin-Xout drive capacity
select bit (Note 2)
b7 b6
Main clock division select
bit 1 (Note 3)
CM16
CM17
0 0 : No division mode
0 1 : Divide-by-2 mode
1 0 : Divide-by-4 mode
1 1 : Divide-by-16 mode
O
O
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: This bit changes to “1”, when changing from high-speed/medium mode to stop mode and at
reset. When shifting from low-speed/low power dissipation mode to stop mode, the value
before stop mode is retained.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0”.
If “1”, division mode is fixed at 8.
Note 4: If this bit is set to “1”, XOUT turns “H”, and the built-in feedback resistor is cut off. XCIN and
XCOUT turn high-impedance state.
Figure 2.16.4. Power control-related registers
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2. Power Control
2.16.2 Stop Mode Set-Up
Settings and operation for entering stop mode are described here.
Operation (1) Enables the interrupt used for returning from stop mode.
(2) Sets the interrupt enable flag (I flag) to “1”.
(3) Clearing the protection and setting all clock stop control bit to “1” stops oscillation and causes
the processor to go into stop mode.
(1) Setting interrupt to cancel stop mode
Interrupt control register
KUPIC
[Address 004116]
SiRIC(i=0,2,3)
S13BCNIC
TAiIC(i=0 to 4)
SiTIC(i=0 to 3)
RSMIC
[Address 004A16, 004216, 005516]
[Address 004316]
[Address 005416, 004516, 004716, 005716, 005916]
[Address 005316, 005116, 004F16, 004D16]
[Address 005816]
VBDIC
[Address 005C16]
INTiIC(i=0 to 2)
S1RIC
S02BCNIC
[Address 005F16, 004416, 005E16]
[Address 004816]
[Address 004916]
b7
b0
b7
b0
0
Interrupt priority level select bit
Interrupt priority level select bit
Make sure that the interrupt priority level of the
interrupt which is used to cancel the wait mode is
higher than the processor interrupt priority(IPL) of
the routine where the WAIT instruction is executed.
Make sure that the interrupt priority
level of the interrupt which is used to
cancel the wait mode is higher than
the processor interrupt priority(IPL) of
the routine where the WAIT
Reserved bit
Must always be set to “0”
instruction is executed.
Disable the interrupt not to be used for cancelling stop mode.
(2) Interrupt enable flag (I flag)
“1”
(3) Canceling protect
b7
b0
Protect register [Address 000A16]
PRCR
0
1
Enables writing to system clock control registers 0 and 1(addresses 000616 and 000716) and
frequency synthesizer registers (addresses 03DB16 to 03DF16)
1 : Write-enabled
Reserved bit
Must always be set to “0”
(3) Setting operation clock after returning from stop mode
(When operating with XIN after returning)
(When operating with XCIN after returning)
b7
0
b0
b7
1
b0
0
System clock control register 0
[Address 000616] CM0
System clock control register 0
[Address 000616] CM0
0
1
0
0
0
Reserved bit
Must always be set to “0”
Reserved bit
Must always be set to “0”
Main clock (XIN-XOUT) stop bit
On
Port XC select bit
XCIN-XCOUT generation
System clock select bit
XIN, XOUT
System clock select bit
XCIN, XCOUT
As this register becomes setting mentioned above when
operating with XIN (count source of BCLK is XIN),
the user does not need to set it again.
When operating with XCIN, set main clock (XIN-XOUT) stop bit
to “0” before setting system clock select bit to “0”. The both
bits cannot be set at the same time.
As this register becomes setting mentioned above when operating with XCIN
(count source of BCLK is XCIN), the user does not need to set it again.
When operating with XIN, set port Xc select bit to “1” before setting system clock
select bit to “1”. The both bits cannot be set at the same time.
(3) All clocks off (stop mode)
b7
b0
System clock control register [Address 000716]
CM1
0
0
0 0
1
All clock stop control bit
1 : All clocks off (stop mode)
Reserved bit
Must always be set to “0”
Insert at least four NOPs following JMP.B instruction after the instruction that sets the all clock stop control bit to “1”.
All clocks off (stop mode)
Figure 2.16.5. Example of stop mode set-up
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2.16.3 Wait Mode Set-Up
Settings and operation for entering wait mode are described here.
Operation (1) Enables the interrupt used for returning from wait mode.
(2) Sets the interrupt enable flag (I flag) to “1”.
(3) Clears the protection and changes the content of the system clock control register.
(4) Executes the WAIT instruction.
(1) Setting interrupt to cancel wait mode
Interrupt control register
KUPIC
[Address 004116
[Address 004A16, 004216, 005516
[Address 004316
[Address 005416, 004516, 004716, 005716, 005916
[Address 004616
[Address 004B16
[Address 005316, 005116, 004F16, 004D16
]
SiRIC(i=0,2,3)
S13BCNIC
TAiIC(i=0 to 4)
EP0IC
ADIC
SiTIC(i=0 to 3)
SUSPIC
]
]
]
]
]
]
[Address 005616
]
]
RSMIC
[Address 005816
SOFIC
[Address 005B16]
VBDIC
USBFIC
b0
[Address 005C16
[Address 005D16
]
]
INTiIC(i=0 to 2)
S1RIC
S02BCNIC
[Address 005F16, 004416, 005E16]
b7
b7
b0
[Address 004816
]
]
0
[Address 004916
Interrupt priority level select bit
Interrupt priority level select bit
Make sure that the interrupt priority
level of the interrupt which is used
to cancel the wait mode is higher
than the processor interrupt priority
(IPL) of the routine where the
Make sure that the interrupt priority level of the
interrupt which is used to cancel the wait mode is
higher than the processor interrupt priority (IPL) of
the routine where the WAIT instruction is executed.
Reserved bit
Must always be set to “0”
WAIT instruction is executed.
Disable the interrupt not to be used for cancelling wait mode.
(2) Interrupt enable flag (I flag)
(3) Canceling protect
“1”
b7
b0
Protect register [Address 000A16
PRCR
]
0
1
Enables writing to system clock control registers 0 and 1(addresses 000616 and 000716) and
frequency synthesizer registers (addresses 03DB16 to 03DF16
1 : Write-enabled
)
Reserved bit
Must always be set to “0”
(3) Control of CPU clock
b7
b0
b7
b0
0
System clock control register 1
[Address 000716] CM1
System clock control register 0
[Address 000616] CM0
0
0
0
0
0
Reserved bit
Must always be set to “0”
Reserved bit
Must always be set to “0”
WAIT peripheral function clock stop bit (Note 2)
0 : Do not stop f , f , f32 in wait mode
1 : Stop f , f , f32 in wait mode
Port X select bit
Main clock division select bit
b7 b6
1
8
1
8
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
C
0 : I/O port
1 : XCIN-XCOUT generation
Main clock (XIN-XOUT) stop bit
0 : On
1 : Off
Main clock division select bit 0
0 : CM16 and CM17 valid
1 : Division by 8 mode
System clock select bit (Note 1, Note 2)
0 : XIN, XOUT
1 : XCIN, XCOUT
Note 1: When switching the system clock, it is necessary to wait for the oscillation to stabilize.
Note 2: Set the WAIT peripheral function clock stop bit to “0” when the system clock select bit is “1”.
(4) WAIT instruction
Insert JMP.B instruction before the WAIT instruction and at least four NOPs after the WAIT instruction.
Wait mode
Figure 2.16.6. Example of wait mode set-up
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2.16.4 Precautions in Power Control
______
(1) The processor does not switch to stop mode when the NMI pin is at “L” level.
____________
(2) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until
main clock oscillation is stabilized.
(3) When entering wait mode, insert a JMP.B instruction before a WAIT instruction. Do not ex-
ecute any instructions which can generate a write to RAM between the JMP.B and WAIT
instructions. Disable the DMA transfers, if a DMA transfer may occur between the JMP.B and
WAIT instructions. After the WAIT instruction, insert at least 4 NOP instructions. When enter-
ing wait mode, the instruction queue roadstead the instructions following WAIT, and depend-
ing on timing, some of these may execute before the microcomputer enters wait mode.
Program example when entering wait mode
Program Example:
JMP.B
L1
I
; Insert JMP.B instruction before WAIT instruction
L1:
FSET
WAIT
NOP
NOP
NOP
NOP
;
; Enter wait mode
; More than 4 NOP instructions
(4) When entering stop mode, insert a JMP.B instruction immediately after executing an instruc-
tion which sets the CM10 bit in the CM1 register to “1”, and then insert at least 4 NOP instruc-
tions. When entering stop mode, the instruction queue reads ahead the instructions following
the instruction which sets the CM10 bit to “1” (all clock stops), and, some of these may
execute before the microcomputer enters stop mode or before the interrupt routine for return-
ing from stop mode.
Program example when entering stop mode
Program Example:
FSET
BSET
JMP.B
I
CM10
L2
; Enter stop mode
; Insert JMP.B instruction
L2:
NOP
NOP
NOP
NOP
; More than 4 NOP instructions
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(5) Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which the
count source is going to be switched must be oscillating stably. Allow a wait time in software for the oscilla-
tion to stabilize before switching over the clock.
(6) Suggestions to reduce power consumption
(a) Ports
The processor retains the state of each programmable I/O port even when it goes to wait mode or to
stop mode. A current flows in active I/O ports. A pass current flows in input ports that float. When
entering wait mode or stop mode, set non-used ports to input and stabilize the potential.
(b) Memory expansion mode and microprocessor mode
When the MCU enters wait mode while operating in memory expansion mode or microprocessor
mode, a pin functioning as part of the address or data bus retains it's state on the bus before wait
mode is entered. Shift to single-chip mode and output an arbitrary value in order to reduce current
consumption. By shifting to single-chip mode, a pin which was functioning as part of the bus be-
comes a general-purpose port and can output an arbitrary value. Set the port registers and direction
_____ ______ _____
registers after shifting to single-chip mode (this implies that any control pins (CS, WR, RD, etc.. )
being used for access of an external device be changed as well).
The same applies to stop mode.
(c) A/D converter
A current always flows in the VREF pin. When entering wait mode or stop mode, set the Vref connec-
tion bit to “0” so that no current flows into the VREF pin.
(d) Stopping peripheral functions
In wait mode, stop non-used peripheral functions using the WAIT peripheral function clock stop bit.
However, peripheral function clock fC32 does not stop so that the peripherals using fC32 do not con-
tribute to the power saving. When the MCU running in low-speed or low power dissipation mode, do
not enter WAIT mode with this bit set to “1”.
(e) External clock
When using an external clock input for the CPU clock, set the main clock stop bit to “1”. Setting the
main clock stop bit to “1” causes the XOUT pin not to operate and the power consumption goes down
(when using an external clock input, the clock signal is input regardless of the content of the main
clock stop bit).
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2. Programmable I/O Ports
2.17 Programmable I/O Ports Usage
2.17.1 Overview of the programmable I/O ports usage
Eighty-one programmable I/O ports and one input-only port are available. I/O pins also serve as I/O pins
for built-in peripheral functions.
Each port has a direction register that defines the I/O direction and also has a port register for I/O data. In
addition, each port has a pull-up control register that defines pull-up in terms of 4 bits. The input-only port
has neither direction register nor pull-up control bit.
The following is an overview of the programmable I/O ports usage:
(1) Writing to a port register
With the direction register set to output, the level of the written values from each relevant pin is output
by writing to a port register. The output level conforms to CMOS output. Port P70 and P71 are N
channel open drain. Writing to the port register, with the direction register set to input, inputs a value
to the port register, but nothing is output to the relevant pins. The output level remains floating.
In memory expansion and microprocessor mode, the contents of corresponding port and direction
_______
_______ _____ ________ ______ ________ _______
_______ __________
registers of pins A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD,
_________
HLDA and BCLK cannot be modified.
(2) Reading a port register
With the direction register set to output, reading a port register takes out the content of the port regis-
ter, not the content of the pin. With the direction register set to input, reading the port register takes out
the content of the pin.
(3) Input-only port
_______
P85 is used as the input-only port, it also serves as NMI. P85 has no direction register. Pull-up cannot
_______
_______
be set to this port. As NMI cannot be disabled, an NMI interrupt occurs if a falling edge is input to P85.
Use P85 for reading the level input at this time only.
(4) Setting pull-up
The pull-up control bit allows setting of the pull-up, in terms of 4 bits, either in use or not in use. For the
four bits chosen, pull-up is effective only in the ports whose direction register is set to input. Pull-up is
not effective in ports whose direction register is set to output.
Do not set pull-up of corresponding pin when XCIN/XCOUT is set or a port is used as A/D input.
Pull-up can be set for P0 to P3, P40 to P43, P50 to P53 in only single-chip mode. Pull-up cannot be set
for P0 to P3, P40 to P43, P50 to P53 in memory expansion and microprocessor modes. The contents
of register can be changed, but the pull-up resistance is not connected.
(5) Setting drive capacity
A normal drive and N-channel high drive for the N-channel transistor drive capacity of port P7 can be
selected. Port P7 can be configured to drive an LED by increasing the drive strength of the corre-
sponding N-channel transistor bits.
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2. Programmable I/O Ports
(6) I/O functions of built-in peripheral devices
Table 2.17.1 shows relation between ports and I/O functions of built-in peripheral devices.
Table 2.17.1. Relation between ports and I/O functions of built-in peripheral devices
Port
Internal peripheral device I/O pins
I/O pins/Serial sound interface, I2C and SPI communication pins for UART0 and UART1
Timer A0 to A3 I/O pins / I/O pins or I2C, SPI communication pins for UART2 and UART3 /
LED drive output pins
P6
P7
P80, P81
Timer A4 I/O pins
P82, P83, P84 Input pins for external interrupt
P86, P87
P90
Sub-clock oscillation circuit I/O pins
Attach/Detach control pin for USB
________
P92
SOF output pin for USB
P93
A/D trigger input pin
P10
A/D converter input pins / key-input interrupt function input pins
(7) Examples of working on non-used pins
Table 2.17.2 contains examples of working on non-used pins. There are shown here for mere ex-
amples. In practical use, make suitable changes and perform sufficient evaluation in compliance with
you application.
(a) Single-chip mode
Table 2.17.2. Examples of working on unused pins in single-chip mode
Pin name
Connection
Ports P0 to P10 (excluding P8
5
)
After setting for input mode, connect every pin to VSS or VCC via a
resistor; or after setting for output mode, leave these pins open.
(Note 1, Note 2, Note 3)
X
OUT (Note 1)
Open
Connect to VCC via a resistor (pull-up)
NMI
Connect to VCC
Connect to VSS
Open
UVCC, AVCC
AVSS, VREF, BYTE
USB D+, USB D-
LPF
Open
VbusDTCT
Open
Note 1: When an external clock is input to the XIN pin.
Note 2: If setting these pins in output mode and opening them, ports are in input mode until switched into
output mode by use of software after reset. Thus the voltage levels of the pins become unstable,
and there can be instances in which the power source current increases while the ports are in
input mode.
In view of an instance in which the contents of the direction registers change due to a runaway
generated by noise or other causes, setting the contents of the direction registers periodically by
use of software increases program reliability.
Note 3: Output “L” if port P70 and P71 are set to output mode.
Port P7 and P7 are N channel open drain output.
0
1
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(b) Memory expansion mode, microprocessor mode
Table 2.17.3. Examples of working on unused pins in memory expansion mode or microprocessor mode
Pin name
Connection
Ports P6 to P10 (excluding P8
5)
After setting for input mode, connect every pin to VSS or VCC via a
resistor; or after setting for output mode, leave these pins open.
(Note 2, Note 3, Note 4)
After setting for port input mode and setting CS1 to CS3 output enable
bit to “0”, connect to VCC via a resistor (pull-up)
P45/CS1 to P47/CS3
Open
BHE(Note 5), ALE(Note 5),
HLDA(Note 5), XOUT (Note 1),
BCLK
Connect via resistor to VCC (pull-up)
HOLD, RDY, NMI
UVCC, AVCC
Connect to VSS
Open
AVSS, VREF
Open
USB D+, USB D-
Open
Open
LPF
VbusDTCT (Note 6)
When an external clock is input to the XIN pin.
Note 1:
Note 2:
If setting these pins in output mode and opening them, ports are in input mode until switched into
output mode by use of software after reset. Thus the voltage levels of the pins become unstable,
and there can be instances in which the power source current increases while the ports are in
input mode.
In view of an instance in which the contents of the direction registers change due to a runaway
generated by noise or other causes, setting the contents of the direction registers periodically by
use of software increases program reliability.
Make wiring as short as possible (not more than 2 cm from the microcomputer's pins) in working
on non-used pins.
Note 3:
Note 4:
Note 5:
Output “L” if port P7
Port P7 and P7 are N channel open drain output.
0 and P71 are set to output mode.
0
1
When a VSS level is connected to the CNVSS pin, these pins are input ports until the processor
mode is switched by use of software after reset. Thus the voltage levels of the pins destabilize,
and there can be an increase in the power source current while these pins are input ports.
VbusDTCT pin is pulled down internaly.
Note 6:
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(8) Registers related to the programmable I/O ports
Figure 2.17.1 shows the memory map of programmable I/O ports-related registers, and Figures
2.17.2 to 2.17.5 show programmable I/O ports-related registers.
Port P0 (P0)
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
Port P1 (P1)
Port P0 direction register (PD0)
Port P1 direction register (PD1)
Port P2 (P2)
Port P3 (P3)
Port P2 direction register (PD2)
Port P3 direction register (PD3)
Port P4 (P4)
Port P5 (P5)
Port P4 direction register (PD4)
Port P5 direction register (PD5)
Port P6 (P6)
Port P7 (P7)
Port P6 direction register (PD6)
Port P7 direction register (PD7)
Port P8 (P8)
03F016
03F116
03F216
03F316
03F416
Port P9 (P9)
Port P8 direction register (PD8)
Port P9 direction register (PD9)
Port P10 (P10)
03F516
03F616
Port P10 direction register (PD10)
P7 drive capacity register (P7DR)
03FA16
03FB16
03FC16
03FD16
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
Pull-up control register 2 (PUR2)
Port control register (PCR)
03FE16
03FF16
Figure 2.17.1. Memory map of programmable I/O ports-related registers
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Port 7 drive capacity register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
P7DR
Address
03FA16
When reset
0016
Bit symbol
P7DR0
Bit name
Function
R W
P7
P7
0
1
LED drive capacity
LED drive capacity
The N-channel high drive capacity
is activated for the corresponding
bit.
P7DR1
P7DR2
P7
2
LED drive capacity
0 : Normal drive
1 : N-channel high drive
P7DR3
P7DR4
P7
P7
3
4
LED drive capacity
LED drive capacity
P7DR5
P7DR6
P7DR7
P7
P7
P7
5
6
7
LED drive capacity
LED drive capacity
LED drive capacity
Port control register
b7 b6 b5 b4 b3 b2 b1 b0
Address
03FF16
Symbol
PCR
When reset
0016
Bit Name
Bit Symbol
PCR0
Function
R
O
W
O
0 : When input port, read port
input level. When output port,
read the contents of Port P1
register.
Port P1control register
1 : Read the contents of Port P1
register through input/output port.
0 : Data read mode enabled
1 : Output disabled
O
O
O
O
OECTRL
WECTRL
AND Flash OE control bit
0 : Input disabled
AND Flash WE control bit 1 : Command/Address mode
enabled
0 : P0 & P1(0-2) GPI/O function
1 : P0 & P1(0-2) AND Flash control
AND Flash port enable bit
O
_
O
_
AFPE
function
Nothing is assigned.
Write “0” when writing to this bit. The value is “0” when read.
Figure 2.17.2. Programmable I/O ports-related registers (1)
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Port Pi direction register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
PDi (i = 0 to 7, 10)
03E216, 03E316, 03E616, 03E716, 03EA16
03EB16, 03EE16, 03EF16, 03F616
0016
Bit symbol
Bit name
Function
R W
PDi_0
PDi_1
PDi_2
PDi_3
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
0
direction register
direction register
direction register
direction register
0 : Input mode
(Functions as an input port)
1 : Output mode
1
2
(Functions as an output port)
3
(i = 0 to 7, 10)
PDi_4
PDi_5
PDi_6
PDi_7
4
direction register
direction register
direction register
direction register
Port Pi
Port Pi
Port Pi
5
6
7
Note 1: In memory expansion and microprocessor mode, the contents of
corresponding port Pi direction register of pins A
CS to CS
BCLK cannot be modified.
0
to A19, D0 to D15,
0
3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and
Port P8 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD8
Address
03F216
When reset
00X00000
2
Bit symbol
PD8_0
Bit name
Function
R W
Port P8
Port P8
Port P8
0
direction register
direction register
direction register
direction register
direction register
0 : Input mode
(Functions as an input port)
1 : Output mode
PD8_1
PD8_2
PD8_3
PD8_4
1
2
(Functions as an output port)
Port P8
Port P8
3
4
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be
indeterminate.
0 : Input mode
(Functions as an input port)
1 : Output mode
PD8_6
PD8_7
Port P8
Port P8
6
7
direction register
direction register
(Functions as an output port)
Port P9 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD9
Address
03F316
When reset
XXXX00X0
2
Bit symbol
PD9_0
Bit name
0 direction register
Function
0 : Input mode
(Functions as an input port)
1 : Output mode
R W
Port P9
(Functions as an output port)
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be
indeterminate.
0 : Input mode
(Functions as an input port)
1 : Output mode
PD9_2
PD9_3
Port P9
Port P9
2
3
direction register
direction register
(Functions as an output port)
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be
indeterminate.
Figure 2.17.3. Programmable I/O ports-related registers (2)
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2. Programmable I/O Ports
Port Pi register (Note 2)
Symbol
Pi (i = 0 to 7, 10)
Address
When reset
b7 b6 b5 b4 b3 b2 b1 b0
03E016, 03E116, 03E416, 03E516, 03E816 Indeterminate
03E916, 03EC16, 03ED16, 03F416
Function
Indeterminate
R W
Bit symbol
Bit name
register
register
register
register
register
Pi_0
Pi_1
Pi_2
Pi_3
Pi_4
Port Pi
0
1
2
3
4
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : “L” level data
Port Pi
Port Pi
Port Pi
Port Pi
1 : “H” level data (Note 1)
(i = 0 to 7, 10)
Pi_5
Pi_6
Pi_7
Port Pi
Port Pi
Port Pi
5
6
7
register
register
register
Note 1: Since P7
0
and P71 are N-channel open drain ports, the data is high-impedance.
Note 2: In memory expansion and microprocessor mode, the contents of
corresponding port Pi register of pins A to A19, D to D15, CS to CS3,
0
0
0
RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot
be modified.
Port P8 register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
P8
Address
03F016
When reset
Indeterminate
Bit symbol
P8_0
Bit name
Function
R W
Port P8
Port P8
Port P8
Port P8
Port P8
Port P8
Port P8
Port P8
0
1
2
3
4
5
6
7
register
register
register
register
register
register
register
register
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
(except for P85)
0 : “L” level data
1 : “H” level data
P8_1
P8_2
P8_3
P8_4
P8_5
P8_6
P8_7
Port P9 register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
P9
Address
03F116
When reset
Indeterminate
Bit symbol
Bit name
Function
R W
P9_0
Port P9
0
register
0 : “L” level data
1 : “H” level data
0 : Not powered
1 : Powered (Note 1)
VbusDTCT
P9_2
Vbus detect state bit
Port P9
2
register
register
0 : “L” level data
1 : “H” level data
0 : “L” level data
1 : “H” level data
P9_3
Port P93
Nothing is assigned.
Write “0” when writing to these bits. The value is indeterminate if read.
Note 1: This pin cannot be used for GPI/O. This bit reads “0” when Vbus detect is disabled.
Figure 2.17.4. Programmable I/O ports-related registers (3)
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2. Programmable I/O Ports
Pull-up control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR0
Address
03FC16
When reset
0016
Bit symbol
PU00
Bit name
P00 to P03 pull-up
Function
R W
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
PU01
PU02
PU03
PU04
PU05
PU06
PU07
P04 to P07 pull-up
P10 to P13 pull-up
P14 to P17 pull-up
P20 to P23 pull-up
P24 to P27 pull-up
P30 to P33 pull-up
P34 to P37 pull-up
1 : Pulled high
Note : In memory expansion and microprocessor mode, the content of this register
can be changed, but the pull-up resistance is not connected.
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR1
Address
03FD16
When reset
0016 (Note 2)
Bit symbol
PU10
Bit name
P40 to P43 pull-up (Note 3)
Function
R W
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
PU11
P44 to P47 pull-up
PU12
PU13
P50 to P53 pull-up (Note 3)
P54 to P57 pull-up
1 : Pulled high
PU14
PU15
PU16
PU17
P60 to P63 pull-up
P64 to P67 pull-up
P72 to P73 pull-up (Note 1)
P74 to P77 pull-up
Note 1: Since P70 and P71 are N-channel open drain ports, pull-up is not available for them.
Note 2: This register becomes 0216 when reset under the following conditions:
a) Hardware reset: when VCC is applied to the CNVSS pin.
b) Software reset: if bit 1 and bit 0 of processor mode register 0 (address 000416)
[102] or[112] before reset.
Note 3: In memory expansion and microprocessor mode, the content of these bits can be
changed, but the pull-up resistance is not connected.
Pull-up control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR2
Address
03FE16
When reset
0016
Bit symbol
PU20
Bit name
P80 to P83 pull-up
Function
R W
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
PU21
P84 to P87 pull-up
(Except P85)
1 : Pulled high
PU22
P90 to P93 pull-up
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
PU24
P100 to P103 pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
PU25
P104 to P107 pull-up
1 : Pulled high
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Figure 2.17.5. Programmable I/O ports-related registers (4)
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THIS PAGE IS BLANK FOR REASONS OF LAYOUT.
Chapter 3
Examples of Peripheral Functions Applications
M30245 Group
3. Applications
This chapter presents applications in which peripheral functions built in the M30245 are used. They are
shown here as examples. In practical use, make suitable changes and perform sufficient evaluation. For
basic use, see Chapter 2 Peripheral Functions Usage.
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3. Timer A Applications
3.1 Long-Period Timers
Overview In this process, Timer A0 and Timer A1 are connected to make a 16-bit timer with a 16-bit
prescaler. Figure 3.1.1 shows the operation timing, Figure 3.1.2 shows the connection dia-
gram, and Figures 3.1.3 and 3.1.4 show the set-up procedure.
Use the following peripheral functions:
• Timer mode of timer A
• Event counter mode of timer A
Specifications
(1) Set timer A0 to timer mode, and set timer A1 to event counter mode.
(2) Perform a count on count source f1 using timer A0 to count for 1 ms, and perform a count
on timer A0 using timer A1 to count for 1 second.
(3) Connect a 16-MHz oscillator to XIN.
Operation (1) Setting the count start flag to “1” causes the counter to begin counting. The counter of
timer A0 performs a down count on count source f1.
(2) If the counter of timer A0 underflows, the counter reloads the content of the reload register
and continues counting. At this time, the timer A0 interrupt request bit goes to “1”. The
counter of timer A1 performs a down count on underflows in timer A0.
(3) If the counter of timer A1 underflows, the counter reloads the content of the reload register
and continues counting. At this time, the timer A1 interrupt request bit goes to “1”.
l = reload register content
(1) Start count
FFFF16
l
(2) Timer A0 underflow
(3) Timer A1 underflow
000016
Time
Time
n = reload register content
Start count.
FFFF16
n
000016
Cleard “0” by software
Set to “1” by software
“1”
“0”
Timer A0 count
start flag
Set to “1” by software
“1”
“0”
Timer A1 count
start flag
“1”
“0”
Timer A0 interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleared by software
Timer A1 interrupt
request bit
“1”
“0”
Figure 3.1.1. Operation timing of long-period timers
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3. Timer AApplications
f
f
1
8
Used for timer mode
Timer A0
Timer A0 interrupt request bit
f
32
C32
f
Timer A1 interrupt request bit
Timer A1
Used for event counter mode
Figure 3.1.2. Connection diagram of long-period timers
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3. Timer A Applications
Setting timer A0
Selecting timer mode and functions
b7
b0
Timer A0 mode register [Address 039616
TA0MR
]
0
0
0
0
0
0
0
0
Selection of timer mode
Pulse output function select bit
0 : Pulse is not output (TA0OUT pin is a normal port pin)
Gate function select bit
b4 b3
0 0 : Gate function not available (TA0IN pin is a normal port pin)
0 (Must always be “0” in timer mode)
Count source select bit
b7 b6
Count source period
Count
source
b7 b6
f(XIN) : 16MH
Z
f(XcIN) : 32.768kH
62.5ns
Z
0 0 : f
1
0
0
1
1
0
1
0
1
f1
f
8
500ns
2µs
f
f
32
C32
976.56µs
Setting counter value
(b15)
b7
(b8)
b0 b7
b0
Timer A0 register [Address 038716, 038616
TA0
]
3E16
7F16
Setting timer A1
Selecting event counter mode and each function
b7
b0
Timer A1 mode register [Address 039716
TA1MR
]
0
0
0
0
0
0
0
1
Selection of event counter mode
Pulse output function select bit]
0 : Pulse is not output (TA1OUT pin is a normal port pin)
Count polarity select bit
Up/down switching cause select bit
0 : Up/down flag content
0 (Must always be “0” in event counter mode)
Count operation type select bit
0 : Reload type
When not using two-phase pulse signal processing, set this bit to “0”
Continued to the next page
Figure 3.1.3. Set-up procedure of long-period timers (1)
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3. Timer AApplications
Continued from the previous page
Setting trigger select register
b7
b0
Trigger select register [Address 038316
TRGSR
]
1
0
Timer A1 event/trigger select bit
b1 b0
1 0 : TA0 overflow is selected
Setting counter value
(b15)
b7
(b8)
b0 b7
b0
Timer A1 register [Address 038916, 038816
TA1
]
0316
E716
Setting count start flag
b7
b0
Count start flag [Address 038016
TABSR
]
1
1
Timer A0 count start flag
1 : Starts counting
Timer A1 count start flag
1 : Starts counting
Start counting
Figure 3.1.4. Set-up procedure of long-period timers (2)
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3. Timer A Applications
3.2 Variable-Period Variable-Duty PWM Output
Overview In this process, Timer A0 and A1 are used to generate variable-period, variable-duty PWM out-
put. Figure 3.2.1 shows the operation timing, Figure 3.2.2 shows the connection diagram, and
Figures 3.2.3 and 3.2.4 show the set-up procedure.
Use the following peripheral functions:
• Timer mode of timer A
• One-shot timer mode of timer A
Specifications
(1) Set timer A0 in timer mode, and set timer A1 in one-shot timer mode with pulse-output function.
(2) Set 1 ms, the PWM period, to timer A0. Set 500 µs, the width of PWM “H” pulse, to timer A1.
Both timer A0 and timer A1 use f1 for the count source.
(3) Connect a 16-MHz oscillator to XIN.
Operation (1) Setting the count start flag to “1” causes the counter of timer A0 to begin counting. The
counter of timer A0 performs a down count on count source f1.
(2) If the counter of timer A0 underflows, the counter reloads the content of the reload register
and continues counting. At this time, the timer A0 interrupt request bit goes to “1”.
(3) An underflow in timer A0 triggers the counter of timer A1 and causes it to begin counting. When
the counter of timer A1 begins counting, the output level of the TA1OUT pin goes to “H”.
(4) As soon as the count of the counter of timer A1 becomes “000016”, the output level of TA1OUT
pin goes to “L”, and the counter reloads the content of the reload register and stops counting.
At the same time, the timer A1 interrupt request bit goes to “1”.
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3. Timer AApplications
l = reload register content
(1) Timer A0 start count
FFFF16
l
(2) Timer A0 underflow
000016
Time
Time
n = reload register content
(3) Timer A1 start count
FFFF16
n
(4) Timer A1 stop count
000116
Set to “1” by software
Timer A0 count
start flag
“1”
“0”
Set to “1” by software
Timer A1 count
start flag
“1”
“0”
500µs
1ms
PWM pulse output
from TA1OUT pin
“H”
“L”
Timer A0 interrupt “1”
request bit
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Cleared to “0” when interrupt request is accepted, or cleared by software
Timer A1 interrupt
request bit
“1”
“0”
Figure 3.2.1. Operation timing of variable-period variable-duty PWM output
f
f
f
1
Used for timer mode (Set to period)
8
Timer A0
Timer A0 interrupt request bit
32
f
C32
Timer A1 interrupt request bit
Timer A1
Used for one-shot timer mode (Set to “H” width)
Figure 3.2.2. Connection diagram of variable-period variable-duty PWM output
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3. Timer A Applications
Setting timer A0
Selecting timer mode and functions
b7
b0
Timer A0 mode register [Address 039616 ]
TA0MR
0
0
0
0
0
0
0
0
Selection of timer mode
Pulse output function select bit
0 : Pulse is not output (TA0OUT pin is a normal port pin)
Gate function select bit
b4 b3
0 0 : Gate function not available (TA0IN pin is a normal port pin)
0 (Must always be “0” in timer mode)
Count source period
Count source select bit
b7 b6
Count
source
b7 b6
f(XIN) : 16MHZ f(XcIN) : 32.768kHZ
0 0 : f1
0
0
1
1
0
1
0
1
f1
62.5ns
500ns
f8
f32
fC32
2µs
976.56µs
Setting counter value
(b15)
b7
(b8)
b0 b7
b0
Timer A0 register [Address 038716, 038616]
TA0
3E16
7F16
Setting timer A1
Selecting one-shot timer mode and functions
b7
b0
Timer A1 mode register [Address 039716 ]
TA1MR
0
0
0
1
0
1
1
0
Selection of one-shot timer mode
Pulse output function select bit
1 : Pulse is output
External trigger select bit (Invalid when choosing timer's overflow as trigger)
Trigger select bit
1 : Selected by event/trigger select register
0 (Must always be “0” in one-shot timer mode)
Count source select bit
b7 b6
Count source period
f(XIN) : 16MHZ f(XcIN) : 32.768kHZ
Count
source
b7 b6
0 0 : f1
0
0
1
1
0
1
0
1
f1
62.5ns
500ns
f8
f32
fC32
2µs
976.56µs
Continued to the next page
Figure 3.2.3. Set-up procedure of variable-period variable-duty PWM output (1)
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3. Timer AApplications
Continued from the previous page
Setting trigger select register
b7
b0
Trigger select register [Address 038316
TRGSR
]
1
0
Timer A1 event/trigger select bit
b1 b0
1 0 : TA0 overflow is selected
Setting one-shot timer's time
(b15)
b7
(b8)
b0 b7
b0
Timer A1 register [Address 038916, 038816
TA1
]
1F16
4016
Setting count start flag
b7
b0
Count start flag [Address 038016
TABSR
]
1
1
Timer A0 count start flag
1 : Starts counting
Timer A1 count start flag
1 : Starts counting
Start counting
Figure 3.2.4. Set-up procedure of variable-period variable-duty PWM output (2)
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3. Timer A Applications
3.3 Buzzer Output
The timer mode is used to make the buzzer ring. Figure 3.3.1 shows the operation timing, and
Figure 3.3.2 shows the set-up procedure.
Overview
Use the following peripheral function:
• The pulse-outputting function in timer mode of timer A.
Specifications
(1) Sound a 2-kHz buzz beep by use of timer A0.
(2) Effect pull-up in the relevant port by use of a pull-up resistor. When the buzzer is off, set the
port high-impedance, and stabilize the potential resulting from pulling up.
(3) Connect a 16-MHz oscillator to XIN.
(1) The microcomputer begins performing a count on timer A0. Timer A0 has disabled interrupts.
(2) The microcomputer begins pulse output by setting the pulse output function select bit to
“Pulse output effected”. P70 changes into TA0OUT pin and outputs 2-kHz pulses.
(3) The microcomputer stops outputting pulses by setting the pulse output function select bit to
“Pulse output not effected”. P70 goes to an input pin, and the output from the pin becomes
high-impedance.
Operation
(1) Start count
(2) Buzzer output ON
(3) Buzzer output OFF
Timer A0
overflow timing
“1”
“0”
Count start flag
“1”
“0”
Pulse output
function select bit
“1”
“0”
P70 output
High-impedance
High-impedance
Figure 3.3.1. Operation timing of buzzer output
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3. Timer AApplications
Initialization of timer A0
b7
b0
Timer A0 mode register
TA0MR [Address 039616
0
0
0
0
0
0
0
0
]
Selection of timer mode
Pulse output function select bit
0 : Pulse is not output (TA0out pin is a normal port pin)
Gate function select bit
b4 b3
0 0 : Gate function not available (TA0in pin is a normal port pin)
0 (Must always be “0” in timer mode)
Count source select bit
Count source period
Count
source
b7 b6
b7 b6
f(XIN) : 16MH
Z
f(XcIN) : 32.768kH
Z
0 0 : f
1
0
0
1
1
0
1
0
1
f1
62.5ns
f8
500ns
2µs
f32
fC32
976.56µs
b15
b7
b8 b7
b0
b0
Timer A0 register
TA0 [Address 038716, 038616
0F16
9F16
]
b7
b0
Count start flag [Address 038016
TABSR
]
1
Timer A0 count start flag
1 : Starts counting
Initialization of port P7 direction register
b7
b0
Port P7 direction register [Address 03EF16
PD7
]
0
Port P70 direction register
0 : Input mode
Buzzer ON
b7
b0
Timer A0 mode register [Address 039616
TA0MR
]
1
Pulse output function select bit
1 : Pulse is output (Port P70 is TA0OUT output pin)
Buzzer OFF
b7
b0
Timer A0 mode register [Address 039616
TA0MR
]
0
Pulse output function select bit
0 : Pulse is not output
Figure 3.3.2. Set-up procedure of buzzer output
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3. Timer A Applications
3.4 Solution for External Interrupt Pins Shortage
Overview The following are solution for external interrupt pins shortage. Figure 3.4.1 shows the set-up
procedure.
Use the following peripheral function:
• Event counter mode of timer A
Specifications
(1) Inputting a falling edge to the TA0IN pin generates a timer A0 interrupt.
Operation (1) Set timer A0 to event counter mode, set timer to “0”, and set interrupt priority levels in timer A0.
(2) Inputting a falling edge to the TA0IN pin generates a timer A0 interrupt.
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3. Timer AApplications
Initialization of timer A0
b7
b0
Timer A0 mode register
TA0MR [Address 039616
0
0
0
0
0
0
0
1
]
Selection of event counter mode
Pulse output function select bit
0 : Pulse is not output (TA0out pin is a normal port pin)
Count polarity select bit
0 : Counts external signal's falling edge
Up/down switching cause select bit
0 : Up/down flag's content
0 (Must always be “0” in event counter mode)
Count operation type select bit
0 : Reload type
When not using two-phase pulse signal processing, set this bit to “0”
b15
b8 b7
b0
b0
Timer A0 register
TA0 [Address 038716, 038616
0016
0016
]
b7
b7
b0
Up/down flag [Address 038416
UDF
]
0
Timer A0 up/down flag
0 : Down count
b7
b0
Count start flag [Address 038016
TABSR
]
1
Timer A0 count start flag
1 : Starts counting
b7
b0
One shot start flag [Address 038216
ONSF
]
0
0 0
Reserved bit (Must always be “0” )
Timer A0 event/trigger select flag
b7 b6
0 0 : Input on TA0IN is selected (Note 1)
Note: Set the corresponding port direction register to “0”.
Setting interrupt priority levels in timer A0
b7
b0
Timer A0 interrupt control register [Address 005416
TA0IC
]
Interrupt control level (set a value 1 to 7)
Initialization of port P7 direction register
b7
b0
Port P7 direction register [Address 03EF16
PD7
]
0
Port P71 direction register
0 : Input mode
Setting interrupt enable flag (I flag)
Figure 3.4.1. Set-up procedure of solution for a shortage of external interrupt pins
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3. DMAC Applications
3.5 Memory to Memory DMA Transfer
Overview The following are steps for changing both source address and destination address to transfer
data from memory to another. The DMA transfer utilizes the workings that assign a higher priority
to the DMA0 transfer if transfer requests simultaneously occur in two DMA channels. Figure
3.5.1 shows the operation timing, Figure 3.5.2 shows the block diagram, and Figures 3.5.3 and
3.5.4 show the set-up procedure.
Use the following peripheral functions:
• Timer mode of timer A
• Two DMAC channels
• One-byte temporary RAM (address 080016)
Specifications
(1) Transfer the content of memory extending over 128 bytes from address F600016 to a 128-
byte area starting from address 0040016. Transfer the content every time a timer A0 interrupt
request occurs.
(2) Use DMA0 for a transfer from the source to built-in memory, and DMA1 for a transfer from
built-in memory to the destination.
Operation (1) A timer A interrupt request occurs. Though both a DMA0 transfer request and a DMA1 trans-
fer request occur simultaneously, the former is executed first.
(2) DMA0 receives a transfer request and transfers data from the source to the built-in memory.
At this time, the source address is incremented.
(3) Next, DMA1 receives a transfer request and transfers data involved from built-in memory to
the destination. At this time, the destination address is incremented.
(1) Transfer request generation
(2) Start DMA0 transferring
(3) Start DMA1 transferring
“1”
“0”
Timer A0
transfer request
Source address
F600016
Source address
080016
080016
0040016
Address bus
RD signal
Destination address
Destination address
“1”
“0”
“1”
“0”
WR signal
Instruction cycle
DMA0 operation
DMA1 operation
Note 1: The DMA0 operation and DMA1 operation are not necessarily executed in succession
due to the a cycle steal operation.
Note 2: The instruction cycle varies from instruction to instruction.
Note 3: Since the parts of the RD and WR signals shown in short-dash lines vary in step with
writing to the internal RAM, waveforms are not output to the RD and WR pins.
Figure 3.5.1. Operation timing of memory to memory DMA transfer
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3. DMAC Applications
Source area
Destination area
F600016
F600016 content
F600116 content
F600216 content
0040016
Temporary RAM
80016
0047F16
F607F16
F607F16 content
Data transfer by DMA0
Data transfer by DMA1
Figure 3.5.2. Block diagram of memory to memory DMA transfer
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3. DMAC Applications
Initialization of DMA0
b7
b0
b7
b0
DMA0 request cause select register
DM0SL [Address 03B816
DMA0 control register
DM0CON [Address 002C16
0
1
1
0
1
1
0
0
0
1
0
0
]
]
Transfer unit bit select bit
1 : 8 bits
DMA request cause select bit
b4 b3 b2 b1 b0
0 0 1 0 0 : Timer A0
Repeat transfer mode select bit
1 : Repeat transfer
Software DMA request bit
0 : Software is not generated
DMA request bit
0 : DMA not requested
DMA enable bit
1 : Enabled
Source address direction select bit
1 : Forward
Destination address direction
select bit
0 : Fixed
b23
b16b15
b8 b7
b0
b0
b0
DMA0 source pointer
SAR0
DAR0
[Address 002216, 002116, 002016]
0F16
0016
6016
0816
0016
0016
b7
b0 b7
b0
b23
b16b15
b8 b7
DMA0 destination
pointer
[Address 002616, 002516, 002416]
b7
b0 b7
b15
b0
b8 b7
0016
7F16
DMA0 transfer counter TCR0
[Address 002916, 002816]
b7
b0
Initialization of DMA1
b7
b0
b7
b0
DMA0 request cause select register
DM1SL [Address 03BA16
DMA1 control register
DM1CON [Address 003C16
1
0
1
0 1
1
0
0
0
1
0
0
]
]
Transfer unit bit select bit
1 : 8 bits
DMA request cause select bit
b4 b3 b2 b1 b0
0 0 1 0 0 : Timer A0
Repeat transfer mode select bit
1 : Repeat transfer
Software DMA request bit
DMA request bit
0 : Software is not generated
0 : DMA not requested
DMA enable bit
1 : Enabled
Source address direction select bit
0 : Fixed
Destination address direction
select bit
1 : Forward
b23
b16b15
b0 b7
b8 b7
b0
b0
DMA1 source pointer
SAR1 [Address 003216, 003116, 003016]
0016
0016
0816
0416
0016
0016
b7
b0
b23
b16 b15
b8 b7
DAR1 [Address 003616, 003516, 003416
]
DMA1 destination
pointer
b7
b0 b7
b15
b0
b8 b7
b0
0016
7F16
DMA1 transfer counter TCR1 [Address 003916, 003816
]
b7
b0
Continued to the next page
Figure 3.5.3. Set-up procedure of memory to memory DMA transfer (1)
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3. DMAC Applications
Continued from the previous page
Initialization of timer A0
b7
b0
Timer A0 mode register
TA0MR [Address 039616
0
0
0
0
0
0
0
0
]
Selection of timer mode
Pulse output function select bit
0 : Pulse is not output (TA0OUT pin is a normal port pin)
Gate function select bit
b4 b3
0 0 : Gate function not available (TA0IN pin is a normal port pin)
0 (Must always be “0” in timer mode)
Count source period
f(XcIN) : 32.768kH
62.5ns
Count source select bit
Count
source
b7 b6
b7 b6
f(XIN) : 16MH
Z
Z
0 0 : f
1
0
0
1
1
0
1
0
1
f1
f
8
500ns
2µs
f
f
32
C32
976.56µs
b15
b7
b8 b7
b0
b0
Timer A0 register
TA0 [Address 0387, 038616
3E16
0F16
]
b7
b0
Count start flag [Address 038016
TABSR
]
1
Timer A0 count start flag
1 : Starts counting
Figure 3.5.4. Set-up procedure of memory to memory DMA transfer (2)
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M30245 Group
3. CRC Snoop Function Applications
3.6 CRC Calculation SFR Access Snoop Function in Clock Synchronous Serial Data Transmit
The M30245 group, by use of DMAC, transfers data from the internal RAM to the UART1 and the
result is transferred to the UART1 by use of SFR access snoop function. The block diagram is
shown in Figure 3.6.1 and the setting routine is shown in Figure 3.6.2 to Figure 3.6.4.
The peripheral functions to be used are as follows:
• DMAC 1 Channel
Overview
• Internal RAM (address 0040016) 512 bytes
• UART1 (Clock synchronous serial I/O mode)
• CRC calculation circuit
• SFR access snoop function
Specifications
(1) Data transfer is performed starting at address 0040016 from the area with 512 bytes to the
UART1. Data are transferred from area between the address 0040016 and the 512nd byte to
the UART1. Transfer is executed every time 1 byte of serial transmit is completed.
(2) Use the DMA0 to transfer data from the internal RAM to the UART1. Select the UART1
transmit to the DMA0 request factor. Select the single transfer mode and set the DMA0
transfer counter to 511 bytes (512-1).
(3) Set the CRC calculation circuit to the CRC-CCITT and set CRC snoop address register to the
address of UART1 transmit buffer register (write snoop).
(4) On completing the DMA, 2-byte data of CRC data register (calculation result) are transferred
to the UART1 and operation is completed.
Operation
(1) Initialize the UART1 related registers.
(2) Initialize the DMA0 related registers in DMA disable state.
(3) Set the DMA0 transfer counter to the transfer data consisting of 511 bytes (in this case, 8-bit
transfer).
(4) Initialize the CRC calculation circuit and the SFR access snoop function.
(5) Set the software DMA request bit of DMA0 to “1”. At this time, 1st byte data are transferred
from RAM to the transmit buffer of the UART1. Simultaneously, the transfer source address
is incremented and the content of the transfer counter is down-counted. The transferred data
are automatically written in CRC input register by the SFR access snoop function.
(6) When the transmit buffer of the UART1 becomes writable state, the DMA transfer request is
occurred by the UART1. At this time, the next data are transferred from RAM to the transmit
buffer of the UART1. Simultaneously, the transfer source address is incremented and the
content of the transfer counter is down-counted. The transferred data are automatically writ-
ten in CRC input register by the SFR access snoop function.
(7) As a result of repetition of the above (6), when the DMA0 transfer counter underflow, DMA
enable bit is set to “0” to complete the DMA0 transfer. Simultaneously, the DMA0 interrupt
request occurs. When the DMA0 interrupt request is detected, CRC data register (2 bytes) is
read, it is transferred to the UART1 transmit buffer sequentially.
Rev.2.00 Oct 16, 2006 page 311 of 354
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M30245 Group
3. CRC Snoop Function Applications
M30245
Source area
Contents of 1st byte
transmission data
0040016
CRC input register
Contents of 2nd byte
transmission data
Contents of 3rd byte
transmission data
Snoop the address of
UART1 transmit buffer register
UART1 transmit
buffer register
Transmission
data
Contents of 512th byte
transmission data
005FF16
DMA0 transfer
Figure 3.6.1. Block diagram of DMA transfer from RAM to UART and SFR snooping function
Rev.2.00 Oct 16, 2006 page 312 of 354
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M30245 Group
3. CRC Snoop Function Applications
ꢀ Initialization of UART1
(See “2.3.2 Operation of Serial I/O (transmission in clock synchronous serial I/O mode” for detail.)
ꢀ Enable UART1 transmit
b7
b0
UART1 transmit / receive control register 1
1
U1C1 [Address 036D16
]
Transmit enable bit
1 : Transmit enable
ꢀ Disable DMA0
b7
b0
DMA0 control register
0
DM0CON
DMA enable bit
0 : Disabled
[Address 002C16]
ꢀ Setting DMA0 cause select register
b7
b0
DMA0 cause select register
DM0SL [Address 03B816
0
0 1 1 1
0
]
DMA request cause select bits
0 1 1 1 0 : UART1 transmit
Nothing is assigned. Write “0” when writing to these bits.
Software DMA request bit
0 : Not occurred
ꢀ Setting DMA0 control register
b7
b0
DMA0 control register
DM0CON [Address 002C16
Transfer unit select bit
1 : 8 bits
0
1 0 0 0
1
]
Repeat transfer mode select bit
0 : Single transfer
DMA request bit
0 : DMA not requested
DMA enable bit
0 : Disabled
Source address direction select bit
1 : Forward
Destination address direction select bit
0 : Fixed
ꢀ Setting source pointer(internal RAM address) and destination pointer (UART1 transmit buffer)
b23
b16b15
b8 b7
b0
b19
DMA0 source pointer
SAR0 [Address 002216 to 002016
0 0 0 0
0016
0416
]
Stores the internal RAM address (040016
)
Nothing is assigned. Write “0” when writing to these bits.
b23
b16b15
b8 b7
b0
b19
DMA0 destination pointer
DAR0 [Address 002616 to 002416
0 0 0 0
6A16
0316
]
Stores the address of UART1 transmit buffer register (036A16
)
Nothing is assigned. Write “0” when writing to these bits.
Continued to the next page
Figure 3.6.2. Setting routine (1) of DMA transfer from RAM to UART using SFR snooping function
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3. CRC Snoop Function Applications
Continued from the previous page
ꢀ Enable DMA0
b7
b0
DMA0 control register
DM0CON [Address 002C16
1
0
]
DMA request bit
0 : DMA not requested
DMA enable bit
1 : Enabled
ꢀ Clear CRC data register
b8 b7
b15
b0
CRC data register
CRCD [Address 03BD16, 03BC16
0016
0016
]
ꢀ Setting CRC mode register
b7
b0
CRC mode register
CRCMR [Address 03B616
1
0
]
CRC mode polynomial selection bit
0 : CRC-CCITT
CRC mode selection bit 0
1 : MSB first mode
ꢀ Setting CRC snoop address register
b8 b7
b15
b0
CRC snoop address register
CRCSRA [Address 03B516, 03B416
0
036A16
1
]
SFR snoop address bit
Set address: 036A16 (UART1 transmit buffer register)
CRCSAR Read
0 : Disabled
CRCSAR Write
1 : Enabled
ꢀ Set Software DMA request bit to “1” in the status that DMA enable bit is “1”
b7
b0
DMA0 cause select register
DM0SL [Address 03B816
1
]
Software DMA request bit
1 : Occurred
Transfer to CRC input register at the same
time by SFR snoop function
1st byte DMA transfer
Continued to the next page
Figure 3.6.3. Setting routine (2) of DMA transfer from RAM to UART using SFR snooping function
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3. CRC Snoop Function Applications
Continued from the previous page
ꢀ The DMA transfer request from the 2nd byte on is occurred
when DMA enable bit = “1” and the UART1 is transmit request state.
Transfer of the data to
CRC input register by
the SFR snoop function.
DMA0 transfer from the 2nd byte on
DMA enable bit is set to “0”
by underflow of the DMA0 transfer counter.
ꢀ Completion of the DMA0 transfer and occurrence of the DMA0 interrupt request.
ꢀ Transfer of the 16-bit calculation result which is stored in CRC data register
to UART1 transmit buffer register every 1 byte.
ꢀ To subsequently start the DMA0 transfer:
Disable the DMA0 once and set the DMA0 related registers once again.
Figure 3.6.4. Setting routine (3) of DMA transfer from RAM to UART using SFR snooping function
Rev.2.00 Oct 16, 2006 page 315 of 354
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M30245 Group
3. USB Applications
3.7 Transfer from USB FIFO to Serial Sound Interface
Overview
The M30245 group, by use of DMAC, transfers data from the USB endpoint 1 OUT FIFO to SS
interface 1 transmit buffer register and fetches one packet data.
The block diagram is shown in Figure 3.7.1 and the setting routine is shown in Figure 3.7.2 to
Figure 3.7.4.
The peripheral functions to be used are as follows:
• DMAC 1 channel
• USB endpoint 1 OUT (Receive)
• Serial sound interface 1
Specifications
(1) Receive packet data of the endpoint 1 OUT FIFO are transferred to SS interface 1 transmit
buffer register. Transfer is executed every time the DMA transfer factor of the serial sound
interface 1 occurs.
(2) Use the DMA0 to transfer data from the endpoint 1 OUT FIFO to SS interface 1 transmit buffer
register. Select the serial sound interface 1 transmit to the DMA0 request factor. Select the
single transfer mode and set the DMA0 transfer counter to 1/2 ꢀ (the data count of one
packet received with endpoint 1 OUT) –1.
(3) Set the endpoint 1 OUT maximum packet size to 288 bytes (when sampling 48KHz/ 24-bit/
stereo) and disable the AUTO_CLR function. The data count of receive packet of endpoint 1
(endpoint 1 OUT write count register) is set to 288 bytes. Endpoint 1 OUT is used in isochro-
nous transfer.
(4) On completing the DMA0 transfer, fetch of one packet data from the endpoint 1 OUT FIFO is
completed by setting CLR_OUT_BUF_RDY bit of endpoint 1 to “1”.
Operation
(1) Initialize the DMA0 related registers in the state which DMA is disabled and USB DMA0
request register is not selected (in this case, 16-bit transfer).
(2) When the OUT_BUF_STS1 flag of endpoint 1 is set to “1” and packet data receive has been
detected, set the DMA0 transfer counter to the 1/2 ꢀ (the data count of receive one packet) –1
(in this application example, 143 value is set).
(3) Set DMA enable bit of DMA0CON to “1” (DMA0 is enabled). Then, the DMA0 transfer request
from the serial sound interface occurs.
(4) When the transfer request is received, the DMA0 transfers the 1st word (16-bit) data from the
endpoint 1 OUT FIFO to the serial sound interface 1. Simultaneously, the content of the
transfer counter is down-counted. Then, the DMA0 transfer request from the serial sound
interface occurs .
(5) As a result of repetition of the above (4), when the DMA0 transfer counter underflow, DMA
enable bit is set to “0” to complete the DMA0 transfer. Simultaneously, the DMA0 interrupt
request occurs. When the DMA0 interrupt request is detected, set CLR_OUT_BUF_RDY bit
of endpoint 1 OUT to “1”.
Rev.2.00 Oct 16, 2006 page 316 of 354
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M30245 Group
3. USB Applications
M30245
DMA0 transfer
USB endpoint 1
OUT FIFO
USB transfer
Serial Sound Interface 1
transmit buffer register
Host CPU
DAC
Figure 3.7.1. Block diagram of DMA transfer from USB FIFO to serial sound interface
Rev.2.00 Oct 16, 2006 page 317 of 354
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M30245 Group
3. USB Applications
ꢀ Initialization USB function unit (See “2.8 USB function” for detail)
Setting USB-related registers
ꢀ Enable USB endpoint 1 OUT
(b15)
b7
(b8)
b0 b7
b0
USB endpoint enable register
USBEPEN [Address 028E16
1
0
0
0
0
0
0
0 0 0
0
0
]
EP1 OUT enable bit
1 : Enabled
(b15)
b7
(b8)
b0 b7
b0
USB Endpoint 1 OUT control and status register
0
EP1OCS [Address 02B616
]
AUTO_CLR bit
0 : AUTO_CLR disabled
(b15)
b7
(b8)
b0 b7
b0
USB Endpoint 1 OUT MAXP register
0
0
0
0
0 0 1 0
0
1
0 0
0
0
0
EP1OMP [Address 02B816
]
Set to 12016 (288 bytes)
ꢀ Initialization serial sound interface (See “2.6 Serial sound interface” for detail)
ꢀ Disable DMA0
b7
b0
DMA0 control register
DM0CON [Address 002C16
0
]
DMA enable bit
0 : Disabled
ꢀ Setting DMA0 cause select register
b7
b0
DMA0 cause select register
DM0SL [Address 03B816
0
0
1
1
1
0
]
DMA request cause select bits
0 1 1 1 0 : SSI1 transmit
Nothing is assigned. Write “0” when writing to these bits.
Software DMA request bit
0 : Not occurred
ꢀ Set USB DMA0 request register [address 029016] to “000016” (not selected)
Continued to the next page
Figure 3.7.2. Setting routine (1) of DMA transfer from USB OUT FIFO to serial sound interface
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3. USB Applications
Continued from the previous page
ꢀ Setting DMA0 control register
b7
b0
DMA0 control register
DM0CON [Address 002C16
0
0 0 0 0
0
]
Transfer unit select bit
0 : 16 bits
Repeat transfer mode select bit
0 : Single transfer
DMA request bit
0 : DMA not requested
DMA enable bit
0 : Disabled
Source address direction select bit
0 : Fixed
Destination address direction select bit
0 : Fixed
ꢀ Setting source pointer(endpoint 1 OUT FIFO data register) and destination pointer
(SS interface 1 transmit buffer register)
b23
b16b15
b8 b7
b0
b19
DMA0 source pointer
SAR0 [Address 002216 to 002016
0 0 0 0
0216
E616
7416
]
Stores the endpoint 1 OUT FIFO (Address 02E616
Nothing is assigned. Write “0” when writing to these bits.
)
b23
b16b15
b8 b7
b0
b19
DMA0 destination pointer
DAR0 [Address 002616 to 002416
0 0 0 0
0316
]
Stores the SS interface 1 transmit register (Address 037416
)
Nothing is assigned. Write “0” when writing to these bits.
ꢀ Checking that OUT_BUF_STS1 flag is “1” and setting the number of the transfer bytes (Note)
(b15)
b7
(b8)
b0 b7
b0
DMA0 transfer counter
TCR0 [Address 002916, 002816
0016
8F16
]
Note: Set 1/2 ꢀ (the value of Endpoint 1 OUT write count register) –1.
ꢀ Enable serial sound interface 1
b7
b0
Serial Sound Interface 1 mode register 0
SSI1MR0 [Address 037016
1
]
Serial Sound Interface enable bit
1 : Enabled
ꢀ Enable DMA0
b7
b0
DMA0 control register
DM0CON [Address 002C16
DMA request bit
1
0
]
0 : DMA not requested
DMA enable bit
1 : Enabled
Continued to the next page
Figure 3.7.3. Setting routine (2) of DMA transfer from USB OUT FIFO to serial sound interface
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3. USB Applications
Continued from the previous page
ꢀ The DMA request of the serial sound interface 1 transmit is occurred
when DMA enable bit = “1” and the OUT_BUF_STS1 flag of endpoint 1 = “1”.
DMA0 transfer of the 1st word
ꢀ DMA request from the 2nd byte on is occurred
when DMA enable bit = “1” and the OUT_BUF_STS1 flag of endpoint 1 = “1”.
DMA0 transfer from the 2nd word on
DMA enable bit is set to "0"
by underflow of the DMA0 transfer counter.
ꢀ Completion of the DMA0 transfer and occurrence of the DMA0 interrupt request.
ꢀ Setting CLR_OUT_BUF_RDY bit of endpoint 1 to “1” and completion of one receive
packet data fetch after confirming of the DMA0 interrupt request.
(b15)
b7
(b8)
b0 b7
b0
USB Endpoint 1 OUT Control and Status register
EP1OCS [Address 02B616
1
0 0
]
CLR_OUT_BUF_RDY bit
1 : Data set unloaded from the OUT FIFO
(updates OUT_BUF_STS1 and OUT_BUF_STS0)
ꢀ To subsequently start DMA0 transfer:
Disable DMA0 once and set the DMA0 related registers again.
Figure 3.7.4. Setting routine (3) of DMA transfer from USB OUT FIFO to serial sound interface
Rev.2.00 Oct 16, 2006 page 320 of 354
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M30245 Group
3. Controlling Power Applications
3.8 Controlling Power Using Stop Mode
Overview The following are steps for controlling power using stop mode. Figure 3.8.1 shows the operation
timing, Figure 3.8.2 shows an example of circuit, and Figures 3.8.3 and 3.8.4 show the set-up
procedure.
Use the following peripheral functions:
• Key-input interrupts
• Stop mode
• Pull-up function
This example is not performed USB power control. Please refer section 2.8.4 for the power
control of USB related.
Specifications
_____
(1) Use P00 through P03 for the scan output pins of a key matrix. Use the input pins (KI0 through
_____
KI3) of the key-input interrupt function for the key-input reading pins. The pull-up function is
also used.
(2) If a key-input interrupt request occurs, clear the stop mode and read a key.
_____
_____
Operation (1) Enable a key-input interrupt and set the pull-up function to pins KI0 through KI3. Change the
output of P00 through P03 to “L” and enter stop mode.
_____
_____
(2) If a key is pressed, “L” is input to one of pins KI0 through KI3 to clear stop mode. A key-input
interrupt occurs to execute the key-input interrupt handling routine.
(3) Sequentially set P00 through P03 to “L” to determine which key was pressed.
(4) When the process to determine the key pressed is completed, change the output from P00
through P03 to “L” again and enter stop mode.
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3. Controlling Power Applications
(1) Shift to stop mode
(2) Cancel a stop mode
(3) Key scan
Key matrix scan
(4) Shift to stop mode
P00 output
P01 output
P02 output
P03 output
P100 to P103 input
Key input
Key ON
Key ON
Key OFF
Key OFF
Key input
interrupt processing
CPU clock
Stop mode
Stop mode
Figure 3.8.1. Operation timing of controlling power using stop mode
VREF
P00
P0
P0
P0
1
2
3
I/O port
P10
0
1
/ KI
0
1
P10
/ KI
P10
2
3
/ KI
2
3
P10
/ KI
Figure 3.8.2. Example of circuit of controling power using stop mode
Rev.2.00 Oct 16, 2006 page 322 of 354
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M30245 Group
3. Controlling Power Applications
Main
Initial condition
b7
Pull-up control register 2
Port P0 direction register
b0
b7
b0
[Address 03FE16
PUR2
]
[Address 03E216
PD0
]
1
1
1
1
1
Key scan output port
P100 to P103 pulled high
b7
b7
b0 Port P10 direction register
[Address 03F616
PD0
]
0
0
0
0
0
0
0
Key input interrupt control register
b7
b0
[Address 004116
]
Key scan input port
b0 Port P0 register
0
0
1
KUPIC
Interrupt priority level select bit
Set higher value than the present IPL
[Address 03E016
P0
]
0
Key scan data
Processor interrupt priority level (IPL) = 0
Interrupt enable flag (I) =0
Setting interrupt except stop mode cancel
I
nterrupt control register SiRIC(i=0,2,3) [Address 004A16, 004216, 005516
S13BCNIC [Address 004316
TAiIC(i=0 to 4) [Address 005416, 004516, 004716, 005716, 005916
]
]
]
EP0IC
ADIC
[Address 004616
[Address 004B16
]
]
DMiIC(i=0 to 3) [Address 004C16, 004E16, 005016, 005216
SiTIC(i=0 to 3) [Address 005316, 005116, 004F16, 004D16
]
]
SUSPIC
RSMIC
RSTIC
SOFIC
VBDIC
USBFIC
[Address 005616
[Address 005816
[Address 005A16
[Address 005B16
[Address 005C16
[Address 005D16
]
]
]
]
]
]
INTiIC(i=0 to 2) [Address 005F16, 004416, 005E16
]
b7
b0
b7
b0
S1RIC
S02BCNIC
[Address 004816
[Address 004916
]
]
0
0
0
0
0
0
0
Interrupt priority level select bit
000 : Interrupt disabled
Interrupt priority level select bit
000 : Interrupt disabled
Reserved bit
Must always be set to “0”
Canceling protect
b7
b0
Protect register [Address 000A16
PRCR
]
0
1
Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716
)
and frequency synthesizer registers (addresses 03DB16 to 03DF16
1 : Write-enabled
)
Setting operation clock after returning from stop mode
(When operating with XIN after returning)
(When operating with XCIN after returning)
System clock control register 0
b7
b0
0
b7
1
b0
0
System clock control register 0
1
0
0
0
0
CM0 [Address 000616
]
CM0 [Address 000616
]
Reserved bit
Reserved bit
Must always be set to “0”
Main clock (XIN-XOUT) stop bit
On
Must always be set to “0”
Port X select bit
C
X
CIN-XCOUT generation
System clock select bit
X
IN, XOUT
System clock select bit
X
CIN, XCOUT
As this register becomes setting mentioned above when
operating with XIN (count source of BCLK is XIN),
the user does not need to set it again.
When operating with XCIN, set main clock (XIN-XOUT) stop bit
to “0” before setting system clock select bit to “0”. The both
bits cannot be set at the same time.
As this register becomes setting mentioned above when operating with XCIN
(count source of BCLK is XCIN), the user does not need to set it again.
When operating with XIN, set port Xc select bit to “1” before setting system
clock select bit to “1”. The both bits cannot be set at the same time.
Continued to the next page
Figure 3.8.3. Set-up procedure of controlling power using stop mode (1)
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3. Controlling Power Applications
Continued from the previous page
Interrupt enable flag (I flag)
“1”
All clocks off (stop mode)
b7
b0
System clock control register 1 [Address 000716
CM1
]
0
0
0
0
1
All clock stop control bit
1 : All clocks off (stop mode)
Reserved bit
Must always be set to “0”
NOP instruction
X 4
Key input interrupt request generation
Insert at least four NOPs following JMP.B instruction after
the instruction that sets the all clock stop control bit to “1”.
Key-input interrupt
Store the registers
Key matrix scan
b7
b0
Port P0 register [Address 03E016
]
P0
Key scan data
1110, 1101, 1011, 0111
Decision of key-input data
b7
b0
Port P0 register [Address 03E016
P0
]
0
0
0
0
Key scan data
Restore the registers
REIT instruction
Figure 3.8.4. Set-up procedure of controlling power using stop mode (2)
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3. Controlling Power Applications
3.9 Controlling Power Using Wait Mode
Overview The following are steps for controling power using wait mode. Figure 3.9.1 shows the operation
timing, and Figures 3.9.2 to 3.9.4 show the set-up procedure.
Use the following peripheral functions:
• Timer mode of timer A
• Wait mode
A flag named “F-WIT” is used in the set-up procedure. The purpose of this flag is to decide
whether or not to clear wait mode. If F_WIT = “1” in the main program, the wait mode is entered;
if F_WIT = “0”, the wait mode is cleared.
Specifications
(1) Connect a 32.768-kHz oscillator to XCIN to serve as the timer count source. As interrupts
occur every one second, which is a count the timer reaches, the controller returns from wait
mode and count the clock using a program.
________
(2) Clear wait mode if a INT0 interrupt request occurs.
Operation (1) Switch the system clock from XIN to XCIN to get low-speed mode.
_______
(2) Stop XIN and enter wait mode. In this instance, enable the timer A2 interrupt and the INT0 interrupt.
(3) When a timer A2 interrupt request occurs (at 1-second intervals), start supplying the BCLK
from XCIN. At this time, count the clock within the routine that handles the timer A2 interrupts
and enter wait mode again.
_______
(4) If a INT0 interrupt occurs, start supplying the BCLK from XCIN. Start the XIN oscillation within
_______
the INT0 interrupt, and switch the system clock to XIN.
(1) Shift to low-speed mode
(2) Stop XIN
(3) Timer A2 interrupt
(4) INT
0
interrupt
X
OUT
X
CIN
Timer A2 overflow
Timer A2
interrupt processing
“H”
“L”
INT0
BCLK
High-speed
Low-speed
High-speed
Low-speed
Low-speed
Low-speed
Figure 3.9.1. Operation timing of controling power using wait mode
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3. Controlling Power Applications
Main
Initial condition
b7
b0
System clock control register 0 [Address 000616
CM0
]
0
0
1
0
0
0
Reserved bit
Must always be set to “0”
WAIT peripheral function clock stop bit
0 : Do not stop peripheral function clock in wait mode
CIN-XCOUT drive capacity select bit
X
Port XC select bit
1 : Functions as XCIN-XCOUT oscillator
Main clock (XIN-XOUT) stop bit
0 : Oscillating
Main clock divide ratio select bit 0
System clock select bit
0 : XIN-XOUT
b7
b0
Timer A2 mode register [Address 039816
TA2MR
]
1
1
0
0
Operation mode select bit
b1 b0
0 0 : Timer mode
Count source select bit
b7 b6
1 1 : fC32 (f(XCIN) divided by 32)
b15
b8 b7
b0
Timer A2 register [Address 038A16, 038B16
TA2
]
0316
FF16
b7
b0
Clock prescaler reset flag [Address 038116
CPSRF
]
1
Rrescaler is reset
b7
b7
b7
b0
Count start flag [Address 038016
TABSR
]
1
0
TA2 start counting
b0
Timer A2 interrupt control register [Address 004716
TA2IC
]
0
1
TA2 interrupt priority level
b0
INT0 interrupt control register [Address 005F16
INT0IC
]
0
0
0
1
INT0 interrupt priority level
Processor interrupt priority level (IPL) = 0
Interrupt enable flag (I) = 0
Setting interrupt except clearing wait mode
I
nterrupt control register
KUPIC [Address 004116
SiRIC(i=0,2,3) [Address 004A16, 004216, 005516
S13BCNIC [Address 004316
TAiIC(i=0,1,3,4) [Address 005416, 004516, 005716, 005916] RSMIC
ADIC
DMiIC(i=0 to 3) [Address 004C16, 004E16, 005016, 005216
SiTIC(i=0 to 3) [Address 005316, 005116, 004F16, 004D16
SUSPIC [Address 005616
[Address 005816
[Address 005A16
[Address 005B16
[Address 005C16
[Address 005D16
[Address 004B16]
]
]
]
]
]
]
]
]
]
]
]
EP0IC
[Address 004616
]
RSTIC
SOFIC
VBDIC
USBFIC
b7
b0
0
0
0
Interrupt priority level select bit
b2 b1 b0
0 0 0 : Interrupt disabled
INTiIC(i=1,2)
S1RIC
S02BCNIC
[Address 004416, 005E16]
b7
b0
[Address 004816
]
]
0
0
0
0
[Address 004916
Interrupt priority level select bit
000 : Interrupt disabled
Reserved bit
Must always be set to “0”
Continued to the next page
Figure 3.9.2. Set-up procedure of controlling power using wait mode (1)
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M30245 Group
3. Controlling Power Applications
Continued from the previous page
Canceling protect
b7
b0
Protect register [Address 000A16
PRCR
]
1
Enables writing to system clock control registers 0 and 1 (address 000616 and 000716
)
1 : write-enabled
Switching system clock
b7
b0
System clock control register 0 [Address 000616
CM0
]
1
0
0
Reserved bit
Must always be set to “0”
System clock select bit
1 : XCIN-XCOUT
Stopping main clock
b7
b0
System clock control register 0 [Address 000616
CM0
]
1
0
0
Reserved bit
Must always be set to “0”
Main clock (XIN-XOUT) stop bit
1 : Off
[F_WIT] = 1
Interrupt enable flag (I flag)
“1”
JMP.B instruction
WAIT instruction
NOP instruction X 4
INT0 interrupt request generated
TA2 interrupt request generated
=
[F_WIT] : 1
≠
Starting main clock oscillator
b7
b0
System clock control register 0 [Address 000616
CM0
]
0
0
0
Reserved bit
Must always be set to “0”
Main clock (XIN-XOUT) stop bit
0 : On
Wait until the main clock has stabilized
Switching system clock
b7
b0
System clock control register 0 [Address 000616
CM0
]
0
0
0
Reserved bit
Must always be set to “0”
System clock select bit
0 : XIN-XOUT
Figure 3.9.3. Set-up procedure of controlling power using wait mode (2)
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3. Controlling Power Applications
INT0 interrupt
Store the registers
[F_WIT] = 0
Restore the registers
REIT instruction
Timer A2 interrupt
Store the registers
Counting clock
Restore the registers
REIT instruction
Figure 3.9.4. Set-up procedure of controlling power using wait mode (3)
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Chapter 4
External Buses
M30245 Group
4. External Buses
4.1 Overview of External Buses
Memory and I/O external expansion can be connected to microcomputer easily by using external buses.
When memory expansion mode or microprocessor mode is selected for processor mode, some of the pins
function as the address bus, the data bus, and as control signals and this makes the external buses be able
to operate.
When accessing an external area, 8-bit data bus width or 16-bit data bus width can be selected, based on
the BYTE pin level. 16-bit width is used to access an internal area,regardless of the level of the BYTE pin.
Fix the BYTE pin either to “H” or “L” level. 8-bit and 16-bit data bus widths cannot be used together in an
external area.
Make sure the BYTE pin is fixed to “H” level when an 8-bit bus width is selected and “L” level when a 16-bit
bus width is selected.
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4. External Buses
4.2 Data Access
4.2.1 Data Bus Width
If the voltage level input to the BYTE pin is “H”, the external data bus width becomes 8 bits, and P10 (/D8)
through P17 (/D15) can be used as I/O ports (Figure 4.2.1).
If the voltage level input to the BYTE pin is “L”, the external data bus width becomes 16 bits, and P00 (/D0)
through P07 (/D7), and P10 (/D8) through P17 (/D15) operate as a data bus (D0 through D15) (Figure 4.2.1).
Bus width :8-bit (BYTE = “H”)
Microcomputer
External device
P0
P1
0
0
to P0
to P1
7
7
Data bus D0 to D7
I/O port
P2
P3
0
0
to P2
to P3
7
7
Address bus A0 to A15
P4
P4
P5
P5
0
4
0
3
to P4
to P4
to P5
to P5
3
7
2
7
Address bus A16 to A19 (Note 1)
Chip select CS0 to CS3 (Note 2)
RD,WRL,WRH / RD,BHE,WR (Note 3)
BCLK, HLDA, HOLD, ALE, RDY
Bus width :16-bit (BYTE = “L”)
Microcomputer
External device
P0
P1
0
0
to P0
to P1
7
7
Data bus D0 to D7
Data bus D8 to D15
P2
P3
0
0
to P2
to P3
7
7
Address bus A0 to A15
P4
P4
0
4
to P4
to P4
3
7
Address bus A16 to A19 (Note 1)
Chip select CS0 to CS3 (Note 2)
RD,WRL,WRH / RD,BHE,WR (Note 3)
BCLK, HLDA, HOLD, ALE, RDY
P5
P5
0
3
to P5
to P5
2
7
Note 1: Can be switched to I/O port using the port P4
0
to P4
3
function select bits of processor mode register 0 (address 000416).
through CS become input ports.
Note 2: When reset,only CS outputs a chip select signal. CS
0
1
3
I/O ports can be switched using the CSi output enable bit of the chip select control register (address 000816).
Note 3: The feature can be switched using the R/W mode select bit of processor mode register 0 (address 000416).
Figure 4.2.1. Level of BYTE pin and external data bus width
Rev.2.00 Oct 16, 2006 page 331 of 354
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4. External Buses
4.2.2 Chip Selects and Address Bus
______
______
Chip selects (P44/CS0 through P47/CS3) are output in areas resulting from dividing a 1-M byte
memory space into four. To use the chip select, the chip select output must be enabled by setting the
chip select control register. Figure 4.2.2 shows addresses in which chip selects become active (“L”).
Since the extent of the internal area and the external area in memory expansion mode is different from
_______
those in microprocessor mode, there is a difference between areas for which CS0 is output. When an
internal ROM/RAM area is being accessed, no chip select is output, and the address bus does not
change (the address of the external area that was accessed previously is held).
0000016
SFR area
Address YYYYY16
E000016
Part number
Address XXXXX16
02BFF16
003FF16
0040016
M30245FCGP
M30245MC-XXXGP
M30245M8-XXXGP
02BFF16
017FF16
E000016
F000016
Internal RAM area
XXXXX16
Internal reserved area
03FFF16
0400016
CS3
CS3
0400016 to 07FFF16 (16K)
0400016 to 07FFF16 (16K)
07FFF16
0800016
CS2
CS2
0800016 to 27FFF16 (128K)
0800016 to 27FFF16 (128K)
27FFF16
2800016
CS1
CS1
2800016 to 2FFFF16 (32K)
2800016 to 2FFFF16 (32K)
2FFFF16
3000016
CS0
3000016 to CFFFF16 (640K)
CFFFF16
D000016
CS0
3000016 to FFFFF16 (832K)
Internal reserved area
Internal ROM area
YYYYY16
FFFFF16
Memory expansion mode
Memory expansion mode
Figure 4.2.2. Addresses in which chip selects turn active (“L”)
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4. External Buses
Chip select control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CSR
Address
000816
When reset
0116
R W
Function
Bit symbol
Bit name
CS0
CS0 output enable bit
CS1 output enable bit
CS2 output enable bit
CS3 output enable bit
CS0 wait bit
0 : Chip select output disabled
(Normal port pin)
1 : Chip select output enabled
CS1
CS2
CS3
CS0W
CS1W
CS2W
CS3W
0 : Wait state inserted
1 : No wait state
CS1 wait bit
CS2 wait bit
CS3 wait bit
Chip select expansion register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CSE
Address
001B16
When reset
0016
R W
Function
Bit symbol
Bit name
CSE0W
CSE1W
CSE2W
CSE3W
CS0 wait expansion bit
CS1 wait expansion bit
CS2 wait expansion bit
CS3 wait expansion bit
0 0 : 1 Wait state
0 1 : 2 Wait states
1 0 : 3 Wait states
1 1 : Inhibited
Note 1: Set CSEiW bits (i = 0 to 3) after setting the corresponding CSiW bit (i = 0 to 3) of the CSR
register to “0”. When CSiW bits are set to “1”, CSEiW bits must be returned to “00 ”.
2
Figure 4.2.3. Level of BYTE pin and external data bus width
4.2.3 R/W Modes
_____
The read/write signal that is output when accessing an external area can be selected between the RD/
________ ______
_____ _________ ________
BHE/WR and the RD/WRH/WRL modes by setting the R/W mode select bit (bit 2) of the processor mode
_____ ________ ______
register 0 (address 000416). Use the (RD/BHE/WR) mode to access an 8-bit and a 16-bit wide RAM, and
_____ _________ ________
the (RD/WRH/WRL) to access a 16-bit wide RAM.
_____ ________ ______
When the M30245 is reset, the RD/BHE/WR mode is selected by default. To switch over the R/W mode,
_____ _______ ______
_____ _________ ________
change the RD/BHE/WR to the RD/WRH/WRL mode before accessing an external RAM.
_____ ________ ______
_____ _________ ________
Refer to the connection examples of RD/BHE/WR and RD/WRH/WRL shown in Section 4.3, “Connection
Examples.”
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4. External Buses
4.3 Connection Examples
4.3.1 16-bit Memory to 16-bit Width Data Bus Connection Example
Figure 4.3.1 shows an example of connecting M5M51016BTP (SRAM). In this diagram, when reset the
microcomputer starts operating in single-chip mode. Change this mode to memory expansion mode in a
program.
Microcomputer
WR
CNVSS
BYTE
BHE
A
0
to A16
A
16
A0
A
15
BC
BC
1
2
to
A
BHE
WR
to
1
A
0
W
CS1
D
0
CS1
RD
CS
OE
DQ
to
DQ16
1
to
D
RD
15
M5M51016BTP
D
0
to D15
Figure 4.3.1. Example of connecting M5M51016BTP
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4. External Buses
4.3.2 8-bit Memory to 16-bit Width Data Bus Connection Example
Figure 4.3.2 shows an example of connecting two M5M5278's (SRAM) to a 16-bit data bus.In this dia-
gram, when reset the microcomputer starts operating in single-chip mode. Change this mode to memory
expansion mode in a program.
Microcomputer
WRH
WRL
CNVSS
BYTE
D
0
to D15
CS0
RD
CS0
RD
WRH
WRL
CS0
RD
S
S
W
W
D
0
D8
to
DQ
to
DQ
1
8
DQ
to
DQ
1
8
OE
OE
to
A
15
D
7
D15
A
to
14
A
15
to
A
to
14
to
A
1
A
0
A
1
A
0
M5M5278D
M5M5278D
A
1
to A15
Figure 4.3.2. Example of connecting two M5M5278's to a 16-bit data bus
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M30245 Group
4. External Buses
_______ ________
Figure 4.3.3 shows how to connect two Am29LV008B (flash memory). In 16-bit bus mode,the BHE/WRH
_______
pin functions as BHE. When connecting 8-bit flash memory chips to the 16-bit bus, make sure the
________
_____
microcomputer’s WRL pin is connected to the WR pins on both flash memory chips, and that data is
written to the flash memory in units of 16 bits beginning with an even address.
Microcomputer
CNVSS
WRL
BYTE
D
0
to D15
CS0
RD
CS0
RD
CS0
RD
CE
OE
CE
OE
WE
WE
D
to
0
D8
to
DQ
to
0
DQ
to
0
D
7
D15
A
19
A
19
DQ
7
DQ
7
A
18
A18
to
to
to
A1
to
A
1
A
0
A0
Am29LV008B
Am29LV008B
A
1
to A19
Figure 4.3.3. Example of connecting two Am29LV008B's to a 16-bit data bus
Rev.2.00 Oct 16, 2006 page 336 of 354
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4. External Buses
4.3.3 8-bit Memory to 8-bit Width Data Bus Connection Example
Figure 4.3.4 shows an example of connecting two M5M5278's (SRAM) to an 8-bit data bus.In this dia-
gram, when reset the microcomputer starts operating in single-chip mode. Change this mode to memory
expansion mode in a program.
Microcomputer
CNVSS
WR
D0 to D7
BYTE
CS0
CS0
CS1
S
WR
WR
D0
W
W
CS1
RD
D0
to
D7
S
DQ1
to
DQ1
to
RD
to
D7
OE
RD
OE
DQ8
DQ8
A14
to
A14
to
A0
A0
M5M5278D
M5M5278D
A0 to A14
Figure 4.3.4. Example of connecting two M5M5278's to an 8-bit data bus
Rev.2.00 Oct 16, 2006 page 337 of 354
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4. External Buses
4.3.4 Two 8-bit and 16-Bit Memory to 16-Bit Width Data Bus Connection Example
Figure 4.3.5 shows an example of connecting M5M28F102 (16-bit flash memory) and two M5M5278's (8-
bit SRAM) to a 16-bit data bus.
Microcomputer
CNVSS
BYTE
WRH
WRL
A
1
to A16
A
to
A
15
A
to
A1
15
A16
15
V
CC
A
W
OE
S
W
OE
S
A
to
A
14
A14
to
A0
to
to
0
RD
RD
CS0
CE
15
1
A
1
A
0
CS1
CS1
D
D
15
to
to
D
D
0
D8
to
D
1
D
1
0
to
D
0
RD
to
to
D
7
D15
8
D
8
D
OE WE
M5M5278D
M5M5278D
M5M28F102
D
0
to D15
CS1
CS0
RD
Figure 4.3.5. Example of connection of two 8-bit memories and one 16-bit memory to 16-bit width data bus
Rev.2.00 Oct 16, 2006 page 338 of 354
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M30245 Group
4. External Buses
4.3.5 Chip Selects and Address Bus
When there are insufficient chip select signals, it is necessary to generate chip selects externally. Figure
_______
4.3.6 shows an example of a connection in which the CS2 (128K bytes) area is divided into four 32K byte
areas.
Microcomputer
CNVSS
WR
RD
A0 to A17
IC0
IC3
BYTE
A15
A16
A17
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
1
2
3
4
5
6
16
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
Y1
A0 to A14
A10
A11
A12
A13
14
13
12
11
3
Y2
Y3
Y4
CS2
4
5
6
7
•
•
•
A14
Y1
D7
D6
D5
D4
D3
8
8
Y4
9
74HC138
10
11
12
13
14
D0 to D7
M5M5278
M5M5278
D0 to D7
Memory map
0000016
0800016
IC0
IC1
IC2
IC3
0FFFF16
1000016
17FFF16
1800016
CS2
1FFFF16
2000016
2FFFF16
3000016
FFFFF16
Figure 4.3.6. Chip selects and address bus
Rev.2.00 Oct 16, 2006 page 339 of 354
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M30245 Group
4. External Buses
4.4 Connectable Memories
4.4.1 Operation Frequency and Access Time
Connectable memories depend upon the BCLK frequency f(BCLK). The frequency of f(BCLK) is equal to
that of the BCLK, and is contingent on the oscillator's frequency and on the settings in the system clock
select bits (bit 6 of address 000616, and bits 6 and 7 of address 000716).
The following are the conditional equations for the connections. Meet these conditions minimally. Fig-
ures 4.4.1 and 4.4.2 show the relation between the frequency of BCLK and memory.
(1) Read cycle time (tCR)/write cycle time (tCW)
Read cycle time (tCR) and write cycle time (tCW) must satisfy the following conditional expressions:
• With the Wait option cleared
9
9
tCR < 10 /f(BCLK) and tCW < 2 × 10 /f(BCLK)
(When CSxW = 1 read: one cycle of BCLK write: two cycles of BCLK)
• With the Wait option selected
9
9
tCR < (m+1) × 10 /f(BCLK) and tCW < (m+1) × 10 /f(BCLK)
(When CSxW = 0 and the number of the expansion waits is selected by the CSExW bit)
(m denotes the number of Wait states: m = “1” when 1 wait selected, “m = 2” when 2 waits selected,
and “m = 3” when 3 waits selected)
(2) Address access time [ta(A)]
Address access time [ta(A)] must satisfy the following conditional expressions:
(a) Vcc = 3.0 to 3.6 V
• With the Wait option cleared
9
ta(A) < 10 /f(BCLK) – 80(ns)*
• With the Wait option selected
9
ta(A) < (m+1) × 10 /f(BCLK) – 80(ns)*
(m = “1” when 1 wait selected, “m = 2” when 2 waits selected, and “m = 3” when 3 waits selected)
*80(ns) = td(BCLK – AD) + tsu(DB – RD) – th(BCLK – RD)
= (address output delay time) + (data input setup time) – (RD signal output hold time)
(3) Chip select access time [ta(S)]
Chip select access time [ta(S)] must satisfy the following conditional expressions:
(a) Vcc = 3.0 to 3.6 V
• With the Wait option cleared
9
ta(S) < 10 /f(BCLK) – 80(ns)*
• With the Wait option selected
9
ta(S) < (m+1) × 10 /f(BCLK) – 80(ns)*
(m = “1” when 1 wait selected, “m = 2” when 2 waits selected, and “m = 3” when 3 waits selected)
*80(ns) = td(BCLK – CS) + tsu(DB – RD) – th(BCLK – RD)
= (chip select output delay time) + (data input setup time) – (RD signal output hold time)
Rev.2.00 Oct 16, 2006 page 340 of 354
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M30245 Group
4. External Buses
(4) Output enable time [ta(OE)]
Output enable time [ta(OE)] must satisfy the following conditional expressions:
(a) Vcc = 3.0 to 3.6 V
• With the Wait option cleared
9
ta(OE) < 10 /(f(BCLK) × 2) – 60(ns) = tac1(RD-DB)
• With the Wait option selected
9
ta(OE) < (m+0.5) × 10 /f(BCLK) – 60(ns) = tac2(RD-DB)
(m = “1” when 1 wait selected, “m = 2” when 2 waits selected, and “m = 3” when 3 waits selected)
(5) Data setup time [tsu(D)]
Data setup time [tsu(D)] must satisfy the following conditional expressions:
(a) Vcc = 3.0 to 3.6 V
• PM16 = 0 (WR width normal)
9
tsu(D) < (n – 0.5) × 10 /f(BCLK) – 40(ns) = td(DB – WR)
• PM16 = 1 (WR width expanded)
9
tsu(D) < n × 10 /f(BCLK) – 40((ns) = td(DB – WR)
*40(ns) = td(BCLK – DB) – th(BCLK – WR)
= (data output delay time) – (WR signal output hold time)
(n = 1 (no wait), n = 2 (1 wait), n = 3 (2 waits), n = 4 (3 waits))
Access time
4000
3920
3500
Without wait
1 wait
2 waits
3 waits
3000
2920
2500
2000
1920
1920
1420
920
1500
1000
500
0
1253
920
587
253
920
920
670
420
170
720
520
320
120
587
420
253
87
491
349
206
63
420
420
295
170
45
364
253
142
31
320
220
120
20
284
193
102
11
253
170
87
170
228
151
74
206
134
63
187
120
53
108
45
-18
16
3
-3
-9
-13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MHz
Figure 4.4.1. Relation between the frequency of BCLK and memory (1)
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4. External Buses
OE access time
4000
3500
3000
2500
2000
1500
1000
500
Without wait
1 wait
2 waits
3440
2440
1440
440
3 waits
1690
1190
690
1107
773
440
107
815
565
315
65
640
440
240
40
523
357
190
23
440
378
329
218
107
-4
297
290
190
90
258
167
76
253
154
128
232
148
65
209
132
55
190
190
119
47
173
107
40
159
96
34
0
11
3
-10
-15
-18
-22
-24
-27
-29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MHZ
Data set up time
4000
3500
3000
2500
2000
1500
1000
500
3960
Without wait
1 wait
2 waits
3 waits
2960
1960 1960
1460
1293
960
627
293
960
960
460
960
710
460
210
760
560
360
160
627
460
293
127
531
460
335
246
210
404
293
182
71
389
360
324
293
268
260
160
60
246
174
103
31
233
142
51
227
160
93
27
210
127
43
210
148
85
191
114
37
103
85
23
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MHz
Figure 4.4.1. Relation between the frequency of BCLK and memory (2)
Rev.2.00 Oct 16, 2006 page 342 of 354
REJ09B0340-0200
M30245 Group
4. External Buses
4.4.2 Connecting Low-Speed Memory
To connect memory with long access time [ta(A)], either decrease the frequency of BCLK or set a soft-
________
ware wait. Using the RDY feature allows you to connect memory having the timing that precludes con-
nection though you set software wait.
(1) Using software wait
Set software wait for the external memory areas by using either of bits CS0W through CS3W of the
chip select control register (address 000816) or the chip select expansion register (address 001B16).
________
When using the RDY signal, the corresponding CS0W through CS3W bit must be set to “0”.
Bits CS0W through CS3W of the chip select control register correspond to chip select CS0 through
CS3, respectively. If these bits are set to “1”, the read bus cycle results in one cycle of BCLK and the
write bus cycle results in two cycles of BCLK; if these bits are set to “0”, the read/write cycle results in
two, three, or four cycles of BCLK according to the chip select expansion register setting. When the
corresponding bit of the chip select control register is set to “0”, the chip select expansion register
setting becomes valid. When this bit is set to “1”, set the corresponding bit of the chip select expansion
register to “002”.
When reset, the value of the chip select control register and the chip select expansion register is set to
“0016”.
These control bits do not affect the SFR area and the internal ROM/RAM area.
Figure 4.4.1 shows software wait and bus cycle, and Figure 4.4.3 shows relation of processor mode
and the wait bit (CSiW, CSiEW).
Table 4.4.1. Software waits and bus cycles
CSExW
(Note 2)
Invalid
Invalid
00
CSxW
Bus Cycles
Area
Write
Read
(Note 2)
2 BCLK cycles
1 BCLK cycle
2 BCLK cycles
3 BCLK cycles
4 BCLK cycles
SFR
2 BCLK cycles
1 BCLK cycle
2 BCLK cycles
3 BCLK cycles
4 BCLK cycles
Invalid
Internal ROM/RAM
Invalid
0
0
0
0
1
01
External memory
areas
10
11
Do not set
2 BCLK cycles
00
1 BCLK cycle
_______
Note 1: When using the RDY signal, set to “0”.
Note 2: Set CSEiW bits (i = 0 to 3) after setting the corresponding CSiW bit (i = 0 to 3) of the CSR register
to “0”. When CSiW bits are set to “1”, CSEiW bits must be returned to “002”.
Rev.2.00 Oct 16, 2006 page 343 of 354
REJ09B0340-0200
M30245 Group
4. External Buses
Single-chip mode
0000016
SFR area
BCLK × 2
BCLK × 1
0040016
Internal RAM area
XXXXX16
YYYYY16
FFFFF16
Type No.
Address XXXXX16 Address YYYYY16
Internal ROM area
BCLK × 1
M30245FCGP
02BFF16
E000016
M30245MC-XXXGP
M30245M8-XXXGP
02BFF16
017FF16
E000016
F000016
• Memory expansion mode and microprocessor examples apply with the following settings:
CS0 = “1”(CS0 output enabled)
CS3 = “1”(CS3 output enabled)
CS0W = “0” (with CS0 wait)
CS3W = “1” (without CS3 wait)
CSE0W = “01
2” (CS0: 2-wait expansion)
Microprocessor mode
Memory expansion mode
SFR area
0000016
0000016
BCLK × 2
BCLK × 2
BCLK × 1
SFR area
0040016
0040016
Internal RAM area
BCLK × 1
Internal RAM area
XXXXX16
XXXXX16
Internal area reserved
CS3 external area
Internal area reserved
CS3 external area
0400016
0800016
0400016
0800016
Read BCLK × 1
Write BCLK × 2
Read BCLK × 1
Write BCLK × 2
2800016
3000016
2800016
3000016
BCLK × 3
BCLK × 1
CS0 external area
Internal area reserved
Internal ROM area
D000016
CS0 external area
BCLK × 3
YYYYY16
FFFFF16
FFFFF16
Figure 4.4.3. Relation of processor mode and the wait bit (CSiW, CSiEW)
Rev.2.00 Oct 16, 2006 page 344 of 354
REJ09B0340-0200
M30245 Group
4. External Buses
________
(2) RDY function usage
_______
To use the RDY function, set a software wait.
_______
_______
The RDY function operates when the BCLK signal falls with the RDY pin at “L”; the bus does not vary
for 1 BCLK, and the state at that moment is held.
_______
_______
The RDY function holds the state of bus for the period in which the RDY pin is at “L”, and releases it
_______
_______
when the BCLK signal falls with the RDY pin at “H”. Figure 4.4.4 shows an example of RDY circuit
(f(XIN)=10MHz) that holds the state of bus for 1 BCLK.
BCLK
S
S
1Q
1Q
2Q
2Q
CK
CK
RDY
D
D
R
R
CS0
RD
BCLK
CS0
RD
1Q
2Q
RDY
(1)
(2)
(1)
(2)
(1) RDY accepted
(2) RDY cleared
The state of data bus and that of address bus are held for the period between (1) and (2).
________
Figure 4.4.4. Example of RDY circuit holding state of bus for 1 BCLK (f(XIN)=10MHz)
Rev.2.00 Oct 16, 2006 page 345 of 354
REJ09B0340-0200
M30245 Group
4. External Buses
4.4.3 Connectable Memories
Connectable memories and their maximum frequencies are given here;
M30245 group maximum frequency is
16MHz (without the wait) for Vcc=3V,
(1) Flash memories (Read only mode)
(a) 3V without wait
Maximum
frequency (MHz)
Model No.
3.57
M5M29GB/T160BVP-80
(b) 3V with wait
Maximum
frequency (MHz)
Model No.
M5M29GB/T160BVP-80
8.33
(2) SRAM
(a) 3V without wait
Maximum
frequency (MHz)
Model No.
M5M54R08AJ-12
5.12
M5M54R16AJ, ATP-12
(b) 3V without wait
Maximum
frequency (MHz)
Model No.
M5M54R08AJ-12
10.0
M5M54R16AJ, ATP-12
Rev.2.00 Oct 16, 2006 page 346 of 354
REJ09B0340-0200
M30245 Group
4. External Buses
__________
__________
4.5 Releasing an External Bus (HOLD input and HLDA output)
The Hold feature is to relinquish the address bus, the data bus, and the control bus on M30245 side in line
with the Hold request from the bus master other than M30245 when the two or more bus masters share the
address bus, the data bus, and the control bus. The Hold feature is effective only in memory expansion
mode and microprocessor mode.
The sequence of using the Hold feature may be:
__________
1. The external bus master turns the input level of the HOLD terminal to “L”.
2. When M30245 becomes ready to relinquish buses, each bus becomes high-impedance state at the
falling edge of BCLK.
__________
3. The HLDA terminal becomes “L” at the rising edge of the next BCLK.
4. The external bus master uses a bus.
5. When the external bus master finishes using a bus, the external bus master returns the input level of
__________
the HOLD terminal to “H”.
__________
6. The output from HLDA terminal becomes “H” at the rising edge of the next BCLK.
7. Each bus returns from the high-impedance state to the former state at the falling edge of the next
BCLK.
__________
As given above, each bus invariably gets in the high-impedance state while the HLDA output is “L”. Also,
M30245 does not relinquish buses during a bus cycle. That is, if a Hold request comes in during a bus
__________
cycle, the HLDA output become “L” after that bus cycle finishes.
In the Hold state, the state of each terminal becomes as follows.
• Address bus A0 to A19
High-impedance state. The case in which A16 to A19 are used as ports P40 to P43 (64K byte address
space) in microprocessor mode and in memory expansion mode too falls under this category.
• Data bus D0 to D15
High-impedance state. The case in which D8 to D15 are used as ports P10 to P17 (8-bit external bus
width) in microprocessor mode and in memory expansion mode too falls under this category.
_____ _____ ________ ________ ________
• RD, WR, WRL, WRH, BHE
High-impedance state.
• ALE
An internal clock signal having the same phase as BCLK is output.
_______
_______
• CS0 to CS3
High-impedance state. The case in which ports are selected by the chip selection control register too
falls under this category.
Figure.4.5.1 shows an example of relinquishing external buses.
Rev.2.00 Oct 16, 2006 page 347 of 354
REJ09B0340-0200
M30245 Group
4. External Buses
Timing chart
BCLK
HOLD
HLDA
ALE
Indeterminate
HiZ
HiZ
HiZ
HiZ
CSn
ADi
DBi
RD/WR
Bus released
(1) (2) (3) (4)
(5) (6) (7)
(8)
(1) An “L” level is input to the HOLD pin.
(2) HOLD is detected.
(3) The CPU releases the bus.
(4) An “L” is output to the HLDA pin.
(5) An “H” is input to the HOLD pin.
(6) An “H” is output to the HLDA pin.
(7) The CPU not releases the bus.
(8) The CPU resumes using the bus.
Figure 4.5.1. Example of releasing the external bus
Rev.2.00 Oct 16, 2006 page 348 of 354
REJ09B0340-0200
M30245 Group
4. External Buses
4.6 Precautions for External Bus
Description When the MCU enters wait mode while operating in memory expansion mode or micropro-
cessor mode, a pin functioning as part of the address or data bus retains it's state on the bus
before wait mode is entered. Shift to single-chip mode and output an arbitrary value in order
to reduce current consumption. By shifting to single-chip mode, a pin which was functioning
as part of the bus becomes a general-purpose port and can output an arbitrary value. Set
the port registers and direction registers after shifting to single-chip mode (this implies that
_____ ______ _____
any control pins (CS, WR, RD, etc.. ) being used for access of an external device be
changed as well).
If the port registers and direction registers are set while in memory expansion mode or
microprocessor mode, the operation will be ignored.
This is similar when entering stop mode.
Figure 4.6.1 shows the setting procedure to enter wait mode or stop mode.
Operate in memory expansion mode or microprocessor mode
Shift to single-chip mode
Set the port register
Note 1
Set the direction register
Enter the wait mode or stop mode
Note 1. This program does not work in external area. Transfer a program
to internal RAM and work on internal RAM.
Figure 4.6.1. Setting procedure to enter wait mode or stop mode
Rev.2.00 Oct 16, 2006 page 349 of 354
REJ09B0340-0200
THIS PAGE IS BLANK FOR REASONS OF LAYOUT.
Chapter 5
Standard Characteristics
M30245 Group
5. Standard Characteristics
5.1 DC Standard Characteristics
Standard characteristics described in this chapter are just examples and not guaranteed. For rated values,
refer to "Electrical Characteristics" of Datasheet.
5.1.1 Port Standard Characteristics
Figures 5.1.1 to 5.1.4 show port standard characteristics.
-35
Vcc=3.3V
-30
Topr = -20C
Topr = 25C
-25
Topr = 85C
-20
-15
-10
-5
0
0
0.5
1
1.5
OH (V)
2
2.5
3
3.3
V
Note 1 : These characteristics are just examples and not guaranteed. For rated values,
refer to “Electrical Characteristics” of Datasheet.
Figure 5.1.1. VOH-IOH standard characteristics of ports P0 to P10 (except P63, P67, and P85)
35
30
25
20
15
10
Vcc=3.3V
Topr = -20C
Topr = 85C
5
0
0
0.5
1
1.5
OL (V)
2
2.5
3
3.3
V
Note 1 : These characteristics are just examples and not guaranteed. For rated values,
refer to “Electrical Characteristics” of Datasheet.
Figure 5.1.2. VOL-IOL standard characteristics of ports P0 to P10 (except P63, P67, and P85)
Rev.2.00 Oct 16, 2006 page 352 of 354
REJ09B0340-0200
M30245 Group
5. Standard Characteristics
-60
-50
-40
-30
-20
-10
0
Vcc=3.3V
Topr = -20°C
Topr = 25°C
Topr = 85°C
0
0.5
1
1.5
2
2.5
3
3.3
VOH (V)
Note 1 : These characteristics are just examples and not guaranteed. For rated values,
refer to “Electrical Characteristics” of Datasheet.
Figure 5.1.3. VOH-IOH standard characteristics of ports P63 to P67
60
55
Vcc=3.3V
50
45
40
35
30
25
20
15
10
5
Topr = -20°C
Topr = 25°C
Topr = 85°C
0
0
0.5
1
1.5
2
2.5
3
3.3
VOL (V)
Note 1 : These characteristics are just examples and not guaranteed. For rated values,
refer to “Electrical Characteristics” of Datasheet.
Figure 5.1.4. VOL-IOL standard characteristics of ports P63, P67, and P7 (when high drive selected)
Rev.2.00 Oct 16, 2006 page 353 of 354
REJ09B0340-0200
M30245 Group
5. Standard Characteristics
5.1.2 VCC-ICC Characteristics
Figure 5.1.5 and Figure 5.1.6 show VCC-ICC characteristics.
Measuring condition
Topr = 25°C
f(XIN) : Square wave 16MHZ
Single-chip mode
Without wait
No division mode
30
25
20
15
10
5
0
2.5
3.0
3.5
4.0
V
CC (V)
Figure 5.1.5. Vcc-Icc characteristics (Mask version)
Measuring condition
Topr = 25°C
f(XIN) : Square wave 16MH
Single-chip mode
Without wait
Z
No division mode
30
25
20
15
10
5
0
2.5
3.0
3.5
4.0
V
CC (V)
Figure 5.1.6. Vcc-Icc characteristics (Flash version)
Rev.2.00 Oct 16, 2006 page 354 of 354
REJ09B0340-0200
M30245 Group User’s Manual
REVISION HISTORY
Rev.
Date
Description
Summary
Page
A
Jan 24, 2003
–
First edition issued
6
2.00 Oct 16, 2006
2.2.1 (c) “3 types” → “2 types”, “an external input signal” deleted
Figure 2.2.4 UDF: bit 5-7; R “ ” → “–”
Figure 2.2.5 ONSF Note 3 added
2.2.10 deleted
Figure 2.2.34 deleted
2.3.1 (3) “Error detection” revised
10
11
28
37
39
42
43
44
Figure 2.3.2 UiRB Note 1 deleted, ABT; W “×” → “
”
Figure 2.3.3 UiMR; When reset revised, Note 3 added
Figure 2.3.4 UiC0: bit 5; “TxDi” → “TxDi/SDAi and SCLi” revised, Note 2 revised,
Note 4 added
UiCi Note 1 added
47
50
51
Figure 2.3.6 UiC0: bit 5; “TxDi” → “TxDi/SDAi and SCLi” revised
Figure 2.3.8 Example of operation revised
Figure 2.3.9 UiMR: bit 0-2 “Set the corresponding ..... to “0” when receiving.” →
“Set the RxDi .... to “0 ” when receiving.” revised
UiC0: bit5; “TxDi” → “TxDi/SDAi and SCLi” revised
Reception (3) revised
Table 2.4.3 Overrun error Description; revised
(c) LSB/MSB first select function added
Figure 2.4.3 UiRB Note 1 deleted, ABT; W “×” → “
54
56
57
60
61
62
”
Figure 2.4.4 UiMR; When reset revised, Note 3 added
Figure 2.4.5 UiC0: bit 5; “TxDi” → “TxDi/SDAi and SCLi” revised, Note 2 revised,
Note 4 added
UiCi Note 1 added
66
70
Figure 2.4.8 UiC0: bit 5; “TxDi” → “TxDi/SDAi and SCLi” revised
Figure 2.4.11 UiMR Note 1 added, UiC0, bit 5; “TxDi” → “TxDi/SDAi and SCLi”
revised
72
74
75
79
2.4.4 added
Figure 2.4.13 Example of operation (when direct format) revised, Note 2 added
Figure 2.4.14 UiC0: bit 5; “TxDi” → “TxDi/SDAi and SCLi” revised
Figure 2.4.17 UiMR Note 1 added, UiC0, bit 5; “TxDi” → “TxDi/SDAi and SCLi”
revised
88
89
90
Figure 2.5.2 UiRB Note 1 deleted, ABT; W “×” → “
”
Figure 2.5.3 UiMR; When reset revised, Note 3 added
Figure 2.5.4 UiC0: bit 5; “TxDi” → “TxDi/SDAi and SCLi” revised, Note 2 revised,
Note 4 added
UiCi Note 1 added
91
92
Figure 2.5.5 UiSMR: bit 7 revised, UiSMR2: bit 7 revised, Note 1 added
Figure 2.5.6 UiSMR3: bit 5-7 revised, Note 4 “The amount of delay varies with the
load on SCLi and SDAi pins.” added
93
96
100
Figure 2.5.7 Note 2 added
Figure 2.5.9 UiC0: bit 5; “TxDi” → “TxDi/SDAi and SCLi” revised
Figure 2.5.12 UiMR Note 1 added, UiC0: bit5; “TxDi” → “TxDi/SDAi and SCLi”
revised
104
108
Figure 2.5.15 UiC0: bit 5; “TxDi” → “TxDi/SDAi and SCLi” revised
Figure 2.5.18 UiMR Note 1 added, UiC0: bit 5; “TxDi” → “TxDi/SDAi and SCLi”
revised
110-120
2.6 added
C-1
M30245 Group User’s Manual
REVISION HISTORY
Rev.
Date
Description
Summary
Page
2.00 Oct 16, 2006
122
124
125
138
Figure 2.7.3 FSC: bit 2, 1 revised
Table 2.7.1 revised
Table 2.7.3 revised
2.8.2 •USB control register; “the minimum 250ns of delay” → “a minimum 187.5
ns of delay (three cycles of BCLK)”
143
144
145
146
154
155
157
163
165
(2) Enable of USB Function Control Unit; 3,7,8 revised
Figure 2.8.16 “Wait for 4 or more cycles of φ” deleted
Figure 2.8.17 FSC: bit 2, 1 revised
Figure 2.8.18 revised
(2) USB Endpoint 0 Interrupt: “• The SETUP_END flag .....” added
(3) USB Function Interrupt: “• The last ACK for control rea ....” added
• Artificial SOF Function revised
• USB Suspend Mode Control: 1 revised and 5, 6, Note added
-Returning Routine of USB Function Control Unit: 5 deleted,
“(other than the FSC)” → “(other than the USBC,USBAD,and frequency synthe-
sizer related registers)”
167
174
210
Figure 2.8.29 added
• USB endpoint 0 MAXP register: “SET_DESCRIPTOR” → “GET_DESCRIPTOR”
2.8.9 “(1) USB Communication” added, (2) Peripheral Circuit; “between the USB
D+pin and the USB D-pin or” deleted
211
212
Figure 2.8.51 revised
(3) Register, Bit: “(addresses 030016 to 033C16, excepting FSC)” →
“(other than the USBC,USBAD,and frequency synthesizer related registers)”
Figure 2.11.2 CRCMR, CRCSAR; When reset revised
CRCSAR Note added
2.11.3 “The target SFRs include the .... the UART-related registers.” →
“The target SFRs include .... Serial Sound Interface-related registers.”
2.13.1 “When the external bus .... to the external areas.” added
2.16.1 (2) “Reducing the driving capacity .... in power consumption.” deleted
(3) revised, (4) added
Figure 2.16.5 (3); “following JMP.B instruction” added
Figure 2.16.6 “Insert at least four NOPs after the WAIT instruction is executed.” →
“Insert JMP.B instruction before .... NOPs after the WAIT instruction.”
2.16.4 (3) revised, (4) added
250
252
258
274
276
280
281
282
283
284
286
287
289
303
320
(d) deleted
Table 2.17.1 revised
Table 2.17.3 AVSS, VREF, USB D+, USB D-, LPF, VbusDTCT, Note 6 added
Figure 2.17.2 PCR revised
Figure 2.17.3 PD9; When reset revised
3.3 deleted
Figure 3.7.4 “The DMA transfer request from .... is transmit request state.” → “The
DMA tansfer request from .... in transmit request state.”
Figure 3.9.3 revised
Chapter 4 added
Chapter 5 added
327
329
351
C-2
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
USER’S MANUAL
M30245 Group
Publication Data : Rev.A Jan 24, 2003
Rev.2.00 Oct 16, 2006
Published by :
Sales Strategic Planning Div.
Renesas Technology Corp.
© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
M30245 Group
User's Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo,100-0004, Japan
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