ISLA214P [RENESAS]
14-Bit, 250MSPS/200MSPS/130MSPS ADC;型号: | ISLA214P |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | 14-Bit, 250MSPS/200MSPS/130MSPS ADC |
文件: | 总35页 (文件大小:1677K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATASHEET
ISLA214P
14-Bit, 250MSPS/200MSPS/130MSPS ADC
FN7572
Rev 2.00
December 5, 2012
The ISLA214P is a series of low power, high performance
14-bit analog-to-digital converters. Designed with Intersil’s
proprietary FemtoCharge™ technology on a standard CMOS
process, the series supports sampling rates of up to 250MSPS.
The ISLA214P is part of a pin-compatible family of 12 to 16-bit
A/Ds with maximum sample rates ranging from 130MSPS to
500MSPS.
Features
• Single supply 1.8V operation
• Clock duty cycle stabilizer
• 75fs clock jitter
• 700MHz bandwidth
• Programmable built-in test patterns
• Multi-ADC support
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters,
such as gain and offset. Digital output data is presented in
selectable LVDS or CMOS formats, and can be configured as
full-width, single data rate (SDR) or half-width, double data
rate (DDR). The ISLA214P is available in a 72-contact QFN
package with an exposed paddle. Operating from a 1.8V
supply, performance is specified over the full industrial
temperature range (-40°C to +85°C).
- SPI programmable fine gain and offset control
- Support for multiple ADC synchronization
- Optimized output timing
• Nap and sleep modes
- 200µs sleep wake-up time
• Data output clock
• SDR/DDR LVDS-compatible or LVCMOS outputs
• Selectable clock divider
Key Specifications
• SNR @ 250/200/130MSPS
73.0/73.8/74.9dBFS f = 30MHz
IN
70.6/71.1/70.9dBFS f = 363MHz
IN
Applications
• Radar array processing
• SFDR @ 250/200/130MSPS
• Software defined radios
82/88/88dBc f = 30MHz
IN
78/82/84dBc f = 363MHz
IN
• Total Power Consumption = 480mW @ 250MSPS
• Broadband communications
• High-performance data acquisition
• Communications test equipment
Pin-Compatible Family
SPEED
(MSPS)
MODEL
RESOLUTION
ISLA216P25
ISLA216P20
ISLA216P13
ISLA214P50
ISLA214P25
ISLA214P20
ISLA214P13
ISLA212P50
ISLA212P25
ISLA212P20
ISLA212P13
16
16
16
14
14
14
14
12
12
12
12
250
200
130
500
250
200
130
500
250
200
130
CLKP
CLKOUTP
CLKOUTN
CLOCK
MANAGEMENT
CLKN
VINP
VINN
14-BIT
250 MSPS
ADC
SHA
D[13:0]P
D[13:0]N
DIGITAL
ERROR
CORRECTION
+
–
VCM
SPI
CONTROL
FN7572 Rev 2.00
December 5, 2012
Page 1 of 35
ISLA214P
Pin Configuration - LVDS MODE
ISLA214P
(72 LD QFN)
TOP VIEW
72 71 70 69 68 67 66 65 64 63
62 61 60 59 58 57 56 55
DNC
DNC
1
2
54 D3P
D3N
53
52
51
50
49
48
47
46
45
44
43
42
41
3
NAPSLP
VCM
D4P
4
D4N
5
AVSS
AVDD
AVSS
VINN
D5P
6
D5N
7
CLKOUTP
CLKOUTN
RLVDS
OVSS
D6P
8
9
VINN
10
11
12
13
14
VINP
VINP
AVSS
AVDD
AVSS
CLKDIV
IPTAT
DNC
D6N
D7P
D7N
15
16
17
40
D8P
39 D8N
38
Thermal Pad Not Drawn to Scale,
Consult Mechanical Drawing
for Physical Dimensions
D9P
37 D9N
Connect Thermal Pad to AVSS
RESETN 18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
FN7572 Rev 2.00
December 5, 2012
Page 2 of 35
ISLA214P
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER
LVDS PIN NAME
LVDS PIN FUNCTION
DDR MODE COMMENTS
1, 2, 17
DNC
Do Not Connect
6, 13, 19, 20, 21, 70, 71,
72
AVDD
1.8V Analog Supply
5, 7, 12, 14
AVSS
OVDD
OVSS
NAPSLP
VCM
Analog Ground
1.8V Output Supply
Output Ground
27, 32, 62
26, 45, 61, 65
3
4
Tri-Level Power Control (Nap, Sleep modes)
Common Mode Output
8, 9
10, 11
15
VINN
Analog Input Negative
VINP
Analog Input Positive
CLKDIV
IPTAT
Tri-Level Clock Divider Control
16
Temperature Monitor (Output current proportional to absolute
temperature)
18
22, 23
24, 25
28
RESETN
Power On Reset (Active Low)
Clock Input True, Complement
CLKP, CLKN
CLKDIVRSTP, CLKDIVRSTN Synchronous Clock Divider Reset True, Complement
D13N
D13P
D12N
D12P
D11N
D11P
D10N
D10P
D9N
LVDS Bit 13(MSB) Output Complement
LVDS Bit 13 (MSB) Output True
LVDS Bit 12 Output Complement
LVDS Bit 12 Output True
NC in DDR Mode
29
NC in DDR Mode
30
DDR Logical Bits 12, 13
DDR Logical Bits 12, 13
NC in DDR Mode
31
33
LVDS Bit 11 Output Complement
LVDS Bit 11 Output True
34
NC in DDR Mode
35
LVDS Bit 10 Output Complement
LVDS Bit 10 Output True
DDR Logical Bits 10, 11
DDR Logical Bits 10, 11
NC in DDR Mode
36
37
LVDS Bit 9 Output Complement
LVDS Bit 9 Output True
38
D9P
NC in DDR Mode
39
D8N
LVDS Bit 8 Output Complement
LVDS Bit 8 Output True
DDR Logical Bits 8, 9
DDR Logical Bits 8, 9
NC in DDR Mode
40
D8P
41
D7N
LVDS Bit 7 Output Complement
LVDS Bit 7 Output True
42
D7P
NC in DDR Mode
43
D6N
LVDS Bit 6 Output Complement
LVDS Bit 6 Output True
DDR Logical Bits 6, 7
DDR Logical Bits 6, 7
44
D6P
46
RLVDS
CLKOUTN, CLKOUTP
D5N
LVDS Bias Resistor (Connect to OVSS with 1% 10k)
LVDS Clock Output Complement, True
LVDS Bit 5 Output Complement
LVDS Bit 5 Output True
47, 48
49
NC in DDR Mode
50
D5P
NC in DDR Mode
51
D4N
LVDS Bit 4 Output Complement
LVDS Bit 4 Output True
DDR Logical Bits 4, 5
DDR Logical Bits 4, 5
NC in DDR Mode
52
D4P
53
D3N
LVDS Bit 3 Output Complement
LVDS Bit 3 Output True
54
D3P
NC in DDR Mode
55
D2N
LVDS Bit 2 Output Complement
LVDS Bit 2 Output True
DDR Logical Bits 2, 3
DDR Logical Bits 2, 3
NC in DDR Mode
56
D2P
57
D1N
LVDS Bit 1 Output Complement
FN7572 Rev 2.00
December 5, 2012
Page 3 of 35
ISLA214P
Pin Descriptions - 72 Ld QFN, LVDS Mode (Continued)
PIN NUMBER
LVDS PIN NAME
LVDS PIN FUNCTION
DDR MODE COMMENTS
NC in DDR Mode
58
D1P
LVDS Bit 1 True
59
D0N
LVDS Bit 0 (LSB) Output Complement
LVDS Bit 0 (LSB) Output True
LVDS Over Range Complement, True
SPI Serial Data Output
DDR Logical Bits 0, 1
DDR Logical Bits 0, 1
DDR Over Range
60
D0P
63, 64
ORN, ORP
SDO
66
67
CSB
SPI Chip Select (active low)
SPI Clock
68
69
SCLK
SDIO
SPI Serial Data Input/Output
Analog Ground
Exposed Paddle
AVSS
Pin Configuration - CMOS MODE
ISLA214P
(72 LD QFN)
TOP VIEW
72 71 70 69 68 67 66 65 64 63 62 61
60 59 58 57 56 55
DNC
DNC
1
2
54 D3
DNC
D4
53
52
51
50
49
48
47
46
45
44
43
42
41
3
NAPSLP
VCM
4
DNC
D5
5
AVSS
AVDD
AVSS
VINN
6
DNC
CLKOUT
DNC
RLVDS
OVSS
D6
7
8
9
VINN
10
11
12
13
14
VINP
VINP
AVSS
AVDD
AVSS
CLKDIV
IPTAT
DNC
DNC
D7
DNC
D8
15
16
17
40
39 DNC
38
Thermal Pad Not Drawn to Scale,
Consult Mechanical Drawing
for Physical Dimensions
D9
37 DNC
Connect Thermal Pad to AVSS
RESETN 18
19 20 21 22 23 24 25 26
27 28 29 30 31 32
33 34 35 36
FN7572 Rev 2.00
December 5, 2012
Page 4 of 35
ISLA214P
Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER
CMOS PIN NAME
CMOS PIN FUNCTION
DDR MODE COMMENTS
1, 2, 17, 28, 30, 33, 35,
37, 39, 41, 43, 47, 49,
51, 53, 55, 57, 59, 63
DNC
Do Not Connect
6, 13, 19, 20, 21, 70, 71,
72
AVDD
1.8V Analog Supply
5, 7, 12, 14
AVSS
OVDD
OVSS
NAPSLP
VCM
Analog Ground
1.8V Output Supply
Output Ground
27, 32, 62
26, 45, 61, 65
3
4
Tri-Level Power Control (Nap, Sleep modes)
Common Mode Output
8, 9
10, 11
15
VINN
Analog Input Negative
VINP
Analog Input Positive
CLKDIV
IPTAT
Tri-Level Clock Divider Control
16
Temperature Monitor (Output current proportional to absolute
temperature)
18
RESETN
Power On Reset (Active Low)
Clock Input True, Complement
22, 23
CLKP, CLKN
24, 25
CLKDIVRSTP, CLKDIVRSTN Synchronous Clock Divider Reset True, Complement
29
D13
D12
D11
D10
D9
CMOS Bit 13 (MSB) Output
CMOS Bit 12 Output
CMOS Bit 11 Output
CMOS Bit 10 Output
CMOS Bit 9 Output
NC in DDR Mode
31
DDR Logical Bits 12, 13
NC in DDR Mode
34
36
DDR Logical Bits 10, 11
NC in DDR Mode
38
40
D8
CMOS Bit 8 Output
DDR Logical Bits 8, 9
NC in DDR Mode
42
D7
CMOS Bit 7 Output
44
D6
CMOS Bit 6 Output
DDR Logical Bits 6, 7
46
RLVDS
CLKOUT
D5
LVDS Bias Resistor (connect to OVSS with 1% 10k)
CMOS Clock Output
CMOS Bit 5 Output
48
50
NC in DDR Mode
52
D4
CMOS Bit 4 Output
DDR Logical Bits 4, 5
NC in DDR Mode
54
D3
CMOS Bit 3 Output
56
D2
CMOS Bit 2 Output
DDR Logical Bits 2, 3
NC in DDR Mode
58
D1
CMOS Bit 1 Output
60
D0
CMOS Bit 0 (LSB) Output
CMOS Over Range
DDR Logical Bits 0, 1
DDR Over Range
64
OR
66
SDO
CSB
SCLK
SDIO
AVSS
SPI Serial Data Output
SPI Chip Select (active low)
SPI Clock
67
68
69
SPI Serial Data Input/Output
Analog Ground
Exposed Paddle
FN7572 Rev 2.00
December 5, 2012
Page 5 of 35
ISLA214P
Ordering Information
PART NUMBER
(Notes 1,2)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISLA214P13IRZ
ISLA214P20IRZ
ISLA214P25IRZ
ISLA214P13 IRZ
ISLA214P20 IRZ
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
72 Ld QFN
L72.10x10E
72 Ld QFN
72 Ld QFN
L72.10x10E
L72.10x10E
ISLA214P25 IRZ
ISLA214P13 IR1Z
ISLA214P20 IR1Z
Coming Soon
ISLA214P13IR1Z
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
48 Ld QFN
48 Ld QFN
48 Ld QFN
TBD
TBD
TBD
Coming Soon
ISLA214P20IR1Z
Coming Soon
ISLA214P25IR1Z
ISLA214P25 IR1Z
Evaluation Board
ISLA214IR72EV1Z
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see respective device information page for ISLA214P. For more information on MSL please see techbrief
TB363.
FN7572 Rev 2.00
December 5, 2012
Page 6 of 35
ISLA214P
Table of Contents
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Switching Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power-On Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
User Initiated Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Temperature Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Nap/Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SPI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Device Configuration/Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Digital Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SPI Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Equivalent Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
A/D Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Clock Input Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
LVCMOS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FN7572 Rev 2.00
December 5, 2012
Page 7 of 35
ISLA214P
Absolute Maximum Ratings
Thermal Information
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Latchup (Tested per JESD-78C;Class 2,Level A) . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
72 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . .
48 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . .
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
(°C/W)
23
24
(°C/W)
0.9
1.0
JA
JC
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
4. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, T = -40°C to +85°C (Typical specifications at +25°C), A = -1dBFS, f = Maximum Conversion Rate (per speed grade).
SAMPLE
A
IN
Boldface limits apply over the operating temperature range, -40°C to +85°C.
ISLA214P25
ISLA214P20
MIN MAX
ISLA214P13
MIN MAX
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
(Note 5) TYP (Note 5) (Note 5) TYP (Note 5) (Note 5) TYP (Note 5) UNITS
DC SPECIFICATIONS (Note 6)
Analog Input
Full-Scale Analog Input
Range
V
Differential
1.95
2.0
2.1
1.95
2.0
2.1
1.95
2.0
2.1
V
P-P
FS
Input Resistance
Input Capacitance
R
C
Differential
Differential
Full Temp
600
4.5
600
4.5
82
600
4.5
74
IN
pF
IN
Full Scale Range Temp.
Drift
A
108
ppm/°C
VTC
Input Offset Voltage
V
-5.0
-1.7
5.0
-5.0
-1.7
5.0
-5.0
-1.7
5.0
mV
V
OS
Common-Mode Output
Voltage
V
0.94
0.94
0.94
CM
Common-Mode Input
Current (per pin)
I
2.6
2.6
2.6
µA/MSPS
CM
Clock Inputs
Inputs Common Mode
Voltage
0.9
1.8
0.9
1.8
0.9
1.8
V
V
CLKP,CLKN Input Swing
(Note 7)
Power Requirements
1.8V Analog Supply
Voltage
AVDD
OVDD
1.7
1.7
1.8
1.8
1.9
1.9
200
88
1.7
1.7
1.8
1.8
174
75
1.9
1.9
184
84
1.7
1.7
1.8
1.8
1.9
1.9
161
77
V
1.8V Digital Supply
Voltage
V
1.8V Analog Supply
Current
I
I
188
78.5
40
152
68.5
40
mA
mA
dB
AVDD
1.8V Digital Supply
Current (Note 6)
3mA LVDS (SDR)
OVDD
Power Supply Rejection
Ratio
PSRR
30MHz, 30mV signal
P-P
on AVDD
40
FN7572 Rev 2.00
December 5, 2012
Page 8 of 35
ISLA214P
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, T = -40°C to +85°C (Typical specifications at +25°C), A = -1dBFS, f = Maximum Conversion Rate (per speed grade).
SAMPLE
A
IN
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
ISLA214P25 ISLA214P20
MIN MAX MIN MAX
ISLA214P13
MIN MAX
PARAMETER
Total Power Dissipation
Normal Mode
SYMBOL
CONDITIONS
(Note 5) TYP (Note 5) (Note 5) TYP (Note 5) (Note 5) TYP (Note 5) UNITS
P
2mA LVDS
454
480
450
432
420
55.8
6
422
448
410
392
375
52.2
6
369
397
360
313
310
48.6
6
mW
mW
mW
mW
mW
mW
mW
µs
D
3mA LVDS (SDR)
3mA LVDS (DDR)
CMOS (SDR)
518
482
428
CMOS (DDR)
Nap Mode
P
P
60
11
57
11
53
10
D
Sleep Mode
CSB at logic high
D
Nap/Sleep Mode
Wakeup Time
Sample Clock Running
200
400
630
AC SPECIFICATIONS
Differential Nonlinearity
DNL
INL
f
= 105MHz
-0.99 ±0.3
±2.5
2.0
40
-0.99 ±0.25
±2.5
1.4
40
-0.99 ±0.25
±2.5
1.4
40
LSB
IN
No Missing Codes
Integral Nonlinearity
f
= 105MHz
LSB
IN
Minimum Conversion
Rate (Note 8)
f
MIN
MSPS
S
Maximum Conversion
Rate
f
MAX
250
200
130
MSPS
S
Signal-to-Noise Ratio
(Note 9)
SNR
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
= 30MHz
73
73.8
74.9
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 105MHz
= 190MHz
= 363MHz
= 461MHz
= 605MHz
= 30MHz
70.1
73
72.1
70.6
69.9
68.4
72.4
72.4
70.7
69.8
66.1
60.5
11.73
72.1
73.7
72.8
71.1
70.0
68.5
73.5
73.1
72.3
70.7
67.4
61.1
11.92
73.0
74.3
73.3
70.9
69.5
67.8
74.6
73.6
72.2
70.6
65.9
61.1
12.10
Signal-to-Noise and
Distortion
(Note 9)
SINAD
= 105MHz
= 190MHz
= 363MHz
= 461MHz
= 605MHz
= 30MHz
69.4
71.0
70.8
Effective Number of Bits
(Note 9)
ENOB
= 105MHz
= 190MHz
= 363MHz
= 461MHz
= 605MHz
11.29 11.73
11.45
11.50 11.83
11.72
11.47 11.93
11.70
Bits
Bits
11.30
11.45
11.44
Bits
10.69
10.90
10.65
Bits
9.76
9.86
9.86
Bits
FN7572 Rev 2.00
December 5, 2012
Page 9 of 35
ISLA214P
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, T = -40°C to +85°C (Typical specifications at +25°C), A = -1dBFS, f = Maximum Conversion Rate (per speed grade).
SAMPLE
A
IN
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
ISLA214P25 ISLA214P20
MIN MAX MIN MAX
ISLA214P13
MIN MAX
PARAMETER
SYMBOL
CONDITIONS
(Note 5) TYP (Note 5) (Note 5) TYP (Note 5) (Note 5) TYP (Note 5) UNITS
Spurious-Free Dynamic
Range
(Note 9)
SFDR
f
f
f
f
f
f
f
f
f
f
f
f
f
f
= 30MHz
82
83
78
78
68
61
89
91
88
87
88
88
87
97
88
84
84
82
71
62
93
90
89
90
93
88
86
104
88
83
78
84
68
61
99
95
91
95
94
87
87
101
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
dBFS
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 105MHz
= 190MHz
= 363MHz
= 461MHz
= 605MHz
= 30MHz
72
72
70
Spurious-Free Dynamic SFDRX23
Range Excluding H2, H3
= 105MHz
= 190MHz
= 363MHz
= 461MHz
= 605MHz
= 70MHz
Intermodulation
Distortion
IMD
= 170MHz
-12
-12
-12
Word Error Rate
Full Power Bandwidth
NOTES:
WER
10
700
10
700
10
700
FPBW
MHz
5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
6. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. I
7. See “Clock Input” on page 20.
specifications apply for 10pF load on each digital output
OVDD
8. The DLL Range setting must be changed for low-speed operation.
9. Minimum specification guaranteed when calibrated at +85°C.
Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
(Note 5)
TYP
(Note 5) UNITS
INPUTS (Note 10)
Input Current High (RESETN)
Input Current Low (RESETN)
Input Current High (SDIO)
Input Current Low (SDIO)
Input Current High (CSB)
Input Current Low (CSB)
Input Current High (CLKDIV)
Input Current Low (CLKDIV)
I
V
V
V
V
V
V
= 1.8V
= 0V
0
1
-12
4
10
-8
µA
µA
µA
µA
IH
IN
IN
IN
IN
IN
IN
I
-25
IL
I
= 1.8V
= 0V
12
IH
I
-600
40
-415
58
5
-300
75
IL
I
= 1.8V
= 0V
IH
I
10
IL
I
16
-34
25
-25
34
µA
µA
V
IH
I
-16
IL
Input Voltage High (SDIO, RESETN)
Input Voltage Low (SDIO, RESETN)
Input Capacitance
V
1.17
IH
V
0.63
V
IL
C
4
pF
DI
FN7572 Rev 2.00
December 5, 2012
Page 10 of 35
ISLA214P
Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
MIN
(Note 5)
MAX
(Note 5) UNITS
PARAMETER
LVDS INPUTS (CLKDIVRSTP, CLKDIVRSTN)
Input Common Mode Range
Input Differential Swing (peak to peak, single-ended)
CLKDIVRSTP Input Pull-down Resistance
CLKDIVRSTN Input Pull-up Resistance
LVDS OUTPUTS
SYMBOL
CONDITIONS
TYP
V
825
250
1575
450
mV
mV
k
k
ICM
V
ID
R
R
100
100
Ipd
Ipu
Differential Output Voltage (Note 11)
Output Offset Voltage
V
3mA Mode
3mA Mode
612
1150
240
mV
P-P
T
V
1120
1200
mV
ps
OS
Output Rise Time
t
R
Output Fall Time
t
240
ps
F
CMOS OUTPUTS
Voltage Output High
V
I
I
= -500µA
= 1mA
OVDD - 0.3 OVDD - 0.1
V
V
OH
OH
Voltage Output Low
V
0.1
1.8
1.4
0.3
OL
OL
Output Rise Time
t
ns
ns
R
Output Fall Time
t
F
NOTES:
10. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD
depending on desired function.
11. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing.
Timing Diagrams
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUTN
CLKOUTP
tDC
tPD
D[12/10/8/6/4/2/0]N
ODD
N-L
EVEN
N-L
ODD
N-L+1
EVEN
N-L+1
EVEN
N-1
ODD
N
EVEN
N
D[12/10/8/6/4/2/0]P
FIGURE 1A. LVDS DDR
FN7572 Rev 2.00
December 5, 2012
Page 11 of 35
ISLA214P
Timing Diagrams(Continued)
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUTN
CLKOUTP
tDC
tPD
D[13:0]N
D[13:0]P
DATA
N-L
DATA
N-L+1
DATA
N
FIGURE 1B. LVDS SDR
FIGURE 1. LVDS TIMING DIAGRAMS
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUT
tDC
tPD
ODD
N-L
EVEN
N-L
ODD
N-L+1
EVEN
N-L+1
EVEN
N-1
ODD
N
EVEN
N
D[12/10/8/6/4/2/0]
FIGURE 2A. CMOS DDR
FN7572 Rev 2.00
December 5, 2012
Page 12 of 35
ISLA214P
Timing Diagrams(Continued)
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUT
tDC
tPD
DATA
N-L
DATA
N-L+1
DATA
N
D[13:0]
FIGURE 2B. CMOS SDR
FIGURE 2. CMOS TIMING DIAGRAMS
Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
MIN
(Note 5)
MAX
(Note 5)
PARAMETER
SYMBOL
CONDITION
TYP
UNITS
ADC OUTPUT
Aperture Delay
t
114
75
ps
fs
A
RMS Aperture Jitter
j
A
Input Clock to Output Clock Propagation
Delay
t
t
AVDD, OVDD = 1.7V to 1.9V,
1.65
2.4
3
ns
CPD
T
= -40°C to +85°C
A
AVDD, OVDD = 1.8V, T = +25°C
A
1.9
2.3
2.75
450
ns
ps
CPD
Relative Input Clock to Output Clock
Propagation Delay (Note 12)
dt
AVDD, OVDD = 1.7V to 1.9V,
-450
CPD
T
= -40°C to +85°C
A
Input Clock to Data Propagation Delay
t
t
1.65
-0.1
2.4
3.5
0.5
ns
ns
PD
Output Clock to Data Propagation Delay,
LVDS Mode
Rising/Falling Edge
Rising/Falling Edge
0.16
DC
Output Clock to Data Propagation Delay,
CMOS Mode
t
-0.1
0.4
0.2
0.65
ns
ns
DC
Synchronous Clock Divider Reset Setup
Time (with respect to the positive edge of
CLKP)
t
0.06
RSTS
Synchronous Clock Divider Reset Hold Time
(with respect to the positive edge of CLKP)
t
0.02
52
0.35
ns
µs
RSTH
Synchronous Clock Divider Reset Recovery
Time
t
DLL recovery time after
Synchronous Reset
RSTRT
L
Latency (Pipeline Delay)
Overvoltage Recovery
10
1
cycles
cycles
t
OVR
FN7572 Rev 2.00
December 5, 2012
Page 13 of 35
ISLA214P
Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
SPI INTERFACE (Notes 13, 14)
SCLK Period
SYMBOL
CONDITION
(Note 5)
TYP
(Note 5)
UNITS
t
Write Operation
16
16
28
5
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
CLK
t
Read Operation
Read or Write
Write
CLK
CSB to SCLKSetup Time
CSB after SCLK Hold Time
CSB after SCLK↓ Hold Time
Data Valid to SCLK Setup Time
Data Valid after SCLK Hold Time
Data Valid after SCLK↓ Time
NOTES:
t
S
t
H
t
Read
16
6
HR
t
Write
DS
DH
t
Read or Write
Read
4
5
t
DVR
12. The relative propagation delay is the difference in propagation time between any two devices that are matched in temperature and voltage, and is
specified over the full operating temperature and voltage range.
13. SPI Interface timing is directly proportional to the ADC sample period (t ). Values above reflect multiples of a 4ns sample period, and must be scaled
S
proportionally for lower sample rates. ADC sample clock must be running for SPI communication.
14. The SPI may operate asynchronously with respect to the ADC sample clock.
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, T = +25°C,
A
A
= -1dBFS, f = 105MHz, f
= 250MSPS.
IN
IN
SAMPLE
95
90
-60
-65
HD3 @ 250MSPS
HD2 @ 250MSPS
SFDR @ 130MSPS
-70
85
80
75
70
65
60
SFDR @ 250MSPS
-75
-80
-85
-90
HD2 @ 130MSPS
HD3 @ 130MSPS
-95
SNR @ 250MSPS
-100
-105
SNR @ 130MSPS
0
100
200
INPUT FREQUENCY (MHz)
FIGURE 4. HD2 AND HD3 vs f
300
400
500
600
0
100
200
INPUT FREQUENCY (MHz)
FIGURE 3. SNR AND SFDR vs f
300
400
500
600
IN
IN
FN7572 Rev 2.00
December 5, 2012
Page 14 of 35
ISLA214P
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, T = +25°C,
A
A
= -1dBFS, f = 105MHz, f
= 250MSPS. (Continued)
IN
IN
SAMPLE
-30
-40
100
90
SFDR (dBfs)
HD2 (dBc)
80
-50
70
SNR (dBfs)
-60
60
HD3 (dBc)
-70
SFDR (dBc)
50
HD2 (dBfs)
HD3 (dBfs)
SNR (dBc)
-80
40
30
20
10
-90
-100
-110
-60
-50
-40
-30
-20
-10
0
-60
-50
-40
-30
-20
-10
0
INPUT AMPLITUDE (dBFS)
INPUT AMPLITUDE (dBFS)
FIGURE 5. SNR AND SFDR vs A
FIGURE 6. HD2 AND HD3 vs A
IN
IN
90
85
80
75
70
-75
-80
HD3
HD2
-85
SFDR
SNR
-90
-95
-100
-105
70
90
110
130 150
SAMPLE RATE (MSPS)
FIGURE 8. HD2 AND HD3 vs f
170 190
210 230
250
70
90
110
130
150
170
190
210
230
250
SAMPLE RATE (MSPS)
FIGURE 7. SNR AND SFDR vs f
SAMPLE
SAMPLE
500
475
450
425
400
375
350
325
300
1.0
0.8
0.6
0.4
0.2
0
LVDS
-0.2
-0.4
-0.6
-0.8
-1.0
CMOS
40
60
80 100 120 140 160 180 200 220 240
SAMPLE RATE (MSPS)
0
2000 4000 6000 8000 10000 12000 14000 16000
CODES
FIGURE 10. DIFFERENTIAL NONLINEARITY
FIGURE 9. POWER vs f
IN 3mA LVDS MODE (SDR) AND
SAMPLE
CMOS MODE (DDR)
FN7572 Rev 2.00
December 5, 2012
Page 15 of 35
ISLA214P
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, T = +25°C,
A
A
= -1dBFS, f = 105MHz, f
= 250MSPS. (Continued)
IN
IN
SAMPLE
4
3
85
80
75
70
65
60
2
1
0
SFDR AIN = -2dBFS
SFDR AIN = -1dBFS
-1
-2
-3
-4
SNR
AIN = -1dBFS
0.75
0.85
0.95
1.05
1.15
0
2000 4000 6000 8000 10000 12000 14000 16000
CODES
INPUT COMMON MODE (V)
FIGURE 11. INTEGRAL NONLINEARITY
FIGURE 12. SNR AND SFDR vs VCM
0
-20
70000
60000
50000
40000
30000
20000
10000
0
64687
60851
A
= -1.0 dBFS
IN
SNR = 73.4 dBFS
SFDR = 80.7 dBc
SINAD = 72.5 dBFS
-40
35036
-60
23400
-80
10120
590 43
-100
-120
4668
23 581
0
0
0
1
0
0
0
20
40
60
80
100
120
8170 8172 8174 8176 8178 8180 8182 8184
CODE
FREQUENCY (MHz)
FIGURE 13. NOISE HISTOGRAM
FIGURE 14. SINGLE-TONE SPECTRUM @ 105MHz
0
-20
0
A
= -1.0 dBFS
IN
A
= -1.0 dBFS
IN
SNR = 72.6 dBFS
SFDR = 78.1 dBc
SINAD = 71.2 dBFS
SNR = 70.9 dBFS
SFDR = 78.4 dBc
SINAD = 70.1 dBFS
-20
-40
-40
-60
-60
-80
-80
-100
-100
-120
-120
0
20
40
FREQUENCY (MHz)
FIGURE 15. SINGLE-TONE SPECTRUM @ 190MHz
60
80
100
120
0
20
40
FREQUENCY (MHz)
FIGURE 16. SINGLE-TONE SPECTRUM @ 363MHz
60
80
100
120
FN7572 Rev 2.00
December 5, 2012
Page 16 of 35
ISLA214P
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, T = +25°C,
A
A
= -1dBFS, f = 105MHz, f
= 250MSPS. (Continued)
IN
IN
SAMPLE
0
0
-20
IMD2
IMD3
2ND HARMONICS
3RD HARMONICS
IMD2
IMD3
2ND HARMONICS
3RD HARMONICS
-20
-40
-60
-40
-60
IMD3 = -97 dBFS
IMD3 = -87 dBFS
-80
-80
-100
-120
-100
-120
0
20
40
60
80
100
120
0
20
40
60
80
100
120
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 17. TWO-TONE SPECTRUM (F1 = 70MHz, F2 = 71MHz AT
-7dBFS)
FIGURE 18. TWO-TONE SPECTRUM (F1 = 170MHz, F2 = 171MHz AT
-7dBFS)
desired, the RESETN pin should be connected to an open-drain
driver with an off-state/high impedance state leakage of less
than 0.5mA to assure exit from the reset state so calibration can
start.
Theory of Operation
Functional Description
The ISLA214P is based on a 14-bit, 250MSPS A/D converter core
that utilizes a pipelined successive approximation architecture
(see Figure 19). The input voltage is captured by a Sample-Hold
Amplifier (SHA) and converted to a unit of charge. Proprietary
charge-domain techniques are used to successively compare the
input to a series of reference charges. Decisions made during the
successive approximation operations determine the digital code
for each input value. Digital error correction is also applied,
resulting in a total latency of 10 clock cycles. This is evident to the
user as a latency between the start of a conversion and the data
being available on the digital outputs.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 20. Calibration status can be
determined by reading the cal_status bit (LSB) at 0xB6. This bit is
‘0’ during calibration and goes to a logic ‘1’ when calibration is
complete. The data outputs produce 0xCCCC during calibration;
this can also be used to determine calibration status.
If the selectable clock divider is set to 1 (default), the output
clock (CLKOUTP/CLKOUTN) will not be affected by the assertion
of RESETN. If the selectable clock divider is set to 2 or 4, the
output clock is set low while RESETN is asserted (low). Normal
operation of the output clock resumes at the next input clock
edge (CLKP/CLKN) after RESETN is de-asserted. At 250MSPS,
the nominal calibration time is 200ms, while the maximum
calibration time is 550ms.
Power-On Calibration
As mentioned previously, the cores perform a self-calibration at
start-up. An internal power-on-reset (POR) circuit detects the
supply voltage ramps and initiates the calibration when the
analog and digital supply voltages are above a threshold. The
following conditions must be adhered to for the power-on
calibration to execute successfully.
• A frequency-stable conversion clock must be applied to the
CLKP/CLKN pins
• DNC pins must not be connected
• SDO has an internal pull-up and should not be driven externally
• RESETN is pulled low by the ADC internally during POR.
External driving of RESETN is optional.
• SPI communications must not be attempted
A user-initiated reset can subsequently be invoked in the event
that the above conditions cannot be met at power-up.
After the power supply has stabilized the internal POR releases
RESETN and an internal pull-up pulls it high, which starts the
calibration sequence. If a subsequent user-initiated reset is
FN7572 Rev 2.00
December 5, 2012
Page 17 of 35
ISLA214P
CLOCK
GENERATION
INP
INN
2.5-BIT
FLASH
6- STAGE
1.5-BIT/ STAGE
3- STAGE
1-BIT/ STAGE
3-BIT
FLASH
2.5-BIT
FLASH
SHA
+
1.25V
–
DIGITAL
ERROR
CORRECTION
LVDS/ LVCMOS
OUTPUTS
FIGURE 19. A/D CORE BLOCK DIAGRAM
Figures 21 through 26 show the effect of temperature on SNR
and SFDR performance with power on calibration performed at
-40°C, +25°C, and +85°C. Each plot shows the variation of
SNR/SFDR across temperature after a single power on
calibration at -40°C, +25°C and +85°C. Best performance is
typically achieved by a user-initiated power on calibration at the
operating conditions, as stated earlier. However, it can be seen
that performance drift with temperature is not a very strong
function of the temperature at which the power on calibration is
performed.
CLKN
CLKP
CALIBRATION
TIME
RESETN
CALIBRATION
BEGINS
CAL_STATUS
BIT
CALIBRATION
COMPLETE
CLKOUTP
FIGURE 20. CALIBRATION TIMING
User Initiated Reset
Recalibration of the A/D can be initiated at any time by driving
the RESETN pin low for a minimum of one clock cycle. An
open-drain driver with a drive strength in its high impedance
state of less than 0.5mA is recommended, as RESETN has an
internal high impedance pull-up to OVDD. As is the case during
power-on reset, RESETN and DNC pins must be in the proper
state for the calibration to successfully execute.
The performance of the ISLA214P changes with variations in
temperature, supply voltage or sample rate. The extent of these
changes may necessitate recalibration, depending on system
performance requirements. Best performance will be achieved
by recalibrating the A/D under the environmental conditions at
which it will operate.
A supply voltage variation of <100mV will generally result in an
SNR change of <0.5dBFS and SFDR change of <3dBc.
In situations where the sample rate is not constant, best results
will be obtained if the device is calibrated at the highest sample
rate. Reducing the sample rate by less than 80MSPS will typically
result in an SNR change of <0.5dBFS and an SFDR change of
<3dBc.
FN7572 Rev 2.00
December 5, 2012
Page 18 of 35
ISLA214P
Temperature Calibration
95
90
85
80
76
130MSPS
250MSPS
75
200MSPS
130MSPS
250MSPS
74
73
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
200MSPS
-35
72
-40
-40
-30
-25
-20
-35
-30
-25
-20
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 22. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
FIGURE 21. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT -40°C, f = 105MHz
DEVICE CALIBRATED AT -40°C, f = 105MHz
IN
IN
76
95
130MSP
75
90
85
80
75
250MSPS
130MSPS
200MSPS
74
200MSPS
73
250MSPS
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
72
5
10
15
20
TEMPERATURE (°C)
FIGURE 23. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
25
30
35
40
45
5
10
15
20
25
30
35
40
45
TEMPERATURE (°C)
FIGURE 24. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +25°C, f = 105MHz
DEVICE CALIBRATED AT +25°C, f = 105MHz
IN
IN
76
75
74
73
72
90
85
80
75
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
250MSPS
130MSPS
130MSPS
200MSPS
200MSPS
250MSPS
-2dBFS ANALOG INPUT
-1dBFS ANALOG INPUT
65
67
69
71
73
75
77
79
81
83
85
65
70
75
80
85
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 25. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +85°C, f = 105MHz
FIGURE 26. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +85°C, f = 105MHz
IN
IN
FN7572 Rev 2.00
December 5, 2012
Page 19 of 35
ISLA214P
transformer and low shunt resistance are recommended for
optimal performance.
Analog Input
A single fully differential input (VINP/VINN) connects to the
sample and hold amplifier (SHA) of each unit A/D. The ideal
full-scale input voltage is 2.0V, centered at the VCM voltage of
0.94V as shown in Figure 27.
A/D
1.8
1.4
1.0
0.6
0.2
VINN
VINP
VCM
0.94V
1.0V
FIGURE 30. DIFFERENTIAL AMPLIFIER INPUT
A differential amplifier, as shown in the simplified block diagram
in Figure 30, can be used in applications that require
DC-coupling. In this configuration, the amplifier will typically
dominate the achievable SNR and distortion performance.
Intersil’s new ISL552xx differential amplifier family can also be
used in certain AC applications with minimal performance
degradation. Contact the factory for more information.
FIGURE 27. ANALOG INPUT RANGE
Best performance is obtained when the analog inputs are driven
differentially. The common-mode output voltage, VCM, should be
used to properly bias the inputs as shown in Figures 28 through
30. An RF transformer will give the best noise and distortion
performance for wideband and/or high intermediate frequency
(IF) inputs. Two different transformer input schemes are shown in
Figures 28 and 29.
Clock Input
The clock input circuit is a differential pair (see Figure 44).
Driving these inputs with a high level (up to 1.8V
on each
P-P
ADT1-1WT
ADT1-1WT
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels. The clock input is functional with
AC-coupled LVDS, LVPECL, and CML drive levels. To maintain the
lowest possible aperture jitter, it is recommended to have high
slew rate at the zero crossing of the differential clock input
signal.
1000pF
A/D
VCM
0.1µF
The recommended drive circuit is shown in Figure 31. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may impact
SNR performance. The clock inputs are internally self-biased to
AVDD/2 to facilitate AC coupling.
FIGURE 28. TRANSFORMER INPUT FOR GENERAL PURPOSE
APPLICATIONS
TX-2-5-1
ADTL1-12
1000pF
TC4-19G2+
1000pF
CLKP
200
A / D
VCM
0.01µF
1000pF
FIGURE 29. TRANSMISSION-LINE TRANSFORMER INPUT FOR
HIGH IF APPLICATIONS
CLKN
1000pF
1000pF
This dual transformer scheme is used to improve common-mode
rejection, which keeps the common-mode level of the input
matched to VCM. The value of the shunt resistor should be
determined based on the desired load impedance. The
differential input resistance of the ISLA214P is 600.
FIGURE 31. RECOMMENDED CLOCK DRIVE
A selectable 2x or 4x frequency divider is provided in series with
the clock input. The divider can be used in the 2x mode with a
sample clock equal to twice the desired sample rate or in 4x
mode with a sample clock equal to four times the desired
sample rate. This allows the use of the Phase Slip feature, which
enables synchronization of multiple ADCs. The Phase Slip feature
can be used as an alternative to using the CLKDIVRST pins to
synchronize ADCs in a multiple ADC system.
The SHA design uses a switched capacitor input stage (see
Figure 43), which creates current spikes when the sampling
capacitance is reconnected to the input voltage. This causes a
disturbance at the input which must settle before the next
sampling point. Lower source impedance will result in faster
settling and improved performance. Therefore a 2:1 or 1:1
FN7572 Rev 2.00
December 5, 2012
Page 20 of 35
ISLA214P
TABLE 1. CLKDIV PIN SETTINGS
Digital Outputs
Output data is available as a parallel bus in
CLKDIV PIN
DIVIDE RATIO
LVDS-compatible(default) or CMOS modes. In either case, the data
is presented in either double data rate (DDR) or single data rate
(default) format. Figures 1A and 1B show the timing relationships
for LVDS and CMOS modes, respectively.
AVSS
Float
AVDD
2
1
4
Additionally, the drive current for LVDS mode can be set to a
nominal 3mA(default) or a power-saving 2mA. The lower current
setting can be used in designs where the receiver is in close
physical proximity to the A/D. The applicability of this setting is
dependent upon the PCB layout, therefore the user should
experiment to determine if performance degradation is
observed.
The clock divider can also be controlled through the SPI port,
which overrides the CLKDIV pin setting. See “SPI Physical
Interface” on page 25. A delay-locked loop (DLL) generates
internal clock signals for various stages within the charge
pipeline. If the frequency of the input clock changes, the DLL may
take up to 52μs to regain lock at 250MSPS. The lock time is
inversely proportional to the sample rate.
The output mode can be controlled through the SPI port, by
writing to address 0x73, see “Serial Peripheral Interface” on
page 25.
The DLL has two ranges of operation, slow and fast. The slow
range can be used for sample rates between 40MSPS and
100MSPS, while the default fast range can be used from
80MSPS to the maximum specified sample rate.
An external resistor creates the bias for the LVDS drivers. A 10k,
1% resistor must be connected from the RLVDS pin to OVSS.
Jitter
Power Dissipation
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter (t ) and SNR is shown in Equation 1 and is
The power dissipated by the ISLA214P is primarily dependent on
the sample rate and the output modes: LVDS vs CMOS and DDR
vs SDR. There is a static bias in the analog supply, while the
remaining power dissipation is linearly related to the sample
rate. The output supply dissipation changes to a lesser degree in
LVDS mode, but is more strongly related to the clock frequency in
CMOS mode.
J
illustrated in Figure 32.
1
-------------------
SNR = 20 log
(EQ. 1)
10
2f
t
IN J
100
95
90
85
80
75
70
65
60
55
Nap/Sleep
tj = 0.1ps
Portions of the device may be shut down to save power during
times when operation of the A/D is not required. Two power saving
modes are available: Nap, and Sleep. Nap mode reduces power
dissipation to < 60mW while Sleep mode reduces power
dissipation to 9mW typically.
14 BITS
tj = 1ps
12 BITS
tj = 10ps
10 BITS
All digital outputs (Data, CLKOUT and OR) are placed in a high
impedance state during Nap or Sleep. The input clock should
remain running and at a fixed frequency during Nap or Sleep, and
CSB should be high. Recovery time from Nap mode will increase
if the clock is stopped, since the internal DLL can take up to 52µs
to regain lock at 250MSPS.
tj = 100ps
50
1M
10M
INPUT FREQUENCY (Hz)
FIGURE 32. SNR vs CLOCK JITTER
100M
1G
By default after the device is powered on, the operational state is
controlled by the NAPSLP pin as shown in Table 2.
This relationship shows the SNR that would be achieved if clock
jitter were the only non-ideal factor. In reality, achievable SNR is
limited by internal factors such as linearity, aperture jitter and
thermal noise. Internal aperture jitter is the uncertainty in the
sampling instant shown in Figure1A. The internal aperture jitter
combines with the input clock jitter in a root-sum-square fashion,
since they are not statistically correlated, and this determines
the total jitter in the system. The total jitter, combined with other
noise sources, then determines the achievable SNR.
TABLE 2. NAPSLP PIN SETTINGS
NAPSLP PIN
AVSS
MODE
Normal
Sleep
Nap
Float
AVDD
Voltage Reference
The power-down mode can also be controlled through the SPI
port, which overrides the NAPSLP pin setting. Details on this are
contained in “Serial Peripheral Interface” on page 25.
A temperature compensated internal voltage reference provides
the reference charges used in the successive approximation
operations. The full-scale range of each A/D is proportional to the
reference voltage. The nominal value of the voltage reference is
1.25V.
FN7572 Rev 2.00
December 5, 2012
Page 21 of 35
ISLA214P
Mapping of the input voltage to the various data formats is
shown in Table 3.
Data Format
Output data can be presented in three formats: two’s
complement (default), Gray code and offset binary. The data
format can be controlled through the SPI port, by writing to
address 0x73. Details on this are contained in “Serial Peripheral
Interface” on page 25.
TABLE 3. INPUT VOLTAGE TO OUTPUT CODE MAPPING
INPUT
TWO’S
VOLTAGE
OFFSET BINARY
COMPLEMENT
GRAY CODE
–Full Scale 00 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000
Offset binary coding maps the most negative input voltage to
code 0x000 (all zeros) and the most positive input to 0xFFF (all
ones). Two’s complement coding simply complements the MSB
of the offset binary representation.
–Full Scale 00 0000 0000 0001 10 0000 0000 0001 00 0000 0000 0001
+ 1LSB
Mid–Scale 10 0000 0000 0000 00 0000 0000 0000 11 0000 0000 0000
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current bit
position and the next most significant bit. Figure 33 shows this
operation.
+Full Scale 11 1111 1111 1110 01 1111 1111 1110 10 0000 0000 0001
– 1LSB
+Full Scale 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000
Clock Divider Synchronous Reset
BINARY
13
12
11
1
0
• • • •
If the selectable clock divider is used, the ADC's internal sample
clock will be at half the frequency (DIV = 2) or one quarter the
frequency (DIV = 4) of the device clock. The phase relationship
between the sample clock and the device clock is initially
indeterminate. An output clock (CLKOUTP, CLKOUTN) is provided
to facilitate latching of the sampled data and estimation of the
internal sample clock's phase. The output clock has a fixed
phase relationship to the sample clock. When the selectable
clock divider is set to 2 or 4, the output clock's phase relationship
to the sample clock remains fixed but is initially indeterminate
with respect to the device clock. When the selectable clock
divider is set to 2 or 4, the synchronous clock divider reset
feature allows the phase of the internal sample clock and the
output clock to be synchronized (refer to Figure 35) with respect
to the device clock. This simplifies data capture in systems
employing multiple A/Ds where sampling of the inputs is desired
to be synchronous.
• • • •
• • • •
GRAY CODE
13
12
11
1
0
FIGURE 33. BINARY TO GRAY CODE CONVERSION
Converting back to offset binary from Gray code must be done
recursively, using the result of each bit for the next lower bit as
shown in Figure 34.
GRAY CODE
13
12
11
1
0
• • • •
The reset signal must be well-timed with respect to the sample
clock (See “Switching Specifications” on page 13).
A 100Ω differential termination resistor must be supplied
between CLKDIVRSTP and CLKDIVRSTN, external to the ADC, (on
the PCB) and should be located as close to the CLKDIVRSTP/N
pins as possible.
• • • •
• • • •
• • • •
BINARY
13
12
11
1
0
FIGURE 34. GRAY CODE TO BINARY CONVERSION
FN7572 Rev 2.00
December 5, 2012
Page 22 of 35
ISLA214P
DEVICE CLOCK
INPUT
L+td
(Note 15)
ANALOG INPUT
CLKDIVRSTP
s1
tRSTH
(Note 16)
tRSTS
tRSTRT
ADC1 OUTPUT DATA
s0
ODD
s0
EVEN
s1
ODD
s1
EVEN
ADC1 CLKOUTP
ADC2 OUTPUT DATA
s0
ODD
s0
EVEN
s1
ODD
s1
EVEN
(NoteA1D7C) 2 CLKOUTP
(PHASE 1)
(Note 17)
ADC2 CLKOUTP
(PHASE 2)
NOTES:
15. Delay equals fixed pipeline latency (L cycles of sample clock) plus fixed analog propagation delay, td.
16. CLKDIVRSTP setup and hold times are with respect to input sample clock rising edge.
CLKDIVRSTN is not shown, but must be driven, and is the compliment of CLKDIVRSTP.
17. Either Output Clock Phase (phase 1 or phase 2 ) equally likely prior to synchronization.
FIGURE 35. SYNCHRONOUS RESET OPERATION, CLOCK DIVIDE = 2, DDR-MODE
CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
FIGURE 36. MSB-FIRST ADDRESSING
CSB
SCLK
SDIO
A0
A1
A2
A11
A12
W0
W1
R/W
D0
D1
D2
D3
D4
D5
D6
D7
FIGURE 37. LSB-FIRST ADDRESSING
FN7572 Rev 2.00
December 5, 2012
Page 23 of 35
ISLA214P
t
DSW
t
CLK
t
t
HI
H
t
DHW
CSB
t
t
S
LO
SCLK
SDIO
R/W W1 W0 A12 A11 A10 A9
A8
A7
D0
D5
D4
D3
D2
D1
SPI WRITE
FIGURE 38. SPI WRITE
tDSW
tCLK
tHR
tHI
tDVR
tS
CSB
tDHW
tLO
SCLK
WRITING A READ COMMAND
A9 A2 A1
READING DATA
)
( 3 WIRE MODE
D2 D1 D0
SDIO
SDO
A0
D7
D6
D3
W1 W 0
A12 A11
A10
R/W
( 4 WIRE MODE)
D3 D2 D1
D7
D0
SPI READ
FIGURE 39. SPI READ
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD 2
FIGURE 40. 2-BYTE TRANSFER
LAST LEGAL
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
FIGURE 41. N-BYTE TRANSFER
FN7572 Rev 2.00
December 5, 2012
Page 24 of 35
ISLA214P
A/D (based on the R/W bit status). The data transfer will
continue as long as CSB remains low and SCLK is active. Stalling
of the CSB pin is allowed at any byte boundary
(instruction/address or data) if the number of bytes being
transferred is three or less. For transfers of four bytes or more,
CSB is allowed to stall in the middle of the instruction/address
bytes or before the first data byte. If CSB transitions to a high
state after that point the state machine will reset and terminate
the data transfer.
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate
configuration of the device and to optimize performance. The
SPI bus consists of chip select (CSB), serial clock (SCLK) serial
data output (SDO), and serial data input/output (SDIO). The
maximum SCLK rate is equal to the A/D sample rate (f
)
SAMPLE
divided by 16 for both write operations and read operations. At
= 250MHz, maximum SCLK is 15.63MHz for writing
f
SAMPLE
and read operations. There is no minimum SCLK rate.
TABLE 4. BYTE TRANSFER SELECTION
The following sections describe various registers that are used to
configure the SPI or adjust performance or functional parameters.
Many registers in the available address space (0x00 to 0xFF) are
not defined in this document. Additionally, within a defined
register there may be certain bits or bit combinations that are
reserved. Undefined registers and undefined values within defined
registers are reserved and should not be selected. Setting any
reserved register or value may produce indeterminate results.
[W1:W0]
00
BYTES TRANSFERRED
1
01
2
3
10
11
4 or more
Figures 40 and 41 on page 24 illustrate the timing relationships
for 2-byte and N-byte transfers, respectively. The operation for a
3-byte transfer can be inferred from these diagrams.
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for the data
transfer. By default, all data is presented on the serial data
input/output (SDIO) pin in three-wire mode. The state of the SDIO
pin is set automatically in the communication protocol
(described in the following). A dedicated serial data output pin
(SDO) can be activated by setting 0x00[7] high to allow operation
in four-wire mode.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register. Bit order
can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB
first) to accommodate various micro controllers.
The SPI port operates in a half duplex master/slave
configuration, with the ISLA214P functioning as a slave. Multiple
slave devices can interface to a single master in three-wire mode
only, since the SDO output of an unaddressed device is asserted
in four wire mode.
Bit 7 SDO Active
Bit 6 LSB First
Setting this bit high configures the SPI to interpret serial data
as arriving in LSB to MSB order.
The chip-select bar (CSB) pin determines when a slave device is
being addressed. Multiple slave devices can be written to
concurrently, but only one slave device can be read from at a
given time (again, only in three-wire mode). If multiple slave
devices are selected for reading at the same time, the results will
be indeterminate.
Bit 5 Soft Reset
Setting this bit high resets all SPI registers to default values.
Bit 4 Reserved
This bit should always be set high.
The communication protocol begins with an instruction/address
phase. The first rising SCLK edge following a high-to-low
transition on CSB determines the beginning of the two-byte
instruction/address command; SCLK must be static low before
the CSB transition. Data can be presented in MSB-first order or
LSB-first order. The default is MSB-first, but this can be changed
by setting 0x00[6] high. Figures 36 and 37 show the appropriate
bit ordering for the MSB-first and LSB-first modes, respectively. In
MSB-first mode, the address is incremented for multi-byte
transfers, while in LSB-first mode it’s decremented.
Bits 3:0 These bits should always mirror bits 4:7 to avoid
ambiguity in bit ordering.
ADDRESS 0X02: BURST_END
If a series of sequential registers are to be set, burst mode can
improve throughput by eliminating redundant addressing. The
burst is ended by pulling the CSB pin high. Setting the burst_end
address determines the end of the transfer; during a write
operation, the user must be cautious to transmit the correct
number of bytes based on the starting and ending addresses.
In the default mode, the MSB is R/W, which determines if the
data is to be read (active high) or written. The next two bits, W1
and W0, determine the number of data bytes to be read or
written (see Table 4). The lower 13 bits contain the first address
for the data transfer. This relationship is illustrated in Figure 38,
and timing values are given in “Switching Specifications” on
page 13.
Bits 7:0 Burst End Address
This register value determines the ending address of the burst
data.
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read from the
FN7572 Rev 2.00
December 5, 2012
Page 25 of 35
ISLA214P
TABLE 6. COARSE GAIN ADJUSTMENT
0x22[3:0] core 0 NOMINAL COARSE GAIN ADJUST
Device Information
ADDRESS 0X08: CHIP_ID
0x26[3:0] core 1
(%)
+2.8
+1.4
-2.8
-1.4
Bit3
Bit2
Bit1
Bit0
ADDRESS 0X09: CHIP_VERSION
The generic die identifier and a revision number, respectively, can
be read from these two registers.
Device Configuration/Control
A common SPI map, which can accommodate single-channel or
multi-channel devices, is used for all Intersil A/D products.
TABLE 7. MEDIUM AND FINE GAIN ADJUSTMENTS
0x23[7:0]
0x24[7:0]
PARAMETER
Steps
MEDIUM GAIN
FINE GAIN
ADDRESS 0X20: OFFSET_COARSE_ADC0
ADDRESS 0X21: OFFSET_FINE_ADC0
256
-2%
256
–Full Scale (0x00)
Mid–Scale (0x80)
+Full Scale (0xFF)
Nominal Step Size
-0.20%
0.00%
The input offset of the A/D core can be adjusted in fine and
coarse steps. Both adjustments are made via an 8-bit word as
detailed in Table 5. The data format is twos complement.
0.00%
+2%
+0.2%
0.016%
0.0016%
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register. Bit 0 in register 0xFE must be set high
to enable updates written to 0x20 and 0x21 to be used by the
ADC (see description for 0xFE).
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By default,
the tri-level NAPSLP pin can select normal operation, nap or
sleep modes (refer to“Nap/Sleep” on page 21). This functionality
can be overridden and controlled through the SPI. This is an
indexed function when controlled from the SPI, but a global
function when driven from the pin. This register is not changed by
a Soft Reset.
TABLE 5. OFFSET ADJUSTMENTS
0x20[7:0]
0x21[7:0]
PARAMETER
Steps
COARSE OFFSET
FINE OFFSET
TABLE 8. POWER-DOWN CONTROL
0x25[2:0]
255
255
–Full Scale (0x00)
Mid–Scale (0x80)
+Full Scale (0xFF)
Nominal Step Size
-133LSB (-47mV)
0.0LSB (0.0mV)
+133LSB (+47mV)
1.04LSB (0.37mV)
-5LSB (-1.75mV)
0.0LSB
VALUE
000
001
POWER DOWN MODE
Pin Control
+5LSB (+1.75mV)
0.04LSB (0.014mV)
Normal Operation
Nap Mode
010
100
Sleep Mode
ADDRESS 0X22: GAIN_COARSE_ADC0
ADDRESS 0X23: GAIN_MEDIUM_ADC0
ADDRESS 0X24: GAIN_FINE_ADC0
ADDRESS 0X26: OFFSET_COARSE_ADC1
ADDRESS 0X27: OFFSET_FINE_ADC1
The input offset of A/D core#1 can be adjusted in fine and
coarse steps in the same way that offset for core#0 can be
adjusted. Both adjustments are made via an 8-bit word as
detailed in Table 5. The data format is two’s complement.
Gain of the A/D core can be adjusted in coarse, medium and fine
steps. Coarse gain is a 4-bit adjustment while medium and fine
are 8-bit. Multiple Coarse Gain Bits can be set for a total
adjustment range of ±4.2%. (‘0011’ -4.2% and ‘1100’ +4.2%)
It is recommended to use one of the coarse gain settings (-4.2%,
-2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the
registers at 0x0023 and 0x24.
The default value of each register will be the result of the self-
calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register. Bit 0 in register 0xFE must be set high
to enable updates written to 0x26 and 0x27 to be used by the
ADC (see description for 0xFE).
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register. Bit 0 in register 0xFE must be set high
to enable updates written to 0x23 and 0x24 to be used by the
ADC (see description for 0xFE).
FN7572 Rev 2.00
December 5, 2012
Page 26 of 35
ISLA214P
LVCMOS. Additionally, the drive strength in LVDS mode can be set
high (default,3mA or low (2mA).
ADDRESS 0X28: GAIN_COARSE_ADC1
ADDRESS 0X29: GAIN_MEDIUM_ADC1
ADDRESS 0X2A: GAIN_FINE_ADC1
Data can be coded in three possible formats: two’s complement
(default), Gray code or offset binary. See Table 11.
Gain of A/D core #1 can be adjusted in coarse, medium and fine
steps in the same way that core #0 can be adjusted. Coarse gain is
a 4-bit adjustment while medium and fine are 8-bit. Multiple
Coarse Gain Bits can be set for a total adjustment range of ±4.2.
Bit 0 in register 0xFE must be set high to enable updates written to
0x29 and 0x2A to be used by the ADC (see description for 0xFE).
This register is not changed by a Soft Reset.
TABLE 10. OUTPUT MODE CONTROL
0x73[7:5]
VALUE
OUTPUT MODE
LVDS 3mA (Default)
LVDS 2mA
000
Global Device Configuration/Control
001
100
LVCMOS
ADDRESS 0X71: PHASE_SLIP
TABLE 11. OUTPUT FORMAT CONTROL
0x73[2:0]
The output data clock is generated by dividing down the A/D input
sample clock. Some systems with multiple A/Ds can more easily latch
the data from each A/D by controlling the phase of the output data
clock. This control is accomplished through the use of the phase_slip
SPI feature, which allows the rising edge of the output data clock to be
advanced by one input clock period, as shown in the Figure 42.
Execution of a phase_slip command is accomplished by first writing a
'0' to bit 0 at address 0x71, followed by writing a '1' to bit 0 at address
0x71.
VALUE
OUTPUT FORMAT
Two’s Complement (Default)
Gray Code
000
010
100
Offset Binary
ADDRESS 0X74: OUTPUT_MODE_B
Bit 6 DLL Range
ADC Input
Clock (500MHz)
This bit sets the DLL operating range to fast (default) or slow.
2ns
4ns
Internal clock signals are generated by a delay-locked loop (DLL),
which has a finite operating range. Table 12 shows the allowable
sample rate ranges for the slow and fast settings.
Output Data
Clock (250MHz)
No clock_slip
2ns
Output Data
Clock (250MHz)
1 clock_slip
Bit 4 DDR Enable
Set to a ‘1’ to enable DDR.
TABLE 12. DLL RANGES
Output Data
Clock (250MHz)
2 clock_slip
DLL RANGE
Slow
MIN
40
MAX
100
250
UNIT
MSPS
MSPS
FIGURE 42. PHASE SLIP
Fast
80
ADDRESS 0X72: CLOCK_DIVIDE
ADDRESS 0XB6: CALIBRATION STATUS
The ISLA214P has a selectable clock divider that can be set to
divide by four, two or one (no division). By default, the tri-level
CLKDIV pin selects the divisor. This functionality can be
overridden and controlled through the SPI, as shown in Table 9.
This register is not changed by a Soft Reset.
The LSB at address 0xB6 can be read to determine calibration
status. The bit is ‘0’ during calibration and goes to a logic ‘1’
when calibration is complete.This register is unique in that it can
be read after POR at calibration, unlike the other registers on
chip, which can’t be read until calibration is complete.
TABLE 9. CLOCK DIVIDER SELECTION
DEVICE TEST
0x72[2:0]
CLOCK DIVIDER
The ISLA214P can produce preset or user defined patterns on the
digital outputs to facilitate in-situ testing. A user can pick from
preset built-in patterns by writing to the output test mode field [7:4]
at 0xC0 or user defined patterns by writing to the user test mode
field [2:0] at 0xC0. The user defined patterns should be loaded at
address space 0xC1 through 0xD0, see the “SPI Memory Map” on
page 30 for more detail.The predefined patterns are shown in
Table 13. The test mode is enabled asynchronously to the sample
clock, therefore several sample clock cycles may elapse before the
data is present on the output bus.
VALUE
000
Pin Control
001
Divide by 1
010
Divide by 2
100
Divide by 4
other
Not Allowed
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output format
of the data, as well as the logical coding. The ISLA214P can
present output data in two physical formats: LVDS (default) or
FN7572 Rev 2.00
December 5, 2012
Page 27 of 35
ISLA214P
ADDRESS 0XC0: TEST_IO
ADDRESS 0XCD: USER_PATT7_LSB
ADDRESS 0XCE: USER_PATT7_MSB
Bits 7:4 Output Test Mode
These bits set the test mode according to Table 13. Other
values are reserved.User test patterns loaded at 0xC1 through
0xD0 are also available by writing ‘1000’ to [7:4] at 0xC0 and a
pattern depth value to [2:0] at 0xC0. See the memory map.
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 7.
ADDRESS 0XCF: USER_PATT8_LSB
ADDRESS 0XD0: USER_PATT8_MSB
Bits 2:0 User Test Mode
The three LSBs in this register determine the test pattern in
combination with registers 0xC1 through 0xD0. Refer to the
SPI Memory Map on page 30.
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 8.
ADDRESS 0XFE: OFFSET/GAIN_ADJUST_ENABLE
TABLE 13. OUTPUT TEST MODES
0xC0[7:4]
Bit 0 at this register must be set high to enable adjustment of
offset coarse and fine adjustments (0x20 and 0x21), and gain
medium and fine adjustments (0x23 and 0x24). It is
recommended that new data be written to the offset and gain
adjustment registers and while Bit 0 is a '0'. Subsequently, Bit 0
should be set to '1' to allow the values written to the
aforementioned registers to be used by the ADC. Bit 0 should be
set to a '0' upon completion.
VALUE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
OUTPUT TEST MODE
WORD 1
WORD 2
Off
Midscale
0x8000
0xFFFF
0x0000
N/A
N/A
N/A
Positive Full-Scale
Negative Full-Scale
SDR/DDR Dependent
Reserved
N/A
N/A
Digital Temperature Sensor
N/A
N/A
ADDRESS 0X4B: TEMP_COUNTER_HIGH
Reserved
N/A
N/A
Bits [2:0] of this register hold the 3 MSBs of the 11-bit
temperature code.
SDR/DDR Dependent
User Pattern
Reserved
N/A
N/A
user_patt1
N/A
user_patt2
N/A
Bit [7] of this register indicates a valid temperature_counter read
was performed. A logic ‘1’ indicates a valid read.
Ramp
N/A
N/A
ADDRESS 0X4C: TEMP_COUNTER_LOW
ADDRESS 0XC1: USER_PATT1_LSB
ADDRESS 0XC2: USER_PATT1_MSB
Bits [7:0] of this register hold the lower 8 LSBs of the 11-bit
temperature code.
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 1.
ADDRESS 0X4D: TEMP_COUNTER_CONTROL
Bit [7] Measurement mode select bit, set to ‘1’ for recommended
PTAT mode. ‘0’ (default) is IPTAT mode and is less accurate and
not recommended.
ADDRESS 0XC3: USER_PATT2_LSB
ADDRESS 0XC4: USER_PATT2_MSB
Bit [6] Temperature counter enable bit. Set to ‘1’ to enable.
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 2
Bit [5] Temperature counter power down bit. Set to ‘1’ to
power-down temperature counter.
ADDRESS 0XC5: USER_PATT3_LSB
ADDRESS 0XC6: USER_PATT3_MSB
Bit [4] Temperature counter reset bit. Set to ‘1’ to reset count.
Bit [3:1] Three bit frequency divider field. Sets temperature
counter update rate. Update rate is proportional to ADC sample
clock rate and divide ratio. A ‘101’ updates the temp counter
every ~ 66µs (for 250MSPS). Faster updates rates result in lower
precision.
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 3
ADDRESS 0XC7: USER_PATT4_LSB
ADDRESS 0XC8: USER_PATT4_MSB
Bit [0] Select sampler bit. Set to ‘0’.
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 4.
This set of registers provides digital access to an PTAT or
IPTAT-based temperature sensor, allowing the system to
estimate the temperature of the die, allowing easy access to
information that can be used to decide when to recalibrate the
A/D as needed.
ADDRESS 0XC9: USER_PATT5_LSB
ADDRESS 0XCA: USER_PATT5_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 5.
The nominal transfer function of the temperature monitor should
be estimated for each device by reading the temperature sensor
at two temperatures and extrapolating a line through these two
points.
ADDRESS 0XCB: USER_PATT6_LSB
ADDRESS 0XCC: USER_PATT6_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 6.
FN7572 Rev 2.00
December 5, 2012
Page 28 of 35
ISLA214P
A typical temperature measurement can occur as follows:
1. Write ‘0xCA’ to address 0x4D - enable temp counter,
divide=’101’
2. Wait ≥ 132µs (at 250Msps) - longer wait time ensures the
sensor completes one valid cycle.
3. Write ‘0x20’ to address 0x4D - power down, disable temp
counter-recommended between measurements. This
ensures that the output does not change between MSB and
LSB reads.
4. Read address 0x4B (MSBs)
5. Read address 0x4C (LSBs)
6. Record temp code value
7. Write ‘0x20’ to address 0x4D - power-down, disable temp
counter. Contact the factory for more information if needed.
© Copyright Intersil Americas LLC 2011-2012. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7572 Rev 2.00
December 5, 2012
Page 29 of 35
ISLA214P
SPI Memory Map
ADDR.
DEF. VALUE
(HEX)
(Hex)
PARAMETER NAME
Port_config
Reserved
BIT 7 (MSB)
SDO Active
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
00
LSB First
Soft Reset
Mirror (bit5) Mirror (bit6) Mirror (bit7)
00h
01
Reserved
02
Burst_end
Burst end address [7:0]
Reserved
00h
03-07
Reserved
08
09
Chip_id
Chip_version
Chip ID #
Chip Version #
Reserved
Read only
Read only
0A-0F
10-1F
20
Reserved
Reserved
Reserved
Offset_coarse_adc0
Offset_fine_adc0
Gain_coarse_adc0
Gain_medium_adc0
Gain_fine_adc0
Modes_adc0
Coarse Offset
Fine Offset
cal. value
cal. value
cal. value
cal. value
cal. value
21
22
Reserved
Coarse Gain
23
Medium Gain
Fine Gain
24
25
Reserved
Power Down Mode ADC0 [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
00h
NOTresetbySoft
Reset
100 = Sleep
Other codes = Reserved
26
27
28
29
2A
2B
Offset_coarse_adc1
Offset_fine_adc1
Gain_coarse_adc1
Gain_medium_adc1
Gain_fine_adc1
Coarse Offset
Fine Offset
cal. value
cal. value
cal. value
cal. value
cal. value
Reserved
Coarse Gain
Medium Gain
Fine Gain
Modes_adc1
Reserved
Power Down Mode ADC1 [2:0]
000 = Pin Control
001 = Normal Operation
00h
NOTresetbySoft
Reset
010 = Nap
100 = Sleep
Other codes = Reserved
2C-2F
30-4A
4B
Reserved
Reserved
Reserved
Reserved
Temp_counter_high
Temp_counter_low
Temp_counter_control
Reserved
Temp Counter [10:8]
Read only
Read only
00h
4C
Temp Counter [7:0]
Reset
4D
Enable
PD
Divider [2:0]
Select
4E-6F
70
Reserved
Skew_diff
Differential Skew
Reserved
80h
00h
71
Phase_slip
Next Clock
Edge
72
Clock_divide
Clock Divide [2:0]
00h
NOTresetbySoft
Reset
000 = Pin Control
001 = divide by 1
010 = divide by 2
100 = divide by 4
Other codes = Reserved
73
Output_mode_A
Output Mode [7:5]
000 = LVDS 3mA (Default)
001 = LVDS 2mA
Output Format [2:0]
000 = Two’s Complement (Default)
010 = Gray Code
00h
NOTresetbySoft
Reset
100 = LVCMOS
100 = Offset Binary
Other codes = Reserved
Other codes = Reserved
74
Output_mode_B
Reserved
DLL Range
0 = Fast
1 = Slow
DDR Enable
Reserved
00h
NOTresetbySoft
Reset
Default=’0’
75-B5
FN7572 Rev 2.00
December 5, 2012
Page 30 of 35
ISLA214P
SPI Memory Map (Continued)
ADDR.
DEF. VALUE
(HEX)
(Hex)
PARAMETER NAME
Cal_status
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
B6
Calibration
Done
Read Only
B7-BF
C0
Reserved
Test_io
Output Test Mode [7:4]
User Test Mode [2:0]
00h
Part in SDR Mode
0 = Off (Note 18)
1 = Midscale Short
2 = +FS Short
Part in SDR Mode
0 = User pattern 1 only
1 = Cycle pattern 1 through 2
2 = Cycle pattern 1 through 3
3 = Cycle pattern 1 through 4
4 = Cycle pattern 1 through 5
5= Cycle pattern 1 through 6
6 = Cycle pattern 1 through7
7 = Cycle pattern 1 through 8
3 = -FS Short
4 = Checkerboard Output (0xAAAA, 0x5555) (Note19
7 = 0xFFFF, 0x0000 all on pattern (Note20)
8 = User Pattern (1 to 8 deep, MSB Justified)
10 = Ramp
5, 6, 9, 11-15 = Reserved
Part in DDR Mode
Part in DDR Mode
0 = Off (Note 18)
1 = Midscale Short
2 = +FS Short
3 = -FS Short
4 = Reserved (Note19)
7 = Reserved (Note20)
8 = User Pattern (1 to 4 deep,MSB Justified)
10 = Ramp
0 = User pattern 1 only
1 = Cycle pattern 1,3
2 = Cycle pattern 1,3,5
3 = Cycle pattern 1,3,5,7
4-7 = NA
5, 6, 9, 11-15 = Reserved
C1
C2
User_patt1_lsb
User_patt1_msb
User_patt2_lsb
B7
B15
B7
B6
B14
B6
B5
B13
B5
B4
B12
B4
B3
B11
B3
B2
B10
B2
B1
B9
B1
B9
B1
B9
B1
B9
B1
B9
B1
B9
B1
B9
B1
B9
B0
B8
B0
B8
B0
B8
B0
B8
B0
B8
B0
B8
B0
B8
B0
B8
0x00
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
C3
C4
User_patt2_msb
User_patt3_lsb
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
C5
C6
User_patt3_msb
User_patt4_lsb
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
C7
C8
User_patt4_msb
User_patt5_lsb
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
C9
CA
CB
CC
User_patt5_msb
User_patt6_lsb
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
User_patt6_msb
User_patt7_lsb
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
CD
CE
User_patt7_msb
User_patt8_lsb
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
CF
D0
D1-FD
FE
User_patt8_msb
Reserved
B15
B14
B13
B12
B11
B10
Reserved
Reserved
Offset/Gain_Adjust_Enable
Enable
“1” =
00h
Enable
FF
Reserved
Reserved
NOTES:
18. During Calibration xCCCC (MSB justified) is presented at the output data bus, toggling on the LSB (and higher) data bits occurs at completion of calibration. This behavior
can be used as an option to determine calibration state.
19. Use test_io = 0x80 and User Pattern 1 = 0x9999 for Checkerboard outputs in DDR mode. In SDR mode, write ‘0x41’ to test_io for Checkerboard outputs.
20. Use test_io = 0x80 and User Pattern 1 = 0xAAAA for all ones/zeroes outputs in DDR mode. In SDR mode, write ‘0x71’ to test_io for all ones/zeroes outputs
FN7572 Rev 2.00
December 5, 2012
Page 31 of 35
ISLA214P
Equivalent Circuits
AVDD
AVDD
TO
CLOCK-PHASE
GENERATION
CLKP
AVDD
AVDD
CSAMP
4pF
TO
11k
11k
INP
INN
CHARGE
PIPELINE
18k
E2
E3
E3
E1
600
AVDD
CSAMP
4pF
18k
AVDD
TO
CHARGE
PIPELINE
E2
CLKN
E1
FIGURE 43. ANALOG INPUTS
FIGURE 44. CLOCK INPUTS
AVDD
AVDD
(20k PULL-UP
ON RESETN
ONLY)
OVDD
AVDD
75k
OVDD
AVDD
TO
SENSE
LOGIC
75k
280
OVDD
20k
INPUT
INPUT
TO
LOGIC
280
75k
75k
FIGURE 45. TRI-LEVEL DIGITAL INPUTS
FIGURE 46. DIGITAL INPUTS
OVDD
2mA OR
3mA
OVDD
DATA
DATA
OVDD
OVDD
D[13:0]P
OVDD
DATA
D[13:0]
D[13:0]N
DATA
DATA
2mA OR
3mA
FIGURE 48. CMOS OUTPUTS
FIGURE 47. LVDS OUTPUTS
FN7572 Rev 2.00
December 5, 2012
Page 32 of 35
ISLA214P
Equivalent Circuits(Continued)
AVDD
VCM
+
0.94V
–
FIGURE 49. VCM_OUT OUTPUT
LVDS Outputs
A/D Evaluation Platform
Output traces and connections must be designed for 50 (100
differential) characteristic impedance. Keep traces direct and
minimize bends where possible. Avoid crossing ground and
power-plane breaks with signal traces.
Intersil offers an A/D Evaluation platform which can be used to
evaluate any of Intersil’s high speed A/D products. The platform
consists of a FPGA based data capture motherboard and a family
of A/D daughtercards. This USB based platform allows a user to
quickly evaluate the A/D’s performance at a user’s specific
application frequency requirements. More information is
available at
LVCMOS Outputs
Output traces and connections must be designed for 50
http://www.intersil.com/converters/adc_eval_platform/
characteristic impedance.
Unused Inputs
Layout Considerations
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO) which will
not be operated do not require connection to ensure optimal A/D
performance. These inputs can be left floating if they are not
used. Tri-level inputs (NAPSLP) accept a floating input as a valid
state, and therefore should be biased according to the desired
functionality.
Split Ground and Power Planes
Data converters operating at high sampling frequencies require
extra care in PC board layout. Many complex board designs
benefit from isolating the analog and digital sections. Analog
supply and ground planes should be laid out under signal and
clock inputs. Locate the digital planes under outputs and logic
pins. Grounds should be joined under the chip.
Definitions
Analog Input Bandwidth is the analog input frequency at which
the spectral output power at the fundamental frequency (as
determined by FFT analysis) is reduced by 3dB from its full-scale
low-frequency value. This is also referred to as Full Power
Bandwidth.
Clock Input Considerations
Use matched transmission lines to the transformer inputs for the
analog input and clock signals. Locate transformers and
terminations as close to the chip as possible.
Aperture Delay or Sampling Delay is the time required after the
rise of the clock input for the sampling switch to open, at which
time the signal is held for conversion.
Exposed Paddle
The exposed paddle must be electrically connected to analog
ground (AVSS) and should be connected to a large copper plane
using numerous vias for optimal thermal performance.
Aperture Jitter is the RMS variation in aperture delay for a set of
samples.
Bypass and Filtering
Clock Duty Cycle is the ratio of the time the clock wave is at logic
high to the total time of one clock period.
Bulk capacitors should have low equivalent series resistance.
Tantalum is a good choice. For best performance, keep ceramic
bypass capacitors very close to device pins. Longer traces will
increase inductance, resulting in diminished dynamic
performance and accuracy. Make sure that connections to
ground are direct and low impedance. Avoid forming ground
loops.
Differential Non-Linearity (DNL) is the deviation of any code width
from an ideal 1 LSB step.
FN7572 Rev 2.00
December 5, 2012
Page 33 of 35
ISLA214P
Effective Number of Bits (ENOB) is an alternate method of
specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it
is calculated as: ENOB = (SINAD - 1.76)/6.02
Pipeline Delay is the number of clock cycles between the
initiation of a conversion and the appearance at the output pins
of the data.
Gain Error is the ratio of the difference between the voltages that
cause the lowest and highest code transitions to the full-scale
voltage less than 2 LSB. It is typically expressed in percent.
Power Supply Rejection Ratio (PSRR) is the ratio of the observed
magnitude of a spur in the A/D FFT, caused by an AC signal
superimposed on the power supply voltage.
I2E The Intersil Interleave Engine. This highly configurable
circuitry performs estimates of offset, gain, and sample time
skew mismatches between the core converters, and updates
analog adjustments for each to minimize interleave spurs.
Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one half the clock frequency, including
harmonics but excluding DC.
Integral Non-Linearity (INL) is the maximum deviation of the
A/D’s transfer function from a best fit line determined by a least
squares curve fit of that transfer function, measured in units of
LSBs.
Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one-half the sampling frequency, excluding
harmonics and DC.
Least Significant Bit (LSB) is the bit that has the smallest value or
SNR and SINAD are either given in units of dB when the power of
the fundamental is used as the reference, or dBFS (dB to full
scale) when the converter’s full-scale input power is used as the
reference.
weight in a digital word. Its value in terms of input voltage is
N
V
/(2 -1) where N is the resolution in bits.
FS
Missing Codes are output codes that are skipped and will never
appear at the A/D output. These codes cannot be reached with
any input value.
Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS
signal amplitude to the RMS value of the largest spurious
spectral component. The largest spurious spectral component
may or may not be a harmonic.
Most Significant Bit (MSB) is the bit that has the largest value or
weight.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
FN7572.2
FN7572.1
CHANGE
Improved the accuracy and clarity of the datasheet.
Initial Release
November 27, 2012
May 11, 2011
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the fastest growing markets within the industrial and infrastructure,
personal computing and high-end consumer markets. For more information about Intersil or to find out how to become a member of
our winning team, visit our website and career page at www.intersil.com.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective product information page.
Also, please check the product information page to ensure that you have the most updated datasheet: ISLA214P
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
Reliability reports are available from our website at: http://rel.intersil.com/reports/search.php
FN7572 Rev 2.00
December 5, 2012
Page 34 of 35
ISLA214P
Package Outline Drawing
L72.10x10E
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 11/09
10.00
A
Z
X
6
EXPOSED
PAD AREA
9.75
B
PIN #1
72
72
INDEX AREA
1
1
6
PIN 1
INDEX AREA
9.75
10.00
0.100 M C A B
(4X)
0.15
4.150 REF.
7.150 REF.
TOP VIEW
9.75 ±0.10
0.100 M C A B
BOTTOM VIEW
11°
Y
ALL AROUND
C0.400X45° (4X)
10.00 ±0.10
SIDE VIEW
(0.350)
R0.200
(7.15)
(4.15 REF)
1
0.500 ±0.100
R0.115 TYP.
72
(4X 9.70)
(4X 8.50)
(3.00 )
DETAIL "X"
DETAIL "Z"
(6.00)
R0.200 MAX.
ALL AROUND
( 72X 0 .23)
0.100 C
( 72X 0 .70)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
SEATING
PLANE
0.080C
0.190~0.245
0.23 ±0.050
2. Dimensioning and tolerancing conform to ANSI Y14.5m-1994.
0.50
C
0.025 ±0.020
3.
Unless otherwise specified, tolerance : Decimal ± 0.10
Angular ±2.50°
0.100M C A B
0.050M C
4. Dimension applies to the metallized terminal and is measured
between 0.015mm and 0.30mm from the terminal tip.
DETAIL "Y"
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
Package outline compliant to JESD-M0220.
7.
FN7572 Rev 2.00
December 5, 2012
Page 35 of 35
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