ISL97671AIRZ-T13_技术文档

6-Channel SMBus/I²C or PWM Dimming LED Driver with

Phase Shift Control

ISL97671A

Features

The ISL97671A is a 6-Channel 45V dual dimming capable LED

driver that can be used with either SMBus/I²C or PWM signal

for dimming control. The ISL97671A can drive six channels of

LEDs from an input of 4.5V~26.5V to an output of up to 45V. It

can also operate from an input as low as 3V to an output of up

to 26.5V in bootstrap configuration (see Figure 38).

• 6 x 50mA channels

• 4.5V to 26.5V input with max 45V output

• 3V (see Figure 38) to 21V input with max 26.5V output

• PWM dimming with phase shift control

• SMBus/I²C controlled PWM or DC dimming

• Direct PWM dimming

The ISL97671A features optional channel phase shift control

to minimize the input: output ripple characteristics and load

transients to improve efficiency and eliminate audible noise.

• PWM dimming linearity

- PWM dimming with adjustable dimming frequency and

duty cycle linear from 0.4% to 100% <30kHz

The device can also be configured in Direct PWM Dimming

with minimum dimming duty cycle of 0.007% at 200Hz.

- Direct PWM dimming duty cycle linear from 0.007% to

100% at 200Hz

The ISL97671A headroom control circuit monitors the highest

LED forward voltage string for output regulation, to minimize

the voltage headroom and power loss in a typical multi-string

operation.

• Current matching ±0.7%

• 600kHz/1.2MHz selectable switching frequency

• Dynamic headroom control

• Fault protection

The ISL97671A is offered in compact and thermally efficient

20 Ld QFN 4mmx3mm package.

- String open/short circuit, OVP, OTP, and optional output

short circuit fault protection

• 20 Ld 4mmx3mm QFN package

Applications

• Tablet PC to notebook displays LED backlighting

• LCD monitor LED backlighting

• Field sequential RGB LED backlighting

Typical Application Circuits

45V*, 6 x 50mA

VIN = 4.5~26.5V

Q1 (OPTIONAL)

ISL97671A

1 FAULT

ISL97671A

FAULT

ISL97671A

1

2

4

FAULT

VIN

1

2

LX 20

2

VIN

OVP

16

OVP

16

4

8

4

VDC

FPWM

PGND 19

CH0 10

7

6

7

6

SMBCLK/SCL

SMBDAT/SDA

7

6

SMBCLK/SCL

SMBDAT/SDA

CH0

10

11

12

13

14

15

CH0 10

SMBDAT/SDA

CH1

CH2

CH3

CH4

CH5

CH1

CH2

CH3

CH4

CH5

CH1

CH2

CH3

CH4

CH5

11

12

13

14

15

11

12

13

14

15

5

3

PWM

EN

5

3

PWM

EN

5

3

PWM

EN

17

RSET

17

8

17

8

RSET

FPWM

*VIN > 12V

COMP

*VIN > 12V

9

18

AGND

COMP

*VIN > 12V

COMP

9

18

9

AGND

18

AGND

FIGURE 1A. SMBus/I²C CONTROLLED

DIMMING AND ADJUSTABLE

DIMMING FREQUENCY

FIGURE 1B. PWM DIMMING WITH PWM INPUT

AND ADJUSTABLE DIMMING

FREQUENCY

FIGURE 1C. DIRECT PWM DIMMING

FIGURE 1. ISL97671A TYPICAL APPLICATION DIAGRAMS

November 30, 2012

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

1

FN7709.3

ISL97671A

Block Diagram

V

= 4.5V TO 26.5V

IN

45V*, 6 x 50mA

V

LX

FAULT

IN

ISL97671A

EN

OVP

VDC

REG

OVP

FAULT/STATUS

REGISTER

OSC AND

RAMP

COMP

FET

DRIVER

Σ = 0

LOGIC

ILIMIT

IMAX

FPWM

COMP

PGND

LED PWM

CONTROL

CH0

CH5

GM

AMP

HIGHEST VF

STRING

DETECT

OC, SC

DETECT

REFERENCE

GENERATOR

+

-

OC, SC

DETECT

*V > 12V

IN

+

-

RSET

FAULT/STATUS

REGISTER

AGND

TEMP

SENSOR

+

-

REGISTERS

PWM BRIGHTNESS CONTROL

DEVICE CONTROL

2

FAULT/STATUS

REGISTER

SMBUS/I C

SMBCLK/SCL

SMBDAT/SDA

PWM

PWM/OC/SC

DC

INTERFACE

AND PWM

CONTROL

LOGIC

FAULT/STATUS

IDENTIFICATION

DC BRIGHTNESS CONTROL

CONFIGURATION

FIGURE 2. ISL97671A BLOCK DIAGRAM

FN7709.3

November 30, 2012

2

ISL97671A

Pin Configuration

Ordering Information

ISL97671A

(20 LD QFN)

TOP VIEW

PART NUMBER

PART

PACKAGE

(Pb-free)

PKG.

DWG. #

(Notes 1, 2, 3)

MARKING

ISL97671AIRZ

671A

20 Ld 3x4 QFN

L20.3x4

ISL97671AIRZ-EVALZ Evaluation Board

20

19

18

17

NOTES:

FAULT

VIN

1. Add “-T* suffix for tape and reel. Please refer to TB347 for details on

reel specifications.

1

2

3

4

5

6

OVP

CH5

CH4

CH3

CH2

CH1

16

15

14

13

12

11

2. These Intersil Pb-free plastic packaged products employ special

Pb-free material sets, molding compounds/die attach materials, and

100% matte tin plate plus anneal (e3 termination finish, which is

RoHS compliant and compatible with both SnPb and Pb-free

soldering operations). Intersil Pb-free products are MSL classified at

Pb-free peak reflow temperatures that meet or exceed the Pb-free

requirements of IPC/JEDEC J STD-020.

EN

VDC

PWM

SMBDAT/SDA

3. For Moisture Sensitivity Level (MSL), please see device information

page for ISL97671A. For more information on MSL please see

techbrief TB363.

7

8

9

10

Pin Descriptions (I = Input, O = Output, S = Supply, X = Don’t Care)

PIN NAME

FAULT

VIN

PIN #

TYPE

DESCRIPTION

1

2

3

O

S

I

Fault Disconnect Switch Gate Control.

Input voltage for the device and LED power.

EN

Enable input. The device needs 4ms for initial power-up enable. It will be disabled if it is not biased for longer than

30.5ms.

VDC

PWM

4

5

6

S

I

Internal LDO output. Connect a decoupling capacitor to ground.

PWM brightness control pin or DPST control input.

SMBDAT/SDA

I/O SMBus/I²C serial data input and output. When pins 6 and 7 are grounded or in logic 0’s for longer than 60ms, the

drivers will be controlled by external PWM signal.

SMBCLK/SCL

FPWM

7

8

I

SMBus/I²C serial clock input. When pins 6 and 7 are grounded or in logic 0’s for longer than 60ms, the drivers will

be controlled by external PWM signal.

I

Set PWM dimming frequency, by connecting a resistor between this pin and ground. When FPWM is tied to VDC and

SMBCLK/SMBDAT is tied to ground, the device will be in Direct PWM Dimming where the output follows the input

frequency and duty cycle without any digitization.

AGND

9

S

I

Analog Ground for precision circuits.

CH0, CH1

CH2, CH3

CH4, CH5

10, 11,

12, 13,

14, 15

Current source and channel monitoring input for channels 0-5.

OVP

RSET

COMP

PGND

LX

16

17

18

19

20

I

Overvoltage protection input.

I

Resistor connection for setting LED current, (see Equation 1 for calculating the I_LED(peak)).

O

S

O

Boost compensation pin.

Power ground

Boost switch node.

EPAD

No electrical connection but should be used to connect PGND and AGND. For example use top plane as PGND and

bottom plane as AGND with vias on EPAD to allow heat dissipation and minimum noise coupling from PGND to

AGND operation.

FN7709.3

November 30, 2012

3

ISL97671A

Table of Contents

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

PWM Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Current Matching and Current Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Dynamic Headroom Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Maximum DC Current Setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

PWM DIMMING Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

PWM Dimming Frequency Adjustment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Phase Shift Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5V Low Dropout Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

IC Protection Features and Fault Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

SMBus/I²C Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Read Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Slave Device Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

SMBus/I²C Register Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PWM Brightness Control Register (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Device Control Register (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Fault/Status Register (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Identification Register (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

DC Brightness Control Register (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Configuration Register (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Output Channel Mask/Fault Readout Register (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Phase Shift Control Register (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Components Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Input Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Output Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Output Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Schottky Diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

High-Current Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Low Voltage Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

16-Bit Dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Field Sequential RGB LED Backlighting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

FN7709.3

November 30, 2012

4

ISL97671A

Absolute Maximum Ratings (T_A= +25°C)

Thermal Information

VIN, EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V

FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN - 8.5V to VIN + 0.3V

VDC, COMP, RSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5V

SMBCLK/SCL, SMBDAT/SDA, FPWM, PWM . . . . . . . . . . . . . . -0.3V to 5.5V

OVP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5V

CH0 - CH5, LX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 45V

PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V

Above voltage ratings are all with respect to AGND pin

Thermal Resistance (Typical)

20 Ld QFN Package (Notes 4, 5, 7) . . . . . .

Thermal Characterization (Typical)

θ

_JA(°C/W)

40

θ

_JC(°C/W)

2.5

PSI_JT(°C/W)

1

20 Ld QFN Package (Note 6) . . . . . . . . . . . . . . . . . . . . .

Maximum Continuous Junction Temperature . . . . . . . . . . . . . . . . .+125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

ESD Rating

Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . . . 3kV

Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 300V

Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kV

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise

noted, all tests are at the specified temperature and are pulsed tests, therefore: T_J= T_C= T_A

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4. θ_JAis measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

Brief TB379.

5. For θ_JC, the “case temp” location is the center of the exposed metal pad on the package underside.

6. PSI_JTis the PSI junction-to-top thermal characterization parameter. If the package top temperature can be measured with this rating then the die

junction temperature can be estimated more accurately than the θ_JCand θ_JCthermal resistance ratings.

7. Refer to JESD51-7 high effective thermal conductivity board layout for proper via and plane designs.

Electrical Specifications V = 12V, EN = 5V, R = 20.1kΩ, unless otherwise noted. Boldface limits apply over the operating

IN

SET

temperature range, -40°C to +85°C.

MIN

MAX

PARAMETER

GENERAL

DESCRIPTION

CONDITION

(Note 8)

TYP

(Note 8)

UNIT

V

V_IN(Note 9)

Backlight Supply Voltage

≤13 LEDs per channel

4.5

26.5

(3.2V/20mA type)

I_{VIN_STBY}

I_VIN

V_INShutdown Current

V_INActive Current

Output Voltage

T_A= +25°C

EN = 5V

5

µA

mA

V

5

V_OUT

4.5V < V_IN≤ 26V,

45

F

_SW= 600kHz

8.55V < V_IN≤ 26V,

V

F

_SW= 1.2MHz

4.5V < V_IN≤ 8.55V, F_SW= 1.2MHz

V_IN/0.19

2.6

V

V_UVLO

V_{UVLO_HYS}

REGULATOR

V_DC

Undervoltage Lockout Threshold

Undervoltage Lockout Hysteresis

2.1

200

4.8

20

mV

LDO Output Voltage

V_IN≥ 6V

4.55

5

V

µA

mV

V

I_{VDC_STBY}

V_LDO

Standby Current

EN = 0V

VDC LDO Droop Voltage

Guaranteed Range for EN Input Low Voltage

V_IN> 5.5V, 20mA

200

0.5

EN_LOW

EN_HI

Guaranteed Range for EN Input High Voltage

EN Low Time Before Shut-down

1.8

V

t_ENLow

30.5

ms

FN7709.3

November 30, 2012

5

ISL97671A

Electrical Specifications V = 12V, EN = 5V, R = 20.1kΩ, unless otherwise noted. Boldface limits apply over the operating

IN

SET

temperature range, -40°C to +85°C. (Continued)

MIN

MAX

PARAMETER

BOOST

DESCRIPTION

CONDITION

(Note 8)

TYP

(Note 8)

UNIT

SW_ILimit

r_DS(ON)

SS

Boost FET Current Limit

1.5

2.0

235

7

2.7

A

mΩ

ms

%

Internal Boost Switch ON-resistance

Soft-Start

T_A= +25°C

100% LED Duty Cycle

_IN= 12V, 72 LEDs, 20mA each,

300

Eff_peak

Peak Efficiency

V

92.9

L = 10µH with DCR 101mΩ,

T_A= +25°C

V

_IN= 12V, 60 LEDs, 20mA each,

90.8

0.1

%

L = 10µH with DCR 101mΩ,

T_A= +25°C

ΔI_OUT/ΔV_IN

Line Regulation

%

D_MAX

Boost Maximum Duty Cycle

F_SW= 1, 600kHz

F_SW= 0, 1.2MHz

F_SW= 1, 600kHz

90

81

D_MIN

Boost Minimum Duty Cycle

9.5

17

%

F

_SW= 0, 1.2MHz

f_{OSC_hi}

f_{OSC_lo}

Lx Frequency High

Lx Frequency Low

F_SW= 1, 600kHz

F_SW= 0, 1.2MHz

LX = 45V, EN = 0V

475

600

640

1.31

10

kHz

MHz

µA

0.97

1.14

I_{LX_leakage}

REFERENCE

FAULT DETECTION

V_SC

LX Pin Leakage Current

Short Circuit Threshold Accuracy

7.5

8.2

150

23

V

Temp_shtdwn Temperature Shutdown Threshold

°C

V

Temp_Hyst

V_OVPlo

Temperature Shutdown Hysteresis

Overvoltage Limit on OVP Pin

1.199

1.24

CURRENT SOURCES

I_MATCH

DC Channel-to-Channel Current Matching

R_SET= 20.1kΩ, Reg0x00 = 0xFF,

(I_OUT= 20mA)

±0.7

500

±1.0

+1.5

%

I_ACC

Current Accuracy

-1.5

1.2

%

V_HEADROOM

Dominant Channel Current Source Headroom I_LED= 20mA

at CH Pin

mV

T_A= +25°C

V_RSET

Voltage at RSET Pin

Maximum LED Current per Channel

R_SET= 20.1kΩ

1.22

50

1.24

V

I_LED(max)

V_IN= 12V, V_OUT= 45V, F_SW= 1.2MHz,

T_A= +25°C

mA

PWM GENERATOR

V_IL

V_IH

Guaranteed Range for PWM Input Low Voltage

Guaranteed Range for PWM Input High Voltage

PWM Input Frequency Range

0.8

VDD

V

1.5

F_PWMI

PWMACC

200

30,000

Hz

bits

PWM Dimming Accuracy (Except Direct PWM

Dimming)

8

t_DIRECTPWM

F_PWM

Direct PWM Minimum On Time

PWM Dimming Frequency Range

Direct PWM Mode

250

350

ns

Hz

100

30,000

FN7709.3

November 30, 2012

6

ISL97671A

Electrical Specifications V = 12V, EN = 5V, R = 20.1kΩ, unless otherwise noted. Boldface limits apply over the operating

IN

SET

temperature range, -40°C to +85°C. (Continued)

MIN

MAX

PARAMETER

FAULT PIN

I_FAULT

DESCRIPTION

CONDITION

(Note 8)

TYP

(Note 8)

UNIT

Fault Pull-down Current

V_IN= 12V

12

6

21

7

30

8.3

1.2

5

µA

V

V_FAULT

Fault Clamp Voltage with Respect to V_IN

LX Start-up Threshold

V_IN= 12, V_IN- V_FAULT

LXstart_thres

0.9

1

V

ILXStart-up

2

LX Start-up Current

3.5

mA

SMBus/I C INTERFACE

V_IL

V_IH

V_OL

Guaranteed Range for Data, Clock Input Low

Voltage

0.8

V

Guaranteed Range for Data, Clock Input High

Voltage

1.5

-10

VDD

2

SMBus/I C Data line Logic Low Voltage

I_PULLUP= 4mA

0.17

10

V

I_LEAK

Input Leakage On SMBData/SMBClk

Measured at 4.8V

µA

2

SMBus/I C TIMING SPECIFICATIONS

t_EN-SMB/I²C

Minimum Time Between EN high and

1µF capacitor on VDC

2

ms

µs

SMBus/I²C Enabled

PWS

Pulse Width Suppression on

SMBCLK/SMBDAT

0.15

0.45

400

f_SMB

t_BUF

SMBus/I²C Clock Frequency

kHz

µs

Bus Free Time Between Stop and Start

Condition

1.3

0.6

t_HD:STA

Hold Time After (Repeated) START Condition.

After this Period, the First Clock is Generated

µs

t_SU:STA

t_SU:STO

t_HD:DAT

t_SU:DAT

t_LOW

t_HIGH

t_F

Repeated Start Condition Setup Time

Stop Condition Setup Time

Data Hold Time

0.6

µs

ns

µs

ns

300

100

1.3

0.6

Data Setup Time

Clock Low Period

Clock High Period

Clock/data Fall Time

Clock/data Rise Time

300

t_R

NOTES:

8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

9. At maximum V_INof 26.5V, minimum V_OUTis limited 28V.

FN7709.3

November 30, 2012

7

ISL97671A

Typical Performance Curves

100

90

80

70

60

50

40

30

20

10

0

100

6P10S LEDs

90

80

70

24V

IN

580kHz

1.2MHz

12V

IN

60

50

40

30

20

10

0

5V

IN

0

5

10

15

20

25

30

35

0

5

10

15

(V)

20

25

30

I

(mA)

V

LED

IN

FIGURE 3. EFFICIENCY vs UP TO 30mA LED CURRENT (100% LED

DUTY CYCLE) vs V_IN

FIGURE 4. EFFICIENCY vs V_INvs SWITCHING FREQUENCY AT 20mA

(100% LED DUTY CYCLE)

100

90

100

80

+25°C

70

-40°C

1.2MHz

580k

60

50

40

30

20

10

0

0°C

+85°C

40

20

0

5

10

15

(V)

20

25

30

0

5

10

15

(V)

20

25

30

V

IN

FIGURE 5. EFFICIENCY vs V_INvs SWITCHING FREQUENCY AT 30mA

(100% LED DUTY CYCLE)

FIGURE 6. EFFICIENCY vs V_INvs TEMPERATURE AT 20mA

(100% LED DUTY CYCLE)

0.40

0.30

0.20

0.10

0.00

1.2

1.0

0.8

4.5 V

IN

0.6

0.4

0.2

0

4.5V

IN

12 V

IN

12V

IN

-0.10

-0.20

-0.30

-0.40

21V

4

IN

0

1

2

3

5

6

7

0

1

2

3

4

5

6

CHANNEL

PWM DIMMING DUTY CYCLE(%)

FIGURE 7. CHANNEL-TO-CHANNEL CURRENT MATCHING

FIGURE 8. CURRENT LINEARITY vs LOW LEVEL PWM DIMMING

DUTY CYCLE vs V_IN

FN7709.3

November 30, 2012

8

ISL97671A

Typical Performance Curves (Continued)

0.60

0.55

0.50

0.45

0.40

-40°C

+25°C

V

= 50mV/DIV

OUT

2.00µs/DIV

0°C

V_LX= 20V/DIV

2.00µs/DIV

0

5

10

15

(V)

20

25

30

V

IN

FIGURE 10. V_OUTRIPPLE VOLTAGE, V_IN= 12V, 6P12S AT

20mA/CHANNEL

FIGURE 9. V_HEADROOMvs V_INvs TEMPERATURE AT 20mA

V_OUT

V_EN

V_LX

I_^I_I^IN^NDD^UU^CTC^OT^ROR

I_^I_I^INN^DD^UU^CTC^OT^ROR

FIGURE 11. SOFT-START INDUCTOR CURRENT AT V_IN= 6V FOR

6P12S AT 20mA/CHANNEL

FIGURE 12. SOFT-START INDUCTOR CURRENT AT V_IN= 12V FOR

6P12S AT 20mA/CHANNEL

6P12S, 20mA/CH

V

= 10V/DIV

V

= 10V/DIV

IN

10ms/DIV

10.0ms/DIV

I_V = 1A/DIV

IN

I_V = 1A/DIV

IN

ILED = 20mA/DIV

EN

FIGURE 13. LINE REGULATION WITH V_INCHANGE FROM 6V TO 26V,

6P12S AT 20mA/CHANNEL

FIGURE 14. LINE REGULATION WITH V_INCHANGE FROM 26V TO 6V

FOR 6P12S AT 20mA/CHANNEL

FN7709.3

November 30, 2012

9

ISL97671A

Typical Performance Curves (Continued)

6P12S, 20mA/CH

V

= 1V/DIV

V

= 1V/DIV

O

10.0ms/DIV

ILED = 20mA/DIV

FIGURE 15. BOOST OUTPUT VOLTAGE WITH BRIGHTNESS CHANGE

FROM 0% TO 100%, V_IN= 12V, 6P12S AT

20mA/CHANNEL

FIGURE 16. BOOST OUTPUT VOLTAGE WITH BRIGHTNESS CHANGE

FROM 100% TO 0%, V_IN= 12V, 6P12S AT

20mA/CHANNEL

6P12S, 20mA/CH

0.0030

0.0025

0.0020

0.0015

V

_O= 10V/DIV

20.0ms/DIV

I_V = 1A/DIV

IN

ILED = 20mA/DIV

F

= 200Hz

PWM

EN

NO CH CAPS

I

= 20mA @ 100% DUTY CYCLE

LED

0.0010

0.006 0.007 0.008 0.009 0.010 0.011 0.012 0.013 0.014

PWM DIMMING DUTY CYCLE (%)

FIGURE 17. ISL97671A SHUTS DOWN AND STOPS SWITCHING

~30ms AFTER EN GOES LOW

FIGURE 18. DIRECT PWM DIMMING LINEARITY AT VERY LOW DUTY

CYCLE

FN7709.3

November 30, 2012

10

ISL97671A

Dynamic Headroom Control

Theory of Operation

The ISL97671A features a proprietary Dynamic Headroom

Control circuit that detects the highest forward voltage string or

effectively the lowest voltage from any of the CH0-CH5 pins.

When this lowest channel voltage is lower than the short circuit

threshold, V_SC, such voltage will be used as the feedback signal

for the boost regulator. The boost makes the output to the correct

level such that the lowest channel pin is at the target headroom

voltage. Since all LED stacks are connected to the same output

voltage, the other channel pins will have a higher voltage, but the

regulated current source circuit on each channel will ensure that

each channel has the same programmed current. The output

voltage will regulate cycle-by-cycle and is always referenced to

the highest forward voltage string in the architecture.

PWM Boost Converter

The current mode PWM boost converter produces the minimal

voltage needed to enable the LED stack with the highest forward

voltage drop to run at the programmed current. The ISL97671A

employs current mode control boost architecture that has a fast

current sense loop and a slow voltage feedback loop. Such

architecture achieves a fast transient response that is essential

for notebook backlight applications in which drained batteries

can be instantly changed to an AC/DC adapter without

noticeable visual disturbance. The number of LEDs that can be

driven by ISL97671A depends on the type of LED chosen in the

application. The ISL97671A is capable of boosting up to 45V and

typically driving 13 LEDs in series for each of the 6 channels,

enabling a total of 78 pieces of the 3.2V/20mA type of LEDs.

MAXIMUM DC CURRENT SETTING

The initial brightness should be set by choosing an appropriate

value for R_SET. This should be chosen to fix the maximum

possible LED current:

Enable

The EN pin is used to enable or disable the ISL97671A operation. It

is a high voltage pin that can be tied directly to V_INup to 26.5V. If EN

is pulled low for longer than 30ms, the device will shut down.

410.5

--------------

I

=

LEDmax

(EQ. 1)

R

SET

Once R_SETis fixed, the LED DC current can be adjusted through

Register 0x07 (BRTDC) as follows:

Current Matching and Current Accuracy

Each channel of the LED current is regulated by the current

source circuit, as shown in Figure 19.

I

= 1.61x(BRTDC ⁄ R

)

SET

(EQ. 2)

LED

The LED peak current is set by translating the R_SETcurrent to the

output with a scaling factor of 410.5/R_SET. The source terminals

of the current source MOSFETs are designed to run at 500mV to

optimize power loss versus accuracy requirements. The sources

of errors of the channel-to-channel current matching come from

the op amps offset, internal layout, reference, and current source

resistors. These parameters are optimized for current matching

and absolute current accuracy. On the other hand, the absolute

accuracy is additionally determined by the external R_SET, and

therefore, additional tolerance will be contributed by the current

setting resistor. A 1% tolerance resistor is therefore

BRTDC can be programmed from 0 to 255 in decimal and

defaults to 255 (0xFF). If left at the default value, LED current will

be fixed at I_LEDmax. BRTDC can be adjusted dynamically on the fly

during operation. BRTDC = 0 disconnects all channels.

For example, if the maximum required LED current (I_LED(max)) is

20mA, rearranging Equation 1 yields Equation 3:

R

= 410.5 ⁄ 0.02 = 20.52kΩ

(EQ. 3)

SET

If BRTDC is set to 200 then:

(EQ. 4)

I

= 1.61 • 200 ⁄ 20100 = 16.02mA

LED

recommended.

PWM DIMMING CONTROL

The ISL97671A provides multiple PWM dimming methods, as

described in the following. Table 1 summarizes the dimming

mode selection. Each of these methods results in PWM chopping

of the current in the LEDs for all 6 channels to provide a lower

average LED current. During the On periods, the LED current will

be defined by the value of R_SETand BRTDC, as described in

Equations 1 and 2. The source of the PWM signal can be

described as follows:

+

-

+

-

REF

1. Internally generated 256 step duty cycle BRT register

programmed through the SMBus/I²C.

RSET

2. External signal from PWM.

+

-

3. DPST mode. Internally generated signal with duty cycle

defined by the product of the PWM input duty cycle and

SMBus/I²C programmed BRT register.

PWM DIMMING

DC DIMMING

4. Direct PWM mode. The output duty cycle and dimming

frequency follow the input PWM signal.

FIGURE 19. SIMPLIFIED CURRENT SOURCE CIRCUIT

The default PWM dimming mode is in DPST. In all of the

methods, the average LED channel current is controlled by I_LED

FN7709.3

November 30, 2012

11

ISL97671A

and the PWM duty cycle in percent, as shown in Equation 5:

cycle is 60% dimming at 1kHz, the resultant PWM duty cycle is

48% dimming at 200Hz.

I

= I

× PWM

LED

(EQ. 5)

LED(ave)

In DPST mode, the ISL97671A features 8-bit dimming resolution;

it calculates the dimming level by taking the 8 most significant

bits of the product of the PWMI duty cycle (digitized with 8-bit

resolution) and of the BRT I²C register.

Method 1 (SMBus/I²C Controlled Dimming)

The average LED channel current is controlled by the internally

generated PWM signal, as shown in Equation 6:

Method 4 (Direct PWM Mode)

(EQ. 6)

I

= I

× (BRT ⁄ 255)

LED

LED(ave)

Direct PWM Dimming mode is selected when F_PWMis tied to V_DC

and SMBCLK/SMBDAT are grounded. The current of the 6

channels will follow the incoming PWM signal’s frequency and

duty cycle. The minimum duty cycle can be as low as 0.007% at

200Hz (or equivalent pulse width of 350ns). This ultra low duty

cycle dimming performance can be achieved if no channel

capacitor is present. Also in Direct PWM Dimming mode the

Phase Shift function will be disabled.

where BRT is the PWM brightness level programmed in the

Register 0x00. BRT ranges from 0 to 255 in decimal and defaults

to 255 (0xFF). BRT = 0 disconnects all channels.

To use only the SMBus/I²C controlled PWM brightness control,

users need to set Register 0x01 to 0x05. Alternatively, the same

operation can be obtained by leaving Register 0x01 at its default

value of 0x01 (DPST mode) and connecting the PWM input to

VDC, so that the dimming level depends only on the BRT register.

TABLE 1. DIMMING MODE SELECTION

SMBCLK/ SMBDAT/

The PWM dimming frequency is adjusted by a resistor at the

FPWM pin.

SCL PIN

SIGNAL

SDA PIN

SIGNAL

DIMMING METHOD

SELECTION

FPWM PIN

0x01 REGISTER

Method 2 (PWM Controlled Dimming with Settable Dimming

Frequency)

2

SMBUS /I C SMBUS/I C Resistor to

Set to 0x05, or set to

0x01 and connect PWM controlled dimming)

to VDC

Method 1 (SMBUS/I C

clock

data

ground

The average LED channel current can also be controlled by the duty

cycle of external PWM signal, as shown in Equation 7:

2

SMBUS /I C SMBUS/I C Resistor to

Set to 0x03, or set to

Method 2 (PWM controlled

0x01 and not program with settable dimming

clock

data

ground

I

= I

× PWMI

LED

(EQ. 7)

register 0x00

N/A

frequency)

LILED(ave)

Grounded

Resistor to

ground

Method 2 (PWM controlled

with settable dimming

frequency)

The PWM dimming frequency is adjusted by a resistor at the

FPWM pin. The PWM input cannot be low for more than 30.5ms

or else the driver will enter shutdown.

2

SMBUS /I C SMBUS/I C Resistor to

Set to 0x01

N/A

Method 3 (DPST mode)

clock

data

ground

To use externally applied PWM signal only for brightness control,

users need to set Register 0x01 to 0x03. Alternatively, the same

operation can be obtained by leaving Register 0x01 at its default

value of 0x01 (DPST mode), and not program Register BRT, so

that it contains its default value of 0xFF. A third way to obtain this

mode of operation is to tie both SCL and SDA to ground.

Grounded

Tie to VDC

Method 4 (Direct PWM

dimming)

PWM Dimming Frequency Adjustment

For dimming methods 1-3, the PWM dimming frequency is set by

an external resistor at the FPWM pin as:

Method 3 (DPST Mode)

7

The average LED channel current can also be controlled by the

product of the SMBus/I²C controlled PWM and the external PWM

signals as:

6.66×10

-----------------------

=

(EQ. 11)

F

PWM

RFPWM

where F_PWMis the PWM dimming frequency and R_FPWMis the

setting resistor.

I

= I

xPWM

DPST

(EQ. 8)

LED(ave)

LED

Where:

The maximum PWM dimming frequency is 30kHz when the duty

cycle is from 0.4% to 100%.

PPWM

= BRT ⁄ 255 × PWMI

(EQ. 9)

DPST

Phase Shift Control

Therefore:

For dimming methods 1-3, the ISL97671A is capable of delaying

the phase of each current source to minimize load transients. By

default, phase shifting is disabled as shown in Figure 20 where

the channels PWM currents are switching at the same time.

(EQ. 10)

I

= I

× BRT ⁄ 255 × PWMI

LED(ave)

LED

Where BRT is the value held in Register 0x00 (default setting

0xFF) controlled by SMBus/I²C and PWMI is the duty cycle of the

incoming PWM signal. In this way, the users can change the

PWM current in ratiometric manner to achieve DPST compliant

backlight dimming. To use the DPST mode, users need to set

Register 0x01 to 0x01. The PWM dimming frequency is adjusted

by a resistor at the FPWM pin.

For example, if the SMBus/I²C controlled PWM duty is 80%

dimming at 200Hz (see Equation 11) and the external PWM duty

FN7709.3

November 30, 2012

12

ISL97671A

t_PWMin

t_FPWM

60%

40%

PWMI

t_ON

t_OFF

ILED0

t_FPWM

(t_PWMout

)

t_ON

60%

t_OFF

40%

ILED1

ILED2

ILED3

t_D1

ILED2

ILED3

ILED4

t_D1

ILED4

ILED5

t_D2

FIGURE 20. NO DELAY (DEFAULT PHASE SHIFT DISABLED)

ILED1

t_D1= Fixed Delay with Integer only while the decimal value will be discarded (eg. 63.75=63)

When EqualPhase = 1(register 0x0A, bit 7), the phase shift evenly

spreads the channels switching across the PWM cycle, depending on

how many channels are enabled, as shown in Figures 21 and 22.

Equal phase means there are fixed delays between channels and

such delay can be calculated as Equation 12 in Figures 21 and 22.

FIGURE 22. 4 EQUAL PHASE CHANNELS PHASE SHIFT ILLUSTRATION

t_FPWM

ILED0

t_ON

t_OFF

t

255

N

FPWM

255

⎛

x

⎞

⎠

t_PD

------------------ ---------

(EQ. 12)

t

=

D1

⎝

ILED1

ILED2

ILED3

t_PD

Equation 13 shows the phase delay between the last channel of

the current duty cycle and the first channel of the next duty cycle

in Figures 21 and 22.

t_PD

t

255

N

FPWM

255

⎛

⎝

⎞⎞

⎠⎠

(EQ. 13)

------------------

---------

t

=

x 255 – (N – 1)

ILED4

ILED5

D2

⎝

t_PD

where (255/N) is rounded down to the nearest integer. For

example, if N = 6, (255/N) = 42, that leads to:

FIGURE 23. PHASE SHIFT WITH 7-BIT PROGRAMMABLE DELAY

t_D1= t_FPWMx 42/255

t_D2= t_FPWMx 45/255

The ISL97671A allows the user to program the amount of phase

shift degree with 7-bit resolution, as shown in Figure 23. To

enable programmable phase shifting, the user must write to the

Phase Shift Control register with EqualPhase = 0 and the

desirable phase shift value of PhaseShift[6:0]. The delay

between CH5 and the repeated CH0 is the rest of the PWM cycle.

where t_FPWMis the sum of t_ONand t_OFF. N is the number of LED

channels. The ISL97671A will detect the number of operating

channels automatically.

60%

40%

PWMI

ILED0

Switching Frequency

The default switching frequency is 600kHz but it can be selected

to 600kHz or 1.2MHz if the SMBus/I²C communications is used.

The switching frequency select bit is accessible in the SMBus/I²C

Configuration Register 0x08 bit 2.

60%

40%

t_D1

ILED1

ILED2

ILED3

t_D1

5V Low Dropout Regulator

t_D1

There is an internal 5V low dropout (LDO) regulator to develop the

necessary low-voltage supply, which is used by the chip’s internal

control circuitry. VDC is the output of this LDO regulator which

requires a bypass capacitor of 1µF or more for the regulation.

The VDC pin can be used as a coarse reference as long as it is

sourcing only a few milliamps.

t_D1

ILED4

ILED5

t_D1

t_D2

t_FPWM

ILED0

t_ON

t_OFF

IC Protection Features and Fault

Management

FIGURE 21. 6 EQUAL PHASE CHANNELS PHASE SHIFT ILLUSTRATION

ISL97671A has several protection and fault management

features that improve system reliability. The following sections

describe them in more detail.

FN7709.3

November 30, 2012

13

ISL97671A

All LED faults are reported via the SMBus/I²C interface to

In-Rush Control and Soft-Start

Register 0x02 (Fault/Status register). The controller is able to

determine which channels have failed via Register 0x09 (Output

Masking register). The controller can also choose to use Register

0x09 to disable faulty channels at start-up, resulting in only

further faulty channels being reported by Register 0x02.

The ISL97671A has separate, built-in, independent in-rush

control and soft-start functions. The in-rush control function is

built around an external short-circuit protection P-channel FET in

series with VIN. At start-up, the fault protection FET is turned on

slowly due to a 21µA pull-down current output from the FAULT

pin. This discharges the fault FET's gate-source capacitance,

turning on the FET in a controlled fashion. As this happens, the

output capacitor is charged slowly through the low-current FET

before it becomes fully enhanced. This results in a low in-rush

current. This current can be further reduced by adding a

capacitor (in the 1nF to 5nF range) across the gate source

terminals of the FET.

Short-Circuit Protection (SCP)

The short-circuit detection circuit monitors the voltage on each

channel and disables faulty channels that are above

approximately 7.5V (this action is described in “PROTECTIONS

TABLE” on page 16).

Open-Circuit Protection (OCP)

Once the chip detects that the fault protection FET is turned on

fully, it assumes that in-rush is complete. At this point, the boost

regulator begins to switch, and the current in the inductor ramps

up. The current in the boost power switch is monitored, and

switching is terminated in any cycle in which the current exceeds

the current limit. The ISL97671A includes a soft-start feature in

which this current limit starts at a low value (275mA). This value

is stepped up to the final 2.2A current limit in seven additional

steps of 275mA each. These steps happen over at least 8ms and

are extended at low LED PWM frequencies if the LED duty cycle is

low. This extension allows the output capacitor to charge to the

required value at a low current limit and prevents high input

current for systems that have only a low to medium output

current requirement.

When one of the LEDs becomes an open circuit, it can behave as

either an infinite resistance or as a gradually increasing finite

resistance. The ISL97671A monitors the current in each channel

such that any string that reaches the intended output current is

considered “good.” Should the current subsequently fall below the

target, the channel is considered an “open circuit.” Furthermore,

should the boost output of the ISL97671A reach the OVP limit, or

should the lower over-temperature threshold be reached, all

channels that are not good are immediately considered to be open

circuit. Detection of an open circuit channel results in a time-out

before the affected channel is disabled. This time-out is sped up

when the device is above the lower over-temperature threshold, in

an attempt to prevent the upper over-temperature trip point from

being reached.

For systems with no master fault protection FET, the in-rush

current flows towards C_OUTwhen V_INis applied. The in-rush

current is determined by the ramp rate of V_INand the values of

C_OUTand L.

Some users employ special types of LEDs that have a Zener

diode structure in parallel with the LED. This configuration

provides ESD enhancement and enables open-circuit operation.

When this type of LED is open circuited, the effect is as if the LED

forward voltage has increased but the lighting level has not

increased. Any affected string will not be disabled, unless the

failure results in the boost OVP limit being reached, which allows

all other LEDs in the string to remain functional. In this case, care

should be taken that the boost OVP limit and SCP limit are set

properly, to ensure that multiple failures on one string do not

cause all other good channels to fault out. This condition could

arise if the increased forward voltage of the faulty channel

makes all other channels look as if they have LED shorts. See

Table 2 for details of responses to fault conditions.

Fault Protection and Monitoring

The ISL97671A features extensive protection functions to cover

all perceivable failure conditions.

The failure mode of an LED can be either an open circuit or a

short. The behavior of an open-circuited LED can additionally

take the form of either infinite resistance or, for some LEDs, a

Zener diode, which is integrated into the device in parallel with

the now-opened LED.

For basic LEDs (which do not have built-in Zener diodes), an

open-circuit failure of an LED results only in the loss of one

channel of LEDs, without affecting other channels. Similarly, a

short-circuit condition on a channel that results in that channel

being turned off does not affect other channels unless a similar

fault is occurring.

OVP and V

OUT

The Overvoltage Protection (OVP) pin has a function of setting the

overvoltage trip level as well as limiting the V_OUTregulation

range.

The ISL97671A OVP threshold is set by R_UPPERand R_LOWERsuch

that:

Due to the lag in boost response to any load change at its output,

certain transient events (such as LED current steps or significant

step changes in LED duty cycle) can transiently look like LED

fault modes. The ISL97671A uses feedback from the LEDs to

determine when it is in a stable operating region and prevents

apparent faults during these transient events from allowing any

of the LED stacks to fault out. See Table 2 for details.

(R

+ R

)

UPPER

LOWER

------------------------------------------------------------

(EQ. 14)

V

= 1.22Vx

OUT_OVP

R

LOWER

and the output voltage V_OUTcan regulate between 64% and

100% of the V_{OUT_OVP}such that:

Allowable V_OUT= 64% to 100% of V_{OUT_OVP}

A fault condition that results in an input current that exceeds the

device’s electrical limits will result in a shutdown of all output

channels.

If R₁and R₂are chosen such that the OVP level is set at 40V,

then V_OUTis allowed to operate between 25.6V and 40V. If the

V_OUTrequirement is changed to an application of six LEDs of 21V,

FN7709.3

November 30, 2012

14

ISL97671A

then the OVP level must be reduced. Users should follow the

start-up, the LX pins inject a fixed current into the output

capacitor. The device does not start unless the voltage at LX

exceeds 1.2V. The OVP pin is also monitored such that if it rises

above and subsequently falls below 20% of the target OVP level,

the input protection FET is also switched off.

V_OUT= (64% ~100%) OVP level requirement; otherwise, the

headroom control will be disturbed such that the channel voltage

can be much higher than expected. This can sometimes prevent

the driver from operating properly.

The resistances should be large, to minimize power loss. For

example, a 1MΩ R_UPPERand a 30kΩ R_LOWERsets OVP to 41.9V.

Large OVP resistors also allow C_OUTto discharge slowly during the

PWM Off time. Parallel capacitors should also be placed across

Over-Temperature Protection (OTP)

The ISL97671A includes two over-temperature thresholds. The lower

threshold is set to +130°C. When this threshold is reached, any

channel that is outputting current at a level significantly below the

regulation target is treated as “open circuit” and is disabled after a

time-out period. This time-out period is 800µs when it is above the

lower threshold. The lower threshold isolates and disables bad

channels before they cause enough power dissipation (as a result of

other channels having large voltages across them) to hit the upper

temperature threshold.

the OVP resistors such that R_UPPER/R_LOWER= C_LOWER/C_UPPER

.

Using a C_UPPERvalue of 30pF is recommended. These capacitors

reduce the AC impedance of the OVP node, which is important

when using high-value resistors. For example, if

R_UPPER/R_LOWER= 33/1, then C_UPPER/C_LOWER= 1/33 with

C_UPPER= 100pF and C_LOWER= 3.3nF

Undervoltage Lock-out

The upper threshold is set to +150°C. Each time this threshold is

reached, the boost stops switching, and the output current

sources switch off. Once the device has cooled to approximately

+100°C, the device restarts, with the DC LED current level

reduced to 75% of the initial setting. If dissipation persists,

subsequent hitting of the limit causes identical behavior, with the

current reduced in steps to 50% and finally 25%. Unless disabled

via the EN pin, the device stays in an active state throughout.

If the input voltage falls below the UVLO level, the device stops

switching and is reset. Operation restarts only when V_INreturns

to the normal operating range.

Input Overcurrent Protection

During a normal switching operation, the current through the

internal boost power FET is monitored. If the current exceeds the

current limit, the internal switch is turned off. Monitoring occurs

on a cycle-by-cycle basis in a self-protecting way. Additionally, the

ISL97671A monitors the voltage at the LX and OVP pins. At

For complete details of fault protection conditions, see Figure 24

and Table 2.

LX

V

OUT

IN

FAULT

O/P

DRIVER

SHORT

OVP

IMAX

FET

LOGIC

ILIMIT

DRIVER

VSC

CH0

CH5

VSET/2

REG

THRM

SHDN

REF

T2

TEMP

SENSOR

OTP

T1

VSET

+

-

VSET

Q0

Q5

-

PWM/OC0/SC0

PWM/OC5/SC5

2

SMBUS/I C

FAULT/

STATUS

REGISTER

CONTROL

LOGIC

DC CURRENT

FIGURE 24. SIMPLIFIED FAULT PROTECTIONS

FN7709.3

November 30, 2012

15

ISL97671A

TABLE 2. PROTECTIONS TABLE

FAILED CHANNEL ACTION

V_OUTREGULATED

BY

CASE

1

FAILURE MODE

DETECTION MODE

GOOD CHANNELS ACTION

CHx Short Circuit

Upper Over-Temperature CHx ON and burns power.

Protection limit (OTP) not

Remaining channels normal

Highest VF of all

channels

triggered and CHx < 7.5V

2

CHx Short Circuit

Upper OTP triggered but

CHx < 7.5V

All channels go off until chip cooled Same as CHx

and then comes back on with

current reduced to 76%. Subsequent

OTP triggers will reduce I_OUTfurther.

Highest VF of

remaining

channels

3

4

5

6

Upper OTP not triggered CHx disabled after 6 PWM cycle

but CHx > 7.5V time-outs.

Remaining channels normal

Highest VF of

remaining

channels

CHx Open Circuit with Upper OTP not triggered

infinite resistance and CHx < 7.5V

V_OUTwill ramp to OVP. CHx will time- Remaining channels normal

Highest VF of

remaining

channels

out after 6 PWM cycles and switch

off. V_OUTwill drop to normal level.

CHx LED Open Circuit Upper OTP not triggered CHx remains ON and has highest VF, Remaining channels ON,

but has paralleled

Zener

VF of CHX

and CHx < 7.5V

thus V_OUTincreases.

remaining channel FETs burn

power

CHx LED Open Circuit Upper OTP triggered but All channels go off until chip cooled Same as CHx

VF of CHx

but has paralleled

Zener

CHx < 7.5V

and then comes back on with

current reduced to 76%. Subsequent

OTP triggers will reduce I_OUTfurther

7

8

CHx LED Open Circuit Upper OTP not triggered CHx remains ON and has highest VF, V_OUTincreases, then CH-X

VF of CHx

but has paralleled

Zener

but CHx > 7.5V

thus V_OUTincreases.

switches OFF after 6 PWM cycles.

This is an unwanted shut off and

can be prevented by setting OVP

at an appropriate level.

Channel-to-Channel

Lower OTP triggered but Any channel below the target current will fault out after 6 PWM cycles. Highest VF of

ΔVF too high

CHx < 7.5V

Remaining channels driven with normal current.

remaining

channels

9

Channel-to-Channel

Upper OTP triggered but All channels go off until chip cools and then come back on with current Boost switch OFF

ΔVF too high

CHx < 7.5V

reduced to 76%. Subsequent OTP triggers will reduce I_OUTfurther

10

Output LED stack

voltage too high

V_OUT> VOVP

Any channel that is below the target current will time-out after 6 PWM

cycles, and V_OUTwill return to the normal regulation voltage required for remaining

other channels. channels

Highest VF of

11

V

_OUT/LX shorted to

GND at start-up or

_OUTshorted in

operation

LX current and timing are The chip is permanently shutdown 31ms after power-up if V_OUT/Lx is

monitored.

shorted to GND.

V

OVP pins monitored for

excursions below 20% of

OVP threshold.

FN7709.3

November 30, 2012

16

ISL97671A

t

F

R

SMBCLK

SMBDAT

t

LOW

V

IH

V

IL

t

HIGH

t

HD:DAT

SU:STA

HD:STA

t

SU:STO

SU:DAT

V

IH

V

IL

t

BUF

P

S

NOTES:

2

SMBus/I C Description

S = start condition

P = stop condition

A = acknowledge

A = not acknowledge

R/W = read enable at high; write enable at low

FIGURE 25. SMBUS/I²C INTERFACE

1

7

1

8

1

8

1

S

Slave Address

W

A

Command Code

A

Data byte

A

P

Master to Slave

Slave to Master

FIGURE 26. WRITE BYTE PROTOCOL

1

7

1

8

1

8

1

8

1

S

Slave Address

W

A

Command Code

A

S

Slave Address

R

A

Data Byte

A

P

Master to Slave

Slave to Master

FIGURE 27. READ BYTE PROTOCOL

FN7709.3

November 30, 2012

17

ISL97671A

2

SMBus/I C Communications

Slave Device Address

The ISL97671A can be controlled by SMBus/I²C for PWM or DC

dimming. Except when both the SDA and SCL input pins are tied to

ground, the LEDs are off by default and the user must use the

SMBus/I²C interface to turn them on. When both SDA and SCL are

instead shorted to ground, the LEDs turn on by default when the IC is

turned on, and the customer can use the ISL97671A without having

to control the SMBus/I²C interface. The switching frequency is fixed

at 600kHz if SMBus/I²C is not used.

The slave address contains 7 MSB plus one LSB as R/W bit, but

these 8 bits are usually called Slave Address bytes. Figure 28 shows

that the high nibble of the Slave Address byte is 0x5 or 0101b to

denote the “backlight controller class.” Bit 3 in the lower nibble of

the Slave Address byte is 1. Bit 0 is always the R/W bit, as specified

by the SMBus/I²C protocol. Note: In this document, the device

address will always be expressed as a full 8-bit address instead of

the shorter 7-bit address typically used in other backlight controller

specifications to avoid confusion. Therefore, if the device is in the

write mode where bit 0 is 0, the slave address byte is 0x58 or

01011000b. If the device is in the read mode where bit 0 is 1, the

slave address byte is 0x59 or 01011001b.

Write Byte

The Write Byte protocol is only three bytes long. The first byte starts

with the slave address followed by the “command code,” which

translates to the “register index” being written. The third byte

contains the data byte that must be written into the register selected

by the “command code”. A shaded label is used on cycles during

which the slaved backlight controller “owns” or “drives” the Data

line. All other cycles are driven by the “host master.”

2

SMBus/I C Register Definitions

The backlight controller registers are Byte wide and accessible via the

SMBus/I²C Read/Write Byte protocols. Their bit assignments are

provided in the following sections with reserved bits containing a

default value of “0”.

Read Byte

MSB

LSB

Figure 27 shows that the four byte long Read Byte protocol starts

out with the slave address followed by the “command code” which

translates to the “register index.” Subsequently, the bus direction

turns around with the re-broadcast of the slave address with bit 0

indicating a read (“R”) cycle. The fourth byte contains the data

being returned by the backlight controller. That byte value in the

data byte reflects the value of the register being queried at the

“command code” index. Note the bus directions, which are

highlighted by the shaded label that is used on cycles during which

the slaved backlight controller “owns” or “drives” the Data line. All

other cycles are driven by the “host master.”

0

1

0

1

0

R/W

DEVICE

ADDRESS

IDENTIFIER

FIGURE 28. SLAVE ADDRESS BYTE DEFINITION

FN7709.3

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18

ISL97671A

TABLE 3A. ISL97671A REGISTER LISTING

DEFAULT

VALUE

SMBUS/I²C

PROTOCOL

ADDRESS

0x00

REGISTER

BIT 7

BRT7

BIT 6

BRT6

BIT 5

BRT5

BIT 4

BRT4

BIT 3

BRT3

BIT 2

BRT2

BIT 1

BRT1

BIT 0

BRT0

PWM

0xFF

Read and Write

Brightness

Control Register

0x01

0x02

0x03

0x07

0x08

0x09

0x0A

Device Control Reserved Reserved

Register

Reserved Reserved Reserved PWM_MD

PWM_SEL

BL_CTL

FAULT

REV0

BRTDC0

VSC

0x00

0xC8

0xFF

0x1F

0x3F

0x00

Read and Write

Read Only

Fault/Status Reserved Reserved

Register

2_CH_SD 1_CH_SD BL_STAT OV_CURR THRM_SHDN

Identification

Register

LED

PANEL

MFG3

MFG2

MFG1

MFG0

REV2

REV1

BRTDC1

Reserved

CH1

Read Only

DC Brightness BRTDC7

Control Register

BRTDC6

BRTDC5

BRTDC4 BRTDC3 BRTDC2

Read and Write

Configuration Reserved Reserved Reserved BstSlew BstSlew

Register

FSW

CH2

Rate1

Rate0

OutputChannel Reserved Reserved

Register

CH5

CH4

CH3

CH0

Phase Shift Deg Equal

Phase

Shift6

Phase

Shift5

Phase

Shift4

Phase

Shift3

Phase

Shift2

Phase

Shift1

Phase

Shift0

TABLE 3B. DATA BIT DESCRIPTIONS

ADDRESS

0x00

REGISTER

DATA BIT DESCRIPTIONS

PWM Brightness Control

Register

BRT[7..0] = 256 steps of DPWM duty cycle brightness control

0x01

0x02

Device Control Register

PWM_MD, PWM_SEL: select the dimming method - see Table 4 for more details. Default = 00

BL_CTL = BL On/Off (1 = On, 0 = Off), default = 0

Fault/Status Register

2_CH_SD = Two LED output channels are shutdown (1 = shutdown, 0 = OK)

1_CH_SD = One LED output channel is shutdown (1 = shutdown, 0 = OK)

BL_STAT = BL status (1 = BL On, 0 = BL Off)

OV_CURR = Input overcurrent (1 = Overcurrent condition, 0 = Current OK)

THRM_SHDN = Thermal Shutdown (1 = Thermal fault, 0 = Thermal OK)

FAULT = Fault occurred (Logic “OR” of all of the fault conditions)

0x03

Identification Register

LED PANEL = 1

MFG[3..0] = Manufacturer ID (16 vendors available. Intersil is vendor ID 9)

REV[2..0] = Silicon rev (Rev 0 through Rev 7 allowed for silicon spins)

0x07

0x08

DC Brightness Control Register

Configuration Register

BRTDC[7..0] = 256 steps of DC brightness control

BstSlewRate[1..0] = Controls strength of FET driver. 00 - 25% drive strength, 01 - 50% drive strength,

10 - 75% drive strength, 11 - 100% drive strength.

F

_SW= Switching frequencies selection, F_SW= 0 = 1.2MHz. F_SW= 1 = 600kMHz

VSC[0] = Short circuit thresholds selection, 0 = disabled, 1 = 7.2V minimum

0x09

0x0A

Output Channel Mask/Fault

Readout Register

CH[5..0] = Output Channel Read and Write. In Write, 1 = Channel Enabled, 0 = Channel Disabled. In

Read, 1 = Channel OK, 0 = Channel Not OK/Channel disabled

Phase Shift Degree

EqualPhase = Controls phase shift mode - When 1, phase shift is 360/N (where N is the number of

channels enabled). When 0, phase shift is defined by PhaseShift<6:0>.

PS[6..0] = 7-bit Phase shift setting - phase shift between each channel is

PhaseShift<6:0>/(255*PWMFreq). In direct PWM modes, phase shift between each channel is

PhaseShift<6:0>/12.8MHz.

FN7709.3

November 30, 2012

19

ISL97671A

PWM Brightness Control Register (0x00)

Device Control Register (0x01)

The Brightness control resolution has 256 steps of PWM duty cycle

adjustment. Figure 29 shows the bit assignment. All of the bits in

this Brightness Control Register can be read or written. Step 0

corresponds to the minimum step where the current is less than

10µA. Steps 1 to 255 represent the linear steps between 0.39% and

100% duty cycle with approximately 0.39% duty cycle adjustment

per step.

This register has two bits that control either SMBus/I²C

controlled or external PWM controlled PWM dimming and a

single bit that controls the backlight ON/OFF state. The

remaining bits are reserved. The bit assignment is shown in

Figure 30. All other bits in the Device Control Register will read as

low unless otherwise written.

• All reserved bits have no functional effect when written.

• An SMBus/I²C Write Byte cycle to Register 0x00 sets the PWM

brightness level only if the backlight controller is in SMBus/I²C

mode (see Table 4) Operating Modes selected by Device

Control Register Bits 1 and 2).

• All defined control bits return their current, latched value when

read.

A value of 1 written to BL_CTL turns on the backlight in 4ms or less

after the write cycle completes. The backlight is deemed to be on

when Bit 3 BL_STAT of Register 0x02 is 1 and Register 0x09 is not 0.

• An SMBus/I²C Read Byte cycle to Register 0x00 returns the

programmed PWM brightness level.

A value of 0 written to BL_CTL immediately turns off the BL. The

BL is deemed to be off when Bit 3 BL_STAT of Register 0x02 is 0

and Register 0x09 is 0.

• An SMBus/I²C setting of 0xFF for Register 0x00 sets the

backlight controller to the maximum brightness.

• An SMBus/I²C setting of 0x00 for Register 0x00 sets the

backlight controller to the minimum brightness output.

The default value for Register 0x01 is 0x00.

• Default value for Register 0x00 is 0xFF.

REGISTER 0x00

PWM BRIGHTNESS CONTROL REGISTER

BRT7

BRT6

Bit 6 (R/W)

BRT5

BRT4

BRT3

BRT2

BRT1

BRT0

Bit 7 (R/W)

Bit 5 (R/W)

Bit 4 (R/W)

Bit 3 (R/W)

Bit 2 (R/W)

Bit 1 (R/W)

Bit 0 (R/W)

BIT ASSIGNMENT

BIT FIELD DEFINITIONS

= 256 steps of PWM brightness levels

FIGURE 29. DESCRIPTIONS OF BRIGHTNESS CONTROL REGISTER

BRT[7..0]

REGISTER 0x01

DEVICE CONTROL REGISTER

RESERVED

Bit 7 (R/W)

RESERVED

Bit 5 (R/W)

RESERVED

Bit 4 (R/W)

RESERVED

Bit 3 (R/W)

PWM_MD

PWM_SEL

Bit 1 (R/W)

BL_CTL

Bit 6 (R/W)

Bit 2 (R/W)

Bit 0 (R/W)

PWM_MD

PWM_SEL

BL_CTL

MODE

X

0

X

0

1

Backlight Off

SMBus/I²C and PWM input controlled (DPST)

dimming (Method 3)

1

X

0

1

SMBus/I²C controlled PWM dimming (Method 1)

PWM input controlled PWM dimming (Method 2)

FIGURE 30. DESCRIPTIONS OF DEVICE CONTROL REGISTER

FN7709.3

November 30, 2012

20

ISL97671A

For example, the Cbt = 50% duty cycle programmed in the

TABLE 4. OPERATING MODES SELECTED BY DEVICE CONTROL

REGISTER BITS 1 AND 2

SMBus/I²C Register 0x00 and the PWM frequency is tuned to be

200Hz with an appropriate capacitor at the FPWM pin. On the other

hand, PWM is fed with a 1kHz 30% high PWM signal. When

PWM_SEL = 0 and PWM_MD = 0, the device is in DPST operation

where DPST brightness = 15% PWM dimming at 200Hz.

PWM_MD

0

PWM_SEL

0

MODE

SMBus/I²C and PWM input controlled

(DPST) dimming (Method 3)

1

X

0

1

SMBus/I²C controlled PWM dimming

(Method 1)

Fault/Status Register (0x02)

PWM input controlled PWM dimming

(Method 2)

This register has 6 status bits that allow monitoring of the backlight

controller’s operating state. Not all of the bits in this register are

fault related (Bit 3 is a simple BL status indicator). The remaining

bits are reserved and return a “0” when read and ignore the bit value

when written. All of the bits in this register are read-only, with the

exception of bit 0, which can be cleared by writing to it.

The PWM_SEL bit determines whether the SMBus/I²C or PWM

input should drive the output brightness in terms of PWM

dimming. When PWM_SEL bit is 1, the PWM input only drives the

output brightness regardless of what the PWM_MD is.

• BL_STAT indicates the current backlight on/off status in

BL_STAT (1 if the BL is on, 0 if the BL is off).

When the PWM_SEL bit is 0, the PWM_MD bit selects the

manner in which the PWM dimming is to be interpreted; when

this bit is 1, the PWM dimming is based on the SMBus/I²C

brightness setting only. When this bit is 0, the PWM dimming

reflects a percentage change in the current brightness

programmed in the SMBus/I²C Register 0x00, i.e., DPST (Display

Power Saving Technology) mode as:

• FAULT is the logical OR of THRM_SHDN, OV_CURR, 2_CH_SD,

and 1_CH_SD should these events occur.

• 1_CH_SD returns a 1 if one or more channels have faulted out.

• 2_CH_SD returns a 1 if two or more channels have faulted out.

• When FAULT is set to 1, it will remain at 1 even if the signal

which sets it goes away. FAULT will be cleared when the

BL_CTL bit of the Device Control Register is toggled or when a

0 is written into the FAULT bit. At that time, if the fault

condition is still present or reoccurs, FAULT will be set to 1

again. BL_STAT will not cause FAULT to be set.

(EQ. 15)

DSPT Brightness = Cbt × PWM

Where:

Cbt = Current brightness setting from SMBus/I²C Register 0x00

without influence from the PWM

• The default value for Register 0x02 is 0x00.

PWM = is the percent duty cycle of the PWM

REGISTER 0x02

FAULT/STATUS REGISTER

RESERVED

Bit 7 (R)

RESERVED

Bit 6 (R)

2_CH_SD

Bit 5 (R)

1_CH_SD

Bit 4 (R)

BL_STAT

Bit 3 (R)

OV_CURR

Bit 2 (R)

THRM_SHDN

Bit 1 (R)

FAULT

Bit 0 (R)

BIT

BIT ASSIGNMENT

BIT FIELD DEFINITIONS

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

2_CH_SD

1_CH_SD

BL_STAT

= Two LED output channels are shutdown (1 = shutdown, 0 = OK)

= One LED output channel is shutdown (1 = shutdown, 0 = OK)

= BL Status (1 = BL On, 0 = BL Off)

OV_CURR

THRM_SHDN

FAULT

= Input Overcurrent (1 = Overcurrent condition, 0 = Current OK)

= Thermal Shutdown (1 = Thermal Fault, 0 = Thermal OK)

= Fault occurred (Logic “OR” of all of the fault conditions)

FIGURE 31. DESCRIPTIONS OF FAULT/STATUS REGISTER

FN7709.3

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ISL97671A

Identification Register (0x03)

DC Brightness Control Register (0x07)

The ID register contains 3 bit fields to denote the LED driver (always

set to 1), manufacturer and the silicon revision of the controller IC.

The bit field widths allow up to 16 vendors with up to 8 silicon

revisions each. All of the bits in this register are read-only.

The DC Brightness Control Register 0x07 sets the LED current

level between 0% and 100% of the level set using the RSET pin.

When PWM dimming, the level set is the current during the on

time. This register allows users to have additional dimming

flexibility by:

• Vendor ID 9 represents Intersil Corporation.

• The default value for Register 0x03 is 0xC8.

1. Effectively achieving 16-bits of dimming control when DC

dimming is combined with PWM dimming

The initial value of REV shall be 0. Subsequent values of REV will

increment by 1.

2. Achieving visual or audio noise free 8-bit DC dimming over

potentially noisy PWM dimming.

The bit assignment is shown in Figure 33. All of the bits in this

Register can be read or written. Steps 0 to 255 represent the

linear steps of current adjustment in DC on-the-fly.

• An SMBus/I²C Write Byte cycle to Register 0x07 sets the DC

LED current level.

• An SMBus/I²C Read Byte cycle to Register 0x07 returns the DC

LED current.

• Default value for Register 0x07 is 0xFF.

REGISTER 0x03

ID REGISTER

LED PANEL

Bit 7 = 1

MFG3

MFG2

Bit 5 (R)

MFG1

MFG0

REV2

REV1

REV0

Bit 6 (R)

Bit 4 (R)

Bit 3 (R)

Bit 2 (R)

Bit 1 (R)

Bit 0 (R)

BIT ASSIGNMENT

MFG[3..0]

BIT FIELD DEFINITIONS

= Manufacturer ID. See “Identification Register

(0x03)” on page 21.

data 0 to 8 in decimal correspond to other vendors

data 9 in decimal represents Intersil ID

data 10 to 14 in decimal are reserved

data 15 in decimal Manufacturer ID is not

implemented

REV[2..0]

= Silicon rev (Rev 0 through Rev 7 allowed for silicon

spins)

FIGURE 32. DESCRIPTIONS OF ID REGISTER

REGISTER 0x07

DC BRIGHTNESS CONTROL REGISTER

BRTDC7

BRTDC6

BRTDC5

BRTDC4

BRTDC3

BRTDC2

BRTDC1

Bit 1 (R/W)

BRTDC0

Bit 0 (R/W)

Bit 7 (R/W)

Bit 6 (R/W)

Bit 5 (R/W)

Bit 4 (R/W)

Bit 3 (R/W)

Bit 2 (R/W)

BIT ASSIGNMENT

BRTDC[7..0]

BIT FIELD DEFINITIONS

= 256 steps of DC brightness levels

FIGURE 33. DESCRIPTIONS OF DC BRIGHTNESS CONTROL REGISTER

FN7709.3

November 30, 2012

22

ISL97671A

Configuration Register (0x08)

Output Channel Mask/Fault Readout

Register (0x09)

The Configuration Register provides many extra functions that

users can explore in order to optimize the driver performance at

a given application.

This register can be read or written. It allows enabling and

disabling each channel individually. The bit position corresponds

to the channel. For example, Bit 0 corresponds to Ch0 and bit 5

corresponds to Ch5 and so on. A 1 bit value enables the channel

of interest. When reading data from this register, any disabled

channel and any faulted out channel will read as 0. This allows

the user to determine which channel is faulty and optionally not

enabling it in order to allow the rest of the system to continue to

function. Additionally, a faulted out channel can be disabled and

re-enabled in order to allow a retry for any faulty channel without

having to power-down the other channels.

A BstSlewRate bit allows users to control the boost FET slew rate

(the rates of turn-on and turn-off). The slew rate can be selected

to four relative strengths when driving the internal boost FET. The

purpose of this function is to allow users to experiment with the

slew rate with respect to EMI effect in the system. In general, the

slower the slew rate is, the lower the EMI interference to the

surrounding circuits; however, the switching loss of the boost FET

is also increased.

The FSW bit allows users to set the boost converter switching

frequency between 1.2MHz and 600kHz. The VSC bit allows

users to set the LED string short circuit threshold VSC to 7.2V or

disable it.

The bit assignment is shown in Figure 35. The default for

Register 0x09 is 0x3F.

The bit assignment is shown in Figure 34. The default value for

Register 0x08 is 0x1F.

REGISTER 0x08

CONFIGURATION REGISTER

RESERVED

Bit 7 (R/W)

RESERVED

Bit 6 (R/W)

BIT5

BIT4

BIT3

FSW

RESERVED

Bit 1 (R/W)

VSC

Bit 5 (R/W)

Bit 4 (R/W)

Bit 3 (R/W)

Bit 2 (R/W)

Bit 0 (R/W)

BIT ASSIGNMENT

BIT FIELD DEFINITIONS

BstSlewRate[1:0]

Controls strength of FET driver. 00 - 25% drive strength, 01 to 50% drive strength,

10 -75% drive strength, 11 to 100% drive strength.

FSW

VSC

2 levels of Switching Frequencies (1 = 1,200kHz, 0 = 600kHz)

Enable / Disable Short Circuit Protection (0 = disabled, 1 = 7.5V minimum)

FIGURE 34. DESCRIPTIONS OF CONFIGURATION REGISTER

REGISTER 0x09

OUTPUT CHANNEL REGISTER

RESERVED

Bit 7 (R/W)

RESERVED

Bit 6 (R/W)

CH5

CH4

CH3

CH2

CH1

CH0

Bit 5 (R/W)

Bit 4 (R/W)

Bit 3 (R/W)

Bit 2 (R/W)

Bit 1 (R/W)

Bit 0 (R/W)

BIT ASSIGNMENT

CH[5..0]

BIT FIELD DEFINITIONS

CH5 = Channel 5, CH4 = Channel 4 and so on

FIGURE 35. OUTPUT CHANNEL REGISTER

FN7709.3

November 30, 2012

23

ISL97671A

REGISTER 0x0A

PHASE SHIFT CONTROL REGISTER

EQUALPHASE

Bit 7 (R/W)

PHASESHIFT6

Bit 6 (R/W)

PHASESHIFT5

Bit 5 (R/W)

PHASESHIFT4

Bit 4 (R/W)

PHASESHIFT3

Bit 3 (R/W)

PHASESHIFT2

Bit 2 (R/W)

PHASESHIFT1

Bit 1 (R/W)

PHASESHIFT0

Bit 0 (R/W)

BIT ASSIGNMENT

EqualPhase

BIT FIELD DEFINITIONS

Controls phase shift mode - When 0, phase shift is defined by PhaseShift<6:0>. When 1, phase shift

is 360/N (where N is the number of channels enabled).

PhaseShift[6..0]

7-bit Phase shift setting - phase shift between each channel is PhaseShift<6:0>/(255*PWMFreq)

FIGURE 36. DESCRIPTIONS OF PHASE SHIFT CONTROL REGISTER

Phase Shift Control Register (0x0A)

Input Capacitor

The Phase Shift Control register is used to set phase delay

between channels. When bit 7 is set high, the phase delay is set

by the number of channels enabled and the PWM frequency.

Referring to Figure 3, the delay time is defined by Equation 16:

Switching regulators require input capacitors to deliver peak

charging current and to reduce the impedance of the input

supply. The capacitors reduce interaction between the regulator

and input supply, thus improving system stability. The high

switching frequency of the loop causes almost all ripple current

to flow into the input capacitor, which must be rated accordingly.

(EQ. 16)

t

= (t

⁄ N)

FPWM

D1

where N is the number of channels enabled, and t_FPWMis the

period of the PWM cycle. When bit 7 is set low, the phase delay is

set by bits 6 to 0 and the PWM frequency. Referencing Figure 23,

the programmable delay time is defined by Equation 17:

A capacitor with low internal series resistance should be chosen

to minimize heating effects and to improve system efficiency.

The X5R and X7R ceramic capacitors offer small size and a lower

value for temperature and voltage coefficient compared to other

ceramic capacitors.

(EQ. 17)

t

= (PS < 6, 0 > xt

⁄ (255))

FPWM

PD

An input capacitor of 10µF is recommended. Ensure that the

voltage rating of the input capacitor is able to handle the full

supply range.

where PS is an integer from 0 to 127, and t_FPWMis the period of

the PWM cycle. By default, all the register bits are set low, which

sets zero delay between each channel. Note that the user should

not program the register to have more than one period of the

PWM cycle delay between the first and last enabled channels.

Inductor

Inductor selection should be based on its maximum current (I_SAT

characteristics, power dissipation (DCR), EMI susceptibility

(shielded vs unshielded), and size. Inductor type and value

influence many key parameters, including ripple current, current

limit, efficiency, transient performance, and stability.

)

Components Selections

According to the inductor Voltage-Second Balance principle, the

change of inductor current during the switching regulator On

time is equal to the change of inductor current during the

switching regulator Off time. As shown in Equations 18 and 19,

since the voltage across an inductor is:

Inductor maximum current capability must be adequate to

handle the peak current in the worst-case condition. If an

inductor core with too low a current rating is chosen, saturation

in the core will cause the effective inductor value to fall, leading

to an increase in peak-to-average current level, poor efficiency,

and overheating in the core. The series resistance, DCR, within

the inductor causes conduction loss and heat dissipation. A

shielded inductor is usually more suitable for EMI-susceptible

applications such as LED backlighting.

V

L

------

ΔI

=

xΔt

(EQ. 18)

L

and ΔI_L@ On = ΔI_L@ Off, therefore:

(EQ. 19)

(V – 0) ⁄ L × D × t = (V – V – V ) ⁄ L × (1 – D) × t

S

I

S

O

D

I

where D is the switching duty cycle defined by the turn-on time

over the switching period. V_Dis a Schottky diode forward voltage

that can be neglected for approximation.

The peak current can be derived from the voltage across the

inductor during the Off period, as shown in Equation 22:

IL

= (V × I ) ⁄ (85% × V ) + 1 ⁄ 2[V × (V – V ) ⁄ (L × V × f )]

peak

O O I I O I O S

Rearranging the terms without accounting for V_Dgives the boost

ratio and duty cycle, respectively, as shown in Equations 20 and 21:

(EQ. 22)

The value of 85% is an average term for the efficiency

(EQ. 20)

V

⁄ V = 1 ⁄ (1 – D)

I

O

approximation. The first term is average current that is inversely

proportional to the input voltage. The second term is inductor

current change that is inversely proportional to L and f_S. As a

result, for a given switching frequency and minimum input

voltage at which the system operates, the inductor I_SATmust be

chosen carefully.

(EQ. 21)

D = (V – V ) ⁄ V

O

I

FN7709.3

November 30, 2012

24

ISL97671A

Output Capacitors

Applications

High-Current Applications

Each channel of the ISL97671A can support up to 30mA

(50mA @ V_IN= 12V). For applications that need higher current,

multiple channels can be grouped to achieve the desired current

(Figure 37). For example, the cathode of the last LED can be

connected to CH0 through CH2; this configuration can be treated

as a single string with 90mA current driving capability.

The output capacitor smooths the output voltage and supplies

load current directly during the conduction phase of the power

switch. Output ripple voltage consists of discharge and charge of

the output capacitor during FET On and OFF time and the voltage

drop due to flow through the ESR of the output capacitor. The

ripple voltage can be shown as Equation 23:

(EQ. 23)

ΔV

= (I ⁄ C × D ⁄ f ) + ((I × ESR)

O O S O

CO

The conservation of charge principle shown in Equation 21 also

indicates that, during the boost switch Off period, the output

capacitor is charged with the inductor ripple current, minus a

relatively small output current in boost topology. As a result, the

user must select an output capacitor with low ESR and adequate

input ripple current capability.

V

OUT

Note: Capacitors have a voltage coefficient that makes their

effective capacitance drop as the voltage across them increases.

C_OUTin Equation 23 assumes the effective value of the capacitor

at a particular voltage and not the manufacturer’s stated value,

measured at 0V.

CH0

CH1

CH2

The value of ΔV_Cocan be reduced by increasing C_Oor f_S, or by

using small ESR capacitors. In general, ceramic capacitors are

the best choice for output capacitors in small- to medium-sized

LCD backlight applications, due to their cost, form factor, and low

ESR.

FIGURE 37. GANGING MULTIPLE CHANNELS FOR HIGH CURRENT

APPLICATIONS

Low Voltage Operations

A larger output capacitor also eases driver response during the

PWM dimming Off period, due to the longer sample and hold

effect of the output drooping. The driver does not need to boost

harder in the next On period that minimizes transient current.

The ISL97671A VIN pin can be separately biased from the LED

power input to allow low-voltage operation. For systems that have

only a single supply, V_OUTcan be tied to the driver VIN pin to allow

initial start-up (Figure 38). The circuit works as follows: when the

input voltage is available and the device is not enabled, V_OUT

follows V_INwith a Schottky diode voltage drop. The V_OUT

boot-strapped to the VIN pin allows initial start-up, once the part

is enabled. Once the driver starts up with V_OUTregulating to the

target, the VIN pin voltage also increases. As long as V_OUTdoes

not exceed 26.5V and the extra power loss on V_INis acceptable,

this configuration can be used for input voltage as low as 3.0V.

The Fault Protection FET feature cannot be used in this

configuration.

The output capacitor is also needed for compensation, and in

general, 2x4.7µF/50V ceramic capacitors are suitable for

notebook display backlight applications.

Output Ripple

ΔV_Co, can be reduced by increasing Co or f_SW, or using small ESR

capacitors. In general, ceramic capacitors are the best choice for

output capacitors in small to medium sized LCD backlight

applications due to their cost, form factor, and low ESR.

For systems that have dual supplies, the VIN pin can be biased

from 5V to 12V, while input voltage can be as low as 2.7V

(Figure 39). In this configuration, VBIAS must be greater than or

equal to VIN to use the fault FET.

A larger output capacitor will also ease the driver response

during PWM dimming Off period due to the longer sample and

hold effect of the output drooping. The driver does not need to

boost harder in the next On period that minimizes transient

current. The output capacitor is also needed for compensation,

and, in general 2x4.7µF/50V ceramic capacitors are suitable for

notebook display backlight applications.

Schottky Diode

A high-speed rectifier diode is necessary to prevent excessive

voltage overshoot. Schottky diodes are recommended because

of their fast recovery time, low forward voltage and reverse

leakage current, which minimize losses. The reverse voltage

rating of the selected Schottky diode must be higher than the

maximum output voltage. Also the average/peak current rating

of the Schottky diode must meet the output current and peak

inductor current requirements.

FN7709.3

November 30, 2012

25

ISL97671A

Compensation

VIN = 3V~21V

26.5V, 6 x 50mA*

The ISL97671A incorporates a transconductance amplifier in its

feedback path to allow the user to optimize boost stability and

transient response. The ISL97671A uses current mode control

architecture, which has a fast current sense loop and a slow

voltage feedback loop. The fast current feedback loop does not

require any compensation, but for stable operation, the slow

voltage loop must be compensated. The compensation is a

series of Rc, Cc1 network from COMP pin to ground, with an

optional Cc2 capacitor connected between the COMP pin and

ground. The Rc sets the high-frequency integrator gain for fast

transient response, and the Cc1 sets the integrator zero to

ensure loop stability. For most applications, the component

values in Figure 40 can be used: Rc is 10kΩ and Cc1 is 3.3nF.

Depending upon the PCB layout, for stability, a Cc2 of 390pF may

be needed to create a pole to cancel the output capacitor ESR’s

zero effect.

ISL97671A

FAULT

1

2

4

LX 20

VIN

OVP

16

VDC

PGND 19

CH0 10

7

6

SMBCLK/SCL

SMBDAT/SDA

CH1

CH2

CH3

CH4

CH5

11

12

13

14

15

5

3

PWM

EN

17

8

RSET

FPWM

AGND

COMP

9

18

*VIN>12V

FIGURE 38. SINGLE SUPPLY 3V OPERATION

Rc 10k

COMP

45V, 6 x 50mA*

VIN = 2.7~26.5V

Cc2

Cc1

390pF

3.3nF

Q1 (OPTIONAL)

ISL97671A

1

FAULT

LX 20

VBIAS = 5V~12V

2

4

VIN

FIGURE 40. COMPENSATION CIRCUIT

OVP

16

VDC

PGND 19

CH0 10

7

6

SMBCLK/SCL

SMBDAT/SDA

CH1

CH2

CH3

CH4

CH5

11

12

13

14

15

5

3

PWM

EN

17

8

RSET

FPWM

AGND

COMP

*VIN > 12V

9

18

FIGURE 39. DUAL SUPPLIES 2.7V OPERATION

16-Bit Dimming

The SMBus/I²C controlled PWM and DC dimmings can be

combined to effectively provide 16 bits of dimming capability,

which can be valuable for automotive and avionics display

applications.

Field Sequential RGB LED Backlighting

The ISL97671A allows to turn each channel ON and OFF

independently. In field sequential RGB LED application, it is

possible to have different DC current and PWM duty cycle for

different channels as long as only one channel is active at a time.

This is achieved by continuously setting a new DC current and/or

PWM duty cycle each time a channel is turned ON. ISL97671A

does not allow to have different DC currents or PWM duty cycles

for channels that are ON at the same time.

FN7709.3

November 30, 2012

26

ISL97671A

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you

have the latest Rev.

DATE

REVISION

FN7709.3

CHANGE

October 3, 2012

Minor changes to improve the wording of various sections.

page 5 - Thermal Information, removed Pb-Free Reflow Profile link.

page 6 - V_OVPloin the spec table, changed to Min 1.199 and Max 1.24 from Min 1.19 and Max 1.24

page 8 - Figure 3 “EFFICIENCY vs up to 20mA LED CURRENT (100% LED DUTY CYCLE) vs VIN” removed.

page 9 - Figures 11, 12 replaced to clear waveforms

page 12 & page 16 respectively, Tables 1, 2 improved.

page 18 - I²C section, specified that the backlight can turns on when SDA/SCL are connected to ground.

page 20 - Improved description of PWM_MD and PWM_SEL I²C register bits. Corrected Figure 30.

Removed Direct PWM and PWM-to-DC register bits from the description

July 11, 2012

FN7709.2

FN7709.1

PWM-to-DC bit and BstSlewRate bit in the register 0x08 updated on page 19, page 22 and page 23.

In “Current Matching and Current Accuracy” on page 11, changed 401.8 to 410.5.

On page 11 Equation 1, changed 401.8 to 410.5.

March 24, 2011

Initial Release to web.

About Intersil

Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management

semiconductors. The company's products address some of the fastest growing markets within the industrial and infrastructure,

personal computing and high-end consumer markets. For more information about Intersil or to find out how to become a member of

our winning team, visit our website and career page at www.intersil.com.

For a complete listing of Applications, Related Documentation and Related Parts, please see the respective product information page.

Also, please check the product information page to ensure that you have the most updated datasheet: ISL97671A

To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff

Reliability reports are available from our website at: http://rel.intersil.com/reports/search.php

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7709.3

November 30, 2012

27

ISL97671A

Package Outline Drawing

L20.3x4

20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 1, 3/10

0.10 M

C

A

B

3.00

A

M

0.05

0.50

16X

20X 0.25 ^+0.05

6

B

4

-0.07

PIN 1 INDEX AREA

(C 0.40)

17

20

A

16

1

6

PIN 1

INDEX AREA

4.00

+0.10

2.65

-0.15

11

6

0.15 (4X)

A

10

7

VIEW "A-A"

1.65 ^+0.10

-0.15

TOP VIEW

20x 0.40±0.10

BOTTOM VIEW

SEE DETAIL "X"

C

0.10

0.9± 0.10

SEATING PLANE

0.08

C

SIDE VIEW

(16 x 0.50)

(2.65)

(3.80)

(20 x 0.25)

5

0.2 REF

C

(20 x 0.60)

0.00 MIN.

0.05 MAX.

(1.65)

(2.80)

DETAIL "X"

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3.

Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be

either a mold or mark feature.

FN7709.3

November 30, 2012

28


型号：	ISL97671AIRZ-T13
厂家：	RENESAS TECHNOLOGY CORP
描述：	LED Driver 驱动接口集成电路
文件：	总28页 (文件大小：917K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL97671AIRZ-T13 [RENESAS]

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