ISL94203EVKIT1Z [RENESAS]
3-to-8 Cell Li-ion Battery Pack Monitor;型号: | ISL94203EVKIT1Z |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | 3-to-8 Cell Li-ion Battery Pack Monitor 电池 |
文件: | 总64页 (文件大小:2586K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATASHEET
ISL94203
3-to-8 Cell Li-ion Battery Pack Monitor
FN7626
Rev 5.00
February 17, 2016
The ISL94203 is a Li-ion battery monitor IC that supports from
3 to 8 series connected cells. It provides full battery monitoring
and pack control. The ISL94203 provides automatic shutdown
and recovery from out of bounds conditions and automatically
controls pack cell balancing.
Features
• Eight cell voltage monitors support Li-ion CoO , Li-ion
2
Mn O and Li-ion FePO4 chemistries
2
4
• Stand-alone pack control - no microcontroller needed
• Multiple voltage protection options
(each programmable to 4.8V; 12-bit digital value)
and selectable overcurrent protection levels
The ISL94203 is highly configurable as a stand-alone unit, but
can be used with an external microcontroller, which
communicates to the IC through an I C interface.
2
• Programmable detection/recovery times for overvoltage,
undervoltage, overcurrent and short-circuit conditions
Applications
• Power tools
• Configuration/calibration registers maintained in EEPROM
• Open battery connect detection
• Battery back-up systems
• E-bikes
• Integrated charge/discharge FET drive circuitry with built-in
charge pump supports high-side N-channel FETs
Related Literature
• AN1952, “ISL94203EVKIT1Z Evaluation Kit User Guide”
• Cell balancing uses external FETs with internal state
machine or external microcontroller
• Enters low power states after periods of inactivity. Charge or
discharge current detection resumes normal scan rates
P+
43V
43V
VBATT
VC8
PSD
CB8
VC7
FETSOFF
CB7
VC6
INT
RGO
CHRG
CB6
VC5
ISL94203
CB5
VC4
SD
EOC
CB4
VC3
SCL
CB3
VC2
SDA
TEMPO
CB2
VC1
xT1
xT2
CB1
VC0
VREF
VSS
ADDR
GND
P-
FIGURE 1. TYPICAL APPLICATION DIAGRAM
FN7626 Rev 5.00
February 17, 2016
Page 1 of 64
ISL94203
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Symbol Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
External Temperature Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Wake-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Change in FET Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Automatic Temperature Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Serial Interface Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Discharge Overcurrent/Short-Circuit Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Charge Overcurrent Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Battery Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pack Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Battery Cell Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power-Up Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Wake-Up Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Low Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Typical Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Cell Fail Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Open-Wire Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Current and Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Current Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Current Sense. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Overcurrent and Short-Circuit Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Overcurrent and Short-Circuit Response (Discharge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Overcurrent Response (Charge). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Microcontroller Overcurrent FET Control Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Voltage, Temperature and Current Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Cell Voltage Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Overvoltage Detection/Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Undervoltage Detection/Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Temperature Monitoring/Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Microcontroller Read of Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Voltage Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Microcontroller FET Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Cell Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Cell Balance in Cascade Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
µC Control of Cell Balance FETs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Cell Balance FET Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Power FET Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
General I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Higher Voltage Microcontrollers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
FN7626 Rev 5.00
February 17, 2016
Page 2 of 64
ISL94203
Packs with Fewer than 8 Cells. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
PC Board Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Circuit Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Serial Interface Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Clock and Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Synchronizing Microcontroller Operations with Internal Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Register Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Registers: Summary (EEPROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Registers: Summary (RAM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Registers: Detailed (EEPROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Registers: Detailed (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
FN7626 Rev 5.00
February 17, 2016
Page 3 of 64
ISL94203
Ordering Information
PART NUMBER
(Notes 1 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
TAPE AND REEL
(UNITS)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL94203IRTZ
94203 IRTZ
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-
48 Ld TQFN
48 Ld TQFN
48 Ld TQFN
48 Ld TQFN
L48.6x6
ISL94203IRTZ-T7
ISL94203IRTZ-T
ISL94203IRTZ-T7A
ISL94203EVKIT1Z
NOTES:
94203 IRTZ
94203 IRTZ
94203 IRTZ
Evaluation Kit
1k
L48.6x6
L48.6x6
L48.6x6
4k
250
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL94203. For more information on MSL please see tech brief TB363.
Pin Configuration
ISL94203
(48 LD TQFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
1
2
36
35
34
33
VC8
CB8
VC7
CB7
VC6
CB6
RGO
EOC
3
SD
4
FETSOFF
5
32 PSD
31
6
INT
30 DNC
PAD
(GND)
7
VC5
CB5
VC4
8
29
28
VSS
VSS
9
CB4
10
27 SDAO
SDAI
SCL
VC3 11
CB3
26
25
12
13 14 15 16 17 18 19 20 21 22 23 24
FN7626 Rev 5.00
February 17, 2016
Page 4 of 64
ISL94203
Pin Descriptions
PIN
NUMBER
SYMBOL
DESCRIPTION
1, 3, 5, 7, 9, VC8, VC7, Battery cell n voltage input. This pin is used to monitor the voltage of this battery cell. The voltage is level shifted to a ground
11, 13, 15,
17
VC6, VC5, reference and is monitored internally by an ADC converter. VCn connects to the positive terminal of a battery cell (CELLN)
VC4, VC3, and VC(n-1) the negative terminal of CELLN (VSS connects with the negative terminal of CELL1).
VC2, VC1,
VC0
2, 4, 6, 8,
CB8, CB7, Cell balancing FET control output n. This internal drive circuit controls an external FET used to divert a portion of the current
10, 12, 14, CB6, CB5, around a cell while the cell is being charged or adds to the current pulled from a cell during discharge in order to perform a
16
CB4, CB3, cell voltage balancing operation. This function is generally used to reduce the voltage on an individual cell relative to other
CB2, CB1 cells in the pack. The cell balancing FETs are turned on or off by an internal cell balance state machine or an external
controller.
18, 28, 29
19
VSS
Ground. This pin connects to the most negative terminal in the battery string.
VREF
Voltage Reference Output. This output provides a 1.8V reference voltage for the internal circuitry and for the external
microcontroller.
20, 21
22
XT1, XT2 Temperature monitor inputs. These pins input the voltage across two external thermistors used to determine the
temperature of the cells and or the power FET. When this input drops below the threshold, an external over-temperature
condition exists.
TEMPO
Temperature monitor output control. This pin outputs a voltage to be used in a divider that consists of a fixed resistor and
a thermistor. The thermistor is located in close proximity to the cells or the power FET. The TEMPO output is connected
internally to the VREF voltage through a PMOS switch only during a measurement of the temperature, otherwise the TEMPO
output is off.
23, 30
24
DNC
ADDR
SCL
Do Not Connect
2
Serial Address. This is an address input for an I C communication link to allow for two cascaded devices on one bus.
2
25
Serial Clock. This is the clock input for an I C communication link.
2
26, 27
SDAI, SDAO Serial Data. These are the data lines for an I C interface. When connected together, they form the standard bidirectional
2
interface for the I C bus. When separated, they can use separate level shifters for a cascaded operation.
31
32
INT
Interrupt. This pin goes active low, when there is an external µC connected to the ISL94203 and µC communication fails to
send a slave byte within a watchdog timer period. This is a CMOS type output.
PSD
Pack Shutdown. This pin goes active high, when any cell voltage reaches the OVLO threshold (OVLO flag). Optionally, PSD is
also set if there is a voltage differential between any two cells that is greater than a specified limit (CELLF flag) or if there
is an open-wire condition. This pin can be used for blowing a fuse in the pack or as an interrupt to an external µC.
33
34
FETSOFF FETSOFF. This input allows an external microcontroller to turn off both Power FET and CB outputs. This pin should be pulled
low when inactive.
SD
Shutdown. This output indicates that the ISL94203 detected any failure condition that would result in the DFET turning off.
This could be undervoltage, overcurrent, over-temperature, under-temperature, etc. The SD pin also goes active if there is
any charge overcurrent condition. This is an open-drain output.
35
EOC
End-of-Charge. This output indicates that the ISL94203 detected a fully charged condition. This is defined by any cell voltage
exceeding an EOC voltage (as defined by an EOC value in EEPROM).
36
37
RGO
Regulator Output. This is the 2.5V regulator output.
CHMON
Charge Monitor. This input monitors the charger connection. When the IC is in the Sleep mode, connecting this pin to the
charger wakes up the device. When the IC recovers from a charge overcurrent condition, this pin is used to monitor that the
charger is removed prior to turning on the power FETs. In a single path configuration, this pin and the LDMON pin connect
together.
38
LDMON
Load Monitor. This pin monitors the load connection. When the IC is in the Sleep mode, connecting this pin to a load wakes
up the device. When the IC recovers from a discharge overcurrent or short-circuit condition, this pin is used to monitor that
the load is removed prior to turning on the power FETs. In a single path configuration, this pin and the CHMON pin connect
together.
39, 40, 41 C3, C2, C1 Charge Pump Capacitor Pins. These external capacitors are used for the charge pump driving the power FETs.
FN7626 Rev 5.00
February 17, 2016
Page 5 of 64
ISL94203
Pin Descriptions(Continued)
PIN
NUMBER
SYMBOL
DFET
DESCRIPTION
42
Discharge FET Control. The ISL94203 controls the gate of a discharge FET through this pin. The power FET is an N-channel
device. The FET is turned on by the ISL94203 if all conditions are acceptable. The ISL94203 will turn off the FET in the event
of an out of bounds condition. The FET can be turned off by an external microcontroller by writing to the CFET control bit.
The CFET output is also turned off by the FETSOFF pin. The FET output cannot be turned on by an external microcontroller
if there are any out of bounds conditions.
43
44
VDD
IC Supply Pin. This pin provides the operating voltage for the IC circuitry.
PCFET
Precharge FET Control. The ISL94203 controls the gate of a precharge FET through this pin. The power FET is an N-channel
device. The FET is turned on by the ISL94203 if all conditions are acceptable. The ISL94203 will turn off the FET in the event
of an out of bounds condition. The FET can be turned off by an external microcontroller by writing to the PCFET control bit.
The PCFET output is also turned off by the FETSOFF pin. The FET output cannot be turned on by an external microcontroller
if there are any out of bounds conditions. Either the PCFET or the CFET turn on, but not both.
45
CFET
Charge FET Control. The ISL94203 controls the gate of a charge FET through this pin. The power FET is an N-channel device.
The FET is turned on by the ISL94203 if all conditions are acceptable. The ISL94203 will turn off the FET in the event of an
out of bounds condition. The FET can be turned off by an external microcontroller by writing to the CFET control bit. The CFET
output is also turned off by the FETSOFF pin. The FET output cannot be turned on by an external microcontroller if there are
any out of bounds conditions. Either the PCFET or the CFET turn on, but not both.
46, 47
48
CSI2, CSI1 Current Sense Inputs. These pins connect to the ISL94203 current sense circuit. There is an external resistance across
which the circuit operates. The sense resistor is typically in the range of 0.2mΩ to 5mΩ.
VBATT
GND
Input Level Shifter Supply and Battery pack voltage input. This pin powers the input level shifters and is also used to monitor
the voltage of the battery stack. The voltage is internally divided by 32 and connected to an ADC converter through a MUX.
PAD
Thermal Pad. This pad should connect to ground.
FN7626 Rev 5.00
February 17, 2016
Page 6 of 64
ISL94203
Block Diagram
N-CHANNEL FETs
P+
PACK+
VDD
VDD
+16V
+16V
CS2
CS1
CURRENT SENSE GAIN AMPLIFIER
x5/x50/x500 GAIN
OVERCURRENT STATE MACHINE
O.C.
RECOVERY
WAKEUP
CIRCUIT
FET CONTROLS/CHARGE PUMP
100Ω
POWER-ON
RESET STATE
MACHINE
470nF
VBATT
VC8
1kΩ
EOC
330kΩ
47nF
EOC/SD
ERROR CONDITIONS
(OV, UV, SLP STATE MACHINES)
10kΩ
VSS
CB8
1kΩ
SD
CB STATE
MACHINE
CB8:1
VC7
VC6
VC5
VC4
330kΩ
47nF
10kΩ
VSS
FETSOFF
CB7
CB6
CB5
CB4
CB3
1kΩ
PSD
INT
330kΩ
47nF
RAM
10kΩ
1kΩ
EEPROM
REGISTERS
TEMP/VOLTAGE
MONITOR ALU
47nF
10kΩ
330kΩ
MEMORY
MANAGER
LDO
RGO
REG
1kΩ
47nF
RGO (OUT)
OSC
10kΩ
TIMING
AND
CONTROL
SCAN STATE
CB STATE
OVERCURRENT STATE
330kΩ
VC3
VC2
VC1
1kΩ
47nF
EOC/SD/ERROR STATE
SCAN STATE
MACHINE
SDAO
SDAI
SCL
2
10kΩ
330kΩ
I C
ADDR
1kΩ
47nF
10kΩ
TEMPO
CB2
CB1
330kΩ
WATCHDOG TIMER
1kΩ
47nF
xT2
xT1
xT2
xT1
10kΩ
14-BIT
ADC
TEMP
TEMP
330kΩ
VB/16
iT
RGO/2
T
GAIN
x1/x2
VC0
BAT-
VREF
P-
VREF
V
SS
PACK-
FIGURE 2. BLOCK DIAGRAM
FN7626 Rev 5.00
February 17, 2016
Page 7 of 64
ISL94203
Absolute Maximum Ratings (Note 4)
Thermal Information
Power Supply Voltage, V . . . . . . . . . . . . . . . . . V - 0.5V to V + 45.0V
Thermal Resistance (Typical)
48 Ld QFN (Notes 5, 6) . . . . . . . . . . . . . . . .
Continuous Package Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . .400mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
(°C/W)
28
(°C/W)
0.75
JA
JC
DD
SS
SS
Cell Voltage (VC, VBATT)
VCn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V
+ 0.5V
BATT
VCn - VSS (n = 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 45.0V
VCn - VSS (n = 6, 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 36.0V
VCn - VSS (n = 4, 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 27.0V
VCn - VSS (n = 2, 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 17.0V
VCn - VSS (n = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 7.0V
VCn - VSS (n = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 3.0V
VCn - VC(n-1) (n = 2 to 12). . . . . . . . . . . . . . . . . . . . . . . . . . . .-3.0V to 7.0V
VC1 - VC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 7.0V
Cell Balance Pin Voltages (VCB)
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Voltage:
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V to 36V
DD
VCBn - VCn-1, n = 1 to 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 7.0V
VCn - VCBn, n = 6 to 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 7.0V
Terminal Voltage
VCn-VC(n-1) Specified Range . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V to 4.3V
VCn-VC(n-1) Extended Range . . . . . . . . . . . . . . . . . . . . . . . . . 1.0V to 4.4V
VCn-VC(n-1) Maximum Range (any cell) . . . . . . . . . . . . . . . . 0.5V to 4.8V
ADDR, xT1, xT2, FETSOFF, PSD, INT. . . . . . . . . . . . . . -0.5 to V
+0.5V
RGO
SCL, SDAI, SDAO, EOC, SD. . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to 5.5V
CFET, PCFET, C1, C2, C3 . . V
DFET, CHMON, LDMON
Current Sense Voltage
to V + 15.5V (60V maximum)
to V + 15.0V (60V maximum)
DD
DD
DD - 0.5V
. . . . . . . . . -0.5V
VBATT, CS1, CS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V
+1.0V
DD
VBATT - CS1, VBATT - CS2 . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +0.5V
CS1 - CS2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +0.5V
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 2kV
Charged Device Model (Tested per JESD22-C101F). . . . . . . . . . . . . . 1kV
Latch-Up (Tested per JESD-78D; Class 2, Level A) . . . . . . . . . . . . . . 100mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. Devices are characterized, but not production tested, at Absolute Maximum Voltages.
5. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
6. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications
V
= 26.4V, T = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply across
A
DD
operating temperature range, -40°C to +85°C.
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 7)
TYP
6.0
(Note 7)
UNIT
V
Power-up Condition – Threshold
Rising
V
V
minimum voltage at which device
DD
operation begins
PORR1
(Device becomes Operational)
(CFET turns on; CHMON = V
)
DD
V
CHMON minimum voltage at which device
operation begins
VDD
3.0
V
V
PORR2
(CFET turns on; V > 6.0V)
DD
Power-Down Condition – Threshold
Falling
V
V
minimum voltage device remains
PORF
DD
operational (RGO turns off)
2.5V Regulated Voltage
1.8V Reference Voltage
V
I
= 3mA
RGO
2.4
2.5
1.8
38
2.6
1.81
45
V
V
RGO
V
1.79
REF
VBATT Input Current - V
I
Input current; Normal/Idle/Doze
= 33.6V
µA
BATT
VBATT
V
DD
Input current; Sleep/Power-Down
= 33.6V
1
µA
V
DD
FN7626 Rev 5.00
February 17, 2016
Page 8 of 64
ISL94203
Electrical Specifications
V
= 26.4V, T = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply across
DD A
operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
Supply Current
SYMBOL
TEST CONDITIONS
(Note 7)
TYP
310
(Note 7)
UNIT
µA
V
I
Device active (Normal mode)
(No error conditions)
370
DD
VDD1
CFET, PCFET, DFET = OFF; V = 33.6V
DD
I
Device active (Idle mode)
(No error conditions)
Idle = 1
215
210
215
275
µA
µA
µA
VDD2
CFET, PCFET, DFET = OFF; V = 33.6V
DD
I
Device active (Doze mode)
(No error conditions)
Doze = 1
265
VDD3
CFET, PCFET, DFET = OFF; V = 33.6V
DD
I
I
FET Drive Current
VDD4
VDD5
(I
increase when FETs are on -
VDD
Normal/Idle/Doze modes); V = 33.6V
DD
Device active (Sleep mode);
Sleep = 1; V = 33.6V
DD
0°C to +60°C
-40°C to +85°C
13
10
30
50
µA
µA
µA
I
Power-down
1
VDD6
PDWN = 1; V = 33.6V
DD
Input Bias Current
ICS1
V
= V
= VCS1 = VCS2 = 33.6V
BATT
15
DD
(Normal, idle, doze)
V
= V = VCS1 = VCS2 = 33.6V
DD
BATT
(Sleep, Power-Down)
0°C to +60°C
-40°C to +85°C
1
3
µA
µA
ICS2
V
= V
= VCS1 = VCS2 = 33.6V
BATT
10
15
DD
(Normal, Idle, Doze)
V
= V = VCS1 = VCS2 = 33.6V
DD
BATT
(Sleep, Power-Down)
0°C to +60°C
-40°C to +85°C
1
3
µA
µA
VCn Input Current
CBn Input Current
I
Cell input leakage current
AO2:AO0 = 0000H
-1
-1
1
VCN
(Normal/Idle/Doze; not sampling cells)
I
Cell Balance pin leakage current
(no balance active)
1
µA
CBN
TEMPERATURE MONITOR SPECIFICATIONS
External Temperature Accuracy
V
External temperature monitoring error. ADC
voltage error when monitoring xT1 input.
TGain = 0; (xTn = 0.2V to 0.737V)
-25
15
mV
V
XT1
Internal Temperature Monitor Output
(See “Temperature
Monitoring/Response” on page 35)
T
[iTB:iT0] *1.8/4095/GAIN
10
GAIN = 2 (TGain bit = 0)
Temperature = +25°C
0.276
1.0
INT25
V
Change in
mV/°C
INTMON
[iTB:iT0] *1.8/4095/GAIN
10
GAIN = 2 (TGain bit = 0)
Temperature = -40°C to +85°C
FN7626 Rev 5.00
February 17, 2016
Page 9 of 64
ISL94203
Electrical Specifications
V
= 26.4V, T = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply across
DD A
operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 7)
TYP
(Note 7)
UNIT
mV
CELL VOLTAGE MONITOR SPECIFICATIONS
Cell Monitor Voltage Accuracy
Cell Monitor Voltage Accuracy
V
Relative cell measurement error
ADCR
(Maximum absolute cell measurement error -
Minimum absolute cell measurement error)
VCn - VC(n-1) = 2.4V to 4.2V; 0°C to +60°C
VCn - VC(n-1) = 0.1V to 4.7V; 0°C to +60°C
VCn - VC(n-1) = 0.1V to 4.7V; -40°C to +85°C
3
10
15
30
V
Absolute cell measurement error
ADC
(Cell measurement error compared with
voltage at the cell)
VCn - VC(n-1) = 2.4V to 4.2V; 0°C to +60°C
VCn - VC(n-1) = 0.1V to 4.7V; 0°C to +60°C
VCn - VC(n-1) = 0.1V to 4.7V; -40°C to +85°C
-15
-20
-30
15
20
30
mV
mV
V
Voltage Accuracy
V
V - [VBB:VB0] *32*1.8/4095;
BATT 10
BATT
BATT
0°C to +60°C
-200
200
-40°C to +85°C
-270
270
CURRENT SENSE AMPLIFIER SPECIFICATIONS
Charge Current Threshold
Discharge Current Threshold
Current Sense Accuracy
VCCTH
VDCTH
VIA1
VCS1-VCS2, CHING indicates charge current
VCS1 = 26.4V
-100
μV
VCS1-VCS2, DCHING indicates discharge
current; VCS1 = 26.4V
100
102
μV
V
= ([ISNSB:ISNS0] *1.8/4095)/5;
10
97
-107
8.0
107
-97
mV
IA1
CHING bit set
Gain = 5
VCS1 = 26.4V, VCS2 - VCS1 = + 100mV
VIA2
VIA3
VIA4
VIA5
V
= ([ISNSB:ISNS0] *1.8/4095)/5;
10
-102
10.0
-10.0
mV
mV
mV
IA2
DCHING bit set
Gain = 5
VCS1 = 26.4V, VCS2 - VCS1 = - 100mV
V
= ([ISNSB:ISNS0] *1.8/4095)/50;
10
12.0
-8.0
IA3
CHING bit set
Gain = 50
VCS1 = 26.4V, VCS2 - VCS1 = + 10mV
V
= ([ISNSB:ISNS0] *1.8/4095)/50;
10
-12.0
IA4
DCHING bit set
Gain = 50
VCS1 = 26.4V, VCS2 - VCS1 = - 10mV
V
= ([ISNSB:ISNS0] *1.8/4095)/500;
10
IA3
CHING bit set
Gain = 500
VCS1 = 26.4V, VCS2 - VCS1 = + 1mV
0°C to +60°C
-40°C to +85°C
0.5
0.4
1.0
1.5
1.6
mV
mV
VIA6
V
= ([ISNSB:ISNS0] *1.8/4095)/500;
10
IA4
DCHING bit set
Gain = 500
VCS1=26.4V, VCS2 - VCS1 = - 1mV
0°C to +60°C
-40°C to +85°C
-1.5
-1.6
-1.0
-0.5
-0.4
FN7626 Rev 5.00
February 17, 2016
Page 10 of 64
ISL94203
Electrical Specifications
V
= 26.4V, T = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply across
DD A
operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 7)
TYP
(Note 7)
UNIT
OVERCURRENT/SHORT-CIRCUIT PROTECTION SPECIFICATIONS
Discharge Overcurrent Detection
Threshold
V
V
V
V
V
V
V
V
V
= 4mV [OCD2:0] = 0,0,0
= 8mV [OCD2:0] = 0,0,1
= 16mV [OCD2:0] = 0,1,0
= 24mV [OCD2:0] = 0,1,1
= 32mV [OCD2:0] = 1,0,0 (default)
= 48mV [OCD2:0] = 1,0,1
= 64mV [OCD2:0] = 1,1,0
= 96mV [OCD2:0] = 1,1,1
2.6
6.4
4.0
8.0
5.4
9.6
mV
mV
mV
mV
mV
mV
mV
mV
ms
OCD
OCD
OCD
OCD
OCD
OCD
OCD
OCD
OCD
12.8
20
16.0
25
19.2
30
26.4
42.5
60.3
90
33.0
50.0
67.0
100
160
39.6
57.5
73.7
110
Discharge Overcurrent Detection
Time
t
[OCDTA:OCDT0] = 0A0H (160ms) (default)
Range:
OCDT
0ms to 1023ms 1ms/step
0s to 1023s; 1s/step
Short-Circuit Detection Threshold
V
V
V
V
V
V
V
V
V
= 16mV [SCD2:0] = 0,0,0
= 24mV [SCD2:0] = 0,0,1
= 32mV [SCD2:0] = 0,1,0
= 48mV [SCD2:0] = 0,1,1
= 64mV [SCD2:0] = 1,0,0
= 96mV [SCD2:0] = 1,0,1 (default)
= 128mV [SCD2:0] = 1,1,0
= 256mV [SCD2:0] = 1,1,1
10.4
18
16.0
24
21.6
30
mV
mV
mV
mV
mV
mV
mV
mV
µs
SCD
SCD
SCD
SCD
SCD
SCD
SCD
SCD
SCD
26
33
40
42
49
56
60
67
74
90
100
134
262
200
110
141
275
127
249
Short-Circuit Current Detection Time
t
[SCTA:SCT0] = 0C8H (200µs) (default)
Range:
SCT
0µs to 1023µs; 1µs/step
0ms to 1023ms 1ms/step
Charge Overcurrent Detection
Threshold
V
V
V
V
V
V
V
V
V
= 1mV [OCC2:0] = 0,0,0
= 2mV [OCC2:0] = 0,0,1
= 4mV [OCC2:0] = 0,1,0
= 6mV [OCC2:0] = 0,1,1
= 8mV [OCC2:0] = 1,0,0 (default)
= 12mV [OCC2:0] = 1,0,1
= 16mV [OCC2:0] = 1,1,0
= 24mV [OCC2:0] = 1,1,1
0.2
0.7
1.0
2.0
2.1
3.3
mV
mV
mV
mV
mV
mV
mV
mV
ms
OCC
OCC
OCC
OCC
OCC
OCC
OCC
OCC
OCC
2.8
4.0
5.2
4.5
6.0
7.5
6.6
8.0
9.8
9.6
12.0
17.0
25.0
160
14.4
19.6
27.5
14.5
22.5
Overcurrent Charge Detection Time
t
[OCCTA:OCCT0] = 0A0H (160ms) (default)
Range:
OCCT
0ms to 1023ms 1ms/step
0s to 1023s; 1s per step
Charge Monitor Input Threshold
(Falling Edge)
V
µCCMON bit = “1”; CMON_EN bit = “1”
µCLMON bit = “1”; LMON_EN bit = “1”
µCLMON bit = “1”; LMON_EN bit = “1”
8.2
8.9
0.6
62
9.8
V
V
CHMON
Load Monitor Input Threshold
(Rising Edge)
V
0.45
0.75
LDMON
LDMON
Load Monitor Output Current
I
µA
FN7626 Rev 5.00
February 17, 2016
Page 11 of 64
ISL94203
Electrical Specifications
V
= 26.4V, T = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply across
DD A
operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 7)
TYP
(Note 7)
UNIT
V
VOLTAGE PROTECTION SPECIFICATIONS
Overvoltage Lockout Threshold
(Rising Edge - Any Cell)
[VCn-VC(n-1)]
V
[OVLOB:OVLO0] = 0E80H (4.35V) (default)
Range: 12-bit value (0V to 4.8V)
4.35
OVLO
Overvoltage Lockout Recovery
Threshold - All Cells
V
Falling edge
V
V
V
OVLOR
OVR
Undervoltage Lockout Threshold
(Falling Edge - Any Cell)
[VCn-VC(n-1)]
V
[UVLOB:UVLO0] = 0600H (1.8V) (default)
Range: 12-bit value (0V to 4.8V)
1.8
UVLO
Undervoltage Lockout Recovery
Threshold - All Cells
V
Rising edge
V
V
UVLOR
UVR
Overvoltage Lockout Detection Time
t
Normal operating mode
176
ms
OVLO
5 consutive samples over the limit
(minimum = 160ms, maximum = 192ms)
Undervoltage Lockout Detection
Time
t
Normal operating mode
5 consecutive samples under the limit
(minimum = 160ms, maximum = 192ms)
176
4.25
4.15
1
ms
V
UVLO
Overvoltage Threshold
(Rising Edge - Any Cell)
[VCn-VC(n-1)]
V
[OVLB:OVL0] = 0E2AH (4.25V) (default)
Range: 12-bit value (0V to 4.8V)
OV
Overvoltage Recovery Voltage
(Falling Edge - All Cells)
[VCn-VC(n-1)]
V
[OVRB:OVR0] = 0DD5H (4.15V) (default)
Range: 12-bit value (0V to 4.8V)
V
OVR
OVT
Overvoltage Detection/Release Time
t
[OVTA:OVT0] = 201H (1s) (default) Range:
0ms to 1023ms; 1ms/step
s
0s to 1023s; 1s/step
Undervoltage Threshold
(Falling Edge - Any Cell)
[VCn-VC(n-1)]
V
[UVLB:UVL0] = 0900H (2.7V) (default)
Range: 12-bit value (0V to 4.8V)
2.7
3.0
1
V
UV
UVR
UVT
Undervoltage Recovery Voltage
(Rising Edge - All Cells)
[VCn-VC(n-1)]
V
[UVRB:UVR0] = 0A00H (3.0V) (default)
Range: 12-bit value (0V to 4.8V)
V
Undervoltage Detection Time
t
[UVTA:UVT0] = 201H (1s) (default)
Range:
s
0ms to 1023ms; 1ms/step
0s to 1023s; 1s/step
Undervoltage Release Time
t
[UVTA:UVT0] = 201H (1s) + 2s (default)
Range:
3
s
UVTR
(0ms to 1023ms) + 2s; 1ms/step
(0s to 1023s) + 2s; 1s/step
Sleep Voltage Threshold
(Falling Edge - Any Cell)
[VCn-VC(n-1)]
V
[SLLB:SLL0] = 06AAH (2.0V) (default)
Range: 12-bit value (0V to 4.8V)
2.0
1
V
s
SLL
Sleep Detection Time
t
[SLTA:SLT0] = 201H (1s) (default) Range:
0ms to 1023ms; 1ms/step
0s to 1023s; 1s/step
SLT
Low Voltage Charge Threshold
(Falling Edge - Any Cell)
[VCn-VC(n-1)]
V
[LVCHB:LVCH0] = 07AAH (2.3V) (default)
Range: 12-bit value (0V to 4.8V)
Pre-charge if any cell is below this voltage
2.3
117
V
LVCH
Low Voltage Charge Threshold
Hysteresis
V
mV
LVCHH
FN7626 Rev 5.00
February 17, 2016
Page 12 of 64
ISL94203
Electrical Specifications
V
= 26.4V, T = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply across
DD A
operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 7)
TYP
4.2
(Note 7)
UNIT
V
End-of-Charge Threshold
(Rising Edge - Any Cell)
[VCn-VC(n-1)]
V
[EOCSB:EOCS0] = 0E00H (4.2V) (default)
Range: 12-bit value (0V to 4.8V)
EOC
End-of-Charge Threshold Hysteresis
Sleep Mode Timer
V
EOCH
117
90
mV
t
[MOD7:MOD0] = 0DH (off)
(default)
min
SMT
Range:
0s to 255 minutes
Watchdog Timer
t
[WDT4:WDT0] = 1FH (31s) (default)
Range: 0s to 31s
31
s
WDT
TEMPERATURE PROTECTION SPECIFICATIONS
Internal Temperature Shutdown
Threshold
T
[IOTSB:IOTS0] = 02D8H
115
°C
ITSD
Internal Temperature Recovery
T
[IOTRB:IOTR0] = 027DH
95
°C
V
ITRCV
External Temperature Output Voltage
V
Voltage output at TEMPO pin (during
2.30
2.45
2.60
TEMPO
temperature scan); I
= 1mA
TEMPO
External Temperature Limit
Threshold (Hot) - xT1 or xT2
Charge, Discharge, Cell Balance
(see Figure 3)
T
xTn Hot threshold. Voltage at V
xT1 or xT2 = 04B6H
TGain = 0
~+55°C; thermistor = 3.535k
Detected by COT, DOT, CBOT bits = 1
,
0.265
0.295
0.672
0.595
V
V
V
V
XTH
TEMPI
External Temperature Recovery
Threshold (Hot) - xT1 or xT2
Charge, Discharge, Cell Balance
(see Figure 3)
T
xTn Hot recovery voltage at V
xT1 or xT2 = 053EH
TGain = 0
XTHR
TEMPI
(~+50°C; thermistor = 4.161k)
Detected by COT, DOT, CBOT bits = 0
External Temperature Limit
Threshold (Cold) - xT1 or xT2
Charge, Discharge, Cell Balance
(see Figure 3)
T
xTn Cold threshold. Voltage at V
xT1 or xT2 = 0BF2H
TGain = 0
(~ -10°C; thermistor = 42.5k)
Detected by CUT, DUT, CBUT bits
XTC
TEMPI
External Temperature Recovery
Threshold (Cold) - xT1 or xT2
Charge, Discharge, Cell Balance
(see Figure 3)
T
xTn Cold recovery voltage at V
xT2 = 0A93H
. xT1 or
TEMPI
XTCH
TGain = 0
(~5°C; thermistor = 22.02k)
Detected by CUT, DUT, CBUT bits
CELL BALANCE SPECIFICATIONS
Cell Balance FET Gate Drive Current
VC1 to VC5 (current out of pin)
VC6 to VC8 (current into pin)
15
15
25
25
35
35
µA
µA
V
Cell Balance Maximum Voltage
Threshold (Rising Edge - Any cell)
[VCMAX]
V
[CBVUB:CBVU0] = 0E00H (4.2V) (default)
Range: 12-bit value (0V to 4.8V)
4.2
CBMX
Cell Balance Maximum Threshold
Hysteresis
V
117
3.0
mV
V
CBMXH
Cell Balance Minimum Voltage
Threshold (Falling Edge - Any cell)
[VCMIN]
V
[CBVLB:CBVL0] = 0A00H (3.0V) (default)
Range: 12-bit value (0V to 4.8V)
CBMN
Cell Balance Minimum Threshold
Hysteresis
V
117
mV
CBMNH
FN7626 Rev 5.00
February 17, 2016
Page 13 of 64
ISL94203
Electrical Specifications
V
= 26.4V, T = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply across
DD A
operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 7)
TYP
2.0
(Note 7)
UNIT
V
Cell Balance Maximum Voltage Delta
Threshold (Rising Edge - Any Cell)
[VCn-VC(n-1)]
V
[CBDUB:CBD0] = 06AAH (2.0V) (default)
Range: 12-bit value (0V to 4.8V)
CBDU
Cell Balance Maximum Voltage Delta
Threshold Hysteresis
V
117
mV
CBDUH
WAKE-UP SPECIFICATIONS
Device CHMON Pin Voltage Threshold
(Wake on Charge)
(Rising Edge)
V
V
CHMON pin rising edge
Device wakes up and sets Sleep flag LOW
7.0
8.0
9.0
V
V
WKUP1
WKUP2
Device LDMON Pin Voltage Threshold
(Wake on Load)
LDMON pin falling edge
Device wakes up and sets Sleep flag LOW
0.15
0.40
0.70
(Falling Edge)
OPEN-WIRE SPECIFICATIONS
Open-Wire Current
I
1.0
mA
V
OW
Open-Wire Detection Threshold
V
VCn-VC(n-1); VCn is open. (n = 2, 3, 4, 5, 6, 7,
8). Open-wire detection active on the VCn
input.
-0.3
OW1
V
V
VC1-VC0; VC1 is open. Open-wire detection
active on the VC1 input.
0.4
V
V
OW2
VC0-VSS; VC0 is open. Open-wire detection
active on the VC0 input.
1.25
OW3
FET CONTROL SPECIFICATIONS
DFET Gate Voltage
V
(ON) 100µA load; V = 36V
DD
47
8
52
9
57
10
V
V
DFET1
DFET2
DFET3
V
V
(ON) 100µA load; V = 6V
DD
(OFF)
0
V
CFET Gate Voltage (ON)
PCFET Gate Voltage (ON)
V
V
V
V
V
V
(ON) 100µA load; V = 36V
DD
47
8
52
9
57
10
V
CFET1
CFET2
CFET3
PFET1
PFET2
PFET3
(ON) 100µA load; V = 6V
DD
V
(OFF)
V
V
DD
(ON) 100µA load; V = 36V
DD
47
8
52
9
57
10
V
(ON) 100µA load; V = 6V
DD
V
(OFF)
V
V
DD
FET Turn-Off Current (DFET)
FET Turn-Off Current (CFET)
FET Turn-Off Current (PCFET)
FETSOFF Rising Edge Threshold
FETSOFF Falling Edge Threshold
I
14
9
15
16
17
17
mA
mA
mA
V
DF(OFF)
I
13
13
CF(OFF)
PF(OFF)
I
9
V
FETSOFF rising edge threshold. Turn off FETs
FETSOFF falling edge threshold. Turn on FETs
1.8
1.2
FO(IH)
V
V
FO(IL)
SERIAL INTERFACE CHARACTERISTICS (Note 8)
Input Buffer Low Voltage (SCL, SDA)
V
V
Voltage relative to V of the device
SS
-0.3
V
V
x 0.3
V
V
RGO
IL
Input Buffer High Voltage (SCL, SDAI,
SDAO)
Voltage relative to V of the device
SS
V
x 0.7
+ 0.1
RGO
RGO
IH
Output Buffer Low Voltage (SDA)
V
I
= 1mA
OL
0.4
V
V
OL
2
SDA and SCL Input Buffer Hysteresis I CHYST Sleep bit = 0
0.05 x V
RGO
SCL Clock Frequency
f
400
kHz
SCL
FN7626 Rev 5.00
February 17, 2016
Page 14 of 64
ISL94203
Electrical Specifications
V
= 26.4V, T = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply across
DD A
operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 7)
TYP
(Note 7)
UNIT
ns
Pulse Width Suppression Time at
SDA and SCL Inputs
t
Any pulse narrower than the maximum spec
is suppressed.
50
IN
SCL Falling Edge to SDA Output Data
Valid
t
From SCL falling crossing V (minimum),
IH
0.9
µs
µs
AA
until SDA exits the V (maximum) to V
IL
IH
(minimum) window
Time the Bus Must Be Free Before
Start of New Transmission
t
SDA crossing V (minimum) during a STOP
IH
1.3
BUF
condition to SDA crossing V (minimum)
IH
during the following START condition
Clock Low Time
t
Measured at the V (maximum) crossing
IL
1.3
0.6
0.6
µs
µs
µs
LOW
Clock High Time
t
Measured at the V (minimum) crossing
IH
HIGH
Start Condition Set-Up Time
t
SCL rising edge to SDA falling edge, both
SU:STA
crossing the V (minimum) level
IH
Start Condition Hold Time
Input Data Set-Up Time
Input Data Hold Time
t
From SDA falling edge crossing
0.6
100
0
µs
ns
µs
HD:STA
V
V
(maximum) to SCL falling edge crossing
(minimum)
IL
IH
t
From SDA exiting the V (maximum) to V
IL
(minimum) window to SCL rising edge
SU:DAT
HD:DAT
IH
crossing V (minimum)
IL
t
From SCL falling edge crossing
0.9
V
V
(minimum) to SDA entering the
IH
IL
(maximum) to V (minimum) window
IH
Stop Condition Set-Up Time
Stop Condition Hold Time
Data Output Hold Time
t
From SCL rising edge crossing V (minimum)
IH
0.6
0.6
0
µs
µs
ns
SU:STO
to SDA rising edge crossing V (maximum)
IL
t
From SDA rising edge to SCL falling edge.
HD:STO
Both crossing V (minimum)
IH
t
From SCL falling edge crossing V
DH
IL
(maximum) until SDA enters the V
IL
(maximum) to V (minimum) window
IH
SDA and SCL Rise Time
SDA and SCL Fall Time
t
From V (maximum) to V (minimum)
IL IH
300
300
ns
ns
kΩ
R
t
From V (minimum) to V (maximum)
IH IL
F
SDA and SCL Bus Pull-Up Resistor
Off-Chip
R
Maximum is determined by t and t
F
1
OUT
R
For C = 400pF, maximum is 2kΩ ~ 2.5kΩ
B
For C = 40pF, maximum is 15kΩ~ 20kΩ
B
Input Leakage (SCL, SDA)
EEPROM Write Cycle Time
NOTES:
I
-10
10
µA
LI
t
+25°C
30
ms
WR
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Device MIN and/or MAX values are based on
temperature limits established by characterization and are not production tested.
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN7626 Rev 5.00
February 17, 2016
Page 15 of 64
ISL94203
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
WAVEFORM
INPUTS
OUTPUTS
DON’T CARE:
CHANGES
ALLOWED
CHANGING:
STATE NOT
KNOWN
MUST BE
STEADY
WILL BE
STEADY
N/A
CENTER LINE
IS HIGH
IMPEDANCE
MAY CHANGE
FROM LOW
TO HIGH
WILL CHANGE
FROM LOW
TO HIGH
MAY CHANGE
FROM HIGH
TO LOW
WILL CHANGE
FROM HIGH
TO LOW
Timing Diagrams
External Temperature Configuration
TEMPO PIN
22kΩ
22kΩ
xT1 PIN
xT2 PIN
DIGITAL TEMPERATURE VOLTAGE READING =
xTn * 2 (TGAIN BIT = 0)
xTn * 1 (TGAIN BIT = 1)
10kΩ
10kΩ
THERMISTORS: 10k, MuRata XH103F
FIGURE 3. EXTERNAL TEMPERATURE CONFIGURATION
Wake-Up Timing
ENTERS SLEEP MODE
LDMON PIN
V
WKUP2
<1µs
CAN STAY IN
SLEEP MODE
CAN STAY IN
SLEEP MODE
IN_SLEEP BIT
V
WKUP1
<1µs
CHMON PIN
~50ms
CAN STAY IN
SLEEP MODE
CAN STAY IN
SLEEP MODE
IN_SLEEP BIT
~140ms
DFET/CFET
If LDMON or CHMON is “active” when entering
Sleep mode, the IC wakes up after a short delay.
FIGURE 4. WAKE-UP TIMING (FROM SLEEP)
FN7626 Rev 5.00
February 17, 2016
Page 16 of 64
ISL94203
Power-Up Timing
V
WKUP1
CHMON PIN
~3s
256ms
LDMON CHECK
DFET/CFET
TURN ON FETs IF NO PACK FAULTS
RGO
~4ms
2
I C COMMUNICATION
FIGURE 5. POWER-UP TIMING (FROM POWER UP/SHUTDOWN)
Change in FET Control
SCL
BIT
3
BIT
BIT
1
BIT
0
BIT
1
BIT
0
SDA
ACK
ACK
~1µs
2
DATA
~1µs (~500µs IF BOTH FETs OFF)
t
t
FTOFF
FTON
90%
90%
DFET/CFET TURN ON
10%
10%
2
FIGURE 6. I C FET CONTROL TIMING
V
FO(OFF)
V
FETSOFF PIN
FO(ON)
~500µs
~1µs
~1µs
DFET/CFET TURN ON
FET CHARGE PUMP
FIGURE 7. FETSOFF FET CONTROL TIMING
FN7626 Rev 5.00
February 17, 2016
Page 17 of 64
ISL94203
Automatic Temperature Scan
128ms
1024ms
2048ms
MONITOR TIME = 120µs
TEMPO PIN
2.5V
EXTERNAL
TEMPERATURE
OVER-TEMPERATURE
THRESHOLD
UNDER-TEMP
OVER-TEMP
xTn
DELAY TIME = 20µs
DELAY TIME = 20µs
MONITOR TEMPERATURE DURING THIS
TIME PERIOD
CBOT, DOT, COT BITs
FET SHUTDOWN OR CELL BALANCE TURN
OFF (IF ENABLED)
SEE Figure 3 FOR TEST CIRCUIT
FIGURE 8. AUTOMATIC TEMPERATURE SCAN
Serial Interface Timing Diagrams
BUS TIMING
t
t
t
R
HIGH
LOW
t
F
SCL
t
SU:STA
t
t
t
SU:DAT
SU:STO
HD:DAT
t
HD:STA
SDA
(INPUT TIMING)
t
BUF
t
t
AA
DH
SDA
(OUTPUT TIMING)
FIGURE 9. SERIAL INTERFACE BUS TIMING
FN7626 Rev 5.00
February 17, 2016
Page 18 of 64
ISL94203
Discharge Overcurrent/Short-Circuit Monitor
LOAD RELEASES DURING THIS TIME
256ms
3 s
V
LDMON
LDMON PIN
DETECTS 2 LDMON PULSES ABOVE THRESHOLD
V
SC
V
OCD
V
DSENSE
t
t
t
SCD
SCD
OCD
‘1’
‘0’
‘0’
DOC BIT
DSC BIT
‘1’
2.5V
SD
OUTPUT
µC REGISTER 1 READ
µC IS OPTIONAL
µC REGISTER 1 READ
LDMON DETECTS LOAD RELEASE
LDMON DETECTS LOAD RELEASE
RESETS DOC, SCD BIT, TURNS ON FET
RESETS DOC, SCD BIT, TURNS ON FET
V
+15V
DD
DFET
OUTPUT
ISL94203 TURNS ON DFET
(µCFET BIT = 0)
FIGURE 10. DISCHARGE/SHORT-CIRCUIT MONITOR
Charge Overcurrent Monitor
(Assumes NO_OCCR bit is ‘0’)
CHARGER RELEASES
V
CHMON
DETECTS 2 CHMON PULSES BELOW THRESHOLD
CHMON PIN
V
CSENSE
V
OCC
t
OCC
‘1’
‘0’
COC BIT
2.5V
SD
OUTPUT
CHMON DETECTS CHARGER RELEASE
RESETS DOC, SCD BIT, TURNS ON FET
REGISTER 1 READ
V
+15V
DD
CFET
OUTPUT
ISL94203 TURNS ON CFET
(µCFET BIT = 0)
FIGURE 11. CHARGE OVERCURRENT MONITOR
FN7626 Rev 5.00
February 17, 2016
Page 19 of 64
ISL94203
N-CHANNEL FETs
Functional Description
CHG+
DISCHG+
PACK+
This IC is intended to be a stand-alone battery pack monitor, so it
provides monitor and protection functions without using an
external microcontroller.
The part locates the power control FETs on the high side with a
built-in charge pump for driving N-channel FETs. The current
sense resistor is also on the high side.
CS1
CS2
100Ω
1kΩ
1kΩ
Power is minimized in all areas, with parts of the circuit powered
down a majority of the time, to extend battery life. At the same
time, the RGO output stays on so that any connected
microcontroller can remain on most of the time.
VBATT
470nF
47nF
VC8
VC7
The ISL94203 includes:
• Input level shifter to enable monitoring of battery stack
voltages
47nF
• 14-bit ADC converter, with voltage readings trimmed and
saved as 12-bit results
FIGURE 12. SINGLE PATH FET DRIVE/POWER SUPPLY DETAIL
• 1.8V voltage reference (0.8% accurate)
• 2.5V regulator, with the voltage maintained during sleep
N-CHANNEL FETs
• Automatic scan of the cell voltages; overvoltage, undervoltage
and sleep voltage monitoring
CHG+
• Selectable overcurrent detection settings
3.3M
- 8 Discharge overcurrent thresholds
DISCHG+
- 8 Charge overcurrent thresholds
- 8 Short-circuit thresholds
500
500
- 12-bit programmable discharge overcurrent delay time
- 12-bit programmable charge overcurrent delay time
- 12-bit programmable short-circuit delay time
CS2
CS1
100Ω
1kΩ
1kΩ
VBATT
470nF
47nF
• Current sense monitor with gain that provides the ability to
read the current sense voltage
VC8
VC7
• Second external temperature sensor for use in monitoring the
pack or power FET temperatures
• EEPROM for storing operating parameters and a user area for
general purpose pack information
47nF
Battery Connections
FIGURE 13. DUAL PATH FET DRIVE/POWER SUPPLY DETAIL
Power Path
Figure 12 shows the main power path connections for a single
charge/discharge path. Figure 13 shows the connection for
separate charge/discharge paths.
Pack Configuration
A register in EEPROM (CELLS) identifies the number of cells that
are supposed to be present, so the ISL94203 only scans these
cells. This register is also used for the cell balance operation. The
register contents are a 1:1 representation of the cells connected
to the pack. For example, in a 6 cell pack, the value in CELLS is
‘11100111’ (CFH), which indicates that cells 1, 2, 3, 6, 7 and 8
are connected. Also see Figure 14 on page 21.
These figures show Schottky diodes on the VDD pin. These are to
maintain the voltage on the VDD pin during high current
conditions or when the Charge FET is OFF. These are not needed
if V can be maintained within 0.5V of V
.
DD BATT
The CHMON pin connects to the pack pin that receives the charge
and the LDMON pin connects to the pack pin that drives the load.
For the single path application, these pins can tie together.
Battery Cell Connections
Suggested connections for pack configurations varying from 3
cells to 8 cells are shown in Figure 14.
FN7626 Rev 5.00
February 17, 2016
Page 20 of 64
ISL94203
8 CELLS
VC8
7 CELLS
VC8
6 CELLS
VC8
CB8
VC7
CB7
VC6
CB8
VC7
CB7
VC6
CB8
VC7
CB7
VC6
CB6
VC5
CB5
VC4
CB6
VC5
CB5
VC4
CB6
VC5
CB5
VC4
CB4
VC3
CB4
VC3
CB4
VC3
CB3
VC2
CB2
VC1
CB1
CB3
VC2
CB2
VC1
CB1
CB3
VC2
CB2
VC1
CB1
VC0
VSS
VC0
VSS
VC0
VSS
5 CELLS
VC8
4 CELLS
VC8
3 CELLS
VC8
CB8
VC7
CB7
VC6
CB8
VC7
CB7
VC6
CB8
VC7
CB7
VC6
CB6
VC5
CB5
VC4
CB6
VC5
CB5
VC4
CB6
VC5
CB5
VC4
CB4
VC3
CB4
VC3
CB4
VC3
CB3
VC2
CB2
VC1
CB1
CB3
VC2
CB2
VC1
CB1
CB3
VC2
CB2
VC1
CB1
VC0
VSS
VC0
VSS
VC0
VSS
NOTE: MULTIPLE CELLS CAN BE CONNECTED IN PARALLEL
FIGURE 14. BATTERY CONNECTION OPTIONS
starts the state machine. If some cells are not connected, the
state machine recognizes this, either through the open-wire test
(see “Typical Operating Conditions” on page 24) or because the
monitored cell voltage reads zero, when the “CELLS” register
indicates that there should be a voltage at that pin. If the cell
voltages do not read correctly, then the ISL94203 remains in the
POR loop until conditions are valid for power-up (It is for this
reason that the factory default for the device is 3 Cells. When
manufacturing the application board, cells 1, 2 and 8 must be
connected to power up. If other cells are connected it is OK, but
for the other cells to be monitored, the CELLS register needs to
be changed).
Operating Modes
Power-Up Operation
When the ISL94203 first connects to the battery pack, it is
unknown which pins connect first or in what order. When the VDD
and VSS pins connect, the device enters the power-down state. It
remains in this state until a charger is connected. The device will
also power up if the CHMON pin is connected to the VDD pin
through an outside resistor to simplify the PCB manufacture. It is
possible that the pack powers up automatically when the battery
stack is connected due to momentary conduction through the
power FET G-S and G-D capacitors.
If the inputs all read good during this sequence, then the state
machine enters the normal monitor state. In the normal state, if
all cell voltages read good and there are no overcurrent or
Once the charger connects (or CHMON connects), the internal
power supply turns on. This powers up all internal supplies and
FN7626 Rev 5.00
February 17, 2016
Page 21 of 64
ISL94203
temperature issues and there is no load, the FETs turn on. To
determine if there is a load, the device does a load check. This
operation waits for about three seconds and then must see no
load for two successive load monitor cycles (256ms apart).
When the cell voltages drop, the ISL94203 remains on if the VDD
voltage remains above 1V and the VRGO voltage is above 2.25V.
This is to maintain operation of the device in the event of a short
drop in cell voltage due to a pack short-circuit condition. In the
event of a longer battery stack voltage drop, then the device will
During the POR operation, the RAM registers are all reset to
default conditions from values saved in the EEPROM.
return to a power-down condition if V drops below a POR
DD
threshold of about 3.5V when V
Figures 15 and 16).
is below 2.25V (see
RGO
•
•
DO A VOLTAGE SCAN.
POWER-DOWN
STATE
ONLY LOOK AT CELLS THAT ARE
SPECIFIED IN THE “CELL” REG.
•
•
IF ALL CELL VOLTAGES AND TEMPS
ARE OK, DO A LOAD TEST.
CHARGER CONNECT
BATTERY STACK CONNECT
AND V > V
IF THERE ARE ANY ERRORS, KEEP
SCANNING VOLTAGES,
DD
POR
TEMPERATURES AND LOAD AT
NORMAL SCAN RATES.
POWER ON RESET
FETs OFF, NO CURRENT SCAN.
V
< 1.2V
RGO
OR
SCAN ONLY VOLTAGES, TEMP, LOAD
(ANY CELL < V
UVLOPD = 1)
OR
FOR 160ms AND
UVLO
ALL VOLTAGES OK
TEMP OK
PDWN BIT SET
NO LOAD
NORMAL OPERATING
MODE
FIGURE 15. POWER-ON RESET STATE MACHINE
WHILE RGO IS ABOVE 2.25V, V
POR DOES NOT CAUSE A POWER-DOWN
DROPPING BELOW
DD
6V
POR ~3.5V
POR SCAN
UVR
UV
VDD
LAST CELL CONNECTED
POR
(RESET
REGISTERS)
POWERED STATE
RGO
2.25V
3s
DFET
CHMON
LDMON
FIGURE 16. POWER-UP/POWER-DOWN/LOW VOLTAGE WAVEFORMS
FN7626 Rev 5.00
February 17, 2016
Page 22 of 64
ISL94203
Doze bit, the device remains in Doze mode regardless of the
timer or the current. Setting the mode control bits to 0 allows the
device to control the mode.
Wake-Up Circuit
When in a Sleep mode, the wake-up circuit detects that the
output pin is pulled low (as might be the case when a load is
attached to the pack and the FETs are off) or pulled high (as
might be the case when the charger is connected and the FETs
are off).
Note: Setting the Idle/Doze timer to 0 immediately forces the
device into the Doze mode when there is no current.
SLEEP MODE
The wake-up circuit does not draw significant continuous current
from the battery.
The ISL94203 enters the Sleep mode when the voltage on the
cells drops below the sleep voltage threshold for a period of time,
specified by the Sleep Delay Timer. To prevent the device from
entering the Sleep mode by a low voltage on the cells, the Sleep
Voltage Level (SLL) register can be set to 0.
Low Power States
In order to minimize power consumption, most circuits are kept
off when not being used and items are sampled when possible.
The device can also enter the Sleep mode from the Doze mode, if
there has been no detected current for more than the duration of
the Sleep mode timer (set in the MOD register). In this case, the
device remains in Doze mode until there has been no current for
0 to 240 minutes (with 16 minute steps).
There are five power states in the device (see Figure 17).
NORMAL MODE
This is the normal monitoring/scan mode. In this mode, the
device monitors the current continuously and scans the voltages
every 32ms. If balancing is called for, then the device activates
external balancing components. All necessary circuits are on and
unnecessary circuits are off.
The external microcontroller forces the ISL94203 to enter Sleep
mode by writing to the Sleep bit (Register 88H). Setting the Sleep
bit forces the Sleep mode, regardless of the current flow.
Note: If both Idle/Doze and Sleep timers are set to 0, the device
immediately goes to sleep. To recover from this condition, apply
current to the device or hold the LDMON pin low (or CHMON pin
high) and write non-zero values to the registers.
During the scan, the ISL94203 draws more current as it activates
the input level shifter, the ADC and data processing. Between
scans, circuits turn off to minimize power consumption.
IDLE MODE
While in the Sleep mode, everything is off except for the 2.5V
regulator and the wake up circuits. The device can be waken by
LDMON connection to a load or CHMON connection to a charger.
If there is no current flowing for 0 to 15 minutes (set in the MOD
register), then the device enters the Idle mode. In this mode,
voltage scanning slows to every 256ms per scan. The FETs and
the LDO remain on. In this mode, the device consumes less
current, because there is more time between scans.
POWER-DOWN MODE
This mode occurs when the voltage on the pack is too low for
proper operation. This occurs when:
When the ISL94203 detects any charge or discharge current, the
device exits the Idle mode and returns to the Normal mode of
operation.
• V is less than the POR threshold and RGO < 2.25V. This
DD
condition occurs if cells discharge over a long period of time.
The device does not automatically enter the Idle mode if the
µCSCAN bit is set to “1”, because the microcontroller is in charge
of performing the scan and controlling the operation.
• V is less than 1V and RGO > 2.25V. This condition can occur
DD
during a short-circuit with minimum capacity cells. The V
drops out, but the RGO cap maintains the logic supply.
DD
Setting the Idle bit to “1” forces the device to enter Idle mode,
regardless of current flow. When a µC sets the Idle bit, the device
remains in Idle, regardless of the timer or the current. Setting the
mode control bits to 0 allows the device to control the mode.
• When any cell voltage is less than the UVLO threshold for more
than about 160ms (and UVLOPD = 1).
• If commanded by an external µC.
Recovering out of any low power state brings the ISL94203 into
the Normal operating mode.
DOZE MODE
While in Idle mode, if there is no current flowing for another 0 to
16 minutes (same value as the idle timer), the device enters the
Doze mode, where cell voltage sampling occurs every 512ms.
The FETs and the LDO remain on. In this mode, the device
consumes less current than Idle mode, because there is more
time between scans.
EXCEPTIONS
There is one exception to the normal sequence of mode
management. When the microcontroller sets the µCSCAN bit, the
internal scan stops. This means that the device no longer looks
for the conditions required for sleep. The external microcontroller
needs to manage the modes of operation.
When the ISL94203 detects any charge or discharge current, the
device exits Doze mode and returns to the Normal mode.
The lower device in a cascaded stack of ISL94203s does not
detect current. As such, the device will progress through the
power states to sleep regardless of the pack current. An external
µC needs to set the operating state to Idle or Doze to prevent the
lower device from going to sleep.
The device does not automatically enter the Idle mode if the
µCSCAN bit is set to “1”, because the microcontroller is in charge
of performing the scan and controlling the operation.
Setting the Doze bit forces the device to enter the Doze mode,
regardless of the current flow. When a microcontroller sets the
FN7626 Rev 5.00
February 17, 2016
Page 23 of 64
ISL94203
{ANY CELL VOLTAGE LESS THAN UVLO
FOR 160ms AND UVLOPD = 1} OR
RGO < 1.2V OR
POWER-DOWN STATE
POWER CONSUMPTION <1µA
PDWN BIT SET TO “1”
FIRST POWER UP: VOLTAGE ON VDD RISES ABOVE
THE POR THRESHOLD.
ALREADY POWERED: A CHARGER WAKE UP SIGNAL.
NORMAL OPERATING
STATE
POWER CONSUMPTION AVERAGE
450µA (2mA PEAKS)
WAKE UP SIGNAL (EITHER
CHARGER OR LOAD)
NO CHARGE OR DISCHARGE CURRENT
DETECTED FOR 1-16 MIN OR IDLE BIT IS SET
IDLE STATE
DOZE STATE
SLEEP STATE
POWER CONSUMPTION AVERAGE
350µA MAX (2mA PEAKS)
ANY CELL VOLTAGE
DROPS BELOW SLEEP
THRESHOLD FOR
NO CHARGE OR DISCHARGE CURRENT DETECTED
FOR 1 TO 16 MIN OR DOZE BIT IS SET
SLEEP DELAY TIME
OR SLEEP BIT
IS SET
WHEN THE DEVICE
POWER CONSUMPTION AVERAGE
300µA (2mA PEAKS)
DETECTS ANY CHARGE OR
DISCHARGE CURRENT,
OPERATION MOVES FROM
DOZE OR IDLE STATES
BACK TO THE NORMAL
OPERATING STATE
NO CHARGE OR DISCHARGE CURRENT DETECTED
FOR 32 TO 256 MIN OR SLEEP BIT IS SET
POWER CONSUMPTION AVERAGE
15µA
FIGURE 17. ISL94203 POWER STATES
TABLE 1. TYPICAL OPERATING CONDITIONS (Continued)
Typical Operating Conditions
TYPICAL
3
UNIT
sec
FUNCTION
Table 1 shows some typical device operating parameters.
Wake-Up Delay from Shutdown or Initial
Power-Up. Time to Turn On Power FETs
Following Charger Connection. All Pack
Conditions OK.
TABLE 1. TYPICAL OPERATING CONDITIONS
TYPICAL
14
UNIT
Bits
Bits
µs
FUNCTION
ADC Resolution
Default Idle/Doze Mode Delay Times
Default Sleep Mode Delay Time
10
90
min
min
ADC Results Saved (and calibrated)
ADC Conversion Time
12
10
Overcurrent/Short-Circuit Scan Time
Continuous
125
Cell Fail Detection
Voltage Scan Time (Time per Cell) Includes
Settling Time
µs
The Cell Fail (CELLF) condition indicates that the difference
between the highest voltage cell and the lowest voltage cell
exceeds a programmed threshold (as specified in the CBDU
register). Once detected, the CELLF condition turns off the cell
balance FETs and the power FETs, but only if the µCFET bit = “0.”
Setting the µCFET bit = “1” prevents the power FETs from turning
off during a CELLF condition. The microcontroller is then
responsible for the power FET control.
Voltage Protection Scan Rate
(Time between scans) Normal Mode;
Idle Mode
32
256
512
ms
Doze Mode
Internal Over-temperature Turn-on/Turn-off
Delay Time
128
ms
ms
External Temperature Autoscan On Time;
TEMPO = 2.5V
0.2
An EEPROM bit, CFPSD, when set to “1”, enables the PSD
activation when the ISL94203 detects a Cell Fail condition. When
CELLF = “1” and CFPSD = “1”, the power FETs and cell balance
FETs turn off, PLUS the PSD output goes active. The pack
designer can use the PSD pin output to deactivate the pack by
blowing a fuse.
External Temperature Autoscan Off Time;
TEMPO = 0V Normal Mode
Idle Mode
128
1024
2048
ms
ms
Doze Mode
Wake-Up Delay from Sleep. Time to Turn On
Power FETs Following Load or Charger
Connection. All Pack Conditions OK.
140
The CELLF function can be disabled by setting the CBDU value to
FFFH. In this case, the voltage differential can never exceed the
limit. However, disabling the cell fail condition also disables the
open-wire detection (see “Open-Wire Detection” on page 25).
FN7626 Rev 5.00
February 17, 2016
Page 24 of 64
ISL94203
VCn
CELL n
INTERNAL
2.5V SUPPLY
NOTE: THE OPEN-WIRE TEST IS
RUN ONLY IF THE DEVICE DETECTS
THE CELLF CONDITION AND THEN
ONCE EVERY 32 VOLTAGE SCANS
WHILE A CELLF CONDITION
VC4
VC3
VC2
CELL 4
CELL 3
CELL 2
CELL 1
EXISTS. EACH CURRENT SOURCE
IS TURNED ON SEQUENTIALLY.
VC1
VC0
FIGURE 18. OPEN-WIRE DETECTION
the voltage of the input to the open-wire threshold of -1.4V
(relative to the adjacent cell) within 30µs. With the cell present,
the voltage will have a negligible change.
Open-Wire Detection
There is a special open battery wire detection function on this
device. The most important reason for an open-wire detection is
to turn off the power FETs if there is an open wire to prevent the
cells from being excessively charged or discharged.
Each input has a comparator that detects if the voltage on an
input drops more than 1.4V below the voltage of the cell below.
Exceptions are VC1 and VC0. For VC1, the circuit looks to see if
the voltage drops below 1V. For VC0, the circuit looks to see if the
voltage exceeds 1.4V. If any comparator trips, then the device
sets an OPEN error flag indicating an open-wire failure and
disables cell balancing. See Figure 19 for sample timing.
Secondarily, the open-wire function prevents the operation of cell
balancing when there is an open wire. There are two reasons for
this. First, if there is an open wire, cell balancing is compromised.
Second, when the cell balance turns on the external balancing
FET and there is an open wire, excessive voltage may appear on
the ISL94203 VCn input pins. Internal clamps and input series
resistors prevent damage as a result of short term exposure to
higher input voltages.
With the open-wire setting of 1mA, input resistors of 1kΩ create
a voltage drop of 1V. This voltage drop, combined with the body
diode clamp of the cell balance FET, provides the -1.4V needed to
detect an open wire. For this reason and for the increased
protection, it is not recommended that smaller input series
resistors be used. For example, with a 100Ω input resistor, the
voltage across the input resistor drops only 0.1V. This will not
allow the input open-wire detection hardware to trigger (although
the digital detection of an open wire still works, the hardware
detection automatically turns off the open-wire current).
The open-wire feature uses built in circuits to force short pulses
of current into or out of the input capacitors (see Figure 18).
When there is no open wire, the battery cell itself changes little in
response to the open-wire test.
The open-wire operation is disabled by setting a control bit
(DOWD) to “1”. When enabled (DOWD = “0”), the ISL94203
performs an open-wire test when the CELLF condition exists and
then once every 32 voltage scans as long as the CELLF condition
remains. A CELLF condition is the first indication that there might
be an open wire.
Input resistors larger than 1kΩ may be desired to increase the
input filtering. This is allowed in the open-wire test, by providing
an increase in the detection time (by changing the OWT value.)
However, increasing the input resistors can significantly affect
measurement accuracy. The ISL94203 has up to 2µA variation in
the input measurement current. This amounts to about 2mV
measurement error with 1k resistors (this error has been factory
calibrated out). However, 10kΩ resistors can result in up to 20mV
measurement errors. To increase the input filtering, the preferred
method is to increase the size of the capacitors.
In operation, the open-wire circuit pulls (or pushes) 1mA of
current sequentially on each VCn input for a period of time. The
open-wire on-time is programmable by a value in the OWT
register. The pulse duration is programmable between 1µs and
512ms. The default values for current and time are 1mA current
and 1ms duration. Note: In the absence of a battery cell, 1mA
input current, along with an external capacitor of 4.7nF, changes
FN7626 Rev 5.00
February 17, 2016
Page 25 of 64
ISL94203
PACK VC5 OPEN WIRE
PACK OPEN WIRE CLEARED
CELLF THRESHOLD
PACK CELL IMBALANCE
CBAL FETs TURN OFF
VC
VC
-
MAX
MIN
CELLF BIT
1s (Note 12)
NO OPEN WIRE SCANS
~160ms (DEFAULT)
OPEN WIRE SCAN
t
OW
~1ms
VC8 OW TEST
VC7 OW TEST
VC6 OW TEST
VC5 OW TEST
VC4 OW TEST
VC3 OW TEST
VC2 OW TEST
VC1 OW TEST
DEFAULT = 20ms
VC6
VC5
VC4
1V
32ms
(Note 9)
~1.7V
(Note 13)
(Note 10)
VOLTAGE SCAN
OPEN BIT
VOLTAGE SCAN REPORTS THAT
VC5 = 0V AND VC6 = 4.8V
NOTES:
9. Voltage drop = 1mA * 1kΩ = 1V
10. Voltage = V of CB5 Balance FET body diode + (1mA * 1kΩ)
F
11. OWPSD bit = 0
12. This time is 8s in Idle and 16s in Doze
13. This 32ms scan rate increases to 256ms in Idle and 512ms in Doze
FIGURE 19. OPEN-WIRE TEST TIMING
Depending on the selection of the input filter components, the
internal open-wire comparators may not detect an open-wire
condition. This might happen if the input resistor is small. In this
case, the body diode of the cell balance FET may clamp the input
before it reaches the open-wire detection threshold. To overcome
this limitation and provide a redundant open-wire detection, at
the end of the open-wire scan, all input voltages are converted to
digital values. If any digital value equals 0V (minimum) or 4.8V
(maximum), the device sets an OPEN error flag indicating an
open-wire failure.
When an open-wire condition occurs and OWPSD = “1”, the OPEN
flag is set, the ISL94203 turns off all power FETs and the cell
balance FETs and the ISL94203 sets the PSD output port active.
The device can automatically recover from an open-wire
condition, because the open-wire test is still functional, unless
the OWPSD bit equals 1 and the PSD pin blows a fuse in the
pack. If the open-wire test finds that the open wire has been
cleared, then OPEN bit is reset and other tests determine
whether conditions allow the power FETs to turn back on.
The open-wire test hardware has two limitations. First, it depends
on the CELLF indicator. If the Cell Balance Maximum Voltage
Delta (CBDU) value is set to high (FFFh for example), then the
device may never detect a CELLF condition. The second limitation
is that the open-wire test does not happen immediately. First, a
scan must detect a CELLF condition. CELLF detection happens in
a maximum of 32ms (Normal mode) or in a maximum of 256ms
(Doze mode). Once CELLF is detected, the open-wire test occurs
on the next scan, 32ms to 256ms later.
When an open-wire condition occurs and the “Open-Wire Power
Shutdown” (OWPSD) bit is equal to “0”, the ISL94203 turns off
all power FETs and the cell balance FETs, but does not set the
PSD output. While in this condition, the device continues to
operate normally in all other ways (i.e., the cells are scanned and
the current monitored. As time passes, the device drops into
lower power modes).
FN7626 Rev 5.00
February 17, 2016
Page 26 of 64
ISL94203
The current sense circuit has a gain x5, x50 or x500. The sense
amplifier allows a very wide range of currents to be monitored.
The gain settings allow a sense resistor in the range of 0.3mΩ to
5mΩ. A diagram of the current sense circuit is shown in
Figure 20.
Current and Voltage Monitoring
There are two main automatic processes in the ISL94203. The
first are the current monitor and overcurrent shutdown circuits.
The second are the voltage, temperature and current analog to
digital scan circuits.
There are two parts of the current sense circuit. The first part is a
digital current monitor circuit. This circuit allows the current to be
tracked by an external microcontroller or computer. The current
sense amplifier gain in this current measurement is set by the
[CG1:CG0] bits. The 14-bit offset adjusted ADC result of the
conversion of the voltage across the current sense resistor is
saved to RAM, as well is a 12-bit value that is used for threshold
comparisons. The offset adjustment is based on a “factory
calibration” value saved in EEPROM.
Current Monitor
The current monitor is an analog detection circuit that tracks the
charge and discharge current and current direction. The current
monitor circuit is on all the time, except in Sleep and
Power-Down modes.
The current monitor compares the voltage across the sense
resistor to several different thresholds. These are short-circuit
(discharge), overcurrent (discharge) and overcurrent (charge). If
the measured voltage exceeds the specified limit, for a specified
duration of time, the ISL94203 acts to protect the system, as
described in the following.
The digital readouts cover the input voltage ranges shown in
Table 2.
TABLE 2. MAXIMUM CURRENT MEASUREMENT RANGE
GAIN
SETTING
VOLTAGE RANGE
(mV)
CURRENT RANGE
(R = 1mΩ)
The current monitor also tracks the direction of the current. This
is a low level detection and indicates the presence of a charge or
discharge current. If either condition is detected, the ISL94203
sets an appropriate flag.
SENSE
5x
-250 to 250
-25 to 25
-250A to 250A
-25A to 25A
50x
500x
-2.5 to 2.5
-2.5A to 2.5A
Current Sense
The current sense element is on the high-side of the battery pack.
R
SENSE
CS2
CS1
500Ω
5kΩ
50kΩ
+
-
CHARGE
OVERCURRENT
DETECT
AO2:0 = 9H
VOLTAGE SCAN
PROGRAMMABLE
DETECTION TIME
COC
250kΩ
250kΩ
NOTE:
AGC SETS GAIN DURING
OVERCURRENT MONITORING.
CG BITS SELECT GAIN WHEN ADC
MEASURES CURRENT.
[OCCTB:OCC0]
[OCC2:OCC0]
GAIN SELECT
PROGRAMMABLE
THRESHOLDS
CG1:0
DISCHARGE
OVERCURRENT
DETECT
PROGRAMMABLE
DETECTION TIME
14-BIT ADC OUTPUT
14-BIT
DOC
AGC
RAM REGISTER
VALUE
[OCDTB:OCDT0]
[OCD2:OCD0]
ADDRESS: [ABh:AAh]
PROGRAMMABLE
THRESHOLDS
PACK CURRENT
12-BIT
14-BIT
ADC
+
-
POLARITY
CONTROL
+
RAM REGISTER
VALUE
ADDRESS: [8Fh:8Eh]
DISCHARGE
SHORT-CIRCUIT
DETECT
12
4
PROGRAMMABLE
DETECTION TIME
DSC
DIGITAL CAL EEPROM
[SCTB:SCT0]
[DSC2:DSC0]
CURRENT
DIRECTION
DETECT +
CHING
PROGRAMMABLE
THRESHOLDS
DCHING
AO3:AO0
VOLTAGE SELECT BITS
2ms FILTER
FIGURE 20. BLOCK DIAGRAM FOR OVERCURRENT DETECT AND CURRENT MONITORING
FN7626 Rev 5.00
February 17, 2016
Page 27 of 64
ISL94203
TABLE 5. DISCHARGE SHORT-CIRCUIT CURRENT THRESHOLD
VOLTAGES (Continued)
The second part is the analog current direction, overcurrent and
short-circuit detect mechanisms. This circuit is on all the time.
During the operation of the overcurrent detection circuit, the
sense amplifier gain is automatically controlled.
EQUIVALENT CURRENT (A)
DSC
SETTING
THRESHOLD
(mV)
0.3mΩ
213.3
0.5mΩ 1mΩ 2mΩ 5mΩ
For current direction detection, there is a 2ms digital delay for
getting into or out of either direction condition. This means that
charge current detection circuit needs to detect an uninterrupted
flow of current out of the pack for more than 2ms to indicate a
discharge condition. Then, the current detector needs to identify
that there is a charge current or no current for a continuous 2ms
to remove the discharge condition.
100
101
110
111
64
96
128
192
64
96
32
48
12.8
19.2
25.6
51.2
(Note 15)
128
256
(Note 15) (Note 15) 128
(Note 15) (Note 15) Note
64
128
NOTE:
15. These selections may not be reasonable due to sense resistor power
dissipation. Assumes short-circuit FET turn off in 10ms or less.
The overvoltage and short-circuit detection thresholds are
programmable using values in the EEPROM. The discharge
overcurrent thresholds are shown in Table 3. The charge
overcurrent thresholds are shown in Table 4. The discharge
short-circuit thresholds are shown in Table 5.
The Charge and Discharge overcurrent conditions and the
Discharge Short-circuit condition need to be continuous for a
period of time before an overcurrent condition is detected. These
times are set by individual 12-bit timers. The timers consist of a
10-bit timer value and a 2-bit scale value (see Table 6).
TABLE 3. DISCHARGE OVERCURRENT THRESHOLD VOLTAGES
EQUIVALENT CURRENT (A)
OCD
SETTING
THRESHOLD
(mV)
TABLE6. CHARGE/DISCHARGEOVERCURRENT/SHORT-CIRCUIT
DELAY TIMES
0.3mΩ
13.3
0.5mΩ
8
1mΩ
4
2mΩ 5mΩ
000
001
4
2
4
0.8
1.6
[OCCTB:A]
[OCDTB:A]
[SCTB:A]
[OCCT9:0]
[OCDT9:0]
[SCT9:0]
8
26.6
16
8
010
16
24
32
48
64
96
53.3
32
16
24
32
48
64
8
3.2
SCALE VALUE
DELAY (10-bit VALUE)
011
80
48
12
16
24
32
4.8
00
01
10
11
0 to 1024µs
0 to 1024ms
100
106.7
(Note 14)
64
6.4
101
96
9.6
0 to 1024s
110
(Note 14) (Note 14)
12.8
19.2
111
(Note 14) (Note 14) (Note 14) 48
0 to 1024 minutes
NOTE:
14. These selections may not be reasonable due to sense resistor power
dissipation.
Overcurrent and Short-Circuit Detection
The ISL94203 continually monitors current by mirroring the
current across a current sense resistor (between the CS1 and
CS2 pins) to a resistor to ground.
TABLE 4. CHARGE OVERCURRENT THRESHOLD VOLTAGES
EQUIVALENT CURRENT (A)
OCC
SETTING
THRESHOLD
(mV)
• A discharge overcurrent condition exists when the voltage
across the external sense resistor exceeds the discharge
overcurrent threshold, set by the discharge overcurrent
threshold bits [OCD2:OCD0], for an overcurrent time delay, set
by the discharge overcurrent time out bits [OCDTB:OCDT0].
This condition sets the DOC bit high. The LD_PRSNT bit is also
set high at this time. If the µCFET bit is 0, then the power FETs
turn off automatically. If the µCFET bit is 1, then the external
µC must control the power FETs.
0.3mΩ 0.5mΩ 1mΩ 2mΩ 5mΩ
000
001
010
011
100
101
110
111
1
2
3.3
6.7
2
1
2
0.5
1
0.2
0.4
0.8
1.2
1.6
2.4
3.2
4.8
4
4
13.3
20
8
4
2
6
12
16
24
32
48
6
3
8
26.6
40
8
4
12
16
24
12
16
24
6
• A charge overcurrent condition exists when the voltage across
the external sense resistor exceeds the charge overcurrent
threshold, set by the charge overcurrent threshold bits
[OCC2:OCC0], for an overcurrent time delay, set by the
discharge overcurrent time out bits [OCCTB:OCCT0]. This
condition sets the COC bit high. The CH_PRSNT bit is also set
high at this time. If the µCFET bit is 0, then the power FETs turn
off automatically. If the µCFET bit is 1, then the external µC
must control the power FETs.
53.3
80
8
12
TABLE 5. DISCHARGE SHORT-CIRCUIT CURRENT THRESHOLD
VOLTAGES
EQUIVALENT CURRENT (A)
DSC
SETTING
THRESHOLD
(mV)
0.3mΩ
53.3
80
0.5mΩ 1mΩ 2mΩ 5mΩ
000
001
010
011
16
24
32
48
32
48
64
96
16
24
32
48
8
3.2
4.8
6.4
9.6
12
16
24
• A discharge short-circuit condition exists when the voltage
across the external sense resistor exceeds the discharge
short-circuit threshold, set by the discharge short-circuit
threshold bits [SCD2:SCD0], for an overcurrent time delay, set
106.7
160
FN7626 Rev 5.00
February 17, 2016
Page 28 of 64
ISL94203
by the discharge short-circuit time out bits [SCDTB:SCDT0].
This condition sets the DSC bit high. The LD_PRSNT bit is also
set high at this time. The power FETs turn off automatically in a
short-circuit condition, regardless of the condition of the µCFET
bit.
LD_PRSNT = “0”, the µC sets the CLR_LERR bit to “1” (to clear the
error condition and reset the DOC or DSC bit) and sets the DFET
and CFET (or PCFET) bits to “1” to turn on the power FETs.
Overcurrent Response (Charge)
Once the ISL94203 enters the charge overcurrent protection
mode, the ISL94203 begins a charger monitor state. In the
charger monitor state, the ISL94203 periodically checks the
charger connection by turning on the CHMON output for 0ms to
15ms every 256ms. Program the use duration with the
[CPW3:CP0] bits in EEPROM.
Overcurrent and Short-Circuit Response
(Discharge)
Once the ISL94203 enters the discharge overcurrent protection or
short-circuit protection mode, the ISL94203 begins a load monitor
state. In the load monitor state, the ISL94203 waits three seconds
and then periodically checks the load by turning on the LDMON
output for 0 to 15ms every 256ms. Program the pulse duration
with the [LPW3:LPW0] bits in EEPROM.
When turned on, the recovery circuit checks the voltage on the
CHMON pin. With a charger present, the voltage on the CHMON
pin is high (>9V) and the CH_PRSNT bit remains set to “1”. When
the charger connection is removed, the voltage on the CHMON
pin falls below the CHMON threshold and the CH_PRSNT bit is
reset. When the charger has been released for a sufficiently long
period of time (two successive sample periods) the ISL94203
recognizes that the conditions are OK and clears the COC bit.
When turned on, the recovery circuit outputs a small current
(~60µA) to flow from the device and into the load. With a load
present, the voltage on the LDMON pin is low and the LD_PRSNT
bit remains set to “1”. When the load rises to a sufficiently high
resistance, the voltage on the LDMON pin rises above the LDMON
threshold and the LD_PRSNT bit is reset. When the load has been
released for a sufficiently long period of time (two successive load
sample periods) the ISL94203 recognizes that the conditions are
OK and resets the DOC or DSC bits.
If the µCFET bit is 0, the device automatically reenables the power
FETs by setting the DFET and CFET (or PCFET) bits to “1” (assuming
all other conditions are within normal ranges). If the µCFET bit is 1,
then the µC must turn on the power FETs.
If the µCFET bit is 0, then the device automatically re-enables the
power FETs by setting the DFET and CFET (or PCFET) bits to “1”
(assuming all other conditions are within normal ranges). If the
µCFET bit is 1, then the µC must turn on the power FETs.
An external microcontroller can override the automatic charger
monitoring of the device. It does this by taking control of the load
monitor circuit (set the µCCMON bit = “1”) and periodically
pulsing the CMON_EN bit. When the microcontroller detects that
CH_PRSNT = ”0”, the µC sets the CLR_CERR bit to “1” (to clear the
error condition and reset the COC bit) and sets the DFET and CFET
(or PCFET) bits to “1” to turn on the power FETs.
An external microcontroller can override the automatic load
monitoring of the device. It does this by taking control of the load
monitor circuit (set the µCLMON bit = “1”) and periodically
pulsing the LMON_EN bit. When the microcontroller detects that
OVERCURRENT
PROTECTION
NORMAL OPERATION MODE
NORMAL OPERATION MODE
MODE
SENSE
CURRENT
I
OCC
t
OCCT
CHARGER REMOVED
CHARGER STILL
CONNECTED
V
CHMON
WHEN µCFET = “0”
SAMPLE RATE SET BY ISL94203
CHMON PIN
WHEN µCFET = “1” AND µCCMON = “1”
SAMPLE RATE SET BY MICROCONTROLLER
CMON_EN
(FROM µC)
(Note 17)
COC BIT
(µCFET = “0”)
(Note 16)
COC BIT
(µCFET = “1”)
CFET
NOTES:
16. When µCFET = “1”, COC bit is reset when the CLR_CERR is set to “1”.
17. When µCFET = “0”, COC is reset by the ISL94203 when the condition is released
FIGURE 21. CHARGE OVERCURRENT PROTECTION MODE - EVENT DIAGRAM
FN7626 Rev 5.00
February 17, 2016
Page 29 of 64
ISL94203
within the watchdog time out period, then the microcontroller
control bits are all reset, the device turns off the power FETs and
the balance FETs and the INT output provides a 1µs pulse one
time per second.
Microcontroller Overcurrent FET Control
Protection
If any of the microcontroller override bits (µCSCAN, µCFET,
µCLMON, µCCMON or µCBAL) are set to “1” and the
microcontroller does not send a valid slave byte to the ISL94203
NORMAL OPERATION MODE
O.C. PROTECTION
NORMAL
SHORT
NORMAL
BATTERY
VOLTAGE
LOAD RELEASED
LOAD NOT RELEASED
3s
3s
WHEN µCFET = “0”
V
LDMON
SAMPLE RATE SET BY µC
LDMON PIN
WHEN µCFET = “1” AND µCLMON = “1”
SAMPLE RATE IS SET BY µC.
LMON_EN
(FROM µC)
NO CURRENT
FOR 2x IDLE/MODE MODE TIME +
SLEEP MODE TIME
V
DSC
V
DSC
V
OCD
V
V
OCD
SS
SLEEP
V
CS
t
t
SC
OCDT
DFET
Note 18
Note 21
Note 20
Note 20
Note 21
Note 20
Note 20
CFET
Note 18
PCFET
Note 18
Note 19
DOC
(STAND ALONE)
DSC
Note 19
DOC
(EXTERNAL CONTROL)
LD_PRSNT
FIGURE 22. DISCHARGE OVERCURRENT PROTECTION MODE - EVENT DIAGRAM
NOTES:
18. When µCFET = “1”, CFET, DFET and PCFET are controlled by external µC.
When µCFET = “0”, CFET, DFET and PCFET are controlled automatically by the ISL94203.
19. When µCFET = “1”, DOC and DSC bits are reset by setting the CLR_LERR bit.
When µCFET = “0”, DOC and DSC are reset by the ISL94203 when the condition is released.
20. PCFET turns on if any cell voltage is less than LVCHG threshold. Otherwise CFET turns on.
21. DFET does not turn on if any cell is less than the UV threshold, unless the DFODUV bit is set.
FN7626 Rev 5.00
February 17, 2016
Page 30 of 64
ISL94203
After each measurement scan, the ISL94203 performs an offset
adjustment and stores the values in RAM. After the values are
stored, the state machine executes compare operations that
determine if the pack is operating within limits. See Figure 23 for
details on the scan sequence.
Voltage, Temperature and Current Scan
The voltage scan consists of the monitoring of the digital
representation of the current, cell voltages, temperatures, pack
voltage and regulator voltage. This scan occurs once every 32ms,
256ms or 512ms (depending on the mode of operation, see
Figure 23). The temperature, pack voltage and regulator voltage
are scanned only every 4th scan. The open wire is scanned every
32nd scan as long as the CELLF condition exists.
During manufacture, Intersil provides calibration values in the
EEPROM for each cell voltage reading. When there is a new
conversion for a particular voltage, the calibration is applied to
the conversion.
CURRENT/VOLTAGE MONITOR (EVERY CYCLE)
ISL94203 CURRENT MONITORING
CURRENT SELECT/SETTLING TIME
ADC CONVERT
~500µs
ISL94203 CELL VOLTAGE MONITORING
TURN ON ADC MUX SEL SETTLING TIME ADC CONVERT
OV/UV/UVLO DETECT/FET UPDATE/ADD
OFFSETS/CB CALCULATIONS/OPEN WIRE DETECT
~100µs
OPEN WIRE
CELL1
CELL1
CELL2
CELL3
CELL7
~1.3 ms
CELL8
CURRENT
LOW POWER STATE
INT_SCAN BIT
32ms
256ms
512ms
CURRENT/VOLTAGE/TEMPERATURE MONITOR (EVERY 4TH CYCLE)
ISL94203 TEMPERATURE MONITORING
MUX SEL SETTLING TIME ADC CONVERT
ISL94203 PACK VOLTAGE MONITORING
MUX SEL SETTLING TIME ADC CONVERT
OV/UV/UVLO DETECT/FET UPDATE/ADD
OFFSETS/CB CALCULATIONS/OPEN WIRE DETECT
TEMPERATURE CALCULATIONS
~50µs
V
/16
OPEN WIRE
CELL1
CELL2
CURRENT
BATT
RGO/2
xT1
xT2
iT
LOW POWER
CELL1
INT_SCAN BIT
~1.7 ms
32ms
256ms
512ms
FIGURE 23. CELL VOLTAGE, CURRENT, TEMPERATURE SCANNING
NOTES:
22. The open-wire test performed every 32 voltage scans, if CELLF = 1, just prior to the scan.
23. FETs turn off immediately if there is an error, but they do not turn on until the end of the voltage scan (at “FET update” if everything else is OK). An
exception to this is when a device wakes up when connected to a load. In this case, the FETs turn on immediately on wake-up, then a scan begins.
24. The voltage scan can be turned off by an external microcontroller by setting the µCSCAN bit. This bit is monitored by the watchdog timer, so if an
external microcontroller stops communicating with the ISL94203 for more than the WDT period, this bit is automatically reset and the scan resumes.
FN7626 Rev 5.00
February 17, 2016
Page 31 of 64
ISL94203
or by turning off the FETs and setting the UVLO bit
(UVLOPD = “0”).
Cell Voltage Monitoring
The circuit that monitors the input cell voltage multiplies the cell
voltage by 3/8. The ADC converts this voltage to a digital value,
using a 1.8V internal reference. The ADC produces a calibrated
14-bit value, but only 12 bits are stored in the cell registers (see
Figure 24.)
When the UVLOPD bit is set to “1” (indicating that the ISL94203
should power down during a UVLO condition) and the µCFET bit is
set to “1” (indicating that the µC is in control of the FETs), the
automatic UVLO control forces a power-down condition,
overriding the µC FET control.
In manufacturing, each cell voltage is calibrated at 3.6V per cell
and at +25°C. This calibrated value is used for all subsequent
voltage threshold comparisons.
The UVLO and OVLO detection both have delays of 5 sample
cycles (typically 160ms) to prevent noise generated entry into the
mode.
The ISL94203 has two different overvoltage and undervoltage
level comparisons, OVLO/UVLO and OV/UV. While both use the
ADC converter output values and a digital comparator, the
responses are different. The OVLO and UVLO levels are meant to
be secondary thresholds above and below the OV and UV
thresholds.
The OVLO and UVLO values are each set by 12-bit values in
EEPROM.
The OVLO has a recovery threshold of OVR and UVLO has a
recovery threshold of UVR (if the response overrides have been
set). If the response overrides are not set, then the recovery
thresholds are usually irrelevant; for example, when the UVLO
forces the device into a power down condition or the OVLO
condition caused a PSD controlled fuse to blow.
UVLO AND OVLO
OVLO and UVLO, because they provide a secondary safety
condition, can cause the pack to shut down, either permanently,
as is the case of an OVLO when the PSD pin connects to an
external fuse; or severely, as is the case of an UVLO when the
device powers down and requires connection to a charger to
recover.
UV, OV AND SLEEP
UV, OV and SLP thresholds are set by individual 12-bit values.
UV and OV recovery thresholds are set by individual 12-bit values.
The OVLO condition can be overridden by setting the OVLO
threshold to FFFH or by an external µC setting the µCSCAN bit to
override the internal automatic scan, then turning on the CFET.
However, if the µC takes permanent control of the scan, the µC
needs to take over the scan for all cells and all control functions,
including comparisons of the cell voltage to OV and UV
thresholds, managing time delays and controlling all cell balance
functions.
The voltage protection scan occurs once every 32ms in normal
operation. If there has been no activity (no charge or discharge
current) detected in a programmable period of 1 to 16 minutes,
then the scan occurs every 256ms (Idle mode). If no charge or
discharge condition has been detected in Idle mode for the
programmable period, then the scan occurs every 512ms.
If an overvoltage, undervoltage or sleep condition is detected and
is pending, the scan rate remains unchanged. It can take longer
to detect the fault condition in Idle or Doze modes. The scan rate
is determined by the mode of operation and the mode of
operation is determined solely by the time since pack
charge/discharge current was detected.
The UVLO response can be overridden by setting the UVLO
threshold to 0V. The device can respond to the UVLO condition by
entering the Power-Down mode (set UVLOPD in EEPROM to “1”)
VC8
VOLTAGE
BUFFER
14-BIT ADC OUTPUT
14-BIT VALUE
VC7
1.8V
RAM REGISTER
ADDRESS: [ABh:AAh]
CELL VOLTAGE
12-BIT VALUE
INPUT
MUX/
LEVEL
SHIFTER
14-BIT
ADC
S
RAM REGISTER
ADDRESS: [91h:90h] + 2(n-1);
(n = CELL NUMBER)
(x 3/8)
VC1
12
VSS
VOLTAGE
BUFFER
VC0
DIGITAL CAL EEPROM
TRIM ADDRESS
[AO3:AO0]
VOLTAGE SELECT BITS
FIGURE 24. BLOCK DIAGRAM OF CELL VOLTAGE CAPTURE
FN7626 Rev 5.00
February 17, 2016
Page 32 of 64
ISL94203
During a scan, each cell is monitored for overvoltage,
undervoltage and sleep voltage. The voltage will also be
converted to an ADC value and be stored in memory.
the device sets an OV flag. Then (if µCFET = 0), the ISL94203
turns the charge FET OFF, by setting the CFET bit to “0”. Once the
OV flag is set the pack has entered Overcharge Protection mode.
The status of the discharge FET remains unaffected.
If, during the scan, a voltage is outside the set limit, then a timer
starts. There is one timer for all of the cells. If the condition
remains on any cell or combination of cells for the duration of the
time period, an error condition exists. This sets the appropriate
flag and notifies the protection circuitry to take action (if
automatic action is enabled).
The charge FET remains off until the voltage on the overcharged
cell drops back below a recovery level, V
, for a recovery time
OVR
period, t
OVR
. The t
OVR
time equals the t time.
OV
Note: The detection timer and recovery timer are asynchronous
to the voltage threshold. As a result, a setting of 1s can result in a
delay time of 1s to 2s, depending on when the OV/OVR is
detected. For a setting of 1000ms, the detection time will be
within 1ms.
The time out delays for OV, UV and Sleep are each 12-bit values
stored in EEPROM (see Table 7).
TABLE 7. OV, UV, SLEEP DELAY TIMES
The device further continues to monitor the battery cell voltages
and is released from overcharge protection mode when
SCALE VALUE
DELAY (10-BIT VALUE)
0 to 1024µs
00
01
10
11
[V
< V for more than the overcharge release time,
Cn - VC(n-1)]
OVR
for all cells.
0 to 1024ms
When the device is released from overcharge protection mode,
the charge FET is automatically switched ON (if µCFET = 0). When
the device returns from Overcharge Protection mode, the status
of the discharge FET remains unaffected.
0 to 1024s
0 to 1024min
The control logic for overvoltage, undervoltage and sleep
conditions is shown in Table 7 and Figures 25 and 26.
During charge, if the voltage on any cell exceeds an End Of
Charge threshold (EOCS) then an EOCHG bit is set and the EOC
output is pulled low. The EOCHG bit and the EOC output resume
normal conditions when the voltage on all cells drops back below
the [EOCS - 117mV] threshold.
Overvoltage Detection/Response
The device needs to monitor the voltage on each battery cell
(V ). If for any cell, [V
> V for a time exceeding t
,
OV
Cn Cn - VC(n-1)]
OV
OVERVOLTAGE LOCK-OUT
NORMAL
NORMAL OPERATION MODE
OVERCHARGE
PROTECTION MODE
OPERATION
MODE
PROTECTION MODE
V
OVLO
V
OV
VEOC
t
OV
V
OVR
VCn
t
OVR
CFLG RESET
DISCHARGE
CHARGE
PACK
CURRENT
DFLG RESET
DFLG SET
DFET
CFET
CFODOV FLAG = “1” ALLOWS
CFET TO TURN ON DURING OV, IF DISCHARGING
EOC PIN
EOCHG BIT
OV BIT
SD PIN
PSD PIN
OVLO BIT
FIGURE 25. OVERVOLTAGE PROTECTION MODE-EVENT DIAGRAM
FN7626 Rev 5.00
February 17, 2016
Page 33 of 64
ISL94203
VC
V
UVR
V
UV
LVCH
V
V
SL
t
+3s
t
+3s
UV
UV
V
UVLO
t
t
UV
UV
t
SL
IF CHARGE VOLTAGE
CONNECTED
CHARGE
I
PACK
DISCHARGE
DISCHARGE
MICROCONTROLLER ONLY.
SAMPLING FOR LOAD RELEASE
(µCLMON BIT = “1”)
(µCLMON PULSES)
(LOOKING FOR TOOL TRIGGER RELEASE)
LMON_EN BIT
(FROM µC)
LOAD RELEASED
LDMON PIN
V
LDMON
(STARTS LOOKING FOR CHARGER/LOAD CONNECT)
CMON_EN BIT
CHMON PIN
V
WAKE UP
WKUPC
WKUPL
CHARGE
DFET REMAINS SET
IF UVLOPD = “0”
AND µCFET = 1
CONNECT
V
LD_PRSNT BIT
DFET BIT
DFET ON IF CHARGING
AND DFODUV BIT IS SET
DFET ON IF CHARGING
AND DFODUV BIT IS SET
CFET BIT
IF PCFETE SET, PCFET
PCFET BIT
TURNS ON HERE, NOT CFT
IN_SLP BIT
UVLO BIT
OVERDISCHARGE
OVERDISCHARGE
UVLO SET IF UVLOPD = “0”.
If UVLOPD = “1” AND
µCFET = 0 OR 1, DEVICE
POWERS DOWN
SLEEP
PROTECTION MODE
PROTECTION MODE
UV BIT
(µCFET =0”)
UV BIT
(µCFET =1”)
RESET WHEN MICROCONTROLLER WRITES CLR_LERR BIT = “1”
FIGURE 26. UNDERVOLTAGE PROTECTION MODE-EVENT DIAGRAM
There is also an overvoltage lockout. When this level is reached,
an OVLO bit is set, the PSD output is set and the charge FET or
precharge FET is immediately turned off (by setting the CFET or
PCFET bit to “0”). The PSD output can be used to blow a fuse to
protect the cells in the pack.
Undervoltage Detection/Response
If V < V , for a time exceeding t , the cells are said to be in
Cn UV UVT
a over discharge (undervoltage) state. In this condition, the
ISL94203 sets a UV bit. If the µCFET bit is set to “0”, the
ISL94203 also switches the discharge FET OFF (by setting the
DFET bit = “0”).
If, during an OV condition, the µCFET bit is set to “1”, the
microcontroller must control both turn off and turn on of the
charge and precharge power FETs. This does not apply to the
OVLO condition.
While any cell voltage is less than a low voltage charge threshold
and if the PCFETE bit is set, the PCFET output is turned on instead
of the CFET output. This enables a precharge condition to limit
the charge current to undervoltage cells.
The device includes an option to turn the charge FET back on in
an overvoltage condition, if there is discharge current flowing out
of the pack. This option is set by the CFODOV (CFET ON During
Overvoltage) Flag stored in EEPROM. Then, if the discharge
current stops and there is still an overcharge condition on the
cell, the device again disables the charge FET.
From the undervoltage mode, if the cells recover to above a V
UVR
plus three seconds, the ISL94203
level for a time exceeding t
UVT
pulses the LDMON output once every 256ms and looks for the
absence of a load. The pulses are of programmable duration
(0ms to 15ms) using the [LPW3:LPW0] bits. During the pulse
period, a small current (~60µA) is output into the load. If there is
FN7626 Rev 5.00
February 17, 2016
Page 34 of 64
ISL94203
no load, then the LDMON voltage will be higher than the recovery
threshold of 0.6V. When the load has been removed and the cells
are above the undervoltage recovery level, the ISL94203 clears
the UV bit and (if µCFET = 0) turns on the discharge FET and
resumes normal operation.
Figure 27A. A TGain bit = 1 and sets the gain to 1x (full scale
input voltage = 1.8V). See Figure 27B.
The default temperature gain setting is x2, so the temperature
monitoring circuit of Figure 27A is preferred. This configuration
has other advantages. The temperature response is more linear
and covers a wider temperature range before nearing the limits
of the ADC reading.
Note: The t detection timer and t
UV UVR
recovery timer are
asynchronous to the voltage threshold. As a result, a setting of 1s
can result in a delay time of 1s to 2s (and a recovery time of 3s to
4s), depending on when the UV/UVR is detected. For a setting of
1000ms, the detection time will be within 1ms.
The internal temperature reading converts from voltage to
temperature using Equations 1 and 2:
intTempmV 1000
----------------------------------------------------------
TGain = 1
– 273.15 = ICTempC
(EQ. 1)
If any of the cells drop below a sleep threshold (VCn < V ) for a
SLP
0.92635
period of time (t ), the device sets the Sleep bit and (if µCFET =
SLT
0) the ISL94203 turns off both FETs (DFET and CFET = “0”) and
puts the pack into a Sleep mode by setting the Sleep bit to “1”. If
the µCFET bit is set, the device does not go to sleep.
intTempmV 1000
----------------------------------------------------------
TGain = 0
– 273.15 = ICTempC
(EQ. 2)
1.8527
There is also an undervoltage lockout condition. This is detected
by comparing the cell voltages to a programmable UVLO
threshold. When any cell voltage drops below the UVLO threshold
and remains below the threshold for 5 voltage scan periods
(~160ms), a UVLO bit is set and the SD output pin goes active. If
UVLOPD = 0 and µCFET = 0, the DFET is also turned off. If
UVLOPD = 1, then the ISL94203 goes into a power-down state.
If the temperature of the IC (Internal Temp) goes above a
programmed over-temperature threshold, then the ISL94203 sets
an over-temp flag (IOT), prevents cell balancing and turns off the
FETs.
OVER-TEMPERATURE
If the temperature of either of the external temperature sensors
(xT1 or xT2), as determined by an external resistor and
thermistor, goes below any of the thresholds (charge, discharge
and cell balance as set by internal EEPROM values), indicating an
over-temperature condition, the ISL94203 sets the
corresponding over-temp flag.
If the µCFET bit is set to “1”, the microcontroller must both turn
off and turn on the discharge power FETs and control the sleep
and power-down conditions.
The device includes an option to turn the discharge FET back on
in an undervoltage condition, if there is a charge current flowing
into the pack. This option is set by the DFODUV (DFET ON During
Undervoltage) Flag stored in EEPROM. Then, if the charge current
stops and there is still an undervoltage condition on the cell, the
device again disables the discharge FET.
If the automatic responses are enabled (µCFET = 0), the Charge
Over-Temperature (COT) or Discharge Over-Temperature (DOT)
flag is set and the corresponding charge or discharge FET is
turned off. If the Cell Balance Over-Temperature (CBOT) flag is
set, the device turns off the balancing outputs and prevents cell
balancing while the condition exists.
Temperature Monitoring/Response
If the automatic responses are disabled (µCFET = 1) then the
ISL94203 only sets the flags and an external microcontroller
responds to the condition.
As part of the normal voltage scan, the ISL94203 monitors both
the temperature of the device and the temperature of two
external temperature sensors. External temperature 2 can be
used to monitor the temperature of the FETs, instead of the cells,
by setting the xT2M bit to “1”.
An exception to the above occurs if the xT2 sensor is configured
as a FET temperature indicator (XT2M = “1”). In this case, the xT2
is not compared to the cell balance temperature thresholds, it is
used only for power FET control.
The temperature voltages have two gain settings (the same gain
for all temperature inputs). For external temperatures, a TGain
bit = 0, sets the gain to 2x (full scale input voltage = 0.9V), see
TEMPO PIN
TEMPO PIN
22kΩ
22kΩ
82.5kΩ
82.5kΩ
xT1 PIN
xT2 PIN
xT1 PIN
xT2 PIN
+80°C = 0.050V
+80°C = 0.153V
+50°C = 0.120V
+25°C = 0.270V
0°C = 0.620V
+50°C = 0.295V
+25°C = 0.463V
0°C = 0.710V
10kΩ
10kΩ
THERMISTORS: 10k,
MuRata XH103F
-40°C = 1.758V
-40°C = 0.755V
FIGURE 27A. T
= 0 (GAIN = 2)
FIGURE 27B. T
= 1 (GAIN = 1)
GAIN
GAIN
FIGURE 27. EXTERNAL TEMPERATURE CIRCUITS
FN7626 Rev 5.00
February 17, 2016
Page 35 of 64
ALLOW CFET TO
TURN ON
CHARGE SHUTDOWN
TURN OFF CFET
DISCHARGE SHUTDOWN
TURN OFF DFET
BALANCE SHUTDOWN
TURN OFF BALANCING
ALLOW DFET TO
TURN ON
BALANCE PERMITTED
µCFET = 0
µCFET = 0
µCFET = 0
µCFET = 1
µCFET = 1
µCFET = 1
CELL BALANCE
OVER-TEMP OK
SET CBOT BIT = 0
DISCHARGE
OVER-TEMP OK
SET DOT BIT = 0
CHARGE
OVER-TEMP OK
SET COT BIT = 0
CHARGE OVER-TEMP
SET COT BIT
DISCHARGE OVER-TEMP
CELL BALANCE OVER-TEMP
SET DOT BIT
SET CBOT BIT
XT2M = 0
XT2M = 0
xT2 OTR
xT2<DOTS or
xT1<DOTS
xT1<CBOTS
xT1>CBOTR
xT2 OT
xT2<COTS or
xT1<COTS
XT2M = 1
XT2M = 1
xT2>DOTR or
xT1>DOTR
xT2>COTR or
xT1>COTR
xT2<CBOTS
xT2>CBOTR
SAMPLE MODE
xT2>CBUTS
xT2<CBUTR
xT2>CUTS OR
xT1>CUTS
xT2<DUTR OR
xT1<DUTR
xT2<CUTR OR
xT1<CUTR
XT2M = 1
xT2 UT
XT2M = 0
xT2>DUTS OR
xT1>DUTS
XT2M = 1
xT2 UTR
XT2M = 0
xT1>CBUTS
xT1<CBUTR
DISCHARGE
UNDER-TEMP OK
SET DUT BI T= 0
CHARGE
UNDER-TEMP OK
SET CUT BIT = 0
DISCHARGE
CELL BALANCE
UNDER-TEMP OK
SET CBUT BIT = 0
CELL BALANCE
UNDER-TEMP
SET CBUT BIT = 1
CHARGE UNDER TEMP
SET CUT BIT = 1
UNDER-TEMP
SET DUT BIT = 1
µCFET = 1
µCFET = 1
µCFET = 1
µCFET = 0
µCFET = 0
µCFET = 0
CHARGE SHUTDOWN
TURN OFF CFET
DISCHARGE SHUTDOWN
TURN OFF DFET
BALANCE SHUT DOWN
TURN OFF BALANCING
BALANCE
PERMITED
ALLOW CFET TO
TURN ON
ALLOW DFET TO
TURN ON
FIGURE 28. TEMPERATURE MANAGEMENT STATE MACHINE
ISL94203
UNDER-TEMPERATURE
TABLE 8. µC CONTROLLED MEASUREMENT OF INDIVIDUAL VOLTAGES
TIMEAT400kHz TIME
I C CLK (ea.) (CUMULATIVE)
If the temperature of either of the external temperature sensors
(xT1 or xT2), as determined by an external resistor and
thermistor, goes above any of the thresholds (charge, discharge
and cell balance as set by internal EEPROM values), indicating an
under-temperature condition, the ISL94203 sets the
corresponding under-temperature flag.
2
NUMBER
2
STEP
OPERATION
I C CYCLES
(µs)
72.5
72.5
(µs)
72.5
145
1
2
Set µCSCAN bit
29
29
Set voltage and
start ADC
If the xT1 automatic responses are enabled (µCFET = 0), then the
Charge Under-Temperature (CUT) or Discharge
3
Wait for ADC
complete
N/A
110
255
Under-Temperature (DUT) flag is set the corresponding charge or
discharge FET is turned off. If the Cell Balance
Under-Temperature (CBUT) flag is set, the device turns off cell
balancing outputs and prevents cell balancing.
4
5
6
Read register AB
Read register AA
Clear µCSCAN bit
29
29
29
72.5
72.5
100
327.5
410
472.5
If the xT2 automatic responses are disabled (µCFET = 1) then the
ISL94203 only sets the flags and an external microcontroller
responds to the condition.
To sample more than one time (for averaging) repeat steps 2
through 5 as many times as desired. However, if this is a
continuous operation, care must be taken to monitor other pack
functions or to pause long enough for the ISL94203 internal
operations to collect data to control the pack. A burst of five
measurements takes about 1.8ms.
An exception to the above occurs if the xT2 sensor is configured
as a FET temperature indicator (XT2M = “1”). In this case, the xT2
is not compared to the cell balance temperature thresholds. It is
used only for power FET control).
Voltage Conversions
To convert from the digital value stored in the register to a “real
world” voltage, the following conversion equations should be
used.
For both xT1 and xT2, when the temperature drops back within a
normal operating range, the over- or under-temperature
condition is reset.
Microcontroller Read of Voltages
The term “HEXvalue ” means the Binary to Decimal conversion
10
of the register value.
An external microcontroller can read the value of any of the
internally monitored voltages independently of the normal
voltage scan. To do this requires that the µC first set the µCSCAN
bit. This stops the internal scan and starts the watchdog timer. If
the µC maintains this state, then communication must continue
and the µC must manage all voltage and current pack control
operations as well as implement the cell balance algorithms.
However, if the µCSCAN bit remains set for a short period of time,
the device continues to monitor voltages and control the pack
operation.
CELL VOLTAGES
HEXvalue 1.8 8
10
(EQ. 3)
-----------------------------------------------------------
Cell Voltage =
4095 3
The cell voltage conversion equation is also used to set the
voltage thresholds.
PACK CURRENT
Once the µCSCAN bit is set, the external µC writes to register 85H
to select the desired voltage and to start the ADC conversion (set
the ADCSTRT bit to 1 to start an ADC conversion). Once the
conversion is complete, the results are read from the ADC
registers [ADCD:ADC0]. The result is a 14-bit value. The ADC
conversion takes about 100µs or the µC can poll the I C link
waiting for an ACK to indicate that the ADC conversion is
complete.
HEXvalue 1.8
10
(EQ. 4)
---------------------------------------------------------------
Pack Current =
4095 Gain SenseR
2
Gain is the gain setting in register 85H, set by the [CG1:CG0] bits.
SenseR is the sense resistor value in Ohms.
If the µCSCAN bit is set when the ISL94203 internal scan is
scheduled, then the internal scan pauses until the µCSCAN bit is
cleared and the internal scan occurs immediately.
This pack current reading is valid only when the current direction
indicators show that there is a charge or discharge current. If the
current is too low for the indicators to show current flowing, then
use the 14-bit value to estimate the current. See “14-bit Register”
on page 38.
Reading an ADC value from the µC requires the following
sequence (and time) to complete:
TEMPERATURE
HEXvalue 1.8
10
(EQ. 5)
--------------------------------------------------
Temperature =
4095
Equation 5 converts the register value to a voltage, but the
temperature then is converted to a temperature depending on
the external arrangement of thermistor and resistors. See
“Temperature Monitoring/Response” on page 35.
FN7626 Rev 5.00
February 17, 2016
Page 37 of 64
ISL94203
• If there is a sleep condition, the device turns the FETs off. On
wake up, the microcontroller is responsible for turning on the
FETs.
14-BIT REGISTER
If HEXvalue is greater than or equal to 8191, then:
10
The microcontroller can also control the FETs by setting the
µCSCAN bit. However, this also stops the scan, requiring the
microcontroller to manage the scan, voltage comparisons, FET
control and cell balance. While the µCSCAN bit is set to “1”, the
only operations controlled by the device are:
HEXvalue – 16384 1.8
(EQ. 6)
(EQ. 7)
10
14-bit value =
-----------------------------------------------------------------------------
8191
If HEXvalue is less than 8191, thenL
10
• Discharge short-circuit FET control. The external µC cannot
override the turn off of the FETs during the short-circuit.
HEXvalue 1.8
10
14-bit value =
--------------------------------------------------
8191
• FETSOFF external control. The FETSOFF pin has priority on
control of the FETs, even when the microcontroller is managing
the scan.
Once the voltage value is obtained, if the measurement is a cell
voltage, then the value should be multiplied by 8/3. A
temperature value is used “as-is”, but the voltage value is
converted to temperature by including the external temperature
circuits into the conversion.
• In all other cases, the microcontroller must manage the FET
control, because it is also managing the voltage scan and all
comparisons.
Cell Balance
To determine pack current from this 14-bit value requires the
following computations.
At the same rate as the scan of the cell voltages, if cell balancing
is on, the system checks for proper cell balance conditions. The
ISL94203 prevents cell balancing if proper temperature, current
and voltage conditions are not met. The cells only balance during
a CBON time period. When the CBOFF timer is running, the cell
balance is off. Three additional bits determine whether the
balancing happens only during charge, only during discharge,
during both charge and discharge, during the end of charge
condition or not at any time.
First, if both current direction flags show zero current, then the
external controller must apply an offset. Measure the 14-bit
voltage when there is a pack current of 0. Then subtract this
offset from the 14-bit current sense measurement value and
take the absolute value of the result. If either of the current
direction flags indicate a current, then do not subtract the offset
value, but use the 14-bit value directly. In either case, divide the
14-bit voltage value by the current sense gain and the current
sense resistor to arrive at the pack current.
• The cell balance circuit depends on the 14-bit ADC converter
built into the device and the results of the cell voltage scan
(after calibration).
Microcontroller FET Control
The external microcontroller can override the device control of the
FETs. With the µCFET bit set to “1”, the external microcontroller can
turn the FETs on or off under all conditions except the following:
• The ADC converter loads a set of registers with each cell
voltage during every cell voltage measurement.
• At the end of the cell voltage measurement scan, the
ISL94203 updates the minimum (CELMIN) and maximum
(CELMAX) cell voltages.
• If there is a discharge short-circuit condition, the device turns
the FETs off. The external microcontroller is responsible for
turning the FETs back on once the short-circuit condition
clears.
• After calculating the CELMIN and CELMAX values, all of the cell
voltages are compared with the CELMIN value. When any of
the cells exceed CELMIN by CBDL (the minimum CB delta
voltage), a flag is set in RAM indicating that the cell needs
balancing (this is the CBnON bit).
• If there is an internal over-temperature condition, the device turns
the FETs off. The external microcontroller is responsible for
turning the FETs back on once the temperature returns to within
normal operating limits.
• If any of the cells exceed the lowest cell by CBDU (maximum
CB delta voltage) then a flag is set indicating that a Cell
voltage failure occurred (CELLF).
• If there is an overvoltage lockout condition, the device turns the
charge or precharge FETs off. The external microcontroller is
responsible for turning the FETs back on, once the OVLO condition
clears. This assumes that the PSD output has not blown a fuse to
disable the pack.
• When the CELLF flag indicates that there is too great a cell to
cell differential, the balancing is turned off.
• If CELMAX is below CBMIN (all the cell voltages are too low for
balancing) then the CBUV bit is set and there will be no cell
balancing. Cell balance does not start again until the CBMIN
value rises above (CBMIN + 117mV). When this happens, the
ISL94203 clears the CBUV bit.
• If there is an open-wire detection, the device turns the FETs off.
The external microcontroller is responsible for turning the FET
back on. This assumes that the open wire did not cause the PSD
output to blow a fuse to disable the pack.
• If the FETSOFF input is HIGH, the FETs turn off and remain off.
The external µC is responsible for turning the FETs on once the
FETSOFF condition clears.
FN7626 Rev 5.00
February 17, 2016
Page 38 of 64
ISL94203
• If the CELMIN voltage is greater than the CBMAX voltage (all the
cell voltages are too high for balancing) then the CBOV bit is set
and there will be no cell balancing. Cell balancing does not start
again until the CBMAX value drops below (CBMAX - 117mV).
When this happens, the ISL94203 clears the CBOV bit.
TABLE 9. CELL BALANCE TRUTH TABLE (SEE Figure 29)
CB_EOC
EOC
PIN
BIT
CBDC
0
CHING
0
CBDD
0
DCHING
0
ENABLE
0
0
1
x
1
• A register in EEPROM (CELLS) identifies the number of cells
that are supposed to be present so only the cells present are
used for the cell balance operation. Note: This is also used in
the cell voltage scan and open-wire detect operation.
0
1
x
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x
0
0
1
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
x
1
• There are no limits to the number of cells that can be balanced
at any one time, because the balancing is done external to the
device.
0
1
x
1
0
1
x
1
• The cell balance block updates at the start of the cell balance
ON period to determine if balancing is needed and that the
right cells are being balanced. The cells selected at this time
will be balanced for the duration of the cell balance period.
0
1
x
1
0
1
x
1
• The cell balance is disabled if any external temperature is out
of a programmed range set by CBUTS (cell balance under
temperature) and CBOTS (cell balance over-temperature).
0
1
x
1
• The cell balance operation can be disabled by setting the Cell
Balance During Charge (CBDC), the Cell Balance During
Discharge (CBDD) and the Cell Balance During End-of-Charge
(CB_EOC) bits to zero. See Table 9 on page 39.
0
1
x
1
0
1
x
1
0
1
x
1
• Cell balancing turns off when set to balance in the charge
mode and there is no charging current detected (see CB_EOC
exception below).
0
1
x
1
• Cell balancing turns off when set to balance in the discharge
mode and there is no discharge current detected (see CB_EOC
exception below).
0
1
x
1
0
1
x
1
• If cell balancing is set to operate during both charge and
discharge, then ISL94203 balances while there is charge
current or discharge current, but does not balance when no
current flow is detected (all other limiting factors continue to
apply). See CB_EOC exception in the following.
0
1
x
1
0
1
x
1
• The CB_EOC bit provides an exception to the cell balance
current direction limit. When the CB_EOC bit is set, balancing
occurs while an end of charge condition exists (EOC bit = 1),
regardless of current flow. This allows the ISL94203 to “drain”
high voltage cells when the charge is complete. This speeds
the balancing of the pack, especially when there is a large
capacity differential between cells. Once the end of charge
condition clears, the cell balance operation returns to normal
programming.
1
0
TABLE 10. CBON AND CBOFF TIMES
TIME (10-BIT VALUE)
0 to 1024µs
SCALE VALUE
00
01
10
11
0 to 1024ms
0 to 1024s
• Balance is disabled by asserting the FETSOFF external pin.
0 to 1024min
• The cell balance outputs are on only while the cell balance on
timer is counting down. This is a 12-bit timer. The cell balance
outputs are all off while the cell balance off timer is counting
down. This is also a 12-bit timer. The timer values are set as in
Table 10.
Cell Balance in Cascade Mode
When two ISL94203 devices are cascaded, both devices should
have the CASC bit set to “1”.
When cascaded, the lower of the two devices will have an ADDR
that is HIGH or set to “1”. The device with ADDR = 1, being on the
bottom of the stack, does not monitor the current or drive the
power FETs. Instead, they are turned off to save power
consumption.
FN7626 Rev 5.00
February 17, 2016
Page 39 of 64
ISL94203
CELL8 VOLTAGE - CELLMIN >
CBMINDV OR [CB8ON]
CB8 DRIVER
CB7 DRIVER
CB6 DRIVER
CB5 DRIVER
CB4 DRIVER
CB3 DRIVER
CB2 DRIVER
CB1 DRIVER
CELL7 VOLTAGE - CELLMIN >
CBMINDV OR [CB7ON]
CB OFF TIMER IS COUNTING
CELL6 VOLTAGE - CELLMIN >
CBMINDV OR [CB6ON]
CBOV BIT
CBUV BIT
CBERR
CBOT BIT
CBUT BIT
OPEN BIT
CELLF BIT
CELL5 VOLTAGE - CELLMIN >
CBMINDV OR [CB5ON]
ENABLE
CASC
CELL4 VOLTAGE - CELLMIN >
CBMINDV OR [CB4ON]
SD PIN
FETSOFF PIN
CELL3 VOLTAGE - CELLMIN >
CBMINDV OR [CB3ON]
1
3
EOC PIN
CB_EOC
2
7
CELL2 VOLTAGE - CELLMIN >
CBMINDV OR [CB2ON]
CHING BIT
CBDD
4
CELL1 VOLTAGE - CELLMIN >
CBMINDV OR [CB1ON]
CBDC BIT
6
5
DCHING BIT
FIGURE 29. CELL BALANCE OPERATION
When CASC = 1, the ISL94203 does not use the current
Cell Balance FET Drive
detection as part of the control algorithm for cell balancing. If all
other conditions are within limits, balancing proceeds without a
detection of current. As such, balancing may happen all of the
time, requiring the use of an external microcontroller to manage
the algorithm. The reason for this is that there is no facility for
the two cascaded devices to automatically know the cell voltages
on the other device. While one device might be balancing all cells
to a voltage of 3V, the other might be balancing toward a voltage
of 3.2V. To simplify the microcontroller design, all scanning and
protection functions operate normally. The external
The cell balance FETs are driven by a current source or sink of
25µA. The gate voltage on the externals FET is set by the gate to
source resistor. This resistor should be set such that the gate
voltage does not exceed 9V. An external 9V zener diode across
the gate to source resistor can help to prevent overvoltage
conditions on the cell balance pin.
The cell balance circuit connection is shown in Figure 30 on
page 41.
microcontroller needs to scan the voltages and monitor status
bits, then make decisions based on the available information
and control the cell balance FETs. Since balancing is unrestricted,
the µC needs only to set the uC_Does_CellBalance state to stop
balancing while the upper device detects no current.
µC Control of Cell Balance FETs
To control the cell balance FETs, the external microcontroller first
needs to set the µCCBAL bit (non-cascaded) to turn off the
automatic cell balance operation. In a cascaded configuration,
the external microcontroller needs to set the CASC bit on the
lower device. This turns off the detection of current. The external
microcontroller also needs to use the µCCBAL bit to override the
automatic cell balance operation.
To turn on a cell balance FET, the µC needs to turn on the cell
balance output FET using the Cell Balance Control Register 84H.
In this register, each bit corresponds to a specific cell balance
output.
With the cell balance outputs specified, the microcontroller sets
the CBAL_ON bit. This turns on the cell balance output control
circuit.
FN7626 Rev 5.00
February 17, 2016
Page 40 of 64
ISL94203
ISL94203
CBAL_ON
ENABLE
CB5ON
100Ω
VC8
470nF
10kΩ
4M
10V
CB8
VC7
316kΩ
39Ω
1kΩ
47nF
10kΩ
10V
10V
4M
4M
CB7
VC6
CB6
CB4ON
CB3ON
316kΩ
39Ω
1kΩ
47nF
10kΩ
316kΩ
39Ω
CB2ON
CB1ON
1kΩ
VC5
CB5
VC4
CB4
47nF
10kΩ
39Ω
10V
10V
10V
10V
316kΩ
1kΩ
4M
4M
4M
47nF
10kΩ
39Ω
39Ω
39Ω
39Ω
316kΩ
1kΩ
VC3
CB3
VC2
CB2
VC1
CB1
47nF
10kΩ
316kΩ
1kΩ
47nF
10kΩ
316kΩ
1kΩ
4M
4M
47nF
10kΩ
316kΩ
1kΩ
10V
VC0
VSS
CB8ON
CB7ON
CB6ON
47nF
VSS
FIGURE 30. CELL BALANCE DRIVE CIRCUITS AND CELL CONNECTION OPTIONS
causes a timeout event. The ISL94203 needs to see a start bit
and a valid slave byte to restart the timer.
Watchdog Timer
2
The I C watchdog timer prevents an external microcontroller
The watchdog timeout signal turns off the cell balance and
power FET outputs, resets the serial interface and pulses the INT
output once per second in an attempt to get the microcontroller
to respond. If the INT is unsuccessful in restarting the
2
from initiating an action that it cannot undo through the I C port,
which can result in poor or unexpected operation of the pack.
The watchdog timer is normally inactive when operating the
device in a stand-alone operation. When the pack is expected to
have a µC along with the ISL94203, the WDT is activated by
setting any of the following bits:
communication interface, the part operates normally, except the
power FETs and cell balance FETs are forced off. The ISL94203
2
remains in this condition until I C communications resumes.
2
When I C communication resumes, the µCSCAN, µCCMON,
µCSCAN, µCCMON, µCLMON, µCCBAL, µCFET, EEEN.
µCLMON, µCFET and EEEN bits are automatically cleared and the
µCCBAL bit remains set. The power FETs and cell balance FETs
turn on, if conditions allow.
When active (an external µC is assumed to be connected), the
2
absence of I C communications for the watchdog timeout period
FN7626 Rev 5.00
February 17, 2016
Page 41 of 64
ISL94203
The PSD pin goes active high, when any cell voltage reaches the
OVLO threshold (OVLO flag). Optionally, PSD also goes high if
there is a voltage differential between any two cells that is
greater than a specified limit (CELLF flag) or if there is an
open-wire condition. This pin can be used for blowing a fuse in
the pack or as an interrupt to an external µC.
Power FET Drive
The ISL94203 drives the power FETs gates with a voltage higher
than the supply voltage by using external capacitors as part of a
charge pump. The capacitors connect (as shown in Figure 2 on
page 7) and are nominally 4.7nF. The charge pump applies
approximately (V *2) voltage to the gate, although the voltage
is clamped at V + 16V.
DD
DD
An input pin (FETSOFF), when pulled high, turns off the power
FETs and the cell balance FETs, regardless of any other condition.
The Power FET turn-on times are limited by the capacitance of
the power FET and the current supplied by the charge pump. The
power FET turn-off times are limited by the capacitance of the
power FET and the pull-down current of the ISL94203. The
ISL94203 provides a pull-down current for up to 300µs. This
should be long enough to discharge any FET capacitance.
Higher Voltage Microcontrollers
When using a microcontroller powered by 3.3V or 5V, the design
can include pull-up resistors to the microcontroller supply on the
communication link and the open-drain SD and EOC pins
(instead of pull-up resistors to RGO.)
Table 11 shows typical turn-on and turn-off times for the
ISL94203 under specific conditions.
The INT pin is a CMOS output with a maximum voltage of
RGO+0.5V. It is OK to connect this directly to a microcontroller as
long as the microcontroller pin does not have a pull up to the
3.3/5V supply. If it does, then a series resistor is recommended.
TABLE 11. POWER FET GATE CONTROL (TYPICAL)
PARAMETER
CONDITIONS
TYPICAL
The FETSOFF input on the ISL94203 is also limited to RGO+0.5V.
This is limited by an input ESD structure that clamps the voltage.
The connection from the µC to this pin should include a series
resistor to limit any current resulting from the clamp.
Power FET Gate DFET, CFET, PCFET
Turn-On Current Charge pump caps = 4.7nF
32kHz 5mA, pulses,
50% duty cycle
Power FET Gate 10% to 90% of final voltage
Turn-On Time
V
= 28V;
DD
DFET, CFET = IRF1404
PCFET = FDD8451
160µs
160µs
An example of this connection is shown in Figure 31.
ISL94203
µCONTROLLER
3.3/5V
Power FET Gate CFET, CFET, PCFET
Turn-Off Current
13mA(CFET, PCFET)
15mA (DFET)
Power FET Gate Pulse duration
Turn-Off Pulse
Width
300µs
SD
In_SD
In_EOC
In_INT
EOC
INT
Power FET Gate 90% to 10% of final voltage
*
Fall Time
V
= 28V;
DD
SCL
SCL
SDA
DFET: IRF1404
CFET: IRF1404
PCFET: FDD8451
6µs
6µs
2µs
SDAI
SDAO
FETSOFF
10k
Out_FETSOFF
* Resistor needed only if µC has a pull-up on the In_INT pin
General I/Os
There is an open-drain output (SD) that is pulled up to RGO (using
an external resistor) and indicates if there are any error
conditions, such as overvoltage, undervoltage, over-temperature,
open input and overcurrent. The output goes active (LOW) when
there is any cell or pack failure condition. The output returns
HIGH when all error conditions clear.
FIGURE 31. CONNECTION OF HIGHER VOLTAGE MICROCONTROLLER
Packs with Fewer than 8 Cells
See “Pack Configuration” on page 20 for help when using fewer
than 8 cells. This section presents options for minimum number
of components. However, when using the ISL94203EVAL1Z
evaluation board with fewer than 8 cells, it is not necessary to
remove components from the PCB. Simply tie the unused
connections together, as shown in Figure 32. This normally
requires only a different cable.
There is an open-drain output (EOC) that is pulled up to RGO
(using an external resistor) and indicates that the cells have
reached an end of conversion state. The output goes active
(LOW) when all cell voltages are above a threshold specified by a
12-bit value in EEPROM. The output returns HIGH, when all cells
are below the EOC threshold.
Factory programmable options offer inverse polarity of SD or
EOC. Please contact Automotive Marketing if there is interest in
either of these options.
FN7626 Rev 5.00
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ISL94203
8 CELLS
VC8
7 CELLS
VC8
6 CELLS
VC8
CB8
VC7
CB7
VC6
CB8
VC7
CB7
VC6
CB8
VC7
CB7
VC6
CB6
VC5
CB5
VC4
CB6
VC5
CB5
VC4
CB6
VC5
CB5
VC4
CB4
VC3
CB4
VC3
CB4
VC3
CB3
VC2
CB2
VC1
CB1
CB3
VC2
CB2
VC1
CB1
CB3
VC2
CB2
VC1
CB1
VC0
VSS
VC0
VSS
VC0
VSS
5 CELLS
VC8
4 CELLS
VC8
3 CELLS
VC8
CB8
VC7
CB7
VC6
CB6
VC5
CB5
VC4
CB8
VC7
CB7
VC6
CB6
VC5
CB5
VC4
CB8
VC7
CB7
VC6
CB6
VC5
CB5
VC4
CB4
VC3
CB4
VC3
CB4
VC3
CB3
VC2
CB2
VC1
CB1
CB3
VC2
CB2
VC1
CB1
CB3
VC2
CB2
VC1
CB1
VC0
VSS
VC0
VSS
VC0
VSS
FIGURE 32. BATTERY CONNECTION OPTIONS USING THE ISL94203EVAL1Z BOARD
signal lines add inductance at high frequency and should be
avoided.
PC Board Layout
The AC performance of this circuit depends greatly on the care
taken in designing the PC board. The following are
recommendations to achieve optimum high performance from
your PC board.
• Match channel-to-channel analog I/O trace lengths and layout
symmetry. This is especially true for the CS1 and CS2 lines,
since their inputs are normally very low voltage.
• Maximize use of AC decoupled PCB layers. All signal I/O lines
should be routed over continuous ground planes (i.e. no split
planes or ground plane gaps under these lines). Avoid vias in
the signal I/O lines.
• The use of low inductance components, such as chip resistors
and chip capacitors, is strongly recommended.
• Minimize signal trace lengths. This is especially true for the
CS1, CS2 and VC0-VC8 inputs. Trace inductance and
capacitance can easily affect circuit performance. Vias in the
• VDD bypass and charge pump capacitors should use wide
temperature and high frequency dielectric (X7R or better) with
capacitors rated at 2X the maximum operating voltage.
FN7626 Rev 5.00
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ISL94203
• The charge pump and VDD bypass capacitors should be
located close to the ISL94203 pins and VDD should have a
good ground connection.
EEPROM
The ISL94203 contains an EEPROM array for storing the device
configuration parameters, the device calibration values and
some user available registers. Access to the EEPROM is through
• When testing use good quality connectors and cables,
matching cable types and keeping cable lengths to a
minimum.
2
the I C port of the device. Memory is organized in a memory map
as described in “Registers: Summary (EEPROM)” on page 49,
“Registers: Summary (RAM)” on page 49, “Registers: Detailed
(EEPROM)” on page 50 and “Registers: Detailed (RAM)” on
page 57.
• An example PCB layout is shown in Figure 33. This shows
placement of the VDD bypass capacitor close to the VDD pin
and with a good ground connection. The charge pump
capacitors are also close to the IC. The current sense lines are
shielded by ground plane as much as possible. The ground
plane under the IC is shown as an “island”. The intent of this
layout was to minimize voltages induced by EMI on the ground
plane in the vicinity of the IC. This example assumes a 4-layer
board with most signals on the inner layers.
When the device powers up, the ISL94203 transfers the contents
of the configuration EEPROM memory areas to RAM (Note: the
user EEPROM has no associated RAM). An external
microcontroller can read the contents of the Configuration RAM
or the contents of the EEPROM. Prior to reading the EEPROM, set
the EEEN bit to “1”. This enables access to the EEPROM area. If
EEEN is “0”, then a read or write occurs in the shadow RAM area.
VDD Cap
Charge Pump Caps
GND Plane
Current Sense Inputs
The content of the Shadow Ram determines the operation of the
device.
Reading from the RAM or EEPROM can be done using a byte or
page read. See:
• “Current Address Read” on page 47
• “Random Read” on page 47
• “Sequential Read” on page 47
• “EEPROM Access” on page 48
• “Register Protection” on page 48
Writing to the Configuration or User EEPROM must use a Page
Write operation. Each Page is four bytes in length and pages
begin at address 0.
See:
• “Page Write” on page 46
• “Register Protection” on page 48
Pink = Top
Blue = Bottom
“Island Ground”
The EEPROM contains an error detection and correction
mechanism. When reading a value from the EEPROM, the device
checks the data value for an error.
FIGURE 33. EXAMPLE 4-LAYER PCB LAYOUT FOR VDD BYPASS,
CHARGE PUMP AND CURRENT SENSE
If there are no errors, then the EEPROM value is valid and the
ECC_USED and ECC_FAIL bits are set to “0”. If there is a 1-bit
error, the ISL94203 corrects the error and sets the ECC_USED bit.
This is a valid operation and value read from the EEPROM is
correct. During an EEPROM read, if there is an error consisting of
two or more bits, the ISL94203 sets the ECC_FAIL bit
QFN Package
The QFN package requires additional PCB layout rules for the
thermal pad. The thermal pad is electrically connected to VSS
supply through the high resistance IC substrate. The thermal pad
provides heat sinking for the IC. In normal operation, the device
should generate little heat, so thermal pad design and layout are
not too important. However, if the design uses the RGO pin to
supply power to external components, then the IC can experience
some internal power dissipation. In this case, careful layout of
the thermal pad and the use of thermal vias to direct the heat
away from the IC is an important consideration. Besides heat
dissipation, the thermal pad also provides noise reduction by
providing a ground plane under the IC.
(ECC_USED = 0). This read contains invalid data.
The error correction is also active during the initial power-on recall
of the EEPROM values to the shadow RAM. The circuit corrects for
any one-bit errors. Two-bit errors are not corrected and the
contents of the shadow RAM maintain the previous value.
Internally, the Power-on Recall circuit uses the ECC_USED and
ECC_FAIL bits to determine there is a proper recall before
allowing the device operation to start. However, an external µC
cannot use these bits to detect the validity of the shadow RAM on
power-up or determine the use of the error correction
mechanism, because the bits automatically reset on the next
valid read.
Circuit Diagrams
The “Block Diagram” on page 7 shows a simple application
diagram with 8 cells in series and two cells in parallel (8S2P).
FN7626 Rev 5.00
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ISL94203
In the read mode, the device transmits eight bits of data,
releases the SDA line, then monitor the line for an acknowledge.
If an acknowledge is detected and no stop condition is generated
by the master, the device will continue to transmit data. The
device terminates further data transmissions if an acknowledge
is not detected. The master must then issue a stop condition to
return the device to Standby mode and place the device into a
known state.
Serial Interface
• The ISL94203 uses a standard I C interface, except the design
separates the SDA input and output (SDAI and SDAO)
2
• Separate SDAI and SDAO lines can be tied together and
2
operate as a typical I C bus
• Interface speed is 400kHz, maximum
• A separate pin is provided to select the slave address of device.
This allows two devices to be cascaded
SCL
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is called the master and the device being
controlled is called the slave. The master always initiates data
transfers and provides the clock for both transmit and receive
operations. Therefore, the ISL94203 devices operate as slaves in
all applications.
SDA
DATA
STABLE
DATA
CHANGE
DATA
STABLE
2
FIGURE 34. VALID DATA CHANGES ON I C BUS
When sending or receiving data, the convention is the most
significant bit (MSB) is sent first. Therefore, the first address bit
sent is Bit 7.
SCL
SDA
Clock and Data
Data states on the SDA line can change only while SCL is LOW.
SDA state changes during SCL HIGH are reserved for indicating
start and stop conditions (see Figure 34).
START
STOP
2
FIGURE 35. I C START AND STOP BITS
Start Condition
SCL FROM
MASTER
All commands are preceded by the start condition, which is a
HIGH-to-LOW transition of SDA when SCL is HIGH. The device
continuously monitors the SDA and SCL lines for the start
condition and will not respond to any command until this
condition has been met (see Figure 35).
1
8
9
DATA OUTPUT
FROM
TRANSMITTER
Stop Condition
DATA OUTPUT
All communications must be terminated by a stop condition,
which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The
stop condition is also used to place the device into the Standby
power mode after a read sequence. A stop condition is only
issued after the transmitting device has released the bus (see
Figure 35).
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 36. ACKNOWLEDGE RESPONSE FROM RECEIVER
Write Operations
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either master
or slave, releases the bus after transmitting eight bits. During the
ninth clock cycle, the receiver pulls the SDA line LOW to
acknowledge that it received the eight bits of data (see
Figure 36).
BYTE WRITE
For a byte write operation, the device requires the Slave Address
Byte and a Word Address Byte. This gives the master access to
any one of the words in the array. After receipt of the Word
Address Byte, the device responds with an acknowledge and
awaits the next eight bits of data. After receiving the 8 bits of the
Data Byte, the device again responds with an acknowledge. The
master then terminates the transfer by generating a stop
condition, at which time the device begins the internal write cycle
to the nonvolatile memory. During this internal write cycle, the
device inputs are disabled, so the device will not respond to any
requests from the master. The SDA output is at high impedance.
See Figure 37 on page 46.
The device responds with an acknowledge after recognition of a
start condition and the correct slave byte. If a write operation is
selected, the device responds with an acknowledge after the
receipt of each subsequent eight bits. The device acknowledges
all incoming data and address bytes, except for the slave byte
when the contents do not match the device’s internal slave
address.
FN7626 Rev 5.00
February 17, 2016
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ISL94203
PAGE WRITE
WATCHDOG
TIMER
A page write operation is initiated in the same manner as the
byte write operation; but instead of terminating the write cycle
after the first data byte is transferred, the master can transmit an
unlimited number of 8-bit bytes. After the receipt of each byte,
the device will respond with an acknowledge and the address is
internally incremented by one. The page address remains
constant. When the counter reaches the end of the page, it “rolls
over” and goes back to ‘0’ on the same page. This means that
the master can write 4 bytes to the page starting at any location
on that page. If the master begins writing at location 2 and loads
4 bytes, then the first 2 bytes are written to locations 2 and 3 and
the last 2 bytes are written to locations 0 and 1. Afterwards, the
address counter would point to location 2 of the page that was
just written. If the master supplies more than 4 bytes of data,
then new data overwrites the previous data, one byte at a time.
See Figure 38.
RESET
S
T
A
R
T
S
T
O
P
SLAVE
BYTE
BYTE
ADDRESS
DATA
SDA BUS
0 1 0 1 0 0 0 0
A
C
K
A
C
K
A
C
K
ISL94203: SLAVE BYTE = 50H (ADDR = 0)
ISL94203: SLAVE BYTE = 52H (ADDR = 1)
FIGURE 37. BYTE WRITE SEQUENCE
Do not write to addresses 58H through 7FH or locations higher
than address ABH, since these addresses access registers that
are reserved. Writing to these locations can result in unexpected
device operation.
A write to a protected block of memory suppresses the
acknowledge bit.
When writing to the EEPROM, write to all addresses of a page
without an intermediate read operation or use a page write
command. Each page is 4 bytes long, starting at address 0.
ADDRESS = 0
DATA BYTE 3
ADDRESS = 1
DATA BYTE 4
ADDRESS = 2
DATA BYTE 1
ADDRESS = 3
DATA BYTE 2
ADDRESS POINTER STARTS AND ENDS HERE
FIGURE 38. WRITING 4 BYTES TO A 4-BYTE PAGE STARTING AT LOCATION 2
WATCHDOG TIMER
S
T
A
R
T
S
T
O
P
SLAVE
BYTE
REGISTER
ADDRESS
DATA(1)
DATA(n)
SDA BUS
0 1 0 1 0 0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
ISL94203: SLAVE BYTE = 50H (ADDR = 0)
ISL94203: SLAVE BYTE = 52H (ADDR = 1)
FIGURE 39. PAGE WRITE SEQUENCE
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ISL94203
WATCHDOG TIMER RESET
S
T
A
R
T
S
T
A
R
T
S
T
O
P
N
A
C
K
SLAVE
BYTE
SLAVE
BYTE
REGISTER
ADDRESS
SDA BUS
0 1 0 1 0 0 0 0
0 1 0 1 0 0 0 1
A
C
K
A
C
K
A
C
K
A
C
K
DATA
ISL94203: SLAVE BYTE = 50H (ADDR = 0)
ISL94203: SLAVE BYTE = 52H (ADDR = 1)
FIGURE 40. RANDOM READ SEQUENCE
WATCHDOG TIMER RESET
S
T
O
P
N
A
C
K
SLAVE
BYTE
1
A
C
K
A
C
K
A
C
K
A
C
K
DATA 1
DATA 2
DATA (n-1)
DATA (n)
ISL94203: SLAVE BYTE = 50H (ADDR = 0)
ISL94203: SLAVE BYTE = 52H (ADDR = 1)
FIGURE 41. SEQUENTIAL READ SEQUENCE
the R/W bit set to one, the master must first perform a “dummy”
write operation. The master issues the start condition and the
Slave Address Byte, receives an acknowledge, then issues the
Word Address Bytes. After acknowledging receipts of the Word
Address Bytes, the master immediately issues another start
condition and the Slave Address Byte with the R/W bit set to one.
This is followed by an acknowledge from the device and then by
the eight bit word. The master terminates the read operation by
not responding with an acknowledge and then issuing a stop
condition (see Figure 40).
Read Operations
Read operations are initiated in the same manner as write
operations with the exception that the R/W bit of the Slave
Address Byte is set to one. There are three basic read operations:
Current Address Reads, Random Reads and Sequential Reads.
CURRENT ADDRESS READ
Internally the device contains an address counter that maintains
the address of the last word read incremented by one. Therefore,
if the last read was to address n, the next read operation would
access data from address n+1. On power-up, the address of the
address counter is undefined, requiring a read or write operation
for initialization. See Figure 42.
SEQUENTIAL READ
Sequential reads can be initiated as either a current address
read or random address read. The first Data Byte is transmitted
as with the other modes; however, the master now responds with
an acknowledge, indicating it requires additional data. The
device continues to output data for each acknowledge received.
The master terminates the read operation by not responding with
an acknowledge and then issuing a stop condition.
Upon receipt of the Slave Address Byte with the R/W bit set to
one, the device issues an acknowledge and then transmits the
eight bits of the Data Byte. The master terminates the read
operation when it does not respond with an acknowledge during
the ninth clock and then issues a stop condition.
The data output is sequential, with the data from address n
followed by the data from address n + 1. The address counter for
read operations increments through all page and column
addresses, allowing the entire memory contents to be serially
read during one operation. At the end of the address space the
counter “rolls over” to address 0000H and the device continues
to output data for each acknowledge received. See Figure 41 for
the acknowledge and data transfer sequence.
It should be noted that the ninth clock cycle of the read operation
is not a “don’t care.” To terminate a read operation, the master
must either issue a stop condition during the ninth cycle or hold
SDA HIGH during the ninth clock cycle and then issue a stop
condition.
RANDOM READ
Random read operation allows the master to access any memory
location in the array. Prior to issuing the Slave Address Byte with
FN7626 Rev 5.00
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ISL94203
WATCHDOG TIMER RESET
S
T
A
R
T
S
T
O
P
N
A
C
K
SLAVE
BYTE
0 1 0 1 0 0 0 1
SDA BUS
A
C
K
A
C
K
DATA
ISL94203: SLAVE BYTE = 50H (ADDR = 0)
ISL94203: SLAVE BYTE = 52H (ADDR = 1)
FIGURE 42. CURRENT ADDRESS READ SEQUENCE
read or write operations. This insures that the results reported to
EEPROM ACCESS
the µC are from a single scan and changes made do not interfere
with state machine detection and timing.
The user is advised not to use page transfers when reading or
writing to EEPROM. Only single byte I C transactions should be
2
used. In addition, “Write” transactions should be separated with
a 30ms delay to enable each byte write operation to complete.
Register Protection
The entire EEPROM memory is write protected on initial power-up
and during normal operation. An enable byte allows writing to
various areas of the memory array.
EEPROM READ
The ISL94203 has a special requirement when reading the
EEPROM. An EEPROM read operation from the first byte of a four
byte page (locations 0H, 4H, 8H, etc.) initiates a recall of the
EEPROM page. This recall takes more than 200µs, so the first
The enable byte is encoded, so that a value of ‘0’ in the EEPROM
Enable register (89H) enables access to the shadow memory
(RAM), a value of ‘1’ allows access to the EEPROM.
2
byte may not be ready in time for a standard I C response. It is
necessary to read this first byte of every page two times.
After a read or write of the EEPROM, the microcontroller should
reset the EEPROM Enable register value back to zero to prevent
inadvertent writes to the EEPROM and to turn off the EEPROM
block to reduce current consumption. If the microcontroller fails
to reset the EEPROM bit and communications to the chip stops,
then the Watchdog timer will reset the EEPROM select bit.
EEPROM WRITE
The ISL94203 also has a special requirement when writing the
EEPROM. An EEPROM write operation to the first byte of a four
byte page (locations 0H, 4H, 8H, etc.) initiates a recall of the
EEPROM page. This recall takes more than 200µs, so the first
2
byte may not be ready in time for a standard I C response. It is
necessary to write this first byte of every page two times. These
“duplicate” writes should be separated with a 30ms delay and
followed with a 30ms delay. Again, only single byte transactions
should be used with a 30ms delay between each write operation.
Synchronizing Microcontroller Operations
with Internal Scan
Internal scans occur every 32ms in Normal mode, 256ms in Idle
mode and 512ms in Doze mode. The internal scan normally
takes about 1.3ms, with every fourth scan taking about 1.7ms.
While the percentage of time taken by the scan is small, it is long
enough that random communications from the microcontroller
can coincide with the internal scan. When the two scans happen
at the same time, errors can occur in the recorded values.
To avoid errors in the recorded values, the goal is to synchronize
2
external I C transactions so that they only occur during the
device’s Low Power State (see Figure 23 on page 31.) To assist in
the synchronization, the microcontroller can use the INT_SCAN
bit. This bit is “0” during the internal scan and “1” during the “Low
Power State”.
The microcontroller software should look for the INT_SCAN bit to
go from a “0” to a “1” to allow the maximum time to complete
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ISL94203
Registers: Summary (EEPROM)
TABLE 12. EEPROM REGISTER SUMMARY
EEPROM (CONFIGURED AS 32 4-BYTE PAGES)
PAGE
0
ADDR
0x
1x
2x
3x
4x
5x
0
1
Overvoltage Level
Overvoltage Delay Minimum CB Delta
Timer
Charge
Over-Temperature
Level
Internal
Over-Temperature
Level
User EEPROM
2
3
Overvoltage
recovery
Undervoltage Delay Maximum CB Delta Charge Over-Temp
Internal
Over-Temperature
Recovery
Timer
Recovery
1
4
5
Undervoltage Level Open Wire Timing Cell Balance On time
Charge
Under-Temperature
Level
Sleep Voltage
6
7
Undervoltage
Recovery
Discharge
OvercurrentTimeout
Settings, Discharge
Setting
Cell Balance Off
Time
Charge
Under-Temperature
Recovery
Sleep Delay Timer/
Watchdog Timer
2
8
9
OVLO Threshold
UVLO Threshold
EOC Voltage Level
Charge overcurrent
Timeout Settings,
Charge overcurrent
Setting
Minimum CB
Temperature Level Over-Temperature
Level
Discharge
Sleep Mode Timer
CELLS Config
Reserved
A
B
Short-Circuit
Minimum CB
Temperature
Recovery
Discharge
Over-Temperature
Recovery
Features 1
Features 2
Timeout Settings/
Recovery Settings,
Short-Circuit Setting
3
C
Minimum CB Volts
Maximum CB
Discharge
Reserved
Temperature Level Under-Temperature
Level
D
E
F
Low Voltage Charge Maximum CB Volts
Level
Maximum CB
Temperature
Recovery
Discharge
Under-Temperature
Recovery
Registers: Summary (RAM)
TABLE 13. RAM REGISTER SUMMARY
RAM
PAGE
ADDR
8x
9x
Ax
0
1
2
0
1
2
3
4
5
6
7
8
9
A
B
Status1
CELL1 Voltage
iT Voltage
Status2
Status3
CELL2 Voltage
CELL3 Voltage
xT1 Voltage
Status4
Cell Balance
Analog Out
xT2 Voltage
FET Cntl/Override Control Bits
Override Control Bits
Force Ops
CELL4 Voltage
CELL5 Voltage
CELL6 Voltage
VBATT/16 Voltage
VRGO/2 Voltage
14-bit ADC Voltage
EE Write Enable
CELLMIN Voltage
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ISL94203
TABLE 13. RAM REGISTER SUMMARY (Continued)
RAM
PAGE
3
ADDR
8x
9x
Ax
C
D
E
F
CELLMAX Voltage
CELL7 Voltage
Reserved
ISense Voltage
CELL8 Voltage
Registers: Detailed (EEPROM)
TABLE 14. EEPROM REGISTER DETAIL
BIT/
ADDR
F
7
E
6
D
5
C
4
B
3
A
2
9
1
8
0
7
6
5
4
3
2
1
0
00
01
Overvoltage Threshold
If any cell voltage is above this threshold voltage for an overvoltage delay time,
the charge FET is turned off.
Default (Hex): 1E2A
(V): 4.25
Charge Detect Pulse Width
These bits set the duration of the
charger monitor pulse width.
OVLB
OVLA
OVL9
OVL8
OVL7
OVL6
OVL5
OVL4
OVL3
OVL2
OVL1
OVL0
CPW3 CPW2 CPW1 CPW0
HEXvalue 1.8 8
10
-----------------------------------------------------------
Threshold =
0000 = 0ms to
1111 = 15ms; Default = 1ms
4095 3
02
03
Overvoltage Recovery
If all cells fall below this overvoltage recovery level, the charge FET is turned on.
Default (Hex): 0DD4
(V): 4.15
Reserved
OVRB OVRA OVR9 OVR8 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0
04
05
Undervoltage Threshold
If any cell voltage is below this threshold voltage for an undervoltage delay time,
the discharge FET is turned off.
Default (Hex): 18FF (V): 2.7
Load Detect Pulse Width
UVLB
UVLA
UVL9
UVL8
UVL7
UVL6
UVL5
UVL4
UVL3
UVL2
UVL1
UVL0
These bits set the duration of the
charger monitor pulse width.
LPW3 LPW2 LPW1 LPW0
HEXvalue 1.8 8
10
-----------------------------------------------------------
Threshold =
0000 = 0 ms to
1111 = 15ms; Default = 1ms
4095 3
06
07
Undervoltage Recovery
If all cells rise above this overvoltage recovery level (and there is no load), the
discharge FET is turned on.
Default (Hex): 09FF
V): 3.0
Reserved
UVRB UVRA UVR9 UVR8 UVR7 UVR6 UVR5 UVR4 UVR3 UVR2 UVR1 UVR0
Default (Hex): 0E7F (V): 4.35
08
09
Overvoltage Lockout Threshold
If any cell voltage is above this threshold for five successive scans, then the
device is in an overvoltage lockout condition. In this condition, the Charge FET is
turned off, the cell balance FETs are turned off, the OVLO bit is set and the PSD
output is set to active.
Reserved
OVLOB OVLOA OVLO9 OVLO8 OVLO7 OVLO6 OVLO5 OVLO4 OVLO3 OVLO2 OVLO1 OVLO0
Default (Hex): 0600 (V): 1.8
0A
0B
Undervoltage Lockout Threshold
If any cell voltage is below this threshold for five successive scans, then the
device is in an undervoltage lockout condition. In this condition, the Discharge
FET is turned off and the UVLO bit is set. The device also powers down (unless
overridden).
Reserved
UVLOB UVLOA UVLO9 UVLO8 UVLO7 UVLO6 UVLO5 UVLO4 UVLO3 UVLO2 UVLO1 UVLO0
FN7626 Rev 5.00
February 17, 2016
Page 50 of 64
ISL94203
TABLE 14. EEPROM REGISTER DETAIL (Continued)
BIT/
ADDR
F
7
E
6
D
5
C
4
B
3
A
2
9
1
8
0
7
6
5
4
3
2
1
0
0C
0D
End-of-Charge (EOC) Threshold
If any cell exceeds this level, then the EOC output and the EOC bit are set.
Default (Hex): 0DFF
(V): 4.2
Reserved
EOCB EOCA EOC9 EOC8 EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
0E
0F
Low Voltage Charge Level
Default (Hex): 07AA (V): 2.3
If the voltage on any cell is less than this level, then the PCFET output turns on
instead of the PC output. To disable this function, set the value to zero or set the
PCFETE bit to 0.
Reserved
LVCHB LVCHA LVCH9 LVCH8 LVCH7 LVCH6 LVCH5 LVCH4 LVCH3 LVCH2 LVCH1 LVCH0
10
11
Overvoltage Delay Time Out
This value sets the time that is required for any cell to be above the overvoltage
threshold before an overvoltage condition is detected.
Default (Hex): 0801 (s):
1
Reserved
OVDTB OVDTA OVDT9 OVDT8 OVDT7 OVDT6 OVDT5 OVDT4 OVDT3 OVDT2 OVDT1 OVDT0
00 = µs
01 = ms
10 = s
0 to 1024
11 = min
12
13
Undervoltage Delay Time Out
This value sets the time that is required for any cell to be below the undervoltage
threshold before an undervoltage condition is detected.
Default (Hex): 0801
(s):
1
Reserved
UVDTB UVDTA UVDT9 UVDT8 UVDT7 UVDT6 UVDT5 UVDT4 UVDT3 UVDT2 UVDT1 UVDT0
00 = µs
01 = ms
10 = s
0 to 1024
11 = min
14
15
Open-Wire Timing (OWT)
This value sets the width of the open-wire test pulse for each cell input.
Default (Hex): 0214
(ms):
20
Reserved
OWT
9
OWT
8
OWT
7
OWT
6
OWT
5
OWT
4
OWT
3
OWT
2
OWT
1
OWT
0
0 = µs
0 to 512
1 = ms
16
17
Discharge Overcurrent Time Out/Threshold
Time Out
Default (Hex): 44A0
(ms): 160
(mV): 32
A discharge overcurrent needs to remain for this time period prior to entering a
discharge overcurrent condition. This is an 12-bit value: Lower 10 bits sets the
time. Upper bits sets the time base.
Threshold
This value sets the voltage across
current sense resistor that creates
a discharge overcurrent condition.
OCD2 OCD1 OCD0
OCDTB OCDTA OCDT9 OCDT8 OCDT7 OCDT6 OCDT5 OCDT4 OCDT3 OCDT2 OCDT1 OCDT0
000 = 4mV
001 = 8mV
010 = 16mV
011 = 24mV
100 = 32mV
101 = 48mV
110 = 64mV
111 = 96mV
00 = µs
01 = ms
10 = s
0 to 1024
11 = min
FN7626 Rev 5.00
February 17, 2016
Page 51 of 64
ISL94203
TABLE 14. EEPROM REGISTER DETAIL (Continued)
BIT/
ADDR
F
7
E
6
D
5
C
4
B
3
A
2
9
1
8
0
7
6
5
4
3
2
1
0
18
19
Charge Overcurrent Time Out/Threshold
Time Out
Default (Hex): 44A0
(ms): 160
(mV):
8
A charge overcurrent needs to remain for this time period prior to entering a
charge overcurrent condition. This is an 12-bit value: Lower 10 bits sets the time.
Upper bits set the time base.
Threshold
This value sets the voltage across
current sense resistor that creates
a charge overcurrent condition
OCC2 OCC1 OCC0
OCCTB OCCTA OCCT9 OCCT8 OCCT7 OCCT6 OCCT5 OCCT4 OCCT3 OCCT2 OCCT1 OCCT0
000 = 1mV
001 = 2mV
010 = 4mV
011 = 6mV
100 = 8mV
101 = 12mV
110 = 16mV
111 = 24mV
00 = µs
01 = ms
10 = s
0 to 1024
11 = min
1A
1B
Discharge Short-Circuit Time Out/Threshold
Time Out
Default (Hex): 60C8
(µs): 200
(mV): 128
A short-circuit current needs to remain for this time period prior to entering a
short-circuit condition. This is an 12 bit value:
Lower 10 bits sets the time. Upper bits set the time base
Threshold
This value sets the voltage across
current sense resistor that creates
a short-circuit condition
SCD2 SCD1 SCD0
SCTB
SCTA
SCT9
SCT8
SCT7
SCT6
SCT5
SCT4
SCT3
SCT2
SCT1
SCT0
000 = 16mV
001 = 24mV
010 = 32mV
011 = 48mV
100 = 64mV
101 = 96mV
110 = 128mV
111 = 256mV
00 = µs
01 = ms
10 = s
0 to 1024
11 = min
1C
1D
Cell Balance Minimum Voltage (CBMIN)
If all cell voltages are less than this voltage, then cell balance stops.
Default (Hex): 0A55
(V): 3.1
Reserved CBVLB CBVLA CBVL9 CBVL8 CBVL7 CBVL6 CBVL5 CBVL4 CBVL3 CBVL2 CBVL1 CBVL0
1E
1F
Cell Balance Maximum Voltage (CBMAX)
If all cell voltages are greater than this voltage, then cell balance stops.
Default (Hex): 0D70
(V): 4.0
Reserved
CBVUB CBVUA CBVU9 CBVU8 CBVU7 CBVU6 CBVU5 CBVU4 CBVU3 CBVU2 CBVU1 CBVU0
20
21
Cell Balance Minimum Differential Voltage (CBMINDV)
If the difference between the voltage on CELLN and the lowest voltage cell is less
than this voltage, then cell balance for CELLN stops.
Default (Hex): 0010
(mV):
20
Reserved
CBDLB CBDLA CBDL9 CBDL8 CBDL7 CBDL6 CBDL5 CBDL4 CBDL3 CBDL2 CBDL1 CBDL0
22
23
Cell Balance Maximum Differential Voltage (CBMAXDV)
If the difference between the voltage on CELLN and the lowest voltage cell is
greater than this voltage, then cell balance for CELLN stops and the CELLF flag
is set.
Default (Hex): 01AB
(mV): 500
Reserved
CBDUB CBDUA CBDU9 CBDU8 CBDU7 CBDU6 CBDU5 CBDU4 CBDU3 CBDU2 CBDU1 CBDU0
FN7626 Rev 5.00
February 17, 2016
Page 52 of 64
ISL94203
TABLE 14. EEPROM REGISTER DETAIL (Continued)
BIT/
ADDR
F
7
E
6
D
5
C
4
B
3
A
2
9
1
8
0
7
6
5
4
3
2
1
0
2
24
25
Cell Balance On Time (CBON)
Default (Hex): 0802
(s):
Cell balance is on for this set amount of time, unless another condition indicates
that there should be no cell balance. This is a 12-bit value: Lower 10 bits sets the
time. Upper 2 bits set the time base.
Reserved
CBONT CBONT CBONT CBONT CBONT CBONT CBONT CBONT CBONT CBONT CBONT CBONT
B
A
9
8
7
6
5
4
3
2
1
0
00 = µs
0 to 1024
01 = ms
10 = s
11 = min
26
27
Cell Balance Off Time (CBOFF)
Cell balance is off for the set amount of time. This is a 12-bit value: Lower 10 bits
sets the time. Upper 2 bits set the time base.
Default (Hex): 0802
(s):
2
Reserved
CBOFT CBOFT CBOFT CBOFT CBOFT CBOFT CBOFT CBOFT CBOFT CBOFT CBOFT CBOFT
B
A
9
8
7
6
5
4
3
2
1
0
00 = µs
0 to 1024
01 = ms
10 = s
11 = min
28
29
Cell Balance Minimum Temperature Limit (CBUTS)
Default (Hex): 0BF2
(V): 1.344
(°C): -10
If the external 1 temperature or the external 2 temperature (XT2M = 0) is greater
than this voltage, then cell balance stops. The voltage is based on recommended
external components (see Figure 27 on page 35).
Reserved
CBUTS CBUTS CBUTS CBUTS CBUTS CBUTS CBUTS CBUTS CBUTS CBUTS CBUTS CBUTS
B
A
9
8
7
6
5
4
3
2
1
0
2A
2B
Cell Balance Minimum Temperature Recovery Level (CBUTR)
Default (Hex): 0A93
(V): 1.19
If the external 1 temperature and the external 2 temperature (XT2M = 0) all
recover and fall below this voltage, then cell balance can resume (all other
conditions OK). The voltage is based on recommended external components
(see Figure 27 on page 35).
(°C):
+5
Reserved
CBUTR CBUTR CBUTR CBUTR CBUTR CBUTR CBUTR CBUTR CBUTR CBUTR CBUTR CBUTR
B
A
9
8
7
6
5
4
3
2
1
0
2C
2D
Cell Balance Maximum Temperature Limit (CBOTS)
Default (Hex): 04B6
(V): 0.530
(°C): +55
If the external 1 temperature or the external 2 temperature (XT2M = 0) is less
than this voltage, then cell balance stops. The voltage is based on recommended
external components (see Figure 27 on page 35).
Reserved
CBOTS CBOTS CBOTS CBOTS CBOTS CBOTS CBOTS CBOTS CBOTS CBOTS CBOTS CBOTS
B
A
9
8
7
6
5
4
3
2
1
0
2E
2F
Cell Balance Maximum Temperature Recovery Level (CBOTR)
Default (Hex): 053E
(V): 0.590
(°C): +50
If the external 1 temperature and the external 2 temperature (XT2M = 0) all
recover and rise above this voltage, then cell balance can resume (all other
conditions OK). The voltage is based on recommended external components
(see Figure 27 on page 35).
Reserved
CBOTR CBOTR CBOTR CBOTR CBOTR CBOTR CBOTR CBOTR CBOTR CBOTR CBOTR CBOTR
B
A
9
8
7
6
5
4
3
2
1
0
For All Temperature Limits, TGain bit = 0, Temperature Gain = 2
Charge Over-Temperature Voltage
If external 1 temperature or the external 2 temperature is less than this voltage,
then the charge FET is turned off and the COT bit is set. The voltage is based on
recommended external components (see Figure 27 on page 35).
30
31
Default (Hex): 04B6
(mV): 0.530
(°C): +55
Reserved
COTSB COTSA COTS9 COTS8 COTS7 COTS6 COTS5 COTS4 COTS3 COTS2 COTS1 COTS0
FN7626 Rev 5.00
February 17, 2016
Page 53 of 64
ISL94203
TABLE 14. EEPROM REGISTER DETAIL (Continued)
BIT/
ADDR
F
7
E
6
D
5
C
4
B
3
A
2
9
1
8
0
7
6
5
4
3
2
1
0
32
33
Charge Over-Temperature Recovery Voltage
Default (Hex): 053E
(mV): 0.590
(°C): +50
If external 1 temperature or the external 2 temperature rise above this setting,
then the charge FET is turned on and the COT bit is reset (unless overrides are in
place). The voltage is based on recommended external components (see
Figure 27 on page 35).
Reserved
COTRB COTRA COTR9 COTR8 COTR7 COTR6 COTR5 COTR4 COTR3 COTR2 COTR1 COTR0
34
35
Charge Under-Temperature Voltage
Default (Hex): 0BF2
(mV): 1.344
(°C): -10
If external 1 temperature or the external 2 temperature is greater than this
voltage, then the charge FET is turned off and the CUT bit is set. The voltage is
based on recommended external components (see Figure 27 on page 35).
Reserved
CUTSB CUTSA CUTS9 CUTS8 CUTS7 CUTS6 CUTS5 CUTS4 CUTS3 CUTS2 CUTS1 CUTS0
36
37
Charge Under-Temperature Recovery Voltage
Default (Hex): 0A93
(mV): 1.190
(°C): +5
If external 1 temperature or the external 2 temperature fall below this setting,
then the charge FET is turned on and the CUT bit is reset (unless overrides are in
place). The voltage is based on recommended external components (see
Figure 27 on page 35).
Reserved
CUTRB CUTRA CUTR9 CUTR8 CUTR7 CUTR6 CUTR5 CUTR4 CUTR3 CUTR2 CUTR1 CUTR0
38
39
Discharge Over-Temperature Voltage
Default (Hex): 4B6
(mV): 0.530
(°C): +55
If external 1 temperature or the external 2 temperature is less than this voltage,
then the discharge FET is turned off and the DOT bit is set. The voltage is based
on recommended external components (see Figure 27 on page 35).
Reserved
DOTSB DOTSA DOTS9 DOTS8 DOTS7 DOTS6 DOTS5 DOTS4 DOTS3 DOTS2 DOTS1 DOTS0
3A
3B
Discharge Over-Temperature Recovery Voltage
Default (Hex): 053E
(mV): 0.590
(°C): +50
If external 1 temperature or the external 2 temperature rise above this setting,
then the discharge FET is turned on and the DOT bit is reset (unless overrides are
in place). The voltage is based on recommended external components (see
Figure 27 on page 35).
Reserved
DOTRB DOTRA DOTR9 DOTR8 DOTR7 DOTR6 DOTR5 DOTR4 DOTR3 DOTR2 DOTR1 DOTR0
3C
3D
Discharge Under-Temperature Voltage
Default (Hex): 0BF2
(mV): 1.344
(°C): -10
If external 1 temperature or the external 2 temperature is greater than this
voltage, then the discharge FET is turned off and the DUT bit is set. The voltage
is based on recommended external components (see Figure 27 on page 35).
Reserved
DUTSB DUTSA DUTS9 DUTS8 DUTS7 DUTS6 DUTS5 DUTS4 DUTS3 DUTS2 DUTS1 DUTS0
3E
3F
Discharge Under-Temperature Recovery Voltage
Default (Hex): 0A93
(mV): 1.190
(°C): +5
If external 1 temperature or the external 2 temperature fall below this setting,
then the discharge FET is turned on and the DUT bit is reset (unless overrides are
in place). The voltage is based on recommended external components (see
Figure 27 on page 35).
Reserved
DUTRB DUTRA DUTR9 DUTR8 DUTR7 DUTR6 DUTR5 DUTR4 DUTR3 DUTR2 DUTR1 DUTR0
40
41
Internal Over-Temperature Voltage
If the internal temperature is greater than this voltage, then all FETs are turned
off and the IOT bit is set.
Default (Hex): 67CH
(mV): 0.73
(°C): +115
Reserved
IOTS
B
IOTS IOTS 9 IOTS 8 IOTS 7 IOTS 6 IOTS 5 IOTS 4 IOTS 3 IOTS 2 IOTS 1 IOTS 0
A
42
43
Internal Over-Temperature Recovery Voltage
When the internal temperature voltage drops below this level, then the FETs can
be turned on again and the IOT bit is reset on the next µC read.
Default (Hex): 621H
(mV): 0.69
(°C): +95
Reserved
IOTR
B
IOTR IOTR 9 IOTR 8 IOTR 7 IOTR 6 IOTR 5 IOTR 4 IOTR 3 IOTR 2 IOTR 1 IOTR 0
A
FN7626 Rev 5.00
February 17, 2016
Page 54 of 64
ISL94203
TABLE 14. EEPROM REGISTER DETAIL (Continued)
BIT/
ADDR
F
7
E
6
D
5
C
4
B
3
A
2
9
1
8
0
7
6
5
4
3
2
1
0
44
45
Sleep Level Voltage
If any cell voltage is below this threshold voltage for a sleep delay time, the
device goes into the Sleep mode.
Default (Hex): 06AA
(V): 2.0
Reserved
SLLB
SLLA
SLL 9 SLL 8 SLL 7 SLL 6 SLL 5 SLL 4 SLL 3 SLL 2 SLL 1 SLL 0
46
47
Sleep Delay Timer/Watchdog Timer
Sleep Delay
Default (Hex): FC0F
Sleep
WDT
(s)
(s)
1
31
This value sets the time that is required for any cell to be below the sleep voltage
threshold before the device enters the Sleep mode. Lower 10 bits sets the time.
Upper 1 bit sets the time base.
Watchdog Timer (WDT)
Time allowed the microcontroller between
2
I C slave byte writes to the ISL94203 after
setting any override bit.
WDT4 WDT3 WDT2 WDT1
0 to 31 seconds
WDT0
SLTA
SLT9
SLT8
SLT7
SLT6
SLT5
SLT4
SLT3
SLT2
SLT1
SLT0
00 = µs
01 = ms
10 = s
0 to 511
11 = min
48
49
Sleep Mode Timer/Cell Configuration
Mode Timer
Time required to enter Sleep mode from the Doze mode when no current is
detected.
Default (Hex): 83FF
Idle/
Doze:
Sleep
Mode
(min)
(min) 240
Cells
16
3
Cell Configuration
Only these combinations are acceptable. Any other combination will
prevent any FET from turning on.
CELL8 CELL7 CELL6 CELL5 CELL4 CELL3 CELL2 CELL1 MOD7 MOD6 MOD5 MOD4 MOD3 MOD2 MOD1 MOD0
8 7 6 5 4 3 2 1
1 0 0 0 0 0 1 1
1 1 0 0 0 0 1 1
1 1 0 0 0 1 1 1
1 1 1 0 0 1 1 1
1 1 1 0 1 1 1 1
1 1 1 1 1 1 1 1
NUMBER OF CELLS
3 Cells connected
4 Cells connected
5 Cells connected
6 Cells connected
7 Cells connected
8 Cells connected
Idle and Doze Mode:
Sleep Mode
[MOD3:0] = 0 to 16 Minutes
[MOD7:0] = 0 to 240 Minutes
Example:
Value = 0101 1010
Idle/Doze = 10 minutes
Sleep = 90 minutes
FN7626 Rev 5.00
February 17, 2016
Page 55 of 64
ISL94203
TABLE 15. EEPROM REGISTER DETAIL (FEATURE CONTROLS)
BIT/
ADDR
7
6
5
4
3
2
1
0
4A
CFPSD
CELLF PSD
Reserved
XT2M
TGain
CASC
Two Devices
Cascaded
PCFETE
Precharge FET
Enable
DOWD
Disable
Open-Wire Scan
OWPSD
Open-Wire PSD
xTemp 2 Mode External Temp
Control Gain
1 =
1 =
Activates PSD
output when a
“Cell Fail”
condition
occurs.
1 =
xT2 monitors
1=
Gain of iT, xT1
1 =
The device is
1 =
1 =
Responds
automatically to
Precharge FET Disable the
FET temp. Cell and xT2 inputs is cascaded with output turns on input open-wire the input Open
balance outputs 1x.
are not shut off 0 =
another device. instead of the
As such, the cell CFET output
detection scan Wire condition
0 = AND sets PSD.
0 =
when xT2
temperature
exceeds Cell
Balance limits
0 =
xT2 monitors
cell temp.
(Normal
Gain of iT, xT1
and xT2 inputs is is disabled.
2x. 0 =
balancefunction when any of the Enable the input 0 =
Does NOT
activate PSD
output when a
cell fails
condition
occurs.
cell voltages are open-wire
Responds
below the under detection scan automatically to
There is only one the LVCHG
device in the
system.
the input Open
Wire condition
and DOES NOT
set PSD.
threshold.
0=
Precharge FET is
not used
operation.)
4B
CBDD
CB during
Discharge
CBDC
CB during
Charge
DFODUV
DFET on during CFET on during
UV (Charging) OV (Discharging) Power-Down
CFODOV
UVLOPD
Enable UVLO
Reserved
Reserved
CB_EOC
Enable CBAL
during EOC
1 =
Do balance
1 =
Do balance
1 =
1 =
1 =
The device
1=
Keep DFET on
Keep CFET on
Cell balance
occurs during
EOC condition
regardless of
current
during discharge during charge
0 =
while the pack is while the pack is powers down
charging, discharging, when detecting
regardlessofthe regardlessofthe an UVLO
cell voltage. This cell voltage. This condition.
minimizes DFET minimizes CFET 0 =
No balance
0 =
during discharge No balance
When both
during charge
direction.
CBDD and CBDC
equal “0”, cell
balance is
power
dissipation
power
dissipation
When a UVLO
condition is
0 =
When both
Cell balance
turns off during
EOC if there is no
current flowing.
CBDD and CBDC during UV, when during OV, when detected, the
turned off.
equal “0”, cell
balance is
turned off.
the pack is
charging
0 =
the pack is
discharging
0 =
device remains
powered.
Normal DFET
operation.
Normal CFET
operation.
4C
4F
Reserved
50
57
User EEPROM
Available to the user (Note: There is no shadow memory associated with these registers).
FN7626 Rev 5.00
February 17, 2016
Page 56 of 64
ISL94203
Registers: Detailed (RAM)
TABLE 16. RAM REGISTER DETAIL (STATUS AND CONTROL)
BIT/
ADDR
7
6
5
4
3
2
1
0
80
(Read
only)
CUT
Charge
Under-Temp
COT
Charge
Over-Temp
DUT
Discharge
Under-Temp
DOT
Discharge
Over-Temp
UVLO
Undervoltage
Lockout
UV
OVLO
Overvoltage
Lockout
OV
Undervoltage
Overvoltage
These An external
bits are thermistor
set and shows the temp shows the
An external
thermistor
An external
thermistor
An external
thermistor
At least one cell At least one cell At least one cell At least one cell
is below the
has an
is above the
overvoltage
lockout
has an
shows the temp shows the temp undervoltage
undervoltage
condition.
overvoltage
condition.
reset by is lower than the temp is higher is lower than the is higher than
lockout
the
minimum
than the
maximum
charge temp
limit.
minimum
discharge temp discharge temp
limit. limit.
the maximum
threshold.
threshold.
device. charge temp
limit.
81
EOCHG
Reserved
OPEN
CELLF
DSC
DOC
COC
IOT
(Read
only)
End of charge
Open wire
Cell Fail
Discharge
Short-Circuit
Discharge
Overcurrent
Charge
Overcurrent
Internal
Over-Temp
These End of charge
bits are voltage reached.
set and
reset by
the
An open input
circuit is
detected.
Indicates that
there is more
than the
maximum
allowable
Short-circuit
current
detected.
Excessive
Discharge
current
Excessive
Charge current sensor indicates
detected.
The internal
an
detected.
over-temperature
condition.
device
voltage
difference
between cells.
82
(Read
only)
LVCHG
Low Voltage
Charge
INT_SCAN
Internal Scan
In-Progress
ECC_FAIL
EEPROM Error
Correct Fail
ECC_USED
EEPROM Error
Correct
DCHING
Discharging
CHING
Charging
CH_PRSNT
Chrgr Present
LD_PRSNT
Load Present
Indicates that a Indicates that a Set to “1” during Set to “1” during
These At least one cell When this bit is EEPROM error
bits are voltage < LVCHG “0” for the correction
set and threshold. If set, duration of the failed. Two bits One bit failed,
reset by PCFET turns on internal scan. failed, error not bit error
EEPROM error
correction used. current is
detected.
discharge
charge current COC, while
is detected. charger is
Charge current attached.
DOC or DSC, while
load attached.
(LDMON <
threshold.)
If µCCMON = “0”,
Charge current is flowing into
is flowing out of the pack.
the pack.
(CHMON >
threshold.)
If µCLMON= “0”, bit resets
the
instead of CFET.
corrected.
corrected.
device
Previous value
retained.
bit resets
automatically. If
automatically. If µCCMON = “1”,
µCLMON = “1”, bit resets by µC
bit resets by µC read of register.
read of register.
83
Reserved
IN_SLEEP
IN_DOZE
IN_IDLE
CBUV
CBOV
CBUT
CBOT
(Read
only)
In Sleep Mode In Doze mode
In Idle Mode
Cell Balance
Undervoltage
Cell Balance
Overvoltage
Cell Balance
Under-Temp
Cell Balance
Over-Temp
No scans. RGO Scans every
Scans every
256ms
These
bits are
set and
reset by
the
remains on,
VREF off.
512ms.
All cell voltages All cell voltages xT1 or xT2
< the minimum > the maximum indicatestemp < indicates temp >
xT1 or xT2
Monitors for a
charger or load
connection.
allowable cell
allowable cell
allowable cell
allowable cell
balance high
temperature
threshold
balance voltage balance voltage balance low
threshold.
threshold.
temperature
threshold
device
84
Cell balance FET control bits
(R/W) These bits control the cell balance when the external controller
overrides the internal cell balance operation.
CB8ON
CB7ON
CB6ON
CB5ON
CB4ON
CB3ON
CB2ON
CB1ON
If µCCBAL = 1, CBAL_ON = 1 and CBnON bit = 1 the cell balance FET is on.
If µCCBAL = 0, CBAL_ON = 0 or CBnON bit = 0 the cell balance FET is off.
FN7626 Rev 5.00
February 17, 2016
Page 57 of 64
ISL94203
TABLE 16. RAM REGISTER DETAIL (STATUS AND CONTROL) (Continued)
BIT/
ADDR
7
6
5
4
3
2
1
0
85
Analog MUX control bits
(R/W) Voltage monitored by ADC when microcontroller overrides the internal
scan operation.
Current Gain Setting
Current gain set when current is monitored by ADC. Only used when
microcontroller overrides the internal scan.
ADC Conversion Start
Reserved
ADCSTRT
CG1
CG0
AO3
AO2
AO1
AO0
Ext µC sets this
bit to 1 to start
a conversion
CG1 0 Gain
0 0 x50
0 1 x5
1 0 x500
1 1 x500
AO3 2 1 0
0 0 0 0 OFF
AO3 2 1 0
1 0 0 0 VC8
1 0 0 1 Pack current
1 0 1 0 VBAT/16
1 0 1 1 RGO/2
1 1 0 0 xT1
1 1 0 1 xT2
1 1 1 0 iT
1 1 1 1 OFF
0 0 0 1 VC1
0 0 1 0 VC2
0 0 1 1 VC3
0 1 0 0 VC4
0 1 0 1 VC5
0 1 1 0 VC6
0 1 1 1 VC7
86
CLR_LERR
LMON_EN
CLR_ERR
Clear charge
error
CMON_EN
PSD
PCFET
CFET
Charge FET
DFET
Discharge FET
(R/W) Clear load error Load monitor
enable
Charge monitor Pack shut down Pre-charge FET
enable
1 = PSD on
0 = PSD off
1 = PCFET on
0 = PCFET off
Bit = 0 if DOC or 0 = CFET off
DSC, unless the Bit = 0 if COC,
automatic
response is
disabled by
µCFET bit. (28) disabled by
µCFET bit. (28)
1 = DFET on
0 = DFET off
Bit = 0 if DOC or
DSC unless the
automatic
response is
disabled by
µCFET bit. (28)
1 = Resets load
monitor error
condition.
This bit is
automatically
cleared.
1 = Charger
monitor on
charge monitor 0 = Charger
1 = CFET on
1 = Load
monitor on
0 = Load
1 = Resets
error condition. monitor off. Only
unless the
automatic
response is
monitor off
This bit is
automatically
cleared.
active when
µCCMON = 1
Onlyactivewhen
µCCMON = 1
Only active
Onlyactivewhen
when µCLMON µCCMON = 1
= 1
87
(R/W)
Reserved
µCFET
µC does FET
control
µCCBAL
µC does cell
balance
µCLMON
µCCMON
µCSCAN
OW_STRT
CBAL_ON
µC does load µC does charger µC does scan Open wire start Cell balance On
monitor
mon
1 = No auto
1 = Does one
1= (CBnON =1)
1 = FETs
1 = Internal
balance
disabled. µC
manages cell
1 = Load
1 = Charge
monitor on
0 = Charge
monitor off
(31)
scan. System
controlled by µC. (bit auto reset to 0= Cell bal
0 = Normal scan 0) outputs OFF
open-wire scan outputs ON
controlled by
external µC.
0 = Norm
automatic FET balance
control (31),
(34)
monitor on
0 = Load
monitor off
(31)
(31), (3333)
0 = No scan Only Only active if
active if DOWD = µCCBAL= 1.
1 or µCSCAN = 1
0=internal
balance
enabled. (31)
88
Reserved
Reserved
Reserved
Reserved
PDWN
SLEEP
DOZE
IDLE
(R/W)
Power-Down
Set Sleep
Set Doze
Set Idle
1 = Power-down 1 = Put device 1 = Put device 1 = Put device
the device.
0 = Normal
operation
into Sleep
mode.
0 = Normal
operation
into Doze mode. into Idle
0 = Normal
operation
mode 0 = Normal
operation.
89
EEPROM Enable
(R/W)
EEEN
Reserved. These bits should be zero.
0 = RAM access
1 = EEPROM
access
FN7626 Rev 5.00
February 17, 2016
Page 58 of 64
ISL94203
TABLE 17. RAM REGISTER DETAIL (MONITORED VOLTAGES)
BIT/
ADDR
F
7
E
6
D
5
C
4
B
3
A
2
9
1
8
0
7
6
5
4
3
2
1
0
8A
8B
Cell Minimum Voltage
This is the voltage of the cell with the minimum voltage.
HEXvalue 1.8 8
10
-----------------------------------------------------------
4095 3
Reserved
CELLMI CELLMI CELLMI CELLMI CELLMI CELLMI CELLMI CELLMI CELLMI CELLMI CELLMI CELLMI
NB NA N9 N8 N7 N6 N5 N4 N3 N2 N1 N0
8C
8D
Cell Maximum Voltage
This is the voltage of the cell with the maximum voltage.
HEXvalue 1.8 8
10
-----------------------------------------------------------
4095 3
Reserved
CELLM CELLM CELLM CELLM CELLM CELLM CELLM CELLM CELLM CELLM CELLM CELLM
AXB
AXA
AX9
AX8
AX7
AX6
AX5
AX4
AX3
AX2
AX1
AX0
8E
8F
Pack Current
This is the current flowing into or out of the pack.
HEXvalue 1.8
10
4095 Gain SenseR
---------------------------------------------------------
Polarity
identified by CHING and DCHING bits.
Reserved
Cell 1 Voltage
ISNSB ISNSA ISNS9 ISNS8 ISNS7 ISNS6 ISNS5 ISNS4 ISNS3 ISNS2 ISNS1 ISNS0
90
91
HEXvalue 1.8 8
10
This is the voltage of CELL1.
-----------------------------------------------------------
4095 3
Reserved
CELL1 CELL1 CELL1 CELL1 CELL1 CELL1 CELL1 CELL1 CELL1 CELL1 CELL1 CELL1
B
A
9
8
7
6
5
4
3
2
1
0
92
93
Cell 2 Voltage
This is the voltage of CELL2.
HEXvalue 1.8 8
10
-----------------------------------------------------------
4095 3
Reserved
CELL2 CELL2 CELL2 CELL2 CELL2 CELL2 CELL2 CELL2 CELL2 CELL2 CELL2 CELL2
B
A
9
8
7
6
5
4
3
2
1
0
94
95
Cell 3 Voltage
This is the voltage of CELL3.
HEXvalue 1.8 8
10
-----------------------------------------------------------
4095 3
Reserved
CELL3 CELL3 CELL3 CELL3 CELL3 CELL3 CELL3 CELL3 CELL3 CELL3 CELL3 CELL3
B
A
9
8
7
6
5
4
3
2
1
0
96
97
Cell 4 Voltage
This is the voltage of CELL4.
HEXvalue 1.8 8
10
-----------------------------------------------------------
4095 3
Reserved
CELL4 CELL4 CELL4 CELL4 CELL4 CELL4 CELL4 CELL4 CELL4 CELL4 CELL4 CELL4
B
A
9
8
7
6
5
4
3
2
1
0
98
99
Cell 5 Voltage
This is the voltage of CELL5.
HEXvalue 1.8 8
10
-----------------------------------------------------------
4095 3
Reserved
CELL5 CELL5 CELL5 CELL5 CELL5 CELL5 CELL5 CELL5 CELL5 CELL5 CELL5 CELL5
B
A
9
8
7
6
5
4
3
2
1
0
9A
9B
Cell 6 Voltage
This is the voltage of CELL6.
HEXvalue 1.8 8
10
-----------------------------------------------------------
4095 3
Reserved
CELL6 CELL6 CELL6 CELL6 CELL6 CELL6 CELL6 CELL6 CELL6 CELL6 CELL6 CELL6
B
A
9
8
7
6
5
4
3
2
1
0
FN7626 Rev 5.00
February 17, 2016
Page 59 of 64
ISL94203
TABLE 17. RAM REGISTER DETAIL (MONITORED VOLTAGES) (Continued)
BIT/
ADDR
F
7
E
6
D
5
C
4
B
3
A
2
9
1
8
0
7
6
5
4
3
2
1
0
9C
9D
Cell 7 Voltage
HEXvalue 1.8 8
10
This is the voltage of CELL7.
Reserved
-----------------------------------------------------------
4095 3
CELL7 CELL7 CELL7 CELL7 CELL7 CELL7 CELL7 CELL74 CELL7 CELL7 CELL7 CELL7
B
A
9
8
7
6
5
3
2
1
0
9E
9F
Cell 8 Voltage
This is the voltage of CELL8.
HEXvalue 1.8 8
10
-----------------------------------------------------------
4095 3
Reserved
CELL8 CELL8 CELL8 CELL8 CELL8 CELL8 CELL8 CELL8 CELL8 CELL8 CELL8 CELL8
B
A
9
8
7
6
5
4
3
2
1
0
A0
A1
Internal Temperature
This is the voltage reported by the ISL94203 internal temperature sensor.
HEXvalue 1.8
10
--------------------------------------------------
4095
Reserved
iTB
iTA
iT9
iT8
iT7
iT6
iT5
iT4
iT3
iT2
iT1
iT0
A2
A3
External 1 Temperature
This is the voltage reported by an external thermistor divider on the xT1 pin.
HEXvalue 1.8
10
--------------------------------------------------
4095
Reserved
xT1B
xT1A
xT19
xT18
xT17
xT16
xT26
VB6
xT15
xT14
xT13
xT12
xT22
VB2
xT11
xT21
VB1
xT10
xT20
VB0
A4
A5
External 2 Temperature
This is the voltage reported by an external thermistor divider on the xT2 pin.
HEXvalue 1.8
10
--------------------------------------------------
4095
Reserved
VBATT Voltage
xT2B
xT2A
xT29
xT28
xT27
xT25
xT24
xT23
A6
A7
HEXvalue 1.8 32
10
This is the voltage of Pack.
---------------------------------------------------------------
4095
Reserved
VBB
VBA
VB9
VB8
VB7
VB5
VB4
VB3
A8
A9
VRGO Voltage
This is the voltage of ISL94203 2.5V regulator.
HEXvalue 1.8 2
10
-----------------------------------------------------------
4095
Reserved
RGOB RGOA RGO 9 RGO 8 RGO 7 RGO 6 RGO 5 RGO 4 RGO 3 RGO 2 RGO 1 RGO 0
FN7626 Rev 5.00
February 17, 2016
Page 60 of 64
ISL94203
TABLE 17. RAM REGISTER DETAIL (MONITORED VOLTAGES) (Continued)
BIT/
ADDR
F
7
E
6
D
5
C
4
B
3
A
2
9
1
8
0
7
6
5
4
3
2
1
0
AA
AB
14-Bit ADC Voltage
HEXvalue – 16384 1.8
10
This is the calibrated voltage out of the ISL94203 ADC. In normal scan mode,
this value is not usable, because it cannot be associated with a specific
monitored voltage. However, when the µC takes over the scan operations, this
value can be useful. This is a 2’s complement number.
----------------------------------------------------------------------------------------
ifHEXvalue 8191
10
8191
HEXvalue 1.8
10
--------------------------------------------
else
8191
Reserved
ADC
D
ADC
C
ADC
B
ADC
A
ADC
9
ADC
8
ADC
7
ADC
6
ADC
5
ADC
4
ADC
3
ADC
2
ADC
1
ADC
0
NOTES:
25. A “1” written to a control or configuration bit causes the action to be taken. A “1” read from a status bit indicates that the condition exists.
26. “Reserved” indicates that the bit or register is reserved for future expansion. When writing to RAM addresses, write a reserved bit with the value
“0”. Do not write to reserved registers at addresses 4CH through 4FH, 58H through 7FH or ACH through FFH. Ignore reserved bits that are returned
in a read operation.
27. The IN_SLEEP bit is cleared on initial power up, by the CHMON pin going high or by the LDMON pin going low.
28. When the automatic responses are enabled, these bits are automatically set and reset by hardware when any conditions indicate. When automatic
2
responses are over-ridden, an external microcontroller I C write operation controls the respective FET and a read of the register returns the current
state of the FET drive output circuit (though not the actual voltage at the output pin).
29. Setting EEEN to 0 prior to a read or write to the EEPROM area results in a read or write to the shadow memory. Setting EEEN to “1” prior to a read
or write from the EEPROM area results in a read or write from the non-volatile array locations.
30. Writes to EEPROM registers require that the EEEN bit be set to “1” and all other bits in EEPROM enable register set to “0” prior to the write operation.
31. This bit is reset when the Watchdog timer is active and expires.
2
32. The memory is configured as 8 pages of 16 bytes. The I C can perform a “page write” to write all values on one page in a single cycle.
33. Setting this bit to “1” disables all internal voltage and temperature scans. When set to “1”, the external µC needs to process all overvoltage,
undervoltage, over-temp, under temp and all cell balance operations.
34. Short-Circuit, Open Wire, Internal Over Temperature, OVLO and UVLO faults, plus Sleep and FETSOFF conditions override the µCFET control bit and
automatically force the appropriate power FETs off.
FN7626 Rev 5.00
February 17, 2016
Page 61 of 64
ISL94203
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Revision.
DATE
REVISION
FN7626.5
CHANGE
February 17, 2016
Added Related Literature section on page 1.
Added ISL94203IRTZ-T7A to the Ordering Information table on page 4.
Updated Figure 2 on page 7.
Updated Figure 26 on page 34.
Updated Figure 29 on page 40.
Added “EEPROM Access” on page 48.
Added “EEPROM Write” on page 48.
Updated “EEPROM Read” on page 48.
Updated “Synchronizing Microcontroller Operations with Internal Scan” on page 48.
Updated Table 15 “82 (Read only)” on page 57.
August 17, 2015
FN7626.4
FN7626.3
Ordering Information table, page 4: Changed ISL94203EVAL1Z to ISL94203EVKIT1Z
February 11, 2015
-Updated datasheet applying Intersil’s standards.
-Added RC circuit to VBATT in Figure 1 on page 1.
-Moved Table of Contents to page 2.
-In the “Pin Descriptions” on page 5 for FETSOFF, add the statement, “This pin should be pulled low when
inactive.”
-Updated VBATT Pin Description on page 6.
-Electrical Specifications, page 8, IVBATT, removed "leakage" from Test Condition.
-Absolute Maximum Ratings, page 8. Updated ESD Ratings standard revision for HBM to JESD22-A114F
and replaced Machine Model ratings with Charge Device Model, per current JEDEC standards.
-In Figures 2, 12, 13 and 30: changed the VBATT series R to 100Ω and VBATT cap to ground to 470nF and
the VCn cap to ground to 47nF.
-Updated Figure 4 on page 16 to show response if LDMON and CHMON are active when device enters
Sleep.
-Updated Figure 7 on page 17 to show charge pump timing relative to FET turn on/off and corrected the
turn on delay time.
-Added INT_SCAN bit in RAM location 0x82 in Table 16 on page 57. The addition of the bit is not a change
to the device. This bit and descriptions about its use, are provided to make use of a previously
undocumented feature.
-Added INT_SCAN bit to Figure 23 on page 31.
-Moved Sections “PC Board Layout” and “QFN Package” to precede Section “EEPROM” on page 44.
-“PC Board Layout” on page 43, fourth bullet, changed “PCB” to “ground plane” and added new bullet
“VDD bypass and charge pump capacitors should use wide temperature and high frequency dielectric
(X7R or better) and it is recommended that the rated voltage be 2X the maximum operating voltage.”
Added a second new bullet, “The charge pump and VDD bypass capacitors should be located close to the
ISL94203 pins and VDD should have a good ground connection.” Added a third new bullet, “An example
PCB layout...” along with a new figure, Figure 33.
-In Figure 2, added a pull-down resistor on FETSOFF.
-In Equations 1 and 2 on page 35, Reversed the TGain values. Now, Equation 1 is for TGain = 1 and
Equation 2 is for TGain = 0.
-On page 38, in “Cell Balance” section updated the 7th bullet by changing from “If CELMAX is below
CBUV” to “If CELMAX is below CBMIN” and "(CBUV + 117mV)” to “(CBMIN + 117mV)”.
-On page 39 in section updated the 8th bullet by changing from “If the CELMIN voltage is greater than the
CBOV voltage” to “If the CELMIN voltage is greater than the CBMAX voltage” and “[CBOV - 117mV]” to
“(CBMAX - 117mV)”.
-In Table 11 on page 42, updated Row1, Column 3 to read “32kHz 5mA pulses, 50% duty cycle” and Row
3, the Power FET turn-off current was changed from “20mA” to “13mA (CFET, PCFET) and 15mA (DFET)”.
-On page 52, CBMIN: Changed “If any cell is less than this voltage” to “If all cell voltages are less than this
voltage”.
-On Page 52, CBMAX: Changed “If any cell is greater than this voltage” to “If all cell voltages are greater
than this voltage”.
-In Table 16 on page 57, the description for COC is changed to read, “Excessive Charge current detected”
and change DOC to read “Excessive Discharge current detected.”
-Updated the About Intersil verbiage
-Updated POD from revision 1 to revision 2 changes are as follows:
“added tolerance ± values”
December 5, 2012
FN7626.2
Initial Release.
FN7626 Rev 5.00
February 17, 2016
Page 62 of 64
ISL94203
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
© Copyright Intersil Americas LLC 2012-2016. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7626 Rev 5.00
February 17, 2016
Page 63 of 64
ISL94203
Package Outline Drawing
L48.6x6
48 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 7/14
4X
4.4
6.00± 0.05
A
0.40
44X
6
B
PIN #1 INDEX AREA
48
37
6
1
36
PIN 1
INDEX AREA
4 .40 ± 0.15
25
12
0.15
(4X)
13
24
0.10 M C A B
C
0.05 M
TOP VIEW
48X 0.45 ± 0.10
4
48X 0.20
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
C
MAX 0.80
BASE PLANE
SEATING PLANE
0.08
(44 X 0.40)
( 5. 75 TYP)
(
C
SIDE VIEW
4. 40)
5
0 . 2 REF
C
(48X 0 . 20)
(48X 0 . 65)
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance: Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN7626 Rev 5.00
February 17, 2016
Page 64 of 64
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