ISL88021IU8HCZ-TK [RENESAS]
1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8, ROHS COMPLIANT, PLASTIC, MO-187AA, MSOP-8;
| 型号： | ISL88021IU8HCZ-TK |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8, ROHS COMPLIANT, PLASTIC, MO-187AA, MSOP-8 光电二极管 |
| 文件： | 总7页 (文件大小：189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL88021, ISL88022
®
Data Sheet
September 18, 2006
FN8226.1
Triple Voltage Monitor with Adjustable
Power-On-Reset and Undervoltage/
Overvoltage Monitoring Capability
Features
• Triple Voltage Monitor and Reset Assertion
• Low V
DD
Detection and Reset Assertion
The ISL88021 and ISL88022 family of devices are
customizable triple voltage-monitoring supervisors that
assert a reset if any of the monitored voltages becomes
non-compliant. They offer popular functions such as
Power-On-Reset timing control with both RESET and
RESET outputs, Supply Voltage Supervision, both under or
overvoltage detection, and Manual Reset assertion. By
offering these features in a small 8 Ld MSOP package, the
ISL88021 and ISL88022 can lower system cost, reduce
board space requirements and increase the reliability of
systems.
- Adjustable Reset Threshold Voltages
- 0.6V ±6mV Over -40°C to +85°C
- Reset Signal Valid to V
DD
= 1V
• 140ms Minimum Reset Pulse Delay that is Customizable
Using an External Capacitor
• Both RST and RST Outputs Available
• Undervoltage/Overvoltage Monitoring Capability
• Low 20µA Consumption
• Small 8 Ld MSOP Package
Applying a voltage to V
activates the Power-On-Reset
DD
• Pb-Free Plus Anneal Available (RoHS Compliant)
circuit which holds RESET low for an adjustable period of
time. This allows the power supply and system oscillator to
stabilize before the processor can execute code.
Applications
• Process Control Systems
• Intelligent Instruments
• Embedded Control Systems
• Computer Systems
Low V
detection circuitry protects the user’s system from
DD
low voltage conditions, resetting the system when V
falls
DD
below its minimum preset voltage threshold V
remains asserted until V
level and stabilizes. Two additional voltage monitoring
inputs, V2MON (preset) and V3MON (adjustable), monitor
other supplies to provide reliable system operation.
. Reset
TH1
returns to its proper operating
DD
• Portable/Battery-Powered Equipment
• Multi-Voltage Systems
The ISL88021 V3MON input monitors for undervoltage (UV)
conditions whereas the ISL88022 V3MON input allows
monitoring for overvoltage (OV) conditions. The monitored
voltage on V3MON on either device is compared via a
resistor divider to a 600mV internal reference. Hence, any
voltage more or less positive than this reference can be
accurately monitored to meet specific system level
requirements or to fine-tune the threshold for applications
requiring higher precision.
Pinout
ISL88021, ISL88022
(8 LD MSOP)
TOP VIEW
8
7
6
1
MR
RST
RST
V
2
3
DD
V2MON
C
POR
These devices also let users increase the Power-On-Reset
time-out delay by connecting a capacitor between C
and
POR
5
GND
4
V3MON
ground. This lengthens the period of an internal clock
counter thereby increasing the time between voltage
compliance and reset outputs signaling.
A manual reset input provides debounce circuitry for
minimum reset component count.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL88021, ISL88022
Ordering Information (See Notes)
Ordering Information (See Notes) (Continued)
PART
NUMBER
PART
MARKING V
V
V2MO V3MON
PART
NUMBER
PART
MARKING V
V
V2MO V3MON
DD
DD
TRIP1 TRIP2
V
TYPE PACKAGE
V
TYPE PACKAGE
OV 8 Ld MSOP
OV 8 Ld MSOP
OV 8 Ld MSOP
OV 8 Ld MSOP
TRIP1 TRIP2
3.09V 1.69V
ISL88021IU8FAZ ANM
ISL88021IU8FCZ ANL
ISL88021IU8FEZ
UV
UV
UV
UV
UV
UV
UV
UV
8 Ld MSOP
8 Ld MSOP
8 Ld MSOP
8 Ld MSOP
8 Ld MSOP
8 Ld MSOP
8 Ld MSOP
8 Ld MSOP
ISL88022IU8HAZ
ISL88022IU8HCZ
ISL88022IU8HEZ ANO
ISL88022IU8HFZ ANN
NOTES:
4.64V 1.69V
4.64V 2.32V
4.64V 2.92V
4.64V 3.09V
3.09V 2.32V
3.09V 2.92V
3.09V 3.09V
4.64V 1.69V
4.64V 2.32V
4.64V 2.92V
4.64V 3.09V
3.09V 1.69V
3.09V 2.32V
3.09V 2.92V
3.09V 3.09V
ISL88021IU8FFZ
ISL88021IU8HAZ
1. Standard versions are shown in bold. For non-standard versions,
please contact factory for availability.
ISL88021IU8HCZ
ISL88021IU8HEZ ANK
ISL88021IU8HFZ ANJ
ISL88022IU8FAZ ANQ
ISL88022IU8FCZ ANP
ISL88022IU8FEZ
2. Add “-TK” suffix for Tape and Reel.
3. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
OV 8 Ld MSOP
OV 8 Ld MSOP
OV 8 Ld MSOP
OV 8 Ld MSOP
ISL88022IU8FFZ
Block Diagrams
V
V
DD
DD
RST
RST
RST
RST
POR
POR
V2MON
V3MON
V2MON
V3MON
C
C
POR
POR
MR
PB
MR
PB
V
V
REF
REF
±
±
GND
GND
ISL88022
ISL88021
Pin Descriptions
ISL88021
ISL88022
NAME
FUNCTION
1
2
3
4
5
1
2
3
4
MR
Active-Low Open Drain Manual Reset Input
Power Supply Input
V
DD
V2MON
GND
Second Undervoltage Monitor Input
Ground
V3MON
V3MON
Undervoltage Monitor Input
Overvoltage Monitor Input
5
6
7
8
6
7
8
C
Set Power-On-Reset Timeout Delay
Active-Low Open Drain Reset Output
Active-High Push-Pull Reset Output
POR
RST
RST
FN8226.1
September 18, 2006
2
ISL88021, ISL88022
Absolute Maximum Ratings
Thermal Information
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . -40 C to +85 C
Voltage on Any Pin with Respect to GND . . . . . . . . . . .-1.0V to +7V
D.C. Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Thermal Resistance (Typical, Note 1)
θ
(°C/W)
145
JA
MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(MSOP - Lead Tips Only)
Recommended Operating Conditions
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
Supply Voltage Range
Supply Current
TEST CONDITIONS
MIN
TYP
MAX
5.5
15
UNITS
V
V
2.0
DD
DD1
DD2
DDA
I
I
V
V
= 5.0V
DD
12.5
5.5
19
µA
DD
V2MON Input Current
V3MON Input Current
V2MON = 3.3V
V3MON = 1.0V
6
µA
I
100
nA
VOLTAGE THRESHOLDS
Fixed Voltage Trip Point for V
V
ISL88021/22IU8HxZ
ISL88021/22IU8FxZ
4.565
3.029
4.649
3.085
46
4.733
3.141
V
V
TH1
DD
V
Hysteresis of V
TH1
V
V
= 4.64V
= 3.09V
mV
mV
V
TH1HYST
TH1
TH1
37
V
Fixed Voltage Trip Point for V2MON
ISL88021/22IU8xFZ
ISL88021/22IU8xEZ
ISL88021/22IU8xCZ
ISL88021/22IU8xAZ
3.034
2.894
2.290
1.660
3.090
2.947
2.332
1.690
37
3.146
3.000
2.374
1.720
TH2
V
V
V
V
Hysteresis of V
TH2
V
V
V
V
V
V
V
= 3.09V
= 2.92V
= 2.32V
= 2.19V
= 1.69V
mV
mV
mV
mV
mV
V
TH2HYST
TH2
TH2
TH2
TH2
TH2
29
23
22
17
V
V3MON Threshold Voltage
Hysteresis Voltage
for V3MON on ISL88021
for V3MON on ISL88022
0.594
0.587
0.605
0.595
3
0.616
0.603
TH3
TH
TH
V
V
mV
REFHYST
RESET
V
Reset Output Voltage Low
RST Output Voltage High
V
V
V
V
≥ 3.3V, Sinking 2.5mA
< 3.3V, Sinking 1.5mA
≥ 3.3V, Sourcing 2.5mA
< 3.3V, Sourcing 1.5mA
0.05
0.05
0.40
0.40
V
V
OL
DD
DD
DD
DD
V
V
-0.6
V
-0.4
V
OH
DD
DD
DD
V
-0.6
V
-0.4
V
DD
t
V
to Reset Asserted Delay
TH
10
µs
ms
pF
RPD
POR
LOAD
t
POR Timeout Delay
C
is open
140
200
5
POR
C
Load Capacitance on Reset Pins
FN8226.1
September 18, 2006
3
ISL88021, ISL88022
Electrical Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
MANUAL RESET
V
MR Input Voltage Low
0.8
V
V
MRL
V
MR Input Voltage High
MR Minimum Pulse Width
Internal Pull-Up Resistor
V
-0.6
DD
MRH
t
550
ns
kΩ
MR
R
20
PU
Power-On-Reset (POR)
Functional Description
Applying power to the ISL88021 and ISL88022 devices
activates a POR circuit which holds the RESET pin low once
The ISL88021 and ISL88022 devices incorporate such features
as Power-On-Reset control, Supply Voltage Supervision,
Undervoltage or Overvoltage Monitoring, and Manual Reset
Assertion.
V
> 1V. This signal provides several benefits:
DD
• It prevents the system microprocessor from starting to
operate with insufficient voltage.
The ISL88021 and ISL88022 devices provide common preset
threshold voltages on both V
optional resistor divider network on V3MON to provide custom
voltage monitoring of voltages greater than 0.6V. An optional
capacitor can be connected between the C
increase the nominal 200ms t
POR
and V2MON and for an
• It prevents the processor from operating prior to
stabilization of the oscillator.
DD
• It ensures that the monitored device is held out of operation
until internal registers are properly loaded.
pin and GND to
delay. Figure 7 illustrates
POR
• It allows time for an FPGA to download its configuration prior
to initialization of the circuit.
operational functionality with a timing diagram.
Voltage Monitoring
During normal operation, the ISL88021 and ISL88022 monitor
When all of the monitored voltages meet their respective
input voltage requirements for the specified reset timeout
the voltage levels on V , V2MON and V3MON. The
DD
delay t
, the POR circuit simultaneously pulls the RST
POR
ISL88021 asserts reset if any one of these voltages fall below
their respective voltage trip points and in the case of ISL88022
above the voltage trip point on the V3MON input. The reset
signal effectively prevents the microprocessor from operating
during a power failure, brownout or over voltage condition. This
signal remains active until all monitored voltages meet all
voltage threshold requirements for the reset time delay period
output low and releases the RST output to allow the system
to begin operation.
Adjusting t
POR
On the ISL88021 and ISL88022, users can adjust the
Power-On-Reset timeout delay (t
) to many times the
POR
nominal t
. Figure 2 illustrates the effect of capacitance
POR
t
. Note that both RESET and RESET signals are provided
on the C
pin to ground, showing changing t
with a
POR
POR
POR
pin. The
for design flexibility. Figure 1 illustrates the VDD, V2MON and
V3MON input threshold voltages for the various available
options.
graph normalized to 175ms for an open C
POR
maximum recommended capacitance that should be placed
on the C pin is 50pF. NOTE: Care should be taken in
POR
PCB layout and capacitor placement in order to eliminate
stray capacitance as much as possible, which contributes to
5.000
t
error.
4.500
4.000
3.500
3.000
2.500
2.000
1.500
1.000
0.500
0.000
Vth = 4.64V
POR
Vth = 3.09V
Vth = 2.92V
Vth = 2.32V
Vth = 1.69V
10
8
6
4
Vth = 0.60V
2
-40
25
85
0
TEMPERATURE (°C)
1
5
9
13 17 21 25 29 33 37 41 45
FIGURE 1. VDD, V2MON, V3MON VTH vs TEMP
CPOR (pF)
FIGURE 2. NORMALIZED t
POR
vs C GRAPH
POR
FN8226.1
September 18, 2006
4
ISL88021, ISL88022
Manual Reset
The manual reset input (MR) allows the user to trigger a reset
by using a push-button switch or by signaling that pin low. The
MR input is an active low debounced input. By connecting a
push-button directly from MR to ground, the designer adds
manual system reset capability. Reset is asserted if the MR pin
is pulled low to less than 100mV for 1µs or longer while the
push-button is closed or a reset is signaled. After MR is
ISL88021IU8HFZ
released, the reset outputs remain asserted for t
. MR input
POR
has an internal 20kΩ pull up resistor provided.
Figure 3 illustrates a typical application diagram for either IC
showing both reset outputs being used along with both a
manual and signalled reset configuration. The V
and
DD
V2MON thresholds are preset whereas the V3MON is capable
of UV (ISL88021) or OV (ISL88022) monitoring of a voltage
greater than or less than 0.6V, respectively.
TO DISPLAY
3.3V - 5V
V
TO µP
DD
RST
RST
ISL88022IU8HFZ
V2MON
MR
1.8V - 3.3V
RESET
SIGNAL
ISL88021
ISL88022
PB
C
POR
V3MON
GND
V
> 0.6V
MON
FIGURE 3. TYPICAL APPLICATION DIAGRAM
Application Considerations
Follow good decoupling practices to prevent transients from
causing unwanted reset signaling due to switching noises
and short duration droops.
FIGURE 4. ISL88021_22EVAL1 SCHEMATIC AND PHOTO
When using the C
on this pin to minimize effect on t
POR
pin, reduce layout stray capacitance
timing. If no PCB
pad is patterned, the t can be 160ms.
POR
POR
MONITORED VOLTAGE RISING AND FALLING RAMP
THROUGH THE PROGRAMMED UV AND OV THRESHOLDS
C
POR
Using the ISL88021_22EVAL1 Platform
The ISL88021_22EVAL1 board is designed to provide both
immediate functional assessment and flexibility to the user.
Both ICs are the ‘HF’ variant having a V
Vth of 4.64V, a
DD
V2MON Vth of 3.09V and V3MON Vth of 0.6V. The top IC
position is the ISL88021 and is configured to monitor for
undervoltage (UV) compliance of a 5V, 3.3V and a 2.5V and
signaling the RESET and RESET outputs. The bottom
position is the ISL88022 variant, which is configured to
measure a 3.3V overvoltage (OV) in addition to UV on both
the 5V and 3.3V supplies. RESET and RESET is asserted for
RESET# RESPONDING TO
MONITORED VOLTAGE. C
POR
= 150ms
PIN IS OPEN, t
POR
at least t
when these voltage go out of range. In both
POR
cases V3MON interfaces with the monitored supply via a
simple resistor divider for comparison to the internal 0.6V
reference. A Manual Reset (MR) input is provided on both
ICs and is invoked by pulling this input LOW.
FIGURE 5. ISL88022EVAL1 3.3V UV AND OV DETECTION
FN8226.1
September 18, 2006
5
ISL88021, ISL88022
3.3V RISING EDGE 100ms/DIV
ISL88022 t
= 150ms
POR
= OPEN
C
POR
ISL88021 t
= 390ms
POR
C
= 10pF
POR
FIGURE 6. ISL88021_22EVAL1 t
COMPARISON
POR
Operational Timing Diagrams
V
TH1
V
DD
1V
V2MON or V3MON
(ISL88021)
V
or V
REF
TH2
>t
MR
MR
t
t
t
t
t
t
POR
POR
RPD
POR
RPD
POR
RST
RST
<t
MD
FIGURE 7. ISL88021 AND ISL88022 TIMING DIAGRAM
FN8226.1
September 18, 2006
6
ISL88021, ISL88022
Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
E1
E
SYMBOL
MIN
MAX
MIN
0.94
0.05
0.75
0.25
0.09
2.95
2.95
MAX
1.10
0.15
0.95
0.36
0.20
3.05
3.05
NOTES
A
A1
A2
b
0.037
0.002
0.030
0.010
0.004
0.116
0.116
0.043
0.006
0.037
0.014
0.008
0.120
0.120
-
-B-
0.20 (0.008)
INDEX
AREA
1 2
A
B
C
-
-
TOP VIEW
4X θ
9
0.25
(0.010)
R1
c
-
R
GAUGE
PLANE
D
3
E1
e
4
SEATING
PLANE
L
0.026 BSC
0.65 BSC
-
-C-
4X θ
L1
A
A2
E
0.187
0.016
0.199
0.028
4.75
0.40
5.05
0.70
-
L
6
SEATING
PLANE
L1
N
0.037 REF
0.95 REF
-
0.10 (0.004)
-A-
C
C
b
8
8
7
-H-
A1
e
R
0.003
0.003
-
-
0.07
0.07
-
-
-
D
0.20 (0.008)
C
R1
0
-
o
o
o
o
5
15
5
15
-
a
SIDE VIEW
C
L
o
o
o
o
0
6
0
6
-
α
E
1
-B-
Rev. 2 01/03
0.20 (0.008)
C
D
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
- H -
and are measured at Datum Plane.
Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
- B -
to be determined at Datum plane
-A -
10. Datums
and
.
- H -
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8226.1
September 18, 2006
7
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