ISL8499IRTZ [RENESAS]
Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Quad SPDT (Dual DPDT) Analog Switch; QFN16, TQFN16, TSSOP16; Temp Range: -40° to 85°C;
| 型号： | ISL8499IRTZ |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Quad SPDT (Dual DPDT) Analog Switch; QFN16, TQFN16, TSSOP16; Temp Range: -40° to 85°C 光电二极管 输出元件 |
| 文件： | 总14页 (文件大小：772K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL8499
FN6111
Rev 3.00
February 5, 2008
Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Quad SPDT (Dual
DPDT) Analog Switch
The Intersil ISL8499 device is a low ON-Resistance, low
voltage, bidirectional, Quad SPDT (Dual DPDT) analog
Features
• Drop in Replacement for the STG3699 and DG2799
switch designed to operate from a single +1.65V to +4.5V
supply. Targeted applications include battery powered
• ON-Resistance (r
)
ON
equipment that benefit from low r
(0.24 and fast
= 13ns). The digital logic
- V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.24
- V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.26
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.45
ON
switching speeds (t
= 15ns, t
ON
OFF
input is 1.8V logic-compatible when using a single +3V supply.
With a supply voltage of 4.2V and logic high voltage of 2.85V
at both logic inputs, the part draws only 10µA max of ICC
current.
• r
• r
Matching between Channels . . . . . . . . . . . . . . . . .0.04
Flatness Across Signal Range . . . . . . . . . . . . . . . .0.05
ON
ON
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This part may be used to “mux-in”
additional functionality while reducing ASIC design risk. The
ISL8499 is offered in small form factor packages, alleviating
board space limitations.
• Single Supply Operation. . . . . . . . . . . . . . . . +1.65V to +4.5V
• Low Power Consumption (PD). . . . . . . . . . . . . . . . . . <0.2µW
• Fast Switching Action (V+ = +4.3V)
- t
- t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns
ON
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13ns
OFF
• Guaranteed Break-Before-Make
The ISL8499 consists of four SPDT switches. It is configured
as a dual double-pole/double-throw (DPDT) device with two
logic control inputs that control two SPDT switches each. The
configuration can be used as a dual differential 2-to-1
multiplexer/demultiplexer. The ISL8499 is pin compatible with
the STG3699 and DG2799.
• 1.8V Logic Compatible (+3V supply)
• Low ICC Current when VinH is not at the V+ Rail
• Available in 16 Ld 3x3 TQFN, 16 Ld 3x3 QFN and
16 Ld TSSOP
• ESD HBM Rating
TABLE 1. FEATURES AT A GLANCE
- COM Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9kV
- All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV
-
Number of Switches
SW
ISL8499
4
Quad SPDT (Dual DPDT)
0.24
• Pb-Free Available (RoHS Compliant)
Applications
4.3V rON
• Battery Powered, Handheld, and Portable Equipment
- Cellular/Mobile Phones
4.3V t /t
ON OFF
15ns/13ns
0.26
3.0V rON
- Pagers
- Laptops, Notebooks, Palmtops
3.0V t /t
21ns/17ns
0.45
ON OFF
1.8V rON
1.8V t /t
• Portable Test and Measurement
• Medical Equipment
51ns/43ns
ON OFF
• Audio and Video Switching
Packages
16 Ld 3x3 TQFN, 16 Ld 3x3 QFN,
16 Ld TSSOP
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
FN6111 Rev 3.00
February 5, 2008
Page 1 of 14
ISL8499
Ordering Information
Pinouts (Note 1)
ISL8499
(16 LD QFN TSSOP)
TOP VIEW
TEMP.
RANGE
(°C)
PART
PKG.
DWG. #
PART NUMBER MARKING
PACKAGE
ISL8499IR
499I
499I
-40 to +85 16 Ld 3x3 QFN L16.3x3
NO1
COM1
NC1
1
2
3
4
5
6
7
8
16 V+
ISL8499IR-T*
-40 to +85 16 Ld 3x3 QFN L16.3x3
Tape and Reel
15 NC4
14 COM4
13 NO4
12 IN3-4
11 NC3
10 COM3
ISL8499IV
8499 IV
8499 IV
-40 to +85 16 Ld TSSOP
M16.173
M16.173
IN1-2
NO2
ISL8499IV-T*
-40 to +85 16 Ld TSSOP
Tape and Reel
COM2
NC2
ISL8499IRZ
(Note)
499Z
-40 to +85 16 Ld 3x3 QFN L16.3x3
(Pb-free)
9
NO3
GND
ISL8499IRZ-T* 499Z
(Note)
-40 to +85 16 Ld 3x3 QFN L16.3x3
Tape and Reel
(Pb-free)
ISL8499IVZ
(Note)
8499 IVZ -40 to +85 16 Ld TSSOP
(Pb-free)
M16.173
M16.173
ISL8499
(16 LD 3X3 TQFN, 3X3 QFN)
TOP VIEW
ISL8499IVZ-T*
(Note)
8499 IVZ -40 to +85 16 Ld TSSOP
Tape and Reel
(Pb-free)
ISL8499IRTZ
(Note)
99TZ
-40 to +85 16 Ld 3x3 TQFN L16.3x3A
(Pb-free)
16 15 14 13
NC1
IN1-2
NO2
COM4
NO4
1
2
3
4
12
11
10
9
ISL8499IRTZ-T* 99TZ
(Note)
-40 to +85 16 Ld 3x3 TQFN L16.3x3A
Tape and Reel
(Pb-free)
IN3-4
NC3
*Please refer to TB347 for details on reel specifications
COM2
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach materials
and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which
is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
5
6
7
8
NOTE:
1. Switches Shown for Logic “0” Input.
Truth Table
LOGIC
NC SW
ON
NO SW
0
1
OFF
ON
OFF
NOTE: Logic “0” 0.5V. Logic “1” 1.4V with a 3V supply.
Pin Descriptions
PIN
FUNCTION
System Power Supply Input (+1.65V to +4.5V)
Ground Connection
V+
GND
IN
Digital Control Input
COM
NO
Analog Switch Common Pin
Analog Switch Normally Open Pin
Analog Switch Normally Closed Pin
NC
FN6111 Rev 3.00
February 5, 2008
Page 2 of 14
ISL8499
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V
Input Voltages
NO, NC, IN (Note 2) . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Output Voltages
COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . 300mA
Peak Current NO, NC, or COM
Thermal Resistance (Typical, Note 3)
(°C/W)
(°C/W)
JC
JA
TQFN and QFN Package (Notes 4, 5).
TSSOP Package (Note 3) . . . . . . . . . .
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
70
150
10
N/A
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . 500mA
ESD Ratings:
Operating Conditions
HBM COM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>9kV
X
Temperature Range
ISL8499IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
HBM NO , NC , IN , V+, GND . . . . . . . . . . . . . . . . . . . . . . .>4kV
X
X
X
MM COM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V
X
MM NO , NC , IN , V+, GND . . . . . . . . . . . . . . . . . . . . . . .>300V
X
X
X
CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1kV
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
4. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
5. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications - 4.3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, V
Unless Otherwise Specified
= 1.6V, V
= 0.5V (Note 6),
INL
INH
TEMP
(°C)
MIN
(Notes 7, 8)
MAX
PARAMETER
TEST CONDITIONS
TYP
(Notes 7, 8) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ON-Resistance, rON
Full
25
0
-
V+
V
ANALOG
V+ = 3.9V, I
= 100mA, V
= 100mA, V
or V = 0V to V+,
NC
-
0.25
0.28
0.04
0.05
0.05
0.05
-
-
-
COM
(See Figure 5)
NO
Full
25
-
rON Matching Between Channels, V+ = 3.9V, I
rON
or V
= Voltage at
or V = 0V to V+,
NC
-
-
-
COM
max rON,(Note 11)
NO
NO
NC
Full
25
-
rON Flatness, R
V+ = 3.9V, I
(Note 9)
= 100mA, V
-
-
FLAT(ON)
COM
Full
25
-
-
NO or NC OFF Leakage Current,
or I
V+ = 4.5V, V
= 0.3V, 3V, V
or V
NO NC
= 3V, 0.3V
-50
-150
-50
-150
50
150
50
150
nA
nA
nA
nA
COM
I
NO(OFF)
NC(OFF)
Full
25
-
COM ON Leakage Current,
V = 4.5V, V
3V, or Floating
= 0.3V, 3V, or V
or V
= 0.3V,
NC
-
COM
NO
I
COM(ON)
Full
-
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 3.9V, V
or V
= 3.0V, R = 50,
25
Full
25
-
-
15
-
25
30
23
28
-
ns
ns
ns
ns
ns
ON
NO
NC
L
C
= 35pF, (See Figure 1, Note 10)
L
Turn-OFF Time, t
V+ = 3.9V, V
or V
= 3.0V, R = 50,
-
13
-
OFF
NO
NC
L
C
= 35pF, (See Figure 1, Note 10)
L
Full
Full
-
Break-Before-Make Time Delay, t
V+ = 4.5V, V
or V
= 3.0V, R = 50,
2
3
D
NO
NC
L
C
C
R
= 35pF, (See Figure 3, Note 10)
L
L
L
Charge Injection, Q
OFF Isolation
= 1.0nF, V = 0V, R = 0See Figure 2)
25
25
-
-
-120
68
-
-
pC
dB
G
G
= 50, C = 5pF, f = 100kHz, V
= 1V
,
,
L
COM
RMS
(See Figure 4)
Crosstalk (Channel-to-Channel)
R
= 50, C = 5pF, f = 100kHz, V
= 1V
25
-
-98
-
dB
L
L
COM
RMS
(See Figure 6)
FN6111 Rev 3.00
February 5, 2008
Page 3 of 14
ISL8499
Electrical Specifications - 4.3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, V
Unless Otherwise Specified (Continued)
= 1.6V, V
= 0.5V (Note 6),
INL
INH
TEMP
(°C)
MIN
(Notes 7, 8)
MAX
PARAMETER
TEST CONDITIONS
f = 20Hz to 20kHz, V = 2V , R = 600
TYP
0.003
106
(Notes 7, 8) UNITS
Total Harmonic Distortion
25
25
25
-
-
-
-
-
-
%
pF
pF
COM
PP
L
NO or NC OFF Capacitance, C
f = 1MHz, V
or V
or V
= V
= V
= 0V, (See Figure 7)
= 0V, (See Figure 7)
OFF
NO
NO
NC
NC
COM
COM
COM ON Capacitance, C
f = 1MHz, V
212
COM(ON)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Full
25
1.65
-
-
-
-
4.5
0.09
1.4
V
Positive Supply Current, I+
V+ = +4.5V, V = 0V or V+
IN
-
-
-
A
A
A
Full
25
Positive Supply Current, I+
V+ = +4.2V, V = 2.85V
IN
12
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
Full
Full
Full
-
-
-
-
0.5
-
V
V
INL
Input Voltage High, V
1.6
-0.5
INH
Input Current, I , I
INH INL
V+ = 4.5V, V = 0V or V+, (Note 10)
IN
0.5
A
NOTES:
6. V = input voltage to perform proper function.
IN
7. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
8. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
9. Flatness is defined as the difference between maximum and minimum value of ON-Resistance over the specified analog signal range.
10. Limits established by characterization and are not production tested.
11. r
ON
matching between channels is calculated by subtracting the channel with the highest max r
value from the channel with lowest max r
ON
ON
value, between NC1 and NC2, NC3 and NC4 or between NO1 and NO2, NO3 and NO4.
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V
Unless Otherwise Specified
= 1.4V, V
= 0.5V (Note 6),
INL
INH
TEMP
(°C)
MIN
(Notes 7, 8)
MAX
PARAMETER
TEST CONDITIONS
TYP
(Notes 7, 8) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
-
-
-
-
-
-
-
-
-
-
-
0.3
-
V+
0.45
0.6
0.08
0.09
0.15
0.15
-
V
ON-Resistance, r
V+ = 2.7V, I
= 100mA, V
or V
= 0V to V+,
= Voltage at
= 0V to V+,
ON
COM
(See Figure 5)
NO
NC
Full
25
r
Matching Between Channels,
V+ = 2.7V, I
COM
= 100mA, V
or V
0.04
-
ON
r
NO
NC
max r , (Note 11)
ON
ON
Full
25
r
Flatness, r
FLAT(ON)
V+ = 2.7V, I
(Note 9)
= 100mA, V
or V
NC
0.06
-
ON
COM
NO
Full
25
NO or NC OFF Leakage Current,
or I
V+ = 3.3V, V
= 0.3V, 3V, V
or V
NO NC
= 3V, 0.3V
1.2
13
1
nA
nA
nA
nA
COM
I
NO(OFF)
NC(OFF)
Full
25
-
COM ON Leakage Current,
V = 3.3V, V
3V, or Floating
= 0.3V, 3V, or V
or V
= 0.3V,
NC
-
COM
NO
I
COM(ON)
Full
35
-
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 2.7V, V
or V
= 1.5V, R = 50,
25
Full
25
-
-
21
-
30
35
27
32
-
ns
ns
ns
ns
ns
ON
NO
NC
L
C
= 35pF, (See Figure 1, Note 10)
L
Turn-OFF Time, t
V+ = 2.7V, V
or V
= 1.5V, R = 50,
-
17
-
OFF
NO
NC
L
C
= 35pF, (See Figure 1, Note 10)
L
Full
Full
-
Break-Before-Make Time Delay, t
V+ = 3.3V, V
or V
= 1.5V, R = 50,
2
3
D
NO
NC
L
C
= 35pF, (See Figure 3, Note 10)
L
FN6111 Rev 3.00
February 5, 2008
Page 4 of 14
ISL8499
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V
Unless Otherwise Specified (Continued)
= 1.4V, V
= 0.5V (Note 6),
INL
INH
TEMP
(°C)
MIN
(Notes 7, 8)
MAX
PARAMETER
TEST CONDITIONS
= 1.0nF, V = 0V, R = 0, (See Figure 2)
TYP
-82
68
(Notes 7, 8) UNITS
Charge Injection, Q
OFF Isolation
C
R
25
25
-
-
-
-
pC
dB
L
L
G
G
= 50, C = 5pF, f = 100kHz, V
= 1V
,
,
L
COM
RMS
(See Figure 4)
Crosstalk (Channel-to-Channel)
R
= 50, C = 5pF, f = 100kHz, V
= 1V
25
-
-98
-
dB
L
L
COM
RMS
(See Figure 6)
Total Harmonic Distortion
f = 20Hz to 20kHz, V
= 2V , R = 600
P-P
25
25
25
-
-
-
0.003
106
-
-
-
%
pF
pF
COM
L
NO or NC OFF Capacitance, C
f = 1MHz, V
f = 1MHz, V
or V
or V
= V
= V
= 0V, (See Figure 7)
= 0V, (See Figure 7)
OFF
NO
NC
NC
COM
COM
COM ON Capacitance, C
212
COM(ON)
NO
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = 3.6V, V = 0V or V+
IN
25
-
-
0.025
0.715
-
-
A
A
Full
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
Full
Full
Full
-
-
-
-
0.5
-
V
V
INL
Input Voltage High, V
1.4
-0.5
INH
Input Current, I
, I
V+ = 3.6V, V = 0V or V+ (Note 10)
IN
0.5
A
INH INL
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.65V to +2V, GND = 0V, V
Otherwise Specified
= 1.0V, V
= 0.4V (Note 6), Unless
INH
INL
TEMP
(°C)
MIN
(Notes 7, 8)
MAX
PARAMETER
TEST CONDITIONS
TYP
(Notes 7, 8) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
-
-
0.45
-
V+
0.8
V
ON-Resistance, r
V+ = 1.8V, I
= 100mA, V
or V
= 0V to V+,
NC
ON
COM
(See Figure 5)
NO
Full
-
0.85
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 1.65V, V
or V
= 1.0V, R = 50,
25
Full
25
-
-
51
-
65
70
58
65
-
ns
ns
ns
ns
ns
ON
NO
NO
NC
L
C
= 35pF, (See Figure 1, Note 10)
L
Turn-OFF Time, t
V+ = 1.65V, V
or V
= 1.0V, R = 50,
-
43
-
OFF
NC
L
C
= 35pF, (See Figure 1, Note 10)
L
Full
Full
-
Break-Before-Make Time Delay, t
V+ = 2.0V, V
or V
= 1.0V, R = 50,
3
8
D
NO
NC
L
C
C
R
= 35pF, (See Figure 3, Note 10)
L
L
L
Charge Injection, Q
OFF Isolation
= 1.0nF, V = 0V, R = 0, See Figure 2
25
25
-
-
-44
68
-
-
pC
dB
G
G
= 50, C = 5pF, f = 100kHz, V
= 1V
,
,
L
COM
RMS
RMS
(See Figure 4)
Crosstalk (Channel-to-Channel)
R
= 50, C = 5pF, f = 100kHz, V
= 1V
25
-
-98
-
dB
L
L
COM
(See Figure 6)
NO or NC OFF Capacitance, C
f = 1MHz, V
f = 1MHz, V
or V
or V
= V
= V
= 0V, (See Figure 7)
= 0V, (See Figure 7)
25
25
-
-
106
212
-
-
pF
pF
OFF
NO
NC
NC
COM
COM
COM ON Capacitance, C
COM(ON)
NO
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
Full
Full
Full
-
-
-
-
0.4
-
V
V
INL
Input Voltage High, V
1.0
-0.5
INH
Input Current, I
, I
V+ = 2.0V, V = 0V or V+ (Note 10)
IN
0.5
A
INH INL
FN6111 Rev 3.00
February 5, 2008
Page 5 of 14
ISL8499
Test Circuits and Waveforms
V+
V+
t < 5ns
r
t < 5ns
f
C
LOGIC
INPUT
50%
0V
NO
0V
t
V
OFF
OUT
NO or NC
IN
SWITCH
INPUT
COM
SWITCH
INPUT
V
V
OUT
90%
90%
C
L
35pF
R
50
LOGIC
INPUT
L
GND
SWITCH
OUTPUT
t
ON
Repeat test for all switches. C includes fixture and stray
L
Logic input waveform is inverted for switches that have the opposite
logic sense.
capacitance.
R
L
----------------------------
V
= V
OUT
(NO or NC)
R
+ r
ON
L
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
C
SWITCH
OUTPUT
V
OUT
R
G
V
COM
OUT
NO or NC
V
OUT
V+
0V
V
ON
ON
GND
IN
G
LOGIC
INPUT
C
L
OFF
LOGIC
INPUT
Q = V
x C
L
OUT
FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
V+
C
V+
0V
NO
LOGIC
INPUT
V
V
OUT
NX
COM
NC
C
R
L
L
50
35pF
IN
GND
90%
LOGIC
INPUT
SWITCH
OUTPUT
V
OUT
0V
t
D
C
includes fixture and stray capacitance.
L
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE TIME
FIGURE 3B. TEST CIRCUIT
FN6111 Rev 3.00
February 5, 2008
Page 6 of 14
ISL8499
Test Circuits and Waveforms (Continued)
V+
V+
C
C
rON = V /100mA
1
SIGNAL
GENERATOR
NO or NC
NO or NC
V
NX
IN
0V or V+
0V or V+
100mA
IN
V
1
COM
COM
ANALYZER
GND
GND
R
L
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. rON TEST CIRCUIT
V+
C
V+
C
SIGNAL
GENERATOR
50
NO or NC
COM
NO or NC
IN
1
0V or V+
IN
0V or V+
IMPEDANCE
ANALYZER
COM
GND
NC or NO
COM
ANALYZER
N.C.
GND
R
L
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
Figure 8). To prevent forward biasing these diodes, V+ must be
applied before any input signals, and the input signal voltages
must remain between V+ and GND. If these conditions cannot
be guaranteed, then one of the following two protection
methods should be employed.
Detailed Description
The ISL8499 is a bidirectional, quad single pole/double throw
(SPDT) analog switch that offers precise switching capability
from a single 1.65V to 4.5V supply with low on-resistance
(0.24) and high speed operation (t
= 15ns, t = 13ns).
ON
OFF
The device is especially well suited for portable battery
powered equipment due to its low operating supply voltage
(1.65V), low power consumption (2.7µW max), low leakage
currents (150nA max), and the tiny TQFN, QFN and TSSOP
Logic inputs can easily be protected by adding a 1k resistor
in series with the input (see Figure 8). The resistor limits the
input current below the threshold that produces permanent
damage, and the sub-microamp input current produces an
insignificant voltage drop during normal operation.
packages. The ultra low ON-Resistance and r
flatness
ON
provide very low insertion loss and distortion to applications that
require signal reproduction.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the purpose
Supply Sequencing and Overvoltage Protection
of using a low r
switch, so two small signal diodes can be
ON
added in series with the supply pins to provide overvoltage
protection for all pins (see Figure 8). These additional diodes
limit the analog signal from 1V below V+ to 1V above GND.
The low leakage current performance is unaffected by this
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
FN6111 Rev 3.00
February 5, 2008
Page 7 of 14
ISL8499
approach, but the switch signal range is reduced and the
resistance may increase, especially at low supply voltages.
operating with a 4.2V supply the device draws only 6A of
current (see Figure 21 for VIN = 2.85V).
High-Frequency Performance
In 50 systems, the signal response is reasonably flat even
past 30MHz with a -3dB bandwidth of 104MHz (see Figure 17).
The frequency response is very consistent over a wide V+
range, and for varying analog signal levels.
OPTIONAL PROTECTION
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
IN
V
X
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
V
NO or NC
COM
feedthrough from a switch’s input to its output. Off Isolation is
the resistance to this feedthrough, while Crosstalk indicates the
amount of feedthrough from one switch to another. Figure 18
details the high Off Isolation and Crosstalk rejection provided
by this part. At 100kHz, Off Isolation is about 68dB in 50
systems, decreasing approximately 20dB per decade as
frequency increases. Higher load impedances decrease Off
Isolation and Crosstalk rejection due to the voltage divider
action of the switch OFF impedance and the load impedance.
GND
OPTIONAL PROTECTION
DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
Power-Supply Considerations
Leakage Considerations
The ISL8499 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins: V+
and GND. V+ and GND drive the internal CMOS switches and
set their analog voltage limits. Unlike switches with a 4V
maximum supply voltage, the ISL8499 4.7V maximum supply
voltage provides plenty of room for the 10% tolerance of 4.3V
supplies, as well as room for overshoot and noise spikes.
Reverse ESD protection diodes are internally connected between
each analog-signal pin and both V+ and GND. One of these
diodes conducts if any analog signal exceeds V+ or GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced, they
are reverse biased differently. Each is biased by either V+ or
GND and the analog signal. This means their leakages will
vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analog-
signal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given switch
can show leakage currents of the same or opposite polarity.
There is no connection between the analog signal paths and
V+ or GND.
The minimum recommended supply voltage is 1.65V but will
operate with a supply voltage below 1.5V. It is important to note
that the input signal range, switching times, and on-resistance
degrade at lower supply voltages. Refer to the “Electrical
Specification” tables starting on page 3 and “Typical
Performance” curves starting on page 6 for details.
V+ and GND also power the internal logic and level shiftiers.
The level shiftiers convert the input logic levels to switched V+
and GND signals to drive the analog switch gate terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes negative
in this configuration.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2.7V to 4.5V (see Figure 14). At 2.7V
the V level is about 0.52V. This is still above the 1.8V CMOS
IL
guaranteed low output maximum level of 0.5V, but noise
margin is reduced.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving the
digital input signals from GND to V+ with a fast transition time
minimizes power dissipation. The ISL8499 has been designed
to minimize the supply current whenever the digital input
voltage is not driven to the supply rails (0V to V+). For example
driving the device with 2.85V logic (0V to 2.85V) while
FN6111 Rev 3.00
February 5, 2008
Page 8 of 14
ISL8499
Typical Performance Curves T = +25°C, Unless Otherwise Specified
A
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.28
0.26
0.24
0.22
0.2
V+ = 4.3V
= 100mA
I
= 100mA
COM
I
COM
V+ = 1.8V
+85°C
+25°C
V+ = 2.7V
0.18
0.16
0.14
V+ = 3V
V+ = 4.3V
V+ = 3.6V
-40°C
0
1
2
3
4
5
0
1
2
3
4
5
V
(V)
COM
V
(V)
COM
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0.35
0.50
V+ = 1.8V
= 100mA
V+ = 2.7V
= 100mA
I
I
COM
COM
0.45
0.40
0.35
0.30
0.25
0.20
+85°C
0.30
0.25
0.20
0.15
+85°C
+25°C
+25°C
-40°C
-40°C
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
(V)
1.5
2.0
V
(V)
V
COM
COM
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
1.1
50
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0
-50
V
INH
V+ = 1.8V
V+ = 3V
V
INL
-100
-150
0
0.5
1.0
1.5
2.0
2.5
3.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
V
(V)
V+ (V)
COM
FIGURE 13. CHARGE INJECTION vs SWITCH VOLTAGE
FIGURE 14. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FN6111 Rev 3.00
February 5, 2008
Page 9 of 14
ISL8499
Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)
A
200
150
100
50
200
150
100
50
+85°C
+25°C
+85°C
+25°C
-40°C
-40°C
0
0
1
1.5
2.0
2.5
3.0
3.5
4.0
4.5
1.5
2.0
2.5
3.0
3.5
4.0
4.5
1
V+ (V)
V+ (V)
FIGURE 15. TURN - ON TIME vs SUPPLY VOLTAGE
FIGURE 16. TURN - OFF TIME vs SUPPLY VOLTAGE
-10
10
V+ = 3V
V+ = 3V
GAIN
-20
-30
-40
-50
-60
-70
-80
-90
20
30
40
50
60
70
80
90
0
-20
0
PHASE
20
40
60
80
ISOLATION
CROSSTALK
-100
-110
100
110
R
= 50
= 0.2V
100
L
V
to 2V
IN
P-P P-P
1M
10M
100M
600M
1k
10k
100k
1M
10M
100M 500M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 17. FREQUENCY RESPONSE
FIGURE 18. CROSSTALK AND OFF ISOLATION
100
50
50
V+ = 4.5V
V+ = 4.5V
= 0.3V
V
COM
0
-50
+25°C
0
+25°C
+85°C
-50
-100
-100
-150
+85°C
0
1
2
V
3
(V)
4
5
0
1
2
3
4
5
COM/NX
V
(V)
NX
FIGURE 19. ON LEAKAGE vs SWITCH VOLTAGE
FIGURE 20. OFF LEAKAGE vs SWITCH VOLTAGE
FN6111 Rev 3.00
February 5, 2008
Page 10 of 14
ISL8499
Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)
A
200
Die Characteristics
V+ = 4.2V
Sweeping Both Logic Inputs
SUBSTRATE POTENTIAL (POWERED UP):
150
100
50
GND (QFN Paddle Connection: To Ground or Float)
TRANSISTOR COUNT:
228
PROCESS:
Si Gate CMOS
0
1
2
3
4
5
V
(V)
IN1-4
FIGURE 21. SUPPLY CURRENT vs VLOGIC
© Copyright Intersil Americas LLC 2005-2008. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6111 Rev 3.00
February 5, 2008
Page 11 of 14
ISL8499
Thin Shrink Small Outline Plastic Packages (TSSOP)
M16.173
N
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
MIN
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
GAUGE
PLANE
SYMBOL
MAX
0.043
0.006
0.037
0.012
0.008
0.201
0.177
MIN
-
MAX
1.10
0.15
0.95
0.30
0.20
5.10
4.50
NOTES
A
A1
A2
b
-
-
0.002
0.033
0.0075
0.0035
0.193
0.169
0.05
0.85
0.19
0.09
4.90
4.30
-
1
2
3
-
L
0.25
0.010
0.05(0.002)
SEATING PLANE
A
9
-A-
c
-
D
D
E1
e
3
-C-
4
0.026 BSC
0.65 BSC
-
A2
e
A1
c
E
0.246
0.020
0.256
0.028
6.25
0.50
6.50
0.70
-
b
0.10(0.004)
L
6
0.10(0.004) M
C
A M B S
N
a
16
16
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 1 2/02
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm
(0.006 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact. (Angles in degrees)
FN6111 Rev 3.00
February 5, 2008
Page 12 of 14
ISL8499
Package Outline Drawing
L16.3x3
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 4/07
4X
1.5
3.00
0.50
12X
A
6
B
PIN #1 INDEX AREA
16
13
6
PIN 1
INDEX AREA
1
12
1 .50 ± 0 . 15
9
4
(4X)
0.15
5
8
0.10 M C A B
+ 0.07
4
TOP VIEW
16X 0.23
- 0.05
16X 0.40 ± 0.10
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
C
0 . 90 ± 0.1
BASE PLANE
( 2. 80 TYP )
(
SEATING PLANE
0.08 C
SIDE VIEW
1. 50 )
( 12X 0 . 5 )
( 16X 0 . 23 )
( 16X 0 . 60)
5
C
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6111 Rev 3.00
February 5, 2008
Page 13 of 14
ISL8499
Thin Quad Flat No-Lead Plastic Package (TQFN)
Thin Micro Lead Frame Plastic Package (TMLFP)
2X
L16.3x3A
0.15
C A
D
A
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
9
D/2
MILLIMETERS
D1
SYMBOL
MIN
NOMINAL
MAX
0.80
0.05
0.80
NOTES
D1/2
A
A1
A2
A3
b
0.70
0.75
-
2X
N
0.15 C
B
-
-
-
-
6
INDEX
AREA
-
9
1
2
3
E1/2
E/2
9
0.20 REF
9
E1
E
B
0.18
1.35
1.35
0.23
0.30
1.65
1.65
5, 8
D
3.00 BSC
-
2X
D1
D2
E
2.75 BSC
9
0.15 C
B
2X
1.50
7, 8, 10
TOP VIEW
0.15 C A
3.00 BSC
-
A2
0
4X
E1
E2
e
2.75 BSC
9
A
/ /
0.10 C
0.08 C
C
1.50
7, 8, 10
0.50 BSC
-
A3 A1
SEATING PLANE
SIDE VIEW
k
0.20
0.30
-
0.40
16
4
-
-
9
L
0.50
8
5
NX b
N
2
0.10 M C A B
4X P
D2
D2
8
Nd
Ne
P
3
7
NX k
(DATUM B)
4
3
2
N
-
-
-
0.60
12
9
4X P
-
9
1
(DATUM A)
2
3
Rev. 0 6/04
(Ne-1)Xe
REF.
E2
6
NOTES:
INDEX
AREA
7
8
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
E2/2
NX L
8
N
e
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
9
CORNER
OPTION 4X
(Nd-1)Xe
REF.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
BOTTOM VIEW
A1
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX b
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
SECTION "C-C"
C
L
C
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
L
9. Features and dimensions A2, A3, D1, E1, P & are present when
Anvil singulation method is used and not present for saw
singulation.
L
L
10
10
L1
L1
e
e
10. Compliant to JEDEC MO-220WEED-2 Issue C, except for the E2
and D2 MAX dimension.
C
C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
FOR EVEN TERMINAL/SIDE
FN6111 Rev 3.00
February 5, 2008
Page 14 of 14
相关型号：
ISL8499IRTZ-T
Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Quad SPDT (Dual DPDT) Analog Switch
INTERSIL
ISL8499IRZ
Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Quad SPDT (Dual DPDT) Analog Switch
INTERSIL
ISL8499IRZ-T
Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Quad SPDT (Dual DPDT) Analog Switch
INTERSIL
ISL8499IRZ-T
Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Quad SPDT (Dual DPDT) Analog Switch; QFN16, TQFN16, TSSOP16; Temp Range: -40° to 85°C
RENESAS
ISL8499IV
Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Quad SPDT (Dual DPDT) Analog Switch
INTERSIL
ISL8499IV-T
Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Quad SPDT (Dual DPDT) Analog Switch
INTERSIL
ISL8499IV-T
QUAD 1-CHANNEL, SGL POLE DOUBLE THROW SWITCH, PDSO16, PLASTIC, MO-153AB, TSSOP-16
RENESAS
ISL8499IVZ
Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Quad SPDT (Dual DPDT) Analog Switch
INTERSIL
©2020 ICPDF网 联系我们和版权申明