ISL84762IR [RENESAS]
DUAL 1-CHANNEL, SGL POLE DOUBLE THROW SWITCH, PDSO10, 3 X 3 MM, PLASTIC, MO-229WEED-3, TDFN-10;
| 型号： | ISL84762IR |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | DUAL 1-CHANNEL, SGL POLE DOUBLE THROW SWITCH, PDSO10, 3 X 3 MM, PLASTIC, MO-229WEED-3, TDFN-10 光电二极管 输出元件 |
| 文件： | 总12页 (文件大小：609K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SIGNS
PART
DED FOR NEW DE
D REPLACEMENT
ISL84714
NOT RECOMMEN
RECOMMENDE
DATASHEET
ISL84762
FN6105
Rev 1.00
September 15, 2008
Ultra Low ON-Resistance, Low Voltage, Single Supply, Dual SPDT Analog Switch
The Intersil ISL84762 device is a low ON-resistance, low
voltage, bidirectional, dual single-pole/double-throw (SPDT)
analog switch designed to operate from a single +1.65V to
+3.6V supply. Targeted applications include battery powered
Features
• Pb-Free Available (RoHS Compliant)
• Pin Compatible Replacement for the MAX4762
equipment that benefits from low r
(0.35 and fast
= 6ns). The digital logic
ON
• ON-Resistance (r
)
ON
switching speeds (t
ON
= 14ns, t
OFF
- V+ = +2.7V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.39
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.55
input is 1.8V logic-compatible when using a single +3V supply.
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This part may be used to “mux-in”
additional functionality while reducing ASIC design risk. The
ISL84762 is offered in small form factor packages, alleviating
board space limitations.
• r
• r
Matching Between Channels . . . . . . . . . . . . . . . . 0.05
Flatness Across Signal Range . . . . . . . . . . . . . . 0.043
ON
ON
• Single Supply Operation. . . . . . . . . . . . . . . . +1.65V to +3.6V
• Low Power Consumption (P ). . . . . . . . . . . . . . . . . <0.02µW
D
• Fast Switching Action (V+ = +2.7V)
- t
- t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14ns
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ns
The ISL84762 is a committed dual single-pole/double-throw
(SPDT) that consist of two normally open (NO) and two
normally (NC) switches. This configuration can be used as a
dual 2-to-1 multiplexer. The ISL84762 is pin compatible with
the MAX4762.
ON
OFF
• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >9kV
• Guaranteed Break-before-Make
• 1.8V Logic Compatible (+3V supply)
TABLE 1. FEATURES AT A GLANCE
ISL84762
• Available in 10 Ld 3x3 Thin DFN and 10 Ld MSOP
Number of Switches
SW
2
SPDT or 2-to-1 MUX
0.35
Applications
• Battery-powered, Handheld, and Portable Equipment
- Cellular/mobile Phones
3V r
ON
- Pagers
3V t /t
12ns/5ns
ON OFF
1.8V r
- Laptops, Notebooks, Palmtops
0.55
ON
1.8V t /t
• Portable Test and Measurement
• Medical Equipment
20ns/8ns
ON OFF
Packages
10 Ld 3x3 TDFN, 10 Ld MSOP
• Audio and Video Switching
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
FN6105 Rev 1.00
Page 1 of 12
September 15, 2008
ISL84762
Ordering Information
Pinout (Note 1)
ISL84762
(10 LD TDFN, MSOP)
TOP VIEW
TEMP.
RANGE
(°C)
PART
NUMBER
PART
MARKING
PKG.
DWG. #
PACKAGE
ISL84762IR
762
-40 to +85 10 Ld 3x3 TDFN L10.3x3A
V+
1
2
3
4
5
10 NO2
ISL84762IR-T* 762
-40 to +85 10 Ld 3x3 TDFN L10.3x3A
Tape and Reel
9
8
7
6
NO1
COM1
NC1
COM2
NC2
ISL84762IU
4762
-40 to +85 10 Ld MSOP
M10.118
M10.118
IN2
ISL84762IU-T* 4762
-40 to +85 10 Ld MSOP
Tape and Reel
IN1
GND
ISL84762IRZ
(Note)
762Z
-40 to +85 10 Ld 3x3 TDFN L10.3x3A
(Pb-free)
NOTE:
ISL84762IRZ-T* 762Z
(Note)
-40 to +85 10 Ld 3x3 TDFN L10.3x3A
Tape and Reel
1. Switches Shown for Logic “0” Input.
(Pb-free)
ISL84762IUZ
(Note)
4762Z
-40 to +85 10 Ld MSOP
(Pb-free)
M10.118
M10.118
Truth Table
LOGIC
NC1, NC2
ON
NO1, NO2
ISL84762IUZ-T* 4762Z
(Note)
-40 to +85 10 Ld MSOP
Tape and Reel
(Pb-free)
0
1
OFF
ON
OFF
*Please refer to TB347 for details on reel specifications.
NOTE: Logic “0” 0.5V. Logic “1” 1.4V with a 3V supply.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Pin Descriptions
PIN
FUNCTION
System Power Supply Input (+1.65V to +3.6V)
Ground Connection
V+
GND
IN
Digital Control Input
COM
NO
Analog Switch Common Pin
Analog Switch Normally Open Pin
Analog Switch Normally Closed Pin
NC
FN6105 Rev 1.00
Page 2 of 12
September 15, 2008
ISL84762
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V
Input Voltages
NO, NC, IN (Note 2) . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Output Voltages
COM (Note 2). . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA
Peak Current NO, NC, or COM
Thermal Resistance (Typical)
(°C/W)
(°C/W)
JC
JA
10 Ld 3x3 TDFN Package (Note 3) . . .
10 Ld MSOP Package (Note 4) . . . . . .
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
47
162
11
N/A
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±500mA
ESD Rating:
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>9kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1kV
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
4. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V
= 1.4V, V
= 0.5V (Note 5)
INL
INH
Unless Otherwise Specified.
TEMP
MIN
MAX
PARAMETER
TEST CONDITIONS
(°C) (Notes 6, 7) TYP (Notes 6, 7) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
-
-
V+
0.6
0.6
0.2
0.2
0.1
0.15
2
V
ON-Resistance, r
V+ = 2.7V, I
COM
(See Figure 5)
= 100mA, V
or V = 0V to V+
NC
0.39
ON
NO
Full
25
-
-
r
Matching Between Channels,
V+ = 2.7V, I
COM
= 100mA, V
NO
or V = Voltage at max
NC
-
0.05
ON
r
r
(Note 10)
ON
ON
Full
25
-
-
r
Flatness, R
V+ = 2.7V, I
(Note 8)
= 100mA, V
or V = 0V to V+
NC
-
0.043
ON
FLAT(ON)
COM
NO
Full
25
-
-
-
-
-
-
NO or NC OFF Leakage Current,
or I
V+ = 3.3V, V
= 0.3V, 3V, V
NO
or V
NC
= 3V, 0.3V
-2
-40
-3
-60
nA
nA
nA
nA
COM
I
NO(OFF)
NC(OFF)
Full
25
40
COM ON Leakage Current,
V = 3.3V, V
= 0.3V, 3V, or V
NO
or V
= 0.3V, 3V,
3
COM
NC
I
or Floating
COM(ON)
Full
60
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 2.7V, V
(See Figure 1, Note 9)
or V
= 1.5V, R = 50, C = 35pF
25
Full
25
-
-
14
-
20
25
12
17
-
ns
ns
ns
ns
ns
ON
NO
NC
L
L
Turn-OFF Time, t
V+ = 2.7V, V
(See Figure 1, Note 9)
or V
= 1.5V, R = 50, C = 35pF
-
6
-
OFF
NO
NC
L
L
Full
Full
-
Break-Before-Make Time Delay, t
V+ = 3.3V, V
or V
= 1.5V, R = 50, C = 35pF
2
7
D
NO
NC
L
L
(See Figure 3, Note 9)
Charge Injection, Q
OFF-Isolation
C
R
= 1.0nF, V = 0V, R = 0See Figure 2)
25
25
-
-
95
-
-
pC
dB
L
L
G
G
= 50, C = 5pF, f = 100kHz, V
= 1V
-68
L
COM
RMS
(See Figure 4)
Crosstalk (Channel-to-Channel)
Total Harmonic Distortion
R
= 50, C = 5pF, f = 100kHz, V
= 1V
25
-
-95
-
dB
L
L
COM
RMS
(See Figure 6)
f = 20Hz to 20kHz, V
= 2V , R = 600
P-P
25
25
-
-
0.003
115
-
-
%
COM
= V = 0V (See Figure 7)
COM
L
NO or NC OFF Capacitance, C
f = 1MHz, V
or V
pF
OFF
NO
NC
FN6105 Rev 1.00
Page 3 of 12
September 15, 2008
ISL84762
Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V
Unless Otherwise Specified. (Continued)
= 1.4V, V
= 0.5V (Note 5)
INL
INH
TEMP
MIN
MAX
PARAMETER
TEST CONDITIONS
or V = V = 0V (See Figure 7)
(°C) (Notes 6, 7) TYP (Notes 6, 7) UNITS
COM ON Capacitance, C
f = 1MHz, V
25
-
224
-
pF
COM(ON)
NO
NC
COM
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Full
25
1.65
-
-
-
3.6
40
V
Positive Supply Current, I+
V+ = +3.6V, V = 0V or V+
IN
-
-
nA
nA
Full
750
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
Full
Full
Full
-
-
-
-
0.5
-
V
V
INL
Input Voltage High, V
1.4
-0.5
INH
Input Current, I
, I
INH INL
V+ = 3.3V, V = 0V or V+ (Note 9)
IN
0.5
µA
Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.65V to +2V, GND = 0V, V
= 1.0V, V
= 0.4V (Note 5),
INL
INH
Unless Otherwise Specified.
TEMP
MIN
MAX
PARAMETER
TEST CONDITIONS
(°C) (Notes 6, 7) TYP (Notes 6, 7) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
-
-
V+
V
ON-Resistance, r
V+ = 1.8V, I
COM
(See Figure 5, Note 9)
= 100mA, V
or V = 0V to V+
NC
0.55
0.6
-
-
ON
NO
Full
-
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 1.65V, V
(See Figure 1, Note 9)
or V
= 1.0V, R =50, C = 35pF
25
Full
25
-
-
22
-
28
33
15
20
-
ns
ns
ns
ns
ns
ON
NO
NC
L
L
Turn-OFF Time, t
V+ = 1.65V, V
(See Figure 1, Note 9)
or V
= 1.0V, R =50, C = 35pF
-
9
-
OFF
NO
NC
L
L
Full
Full
-
Break-Before-Make Time Delay, t
V+ = 2.0V, V
or V
= 1.0V, R =50, C = 35pF,
2
9
D
NO
NC
L
L
(See Figure 3, Note 9)
Charge Injection, Q
OFF-Isolation
C
R
= 1.0nF, V = 0V, R = 0See Figure 2)
25
25
-
-
49
-
-
pC
dB
L
L
G
G
= 50, C = 5pF, f = 100kHz, V
= 1V
-68
L
COM
RMS
(See Figure 4)
Crosstalk (Channel-to-Channel)
R
= 50, C = 5pF, f = 100kHz, V
= 1V
25
-
-95
-
dB
L
L
COM
RMS
(See Figure 6)
NO or NC OFF Capacitance, C
f = 1MHz, V
f = 1MHz, V
or V
or V
= V
= V
= 0V (See Figure 7)
= 0V (See Figure 7)
25
25
-
-
115
224
-
-
pF
pF
OFF
NO
NO
NC
NC
COM
COM
COM ON Capacitance, C
COM(ON)
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
Full
Full
Full
-
-
-
-
0.4
-
V
V
INL
Input Voltage High, V
1.0
-0.5
INH
Input Current, I
NOTES:
, I
INH INL
V+ = 2.0V, V = 0V or V+ (Note 9)
IN
0.5
µA
5. V = input voltage to perform proper function.
IN
6. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
8. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range.
9. Limits established by characterization and are not production tested.
10. r
ON
matching between channels is calculated by subtracting the channel with the highest max r
ON
value from the channel with lowest max r
ON
value.
FN6105 Rev 1.00
Page 4 of 12
September 15, 2008
ISL84762
Test Circuits and Waveforms
V+
C
V+
t < 5ns
r
t < 5ns
f
LOGIC
INPUT
50%
0V
NO
0V
V
OUT
t
NO OR NC
IN
OFF
SWITCH
INPUT
COM
SWITCH
INPUT
V
V
OUT
90%
90%
C
L
35pF
R
50
LOGIC
INPUT
L
GND
SWITCH
OUTPUT
t
ON
Repeat test for all switches. C includes fixture and stray
L
Logic input waveform is inverted for switches that have the opposite
logic sense.
capacitance.
R
L
-----------------------
V
= V
OUT
(NO or NC)
R
+ r
ON
L
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
C
V
R
OUT
G
COM
NO OR NC
GND
SWITCH
OUTPUT
V
OUT
V
V
OUT
IN
G
C
L
V+
0V
ON
ON
LOGIC
INPUT
LOGIC
INPUT
OFF
Q = V
x C
L
OUT
Repeat test for all switches.
FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
V+
C
V+
0V
NO
LOGIC
INPUT
V
V
OUT
NX
COM
NC
C
R
L
L
50
35pF
IN
GND
90%
LOGIC
INPUT
SWITCH
OUTPUT
V
OUT
0V
t
D
Repeat test for all switches. C includes fixture and stray
L
capacitance.
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
FN6105 Rev 1.00
Page 5 of 12
September 15, 2008
ISL84762
Test Circuits and Waveforms (Continued)
V+
C
V+
C
SIGNAL
GENERATOR
r
= V /100mA
1
NO OR NC
ON
NO OR NC
V
NX
IN
0V OR V+
0V OR V+
100mA
IN
V
1
COM
ANALYZER
GND
COM
R
L
GND
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
Repeat test for all switches.
FIGURE 4. OFF-ISOLATION TEST CIRCUIT
FIGURE 5. r
TEST CIRCUIT
ON
V+
C
V+
C
SIGNAL
GENERATOR
NO OR NC
50
COM
NO OR NC
IN
1
0V OR V+
IN
0V OR V+
IMPEDANCE
ANALYZER
NC OR NO
COM
COM
ANALYZER
NC
GND
GND
R
L
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
Repeat test for all switches.
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
During an overvoltage transient event, such as occurs during
system level IEC 61000 ESD testing, substrate currents can be
generated in the IC that can trigger parasitic SCR structures to
turn ON, creating a low impedance path from the V+ power
supply to ground. This will result in a significant amount of
current flow in the IC, which can potentially create a latch-up
state or permanently damage the IC. The external V+ resistor
limits the current during this over-stress situation and has been
found to prevent latch-up or destructive damage for many
overvoltage transient events.
Detailed Description
The ISL84762 is a bidirectional, dual single pole/double throw
(SPDT) analog switch that offers precise switching capability
from a single 1.65V to 3.6V supply with low ON-resistance
(0.39) and high speed operation (t
= 14ns, t = 6ns).
ON
OFF
The device is especially well suited for portable battery
powered equipment due to its low operating supply voltage
(1.65V), low power consumption (2.7µW max), low leakage
currents (60nA max), and the tiny, Thin DFN and MSOP
packages. The ultra low ON-resistance and r
flatness provide
ON
very low insertion loss and distortion to applications that require
signal reproduction.
Under normal operation, the sub-microamp I
current of the
DD
IC produces an insignificant voltage drop across the 100
series resistor resulting in no impact to switch operation or
performance.
External V+ Series Resistor
For improved ESD and latch-up immunity, Intersil recommends
adding a 100 resistor in series with the V+ power supply pin
of the ISL84762 IC (see Figure 8).
FN6105 Rev 1.00
Page 6 of 12
September 15, 2008
ISL84762
V+
OPTIONAL
SCHOTTKY
DIODE
C
OPTIONAL
PROTECTION
RESISTOR
V+
100
OPTIONAL
PROTECTION
RESISTOR
IN
V
X
NO
NC
COM
V
NX
COM
IN
GND
GND
OPTIONAL
SCHOTTKY
DIODE
FIGURE 8. V+ SERIES RESISTOR FOR ENHANCED ESD AND
LATCH-UP IMMUNITY
FIGURE 9. OVERVOLTAGE PROTECTION
Power-Supply Considerations
Supply Sequencing and Overvoltage Protection
The ISL84762 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins: V+
and GND. V+ and GND drive the internal CMOS switches and
set their analog voltage limits. Unlike switches with a 4V
maximum supply voltage, the ISL84762 4.8V maximum supply
voltage provides plenty of room for the 10% tolerance of 3.6V
supplies, as well as room for overshoot and noise spikes.
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 9). To prevent forward biasing these diodes, V+ must be
applied before any input signals, and the input signal voltages
must remain between V+ and GND.
The minimum recommended supply voltage is 1.65V but the
part will operate with a supply below 1.5V. It is important to
note that the input signal range, switching times, and
ON-resistance degrade at lower supply voltages. Refer to the
“Electrical Specifications” tables beginning on page 3 and
“Typical Performance Curves” beginning on page 8 for details.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at the
logic pin and signal pins from exceeding the maximum ratings
of the switch. The following two methods can be used to
provided additional protection to limit the current in the event
that the voltage at a signal pin or logic pin goes below ground
or above the V+ rail.
V+ and GND also power the internal logic and level shiftiers.
The level shiftiers convert the input logic levels to switched V+
and GND signals to drive the analog switch gate terminals.
Logic inputs can be protected by adding a 1k resistor in
series with the logic input (see Figure 9). The resistor limits the
input current below the threshold that produces permanent
damage, and the sub-microamp input current produces an
insignificant voltage drop during normal operation.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes negative
in this configuration.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the purpose
of using a low r
switch. Connecting Schottky diodes to the
ON
signal pins as shown in Figure 9 will shunt the fault current to
the supply or to ground thereby protecting the switch. These
Schottky diodes must be sized to handle the expected fault
current.
FN6105 Rev 1.00
Page 7 of 12
September 15, 2008
ISL84762
this part. At 100kHz, off-Isolation is about 68dB in 50
systems, decreasing approximately 20dB per decade as
frequency increases. Higher load impedances decrease off-
Isolation and crosstalk rejection due to the voltage divider
action of the switch OFF impedance and the load impedance.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2.0V to 3.6V (see Figure 16). At 3.6V
the V level is about 1.27V. This is still below the 1.8V CMOS
IH
guaranteed high output minimum level of 1.4V, but noise
margin is reduced.
Leakage Considerations
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving the
digital input signals from GND to V+ with a fast transition time
minimizes power dissipation.
Reverse ESD protection diodes are internally connected between
each analog-signal pin and both V+ and GND. One of these
diodes conducts if any analog signal exceeds V+ or GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced, they
are reverse biased differently. Each is biased by either V+ or
GND and the analog signal. This means their leakages will
vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analog-
signal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given switch
can show leakage currents of the same or opposite polarity.
There is no connection between the analog signal paths and
High-Frequency Performance
In 50 systems, the signal response is reasonably flat even
past 30MHz with a -3dB bandwidth of 120MHz (see Figure 17).
The frequency response is very consistent over a wide V+
range, and for varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off-Isolation is
the resistance to this feedthrough, while crosstalk indicates the
amount of feedthrough from one switch to another. Figure 18
details the high off-Isolation and crosstalk rejection provided by
Typical Performance Curves
T = +25°C, Unless Otherwise Specified.
A
0.7
0.44
0.42
0.40
0.38
0.36
0.34
0.32
0.30
V+ = 2.7V
= 100mA
I
= 100mA
COM
I
COM
0.6
+85°C
+25°C
0.5
V+ = 1.8V
V+ = 3.6V
0.4
0.3
0.2
0.1
V+ = 2.7V
V+ = 3V
-40°C
0
0.5
1.0
1.5
(V)
2.0
2.5
3.0
0
1
2
3
4
V
V
(V)
COM
COM
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
FN6105 Rev 1.00
Page 8 of 12
September 15, 2008
ISL84762
Typical Performance Curves
T
= +25°C, Unless Otherwise Specified. (Continued)
A
0.65
100
V+ = 1.8V
I
= 100mA
COM
0.60
75
50
25
0
+85°C
V+ = 3V
0.55
0.50
0.45
V+ = 1.8V
+25°C
1.5
-40°C
0.40
0.35
-25
-50
0
0.5
1.0
(V)
2.0
0
0.5
1.0
1.5
2.0
2.5
3.0
V
(V)
V
COM
COM
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 13. CHARGE INJECTION vs SWITCH VOLTAGE
60
50
40
30
14
13
12
11
10
9
8
7
6
5
4
3
+85°C
-40°C
+25°C
+85°C
+25°C
3.5
20
-40°C
2.0
10
1.0
1.5
2.5
3.0
3.5
4.0
4.5
1.5
2.0
2.5
3.0
4.0
4.5
1.0
V+ (V)
V+ (V)
FIGURE 14. TURN-ON TIME vs SUPPLY VOLTAGE
FIGURE 15. TURN-OFF TIME vs SUPPLY VOLTAGE
1.5
V+ = 3V
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0
GAIN
-20
V
0
INH
PHASE
20
40
V
INL
60
80
R
= 50
= 0.2V
100
L
V
TO 2V
P-P P-P
IN
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
1M
10M
100M
600M
V+ (V)
FREQUENCY (Hz)
FIGURE 16. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FIGURE 17. FREQUENCY RESPONSE
FN6105 Rev 1.00
Page 9 of 12
September 15, 2008
ISL84762
Typical Performance Curves
T
= +25°C, Unless Otherwise Specified. (Continued)
A
-10
10
V+ = 3V
-20
20
Die Characteristics
-30
-40
-50
30
SUBSTRATE POTENTIAL (POWERED UP):
40
50
60
70
80
90
GND (QFN Paddle Connection: Tie to GND or Float)
TRANSISTOR COUNT:
-60
114
ISOLATION
-70
PROCESS:
-80
Submicron CMOS
CROSSTALK
-90
-100
-110
100
110
1k
10k
100k
1M
10M
100M 500M
FREQUENCY (Hz)
FIGURE 18. CROSSTALK AND OFF-ISOLATION
© Copyright Intersil Americas LLC 2004-2008. All Rights Reserved.
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For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6105 Rev 1.00
Page 10 of 12
September 15, 2008
ISL84762
Thin Dual Flat No-Lead Plastic Package (TDFN)
L10.3x3A
2X
0.10 C
A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
A
D
MILLIMETERS
2X
0.10
C B
SYMBOL
MIN
0.70
-
NOMINAL
MAX
0.80
0.05
NOTES
A
A1
A3
b
0.75
-
-
0.20 REF
0.25
3.0
-
E
-
6
INDEX
AREA
0.20
2.95
2.25
2.95
1.45
0.30
3.05
2.35
3.05
1.55
5, 8
D
-
TOP VIEW
B
A
D2
E
2.30
3.0
7, 8
-
// 0.10
0.08
C
E2
e
1.50
0.50 BSC
-
7, 8
-
C
k
0.25
0.25
-
-
A3
C
SIDE VIEW
L
0.30
10
0.35
8
SEATING
PLANE
N
2
D2
D2/2
2
Nd
5
3
7
8
(DATUM B)
Rev. 3 3/06
NOTES:
1
6
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
INDEX
AREA
NX k
E2
3. Nd refers to the number of terminals on D.
(DATUM A)
4. All dimensions are in millimeters. Angles are in degrees.
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
NX L
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
N
N-1
NX b
8
e
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
(Nd-1)Xe
REF.
M
0.10
C A B
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
BOTTOM VIEW
C
9. Compliant to JEDEC MO-229-WEED-3 except for D2
dimensions.
L
(A1)
NX (b)
L1
L
9
5
e
SECTION "C-C"
TERMINAL TIP
FOR ODD TERMINAL/SIDE
C C
FN6105 Rev 1.00
Page 11 of 12
September 15, 2008
ISL84762
Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
E1
E
SYMBOL
MIN
MAX
MIN
0.94
0.05
0.75
0.18
0.09
2.95
2.95
MAX
1.10
0.15
0.95
0.27
0.20
3.05
3.05
NOTES
A
A1
A2
b
0.037
0.002
0.030
0.007
0.004
0.116
0.116
0.043
0.006
0.037
0.011
0.008
0.120
0.120
-
-B-
0.20 (0.008)
INDEX
AREA
1 2
A
B
C
-
-
TOP VIEW
4X
9
0.25
(0.010)
R1
c
-
R
GAUGE
PLANE
D
3
E1
e
4
SEATING
PLANE
L
0.020 BSC
0.50 BSC
-
-C-
4X
L1
A
A2
E
0.187
0.016
0.199
0.028
4.75
0.40
5.05
0.70
-
L
6
SEATING
PLANE
L1
N
0.037 REF
10
0.95 REF
10
-
0.10 (0.004)
-A-
C
C
b
7
-H-
A1
e
R
0.003
0.003
-
-
0.07
0.07
-
-
-
D
0.20 (0.008)
C
R1
-
o
o
o
o
a
SIDE VIEW
5
15
5
15
-
C
L
o
o
o
o
0
6
0
6
-
E
1
-B-
Rev. 0 12/02
0.20 (0.008)
C
D
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
- H -
and are measured at Datum Plane.
Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
- B -
-A -
10. Datums
and
to be determined at Datum plane
.
- H -
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only
FN6105 Rev 1.00
Page 12 of 12
September 15, 2008
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