ISL78434AVEZ-T [RENESAS]
100V Boot, 4A Peak, Half-Bridge Driver with Single PWM Input and Adaptive Dead Time Control;
| 型号： | ISL78434AVEZ-T |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 100V Boot, 4A Peak, Half-Bridge Driver with Single PWM Input and Adaptive Dead Time Control |
| 文件： | 总34页 (文件大小：1684K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL78424, ISL78434, ISL78444
100V Boot, 4A Peak, Half-Bridge Driver with Single PWM Input and Adaptive
Dead Time Control
FN9357
Rev.0.00
Sep 10, 2018
The ISL78424, ISL78434, and ISL78444 are Automotive
Grade (AEC-Q100 Grade 1) high voltage, high
frequency, half-bridge NMOS FET drivers for driving
the gates of up to 70V half-bridge topologies.
Features
• Patented gate-sensed adaptive dead time control
provides shoot-through protection and mimized dead
time
The family of half-bridge drivers feature 3A sourcing,
4A sinking peak gate drive current. The ISL78424 and
ISL78444 feature a single tri-level PWM input for
controlling both gate drivers. The ISL78434 has dual
independent inputs for controlling the high-side and
low-side driver separately. The ISL78424 and ISL78434
have independent sourcing and sinking pins for each gate
driver while ISL78444 has a single combined
• Unique tri-level PWM input for integration with
Renesas multiphase controllers (for example,
ISL78225 and ISL78226)
• 3A sourcing and 4A sinking output current
• On-chip 3Ω bootsrap FET switch
• Programmable dead time delay with single resistor
• Tri-level PWM input (ISL78424, ISL78444)
• Independent HI/LI inputs (ISL78434)
sourcing/sinking output for each gate driver.
Strong gate drive strength and the Adaptive Dead Time
(ADT) feature allow this family of drivers to switch high
• Separate source/sink pins at driver outputs
(ISL78424, ISL78434)
voltage, low r
power FETs in half-bridge
DS(ON)
topologies at high operating frequencies while providing
shoot-through protection and minimizing dead time
switching losses.
• Bootstrap and VDD Undervoltage Lockout (UVLO)
• Wide supply range: 8V to 18V
• Bootstrap supply maximum voltage: 100V
• Maximum phase voltage: 86V
The ISL78424, ISL78434, and ISL78444 are offered in a 14
Ld HTSSOP package that complies with 100V conductor
spacing per IPC-2221B. The ISL78444 is pin compatible
with the ISL78420. All devices are specified across a
wide ambient temperature range of -40°C to +140°C.
• Minimum phase voltage: -10V
Applications
• Automotive half-bridge and 3-phase motor driver
Related Literature
For a full list of related documents, visit our website:
• 12V to 24V and 12V to 48V bidirectional DC/DC
(with ISL78226, ISL78224 controllers)
• ISL78424, ISL78434, ISL78444 product pages
• Multi-phase boost (with ISL78220 and ISL78225
controllers)
V_BUS
RSINK
12V
48V
PWM
VDD
EN
LO
RSOURCE
CBOOT
VOUT
HB
14 VDD
1
2
3
4
5
6
HB
HO
HS
ISL78444
EPAD
RSOURCE
HO_H
LO_H
13
RDT
VSS
PWM1
PWM2
PWM3
PWM4
LO_L
12
HO_L
HS
ISL78226
6-Phase
DC/DC
RSINK
VSS
11
ISL78424
Phase #1
Phase #2
Phase #3
Phase #4
Phase #5
Phase #6
PWM
10
NC
Controller
PWM5
PWM6
From
Controller
EN
9
NC
AGND
RDT
8
7
Figure 1. Independent Source and Sink Outputs for
Optimizing Gate Drive Current and Adaptive Dead Time
Sensing
Figure 2. NMOS Half-Bridge Driver for 12V-48V Bi-Directional
DC/DC Controller
FN9357 Rev.0.00
Sep 10, 2018
Page 1 of 34
ISL78424, ISL78434, ISL78444
Contents
1.
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1
1.2
1.3
1.4
2.
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1
2.2
2.3
2.4
2.5
2.6
3.
4.
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Product Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Single PWM or Independent HI/LI Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ISL78424 and ISL78444 PWM Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ISL78434 HI/LI Lockout Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Separate Source and Sink Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Peak Gate Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Shoot-Through Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Shoot-Through and Dead Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Adaptive Dead Time Control (ADTC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Adaptive Dead Time and Gate Resistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Falling Thresholds for ADTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Adjustable Dead Time Delay (RDT Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Integrated Bootstrap Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Bootstrap Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
EN Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
UVLO Protection - VDD and Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
5.
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Supply Voltage Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Bootstrap Capacitor Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Gate Drive Limiting Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Adaptive Dead Time Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Adjustable Dead Time Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Power Dissipation Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1
5.2
5.3
5.4
5.5
5.6
6.
7.
8.
PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
FN9357 Rev.0.00
Sep 10, 2018
Page 2 of 34
ISL78424, ISL78434, ISL78444
1. Overview
1. Overview
1.1
Block Diagrams
ISL78424
10
HB
VDD
HO_H
HO_L
5V
Regulator
Gate
Drive
Switch
Control
HB
UVLO
5V
Level
Shift
1M
5V
PWM
HS
HS
Adaptive
Dead Time
Delay
Delay
160k
160k
VDD
UVLO
-
PWM
+
LO_H
LO_L
~6V
-
+
Gate
Drive
100k
EN
0.6V
Ref
VSS
~6V
5V
160k
Prog Dead
Time
RDT
AGND
Figure 3. ISL78424 Block Diagram
FN9357 Rev.0.00
Sep 10, 2018
Page 3 of 34
ISL78424, ISL78434, ISL78444
1. Overview
ISL78434
10
VDD
HB
HO_H
HO_L
5V
Regulator
Gate
Drive
Switch
Control
HB
UVLO
5V
Level
Shift
1M
LI
HS
HS
HI
~6V
Delay
Delay
Adaptive
Dead Time
160k
VDD
UVLO
LO_H
LO_L
LI
Gate
Drive
~6V
~6V
160k
160k
100k
EN
VSS
AGND
Figure 4. ISL78434 Block Diagram
FN9357 Rev.0.00
Sep 10, 2018
Page 4 of 34
ISL78424, ISL78434, ISL78444
1. Overview
ISL78444
10
VDD
HB
HO
5V
Regulator
Gate
Drive
Switch
Control
HB
UVLO
5V
Level
Shift
1M
5V
PWM
HS
HS
Adaptive
Dead Time
Delay
Delay
160k
-
VDD
UVLO
PWM
+
~6V
160k
-
+
Gate
Drive
LO
100k
EN
0.6V
Ref
~6V
VSS
5V
160k
Prog Dead
Time
RDT
AGND
Figure 5. ISL78444 Block Diagram
FN9357 Rev.0.00
Sep 10, 2018
Page 5 of 34
ISL78424, ISL78434, ISL78444
1. Overview
1.2
Ordering Information
Part Number
(Notes 2, 3)
Part
Marking
Temp Range
(°C)
Tape and Reel
(Units) (Note 1)
Package
(RoHS Compliant)
Pkg.
Dwg. #
ISL78424AVEZ
ISL78424AVEZ-T
ISL78424AVEZ-T7A
ISL78434AVEZ
ISL78434AVEZ-T
ISL78434AVEZ-T7A
ISL78444AVEZ
ISL78444AVEZ-T
ISL78444AVEZ-T7A
Notes:
78424 AVEZ
78424 AVEZ
78424 AVEZ
78434 AVEZ
78434 AVEZ
78434 AVEZ
78444 AVEZ
78444 AVEZ
78444 AVEZ
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-
14 Ld HTSSOP
M14.173B
2.5k
250
-
14 Ld HTSSOP
14 Ld HTSSOP
14 Ld HTSSOP
14 Ld HTSSOP
14 Ld HTSSOP
14 Ld HTSSOP
14 Ld HTSSOP
14 Ld HTSSOP
M14.173B
M14.173B
M14.173B
M14.173B
M14.173B
M14.173B
M14.173B
M14.173B
2.5k
250
-
2.5k
250
1. Refer to TB347 for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), refer to the ISL78424, ISL78434, and ISL78444 product information pages. For more
information about MSL, refer to TB363.
4. These packages are in compliance with 100V conductor spacing guidelines per IPC-2221.
Table 1. Key Differences Between Family of Parts
Part Number
ISL78424
Input
PWM
HI/LI
Driver Output Pins
Adaptive Dead Time Control
HO_H: High-Side Source
Yes
Yes
HO_L: High-side Sink
LO_H: Low-Side Source
LO_L: Low-Side Sink
ISL78434
ISL78444
PWM
HO: High-Side Source and Sink
LO: Low-Side Source and Sink
Yes
1.3
Pin Configurations
ISL78424 (14 Ld HTSSOP)
Top View
ISL78434 (14 Ld HTSSOP)
Top View
14 VDD
14 VDD
ISL78434
ISL78424
HB
1
2
3
4
5
6
7
HB
1
2
13
13
LO_H
HO_H
LO_H
HO_H
HO_L
12 LO_L
12
11
10
9
LO_L
VSS
3
4
5
6
7
HO_L
HS
EPAD
VSS
LI
EPAD
11
10
9
HS
NC
NC
PWM
EN
NC
EN
NC
HI
8
RDT
AGND
8
AGND
FN9357 Rev.0.00
Sep 10, 2018
Page 6 of 34
ISL78424, ISL78434, ISL78444
1. Overview
ISL78444 (14 Ld HTSSOP)
Top View
14 VDD
ISL78444
NC
1
2
3
4
5
6
7
13
12
LO
NC
VSS
HB
HO
EPAD
11 PWM
EN
10
9
HS
RDT
AGND
NC
NC
8
1.4
Pin Descriptions
ISL78424 ISL78434 ISL78444 Symbol
Description
1
-
1
-
3
4
-
HB
HO
High-side bootstrap supply voltage referenced to HS. Connect boot cap from HB to HS.
High-side driver output. Connect to gate of high-side NFET.
2
2
HO_H High-side driver source output. Connect to gate of high-side NFET. This pin is also the
sense input for high-side adaptive dead time control.
3
4
7
-
3
4
7
8
-
-
HO_L High-side driver sink output. Connect to gate of high-side NFET.
5
8
-
HS
High-side driver reference. Connect to source of high-side NFET.
AGND Analog ground pin. Connect to VSS through EPAD.
HI
High-side gate driver logic input. 3V and 5V logic compatible.
8
9
RDT
Adjustable dead time delay pin. Connect a resistor to ground to increase the dead time
delay in addition to the adaptive dead time control. See “Adjustable Dead Time Delay
(RDT Pin)” on page 25 for more information.
9
9
10
EN
LI
Driver enable. When high, the driver outputs respond to input logic control. When low, the
low-side driver sink output is active and the high-side driver sink output has a 1MΩ
impedance to HS to keep the half bridge NFETs off.
-
10
-
-
Low-side gate driver logic input. 3V and 5V logic compatible.
10
11
11
12
PWM Tri-Level PWM input for controlling the driver outputs.
11
VSS
Low-side driver reference. Connect to AGND through EPAD. Connect to source of
low-side NFET.
-
-
13
-
LO
Low-side driver output. Connect to gate of low-side NFET.
12
13
12
13
LO_L Low-side driver sink output. Connect to gate of low-side NFET.
-
LO_H Low-side driver source output. Connect to gate of low-side NFET. This pin is also the
sense input for the low-side adaptive dead time control.
14
14
14
VDD
NC
Supply voltage for internal bias circuitry and low-side driver source output.
No connect. This pin is not internally connected.
5, 6
5, 6
1, 2, 6, 7
EPAD
Bottom side thermal pad is not electrically connected internally. Connect VSS and AGND
pins together with EPAD on PCB. Connect EPAD PCB to ground plane with as many vias
as possible for optimum thermal performance. See “PCB Layout Guidelines” on page 31
for more information.
FN9357 Rev.0.00
Sep 10, 2018
Page 7 of 34
ISL78424, ISL78434, ISL78444
2. Specifications
2. Specifications
2.1
Absolute Maximum Ratings
All voltages referenced to VSS unless otherwise specified.
Parameter
Minimum
-0.3
Maximum
Unit
V
Supply Voltage, VDD, HB-HS
PWM, HI, LI and EN Voltage
RDT Voltage
20
VDD + 0.3
5
-0.3
V
-0.3
V
Voltage on LO
-0.3
VDD + 0.3
VHB + 0.3
100
V
Voltage on HO (Referenced to HS)
Voltage on HB
VHS - 0.3
V
V
Voltage on HS
-1
86
V
Average Current in VDD to HB FET
ESD Rating
100
mA
Unit
kV
kV
mA
Value
2.5
Human Body Model (Tested per AEC-Q100-002)
Charged Device Model (Tested per AEC-Q100-011)
Latch-Up (Tested per AEC-A100-004)
1
100
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can
adversely impact product reliability and result in failures not covered by warranty.
2.2
Thermal Information
Thermal Resistance (Typical)
JA (°C/W)
JC (°C/W)
14 Ld HTSSOP Package (Notes 5, 6)
Notes:
35
2.5
5. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach”
features. See TB379.
6. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Parameter
Maximum Power Dissipation at +25°C in Free Air
Storage Temperature Range
Minimum
Maximum
3.5
Unit
W
-65
-55
+150
°C
Junction Temperature Range
+150
°C
Pb-Free Reflow Profile
Refer to TB493
2.3
Recommended Operating Conditions
Parameter
Minimum
Maximum
18
Unit
V
Supply Voltage, VDD
Voltage on HS
8
-0.7
70
V
Voltage on HS (Negative repetitive transient <100ns)
Voltage on HB (Referenced to HS)
Voltage on HB (Referenced to VSS)
HS Slew Rate
-10
V
8
18
V
86
V
<50
+140
V/ns
°C
Junction Temperature
-40
FN9357 Rev.0.00
Sep 10, 2018
Page 8 of 34
ISL78424, ISL78434, ISL78444
2. Specifications
2.4
Electrical Specifications
Unless otherwise specified: VDD = 12V, VSS = AGND = HS = 0V, HB = HS+VDD, EN = 5V, PWM = 2.5V, HI = LI = 0V, 10kΩ resistor on
RDT pin to AGND. No load on LO or HO. Typical parameters for TJ = +25°C. Boldface limits apply across the ambient operating
temperature range, -40°C to +140°C.
Min
Max
Parameters
Symbol
Test Conditions
(Note 7) Typ (Note 7) Unit
Supply Currents
VDD Quiescent Current
IDD1
IDD2
RDT = 0Ω to AGND
-
-
500
650
800
830
µA
µA
RDT = 10kΩ to AGND, ISL78424 and
ISL78444 only
V
DD Operating Current
IDDO1
PWM 0V to 5V
-
6.6
11.8
mA
HI and LI 0V to 5V
f
R
PWM = 500kHz, 50% duty cycle
DT = 0Ω to AGND; VHS = 5V
IDDO2
PWM 0V to 5V
-
6.8
11.9
mA
ISL78424 and ISL78444 only
f
R
PWM = 500kHz, 50% duty cycle
DT = 10kΩ to AGND; VHS = 5V
VDD Disabled Current
IDDSD
IHBQ
IHBO
EN = 0V
-
-
-
170
250
5.4
360
320
10
µA
µA
HB to HS Quiescent Current
HB to HS Operating Current
PWM = 12V; HI = 12V
fPWM = 500kHz, 50% duty cycle
PWM = 2.5V to 5V
mA
HI 0V to 5V; VHS = 5V
HB to VSS Leakage Current
HB to VSS Bias Current
IHBSLeak VHB = VHS = 70V
IHBSBias IHBSBias = IHB - IHS
VDD = 16V; VHB = 86V; VHS = 70V;
-
-
50
80
µA
µA
125
150
PWM = 5V; HI = 5V
Tri-Level PWM Input
High Level Rising Threshold
Middle Level Range
VPWMH
VMIDH
VMIDL
-
3.0
-
3.5
3.3
1.5
200
1.2
30
3.8
V
V
Middle level upper limit
Middle level lower limit
-
1.65
-
V
Middle Level Hysteresis
-
mV
V
Low Level Falling Threshold
Logic High and Low Input Current
VPWML
0.8
20
10
2.35
-
-
IPWM_IH VPWM = 5V; Sourcing
IPWM_IL VPWM = 0V; Sinking
45
35
2.55
-
µA
µA
V
24
Open Circuit Voltage
Vfloat
Rmid
No load on PWM pin
2.5
165
PWM Middle Level Resistors
Pull-up resistor to internal reference
and pull-down resistor to AGND
kΩ
HI/LI Input
High Level Threshold
Low Level Threshold
Input Hysteresis
VIH
VIL
-
1.0
-
1.7
1.3
2.1
V
V
-
-
400
175
mV
kΩ
HI/LI Pin Pull-Down Resistance
EN Input
RHI_LI
HI = LI = 5V
100
320
High Level Threshold
Low Level Threshold
EN Input Hysteresis
VENH
VENL
-
1.0
-
1.7
1.3
400
2.1
V
V
-
-
mV
FN9357 Rev.0.00
Sep 10, 2018
Page 9 of 34
ISL78424, ISL78434, ISL78444
2. Specifications
Unless otherwise specified: VDD = 12V, VSS = AGND = HS = 0V, HB = HS+VDD, EN = 5V, PWM = 2.5V, HI = LI = 0V, 10kΩ resistor on
RDT pin to AGND. No load on LO or HO. Typical parameters for TJ = +25°C. Boldface limits apply across the ambient operating
temperature range, -40°C to +140°C. (Continued)
Min
Max
Parameters
EN Pin Pull-Down Resistor
Symbol
Test Conditions
(Note 7) Typ (Note 7) Unit
REN
EN = 5V
100
175
3
260
kΩ
µs
Enable High Delay
tEN_H_LO From VENH to transition at LO;
PWM = 0V, ISL78424 and ISL78444;
LI = 5V, HI = 0V, for ISL78434
-
5.275
tEN_H_HO From VENH to transition at HO;
PWM = 5V, ISL78424 and ISL78444;
LI = 0V, HI = 5V, for ISL78434
-
-
-
-
3
µs
µs
µs
µs
Enable Low Delay
tEN_L_HO From VENL to transition at HO;
PWM = 5V, ISL78424 and ISL78444;
LI = 0V, HI = 5V, for ISL78434
0.8
0.8
20
tEN_L_LO From VENL to transition at LO;
PWM = 0V, ISL78424 and ISL78444;
LI = 5V, HI = 0V, for ISL78434
1.7
V
DD Start-Up Delay
tVDD
EN = VDD
ISL78424, ISL78444 PWM = 0V;
ISL78434 HI = 0V, LI = VDD
DD crossing VDDR to LO rising
;
-
;
V
Undervoltage Protection
DD Rising Threshold
V
VDDR
VDDH
VHBR
VHBH
6.8
7.2
0.7
7
7.7
-
V
V
V
V
VDD UVLO Hysteresis
HB Rising Threshold
HB UVLO Hysteresis
Bootstrap FET Switch
Low Current Forward Voltage
High Current Forward Voltage
VDD to HB Resistance
LO Gate Driver
-
6
-
7.8
-
0.5
VDL
VDH
IVDD-HB = 100µA
IVDD-HB = 100mA
-
-
1
0.3
3
-
mV
V
1
6
RBOOT
IBOOT out of HB pin = 100mA
1
Ω
Output Low Voltage
VLOL
VLOH
ILO = 100mA sink
-
-
100
170
225
325
mV
mV
Output High Voltage
ILO = 100mA source;
Voltage below VDD rail:
V
OHL = VDD - VLO
Peak Pull-Up Current
ILOH
VLO = 0V; T = +25°C
VLO = 0V; T = +85°C
VLO = 0V; T = +140°C
VLO = 12V; T = +25°C
VLO = 12V; T = +85°C
VLO = 12V; T = +140°C
-
-
-
-
-
-
4
3.75
3.5
4.5
4
-
-
-
-
-
-
A
A
A
A
A
A
Peak Pull-Down Current
ILOL
3.5
HO Gate Driver
Output Low Voltage
Output High Voltage
VHOH
VHOL
IHO = 100mA sink
-
-
100
170
225
325
mV
mV
IHO = 100mA source
Voltage below VHB rail:
V
OHH = VHB - VHO
FN9357 Rev.0.00
Sep 10, 2018
Page 10 of 34
ISL78424, ISL78434, ISL78444
2. Specifications
Unless otherwise specified: VDD = 12V, VSS = AGND = HS = 0V, HB = HS+VDD, EN = 5V, PWM = 2.5V, HI = LI = 0V, 10kΩ resistor on
RDT pin to AGND. No load on LO or HO. Typical parameters for TJ = +25°C. Boldface limits apply across the ambient operating
temperature range, -40°C to +140°C. (Continued)
Min
Max
Parameters
Peak Pull-Up Current
Symbol
Test Conditions
VLO = 0V; T = +25°C
(Note 7) Typ (Note 7) Unit
IHOH
-
-
-
-
-
-
3.75
3.5
3.25
4.5
4
-
-
-
-
-
-
A
A
A
A
A
A
VLO = 0V; T = +85°C
VLO = 0V; T = +140°C
VLO = 12V; T = +25°C
VLO = 12V; T = +85°C
VLO = 12V; T = +140°C
Peak Pull-Down Current
IHOL
3.5
Adaptive Dead Time Control Threshold Voltage
LO or LO_H Threshold Voltage Relative to VSS
VADTC_LO Falling edge on LO
VADTC_HO Falling edge on HO
-
-
1.3
1.0
-
-
V
V
HO or HO_H Threshold Voltage Relative to HS
(Gate Sense Threshold)
HS Threshold Voltage Relative to VSS
(Phase Sense Threshold)
VADTC_HS Falling edge on HS;
HO-HS > VADTC_HO
-
0.5
-
V
2.5
Switching Specifications
Unless otherwise specified: VDD = 12V, VSS = AGND = HS = 0V, HB = HS+VDD, PWM = 0V to 5V or HI/LI = 0V to 5V switching. No load on LO
or HO. Typical parameters for TJ = +25°C. Boldface limits apply across the operating temperature range, -40°C to +140°C.
Min
Max
Parameters
HO Turn-Off Propagation Delay
LO Turn-Off Propagation Delay
PWM Propagation Delay Matching
HO Turn-Off Propagation Delay
Symbol
tPDHO
Test Conditions
PWM falling to HO falling
(Note 7) Typ (Note 7) Unit
29
35
45
45
0
75
66
10
75
ns
ns
ns
ns
tPDLO
PWM rising to LO falling
tPDHO - tPDLO
-10
45
tPDHO1
tPDHO2
tPDLO1
tPDLO2
PWM entering mid-level state to HO falling
PWM = 5V to 2.5V
55
RDT = 0Ω to AGND
HO Turn-On Propagation Delay
LO Turn-Off Propagation Delay
LO Turn-On Propagation Delay
PWM exiting mid-level state to HO rising
PWM = 2.5V to 5V;
25
50
34
40
65
45
60
80
61
ns
ns
ns
RDT = 0Ω to AGND
PWM entering mid-level state to LO falling
PWM = 0V to 2.5V
RDT = 0Ω to AGND
PWM exiting mid-level state to LO rising
PWM = 2.5V to 0V
RDT = 0Ω to AGND
HO Turn-Off Propagation Delay
LO Turn-Off Propagation Delay
tPDHI1
tPDLI1
HI falling to HO falling
LI = 0V
27
34
45
45
60
56
ns
ns
LI Falling to LO Falling
HI = 0V
HI and LI Falling Propagation Delay Matching
HO Turn-On Propagation Delay
t
PDHI1 - tPDLI1
-10
18
0
10
47
ns
ns
tPDHI2
tPDLI2
HI rising to HO rising
LI = 0V
28
LO Turn-On Propagation Delay
LI rising to LO rising
HI = 0V
27
35
-7
51
-1
ns
ns
HI and LI Rising Propagation Delay Matching
tPDHI2 - tPDLI2
-15
FN9357 Rev.0.00
Sep 10, 2018
Page 11 of 34
ISL78424, ISL78434, ISL78444
2. Specifications
Unless otherwise specified: VDD = 12V, VSS = AGND = HS = 0V, HB = HS+VDD, PWM = 0V to 5V or HI/LI = 0V to 5V switching. No load on LO
or HO. Typical parameters for TJ = +25°C. Boldface limits apply across the operating temperature range, -40°C to +140°C. (Continued)
Min
Max
Parameters
Symbol
Test Conditions
LO falling to HO rising
(Note 7) Typ (Note 7) Unit
Minimum Dead Time Delay (Note 8)
Includes ISL78434
tDTLHmin
50
60
70
85
100
130
325
ns
ns
ns
(LO Sense) RDT = 0Ω to AGND
tDTHLmin HO falling to LO rising
(HO Sense) HS = 5V, RDT = 0Ω to AGND
tDTHSmin ISL78424 and ISL78434 only
150
210
(HS Sense) HS falling to LO rising
HO_H-HS > VADTC_HO
RDT = 0Ω to AGND
Low Range Resistor Delay (Note 8)
(ISL78424 and ISL78444 only)
tDTLH_10k LO falling to HO rising
(LO Sense) RDT = 10kΩ to AGND
89
110
125
142
150
ns
ns
tDTHL_10k HO falling to LO rising
(HO Sense) HS = 5V
108
RDT = 10kΩ to AGND
tDTHS_10k ISL78424 only
(HS Sense) HS falling to LO Rising
HO_H-HS > VADTC_HO
190
250
350
ns
RDT = 10kΩ to AGND
Mid Range Resistor Delay (Note 8)
(ISL78424 and ISL78444 only)
tDTLH_65k LO falling to HO rising
(LO Sense) RDT = 100kΩ to AGND
250
265
290
300
335
340
ns
ns
tDTHL_65k HO falling to LO rising
(HO Sense) HS = 5V
RDT = 100kΩ to AGND
tDTHS_65k ISL78424 only
(HS Sense) HS falling to LO rising
HO_H-HS > VADTC_HO
385
440
542
ns
RDT = 100kΩ to AGND
High Range Resistor Delay (Note 8)
(ISL78424 and ISL78444 only)
tDTLH_100k LO falling to HO rising
(LO Sense) RDT = 100kΩ to AGND
-
-
405
430
-
-
ns
ns
tDTHL_100k HO falling to LO rising
(HO Sense) HS = 5V
RDT = 100kΩ to AGND
tDTHS_100k ISL78424 only
(HS Sense) HS falling to LO rising
HO_H-HS > VADTC_HO
-
550
-
ns
RDT = 100kΩ to AGND
Dead Time Delay Matching (Note 8)
LO Gate Sense to HO Gate Sense Delay
Matching
tMATCHmin RDT = 0Ω to AGND
-38
-38
-15
-12
15
13
ns
ns
(tDTHLmin - tDTLHmin
)
tMATCH_10k RDT = 10kΩ to AGND
(tDTHL_10k - tDTLH_10k
)
ISL78424 and ISL78444 only
tMATCH_65k RDT = 65kΩ to AGND
(tDTHL_65k - tDTLH_65k
-38
-
-13
10
10
-
ns
ns
)
ISL78424 and ISL78444 only
Either Output Rise/Fall Time
(10% to 90%/90% to 10%)
t
RC,tFC
tmin
CL = 1nF
Minimum Input Pulse Width for Output to
Respond
ISL78424, ISL78444
ISL78434
-
-
50
50
-
-
ns
ns
Notes:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.
8. Dead Time is defined as the period of time between LO falling and HO rising or between HO falling and LO rising.
FN9357 Rev.0.00
Sep 10, 2018
Page 12 of 34
ISL78424, ISL78434, ISL78444
2. Specifications
2.6
Timing Diagrams
tPDLO
tPDHO
VPWMH
VPWML
PWM
LO
50%
1V
50%
50%
1V
50%
HO
EN
tADTC
+ tDTLH
tADTC
+ tDTHL
tPDHO2 + tDTLH
tPDHO1
tPDLO2 + tDTHL
tPDLO1
VPWMH
VMIDH
VPWML
VMIDL
PWM
LO
50%
50%
50%
50%
50%
50%
HO
EN
VENH
VENL
tENL
tENH
Figure 6. ISL78424, ISL78444
Notes:
9. Rise and Fall Times on PWM signal are shown exaggerated.
10. Timing Diagrams are with HS = VSS = 0V
11. For ISL78424, HO_H shorted to HO_L and represented as HO; LO_H shorted to LO_L and represented as LO
12. tADTC: Adaptive dead time control delay from LO or HO falling below VADTC
13. tDTLH and tDTHL is adjustable dead time delay. See “Adjustable Dead Time Delay (RDT Pin)” on page 25 for more information.
14. For RDT = 0V the adjustable dead time control is disabled and tDTLH = tDTHL = 0ns
15. tADTC + tDTLH: Dead time delay from LO falling to HO rising. Measured from 1V on LO to 50% of HO.
16. tADTC + tDTHL: Dead time delay from HO falling to LO rising. Measured from 1V on HO to 50% of LO.
17. tPDLO: Propagation delay from PWM rising to LO falling. Measured from PWM = 3.8V to 50% of LO.
18. tPDHO: Propagation delay from PWM falling to HO falling. Measured from PWM = 0.8V to 50% of HO.
19. tPDLO1: Propagation delay from PWM entering tri-level state to LO falling. Measured from PWM = 1.6V to 50% of LO.
20. tPDLO2: Propagation delay from PWM exiting tri-level state to LO rising. Measured from PWM = 0.8V to 50% of LO.
21. tPDHO1: Propagation delay from PWM entering tri-level state to HO falling. Measured from PWM = 3.0V to 50% of HO.
22. tPDHO2: Propagation delay from PWM exiting tri-level state to HO rising. Measured from PWM = 3.8V to 50% of HO.
23. tENL: Disable delay time from EN falling. Measured from VENL to 50% falling on LO with PWM = 0V.
24. tENH: Enable delay time from EN rising. Measured from VENH to 50% rising on LO with PWM = 0V.
FN9357 Rev.0.00
Sep 10, 2018
Page 13 of 34
ISL78424, ISL78434, ISL78444
2. Specifications
tPDLI1
tPDHI1
LI
VLI_IH
VLI_IL
VHI_IH
VHI_IL
HI
LO
50%
50%
1V, Typ
50%
50%
HO
1V, Typ
tDTLH
tDTHL
EN
tPDLI2
LI
VHI_IH
VHI_IL
VLI_IH
VLI_IL
HI
LO
50%
50%
50%
50%
tPDHI2
HO
EN
VENH
VENL
tENH
tENL
Figure 7. ISL78434
Notes:
25. Rise and fall times on HI and LI signal are shown exaggerated.
26. Timing diagrams are with HS = VSS = 0V
27. For ISL78434, HO_H shorted to HO_L and represented as HO; LO_H shorted to LO_L and represented as LO
28. tDTLH: Adaptive dead time delay from LO falling to HO rising. Measured from 1V on LO to 50% of HO.
29. tDTHL: Adaptive dead time delay from HO falling to LO rising. Measured from 1V on HO to 50% of LO.
30. tPDLI1: Propagation delay from LI falling to LO falling. Measured from LI = 1.0V to 50% of LO.
31. tPDHI1: Propagation delay from HI falling to HO falling. Measured from HI = 1.0V to 50% of HO.
32. tPDLI2: Propagation delay from LI rising to LO rising. Measured from LI = 2.1V to 50% of LO with HI = 0 for >1µs before LI rising.
33. tPDHI2: Propagation delay from HI rising to HO rising. Measured from HI = 2.1V to 50% of HO with LI = 0 for >1µs before HI rising.
34. tENL: Disable delay time from EN falling. Measured from VENL to 50% falling on LO with LI = 5V.
35. tENH: Enable delay time from EN rising. Measured from VENH to 50% rising on LO with LI = 5V.
FN9357 Rev.0.00
Sep 10, 2018
Page 14 of 34
ISL78424, ISL78434, ISL78444
3. Typical Performance Curves
3. Typical Performance Curves
Unless otherwise stated, typical performance curves are taken with conditions with respect to its corresponding
parameter in the Electrical Specifications table.
300
250
200
150
100
50
1.0
0.9
0.8
0.7
0.6
0.5
0.4
VDD = 12V
VDD = 8V
VDD = 18V
VDD = 12V
VDD = 8V
VDD = 18V
0
-50
0
50
100
150
-50
0
50
100
150
Temperature (°C)
Temperature (°C)
Figure 8. Quiescent Current vs Temperature
Figure 9. Shutdown Current vs Temperature
(ISL78424 and ISL78444)
300
250
200
150
100
50
140
VDD = 12V
VDD = 8V
VDD = 18V
120
100
80
60
40
20
0
VDD = 12V
VDD = 8V
VDD = 18V
0
-50
0
50
100
150
-50
0
50
100
150
Temperature (°C)
Temperature (°C)
Figure 10. Shutdown Current vs Temperature (ISL78434)
Figure 11. HB to VSS Bias Current vs Temperature
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
-50
0
50
100
150
-50
0
50
100
150
Temperature (°C)
Temperature (°C)
Figure 12. PWM High Rising Threshold Voltage vs
Temperature
Figure 13. PWM Low Falling Threshold Voltage vs
Temperature
FN9357 Rev.0.00
Sep 10, 2018
Page 15 of 34
ISL78424, ISL78434, ISL78444
3. Typical Performance Curves
5.0
4.5
4.0
3.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
HI Rising
HI Falling
3.0
PWM High Rising
PWM Low Falling
2.5
2.0
1.5
1.0
0.5
0.0
PWM Mid High Falling
PWM Mid Low Rising
-50
0
50
100
150
-50
0
50
100
150
150
150
Temperature (°C)
Temperature (°C)
Figure 14. PWM Threshold Voltage vs Temperature
Figure 15. HI Threshold Voltage vs Temperature
5.0
5.0
LI Rising
EN Rising
EN Falling
4.5
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
LI Falling
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-50
0
50
100
150
-50
0
50
100
Temperature (°C)
Temperature (°C)
Figure 16. LI Threshold Voltage vs Temperature
Figure 17. EN Threshold Voltage vs Temperature
8
10
VDD Rising
EN Rising
EN Falling
9
7
6
5
4
3
2
1
0
VDD Falling
8
7
6
5
4
3
2
1
0
-50
0
50
100
150
-50
0
50
100
Temperature (°C)
Temperature (°C)
Figure 18. EN Delay Time vs Temperature
Figure 19. UVLO Threshold Voltage vs Temperature
FN9357 Rev.0.00
Sep 10, 2018
Page 16 of 34
ISL78424, ISL78434, ISL78444
3. Typical Performance Curves
10
6
5
4
3
2
1
0
VHB Rising
VHB Falling
9
8
7
6
5
4
3
2
1
0
-50
0
50
Temperature (°C)
100
150
-50
0
50
100
150
Temperature (°C)
Figure 20. Boot UVLO Threshold Voltage vs Temperature
Figure 21. Boot Switch Resistance vs Temperature
8
8
Pull Up
Pull Down
Pull Up
7
7
Pull Down
6
5
4
3
2
1
0
6
5
4
3
2
1
0
-60 -40 -20
0
20
40
60
80 100 120 140 160
-60 -40 -20
0
20
40
60
80 100 120 140 160
Temperature (°C)
Temperature (°C)
Figure 22. Low-Side Peak Current vs Temperature
Figure 23. High-Side Peak Current vs Temperature
0.50
0.50
VLO High Voltage
VHO High Voltage
0.45
0.45
VLO Low Voltage
0.40
VHO Low Voltage
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-50
0
50
100
150
-50
0
50
100
150
Temperature (°C)
Temperature (°C)
Figure 25. LO Gate Driver Voltage vs Temperature
Figure 24. HO Gate Driver Voltage vs Temperature
FN9357 Rev.0.00
Sep 10, 2018
Page 17 of 34
ISL78424, ISL78434, ISL78444
3. Typical Performance Curves
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
PWM Mid to HO Falling
PWM Mid to HO Rising
PWM Mid to LO Falling
PWM Mid to LO Rising
-50
0
50
100
150
-50
0
50
Temperature (°C)
100
150
Temperature (°C)
Figure 26. PWM to HO Propagation Delay vs
Temperature
Figure 27. PWM to LO Propagation Delay vs
Temperature
60
50
40
30
20
10
0
60
50
40
30
20
10
0
LI Falling to LO Falling
LI Rising to LO Rising
HI Falling to HO Falling
HI Rising to HO Rising
-50
0
50
100
150
-50
0
50
100
150
Temperature (°C)
Temperature (°C)
Figure 28. HI Propagation Delay vs Temperature
Figure 29. LI Propagation Delay vs Temperature
500
500
450
400
350
300
250
450
400
350
300
250
200
150
100
50
RDT = 0kΩ
RDT = 50kΩ
RDT = 100kΩ
RDT = 10kΩ
RDT = 64.4kΩ
RDT = 0kΩ
RDT = 10kΩ
200
150
100
50
RDT = 50kΩ
RDT = 100kΩ
RDT = 64.4kΩ
0
0
-50
0
50
100
150
-50
0
50
100
150
Temperature (°C)
Temperature (°C)
Figure 30. Dead Time HO Falling to LO Rising vs
Temperature (ISL78424 and ISL78444 only)
Figure 31. Dead Time LO Falling to HO Rising vs
Temperature (ISL78424 and ISL78444 only)
FN9357 Rev.0.00
Sep 10, 2018
Page 18 of 34
ISL78424, ISL78434, ISL78444
3. Typical Performance Curves
500
500
450
400
350
300
250
200
150
100
50
Temp = -40˚C
Temp = 25˚C
Temp = 140˚C
Temp = -40˚C
Temp = 25˚C
Temp = 140˚C
450
400
350
300
250
200
150
100
50
0
0
0
20
40
60
80
100
0
20
40
60
80
100
Resistance (kΩ)
Resistance (kΩ)
Figure 32. Dead Time HO Falling to LO Rising vs RDT
Resistance (ISL78424 and ISL78444 only)
Figure 33. Dead Time LO Falling to HO Rising vs RDT
Resistance (ISL78424 and ISL78444 only)
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
0
2
4
6
8
10
0
2
4
6
8
10
Capacitance (nF)
Capacitance (nF)
Figure 34. VDD Current vs Capacitance on HO, LO
Figure 35. HB to HS Current vs Capacitance on HO, LO
PWM, 5V/Div
PWM, 5V/Div
BOOT, 5V/Div
BOOT, 5V/Div
HO, 5V/Div
HS, 5V/Div
HO, 5V/Div
HS, 5V/Div
HO-HS, 5V/Div
HO-HS, 5V/Div
LO, 5V/Div
LO, 5V/Div
20ns/Div
20ns/Div
Figure 36. Dead Time HO Falling to LO Rising
Figure 37. Dead Time LO Falling to HO Rising
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ISL78424, ISL78434, ISL78444
4. Product Description
4. Product Description
The ISL78424, ISL78434, and ISL78444 are Automotive Grade (AEC-Q100 Grade 1) high voltage, high frequency,
half-bridge N-MOSFET gate drivers for up to 70V half-bridge topologies. The family of half bridge drivers feature 3A
sourcing, 4A sinking peak gate drive current. The ISL78424 and ISL78444 feature a single tri-level PWM input for
controlling both gate drivers. The ISL78434 has dual independent inputs for controlling the high and low-side driver
separately. Strong gate drive strength and the adaptive dead time feature allow this family of drivers to switch high
voltage, low r power MOSFETs in half bridge topologies at high operating frequencies while providing
ON
shoot-through protection and minimizing dead time switching losses. For drivers with single PWM inputs (ISL78424
and ISL78444), when the input is logic high, the high-side driver is on and the low-side driver is off. When the input is
a logic low, the low-side driver is on and the high-side driver is off. When the input voltage is mid-level, both the high
and low-side drivers are low to keep the bridge off. The tri-level single PWM input allows the half-bridge to be phase
dropped in multi-phase applications. When the enable pin (EN) is low, it takes the bridge driver outputs to a low state
to turn off the FETs. When used with the Renesas Multiphase PWM Controllers (ISL78220, ISL78225, ISL78224, and
ISL78226) with driver enable output logic, the EN pin prevents false bridge operation during controller start up.
4.1
Single PWM or Independent HI/LI Inputs
The ISL78424 and ISL78444 feature a single tri-level PWM input pin to control both the high-side and low-side
driver outputs. When PWM is logic high on the ISL78424, the high-side source driver is active and the low-side
sink driver is active. When PWM is logic low on the ISL78424, the low-side source driver is active and the
high-side sink driver is active. The ISL78444 combines the sinking and sourcing drivers to make one gate drive
signal (LO or HO). The gate drive signal is high when the sourcing driver is active, and conversely, the gate drive is
low when the sinking driver is active. If the PWM pin is left floating, internal pull-up and pull down resistors bias
the PWM pin to the mid-level state. The mid-level state has both high-side and low-side sink drivers active.
Alternatively, the PWM pin can be actively driven to the mid-level state.
The single tri-level PWM input is ideal for multi-phase DC/DC converter applications that require phase dropping
in light-load conditions. With a single input controlling the high and low-side driver, this reduces the number of
controller signals needed by half and simplifies the PCB design, especially in six phase or greater DC/DC
converters. The mid-level state puts the half-bridge in high impedance state for phase dropping.
The ISL78434 features independent inputs HI and LI that drive the HO and LO outputs, respectively. The PWM
pin is replaced with HI and LI pins. Separate inputs are used in controllers that need to control the upper and lower
FET with independent signals.
4.2
ISL78424 and ISL78444 PWM Input
The ISL78424 and ISL78444 single PWM input controls both high and low-side driver with one control signal.
When the PWM input is switching between logic high and logic low, the high-side driver output is in phase with
the PWM input while the low-side driver is logic inverted from the PWM input. If the PWM is in mid-level (that is,
2.5V) both driver outputs are low. By design, the PWM input prevents a controller from turning both drivers on,
providing shoot-through protection against faulted input logic that can occur from a two input driver inadvertently
turning both drivers on.
5V
2.5V
PWM
0V
HB
HO
HS
VDD
LO
VSS
Figure 38. Single PWM Tri-Level Input Control
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Sep 10, 2018
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ISL78424, ISL78434, ISL78444
4. Product Description
4.3
ISL78434 HI/LI Lockout Protection
With independent HI and LI inputs being driven by two control signals, dead time is set with the controller by
ensuring one control signal is off prior to turning on the other one. There is a possibility the controller outputs are
damaged, faulted or from improper dead time programming, causing logic high to both inputs to the driver. The
ISL78434 features an input lockout protection to prevent both driver outputs going active high at the same time.
Internal logic in the IC senses the HI and LI inputs. The driver locks out any input logic from propagating to that
driver output if the other input is already logic high. For example, if HI = 1, LO output does not respond to LI input
logic high. If LI = 1, HO output does not respond to HI input logic high. The lockout function is disabled when the
first high input goes low, allowing the second input logic to propagate to the output. As a further protection against
shoot-through, adaptive dead time is enforced when recovering from the lockout function.
5V
HI
0V
Lockout
Enforced
HB
HO
HS
5V
LI
0V
VDD
VSS
LO
Figure 39. HI/LI Input with Lockout Protection
4.4
Separate Source and Sink Outputs
The ISL78424 and ISL78434 feature separate pins for the sourcing and sinking driver outputs. The HO_H and
HO_L are the high-side sourcing and sinking drivers, respectively. The LO_H and LO_L are the low-side sourcing
and sinking drivers, respectively. Separate source and sink output pins allow optimizing the FET turn on/off times
using gate drive limiting resistors.
The half bridge MOSFET drain-to-source switching dv/dt and di/dt can cause problems when the turn on or turn off
occurs too fast (transient overshoot, ringing, and EMI). Many half bridge circuit designs commonly place gate
drive limiting resistors in series with the driver output to limit the gate drive current and effectively slow down the
turn on and/or turn off of the MOSFET. The turn on and turn off times are typically independently optimized.
A cumbersome solution for single output drivers is to use a series diode + resistor in parallel of a second gate
resistor to provide isolation of the sourcing and sinking driver currents (see Figure 40 on page 22). With the diode
solution, the gate drive limiting impedance is the parallel resistance in the sinking path and the resistance without
the diode in the sourcing path. The drawback of the diode solution is the extra component cost and the parallel
resistance requires tuning of both resistors for slew rate control.
FN9357 Rev.0.00
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ISL78424, ISL78434, ISL78444
4. Product Description
V_BUS
D1
R_SINK
R_SOURCE
R_SOURCE
LO
VDD
HB
8
7
6
5
1
2
3
4
CBOOT
RBOOT
D2
R_SINK
VSS
HI
EPAD
HO
HS
LI
Figure 40. Gate Resistors in Standard Bridge Driver
A solution to eliminate the diode and simplify the gate resistance tuning is to provide independent high (sourcing)
and low (sinking) driver outputs. This gives flexibility of tuning the source and sink driver impedance to the
MOSFET gate without the need of a blocking diode. To separate each output into independent source and sink
paths, the half bridge requires an additional pin per driver output (see Figure 41).
V_BUS
R_SINK
R_SOURCE
CBOOT
VDD
HB
14
13
12
11
1
2
3
4
5
6
R_SOURCE
R_SINK
LO_H
LO_L
VSS
HO_H
HO_L
HS
EPAD
PWM
From
Controller
NC
NC
10
9
EN
AGND
RDT
7
8
Figure 41. Independent Source and Sink Driver Outputs
4.5
Peak Gate Drive Currents
The high-side and low-side drivers feature 3A peak sourcing and 4A peak sinking drive capability. Strong gate
drive allows fast switching times when low r , high voltage power MOSFETs are used. The switching time of
DS(ON)
the MOSFET translates to the total gate charge of the MOSFET divided by the peak current of the driver.
Example:
Q
= 50nC = 50nA•s
GS
I
I
= 3A
= 4A
SOURCING
SINKING
Q
50nA s
GS
--------------------------------
-----------------------
(EQ. 1)
(EQ. 2)
t
=
=
=
= 16.7ns
= 12.5ns
FET_ON
I
3A
SOURCING
Q
50nA s
GS
-------------------------
-----------------------
t
=
FET_OFF
I
4A
SINKING
FN9357 Rev.0.00
Sep 10, 2018
Page 22 of 34
ISL78424, ISL78434, ISL78444
4. Product Description
As we can see with the high sourcing and sinking currents of the ISL78424, ISL78434, and ISL78444, the
switching times of the MOSFETs are 16.7ns (turn on) and 12.5ns (turn off) for a MOSFET with about 5nF of gate
capacitance (V = 0V to 10V). Some bridge drivers offer gate drive capability as low as 500mA, resulting in
GS
switching times in the 100ns range for the MOSFET in the example above.
4.6
Shoot-Through Protection
The ISL78424, ISL78434, and ISL78444 feature shoot-through protection of the half bridge by preventing the
driver from turning on both FETs at the same time. These drivers integrate Adaptive Dead Time Control (ADTC)
that prevents a MOSFET in the bridge from being switched on until the complementary MOSFET has been
switched off. The ADTC function seeks to minimize dead time, the time when both MOSFETs are off, while
preventing the possibility that both MOSFETs are on at the same time, a condition that could result in
shoot-through. ADTC prevents shoot-through while minimizing the higher conduction losses that occur during
long dead times.
4.7
Shoot-Through and Dead Time
Shoot-through occurs when both FETs in the half bridge are on at the same time, creating a short-circuit path of the
bridge. In a buck regulator, the bus voltage would see a short-circuit to ground causing large current to flow
through both FETs. This leads to high power dissipation and can result in FET damage. Dead time is the time when
both FETs are off at the same time. Before a FET in the half bridge is turned on, the complementary FET is first
switched off, purposefully creating a period of dead time that prevents shoot-through. However, if care is not taken,
under some conditions one FET may not be completely off before the complementary FET is turned on. In such a
condition, there is no dead time and a transient shoot though condition occurs that results in a momentary
short-circuit of the bridge. This fault becomes very serious as the duration when both FETs are on simultaneously is
extended and can quickly result in damage of the power FETs due to high power dissipation. ISL78424, ISL78434,
and ISL78444 driver includes shoot-through protection to prevent such a condition.
4.8
Adaptive Dead Time Control (ADTC)
With proper design, shoot-through caused by faulted inputs turning both drivers on are avoided. Other
shoot-through conditions occur when there is no dead time on the driver outputs causing a momentary overlap
when both FETs are still on. This kind of shoot-through occurs when the gate to source voltage for the top and
bottom FET are above the gate threshold voltages, turning both FETs on. Even with proper input logic control,
anything that causes the turning off FET to overlap with the turning on FET without dead time causes a transient
shoot-through. To prevent against transient shoot-through faults, the ISL78424, ISL78434, and ISL78444 family of
drivers implement Adaptive Dead Time Control circuit that prevents a driver output from turning ON until a
satisfactory condition is sensed at the turning OFF driver. To turn on a FET, the associated driver output does not go
high until the driver output of the turning off FET crosses a falling threshold. This ensures that one FET is
completely off before the other FET is turned on with a minimum dead time, minimizing switching losses, and
increasing converter efficiency.
PWM
HO
VADTC_HO
tADT_LO
tADT_HO
LO
VADTC_LO
Figure 42. Adaptive Dead Time Control
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ISL78424, ISL78434, ISL78444
4. Product Description
4.9
Adaptive Dead Time and Gate Resistors
To prevent shoot-through, adaptive dead time control senses the voltage at the driver output pins for crossing a
falling threshold, at which point the driver considers the FET to be off, before turning the other driver on. With
single driver outputs HO and LO, the accuracy of the sense circuit is disrupted when gate resistors are used in series
with the driver outputs to slow down the FET turn on/off time because the resistor isolates the driver output from
the FET gate. The resistor and FET gate capacitance form an RC low pass filter of the driver output to the FET
gate. With the gate voltage lagging behind the driver output voltage, the adaptive dead time control could sense a
falling threshold at the driver output but the slower falling gate voltage could still be higher than the gate threshold,
resulting in no dead time and causing a momentary shoot-through condition of the bridge.
V_BUS
PWM
RG1
HO
LO
VADTC_LO
Ceq
LO
Low-Side
FET VGS
RG2
CO
RL
Vgsth
LO
+
Vgs
-
Ceq
HO
tADT_LO
Figure 43. Adaptive Dead Time Problem with Gate Resistors
The ISL78424 and ISL78434 drivers include a means of using independent source/sink driver outputs to overcome
the error that gate resistors typically introduce to adaptive dead time implementations. The driver output sourcing
pins (LO_H and HO_H) are used as a Kelvin sense when not actively sourcing. When the sinking pins (LO_L or
HO_L) are active during FET turn off, even with gate resistors between driver output and FET gate, the gate
voltage (and not the driver output) is sensed by the LO_H or HO_H pin. Adaptive Dead Time Control combined
with the gate sensing from separate driver output source and sink pins eliminates the error of inaccurate adaptive
dead time sensing when combined with gate resistors.
PWM
LO_L
LO_H
(Sensing Pin)
VADTC_LO
HO_H
tADT_LO
Figure 44. Adaptive Dead Time with Gate Sensing
Adaptive dead time control minimizes dead time needed to prevent bridge shoot-through. During dead time, the
body diode of the synchronous FET conducts, generating conduction losses that exceed those that would occur if
the MOSFET itself was conducting. Because conduction losses are higher during dead time than they otherwise
would be if the MOSFET were conducting, conversion efficiency is improved as dead time is decreased, so long as
FN9357 Rev.0.00
Sep 10, 2018
Page 24 of 34
ISL78424, ISL78434, ISL78444
4. Product Description
shoot-through does not occur. The lowest adaptive dead time achieved is limited by the propagation delay of the
sense circuitry inside the driver. If more dead time is required, the adjustable dead time delay function (ISL78424
and ISL78444 only) further increases the minimum dead time set by the Adaptive dead time control by adjusting
the resistor value on RDT pin.
V_BUS
REQ
RSENSE
CEQ
14 VDD
NC
1
2
3
4
5
6
RSINK
LO_H
13
NC
HB
CBOOT
LO_L
12
HO_H
HO_L
RSENSE
CEQ
11 VSS
EPAD
PWM
EN
10
9
HS
NC
7
8
RDT
Figure 45. Adaptive Dead Time with Independent Source/Sink for Gate Sensing
4.10 Falling Thresholds for ADTC
The three thresholds for the falling edge detection for Adaptive Dead Time Control - two for the high-side and one
for the low-side are summarized in Table 2. For ISL78424 and ISL78434, the detection is sensed at the driver
source pins LO_H (low side) and HO_H (high side). For ISL78444 where the source and sink driver outputs are on
one pin, the detection is done at LO and HO directly, losing the gate sense capability. Additionally, there is a falling
edge HS phase sense detector on the high-side driver that turns on the LO output when the high-side gate sense is
not detected. This occurs when a large gate resistor slows down the turn off of the high-side FET such that gate
voltage is below the Miller voltage but still above the ADTC detection threshold. Here the changing of the HS
phase node voltage detects that the high-side FET has turned off.
Table 2. Adaptive Dead Time Falling Edge Thresholds (Note)
Sense Pin
LO_H
Name
Low-Side Gate Sense
Threshold Voltage (Typical)
1.0V from LO_H to VSS
HO_H
HS
High-Side Gate Sense
High-Side Phase Sense
1.3V from HO_H to HS
0.5V from HS to VSS
Note: This information only applies to the ISL78424 and ISL78434. The ISL78444 uses LO and HO as sense pins.
4.11 Adjustable Dead Time Delay (RDT Pin)
The minimum dead time due to propagation delays of the adaptive dead time control circuit on this family of bridge
drivers can be increased with the adjustable dead time delay feature (ISL78424 and ISL78444). Connect a resistor
from the RDT pin to AGND to further increase the dead time set by the ADTC circuit. The adaptive dead time
range due to the additional programmed dead time is 30ns to 240ns, from the allowable R resistance values of
DT
10kΩ to 100kΩ. This function is useful if the minimum dead time from the adaptive dead time control requires
extra margin in the system to prevent shoot-through from occurring.
If adjustable dead time delay is not needed, connect the RDT pin to ground.
A 0.6V reference voltage combined with the resistor on the RDT pin generates a current for an internal oscillator;
the current being proportional to the additional dead time delay. The relationship of resistor value on the RDT pin
to dead time is shown in Figure 46 on page 26.
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ISL78424, ISL78434, ISL78444
4. Product Description
400
350
300
250
200
150
100
50
0
0
20
40
60
80
100
120
Resistance (kΩ)
Figure 46. Dead Time HO Falling to LO Rising vs RDT Resistance
(ISL78424; VDD = VHB - VHS = 12V; VHS = 0V)
4.12 Integrated Bootstrap Switch
The ISL78424, ISL78434, and ISL78444 family integrates a bootstrap switch internal to the IC. No external boot
diode is necessary for the high-side driver bootstrap operation. The advantage of a boot switch compared to a boot
diode is that a switch has less voltage drop across it. With a switch the bootstrap voltage at HB can be charged to
~VDD while a boot diode has ~0.7V drop at HB. With the boot switch implementation, the low-side and high-side
driver outputs can turn on FETs at the V voltage across gate to source. The boot switch r is 3Ω typical which
DD
ON
provides the proper impedance to refresh the boot capacitor in applications up to 500kHz when the proper boot
capacitor is selected.
Upon initial enabling of driver, the boot switch is turned on when PWM is logic low for the ISL78424 and
ISL78444 (LI is logic high and HI is logic low for the ISL78434) and the HS pin is below 2V. After a subsequent
turning on of the high-side driver, PWM is logic high for the ISL78424 and ISL78444 (LI is logic low and HI is
logic high for the ISL78434), whenever PWM (HI for the ISL78434) is not logic high and the HS pin is below 2V
the boot switch is turned on. When the boot switch FET is not turned on, there is a parallel path of the FET body
diode with a 10Ω series impedance (see Figure 47).
Figure 47. Bootstrap Switch
4.13 Bootstrap Capacitor
To provide the proper gate drive to the high-side FET, the high-side driver bias on this family of drivers is handled
with a bootstrap capacitor across the HB and HS pins. The boot bias is recharged whenever the HS pin voltage goes
below 2V and the high-side source driver is not commanded by PWM or HI. The internal boot switch from VDD to
HB turns on and the bootstrap capacitor is charged by VDD. To maintain operation of the high-side gate drive and
at the same time be adequately charged during initial boot up and refreshed in operation requires choosing an
appropriate capacitor value. In general, for most applications a 0.1µF to 0.33µF bootstrap capacitor is a good
starting point. For more information on choosing the right bootstrap capacitor, see “Bootstrap Capacitor Design” on
page 28.
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ISL78424, ISL78434, ISL78444
4. Product Description
4.14 EN Pin
The EN pin when placed in logic 0 state places the driver into a low power shutdown state. In shutdown, the driver
outputs do not respond to PWM inputs (for ISL78424 and ISL78444) and HI/LI inputs (for ISL78434). The
low-side driver sink output is active and the high-side driver sink output has a 1MΩ impedance to HS to keep the
bridge FETs off. The EN pin is used with Renesas analog DC/DC controllers (that is, ISL78220, ISL78225, and
ISL78226) to provide a state of non-operation before soft-start of the converter. The Renesas controllers have a
driver enable pin that asserts high when soft-start begins to ensure the half bridge is not switching before the
controller is properly biased.
The EN pin has an internal 160kΩ pull-down resistor that disables the driver when the pin is left floating.
4.15 UVLO Protection - VDD and Boot
The driver implements UVLO on both the VDD and HB-HS bootstrap supply. When the voltage on VDD and HB
(referenced to HS) is below the UVLO threshold, UVLO protection is active. For the VDD UVLO, both driver
sourcing outputs are disabled and the low-side sinking output is active. For boot UVLO, only the high-side driver
sourcing output is disable and there is a 1MΩ impedance on the HO pin relative to HS. The low-side driver
continues to respond to driver inputs in Boot UVLO.
When coming out of VDD UVLO, the high-side sourcing driver does not respond to input commands until the
low-side sourcing driver is active first. This ensures a boot refresh cycle occurs first to charge the bootstrap
capacitor to provide proper bias for the high-side driver.
FN9357 Rev.0.00
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ISL78424, ISL78434, ISL78444
5. Applications Information
5. Applications Information
5.1
Supply Voltage Operating Range
The recommended operating voltage range on VDD is 8V to 18V. Renesas recommends placing a 0.1µF high
frequency decoupling capacitor close to the VDD and VSS pin of the IC. A decoupling capacitor of at least 10
times the value of the boot capacitor is recommended to be placed in parallel with the 0.1µF at VDD and VSS.
5.2
Bootstrap Capacitor Design
ISL78424, ISL78434, and ISL78444 family has an integrated bootstrap switch that charges the external bootstrap
capacitor required on the HB to HS pins. To ensure that proper value of the bootstrap capacitance is selected, the
minimum V of the FET which is being driven needs to take into account, along with the voltage drop across the
GS
bootstrap switch, typically 0.4V.
(EQ. 3)
V
= V
– V
– V
DH GS_MIN
BOOT
DD
• ΔV
= Maximum allowable voltage dip to ensure proper function
BOOT
• V = V
charging supply
BOOT
DD
• V = High current forward voltage
DH
• V
= Minimum V voltage of FET required to keep FET on
GS
GS_MIN
The minimum C
capacitance required to ensure proper functionality becomes dependent on the total charge
BOOT
required during the on state of the high side when the C
voltage of the boot.
is not charging, along with the allowable change in
BOOT
Q
TOTAL
-----------------------
C
=
(EQ. 4)
BOOT
V
BOOT
where:
(EQ. 5)
Q
= Q
+ I
+ I
+ I
t
TOTAL
G_MAX
GS_LKG
HBQ
HBSLEAK
ON
• Q
= Maximum gate charge, from FET datasheet
G_MAX
• I
• I
• I
= Maximum FET gate-body leakage current, from FET datasheet
GS_LKG
= Boot quiescent current
HBQ
= Boot leakage current
HBSLEAK
5.3
Gate Drive Limiting Resistors
Gate limiting resistors are generally used for two purposes. One is to slow down the NMOS FET turn on and turn
off by limiting drive current to the gate. The ISL78424 and ISL78434 has separate sourcing and sinking pins on the
driver outputs which allow independent control of the gate drive limiting.
A second reason for adding gate drive limiting resistors is to control the transient ringing voltage on the MOSFET
gate-source pins. This occurs when there is excessive trace inductance in the layout of the driver output to the
MOSFET gate, combined with a low impedance high current driver output producing very fast edges with large
transient voltages at the FET gate. Gate drive limiting resistors reduce the peak voltage to safe levels to the gate.
FN9357 Rev.0.00
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ISL78424, ISL78434, ISL78444
5. Applications Information
5.4
Adaptive Dead Time Control
The ISL78424 and ISL78434 use gate sensing adaptive dead time control for turning on a NMOS FET gate with a
minimum dead time after a valid detection of turning off the other NMOS FET gate in a half bridge configuration.
The gate sense pins accurately monitor the FET gate-to-source voltage for crossing the internal detection thresholds
on the driver.
A low-side gate sense (1.3V typical) and two detectors on the high side (gate sense (1.0V typical to HS) and phase
sense (0.5V to VSS typical)), determine when the FET gate voltage is sufficiently low enough to turn a FET off
before allowing the other gate driver to turn on. Some bridge drivers with adaptive dead time control only offer a
high-side phase sense. The high-side gate sense is necessary for boost converter applications because the HS phase
node is clamped to the synchronous FET body diode voltage above VOUT and only falls when the low-side FET is
turned on.
In Buck Converter applications, the turn off of the high-side control FET causes the HS phase node to fall until
clamped by a body diode voltage below GND of the low-side FET. The falling edge HS dv/dt is proportional to the
peak inductor current at high-side FET turn off. A fast dv/dt on HS couples current into the high-side gate sense
detection circuitry that triggers the HO_H gate sense circuitry, even though the high-side gate sense (HO_H-HS) is
still above the gate sense threshold. In this situation, the Adaptive Dead Time is determined by the falling edge of
HS to LO rising. The high-side gate sense detection circuitry is only active on falling edges of HO from PWM or
HI going low, therefore ringing on rising edges of phase/HS does not cause false detection of the gate sense.
5.5
Adjustable Dead Time Control
When the minimum dead times from the adaptive dead time control is insufficient, the ISL78424 and ISL78444
provides adjustable dead time control on the RDT pin. A resistor on the RDT pin to AGND adds an additional
delay in addition to the adaptive dead time delay.
The recommended range of resistor values is 10kΩ to 100kΩ which provides an additional 40ns to 340ns dead time
delay in addition to the ADTC. Place the resistor as close as possible to the RDT and AGND pins. If additional
delay is not needed, short the RDT pin to AGND.
5.6
Power Dissipation Calculation
The ISL78424, ISL78434, and ISL78444 family power dissipation loss is comprised of the DC loss (P
)
LOSS_DC
and the losses due to switching (P
).
LOSS_SW
+ P
Q
(EQ. 6)
P
= P
LOSS_DC
LOSS_TOTAL
The DC power loss is proportional to the input voltage (V ) of the driver and the quiescent current, 500µA
DD
typical.
P
= V
I
DD Q
(EQ. 7)
LOSS_DC
The switching power loss accounts for the larger portion of the power loss and is directly proportional to the
frequency (f ) at which the drivers (HO and LO) are turning on/off their respective transistors, the gate charge of
SW
the transistor being driven (Q
FETs.
), and the input voltage of the drivers (V ) which is the drive voltage for the
G_MAX
DD
Separate source and sink output pins allow for optimized FET turn on/off times using different value resistors.
These gate resistors also help to allow calculation of the energy required to charge the gate (C ) of the FETs,
GATE
and the energy dissipated in this gate resistor is equal to the energy stored in the capacitor. The energy dissipation
of the resistor does not depend on the gate resistance, but solely on the gate charge of the transistor.
FN9357 Rev.0.00
Sep 10, 2018
Page 29 of 34
ISL78424, ISL78434, ISL78444
5. Applications Information
Q
G_MAX
-----------------------
C
E
=
(EQ. 8)
(EQ. 9)
GATE
V
DD
1
1
2
2
--
--
=
V
=
Q
V
G_MAX DD
CGATE
DD
2
As the transistor is being switched on/off, the power loss is doubled as the user is charging up the gate to V with
DD
a finite amount of energy, ECGATE, and then it is discharging that finite amount of energy when the gate is brought
back to GND.
2
(EQ. 10)
P
= 2 E
f
= C
V
f
= Q
V
f
DD SW
LOSS_SW
CGATE
SW
GATE
DD
SW
G_MAX
where:
• Q
= Maximum gate charge, from FET datasheet
G_MAX
• E
= Energy required to charge the drive transistor gate voltage to V ; energy stored in capacitor
DD
CGATE
• V = Driver input voltage
DD
• f = Switching frequency operation of driver
SW
FN9357 Rev.0.00
Sep 10, 2018
Page 30 of 34
ISL78424, ISL78434, ISL78444
6. PCB Layout Guidelines
6. PCB Layout Guidelines
For best thermal performance, connect the driver EPAD to a low thermal impedance ground plane. Use as many vias as
possible to connect the top layer PCB thermal land to ground planes on other PCB layers. For best electrical
performance, connect the VSS and AGND pins together through the EPAD to maintain a low impedance connection
between the two pins.
When adjustable dead time is used (ISL78424 and ISL78444 only), connect the resistor to the RDT pin and GND plane
close to the IC to minimize ground noise from disrupting the timing performance.
Place the VDD decoupling capacitors and bootstrap capacitors close to the VDD-VSS and HB-HS pins, respectively.
Use decoupling capacitors to reduce the influence of parasitic inductors. To be effective, these capacitors must also
have the shortest possible lead lengths. If vias are used, connect several paralleled vias to reduce the inductance of the
vias.
(1) Keep power loops as short as possible by paralleling the source and return traces.
(2) Adding resistance might be necessary to dampen resonating parasitic circuits. In PCB designs with long leads on
the LO and HO outputs, add series gate resistors on the bridge FETs to dampen the oscillations.
(3) Large power components (power FETs, electrolytic capacitors, power resistors, etc.) have internal parasitic
inductance, which cannot be eliminated. This must be accounted for in the PCB layout and circuit design.
(4) If you simulate your circuits, consider including parasitic components.
14 VDD
1
2
3
4
5
6
HB
HO_H
HO_L
HS
ISL78424
13 LO_H
CVDD
CBOOT
12
11
10
9
LO_L
VSS
PWM
EN
EPAD
NC
NC
7
8
RDT
AGND
GND
RDT
Figure 48. Component Placement
FN9357 Rev.0.00
Sep 10, 2018
Page 31 of 34
ISL78424, ISL78434, ISL78444
7. Revision History
7. Revision History
Rev.
Date
Description
0.00 Sep 10, 2018 Initial release
FN9357 Rev.0.00
Sep 10, 2018
Page 32 of 34
ISL78424, ISL78434, ISL78444
8. Package Outline Drawing
For the most recent package outline drawing, see M14.173B.
8. Package Outline Drawing
M14.173B
14 LEAD HEATSINK THIN SHRINK SMALL OUTLINE PACKAGE (HTSSOP)
Rev 1, 1/10
A
1
3
3.10 ±0.10
5.00 ±0.10
8
14
SEE
DETAIL "X"
6.40
PIN #1
I.D. MARK
3.00 ±0.10
4.40 ±0.10
2
3
0.20 C B A
1
7
B
EXPOSED THERMAL PAD
0.65
0.15 +0.05/-0.06
BOTTOM VIEW
END VIEW
TOP VIEW
1.00 REF
H
0.05
C
0.90 +0.15/-0.10
1.20 MAX
5
SEATING
PLANE
GAUGE
PLANE
0.25
0.25 +0.05/-0.06
0.10 CBA
0.10 C
0°-8°
0.60 ±0.15
0.05 MIN
0.15 MAX
SIDE VIEW
(3.10)
DETAIL "X"
(1.45)
(3.00)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
(5.65)
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion.
Allowable protrusion shall be 0.80mm total in excess of dimension at
maximum material condition.
Minimum space between protrusion and adjacent lead is 0.07mm.
6. Dimension in ( ) are for reference only.
(0.65 TYP)
(0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
7. Conforms to JEDEC MO-153, variation ABT-1.
FN9357 Rev.0.00
Sep 10, 2018
Page 33 of 34
Notice
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